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3731a334 AO |
1 | /* |
2 | * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller | |
3 | * | |
4 | * Copyright (C) 2012 Alan Ott <alan@signal11.us> | |
5 | * Signal 11 Software | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
3731a334 AO |
16 | */ |
17 | ||
18 | #include <linux/spi/spi.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/module.h> | |
b0156792 | 21 | #include <linux/regmap.h> |
4ca24aca | 22 | #include <linux/ieee802154.h> |
afaf7fde | 23 | #include <linux/irq.h> |
5ad60d36 | 24 | #include <net/cfg802154.h> |
3731a334 AO |
25 | #include <net/mac802154.h> |
26 | ||
27 | /* MRF24J40 Short Address Registers */ | |
c9f883f6 | 28 | #define REG_RXMCR 0x00 /* Receive MAC control */ |
7d840545 AA |
29 | #define BIT_PROMI BIT(0) |
30 | #define BIT_ERRPKT BIT(1) | |
31 | #define BIT_NOACKRSP BIT(5) | |
32 | #define BIT_PANCOORD BIT(3) | |
33 | ||
c9f883f6 AA |
34 | #define REG_PANIDL 0x01 /* PAN ID (low) */ |
35 | #define REG_PANIDH 0x02 /* PAN ID (high) */ | |
36 | #define REG_SADRL 0x03 /* Short address (low) */ | |
37 | #define REG_SADRH 0x04 /* Short address (high) */ | |
38 | #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */ | |
554b4949 AA |
39 | #define REG_EADR1 0x06 |
40 | #define REG_EADR2 0x07 | |
41 | #define REG_EADR3 0x08 | |
42 | #define REG_EADR4 0x09 | |
43 | #define REG_EADR5 0x0A | |
44 | #define REG_EADR6 0x0B | |
45 | #define REG_EADR7 0x0C | |
46 | #define REG_RXFLUSH 0x0D | |
47 | #define REG_ORDER 0x10 | |
c9f883f6 | 48 | #define REG_TXMCR 0x11 /* Transmit MAC control */ |
7d840545 AA |
49 | #define TXMCR_MIN_BE_SHIFT 3 |
50 | #define TXMCR_MIN_BE_MASK 0x18 | |
51 | #define TXMCR_CSMA_RETRIES_SHIFT 0 | |
52 | #define TXMCR_CSMA_RETRIES_MASK 0x07 | |
53 | ||
554b4949 AA |
54 | #define REG_ACKTMOUT 0x12 |
55 | #define REG_ESLOTG1 0x13 | |
56 | #define REG_SYMTICKL 0x14 | |
57 | #define REG_SYMTICKH 0x15 | |
c9f883f6 AA |
58 | #define REG_PACON0 0x16 /* Power Amplifier Control */ |
59 | #define REG_PACON1 0x17 /* Power Amplifier Control */ | |
60 | #define REG_PACON2 0x18 /* Power Amplifier Control */ | |
554b4949 | 61 | #define REG_TXBCON0 0x1A |
c9f883f6 | 62 | #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */ |
7d840545 | 63 | #define BIT_TXNTRIG BIT(0) |
87820441 | 64 | #define BIT_TXNSECEN BIT(1) |
7d840545 AA |
65 | #define BIT_TXNACKREQ BIT(2) |
66 | ||
554b4949 AA |
67 | #define REG_TXG1CON 0x1C |
68 | #define REG_TXG2CON 0x1D | |
69 | #define REG_ESLOTG23 0x1E | |
70 | #define REG_ESLOTG45 0x1F | |
71 | #define REG_ESLOTG67 0x20 | |
72 | #define REG_TXPEND 0x21 | |
73 | #define REG_WAKECON 0x22 | |
74 | #define REG_FROMOFFSET 0x23 | |
c9f883f6 | 75 | #define REG_TXSTAT 0x24 /* TX MAC Status Register */ |
554b4949 AA |
76 | #define REG_TXBCON1 0x25 |
77 | #define REG_GATECLK 0x26 | |
78 | #define REG_TXTIME 0x27 | |
79 | #define REG_HSYMTMRL 0x28 | |
80 | #define REG_HSYMTMRH 0x29 | |
c9f883f6 | 81 | #define REG_SOFTRST 0x2A /* Soft Reset */ |
554b4949 AA |
82 | #define REG_SECCON0 0x2C |
83 | #define REG_SECCON1 0x2D | |
c9f883f6 | 84 | #define REG_TXSTBL 0x2E /* TX Stabilization */ |
554b4949 | 85 | #define REG_RXSR 0x30 |
c9f883f6 | 86 | #define REG_INTSTAT 0x31 /* Interrupt Status */ |
7d840545 AA |
87 | #define BIT_TXNIF BIT(0) |
88 | #define BIT_RXIF BIT(3) | |
5a62f3c6 AM |
89 | #define BIT_SECIF BIT(4) |
90 | #define BIT_SECIGNORE BIT(7) | |
7d840545 | 91 | |
c9f883f6 | 92 | #define REG_INTCON 0x32 /* Interrupt Control */ |
7d840545 AA |
93 | #define BIT_TXNIE BIT(0) |
94 | #define BIT_RXIE BIT(3) | |
5a62f3c6 | 95 | #define BIT_SECIE BIT(4) |
7d840545 | 96 | |
c9f883f6 AA |
97 | #define REG_GPIO 0x33 /* GPIO */ |
98 | #define REG_TRISGPIO 0x34 /* GPIO direction */ | |
554b4949 | 99 | #define REG_SLPACK 0x35 |
c9f883f6 | 100 | #define REG_RFCTL 0x36 /* RF Control Mode Register */ |
7d840545 AA |
101 | #define BIT_RFRST BIT(2) |
102 | ||
554b4949 AA |
103 | #define REG_SECCR2 0x37 |
104 | #define REG_BBREG0 0x38 | |
c9f883f6 | 105 | #define REG_BBREG1 0x39 /* Baseband Registers */ |
7d840545 AA |
106 | #define BIT_RXDECINV BIT(2) |
107 | ||
c9f883f6 | 108 | #define REG_BBREG2 0x3A /* */ |
7d840545 AA |
109 | #define BBREG2_CCA_MODE_SHIFT 6 |
110 | #define BBREG2_CCA_MODE_MASK 0xc0 | |
111 | ||
554b4949 AA |
112 | #define REG_BBREG3 0x3B |
113 | #define REG_BBREG4 0x3C | |
c9f883f6 AA |
114 | #define REG_BBREG6 0x3E /* */ |
115 | #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */ | |
3731a334 AO |
116 | |
117 | /* MRF24J40 Long Address Registers */ | |
c9f883f6 | 118 | #define REG_RFCON0 0x200 /* RF Control Registers */ |
7d840545 AA |
119 | #define RFCON0_CH_SHIFT 4 |
120 | #define RFCON0_CH_MASK 0xf0 | |
121 | #define RFOPT_RECOMMEND 3 | |
122 | ||
c9f883f6 AA |
123 | #define REG_RFCON1 0x201 |
124 | #define REG_RFCON2 0x202 | |
125 | #define REG_RFCON3 0x203 | |
7d840545 AA |
126 | |
127 | #define TXPWRL_MASK 0xc0 | |
128 | #define TXPWRL_SHIFT 6 | |
129 | #define TXPWRL_30 0x3 | |
130 | #define TXPWRL_20 0x2 | |
131 | #define TXPWRL_10 0x1 | |
132 | #define TXPWRL_0 0x0 | |
133 | ||
134 | #define TXPWRS_MASK 0x38 | |
135 | #define TXPWRS_SHIFT 3 | |
136 | #define TXPWRS_6_3 0x7 | |
137 | #define TXPWRS_4_9 0x6 | |
138 | #define TXPWRS_3_7 0x5 | |
139 | #define TXPWRS_2_8 0x4 | |
140 | #define TXPWRS_1_9 0x3 | |
141 | #define TXPWRS_1_2 0x2 | |
142 | #define TXPWRS_0_5 0x1 | |
143 | #define TXPWRS_0 0x0 | |
144 | ||
c9f883f6 AA |
145 | #define REG_RFCON5 0x205 |
146 | #define REG_RFCON6 0x206 | |
147 | #define REG_RFCON7 0x207 | |
148 | #define REG_RFCON8 0x208 | |
554b4949 AA |
149 | #define REG_SLPCAL0 0x209 |
150 | #define REG_SLPCAL1 0x20A | |
151 | #define REG_SLPCAL2 0x20B | |
152 | #define REG_RFSTATE 0x20F | |
c9f883f6 AA |
153 | #define REG_RSSI 0x210 |
154 | #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */ | |
7d840545 AA |
155 | #define BIT_INTEDGE BIT(1) |
156 | ||
c9f883f6 AA |
157 | #define REG_SLPCON1 0x220 |
158 | #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */ | |
159 | #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */ | |
554b4949 AA |
160 | #define REG_REMCNTL 0x224 |
161 | #define REG_REMCNTH 0x225 | |
162 | #define REG_MAINCNT0 0x226 | |
163 | #define REG_MAINCNT1 0x227 | |
164 | #define REG_MAINCNT2 0x228 | |
165 | #define REG_MAINCNT3 0x229 | |
c9f883f6 | 166 | #define REG_TESTMODE 0x22F /* Test mode */ |
554b4949 AA |
167 | #define REG_ASSOEAR0 0x230 |
168 | #define REG_ASSOEAR1 0x231 | |
169 | #define REG_ASSOEAR2 0x232 | |
170 | #define REG_ASSOEAR3 0x233 | |
171 | #define REG_ASSOEAR4 0x234 | |
172 | #define REG_ASSOEAR5 0x235 | |
173 | #define REG_ASSOEAR6 0x236 | |
174 | #define REG_ASSOEAR7 0x237 | |
175 | #define REG_ASSOSAR0 0x238 | |
176 | #define REG_ASSOSAR1 0x239 | |
177 | #define REG_UNONCE0 0x240 | |
178 | #define REG_UNONCE1 0x241 | |
179 | #define REG_UNONCE2 0x242 | |
180 | #define REG_UNONCE3 0x243 | |
181 | #define REG_UNONCE4 0x244 | |
182 | #define REG_UNONCE5 0x245 | |
183 | #define REG_UNONCE6 0x246 | |
184 | #define REG_UNONCE7 0x247 | |
185 | #define REG_UNONCE8 0x248 | |
186 | #define REG_UNONCE9 0x249 | |
187 | #define REG_UNONCE10 0x24A | |
188 | #define REG_UNONCE11 0x24B | |
189 | #define REG_UNONCE12 0x24C | |
c9f883f6 | 190 | #define REG_RX_FIFO 0x300 /* Receive FIFO */ |
3731a334 AO |
191 | |
192 | /* Device configuration: Only channels 11-26 on page 0 are supported. */ | |
193 | #define MRF24J40_CHAN_MIN 11 | |
194 | #define MRF24J40_CHAN_MAX 26 | |
195 | #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \ | |
196 | - ((u32)1 << MRF24J40_CHAN_MIN)) | |
197 | ||
198 | #define TX_FIFO_SIZE 128 /* From datasheet */ | |
199 | #define RX_FIFO_SIZE 144 /* From datasheet */ | |
200 | #define SET_CHANNEL_DELAY_US 192 /* From datasheet */ | |
201 | ||
db9e0ee8 SV |
202 | enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC }; |
203 | ||
3731a334 AO |
204 | /* Device Private Data */ |
205 | struct mrf24j40 { | |
206 | struct spi_device *spi; | |
5a504397 | 207 | struct ieee802154_hw *hw; |
3731a334 | 208 | |
b0156792 AA |
209 | struct regmap *regmap_short; |
210 | struct regmap *regmap_long; | |
6844a0e4 AA |
211 | |
212 | /* for writing txfifo */ | |
213 | struct spi_message tx_msg; | |
214 | u8 tx_hdr_buf[2]; | |
215 | struct spi_transfer tx_hdr_trx; | |
216 | u8 tx_len_buf[2]; | |
217 | struct spi_transfer tx_len_trx; | |
218 | struct spi_transfer tx_buf_trx; | |
219 | struct sk_buff *tx_skb; | |
220 | ||
221 | /* post transmit message to send frame out */ | |
222 | struct spi_message tx_post_msg; | |
223 | u8 tx_post_buf[2]; | |
224 | struct spi_transfer tx_post_trx; | |
225 | ||
c91a3011 AA |
226 | /* for protect/unprotect/read length rxfifo */ |
227 | struct spi_message rx_msg; | |
228 | u8 rx_buf[3]; | |
229 | struct spi_transfer rx_trx; | |
230 | ||
231 | /* receive handling */ | |
232 | struct spi_message rx_buf_msg; | |
233 | u8 rx_addr_buf[2]; | |
234 | struct spi_transfer rx_addr_trx; | |
235 | u8 rx_lqi_buf[2]; | |
236 | struct spi_transfer rx_lqi_trx; | |
237 | u8 rx_fifo_buf[RX_FIFO_SIZE]; | |
238 | struct spi_transfer rx_fifo_buf_trx; | |
239 | ||
37441611 AA |
240 | /* isr handling for reading intstat */ |
241 | struct spi_message irq_msg; | |
242 | u8 irq_buf[2]; | |
243 | struct spi_transfer irq_trx; | |
3731a334 AO |
244 | }; |
245 | ||
b0156792 AA |
246 | /* regmap information for short address register access */ |
247 | #define MRF24J40_SHORT_WRITE 0x01 | |
248 | #define MRF24J40_SHORT_READ 0x00 | |
249 | #define MRF24J40_SHORT_NUMREGS 0x3F | |
250 | ||
251 | /* regmap information for long address register access */ | |
252 | #define MRF24J40_LONG_ACCESS 0x80 | |
253 | #define MRF24J40_LONG_NUMREGS 0x38F | |
254 | ||
3731a334 AO |
255 | /* Read/Write SPI Commands for Short and Long Address registers. */ |
256 | #define MRF24J40_READSHORT(reg) ((reg) << 1) | |
257 | #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1) | |
258 | #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5) | |
259 | #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4) | |
260 | ||
cf82dabd AO |
261 | /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */ |
262 | #define MAX_SPI_SPEED_HZ 10000000 | |
3731a334 AO |
263 | |
264 | #define printdev(X) (&X->spi->dev) | |
265 | ||
b0156792 AA |
266 | static bool |
267 | mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg) | |
268 | { | |
269 | switch (reg) { | |
270 | case REG_RXMCR: | |
271 | case REG_PANIDL: | |
272 | case REG_PANIDH: | |
273 | case REG_SADRL: | |
274 | case REG_SADRH: | |
275 | case REG_EADR0: | |
276 | case REG_EADR1: | |
277 | case REG_EADR2: | |
278 | case REG_EADR3: | |
279 | case REG_EADR4: | |
280 | case REG_EADR5: | |
281 | case REG_EADR6: | |
282 | case REG_EADR7: | |
283 | case REG_RXFLUSH: | |
284 | case REG_ORDER: | |
285 | case REG_TXMCR: | |
286 | case REG_ACKTMOUT: | |
287 | case REG_ESLOTG1: | |
288 | case REG_SYMTICKL: | |
289 | case REG_SYMTICKH: | |
290 | case REG_PACON0: | |
291 | case REG_PACON1: | |
292 | case REG_PACON2: | |
293 | case REG_TXBCON0: | |
294 | case REG_TXNCON: | |
295 | case REG_TXG1CON: | |
296 | case REG_TXG2CON: | |
297 | case REG_ESLOTG23: | |
298 | case REG_ESLOTG45: | |
299 | case REG_ESLOTG67: | |
300 | case REG_TXPEND: | |
301 | case REG_WAKECON: | |
302 | case REG_FROMOFFSET: | |
303 | case REG_TXBCON1: | |
304 | case REG_GATECLK: | |
305 | case REG_TXTIME: | |
306 | case REG_HSYMTMRL: | |
307 | case REG_HSYMTMRH: | |
308 | case REG_SOFTRST: | |
309 | case REG_SECCON0: | |
310 | case REG_SECCON1: | |
311 | case REG_TXSTBL: | |
312 | case REG_RXSR: | |
313 | case REG_INTCON: | |
314 | case REG_TRISGPIO: | |
315 | case REG_GPIO: | |
316 | case REG_RFCTL: | |
6367551f | 317 | case REG_SECCR2: |
b0156792 AA |
318 | case REG_SLPACK: |
319 | case REG_BBREG0: | |
320 | case REG_BBREG1: | |
321 | case REG_BBREG2: | |
322 | case REG_BBREG3: | |
323 | case REG_BBREG4: | |
324 | case REG_BBREG6: | |
325 | case REG_CCAEDTH: | |
326 | return true; | |
327 | default: | |
328 | return false; | |
329 | } | |
330 | } | |
331 | ||
332 | static bool | |
333 | mrf24j40_short_reg_readable(struct device *dev, unsigned int reg) | |
334 | { | |
335 | bool rc; | |
336 | ||
337 | /* all writeable are also readable */ | |
338 | rc = mrf24j40_short_reg_writeable(dev, reg); | |
339 | if (rc) | |
340 | return rc; | |
341 | ||
342 | /* readonly regs */ | |
343 | switch (reg) { | |
344 | case REG_TXSTAT: | |
345 | case REG_INTSTAT: | |
346 | return true; | |
347 | default: | |
348 | return false; | |
349 | } | |
350 | } | |
351 | ||
352 | static bool | |
353 | mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg) | |
354 | { | |
355 | /* can be changed during runtime */ | |
356 | switch (reg) { | |
357 | case REG_TXSTAT: | |
358 | case REG_INTSTAT: | |
359 | case REG_RXFLUSH: | |
360 | case REG_TXNCON: | |
361 | case REG_SOFTRST: | |
362 | case REG_RFCTL: | |
363 | case REG_TXBCON0: | |
364 | case REG_TXG1CON: | |
365 | case REG_TXG2CON: | |
366 | case REG_TXBCON1: | |
367 | case REG_SECCON0: | |
368 | case REG_RXSR: | |
369 | case REG_SLPACK: | |
370 | case REG_SECCR2: | |
371 | case REG_BBREG6: | |
372 | /* use them in spi_async and regmap so it's volatile */ | |
373 | case REG_BBREG1: | |
374 | return true; | |
375 | default: | |
376 | return false; | |
377 | } | |
378 | } | |
379 | ||
380 | static bool | |
381 | mrf24j40_short_reg_precious(struct device *dev, unsigned int reg) | |
382 | { | |
383 | /* don't clear irq line on read */ | |
384 | switch (reg) { | |
385 | case REG_INTSTAT: | |
386 | return true; | |
387 | default: | |
388 | return false; | |
389 | } | |
390 | } | |
391 | ||
392 | static const struct regmap_config mrf24j40_short_regmap = { | |
393 | .name = "mrf24j40_short", | |
394 | .reg_bits = 7, | |
395 | .val_bits = 8, | |
396 | .pad_bits = 1, | |
397 | .write_flag_mask = MRF24J40_SHORT_WRITE, | |
398 | .read_flag_mask = MRF24J40_SHORT_READ, | |
399 | .cache_type = REGCACHE_RBTREE, | |
400 | .max_register = MRF24J40_SHORT_NUMREGS, | |
401 | .writeable_reg = mrf24j40_short_reg_writeable, | |
402 | .readable_reg = mrf24j40_short_reg_readable, | |
403 | .volatile_reg = mrf24j40_short_reg_volatile, | |
404 | .precious_reg = mrf24j40_short_reg_precious, | |
405 | }; | |
406 | ||
407 | static bool | |
408 | mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg) | |
409 | { | |
410 | switch (reg) { | |
411 | case REG_RFCON0: | |
412 | case REG_RFCON1: | |
413 | case REG_RFCON2: | |
414 | case REG_RFCON3: | |
415 | case REG_RFCON5: | |
416 | case REG_RFCON6: | |
417 | case REG_RFCON7: | |
418 | case REG_RFCON8: | |
419 | case REG_SLPCAL2: | |
420 | case REG_SLPCON0: | |
421 | case REG_SLPCON1: | |
422 | case REG_WAKETIMEL: | |
423 | case REG_WAKETIMEH: | |
424 | case REG_REMCNTL: | |
425 | case REG_REMCNTH: | |
426 | case REG_MAINCNT0: | |
427 | case REG_MAINCNT1: | |
428 | case REG_MAINCNT2: | |
429 | case REG_MAINCNT3: | |
430 | case REG_TESTMODE: | |
431 | case REG_ASSOEAR0: | |
432 | case REG_ASSOEAR1: | |
433 | case REG_ASSOEAR2: | |
434 | case REG_ASSOEAR3: | |
435 | case REG_ASSOEAR4: | |
436 | case REG_ASSOEAR5: | |
437 | case REG_ASSOEAR6: | |
438 | case REG_ASSOEAR7: | |
439 | case REG_ASSOSAR0: | |
440 | case REG_ASSOSAR1: | |
441 | case REG_UNONCE0: | |
442 | case REG_UNONCE1: | |
443 | case REG_UNONCE2: | |
444 | case REG_UNONCE3: | |
445 | case REG_UNONCE4: | |
446 | case REG_UNONCE5: | |
447 | case REG_UNONCE6: | |
448 | case REG_UNONCE7: | |
449 | case REG_UNONCE8: | |
450 | case REG_UNONCE9: | |
451 | case REG_UNONCE10: | |
452 | case REG_UNONCE11: | |
453 | case REG_UNONCE12: | |
454 | return true; | |
455 | default: | |
456 | return false; | |
457 | } | |
458 | } | |
459 | ||
460 | static bool | |
461 | mrf24j40_long_reg_readable(struct device *dev, unsigned int reg) | |
462 | { | |
463 | bool rc; | |
464 | ||
465 | /* all writeable are also readable */ | |
466 | rc = mrf24j40_long_reg_writeable(dev, reg); | |
467 | if (rc) | |
468 | return rc; | |
469 | ||
470 | /* readonly regs */ | |
471 | switch (reg) { | |
472 | case REG_SLPCAL0: | |
473 | case REG_SLPCAL1: | |
474 | case REG_RFSTATE: | |
475 | case REG_RSSI: | |
476 | return true; | |
477 | default: | |
478 | return false; | |
479 | } | |
480 | } | |
481 | ||
482 | static bool | |
483 | mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg) | |
484 | { | |
485 | /* can be changed during runtime */ | |
486 | switch (reg) { | |
487 | case REG_SLPCAL0: | |
488 | case REG_SLPCAL1: | |
489 | case REG_SLPCAL2: | |
490 | case REG_RFSTATE: | |
491 | case REG_RSSI: | |
492 | case REG_MAINCNT3: | |
493 | return true; | |
494 | default: | |
495 | return false; | |
496 | } | |
497 | } | |
498 | ||
499 | static const struct regmap_config mrf24j40_long_regmap = { | |
500 | .name = "mrf24j40_long", | |
501 | .reg_bits = 11, | |
502 | .val_bits = 8, | |
503 | .pad_bits = 5, | |
504 | .write_flag_mask = MRF24J40_LONG_ACCESS, | |
505 | .read_flag_mask = MRF24J40_LONG_ACCESS, | |
506 | .cache_type = REGCACHE_RBTREE, | |
507 | .max_register = MRF24J40_LONG_NUMREGS, | |
508 | .writeable_reg = mrf24j40_long_reg_writeable, | |
509 | .readable_reg = mrf24j40_long_reg_readable, | |
510 | .volatile_reg = mrf24j40_long_reg_volatile, | |
511 | }; | |
512 | ||
513 | static int mrf24j40_long_regmap_write(void *context, const void *data, | |
514 | size_t count) | |
515 | { | |
516 | struct spi_device *spi = context; | |
517 | u8 buf[3]; | |
518 | ||
519 | if (count > 3) | |
520 | return -EINVAL; | |
521 | ||
522 | /* regmap supports read/write mask only in frist byte | |
523 | * long write access need to set the 12th bit, so we | |
524 | * make special handling for write. | |
525 | */ | |
526 | memcpy(buf, data, count); | |
527 | buf[1] |= (1 << 4); | |
528 | ||
529 | return spi_write(spi, buf, count); | |
530 | } | |
531 | ||
532 | static int | |
533 | mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size, | |
534 | void *val, size_t val_size) | |
535 | { | |
536 | struct spi_device *spi = context; | |
537 | ||
538 | return spi_write_then_read(spi, reg, reg_size, val, val_size); | |
539 | } | |
540 | ||
541 | static const struct regmap_bus mrf24j40_long_regmap_bus = { | |
542 | .write = mrf24j40_long_regmap_write, | |
543 | .read = mrf24j40_long_regmap_read, | |
544 | .reg_format_endian_default = REGMAP_ENDIAN_BIG, | |
545 | .val_format_endian_default = REGMAP_ENDIAN_BIG, | |
546 | }; | |
547 | ||
6844a0e4 AA |
548 | static void write_tx_buf_complete(void *context) |
549 | { | |
550 | struct mrf24j40 *devrec = context; | |
551 | __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb); | |
7d840545 | 552 | u8 val = BIT_TXNTRIG; |
6844a0e4 AA |
553 | int ret; |
554 | ||
87820441 AM |
555 | if (ieee802154_is_secen(fc)) |
556 | val |= BIT_TXNSECEN; | |
557 | ||
6844a0e4 | 558 | if (ieee802154_is_ackreq(fc)) |
7d840545 | 559 | val |= BIT_TXNACKREQ; |
6844a0e4 AA |
560 | |
561 | devrec->tx_post_msg.complete = NULL; | |
562 | devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON); | |
563 | devrec->tx_post_buf[1] = val; | |
564 | ||
565 | ret = spi_async(devrec->spi, &devrec->tx_post_msg); | |
566 | if (ret) | |
567 | dev_err(printdev(devrec), "SPI write Failed for transmit buf\n"); | |
568 | } | |
569 | ||
3731a334 AO |
570 | /* This function relies on an undocumented write method. Once a write command |
571 | and address is set, as many bytes of data as desired can be clocked into | |
572 | the device. The datasheet only shows setting one byte at a time. */ | |
573 | static int write_tx_buf(struct mrf24j40 *devrec, u16 reg, | |
574 | const u8 *data, size_t length) | |
575 | { | |
3731a334 | 576 | u16 cmd; |
6844a0e4 | 577 | int ret; |
3731a334 AO |
578 | |
579 | /* Range check the length. 2 bytes are used for the length fields.*/ | |
580 | if (length > TX_FIFO_SIZE-2) { | |
581 | dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n"); | |
582 | length = TX_FIFO_SIZE-2; | |
583 | } | |
584 | ||
3731a334 | 585 | cmd = MRF24J40_WRITELONG(reg); |
6844a0e4 AA |
586 | devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff; |
587 | devrec->tx_hdr_buf[1] = cmd & 0xff; | |
588 | devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */ | |
589 | devrec->tx_len_buf[1] = length; /* Total length */ | |
590 | devrec->tx_buf_trx.tx_buf = data; | |
591 | devrec->tx_buf_trx.len = length; | |
592 | ||
593 | ret = spi_async(devrec->spi, &devrec->tx_msg); | |
3731a334 AO |
594 | if (ret) |
595 | dev_err(printdev(devrec), "SPI write Failed for TX buf\n"); | |
596 | ||
3731a334 AO |
597 | return ret; |
598 | } | |
599 | ||
6844a0e4 AA |
600 | static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb) |
601 | { | |
602 | struct mrf24j40 *devrec = hw->priv; | |
603 | ||
604 | dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len); | |
605 | devrec->tx_skb = skb; | |
606 | ||
607 | return write_tx_buf(devrec, 0x000, skb->data, skb->len); | |
608 | } | |
609 | ||
5a504397 | 610 | static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level) |
3731a334 AO |
611 | { |
612 | /* TODO: */ | |
ca079ad6 | 613 | pr_warn("mrf24j40: ed not implemented\n"); |
3731a334 AO |
614 | *level = 0; |
615 | return 0; | |
616 | } | |
617 | ||
5a504397 | 618 | static int mrf24j40_start(struct ieee802154_hw *hw) |
3731a334 | 619 | { |
5a504397 | 620 | struct mrf24j40 *devrec = hw->priv; |
3731a334 AO |
621 | |
622 | dev_dbg(printdev(devrec), "start\n"); | |
623 | ||
42c7148e AA |
624 | /* Clear TXNIE and RXIE. Enable interrupts */ |
625 | return regmap_update_bits(devrec->regmap_short, REG_INTCON, | |
5a62f3c6 | 626 | BIT_TXNIE | BIT_RXIE | BIT_SECIE, 0); |
3731a334 AO |
627 | } |
628 | ||
5a504397 | 629 | static void mrf24j40_stop(struct ieee802154_hw *hw) |
3731a334 | 630 | { |
5a504397 | 631 | struct mrf24j40 *devrec = hw->priv; |
529160dc | 632 | |
3731a334 AO |
633 | dev_dbg(printdev(devrec), "stop\n"); |
634 | ||
42c7148e | 635 | /* Set TXNIE and RXIE. Disable Interrupts */ |
7d840545 AA |
636 | regmap_update_bits(devrec->regmap_short, REG_INTCON, |
637 | BIT_TXNIE | BIT_TXNIE, BIT_TXNIE | BIT_TXNIE); | |
3731a334 AO |
638 | } |
639 | ||
e37d2ec8 | 640 | static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel) |
3731a334 | 641 | { |
5a504397 | 642 | struct mrf24j40 *devrec = hw->priv; |
3731a334 AO |
643 | u8 val; |
644 | int ret; | |
645 | ||
646 | dev_dbg(printdev(devrec), "Set Channel %d\n", channel); | |
647 | ||
648 | WARN_ON(page != 0); | |
649 | WARN_ON(channel < MRF24J40_CHAN_MIN); | |
650 | WARN_ON(channel > MRF24J40_CHAN_MAX); | |
651 | ||
652 | /* Set Channel TODO */ | |
7d840545 AA |
653 | val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND; |
654 | ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0, | |
655 | RFCON0_CH_MASK, val); | |
42c7148e AA |
656 | if (ret) |
657 | return ret; | |
3731a334 AO |
658 | |
659 | /* RF Reset */ | |
7d840545 AA |
660 | ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, |
661 | BIT_RFRST); | |
3731a334 AO |
662 | if (ret) |
663 | return ret; | |
3731a334 | 664 | |
7d840545 | 665 | ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0); |
42c7148e AA |
666 | if (!ret) |
667 | udelay(SET_CHANNEL_DELAY_US); /* per datasheet */ | |
3731a334 | 668 | |
42c7148e | 669 | return ret; |
3731a334 AO |
670 | } |
671 | ||
5a504397 | 672 | static int mrf24j40_filter(struct ieee802154_hw *hw, |
3731a334 AO |
673 | struct ieee802154_hw_addr_filt *filt, |
674 | unsigned long changed) | |
675 | { | |
5a504397 | 676 | struct mrf24j40 *devrec = hw->priv; |
3731a334 AO |
677 | |
678 | dev_dbg(printdev(devrec), "filter\n"); | |
679 | ||
57205c14 | 680 | if (changed & IEEE802154_AFILT_SADDR_CHANGED) { |
3731a334 AO |
681 | /* Short Addr */ |
682 | u8 addrh, addrl; | |
529160dc | 683 | |
b70ab2e8 PB |
684 | addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff; |
685 | addrl = le16_to_cpu(filt->short_addr) & 0xff; | |
3731a334 | 686 | |
42c7148e AA |
687 | regmap_write(devrec->regmap_short, REG_SADRH, addrh); |
688 | regmap_write(devrec->regmap_short, REG_SADRL, addrl); | |
3731a334 AO |
689 | dev_dbg(printdev(devrec), |
690 | "Set short addr to %04hx\n", filt->short_addr); | |
691 | } | |
692 | ||
57205c14 | 693 | if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) { |
3731a334 | 694 | /* Device Address */ |
b70ab2e8 PB |
695 | u8 i, addr[8]; |
696 | ||
697 | memcpy(addr, &filt->ieee_addr, 8); | |
3731a334 | 698 | for (i = 0; i < 8; i++) |
42c7148e AA |
699 | regmap_write(devrec->regmap_short, REG_EADR0 + i, |
700 | addr[i]); | |
3731a334 AO |
701 | |
702 | #ifdef DEBUG | |
ca079ad6 | 703 | pr_debug("Set long addr to: "); |
3731a334 | 704 | for (i = 0; i < 8; i++) |
ca079ad6 VB |
705 | pr_debug("%02hhx ", addr[7 - i]); |
706 | pr_debug("\n"); | |
3731a334 AO |
707 | #endif |
708 | } | |
709 | ||
57205c14 | 710 | if (changed & IEEE802154_AFILT_PANID_CHANGED) { |
3731a334 AO |
711 | /* PAN ID */ |
712 | u8 panidl, panidh; | |
529160dc | 713 | |
b70ab2e8 PB |
714 | panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff; |
715 | panidl = le16_to_cpu(filt->pan_id) & 0xff; | |
42c7148e AA |
716 | regmap_write(devrec->regmap_short, REG_PANIDH, panidh); |
717 | regmap_write(devrec->regmap_short, REG_PANIDL, panidl); | |
3731a334 AO |
718 | |
719 | dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id); | |
720 | } | |
721 | ||
57205c14 | 722 | if (changed & IEEE802154_AFILT_PANC_CHANGED) { |
3731a334 AO |
723 | /* Pan Coordinator */ |
724 | u8 val; | |
725 | int ret; | |
726 | ||
3731a334 | 727 | if (filt->pan_coord) |
7d840545 | 728 | val = BIT_PANCOORD; |
3731a334 | 729 | else |
7d840545 AA |
730 | val = 0; |
731 | ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, | |
732 | BIT_PANCOORD, val); | |
42c7148e AA |
733 | if (ret) |
734 | return ret; | |
3731a334 AO |
735 | |
736 | /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA). | |
737 | * REG_ORDER is maintained as default (no beacon/superframe). | |
738 | */ | |
739 | ||
740 | dev_dbg(printdev(devrec), "Set Pan Coord to %s\n", | |
ce261bc3 | 741 | filt->pan_coord ? "on" : "off"); |
3731a334 AO |
742 | } |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
c91a3011 | 747 | static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec) |
3731a334 | 748 | { |
c91a3011 | 749 | int ret; |
3731a334 | 750 | |
c91a3011 AA |
751 | /* Turn back on reception of packets off the air. */ |
752 | devrec->rx_msg.complete = NULL; | |
753 | devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1); | |
754 | devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */ | |
755 | ret = spi_async(devrec->spi, &devrec->rx_msg); | |
3731a334 | 756 | if (ret) |
c91a3011 AA |
757 | dev_err(printdev(devrec), "failed to unlock rx buffer\n"); |
758 | } | |
3731a334 | 759 | |
c91a3011 AA |
760 | static void mrf24j40_handle_rx_read_buf_complete(void *context) |
761 | { | |
762 | struct mrf24j40 *devrec = context; | |
763 | u8 len = devrec->rx_buf[2]; | |
764 | u8 rx_local_buf[RX_FIFO_SIZE]; | |
765 | struct sk_buff *skb; | |
766 | ||
767 | memcpy(rx_local_buf, devrec->rx_fifo_buf, len); | |
768 | mrf24j40_handle_rx_read_buf_unlock(devrec); | |
769 | ||
770 | skb = dev_alloc_skb(IEEE802154_MTU); | |
3731a334 | 771 | if (!skb) { |
c91a3011 AA |
772 | dev_err(printdev(devrec), "failed to allocate skb\n"); |
773 | return; | |
3731a334 AO |
774 | } |
775 | ||
c91a3011 AA |
776 | memcpy(skb_put(skb, len), rx_local_buf, len); |
777 | ieee802154_rx_irqsafe(devrec->hw, skb, 0); | |
778 | ||
779 | #ifdef DEBUG | |
780 | print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1, | |
781 | rx_local_buf, len, 0); | |
782 | pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n", | |
783 | devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]); | |
784 | #endif | |
785 | } | |
786 | ||
787 | static void mrf24j40_handle_rx_read_buf(void *context) | |
788 | { | |
789 | struct mrf24j40 *devrec = context; | |
790 | u16 cmd; | |
791 | int ret; | |
792 | ||
793 | /* if length is invalid read the full MTU */ | |
794 | if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2])) | |
795 | devrec->rx_buf[2] = IEEE802154_MTU; | |
796 | ||
797 | cmd = MRF24J40_READLONG(REG_RX_FIFO + 1); | |
798 | devrec->rx_addr_buf[0] = cmd >> 8 & 0xff; | |
799 | devrec->rx_addr_buf[1] = cmd & 0xff; | |
800 | devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2]; | |
801 | ret = spi_async(devrec->spi, &devrec->rx_buf_msg); | |
802 | if (ret) { | |
803 | dev_err(printdev(devrec), "failed to read rx buffer\n"); | |
804 | mrf24j40_handle_rx_read_buf_unlock(devrec); | |
3731a334 | 805 | } |
c91a3011 | 806 | } |
3731a334 | 807 | |
c91a3011 AA |
808 | static void mrf24j40_handle_rx_read_len(void *context) |
809 | { | |
810 | struct mrf24j40 *devrec = context; | |
811 | u16 cmd; | |
812 | int ret; | |
3731a334 | 813 | |
c91a3011 AA |
814 | /* read the length of received frame */ |
815 | devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf; | |
816 | devrec->rx_trx.len = 3; | |
817 | cmd = MRF24J40_READLONG(REG_RX_FIFO); | |
818 | devrec->rx_buf[0] = cmd >> 8 & 0xff; | |
819 | devrec->rx_buf[1] = cmd & 0xff; | |
3731a334 | 820 | |
c91a3011 AA |
821 | ret = spi_async(devrec->spi, &devrec->rx_msg); |
822 | if (ret) { | |
823 | dev_err(printdev(devrec), "failed to read rx buffer length\n"); | |
824 | mrf24j40_handle_rx_read_buf_unlock(devrec); | |
825 | } | |
826 | } | |
3731a334 | 827 | |
c91a3011 AA |
828 | static int mrf24j40_handle_rx(struct mrf24j40 *devrec) |
829 | { | |
830 | /* Turn off reception of packets off the air. This prevents the | |
831 | * device from overwriting the buffer while we're reading it. | |
832 | */ | |
833 | devrec->rx_msg.complete = mrf24j40_handle_rx_read_len; | |
834 | devrec->rx_trx.len = 2; | |
835 | devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1); | |
7d840545 | 836 | devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */ |
c91a3011 AA |
837 | |
838 | return spi_async(devrec->spi, &devrec->rx_msg); | |
3731a334 AO |
839 | } |
840 | ||
2323cf38 AA |
841 | static int |
842 | mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be, | |
843 | u8 retries) | |
844 | { | |
845 | struct mrf24j40 *devrec = hw->priv; | |
846 | u8 val; | |
847 | ||
848 | /* min_be */ | |
7d840545 | 849 | val = min_be << TXMCR_MIN_BE_SHIFT; |
2323cf38 | 850 | /* csma backoffs */ |
7d840545 | 851 | val |= retries << TXMCR_CSMA_RETRIES_SHIFT; |
2323cf38 | 852 | |
7d840545 AA |
853 | return regmap_update_bits(devrec->regmap_short, REG_TXMCR, |
854 | TXMCR_MIN_BE_MASK | TXMCR_CSMA_RETRIES_MASK, | |
855 | val); | |
2323cf38 AA |
856 | } |
857 | ||
f1d78127 AA |
858 | static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw, |
859 | const struct wpan_phy_cca *cca) | |
860 | { | |
861 | struct mrf24j40 *devrec = hw->priv; | |
862 | u8 val; | |
863 | ||
864 | /* mapping 802.15.4 to driver spec */ | |
865 | switch (cca->mode) { | |
866 | case NL802154_CCA_ENERGY: | |
867 | val = 2; | |
868 | break; | |
869 | case NL802154_CCA_CARRIER: | |
870 | val = 1; | |
871 | break; | |
872 | case NL802154_CCA_ENERGY_CARRIER: | |
873 | switch (cca->opt) { | |
874 | case NL802154_CCA_OPT_ENERGY_CARRIER_AND: | |
875 | val = 3; | |
876 | break; | |
877 | default: | |
878 | return -EINVAL; | |
879 | } | |
880 | break; | |
881 | default: | |
882 | return -EINVAL; | |
883 | } | |
884 | ||
7d840545 AA |
885 | return regmap_update_bits(devrec->regmap_short, REG_BBREG2, |
886 | BBREG2_CCA_MODE_MASK, | |
887 | val << BBREG2_CCA_MODE_SHIFT); | |
f1d78127 AA |
888 | } |
889 | ||
e33a0f96 AA |
890 | /* array for representing ed levels */ |
891 | static const s32 mrf24j40_ed_levels[] = { | |
892 | -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100, | |
893 | -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100, | |
894 | -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100, | |
895 | -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100, | |
896 | -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100, | |
897 | -4000, -3900, -3800, -3700, -3600, -3500 | |
898 | }; | |
899 | ||
900 | /* map ed levels to register value */ | |
901 | static const s32 mrf24j40_ed_levels_map[][2] = { | |
902 | { -9000, 0 }, { -8900, 1 }, { -8800, 2 }, { -8700, 5 }, { -8600, 9 }, | |
903 | { -8500, 13 }, { -8400, 18 }, { -8300, 23 }, { -8200, 27 }, | |
904 | { -8100, 32 }, { -8000, 37 }, { -7900, 43 }, { -7800, 48 }, | |
905 | { -7700, 53 }, { -7600, 58 }, { -7500, 63 }, { -7400, 68 }, | |
906 | { -7300, 73 }, { -7200, 78 }, { -7100, 83 }, { -7000, 89 }, | |
907 | { -6900, 95 }, { -6800, 100 }, { -6700, 107 }, { -6600, 111 }, | |
908 | { -6500, 117 }, { -6400, 121 }, { -6300, 125 }, { -6200, 129 }, | |
909 | { -6100, 133 }, { -6000, 138 }, { -5900, 143 }, { -5800, 148 }, | |
910 | { -5700, 153 }, { -5600, 159 }, { -5500, 165 }, { -5400, 170 }, | |
911 | { -5300, 176 }, { -5200, 183 }, { -5100, 188 }, { -5000, 193 }, | |
912 | { -4900, 198 }, { -4800, 203 }, { -4700, 207 }, { -4600, 212 }, | |
913 | { -4500, 216 }, { -4400, 221 }, { -4300, 225 }, { -4200, 228 }, | |
914 | { -4100, 233 }, { -4000, 239 }, { -3900, 245 }, { -3800, 250 }, | |
915 | { -3700, 253 }, { -3600, 254 }, { -3500, 255 }, | |
916 | }; | |
917 | ||
918 | static int mrf24j40_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm) | |
919 | { | |
920 | struct mrf24j40 *devrec = hw->priv; | |
921 | int i; | |
922 | ||
923 | for (i = 0; i < ARRAY_SIZE(mrf24j40_ed_levels_map); i++) { | |
924 | if (mrf24j40_ed_levels_map[i][0] == mbm) | |
925 | return regmap_write(devrec->regmap_short, REG_CCAEDTH, | |
926 | mrf24j40_ed_levels_map[i][1]); | |
927 | } | |
928 | ||
929 | return -EINVAL; | |
930 | } | |
931 | ||
00250f78 AA |
932 | static const s32 mrf24j40ma_powers[] = { |
933 | 0, -50, -120, -190, -280, -370, -490, -630, -1000, -1050, -1120, -1190, | |
934 | -1280, -1370, -1490, -1630, -2000, -2050, -2120, -2190, -2280, -2370, | |
935 | -2490, -2630, -3000, -3050, -3120, -3190, -3280, -3370, -3490, -3630, | |
936 | }; | |
937 | ||
938 | static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm) | |
939 | { | |
940 | struct mrf24j40 *devrec = hw->priv; | |
941 | s32 small_scale; | |
942 | u8 val; | |
943 | ||
944 | if (0 >= mbm && mbm > -1000) { | |
7d840545 | 945 | val = TXPWRL_0 << TXPWRL_SHIFT; |
00250f78 AA |
946 | small_scale = mbm; |
947 | } else if (-1000 >= mbm && mbm > -2000) { | |
7d840545 | 948 | val = TXPWRL_10 << TXPWRL_SHIFT; |
00250f78 AA |
949 | small_scale = mbm + 1000; |
950 | } else if (-2000 >= mbm && mbm > -3000) { | |
7d840545 | 951 | val = TXPWRL_20 << TXPWRL_SHIFT; |
00250f78 AA |
952 | small_scale = mbm + 2000; |
953 | } else if (-3000 >= mbm && mbm > -4000) { | |
7d840545 | 954 | val = TXPWRL_30 << TXPWRL_SHIFT; |
00250f78 AA |
955 | small_scale = mbm + 3000; |
956 | } else { | |
957 | return -EINVAL; | |
958 | } | |
959 | ||
960 | switch (small_scale) { | |
961 | case 0: | |
7d840545 | 962 | val |= (TXPWRS_0 << TXPWRS_SHIFT); |
00250f78 AA |
963 | break; |
964 | case -50: | |
7d840545 | 965 | val |= (TXPWRS_0_5 << TXPWRS_SHIFT); |
00250f78 AA |
966 | break; |
967 | case -120: | |
7d840545 | 968 | val |= (TXPWRS_1_2 << TXPWRS_SHIFT); |
00250f78 AA |
969 | break; |
970 | case -190: | |
7d840545 | 971 | val |= (TXPWRS_1_9 << TXPWRS_SHIFT); |
00250f78 AA |
972 | break; |
973 | case -280: | |
7d840545 | 974 | val |= (TXPWRS_2_8 << TXPWRS_SHIFT); |
00250f78 AA |
975 | break; |
976 | case -370: | |
7d840545 | 977 | val |= (TXPWRS_3_7 << TXPWRS_SHIFT); |
00250f78 AA |
978 | break; |
979 | case -490: | |
7d840545 | 980 | val |= (TXPWRS_4_9 << TXPWRS_SHIFT); |
00250f78 AA |
981 | break; |
982 | case -630: | |
7d840545 | 983 | val |= (TXPWRS_6_3 << TXPWRS_SHIFT); |
00250f78 AA |
984 | break; |
985 | default: | |
986 | return -EINVAL; | |
987 | } | |
988 | ||
7d840545 AA |
989 | return regmap_update_bits(devrec->regmap_long, REG_RFCON3, |
990 | TXPWRL_MASK | TXPWRS_MASK, val); | |
00250f78 AA |
991 | } |
992 | ||
8ba40417 AA |
993 | static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on) |
994 | { | |
995 | struct mrf24j40 *devrec = hw->priv; | |
996 | int ret; | |
997 | ||
998 | if (on) { | |
999 | /* set PROMI, ERRPKT and NOACKRSP */ | |
7d840545 AA |
1000 | ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, |
1001 | BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP, | |
1002 | BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP); | |
8ba40417 AA |
1003 | } else { |
1004 | /* clear PROMI, ERRPKT and NOACKRSP */ | |
7d840545 AA |
1005 | ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, |
1006 | BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP, | |
1007 | 0); | |
8ba40417 AA |
1008 | } |
1009 | ||
1010 | return ret; | |
1011 | } | |
1012 | ||
16301861 | 1013 | static const struct ieee802154_ops mrf24j40_ops = { |
3731a334 | 1014 | .owner = THIS_MODULE, |
6844a0e4 | 1015 | .xmit_async = mrf24j40_tx, |
3731a334 AO |
1016 | .ed = mrf24j40_ed, |
1017 | .start = mrf24j40_start, | |
1018 | .stop = mrf24j40_stop, | |
1019 | .set_channel = mrf24j40_set_channel, | |
1020 | .set_hw_addr_filt = mrf24j40_filter, | |
2323cf38 | 1021 | .set_csma_params = mrf24j40_csma_params, |
f1d78127 | 1022 | .set_cca_mode = mrf24j40_set_cca_mode, |
e33a0f96 | 1023 | .set_cca_ed_level = mrf24j40_set_cca_ed_level, |
00250f78 | 1024 | .set_txpower = mrf24j40_set_txpower, |
8ba40417 | 1025 | .set_promiscuous_mode = mrf24j40_set_promiscuous_mode, |
3731a334 AO |
1026 | }; |
1027 | ||
37441611 | 1028 | static void mrf24j40_intstat_complete(void *context) |
3731a334 | 1029 | { |
37441611 AA |
1030 | struct mrf24j40 *devrec = context; |
1031 | u8 intstat = devrec->irq_buf[1]; | |
3731a334 | 1032 | |
37441611 | 1033 | enable_irq(devrec->spi->irq); |
3731a334 | 1034 | |
5a62f3c6 AM |
1035 | /* Ignore Rx security decryption */ |
1036 | if (intstat & BIT_SECIF) | |
1037 | regmap_write_async(devrec->regmap_short, REG_SECCON0, | |
1038 | BIT_SECIGNORE); | |
1039 | ||
3731a334 | 1040 | /* Check for TX complete */ |
7d840545 | 1041 | if (intstat & BIT_TXNIF) |
6844a0e4 | 1042 | ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false); |
3731a334 AO |
1043 | |
1044 | /* Check for Rx */ | |
7d840545 | 1045 | if (intstat & BIT_RXIF) |
3731a334 | 1046 | mrf24j40_handle_rx(devrec); |
37441611 AA |
1047 | } |
1048 | ||
1049 | static irqreturn_t mrf24j40_isr(int irq, void *data) | |
1050 | { | |
1051 | struct mrf24j40 *devrec = data; | |
1052 | int ret; | |
1053 | ||
1054 | disable_irq_nosync(irq); | |
1055 | ||
1056 | devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT); | |
1057 | /* Read the interrupt status */ | |
1058 | ret = spi_async(devrec->spi, &devrec->irq_msg); | |
1059 | if (ret) { | |
1060 | enable_irq(irq); | |
1061 | return IRQ_NONE; | |
1062 | } | |
3731a334 | 1063 | |
4a4e1da8 | 1064 | return IRQ_HANDLED; |
3731a334 AO |
1065 | } |
1066 | ||
3dac9a79 VB |
1067 | static int mrf24j40_hw_init(struct mrf24j40 *devrec) |
1068 | { | |
afaf7fde | 1069 | u32 irq_type; |
3dac9a79 | 1070 | int ret; |
3dac9a79 VB |
1071 | |
1072 | /* Initialize the device. | |
1073 | From datasheet section 3.2: Initialization. */ | |
42c7148e | 1074 | ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07); |
3dac9a79 VB |
1075 | if (ret) |
1076 | goto err_ret; | |
1077 | ||
42c7148e | 1078 | ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98); |
3dac9a79 VB |
1079 | if (ret) |
1080 | goto err_ret; | |
1081 | ||
42c7148e | 1082 | ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95); |
3dac9a79 VB |
1083 | if (ret) |
1084 | goto err_ret; | |
1085 | ||
42c7148e | 1086 | ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03); |
3dac9a79 VB |
1087 | if (ret) |
1088 | goto err_ret; | |
1089 | ||
42c7148e | 1090 | ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01); |
3dac9a79 VB |
1091 | if (ret) |
1092 | goto err_ret; | |
1093 | ||
42c7148e | 1094 | ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80); |
3dac9a79 VB |
1095 | if (ret) |
1096 | goto err_ret; | |
1097 | ||
42c7148e | 1098 | ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90); |
3dac9a79 VB |
1099 | if (ret) |
1100 | goto err_ret; | |
1101 | ||
42c7148e | 1102 | ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80); |
3dac9a79 VB |
1103 | if (ret) |
1104 | goto err_ret; | |
1105 | ||
42c7148e | 1106 | ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10); |
3dac9a79 VB |
1107 | if (ret) |
1108 | goto err_ret; | |
1109 | ||
42c7148e | 1110 | ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21); |
3dac9a79 VB |
1111 | if (ret) |
1112 | goto err_ret; | |
1113 | ||
42c7148e | 1114 | ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80); |
3dac9a79 VB |
1115 | if (ret) |
1116 | goto err_ret; | |
1117 | ||
42c7148e | 1118 | ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60); |
3dac9a79 VB |
1119 | if (ret) |
1120 | goto err_ret; | |
1121 | ||
42c7148e | 1122 | ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40); |
3dac9a79 VB |
1123 | if (ret) |
1124 | goto err_ret; | |
1125 | ||
42c7148e | 1126 | ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04); |
3dac9a79 VB |
1127 | if (ret) |
1128 | goto err_ret; | |
1129 | ||
42c7148e | 1130 | ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0); |
3dac9a79 VB |
1131 | if (ret) |
1132 | goto err_ret; | |
1133 | ||
1134 | udelay(192); | |
1135 | ||
1136 | /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */ | |
42c7148e | 1137 | ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00); |
3dac9a79 VB |
1138 | if (ret) |
1139 | goto err_ret; | |
1140 | ||
db9e0ee8 SV |
1141 | if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) { |
1142 | /* Enable external amplifier. | |
1143 | * From MRF24J40MC datasheet section 1.3: Operation. | |
1144 | */ | |
42c7148e AA |
1145 | regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07, |
1146 | 0x07); | |
db9e0ee8 | 1147 | |
42c7148e AA |
1148 | /* Set GPIO3 as output. */ |
1149 | regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08, | |
1150 | 0x08); | |
db9e0ee8 | 1151 | |
42c7148e AA |
1152 | /* Set GPIO3 HIGH to enable U5 voltage regulator */ |
1153 | regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08); | |
db9e0ee8 SV |
1154 | |
1155 | /* Reduce TX pwr to meet FCC requirements. | |
1156 | * From MRF24J40MC datasheet section 3.1.1 | |
1157 | */ | |
42c7148e | 1158 | regmap_write(devrec->regmap_long, REG_RFCON3, 0x28); |
db9e0ee8 SV |
1159 | } |
1160 | ||
afaf7fde AA |
1161 | irq_type = irq_get_trigger_type(devrec->spi->irq); |
1162 | if (irq_type == IRQ_TYPE_EDGE_RISING || | |
1163 | irq_type == IRQ_TYPE_EDGE_FALLING) | |
1164 | dev_warn(&devrec->spi->dev, | |
1165 | "Using edge triggered irq's are not recommended, because it can cause races and result in a non-functional driver!\n"); | |
1166 | switch (irq_type) { | |
1167 | case IRQ_TYPE_EDGE_RISING: | |
1168 | case IRQ_TYPE_LEVEL_HIGH: | |
1169 | /* set interrupt polarity to rising */ | |
1170 | ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0, | |
7d840545 | 1171 | BIT_INTEDGE, BIT_INTEDGE); |
afaf7fde AA |
1172 | if (ret) |
1173 | goto err_ret; | |
1174 | break; | |
1175 | default: | |
1176 | /* default is falling edge */ | |
1177 | break; | |
1178 | } | |
1179 | ||
3dac9a79 VB |
1180 | return 0; |
1181 | ||
1182 | err_ret: | |
1183 | return ret; | |
1184 | } | |
1185 | ||
6844a0e4 AA |
1186 | static void |
1187 | mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec) | |
1188 | { | |
1189 | spi_message_init(&devrec->tx_msg); | |
1190 | devrec->tx_msg.context = devrec; | |
1191 | devrec->tx_msg.complete = write_tx_buf_complete; | |
1192 | devrec->tx_hdr_trx.len = 2; | |
1193 | devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf; | |
1194 | spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg); | |
1195 | devrec->tx_len_trx.len = 2; | |
1196 | devrec->tx_len_trx.tx_buf = devrec->tx_len_buf; | |
1197 | spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg); | |
1198 | spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg); | |
1199 | ||
1200 | spi_message_init(&devrec->tx_post_msg); | |
1201 | devrec->tx_post_msg.context = devrec; | |
1202 | devrec->tx_post_trx.len = 2; | |
1203 | devrec->tx_post_trx.tx_buf = devrec->tx_post_buf; | |
1204 | spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg); | |
1205 | } | |
1206 | ||
c91a3011 AA |
1207 | static void |
1208 | mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec) | |
1209 | { | |
1210 | spi_message_init(&devrec->rx_msg); | |
1211 | devrec->rx_msg.context = devrec; | |
1212 | devrec->rx_trx.len = 2; | |
1213 | devrec->rx_trx.tx_buf = devrec->rx_buf; | |
1214 | devrec->rx_trx.rx_buf = devrec->rx_buf; | |
1215 | spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg); | |
1216 | ||
1217 | spi_message_init(&devrec->rx_buf_msg); | |
1218 | devrec->rx_buf_msg.context = devrec; | |
1219 | devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete; | |
1220 | devrec->rx_addr_trx.len = 2; | |
1221 | devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf; | |
1222 | spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg); | |
1223 | devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf; | |
1224 | spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg); | |
1225 | devrec->rx_lqi_trx.len = 2; | |
1226 | devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf; | |
1227 | spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg); | |
1228 | } | |
1229 | ||
37441611 AA |
1230 | static void |
1231 | mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec) | |
1232 | { | |
1233 | spi_message_init(&devrec->irq_msg); | |
1234 | devrec->irq_msg.context = devrec; | |
1235 | devrec->irq_msg.complete = mrf24j40_intstat_complete; | |
1236 | devrec->irq_trx.len = 2; | |
1237 | devrec->irq_trx.tx_buf = devrec->irq_buf; | |
1238 | devrec->irq_trx.rx_buf = devrec->irq_buf; | |
1239 | spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg); | |
1240 | } | |
1241 | ||
766928fb AA |
1242 | static void mrf24j40_phy_setup(struct mrf24j40 *devrec) |
1243 | { | |
d344c912 | 1244 | ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr); |
766928fb | 1245 | devrec->hw->phy->current_channel = 11; |
2323cf38 AA |
1246 | |
1247 | /* mrf24j40 supports max_minbe 0 - 3 */ | |
1248 | devrec->hw->phy->supported.max_minbe = 3; | |
1249 | /* datasheet doesn't say anything about max_be, but we have min_be | |
1250 | * So we assume the max_be default. | |
1251 | */ | |
1252 | devrec->hw->phy->supported.min_maxbe = 5; | |
1253 | devrec->hw->phy->supported.max_maxbe = 5; | |
f1d78127 | 1254 | |
eb24d061 | 1255 | devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER; |
f1d78127 AA |
1256 | devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) | |
1257 | BIT(NL802154_CCA_CARRIER) | | |
1258 | BIT(NL802154_CCA_ENERGY_CARRIER); | |
1259 | devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND); | |
e33a0f96 AA |
1260 | |
1261 | devrec->hw->phy->cca_ed_level = -6900; | |
1262 | devrec->hw->phy->supported.cca_ed_levels = mrf24j40_ed_levels; | |
1263 | devrec->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(mrf24j40_ed_levels); | |
00250f78 AA |
1264 | |
1265 | switch (spi_get_device_id(devrec->spi)->driver_data) { | |
1266 | case MRF24J40: | |
1267 | case MRF24J40MA: | |
1268 | devrec->hw->phy->supported.tx_powers = mrf24j40ma_powers; | |
1269 | devrec->hw->phy->supported.tx_powers_size = ARRAY_SIZE(mrf24j40ma_powers); | |
1270 | devrec->hw->phy->flags |= WPAN_PHY_FLAG_TXPOWER; | |
1271 | break; | |
1272 | default: | |
1273 | break; | |
1274 | } | |
766928fb AA |
1275 | } |
1276 | ||
bb1f4606 | 1277 | static int mrf24j40_probe(struct spi_device *spi) |
3731a334 | 1278 | { |
afaf7fde | 1279 | int ret = -ENOMEM, irq_type; |
b2cfdf3c | 1280 | struct ieee802154_hw *hw; |
3731a334 AO |
1281 | struct mrf24j40 *devrec; |
1282 | ||
ca079ad6 | 1283 | dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq); |
3731a334 | 1284 | |
b2cfdf3c AA |
1285 | /* Register with the 802154 subsystem */ |
1286 | ||
1287 | hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops); | |
1288 | if (!hw) | |
0aaf43f5 | 1289 | goto err_ret; |
b2cfdf3c AA |
1290 | |
1291 | devrec = hw->priv; | |
1292 | devrec->spi = spi; | |
1293 | spi_set_drvdata(spi, devrec); | |
1294 | devrec->hw = hw; | |
1295 | devrec->hw->parent = &spi->dev; | |
1296 | devrec->hw->phy->supported.channels[0] = CHANNEL_MASK; | |
2323cf38 | 1297 | devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT | |
8ba40417 AA |
1298 | IEEE802154_HW_CSMA_PARAMS | |
1299 | IEEE802154_HW_PROMISCUOUS; | |
b2cfdf3c | 1300 | |
e33a0f96 AA |
1301 | devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE | |
1302 | WPAN_PHY_FLAG_CCA_ED_LEVEL; | |
f1d78127 | 1303 | |
6844a0e4 | 1304 | mrf24j40_setup_tx_spi_messages(devrec); |
c91a3011 | 1305 | mrf24j40_setup_rx_spi_messages(devrec); |
37441611 | 1306 | mrf24j40_setup_irq_spi_messages(devrec); |
6844a0e4 | 1307 | |
b0156792 AA |
1308 | devrec->regmap_short = devm_regmap_init_spi(spi, |
1309 | &mrf24j40_short_regmap); | |
1310 | if (IS_ERR(devrec->regmap_short)) { | |
1311 | ret = PTR_ERR(devrec->regmap_short); | |
1312 | dev_err(&spi->dev, "Failed to allocate short register map: %d\n", | |
1313 | ret); | |
1314 | goto err_register_device; | |
1315 | } | |
1316 | ||
1317 | devrec->regmap_long = devm_regmap_init(&spi->dev, | |
1318 | &mrf24j40_long_regmap_bus, | |
1319 | spi, &mrf24j40_long_regmap); | |
1320 | if (IS_ERR(devrec->regmap_long)) { | |
1321 | ret = PTR_ERR(devrec->regmap_long); | |
1322 | dev_err(&spi->dev, "Failed to allocate long register map: %d\n", | |
1323 | ret); | |
1324 | goto err_register_device; | |
1325 | } | |
1326 | ||
78aedb6b AA |
1327 | if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) { |
1328 | dev_warn(&spi->dev, "spi clock above possible maximum: %d", | |
1329 | MAX_SPI_SPEED_HZ); | |
1330 | return -EINVAL; | |
1331 | } | |
3731a334 | 1332 | |
3dac9a79 | 1333 | ret = mrf24j40_hw_init(devrec); |
3731a334 | 1334 | if (ret) |
a339e184 | 1335 | goto err_register_device; |
3731a334 | 1336 | |
766928fb AA |
1337 | mrf24j40_phy_setup(devrec); |
1338 | ||
afaf7fde AA |
1339 | /* request IRQF_TRIGGER_LOW as fallback default */ |
1340 | irq_type = irq_get_trigger_type(spi->irq); | |
1341 | if (!irq_type) | |
1342 | irq_type = IRQF_TRIGGER_LOW; | |
1343 | ||
37441611 | 1344 | ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr, |
afaf7fde | 1345 | irq_type, dev_name(&spi->dev), devrec); |
3731a334 AO |
1346 | if (ret) { |
1347 | dev_err(printdev(devrec), "Unable to get IRQ"); | |
a339e184 | 1348 | goto err_register_device; |
3731a334 AO |
1349 | } |
1350 | ||
a339e184 AA |
1351 | dev_dbg(printdev(devrec), "registered mrf24j40\n"); |
1352 | ret = ieee802154_register_hw(devrec->hw); | |
1353 | if (ret) | |
1354 | goto err_register_device; | |
1355 | ||
3731a334 AO |
1356 | return 0; |
1357 | ||
3731a334 | 1358 | err_register_device: |
5a504397 | 1359 | ieee802154_free_hw(devrec->hw); |
0aaf43f5 | 1360 | err_ret: |
3731a334 AO |
1361 | return ret; |
1362 | } | |
1363 | ||
bb1f4606 | 1364 | static int mrf24j40_remove(struct spi_device *spi) |
3731a334 | 1365 | { |
4fa0a0ef | 1366 | struct mrf24j40 *devrec = spi_get_drvdata(spi); |
3731a334 AO |
1367 | |
1368 | dev_dbg(printdev(devrec), "remove\n"); | |
1369 | ||
5a504397 AA |
1370 | ieee802154_unregister_hw(devrec->hw); |
1371 | ieee802154_free_hw(devrec->hw); | |
3731a334 AO |
1372 | /* TODO: Will ieee802154_free_device() wait until ->xmit() is |
1373 | * complete? */ | |
1374 | ||
3731a334 AO |
1375 | return 0; |
1376 | } | |
1377 | ||
2e6fd648 AA |
1378 | static const struct of_device_id mrf24j40_of_match[] = { |
1379 | { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 }, | |
1380 | { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA }, | |
1381 | { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC }, | |
1382 | { }, | |
1383 | }; | |
1384 | MODULE_DEVICE_TABLE(of, mrf24j40_of_match); | |
1385 | ||
3731a334 | 1386 | static const struct spi_device_id mrf24j40_ids[] = { |
db9e0ee8 SV |
1387 | { "mrf24j40", MRF24J40 }, |
1388 | { "mrf24j40ma", MRF24J40MA }, | |
1389 | { "mrf24j40mc", MRF24J40MC }, | |
3731a334 AO |
1390 | { }, |
1391 | }; | |
1392 | MODULE_DEVICE_TABLE(spi, mrf24j40_ids); | |
1393 | ||
1394 | static struct spi_driver mrf24j40_driver = { | |
1395 | .driver = { | |
2e6fd648 | 1396 | .of_match_table = of_match_ptr(mrf24j40_of_match), |
3731a334 | 1397 | .name = "mrf24j40", |
3731a334 AO |
1398 | }, |
1399 | .id_table = mrf24j40_ids, | |
1400 | .probe = mrf24j40_probe, | |
bb1f4606 | 1401 | .remove = mrf24j40_remove, |
3731a334 AO |
1402 | }; |
1403 | ||
3d4a1316 | 1404 | module_spi_driver(mrf24j40_driver); |
3731a334 AO |
1405 | |
1406 | MODULE_LICENSE("GPL"); | |
1407 | MODULE_AUTHOR("Alan Ott"); | |
1408 | MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver"); |