projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
xfrm: Accept ESP packets regardless of UDP encapsulation mode
[deliverable/linux.git] / drivers / net / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/vmalloc.h>
32#include <linux/pagemap.h>
33#include <linux/netdevice.h>
9d5c8243
AK		 34#include <linux/ipv6.h>
35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
37#include <linux/mii.h>
38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/pci.h>
c54106bb 41#include <linux/pci-aspm.h>
9d5c8243
AK		 42#include <linux/delay.h>
43#include <linux/interrupt.h>
44#include <linux/if_ether.h>
40a914fa 45#include <linux/aer.h>
421e02f0 46#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 47#include <linux/dca.h>
48#endif
9d5c8243
AK		 49#include "igb.h"
50
0024fd00 51#define DRV_VERSION "1.2.45-k2"
9d5c8243
AK		 52char igb_driver_name[] = "igb";
53char igb_driver_version[] = DRV_VERSION;
54static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
2d064c06 56static const char igb_copyright[] = "Copyright (c) 2008 Intel Corporation.";
9d5c8243 57
9d5c8243
AK		 58static const struct e1000_info *igb_info_tbl[] = {
59 [board_82575] = &e1000_82575_info,
60};
61
62static struct pci_device_id igb_pci_tbl[] = {
2d064c06
AD		 63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
9d5c8243
AK		 66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
69 /* required last entry */
70 {0, }
71};
72
73MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
74
75void igb_reset(struct igb_adapter *);
76static int igb_setup_all_tx_resources(struct igb_adapter *);
77static int igb_setup_all_rx_resources(struct igb_adapter *);
78static void igb_free_all_tx_resources(struct igb_adapter *);
79static void igb_free_all_rx_resources(struct igb_adapter *);
9d5c8243
AK		 80void igb_update_stats(struct igb_adapter *);
81static int igb_probe(struct pci_dev *, const struct pci_device_id *);
82static void __devexit igb_remove(struct pci_dev *pdev);
83static int igb_sw_init(struct igb_adapter *);
84static int igb_open(struct net_device *);
85static int igb_close(struct net_device *);
86static void igb_configure_tx(struct igb_adapter *);
87static void igb_configure_rx(struct igb_adapter *);
88static void igb_setup_rctl(struct igb_adapter *);
89static void igb_clean_all_tx_rings(struct igb_adapter *);
90static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 91static void igb_clean_tx_ring(struct igb_ring *);
92static void igb_clean_rx_ring(struct igb_ring *);
9d5c8243
AK		 93static void igb_set_multi(struct net_device *);
94static void igb_update_phy_info(unsigned long);
95static void igb_watchdog(unsigned long);
96static void igb_watchdog_task(struct work_struct *);
97static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
98 struct igb_ring *);
99static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
100static struct net_device_stats *igb_get_stats(struct net_device *);
101static int igb_change_mtu(struct net_device *, int);
102static int igb_set_mac(struct net_device *, void *);
103static irqreturn_t igb_intr(int irq, void *);
104static irqreturn_t igb_intr_msi(int irq, void *);
105static irqreturn_t igb_msix_other(int irq, void *);
106static irqreturn_t igb_msix_rx(int irq, void *);
107static irqreturn_t igb_msix_tx(int irq, void *);
108static int igb_clean_rx_ring_msix(struct napi_struct *, int);
421e02f0 109#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 110static void igb_update_rx_dca(struct igb_ring *);
111static void igb_update_tx_dca(struct igb_ring *);
112static void igb_setup_dca(struct igb_adapter *);
421e02f0 113#endif /* CONFIG_IGB_DCA */
3b644cf6 114static bool igb_clean_tx_irq(struct igb_ring *);
661086df 115static int igb_poll(struct napi_struct *, int);
3b644cf6
MW		 116static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
117static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
d3352520
AD		 118#ifdef CONFIG_IGB_LRO
119static int igb_get_skb_hdr(struct sk_buff *skb, void **, void **, u64 *, void *);
120#endif
9d5c8243
AK		 121static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
122static void igb_tx_timeout(struct net_device *);
123static void igb_reset_task(struct work_struct *);
124static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
125static void igb_vlan_rx_add_vid(struct net_device *, u16);
126static void igb_vlan_rx_kill_vid(struct net_device *, u16);
127static void igb_restore_vlan(struct igb_adapter *);
128
129static int igb_suspend(struct pci_dev *, pm_message_t);
130#ifdef CONFIG_PM
131static int igb_resume(struct pci_dev *);
132#endif
133static void igb_shutdown(struct pci_dev *);
421e02f0 134#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 135static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
136static struct notifier_block dca_notifier = {
137 .notifier_call = igb_notify_dca,
138 .next = NULL,
139 .priority = 0
140};
141#endif
9d5c8243
AK		 142
143#ifdef CONFIG_NET_POLL_CONTROLLER
144/* for netdump / net console */
145static void igb_netpoll(struct net_device *);
146#endif
147
148static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
149 pci_channel_state_t);
150static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
151static void igb_io_resume(struct pci_dev *);
152
153static struct pci_error_handlers igb_err_handler = {
154 .error_detected = igb_io_error_detected,
155 .slot_reset = igb_io_slot_reset,
156 .resume = igb_io_resume,
157};
158
159
160static struct pci_driver igb_driver = {
161 .name = igb_driver_name,
162 .id_table = igb_pci_tbl,
163 .probe = igb_probe,
164 .remove = __devexit_p(igb_remove),
165#ifdef CONFIG_PM
166 /* Power Managment Hooks */
167 .suspend = igb_suspend,
168 .resume = igb_resume,
169#endif
170 .shutdown = igb_shutdown,
171 .err_handler = &igb_err_handler
172};
173
7dfc16fa
AD		 174static int global_quad_port_a; /* global quad port a indication */
175
9d5c8243
AK		 176MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
177MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
178MODULE_LICENSE("GPL");
179MODULE_VERSION(DRV_VERSION);
180
181#ifdef DEBUG
182/**
183 * igb_get_hw_dev_name - return device name string
184 * used by hardware layer to print debugging information
185 **/
186char *igb_get_hw_dev_name(struct e1000_hw *hw)
187{
188 struct igb_adapter *adapter = hw->back;
189 return adapter->netdev->name;
190}
191#endif
192
193/**
194 * igb_init_module - Driver Registration Routine
195 *
196 * igb_init_module is the first routine called when the driver is
197 * loaded. All it does is register with the PCI subsystem.
198 **/
199static int __init igb_init_module(void)
200{
201 int ret;
202 printk(KERN_INFO "%s - version %s\n",
203 igb_driver_string, igb_driver_version);
204
205 printk(KERN_INFO "%s\n", igb_copyright);
206
7dfc16fa
AD		 207 global_quad_port_a = 0;
208
9d5c8243 209 ret = pci_register_driver(&igb_driver);
421e02f0 210#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 211 dca_register_notify(&dca_notifier);
212#endif
9d5c8243
AK		 213 return ret;
214}
215
216module_init(igb_init_module);
217
218/**
219 * igb_exit_module - Driver Exit Cleanup Routine
220 *
221 * igb_exit_module is called just before the driver is removed
222 * from memory.
223 **/
224static void __exit igb_exit_module(void)
225{
421e02f0 226#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 227 dca_unregister_notify(&dca_notifier);
228#endif
9d5c8243
AK		 229 pci_unregister_driver(&igb_driver);
230}
231
232module_exit(igb_exit_module);
233
234/**
235 * igb_alloc_queues - Allocate memory for all rings
236 * @adapter: board private structure to initialize
237 *
238 * We allocate one ring per queue at run-time since we don't know the
239 * number of queues at compile-time.
240 **/
241static int igb_alloc_queues(struct igb_adapter *adapter)
242{
243 int i;
244
245 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
246 sizeof(struct igb_ring), GFP_KERNEL);
247 if (!adapter->tx_ring)
248 return -ENOMEM;
249
250 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
251 sizeof(struct igb_ring), GFP_KERNEL);
252 if (!adapter->rx_ring) {
253 kfree(adapter->tx_ring);
254 return -ENOMEM;
255 }
256
6eb5a7f1
AD		 257 adapter->rx_ring->buddy = adapter->tx_ring;
258
661086df
PWJ		 259 for (i = 0; i < adapter->num_tx_queues; i++) {
260 struct igb_ring *ring = &(adapter->tx_ring[i]);
68fd9910 261 ring->count = adapter->tx_ring_count;
661086df
PWJ		 262 ring->adapter = adapter;
263 ring->queue_index = i;
264 }
9d5c8243
AK		 265 for (i = 0; i < adapter->num_rx_queues; i++) {
266 struct igb_ring *ring = &(adapter->rx_ring[i]);
68fd9910 267 ring->count = adapter->rx_ring_count;
9d5c8243 268 ring->adapter = adapter;
844290e5 269 ring->queue_index = i;
9d5c8243
AK		 270 ring->itr_register = E1000_ITR;
271
844290e5 272 /* set a default napi handler for each rx_ring */
661086df 273 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
9d5c8243
AK		 274 }
275 return 0;
276}
277
a88f10ec
AD		 278static void igb_free_queues(struct igb_adapter *adapter)
279{
280 int i;
281
282 for (i = 0; i < adapter->num_rx_queues; i++)
283 netif_napi_del(&adapter->rx_ring[i].napi);
284
285 kfree(adapter->tx_ring);
286 kfree(adapter->rx_ring);
287}
288
9d5c8243
AK		 289#define IGB_N0_QUEUE -1
290static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
291 int tx_queue, int msix_vector)
292{
293 u32 msixbm = 0;
294 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 295 u32 ivar, index;
296
297 switch (hw->mac.type) {
298 case e1000_82575:
9d5c8243
AK		 299 /* The 82575 assigns vectors using a bitmask, which matches the
300 bitmask for the EICR/EIMS/EIMC registers. To assign one
301 or more queues to a vector, we write the appropriate bits
302 into the MSIXBM register for that vector. */
303 if (rx_queue > IGB_N0_QUEUE) {
304 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
305 adapter->rx_ring[rx_queue].eims_value = msixbm;
306 }
307 if (tx_queue > IGB_N0_QUEUE) {
308 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
309 adapter->tx_ring[tx_queue].eims_value =
310 E1000_EICR_TX_QUEUE0 << tx_queue;
311 }
312 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
2d064c06
AD		 313 break;
314 case e1000_82576:
106ef2fe 315 /* The 82576 uses a table-based method for assigning vectors.
2d064c06
AD		 316 Each queue has a single entry in the table to which we write
317 a vector number along with a "valid" bit. Sadly, the layout
318 of the table is somewhat counterintuitive. */
319 if (rx_queue > IGB_N0_QUEUE) {
320 index = (rx_queue & 0x7);
321 ivar = array_rd32(E1000_IVAR0, index);
322 if (rx_queue < 8) {
323 /* vector goes into low byte of register */
324 ivar = ivar & 0xFFFFFF00;
325 ivar |= msix_vector | E1000_IVAR_VALID;
326 } else {
327 /* vector goes into third byte of register */
328 ivar = ivar & 0xFF00FFFF;
329 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
330 }
331 adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
332 array_wr32(E1000_IVAR0, index, ivar);
333 }
334 if (tx_queue > IGB_N0_QUEUE) {
335 index = (tx_queue & 0x7);
336 ivar = array_rd32(E1000_IVAR0, index);
337 if (tx_queue < 8) {
338 /* vector goes into second byte of register */
339 ivar = ivar & 0xFFFF00FF;
340 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
341 } else {
342 /* vector goes into high byte of register */
343 ivar = ivar & 0x00FFFFFF;
344 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
345 }
346 adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
347 array_wr32(E1000_IVAR0, index, ivar);
348 }
349 break;
350 default:
351 BUG();
352 break;
353 }
9d5c8243
AK		 354}
355
356/**
357 * igb_configure_msix - Configure MSI-X hardware
358 *
359 * igb_configure_msix sets up the hardware to properly
360 * generate MSI-X interrupts.
361 **/
362static void igb_configure_msix(struct igb_adapter *adapter)
363{
364 u32 tmp;
365 int i, vector = 0;
366 struct e1000_hw *hw = &adapter->hw;
367
368 adapter->eims_enable_mask = 0;
2d064c06
AD		 369 if (hw->mac.type == e1000_82576)
370 /* Turn on MSI-X capability first, or our settings
371 * won't stick. And it will take days to debug. */
372 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
373 E1000_GPIE_PBA | E1000_GPIE_EIAME |
374 E1000_GPIE_NSICR);
9d5c8243
AK		 375
376 for (i = 0; i < adapter->num_tx_queues; i++) {
377 struct igb_ring *tx_ring = &adapter->tx_ring[i];
378 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
379 adapter->eims_enable_mask |= tx_ring->eims_value;
380 if (tx_ring->itr_val)
6eb5a7f1 381 writel(tx_ring->itr_val,
9d5c8243
AK		 382 hw->hw_addr + tx_ring->itr_register);
383 else
384 writel(1, hw->hw_addr + tx_ring->itr_register);
385 }
386
387 for (i = 0; i < adapter->num_rx_queues; i++) {
388 struct igb_ring *rx_ring = &adapter->rx_ring[i];
25ac3c24 389 rx_ring->buddy = NULL;
9d5c8243
AK		 390 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
391 adapter->eims_enable_mask |= rx_ring->eims_value;
392 if (rx_ring->itr_val)
6eb5a7f1 393 writel(rx_ring->itr_val,
9d5c8243
AK		 394 hw->hw_addr + rx_ring->itr_register);
395 else
396 writel(1, hw->hw_addr + rx_ring->itr_register);
397 }
398
399
400 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 401 switch (hw->mac.type) {
402 case e1000_82575:
9d5c8243
AK		 403 array_wr32(E1000_MSIXBM(0), vector++,
404 E1000_EIMS_OTHER);
405
9d5c8243
AK		 406 tmp = rd32(E1000_CTRL_EXT);
407 /* enable MSI-X PBA support*/
408 tmp |= E1000_CTRL_EXT_PBA_CLR;
409
410 /* Auto-Mask interrupts upon ICR read. */
411 tmp |= E1000_CTRL_EXT_EIAME;
412 tmp |= E1000_CTRL_EXT_IRCA;
413
414 wr32(E1000_CTRL_EXT, tmp);
415 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
844290e5 416 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 417
2d064c06
AD		 418 break;
419
420 case e1000_82576:
421 tmp = (vector++ | E1000_IVAR_VALID) << 8;
422 wr32(E1000_IVAR_MISC, tmp);
423
424 adapter->eims_enable_mask = (1 << (vector)) - 1;
425 adapter->eims_other = 1 << (vector - 1);
426 break;
427 default:
428 /* do nothing, since nothing else supports MSI-X */
429 break;
430 } /* switch (hw->mac.type) */
9d5c8243
AK		 431 wrfl();
432}
433
434/**
435 * igb_request_msix - Initialize MSI-X interrupts
436 *
437 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
438 * kernel.
439 **/
440static int igb_request_msix(struct igb_adapter *adapter)
441{
442 struct net_device *netdev = adapter->netdev;
443 int i, err = 0, vector = 0;
444
445 vector = 0;
446
447 for (i = 0; i < adapter->num_tx_queues; i++) {
448 struct igb_ring *ring = &(adapter->tx_ring[i]);
449 sprintf(ring->name, "%s-tx%d", netdev->name, i);
450 err = request_irq(adapter->msix_entries[vector].vector,
451 &igb_msix_tx, 0, ring->name,
452 &(adapter->tx_ring[i]));
453 if (err)
454 goto out;
455 ring->itr_register = E1000_EITR(0) + (vector << 2);
6eb5a7f1 456 ring->itr_val = 976; /* ~4000 ints/sec */
9d5c8243
AK		 457 vector++;
458 }
459 for (i = 0; i < adapter->num_rx_queues; i++) {
460 struct igb_ring *ring = &(adapter->rx_ring[i]);
461 if (strlen(netdev->name) < (IFNAMSIZ - 5))
462 sprintf(ring->name, "%s-rx%d", netdev->name, i);
463 else
464 memcpy(ring->name, netdev->name, IFNAMSIZ);
465 err = request_irq(adapter->msix_entries[vector].vector,
466 &igb_msix_rx, 0, ring->name,
467 &(adapter->rx_ring[i]));
468 if (err)
469 goto out;
470 ring->itr_register = E1000_EITR(0) + (vector << 2);
471 ring->itr_val = adapter->itr;
844290e5
PW		 472 /* overwrite the poll routine for MSIX, we've already done
473 * netif_napi_add */
474 ring->napi.poll = &igb_clean_rx_ring_msix;
9d5c8243
AK		 475 vector++;
476 }
477
478 err = request_irq(adapter->msix_entries[vector].vector,
479 &igb_msix_other, 0, netdev->name, netdev);
480 if (err)
481 goto out;
482
9d5c8243
AK		 483 igb_configure_msix(adapter);
484 return 0;
485out:
486 return err;
487}
488
489static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
490{
491 if (adapter->msix_entries) {
492 pci_disable_msix(adapter->pdev);
493 kfree(adapter->msix_entries);
494 adapter->msix_entries = NULL;
7dfc16fa 495 } else if (adapter->flags & IGB_FLAG_HAS_MSI)
9d5c8243
AK		 496 pci_disable_msi(adapter->pdev);
497 return;
498}
499
500
501/**
502 * igb_set_interrupt_capability - set MSI or MSI-X if supported
503 *
504 * Attempt to configure interrupts using the best available
505 * capabilities of the hardware and kernel.
506 **/
507static void igb_set_interrupt_capability(struct igb_adapter *adapter)
508{
509 int err;
510 int numvecs, i;
511
512 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
513 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
514 GFP_KERNEL);
515 if (!adapter->msix_entries)
516 goto msi_only;
517
518 for (i = 0; i < numvecs; i++)
519 adapter->msix_entries[i].entry = i;
520
521 err = pci_enable_msix(adapter->pdev,
522 adapter->msix_entries,
523 numvecs);
524 if (err == 0)
34a20e89 525 goto out;
9d5c8243
AK		 526
527 igb_reset_interrupt_capability(adapter);
528
529 /* If we can't do MSI-X, try MSI */
530msi_only:
531 adapter->num_rx_queues = 1;
661086df 532 adapter->num_tx_queues = 1;
9d5c8243 533 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 534 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 535out:
661086df 536 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 537 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
9d5c8243
AK		 538 return;
539}
540
541/**
542 * igb_request_irq - initialize interrupts
543 *
544 * Attempts to configure interrupts using the best available
545 * capabilities of the hardware and kernel.
546 **/
547static int igb_request_irq(struct igb_adapter *adapter)
548{
549 struct net_device *netdev = adapter->netdev;
550 struct e1000_hw *hw = &adapter->hw;
551 int err = 0;
552
553 if (adapter->msix_entries) {
554 err = igb_request_msix(adapter);
844290e5 555 if (!err)
9d5c8243 556 goto request_done;
9d5c8243
AK		 557 /* fall back to MSI */
558 igb_reset_interrupt_capability(adapter);
559 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 560 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 561 igb_free_all_tx_resources(adapter);
562 igb_free_all_rx_resources(adapter);
563 adapter->num_rx_queues = 1;
564 igb_alloc_queues(adapter);
844290e5 565 } else {
2d064c06
AD		 566 switch (hw->mac.type) {
567 case e1000_82575:
568 wr32(E1000_MSIXBM(0),
569 (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
570 break;
571 case e1000_82576:
572 wr32(E1000_IVAR0, E1000_IVAR_VALID);
573 break;
574 default:
575 break;
576 }
9d5c8243 577 }
844290e5 578
7dfc16fa 579 if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243
AK		 580 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
581 netdev->name, netdev);
582 if (!err)
583 goto request_done;
584 /* fall back to legacy interrupts */
585 igb_reset_interrupt_capability(adapter);
7dfc16fa 586 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 587 }
588
589 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
590 netdev->name, netdev);
591
6cb5e577 592 if (err)
9d5c8243
AK		 593 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
594 err);
9d5c8243
AK		 595
596request_done:
597 return err;
598}
599
600static void igb_free_irq(struct igb_adapter *adapter)
601{
602 struct net_device *netdev = adapter->netdev;
603
604 if (adapter->msix_entries) {
605 int vector = 0, i;
606
607 for (i = 0; i < adapter->num_tx_queues; i++)
608 free_irq(adapter->msix_entries[vector++].vector,
609 &(adapter->tx_ring[i]));
610 for (i = 0; i < adapter->num_rx_queues; i++)
611 free_irq(adapter->msix_entries[vector++].vector,
612 &(adapter->rx_ring[i]));
613
614 free_irq(adapter->msix_entries[vector++].vector, netdev);
615 return;
616 }
617
618 free_irq(adapter->pdev->irq, netdev);
619}
620
621/**
622 * igb_irq_disable - Mask off interrupt generation on the NIC
623 * @adapter: board private structure
624 **/
625static void igb_irq_disable(struct igb_adapter *adapter)
626{
627 struct e1000_hw *hw = &adapter->hw;
628
629 if (adapter->msix_entries) {
844290e5 630 wr32(E1000_EIAM, 0);
9d5c8243
AK		 631 wr32(E1000_EIMC, ~0);
632 wr32(E1000_EIAC, 0);
633 }
844290e5
PW		 634
635 wr32(E1000_IAM, 0);
9d5c8243
AK		 636 wr32(E1000_IMC, ~0);
637 wrfl();
638 synchronize_irq(adapter->pdev->irq);
639}
640
641/**
642 * igb_irq_enable - Enable default interrupt generation settings
643 * @adapter: board private structure
644 **/
645static void igb_irq_enable(struct igb_adapter *adapter)
646{
647 struct e1000_hw *hw = &adapter->hw;
648
649 if (adapter->msix_entries) {
844290e5
PW		 650 wr32(E1000_EIAC, adapter->eims_enable_mask);
651 wr32(E1000_EIAM, adapter->eims_enable_mask);
652 wr32(E1000_EIMS, adapter->eims_enable_mask);
9d5c8243 653 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5
PW		 654 } else {
655 wr32(E1000_IMS, IMS_ENABLE_MASK);
656 wr32(E1000_IAM, IMS_ENABLE_MASK);
657 }
9d5c8243
AK		 658}
659
660static void igb_update_mng_vlan(struct igb_adapter *adapter)
661{
662 struct net_device *netdev = adapter->netdev;
663 u16 vid = adapter->hw.mng_cookie.vlan_id;
664 u16 old_vid = adapter->mng_vlan_id;
665 if (adapter->vlgrp) {
666 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
667 if (adapter->hw.mng_cookie.status &
668 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
669 igb_vlan_rx_add_vid(netdev, vid);
670 adapter->mng_vlan_id = vid;
671 } else
672 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
673
674 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
675 (vid != old_vid) &&
676 !vlan_group_get_device(adapter->vlgrp, old_vid))
677 igb_vlan_rx_kill_vid(netdev, old_vid);
678 } else
679 adapter->mng_vlan_id = vid;
680 }
681}
682
683/**
684 * igb_release_hw_control - release control of the h/w to f/w
685 * @adapter: address of board private structure
686 *
687 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
688 * For ASF and Pass Through versions of f/w this means that the
689 * driver is no longer loaded.
690 *
691 **/
692static void igb_release_hw_control(struct igb_adapter *adapter)
693{
694 struct e1000_hw *hw = &adapter->hw;
695 u32 ctrl_ext;
696
697 /* Let firmware take over control of h/w */
698 ctrl_ext = rd32(E1000_CTRL_EXT);
699 wr32(E1000_CTRL_EXT,
700 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
701}
702
703
704/**
705 * igb_get_hw_control - get control of the h/w from f/w
706 * @adapter: address of board private structure
707 *
708 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
709 * For ASF and Pass Through versions of f/w this means that
710 * the driver is loaded.
711 *
712 **/
713static void igb_get_hw_control(struct igb_adapter *adapter)
714{
715 struct e1000_hw *hw = &adapter->hw;
716 u32 ctrl_ext;
717
718 /* Let firmware know the driver has taken over */
719 ctrl_ext = rd32(E1000_CTRL_EXT);
720 wr32(E1000_CTRL_EXT,
721 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
722}
723
9d5c8243
AK		 724/**
725 * igb_configure - configure the hardware for RX and TX
726 * @adapter: private board structure
727 **/
728static void igb_configure(struct igb_adapter *adapter)
729{
730 struct net_device *netdev = adapter->netdev;
731 int i;
732
733 igb_get_hw_control(adapter);
734 igb_set_multi(netdev);
735
736 igb_restore_vlan(adapter);
9d5c8243
AK		 737
738 igb_configure_tx(adapter);
739 igb_setup_rctl(adapter);
740 igb_configure_rx(adapter);
662d7205
AD		 741
742 igb_rx_fifo_flush_82575(&adapter->hw);
743
9d5c8243
AK		 744 /* call IGB_DESC_UNUSED which always leaves
745 * at least 1 descriptor unused to make sure
746 * next_to_use != next_to_clean */
747 for (i = 0; i < adapter->num_rx_queues; i++) {
748 struct igb_ring *ring = &adapter->rx_ring[i];
3b644cf6 749 igb_alloc_rx_buffers_adv(ring, IGB_DESC_UNUSED(ring));
9d5c8243
AK		 750 }
751
752
753 adapter->tx_queue_len = netdev->tx_queue_len;
754}
755
756
757/**
758 * igb_up - Open the interface and prepare it to handle traffic
759 * @adapter: board private structure
760 **/
761
762int igb_up(struct igb_adapter *adapter)
763{
764 struct e1000_hw *hw = &adapter->hw;
765 int i;
766
767 /* hardware has been reset, we need to reload some things */
768 igb_configure(adapter);
769
770 clear_bit(__IGB_DOWN, &adapter->state);
771
844290e5
PW		 772 for (i = 0; i < adapter->num_rx_queues; i++)
773 napi_enable(&adapter->rx_ring[i].napi);
774 if (adapter->msix_entries)
9d5c8243 775 igb_configure_msix(adapter);
9d5c8243
AK		 776
777 /* Clear any pending interrupts. */
778 rd32(E1000_ICR);
779 igb_irq_enable(adapter);
780
781 /* Fire a link change interrupt to start the watchdog. */
782 wr32(E1000_ICS, E1000_ICS_LSC);
783 return 0;
784}
785
786void igb_down(struct igb_adapter *adapter)
787{
788 struct e1000_hw *hw = &adapter->hw;
789 struct net_device *netdev = adapter->netdev;
790 u32 tctl, rctl;
791 int i;
792
793 /* signal that we're down so the interrupt handler does not
794 * reschedule our watchdog timer */
795 set_bit(__IGB_DOWN, &adapter->state);
796
797 /* disable receives in the hardware */
798 rctl = rd32(E1000_RCTL);
799 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
800 /* flush and sleep below */
801
fd2ea0a7 802 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 803
804 /* disable transmits in the hardware */
805 tctl = rd32(E1000_TCTL);
806 tctl &= ~E1000_TCTL_EN;
807 wr32(E1000_TCTL, tctl);
808 /* flush both disables and wait for them to finish */
809 wrfl();
810 msleep(10);
811
844290e5
PW		 812 for (i = 0; i < adapter->num_rx_queues; i++)
813 napi_disable(&adapter->rx_ring[i].napi);
9d5c8243 814
9d5c8243
AK		 815 igb_irq_disable(adapter);
816
817 del_timer_sync(&adapter->watchdog_timer);
818 del_timer_sync(&adapter->phy_info_timer);
819
820 netdev->tx_queue_len = adapter->tx_queue_len;
821 netif_carrier_off(netdev);
822 adapter->link_speed = 0;
823 adapter->link_duplex = 0;
824
3023682e
JK		 825 if (!pci_channel_offline(adapter->pdev))
826 igb_reset(adapter);
9d5c8243
AK		 827 igb_clean_all_tx_rings(adapter);
828 igb_clean_all_rx_rings(adapter);
829}
830
831void igb_reinit_locked(struct igb_adapter *adapter)
832{
833 WARN_ON(in_interrupt());
834 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
835 msleep(1);
836 igb_down(adapter);
837 igb_up(adapter);
838 clear_bit(__IGB_RESETTING, &adapter->state);
839}
840
841void igb_reset(struct igb_adapter *adapter)
842{
843 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 844 struct e1000_mac_info *mac = &hw->mac;
845 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 846 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
847 u16 hwm;
848
849 /* Repartition Pba for greater than 9k mtu
850 * To take effect CTRL.RST is required.
851 */
2d064c06 852 if (mac->type != e1000_82576) {
9d5c8243 853 pba = E1000_PBA_34K;
2d064c06
AD		 854 }
855 else {
856 pba = E1000_PBA_64K;
857 }
9d5c8243 858
2d064c06
AD		 859 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
860 (mac->type < e1000_82576)) {
9d5c8243
AK		 861 /* adjust PBA for jumbo frames */
862 wr32(E1000_PBA, pba);
863
864 /* To maintain wire speed transmits, the Tx FIFO should be
865 * large enough to accommodate two full transmit packets,
866 * rounded up to the next 1KB and expressed in KB. Likewise,
867 * the Rx FIFO should be large enough to accommodate at least
868 * one full receive packet and is similarly rounded up and
869 * expressed in KB. */
870 pba = rd32(E1000_PBA);
871 /* upper 16 bits has Tx packet buffer allocation size in KB */
872 tx_space = pba >> 16;
873 /* lower 16 bits has Rx packet buffer allocation size in KB */
874 pba &= 0xffff;
875 /* the tx fifo also stores 16 bytes of information about the tx
876 * but don't include ethernet FCS because hardware appends it */
877 min_tx_space = (adapter->max_frame_size +
878 sizeof(struct e1000_tx_desc) -
879 ETH_FCS_LEN) * 2;
880 min_tx_space = ALIGN(min_tx_space, 1024);
881 min_tx_space >>= 10;
882 /* software strips receive CRC, so leave room for it */
883 min_rx_space = adapter->max_frame_size;
884 min_rx_space = ALIGN(min_rx_space, 1024);
885 min_rx_space >>= 10;
886
887 /* If current Tx allocation is less than the min Tx FIFO size,
888 * and the min Tx FIFO size is less than the current Rx FIFO
889 * allocation, take space away from current Rx allocation */
890 if (tx_space < min_tx_space &&
891 ((min_tx_space - tx_space) < pba)) {
892 pba = pba - (min_tx_space - tx_space);
893
894 /* if short on rx space, rx wins and must trump tx
895 * adjustment */
896 if (pba < min_rx_space)
897 pba = min_rx_space;
898 }
2d064c06 899 wr32(E1000_PBA, pba);
9d5c8243 900 }
9d5c8243
AK		 901
902 /* flow control settings */
903 /* The high water mark must be low enough to fit one full frame
904 * (or the size used for early receive) above it in the Rx FIFO.
905 * Set it to the lower of:
906 * - 90% of the Rx FIFO size, or
907 * - the full Rx FIFO size minus one full frame */
908 hwm = min(((pba << 10) * 9 / 10),
2d064c06 909 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 910
2d064c06
AD		 911 if (mac->type < e1000_82576) {
912 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
913 fc->low_water = fc->high_water - 8;
914 } else {
915 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
916 fc->low_water = fc->high_water - 16;
917 }
9d5c8243
AK		 918 fc->pause_time = 0xFFFF;
919 fc->send_xon = 1;
920 fc->type = fc->original_type;
921
922 /* Allow time for pending master requests to run */
923 adapter->hw.mac.ops.reset_hw(&adapter->hw);
924 wr32(E1000_WUC, 0);
925
926 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
927 dev_err(&adapter->pdev->dev, "Hardware Error\n");
928
929 igb_update_mng_vlan(adapter);
930
931 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
932 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
933
934 igb_reset_adaptive(&adapter->hw);
f5f4cf08 935 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 936}
937
42bfd33a
TI		 938/**
939 * igb_is_need_ioport - determine if an adapter needs ioport resources or not
940 * @pdev: PCI device information struct
941 *
942 * Returns true if an adapter needs ioport resources
943 **/
944static int igb_is_need_ioport(struct pci_dev *pdev)
945{
946 switch (pdev->device) {
947 /* Currently there are no adapters that need ioport resources */
948 default:
949 return false;
950 }
951}
952
2e5c6922
SH		 953static const struct net_device_ops igb_netdev_ops = {
954 .ndo_open = igb_open,
955 .ndo_stop = igb_close,
00829823 956 .ndo_start_xmit = igb_xmit_frame_adv,
2e5c6922
SH		 957 .ndo_get_stats = igb_get_stats,
958 .ndo_set_multicast_list = igb_set_multi,
959 .ndo_set_mac_address = igb_set_mac,
960 .ndo_change_mtu = igb_change_mtu,
961 .ndo_do_ioctl = igb_ioctl,
962 .ndo_tx_timeout = igb_tx_timeout,
963 .ndo_validate_addr = eth_validate_addr,
964 .ndo_vlan_rx_register = igb_vlan_rx_register,
965 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
966 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
967#ifdef CONFIG_NET_POLL_CONTROLLER
968 .ndo_poll_controller = igb_netpoll,
969#endif
970};
971
9d5c8243
AK		 972/**
973 * igb_probe - Device Initialization Routine
974 * @pdev: PCI device information struct
975 * @ent: entry in igb_pci_tbl
976 *
977 * Returns 0 on success, negative on failure
978 *
979 * igb_probe initializes an adapter identified by a pci_dev structure.
980 * The OS initialization, configuring of the adapter private structure,
981 * and a hardware reset occur.
982 **/
983static int __devinit igb_probe(struct pci_dev *pdev,
984 const struct pci_device_id *ent)
985{
986 struct net_device *netdev;
987 struct igb_adapter *adapter;
988 struct e1000_hw *hw;
c54106bb 989 struct pci_dev *us_dev;
9d5c8243
AK		 990 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
991 unsigned long mmio_start, mmio_len;
c54106bb
AD		 992 int i, err, pci_using_dac, pos;
993 u16 eeprom_data = 0, state = 0;
9d5c8243
AK		 994 u16 eeprom_apme_mask = IGB_EEPROM_APME;
995 u32 part_num;
42bfd33a 996 int bars, need_ioport;
9d5c8243 997
42bfd33a
TI		 998 /* do not allocate ioport bars when not needed */
999 need_ioport = igb_is_need_ioport(pdev);
1000 if (need_ioport) {
1001 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
1002 err = pci_enable_device(pdev);
1003 } else {
1004 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1005 err = pci_enable_device_mem(pdev);
1006 }
9d5c8243
AK		 1007 if (err)
1008 return err;
1009
1010 pci_using_dac = 0;
1011 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
1012 if (!err) {
1013 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1014 if (!err)
1015 pci_using_dac = 1;
1016 } else {
1017 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1018 if (err) {
1019 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1020 if (err) {
1021 dev_err(&pdev->dev, "No usable DMA "
1022 "configuration, aborting\n");
1023 goto err_dma;
1024 }
1025 }
1026 }
1027
c54106bb
AD		 1028 /* 82575 requires that the pci-e link partner disable the L0s state */
1029 switch (pdev->device) {
1030 case E1000_DEV_ID_82575EB_COPPER:
1031 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1032 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1033 us_dev = pdev->bus->self;
1034 pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP);
1035 if (pos) {
1036 pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1037 &state);
1038 state &= ~PCIE_LINK_STATE_L0S;
1039 pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL,
1040 state);
ac450208
BH		 1041 dev_info(&pdev->dev,
1042 "Disabling ASPM L0s upstream switch port %s\n",
1043 pci_name(us_dev));
c54106bb
AD		 1044 }
1045 default:
1046 break;
1047 }
1048
42bfd33a 1049 err = pci_request_selected_regions(pdev, bars, igb_driver_name);
9d5c8243
AK		 1050 if (err)
1051 goto err_pci_reg;
1052
40a914fa
AD		 1053 pci_enable_pcie_error_reporting(pdev);
1054
9d5c8243 1055 pci_set_master(pdev);
c682fc23 1056 pci_save_state(pdev);
9d5c8243
AK		 1057
1058 err = -ENOMEM;
661086df 1059 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1060 if (!netdev)
1061 goto err_alloc_etherdev;
1062
1063 SET_NETDEV_DEV(netdev, &pdev->dev);
1064
1065 pci_set_drvdata(pdev, netdev);
1066 adapter = netdev_priv(netdev);
1067 adapter->netdev = netdev;
1068 adapter->pdev = pdev;
1069 hw = &adapter->hw;
1070 hw->back = adapter;
1071 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
42bfd33a
TI		 1072 adapter->bars = bars;
1073 adapter->need_ioport = need_ioport;
9d5c8243
AK		 1074
1075 mmio_start = pci_resource_start(pdev, 0);
1076 mmio_len = pci_resource_len(pdev, 0);
1077
1078 err = -EIO;
1079 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1080 if (!adapter->hw.hw_addr)
1081 goto err_ioremap;
1082
2e5c6922 1083 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1084 igb_set_ethtool_ops(netdev);
9d5c8243 1085 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1086
1087 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1088
1089 netdev->mem_start = mmio_start;
1090 netdev->mem_end = mmio_start + mmio_len;
1091
9d5c8243
AK		 1092 /* PCI config space info */
1093 hw->vendor_id = pdev->vendor;
1094 hw->device_id = pdev->device;
1095 hw->revision_id = pdev->revision;
1096 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1097 hw->subsystem_device_id = pdev->subsystem_device;
1098
1099 /* setup the private structure */
1100 hw->back = adapter;
1101 /* Copy the default MAC, PHY and NVM function pointers */
1102 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1103 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1104 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1105 /* Initialize skew-specific constants */
1106 err = ei->get_invariants(hw);
1107 if (err)
1108 goto err_hw_init;
1109
1110 err = igb_sw_init(adapter);
1111 if (err)
1112 goto err_sw_init;
1113
1114 igb_get_bus_info_pcie(hw);
1115
7dfc16fa
AD		 1116 /* set flags */
1117 switch (hw->mac.type) {
1118 case e1000_82576:
1119 case e1000_82575:
1120 adapter->flags |= IGB_FLAG_HAS_DCA;
1121 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1122 break;
1123 default:
1124 break;
1125 }
1126
9d5c8243
AK		 1127 hw->phy.autoneg_wait_to_complete = false;
1128 hw->mac.adaptive_ifs = true;
1129
1130 /* Copper options */
1131 if (hw->phy.media_type == e1000_media_type_copper) {
1132 hw->phy.mdix = AUTO_ALL_MODES;
1133 hw->phy.disable_polarity_correction = false;
1134 hw->phy.ms_type = e1000_ms_hw_default;
1135 }
1136
1137 if (igb_check_reset_block(hw))
1138 dev_info(&pdev->dev,
1139 "PHY reset is blocked due to SOL/IDER session.\n");
1140
1141 netdev->features = NETIF_F_SG |
1142 NETIF_F_HW_CSUM |
1143 NETIF_F_HW_VLAN_TX |
1144 NETIF_F_HW_VLAN_RX |
1145 NETIF_F_HW_VLAN_FILTER;
1146
1147 netdev->features |= NETIF_F_TSO;
9d5c8243 1148 netdev->features |= NETIF_F_TSO6;
48f29ffc 1149
d3352520
AD		 1150#ifdef CONFIG_IGB_LRO
1151 netdev->features |= NETIF_F_LRO;
1152#endif
1153
48f29ffc
JK		 1154 netdev->vlan_features |= NETIF_F_TSO;
1155 netdev->vlan_features |= NETIF_F_TSO6;
1156 netdev->vlan_features |= NETIF_F_HW_CSUM;
1157 netdev->vlan_features |= NETIF_F_SG;
1158
9d5c8243
AK		 1159 if (pci_using_dac)
1160 netdev->features |= NETIF_F_HIGHDMA;
1161
1162 netdev->features |= NETIF_F_LLTX;
1163 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1164
1165 /* before reading the NVM, reset the controller to put the device in a
1166 * known good starting state */
1167 hw->mac.ops.reset_hw(hw);
1168
1169 /* make sure the NVM is good */
1170 if (igb_validate_nvm_checksum(hw) < 0) {
1171 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1172 err = -EIO;
1173 goto err_eeprom;
1174 }
1175
1176 /* copy the MAC address out of the NVM */
1177 if (hw->mac.ops.read_mac_addr(hw))
1178 dev_err(&pdev->dev, "NVM Read Error\n");
1179
1180 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1181 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1182
1183 if (!is_valid_ether_addr(netdev->perm_addr)) {
1184 dev_err(&pdev->dev, "Invalid MAC Address\n");
1185 err = -EIO;
1186 goto err_eeprom;
1187 }
1188
1189 init_timer(&adapter->watchdog_timer);
1190 adapter->watchdog_timer.function = &igb_watchdog;
1191 adapter->watchdog_timer.data = (unsigned long) adapter;
1192
1193 init_timer(&adapter->phy_info_timer);
1194 adapter->phy_info_timer.function = &igb_update_phy_info;
1195 adapter->phy_info_timer.data = (unsigned long) adapter;
1196
1197 INIT_WORK(&adapter->reset_task, igb_reset_task);
1198 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1199
1200 /* Initialize link & ring properties that are user-changeable */
1201 adapter->tx_ring->count = 256;
1202 for (i = 0; i < adapter->num_tx_queues; i++)
1203 adapter->tx_ring[i].count = adapter->tx_ring->count;
1204 adapter->rx_ring->count = 256;
1205 for (i = 0; i < adapter->num_rx_queues; i++)
1206 adapter->rx_ring[i].count = adapter->rx_ring->count;
1207
1208 adapter->fc_autoneg = true;
1209 hw->mac.autoneg = true;
1210 hw->phy.autoneg_advertised = 0x2f;
1211
1212 hw->fc.original_type = e1000_fc_default;
1213 hw->fc.type = e1000_fc_default;
1214
1215 adapter->itr_setting = 3;
1216 adapter->itr = IGB_START_ITR;
1217
1218 igb_validate_mdi_setting(hw);
1219
1220 adapter->rx_csum = 1;
1221
1222 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1223 * enable the ACPI Magic Packet filter
1224 */
1225
1226 if (hw->bus.func == 0 ||
1227 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1228 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1229 &eeprom_data);
1230
1231 if (eeprom_data & eeprom_apme_mask)
1232 adapter->eeprom_wol |= E1000_WUFC_MAG;
1233
1234 /* now that we have the eeprom settings, apply the special cases where
1235 * the eeprom may be wrong or the board simply won't support wake on
1236 * lan on a particular port */
1237 switch (pdev->device) {
1238 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1239 adapter->eeprom_wol = 0;
1240 break;
1241 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1242 case E1000_DEV_ID_82576_FIBER:
1243 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1244 /* Wake events only supported on port A for dual fiber
1245 * regardless of eeprom setting */
1246 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1247 adapter->eeprom_wol = 0;
1248 break;
1249 }
1250
1251 /* initialize the wol settings based on the eeprom settings */
1252 adapter->wol = adapter->eeprom_wol;
e1b86d84 1253 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 1254
1255 /* reset the hardware with the new settings */
1256 igb_reset(adapter);
1257
1258 /* let the f/w know that the h/w is now under the control of the
1259 * driver. */
1260 igb_get_hw_control(adapter);
1261
1262 /* tell the stack to leave us alone until igb_open() is called */
1263 netif_carrier_off(netdev);
fd2ea0a7 1264 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1265
1266 strcpy(netdev->name, "eth%d");
1267 err = register_netdev(netdev);
1268 if (err)
1269 goto err_register;
1270
421e02f0 1271#ifdef CONFIG_IGB_DCA
7dfc16fa
AD		 1272 if ((adapter->flags & IGB_FLAG_HAS_DCA) &&
1273 (dca_add_requester(&pdev->dev) == 0)) {
1274 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1275 dev_info(&pdev->dev, "DCA enabled\n");
1276 /* Always use CB2 mode, difference is masked
1277 * in the CB driver. */
1278 wr32(E1000_DCA_CTRL, 2);
1279 igb_setup_dca(adapter);
1280 }
1281#endif
1282
9d5c8243
AK		 1283 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1284 /* print bus type/speed/width info */
7c510e4b 1285 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243
AK		 1286 netdev->name,
1287 ((hw->bus.speed == e1000_bus_speed_2500)
1288 ? "2.5Gb/s" : "unknown"),
1289 ((hw->bus.width == e1000_bus_width_pcie_x4)
1290 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1291 ? "Width x1" : "unknown"),
7c510e4b 1292 netdev->dev_addr);
9d5c8243
AK		 1293
1294 igb_read_part_num(hw, &part_num);
1295 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1296 (part_num >> 8), (part_num & 0xff));
1297
1298 dev_info(&pdev->dev,
1299 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1300 adapter->msix_entries ? "MSI-X" :
7dfc16fa 1301 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243
AK		 1302 adapter->num_rx_queues, adapter->num_tx_queues);
1303
9d5c8243
AK		 1304 return 0;
1305
1306err_register:
1307 igb_release_hw_control(adapter);
1308err_eeprom:
1309 if (!igb_check_reset_block(hw))
f5f4cf08 1310 igb_reset_phy(hw);
9d5c8243
AK		 1311
1312 if (hw->flash_address)
1313 iounmap(hw->flash_address);
1314
1315 igb_remove_device(hw);
a88f10ec 1316 igb_free_queues(adapter);
9d5c8243
AK		 1317err_sw_init:
1318err_hw_init:
1319 iounmap(hw->hw_addr);
1320err_ioremap:
1321 free_netdev(netdev);
1322err_alloc_etherdev:
42bfd33a 1323 pci_release_selected_regions(pdev, bars);
9d5c8243
AK		 1324err_pci_reg:
1325err_dma:
1326 pci_disable_device(pdev);
1327 return err;
1328}
1329
1330/**
1331 * igb_remove - Device Removal Routine
1332 * @pdev: PCI device information struct
1333 *
1334 * igb_remove is called by the PCI subsystem to alert the driver
1335 * that it should release a PCI device. The could be caused by a
1336 * Hot-Plug event, or because the driver is going to be removed from
1337 * memory.
1338 **/
1339static void __devexit igb_remove(struct pci_dev *pdev)
1340{
1341 struct net_device *netdev = pci_get_drvdata(pdev);
1342 struct igb_adapter *adapter = netdev_priv(netdev);
421e02f0 1343#ifdef CONFIG_IGB_DCA
fe4506b6 1344 struct e1000_hw *hw = &adapter->hw;
9280fa52 1345#endif
9d5c8243
AK		 1346
1347 /* flush_scheduled work may reschedule our watchdog task, so
1348 * explicitly disable watchdog tasks from being rescheduled */
1349 set_bit(__IGB_DOWN, &adapter->state);
1350 del_timer_sync(&adapter->watchdog_timer);
1351 del_timer_sync(&adapter->phy_info_timer);
1352
1353 flush_scheduled_work();
1354
421e02f0 1355#ifdef CONFIG_IGB_DCA
7dfc16fa 1356 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 1357 dev_info(&pdev->dev, "DCA disabled\n");
1358 dca_remove_requester(&pdev->dev);
7dfc16fa 1359 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 1360 wr32(E1000_DCA_CTRL, 1);
1361 }
1362#endif
1363
9d5c8243
AK		 1364 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1365 * would have already happened in close and is redundant. */
1366 igb_release_hw_control(adapter);
1367
1368 unregister_netdev(netdev);
1369
f5f4cf08
AD		 1370 if (!igb_check_reset_block(&adapter->hw))
1371 igb_reset_phy(&adapter->hw);
9d5c8243
AK		 1372
1373 igb_remove_device(&adapter->hw);
1374 igb_reset_interrupt_capability(adapter);
1375
a88f10ec 1376 igb_free_queues(adapter);
9d5c8243
AK		 1377
1378 iounmap(adapter->hw.hw_addr);
1379 if (adapter->hw.flash_address)
1380 iounmap(adapter->hw.flash_address);
42bfd33a 1381 pci_release_selected_regions(pdev, adapter->bars);
9d5c8243
AK		 1382
1383 free_netdev(netdev);
1384
40a914fa
AD		 1385 pci_disable_pcie_error_reporting(pdev);
1386
9d5c8243
AK		 1387 pci_disable_device(pdev);
1388}
1389
1390/**
1391 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1392 * @adapter: board private structure to initialize
1393 *
1394 * igb_sw_init initializes the Adapter private data structure.
1395 * Fields are initialized based on PCI device information and
1396 * OS network device settings (MTU size).
1397 **/
1398static int __devinit igb_sw_init(struct igb_adapter *adapter)
1399{
1400 struct e1000_hw *hw = &adapter->hw;
1401 struct net_device *netdev = adapter->netdev;
1402 struct pci_dev *pdev = adapter->pdev;
1403
1404 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1405
68fd9910
AD		 1406 adapter->tx_ring_count = IGB_DEFAULT_TXD;
1407 adapter->rx_ring_count = IGB_DEFAULT_RXD;
9d5c8243
AK		 1408 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1409 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1410 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1411 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1412
1413 /* Number of supported queues. */
1414 /* Having more queues than CPUs doesn't make sense. */
661086df 1415 adapter->num_rx_queues = min((u32)IGB_MAX_RX_QUEUES, (u32)num_online_cpus());
661086df 1416 adapter->num_tx_queues = min(IGB_MAX_TX_QUEUES, num_online_cpus());
9d5c8243 1417
661086df
PWJ		 1418 /* This call may decrease the number of queues depending on
1419 * interrupt mode. */
9d5c8243
AK		 1420 igb_set_interrupt_capability(adapter);
1421
1422 if (igb_alloc_queues(adapter)) {
1423 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1424 return -ENOMEM;
1425 }
1426
1427 /* Explicitly disable IRQ since the NIC can be in any state. */
1428 igb_irq_disable(adapter);
1429
1430 set_bit(__IGB_DOWN, &adapter->state);
1431 return 0;
1432}
1433
1434/**
1435 * igb_open - Called when a network interface is made active
1436 * @netdev: network interface device structure
1437 *
1438 * Returns 0 on success, negative value on failure
1439 *
1440 * The open entry point is called when a network interface is made
1441 * active by the system (IFF_UP). At this point all resources needed
1442 * for transmit and receive operations are allocated, the interrupt
1443 * handler is registered with the OS, the watchdog timer is started,
1444 * and the stack is notified that the interface is ready.
1445 **/
1446static int igb_open(struct net_device *netdev)
1447{
1448 struct igb_adapter *adapter = netdev_priv(netdev);
1449 struct e1000_hw *hw = &adapter->hw;
1450 int err;
1451 int i;
1452
1453 /* disallow open during test */
1454 if (test_bit(__IGB_TESTING, &adapter->state))
1455 return -EBUSY;
1456
1457 /* allocate transmit descriptors */
1458 err = igb_setup_all_tx_resources(adapter);
1459 if (err)
1460 goto err_setup_tx;
1461
1462 /* allocate receive descriptors */
1463 err = igb_setup_all_rx_resources(adapter);
1464 if (err)
1465 goto err_setup_rx;
1466
1467 /* e1000_power_up_phy(adapter); */
1468
1469 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1470 if ((adapter->hw.mng_cookie.status &
1471 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1472 igb_update_mng_vlan(adapter);
1473
1474 /* before we allocate an interrupt, we must be ready to handle it.
1475 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1476 * as soon as we call pci_request_irq, so we have to setup our
1477 * clean_rx handler before we do so. */
1478 igb_configure(adapter);
1479
1480 err = igb_request_irq(adapter);
1481 if (err)
1482 goto err_req_irq;
1483
1484 /* From here on the code is the same as igb_up() */
1485 clear_bit(__IGB_DOWN, &adapter->state);
1486
844290e5
PW		 1487 for (i = 0; i < adapter->num_rx_queues; i++)
1488 napi_enable(&adapter->rx_ring[i].napi);
9d5c8243
AK		 1489
1490 /* Clear any pending interrupts. */
1491 rd32(E1000_ICR);
844290e5
PW		 1492
1493 igb_irq_enable(adapter);
1494
d55b53ff
JK		 1495 netif_tx_start_all_queues(netdev);
1496
9d5c8243
AK		 1497 /* Fire a link status change interrupt to start the watchdog. */
1498 wr32(E1000_ICS, E1000_ICS_LSC);
1499
1500 return 0;
1501
1502err_req_irq:
1503 igb_release_hw_control(adapter);
1504 /* e1000_power_down_phy(adapter); */
1505 igb_free_all_rx_resources(adapter);
1506err_setup_rx:
1507 igb_free_all_tx_resources(adapter);
1508err_setup_tx:
1509 igb_reset(adapter);
1510
1511 return err;
1512}
1513
1514/**
1515 * igb_close - Disables a network interface
1516 * @netdev: network interface device structure
1517 *
1518 * Returns 0, this is not allowed to fail
1519 *
1520 * The close entry point is called when an interface is de-activated
1521 * by the OS. The hardware is still under the driver's control, but
1522 * needs to be disabled. A global MAC reset is issued to stop the
1523 * hardware, and all transmit and receive resources are freed.
1524 **/
1525static int igb_close(struct net_device *netdev)
1526{
1527 struct igb_adapter *adapter = netdev_priv(netdev);
1528
1529 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1530 igb_down(adapter);
1531
1532 igb_free_irq(adapter);
1533
1534 igb_free_all_tx_resources(adapter);
1535 igb_free_all_rx_resources(adapter);
1536
1537 /* kill manageability vlan ID if supported, but not if a vlan with
1538 * the same ID is registered on the host OS (let 8021q kill it) */
1539 if ((adapter->hw.mng_cookie.status &
1540 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1541 !(adapter->vlgrp &&
1542 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1543 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1544
1545 return 0;
1546}
1547
1548/**
1549 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1550 * @adapter: board private structure
1551 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1552 *
1553 * Return 0 on success, negative on failure
1554 **/
1555
1556int igb_setup_tx_resources(struct igb_adapter *adapter,
1557 struct igb_ring *tx_ring)
1558{
1559 struct pci_dev *pdev = adapter->pdev;
1560 int size;
1561
1562 size = sizeof(struct igb_buffer) * tx_ring->count;
1563 tx_ring->buffer_info = vmalloc(size);
1564 if (!tx_ring->buffer_info)
1565 goto err;
1566 memset(tx_ring->buffer_info, 0, size);
1567
1568 /* round up to nearest 4K */
1569 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1570 + sizeof(u32);
1571 tx_ring->size = ALIGN(tx_ring->size, 4096);
1572
1573 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1574 &tx_ring->dma);
1575
1576 if (!tx_ring->desc)
1577 goto err;
1578
1579 tx_ring->adapter = adapter;
1580 tx_ring->next_to_use = 0;
1581 tx_ring->next_to_clean = 0;
9d5c8243
AK		 1582 return 0;
1583
1584err:
1585 vfree(tx_ring->buffer_info);
1586 dev_err(&adapter->pdev->dev,
1587 "Unable to allocate memory for the transmit descriptor ring\n");
1588 return -ENOMEM;
1589}
1590
1591/**
1592 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1593 * (Descriptors) for all queues
1594 * @adapter: board private structure
1595 *
1596 * Return 0 on success, negative on failure
1597 **/
1598static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1599{
1600 int i, err = 0;
661086df 1601 int r_idx;
9d5c8243
AK		 1602
1603 for (i = 0; i < adapter->num_tx_queues; i++) {
1604 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1605 if (err) {
1606 dev_err(&adapter->pdev->dev,
1607 "Allocation for Tx Queue %u failed\n", i);
1608 for (i--; i >= 0; i--)
3b644cf6 1609 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 1610 break;
1611 }
1612 }
1613
661086df
PWJ		 1614 for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1615 r_idx = i % adapter->num_tx_queues;
1616 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1617 }
9d5c8243
AK		 1618 return err;
1619}
1620
1621/**
1622 * igb_configure_tx - Configure transmit Unit after Reset
1623 * @adapter: board private structure
1624 *
1625 * Configure the Tx unit of the MAC after a reset.
1626 **/
1627static void igb_configure_tx(struct igb_adapter *adapter)
1628{
1629 u64 tdba, tdwba;
1630 struct e1000_hw *hw = &adapter->hw;
1631 u32 tctl;
1632 u32 txdctl, txctrl;
1633 int i;
1634
1635 for (i = 0; i < adapter->num_tx_queues; i++) {
1636 struct igb_ring *ring = &(adapter->tx_ring[i]);
1637
1638 wr32(E1000_TDLEN(i),
1639 ring->count * sizeof(struct e1000_tx_desc));
1640 tdba = ring->dma;
1641 wr32(E1000_TDBAL(i),
1642 tdba & 0x00000000ffffffffULL);
1643 wr32(E1000_TDBAH(i), tdba >> 32);
1644
1645 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1646 tdwba |= 1; /* enable head wb */
1647 wr32(E1000_TDWBAL(i),
1648 tdwba & 0x00000000ffffffffULL);
1649 wr32(E1000_TDWBAH(i), tdwba >> 32);
1650
1651 ring->head = E1000_TDH(i);
1652 ring->tail = E1000_TDT(i);
1653 writel(0, hw->hw_addr + ring->tail);
1654 writel(0, hw->hw_addr + ring->head);
1655 txdctl = rd32(E1000_TXDCTL(i));
1656 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1657 wr32(E1000_TXDCTL(i), txdctl);
1658
1659 /* Turn off Relaxed Ordering on head write-backs. The
1660 * writebacks MUST be delivered in order or it will
1661 * completely screw up our bookeeping.
1662 */
1663 txctrl = rd32(E1000_DCA_TXCTRL(i));
1664 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1665 wr32(E1000_DCA_TXCTRL(i), txctrl);
1666 }
1667
1668
1669
1670 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1671
1672 /* Program the Transmit Control Register */
1673
1674 tctl = rd32(E1000_TCTL);
1675 tctl &= ~E1000_TCTL_CT;
1676 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1677 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1678
1679 igb_config_collision_dist(hw);
1680
1681 /* Setup Transmit Descriptor Settings for eop descriptor */
1682 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1683
1684 /* Enable transmits */
1685 tctl |= E1000_TCTL_EN;
1686
1687 wr32(E1000_TCTL, tctl);
1688}
1689
1690/**
1691 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1692 * @adapter: board private structure
1693 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1694 *
1695 * Returns 0 on success, negative on failure
1696 **/
1697
1698int igb_setup_rx_resources(struct igb_adapter *adapter,
1699 struct igb_ring *rx_ring)
1700{
1701 struct pci_dev *pdev = adapter->pdev;
1702 int size, desc_len;
1703
d3352520
AD		 1704#ifdef CONFIG_IGB_LRO
1705 size = sizeof(struct net_lro_desc) * MAX_LRO_DESCRIPTORS;
1706 rx_ring->lro_mgr.lro_arr = vmalloc(size);
1707 if (!rx_ring->lro_mgr.lro_arr)
1708 goto err;
1709 memset(rx_ring->lro_mgr.lro_arr, 0, size);
1710#endif
1711
9d5c8243
AK		 1712 size = sizeof(struct igb_buffer) * rx_ring->count;
1713 rx_ring->buffer_info = vmalloc(size);
1714 if (!rx_ring->buffer_info)
1715 goto err;
1716 memset(rx_ring->buffer_info, 0, size);
1717
1718 desc_len = sizeof(union e1000_adv_rx_desc);
1719
1720 /* Round up to nearest 4K */
1721 rx_ring->size = rx_ring->count * desc_len;
1722 rx_ring->size = ALIGN(rx_ring->size, 4096);
1723
1724 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1725 &rx_ring->dma);
1726
1727 if (!rx_ring->desc)
1728 goto err;
1729
1730 rx_ring->next_to_clean = 0;
1731 rx_ring->next_to_use = 0;
9d5c8243
AK		 1732
1733 rx_ring->adapter = adapter;
9d5c8243
AK		 1734
1735 return 0;
1736
1737err:
d3352520
AD		 1738#ifdef CONFIG_IGB_LRO
1739 vfree(rx_ring->lro_mgr.lro_arr);
1740 rx_ring->lro_mgr.lro_arr = NULL;
1741#endif
9d5c8243
AK		 1742 vfree(rx_ring->buffer_info);
1743 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1744 "the receive descriptor ring\n");
1745 return -ENOMEM;
1746}
1747
1748/**
1749 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1750 * (Descriptors) for all queues
1751 * @adapter: board private structure
1752 *
1753 * Return 0 on success, negative on failure
1754 **/
1755static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1756{
1757 int i, err = 0;
1758
1759 for (i = 0; i < adapter->num_rx_queues; i++) {
1760 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1761 if (err) {
1762 dev_err(&adapter->pdev->dev,
1763 "Allocation for Rx Queue %u failed\n", i);
1764 for (i--; i >= 0; i--)
3b644cf6 1765 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 1766 break;
1767 }
1768 }
1769
1770 return err;
1771}
1772
1773/**
1774 * igb_setup_rctl - configure the receive control registers
1775 * @adapter: Board private structure
1776 **/
1777static void igb_setup_rctl(struct igb_adapter *adapter)
1778{
1779 struct e1000_hw *hw = &adapter->hw;
1780 u32 rctl;
1781 u32 srrctl = 0;
1782 int i;
1783
1784 rctl = rd32(E1000_RCTL);
1785
1786 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 1787 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 1788
69d728ba 1789 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
9d5c8243
AK		 1790 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1791
87cb7e8c
AK		 1792 /*
1793 * enable stripping of CRC. It's unlikely this will break BMC
1794 * redirection as it did with e1000. Newer features require
1795 * that the HW strips the CRC.
9d5c8243 1796 */
87cb7e8c 1797 rctl |= E1000_RCTL_SECRC;
9d5c8243 1798
9b07f3d3
AD		 1799 /*
1800 * disable store bad packets, long packet enable, and clear size bits.
1801 */
1802 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_LPE | E1000_RCTL_SZ_256);
9d5c8243 1803
9b07f3d3 1804 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
9d5c8243 1805 /* Setup buffer sizes */
9d5c8243
AK		 1806 switch (adapter->rx_buffer_len) {
1807 case IGB_RXBUFFER_256:
1808 rctl |= E1000_RCTL_SZ_256;
9d5c8243
AK		 1809 break;
1810 case IGB_RXBUFFER_512:
1811 rctl |= E1000_RCTL_SZ_512;
9d5c8243
AK		 1812 break;
1813 case IGB_RXBUFFER_1024:
1814 rctl |= E1000_RCTL_SZ_1024;
9d5c8243 1815 break;
9d5c8243
AK		 1816 default:
1817 rctl |= E1000_RCTL_SZ_2048;
9d5c8243 1818 break;
9d5c8243
AK		 1819 }
1820 } else {
9b07f3d3 1821 rctl |= E1000_RCTL_LPE;
9d5c8243
AK		 1822 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1823 }
1824
1825 /* 82575 and greater support packet-split where the protocol
1826 * header is placed in skb->data and the packet data is
1827 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1828 * In the case of a non-split, skb->data is linearly filled,
1829 * followed by the page buffers. Therefore, skb->data is
1830 * sized to hold the largest protocol header.
1831 */
1832 /* allocations using alloc_page take too long for regular MTU
1833 * so only enable packet split for jumbo frames */
1834 if (rctl & E1000_RCTL_LPE) {
1835 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
bf36c1a0 1836 srrctl |= adapter->rx_ps_hdr_size <<
9d5c8243 1837 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
9d5c8243
AK		 1838 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1839 } else {
1840 adapter->rx_ps_hdr_size = 0;
1841 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1842 }
1843
1844 for (i = 0; i < adapter->num_rx_queues; i++)
1845 wr32(E1000_SRRCTL(i), srrctl);
1846
1847 wr32(E1000_RCTL, rctl);
1848}
1849
1850/**
1851 * igb_configure_rx - Configure receive Unit after Reset
1852 * @adapter: board private structure
1853 *
1854 * Configure the Rx unit of the MAC after a reset.
1855 **/
1856static void igb_configure_rx(struct igb_adapter *adapter)
1857{
1858 u64 rdba;
1859 struct e1000_hw *hw = &adapter->hw;
1860 u32 rctl, rxcsum;
1861 u32 rxdctl;
1862 int i;
1863
1864 /* disable receives while setting up the descriptors */
1865 rctl = rd32(E1000_RCTL);
1866 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1867 wrfl();
1868 mdelay(10);
1869
1870 if (adapter->itr_setting > 3)
6eb5a7f1 1871 wr32(E1000_ITR, adapter->itr);
9d5c8243
AK		 1872
1873 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1874 * the Base and Length of the Rx Descriptor Ring */
1875 for (i = 0; i < adapter->num_rx_queues; i++) {
1876 struct igb_ring *ring = &(adapter->rx_ring[i]);
1877 rdba = ring->dma;
1878 wr32(E1000_RDBAL(i),
1879 rdba & 0x00000000ffffffffULL);
1880 wr32(E1000_RDBAH(i), rdba >> 32);
1881 wr32(E1000_RDLEN(i),
1882 ring->count * sizeof(union e1000_adv_rx_desc));
1883
1884 ring->head = E1000_RDH(i);
1885 ring->tail = E1000_RDT(i);
1886 writel(0, hw->hw_addr + ring->tail);
1887 writel(0, hw->hw_addr + ring->head);
1888
1889 rxdctl = rd32(E1000_RXDCTL(i));
1890 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1891 rxdctl &= 0xFFF00000;
1892 rxdctl |= IGB_RX_PTHRESH;
1893 rxdctl |= IGB_RX_HTHRESH << 8;
1894 rxdctl |= IGB_RX_WTHRESH << 16;
1895 wr32(E1000_RXDCTL(i), rxdctl);
d3352520
AD		 1896#ifdef CONFIG_IGB_LRO
1897 /* Intitial LRO Settings */
1898 ring->lro_mgr.max_aggr = MAX_LRO_AGGR;
1899 ring->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1900 ring->lro_mgr.get_skb_header = igb_get_skb_hdr;
1901 ring->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1902 ring->lro_mgr.dev = adapter->netdev;
1903 ring->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1904 ring->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1905#endif
9d5c8243
AK		 1906 }
1907
1908 if (adapter->num_rx_queues > 1) {
1909 u32 random[10];
1910 u32 mrqc;
1911 u32 j, shift;
1912 union e1000_reta {
1913 u32 dword;
1914 u8 bytes[4];
1915 } reta;
1916
1917 get_random_bytes(&random[0], 40);
1918
2d064c06
AD		 1919 if (hw->mac.type >= e1000_82576)
1920 shift = 0;
1921 else
1922 shift = 6;
9d5c8243
AK		 1923 for (j = 0; j < (32 * 4); j++) {
1924 reta.bytes[j & 3] =
1925 (j % adapter->num_rx_queues) << shift;
1926 if ((j & 3) == 3)
1927 writel(reta.dword,
1928 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1929 }
1930 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1931
1932 /* Fill out hash function seeds */
1933 for (j = 0; j < 10; j++)
1934 array_wr32(E1000_RSSRK(0), j, random[j]);
1935
1936 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1937 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1938 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1939 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1940 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1941 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1942 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1943 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1944
1945
1946 wr32(E1000_MRQC, mrqc);
1947
1948 /* Multiqueue and raw packet checksumming are mutually
1949 * exclusive. Note that this not the same as TCP/IP
1950 * checksumming, which works fine. */
1951 rxcsum = rd32(E1000_RXCSUM);
1952 rxcsum |= E1000_RXCSUM_PCSD;
1953 wr32(E1000_RXCSUM, rxcsum);
1954 } else {
1955 /* Enable Receive Checksum Offload for TCP and UDP */
1956 rxcsum = rd32(E1000_RXCSUM);
1957 if (adapter->rx_csum) {
1958 rxcsum |= E1000_RXCSUM_TUOFL;
1959
1960 /* Enable IPv4 payload checksum for UDP fragments
1961 * Must be used in conjunction with packet-split. */
1962 if (adapter->rx_ps_hdr_size)
1963 rxcsum |= E1000_RXCSUM_IPPCSE;
1964 } else {
1965 rxcsum &= ~E1000_RXCSUM_TUOFL;
1966 /* don't need to clear IPPCSE as it defaults to 0 */
1967 }
1968 wr32(E1000_RXCSUM, rxcsum);
1969 }
1970
1971 if (adapter->vlgrp)
1972 wr32(E1000_RLPML,
1973 adapter->max_frame_size + VLAN_TAG_SIZE);
1974 else
1975 wr32(E1000_RLPML, adapter->max_frame_size);
1976
1977 /* Enable Receives */
1978 wr32(E1000_RCTL, rctl);
1979}
1980
1981/**
1982 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 1983 * @tx_ring: Tx descriptor ring for a specific queue
1984 *
1985 * Free all transmit software resources
1986 **/
68fd9910 1987void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 1988{
3b644cf6 1989 struct pci_dev *pdev = tx_ring->adapter->pdev;
9d5c8243 1990
3b644cf6 1991 igb_clean_tx_ring(tx_ring);
9d5c8243
AK		 1992
1993 vfree(tx_ring->buffer_info);
1994 tx_ring->buffer_info = NULL;
1995
1996 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1997
1998 tx_ring->desc = NULL;
1999}
2000
2001/**
2002 * igb_free_all_tx_resources - Free Tx Resources for All Queues
2003 * @adapter: board private structure
2004 *
2005 * Free all transmit software resources
2006 **/
2007static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2008{
2009 int i;
2010
2011 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2012 igb_free_tx_resources(&adapter->tx_ring[i]);
9d5c8243
AK		 2013}
2014
2015static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2016 struct igb_buffer *buffer_info)
2017{
2018 if (buffer_info->dma) {
2019 pci_unmap_page(adapter->pdev,
2020 buffer_info->dma,
2021 buffer_info->length,
2022 PCI_DMA_TODEVICE);
2023 buffer_info->dma = 0;
2024 }
2025 if (buffer_info->skb) {
2026 dev_kfree_skb_any(buffer_info->skb);
2027 buffer_info->skb = NULL;
2028 }
2029 buffer_info->time_stamp = 0;
2030 /* buffer_info must be completely set up in the transmit path */
2031}
2032
2033/**
2034 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 2035 * @tx_ring: ring to be cleaned
2036 **/
3b644cf6 2037static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 2038{
3b644cf6 2039 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243
AK		 2040 struct igb_buffer *buffer_info;
2041 unsigned long size;
2042 unsigned int i;
2043
2044 if (!tx_ring->buffer_info)
2045 return;
2046 /* Free all the Tx ring sk_buffs */
2047
2048 for (i = 0; i < tx_ring->count; i++) {
2049 buffer_info = &tx_ring->buffer_info[i];
2050 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2051 }
2052
2053 size = sizeof(struct igb_buffer) * tx_ring->count;
2054 memset(tx_ring->buffer_info, 0, size);
2055
2056 /* Zero out the descriptor ring */
2057
2058 memset(tx_ring->desc, 0, tx_ring->size);
2059
2060 tx_ring->next_to_use = 0;
2061 tx_ring->next_to_clean = 0;
2062
2063 writel(0, adapter->hw.hw_addr + tx_ring->head);
2064 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2065}
2066
2067/**
2068 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2069 * @adapter: board private structure
2070 **/
2071static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2072{
2073 int i;
2074
2075 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 2076 igb_clean_tx_ring(&adapter->tx_ring[i]);
9d5c8243
AK		 2077}
2078
2079/**
2080 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 2081 * @rx_ring: ring to clean the resources from
2082 *
2083 * Free all receive software resources
2084 **/
68fd9910 2085void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2086{
3b644cf6 2087 struct pci_dev *pdev = rx_ring->adapter->pdev;
9d5c8243 2088
3b644cf6 2089 igb_clean_rx_ring(rx_ring);
9d5c8243
AK		 2090
2091 vfree(rx_ring->buffer_info);
2092 rx_ring->buffer_info = NULL;
2093
d3352520
AD		 2094#ifdef CONFIG_IGB_LRO
2095 vfree(rx_ring->lro_mgr.lro_arr);
2096 rx_ring->lro_mgr.lro_arr = NULL;
2097#endif
2098
9d5c8243
AK		 2099 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2100
2101 rx_ring->desc = NULL;
2102}
2103
2104/**
2105 * igb_free_all_rx_resources - Free Rx Resources for All Queues
2106 * @adapter: board private structure
2107 *
2108 * Free all receive software resources
2109 **/
2110static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2111{
2112 int i;
2113
2114 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2115 igb_free_rx_resources(&adapter->rx_ring[i]);
9d5c8243
AK		 2116}
2117
2118/**
2119 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 2120 * @rx_ring: ring to free buffers from
2121 **/
3b644cf6 2122static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 2123{
3b644cf6 2124 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 2125 struct igb_buffer *buffer_info;
2126 struct pci_dev *pdev = adapter->pdev;
2127 unsigned long size;
2128 unsigned int i;
2129
2130 if (!rx_ring->buffer_info)
2131 return;
2132 /* Free all the Rx ring sk_buffs */
2133 for (i = 0; i < rx_ring->count; i++) {
2134 buffer_info = &rx_ring->buffer_info[i];
2135 if (buffer_info->dma) {
2136 if (adapter->rx_ps_hdr_size)
2137 pci_unmap_single(pdev, buffer_info->dma,
2138 adapter->rx_ps_hdr_size,
2139 PCI_DMA_FROMDEVICE);
2140 else
2141 pci_unmap_single(pdev, buffer_info->dma,
2142 adapter->rx_buffer_len,
2143 PCI_DMA_FROMDEVICE);
2144 buffer_info->dma = 0;
2145 }
2146
2147 if (buffer_info->skb) {
2148 dev_kfree_skb(buffer_info->skb);
2149 buffer_info->skb = NULL;
2150 }
2151 if (buffer_info->page) {
bf36c1a0
AD		 2152 if (buffer_info->page_dma)
2153 pci_unmap_page(pdev, buffer_info->page_dma,
2154 PAGE_SIZE / 2,
2155 PCI_DMA_FROMDEVICE);
9d5c8243
AK		 2156 put_page(buffer_info->page);
2157 buffer_info->page = NULL;
2158 buffer_info->page_dma = 0;
bf36c1a0 2159 buffer_info->page_offset = 0;
9d5c8243
AK		 2160 }
2161 }
2162
9d5c8243
AK		 2163 size = sizeof(struct igb_buffer) * rx_ring->count;
2164 memset(rx_ring->buffer_info, 0, size);
2165
2166 /* Zero out the descriptor ring */
2167 memset(rx_ring->desc, 0, rx_ring->size);
2168
2169 rx_ring->next_to_clean = 0;
2170 rx_ring->next_to_use = 0;
2171
2172 writel(0, adapter->hw.hw_addr + rx_ring->head);
2173 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2174}
2175
2176/**
2177 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2178 * @adapter: board private structure
2179 **/
2180static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2181{
2182 int i;
2183
2184 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 2185 igb_clean_rx_ring(&adapter->rx_ring[i]);
9d5c8243
AK		 2186}
2187
2188/**
2189 * igb_set_mac - Change the Ethernet Address of the NIC
2190 * @netdev: network interface device structure
2191 * @p: pointer to an address structure
2192 *
2193 * Returns 0 on success, negative on failure
2194 **/
2195static int igb_set_mac(struct net_device *netdev, void *p)
2196{
2197 struct igb_adapter *adapter = netdev_priv(netdev);
2198 struct sockaddr *addr = p;
2199
2200 if (!is_valid_ether_addr(addr->sa_data))
2201 return -EADDRNOTAVAIL;
2202
2203 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2204 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2205
2206 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2207
2208 return 0;
2209}
2210
2211/**
2212 * igb_set_multi - Multicast and Promiscuous mode set
2213 * @netdev: network interface device structure
2214 *
2215 * The set_multi entry point is called whenever the multicast address
2216 * list or the network interface flags are updated. This routine is
2217 * responsible for configuring the hardware for proper multicast,
2218 * promiscuous mode, and all-multi behavior.
2219 **/
2220static void igb_set_multi(struct net_device *netdev)
2221{
2222 struct igb_adapter *adapter = netdev_priv(netdev);
2223 struct e1000_hw *hw = &adapter->hw;
2224 struct e1000_mac_info *mac = &hw->mac;
2225 struct dev_mc_list *mc_ptr;
2226 u8 *mta_list;
2227 u32 rctl;
2228 int i;
2229
2230 /* Check for Promiscuous and All Multicast modes */
2231
2232 rctl = rd32(E1000_RCTL);
2233
746b9f02 2234 if (netdev->flags & IFF_PROMISC) {
9d5c8243 2235 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
746b9f02
PM		 2236 rctl &= ~E1000_RCTL_VFE;
2237 } else {
2238 if (netdev->flags & IFF_ALLMULTI) {
2239 rctl |= E1000_RCTL_MPE;
2240 rctl &= ~E1000_RCTL_UPE;
2241 } else
2242 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
78ed11a5 2243 rctl |= E1000_RCTL_VFE;
746b9f02 2244 }
9d5c8243
AK		 2245 wr32(E1000_RCTL, rctl);
2246
2247 if (!netdev->mc_count) {
2248 /* nothing to program, so clear mc list */
2d064c06 2249 igb_update_mc_addr_list_82575(hw, NULL, 0, 1,
9d5c8243
AK		 2250 mac->rar_entry_count);
2251 return;
2252 }
2253
2254 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2255 if (!mta_list)
2256 return;
2257
2258 /* The shared function expects a packed array of only addresses. */
2259 mc_ptr = netdev->mc_list;
2260
2261 for (i = 0; i < netdev->mc_count; i++) {
2262 if (!mc_ptr)
2263 break;
2264 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2265 mc_ptr = mc_ptr->next;
2266 }
2d064c06
AD		 2267 igb_update_mc_addr_list_82575(hw, mta_list, i, 1,
2268 mac->rar_entry_count);
9d5c8243
AK		 2269 kfree(mta_list);
2270}
2271
2272/* Need to wait a few seconds after link up to get diagnostic information from
2273 * the phy */
2274static void igb_update_phy_info(unsigned long data)
2275{
2276 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 2277 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 2278}
2279
2280/**
2281 * igb_watchdog - Timer Call-back
2282 * @data: pointer to adapter cast into an unsigned long
2283 **/
2284static void igb_watchdog(unsigned long data)
2285{
2286 struct igb_adapter *adapter = (struct igb_adapter *)data;
2287 /* Do the rest outside of interrupt context */
2288 schedule_work(&adapter->watchdog_task);
2289}
2290
2291static void igb_watchdog_task(struct work_struct *work)
2292{
2293 struct igb_adapter *adapter = container_of(work,
2294 struct igb_adapter, watchdog_task);
2295 struct e1000_hw *hw = &adapter->hw;
2296
2297 struct net_device *netdev = adapter->netdev;
2298 struct igb_ring *tx_ring = adapter->tx_ring;
2299 struct e1000_mac_info *mac = &adapter->hw.mac;
2300 u32 link;
7a6ea550 2301 u32 eics = 0;
9d5c8243 2302 s32 ret_val;
7a6ea550 2303 int i;
9d5c8243
AK		 2304
2305 if ((netif_carrier_ok(netdev)) &&
2306 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2307 goto link_up;
2308
2309 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2310 if ((ret_val == E1000_ERR_PHY) &&
2311 (hw->phy.type == e1000_phy_igp_3) &&
2312 (rd32(E1000_CTRL) &
2313 E1000_PHY_CTRL_GBE_DISABLE))
2314 dev_info(&adapter->pdev->dev,
2315 "Gigabit has been disabled, downgrading speed\n");
2316
2317 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2318 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2319 link = mac->serdes_has_link;
2320 else
2321 link = rd32(E1000_STATUS) &
2322 E1000_STATUS_LU;
2323
2324 if (link) {
2325 if (!netif_carrier_ok(netdev)) {
2326 u32 ctrl;
2327 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2328 &adapter->link_speed,
2329 &adapter->link_duplex);
2330
2331 ctrl = rd32(E1000_CTRL);
527d47c1
AD		 2332 /* Links status message must follow this format */
2333 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
9d5c8243 2334 "Flow Control: %s\n",
527d47c1 2335 netdev->name,
9d5c8243
AK		 2336 adapter->link_speed,
2337 adapter->link_duplex == FULL_DUPLEX ?
2338 "Full Duplex" : "Half Duplex",
2339 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2340 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2341 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2342 E1000_CTRL_TFCE) ? "TX" : "None")));
2343
2344 /* tweak tx_queue_len according to speed/duplex and
2345 * adjust the timeout factor */
2346 netdev->tx_queue_len = adapter->tx_queue_len;
2347 adapter->tx_timeout_factor = 1;
2348 switch (adapter->link_speed) {
2349 case SPEED_10:
2350 netdev->tx_queue_len = 10;
2351 adapter->tx_timeout_factor = 14;
2352 break;
2353 case SPEED_100:
2354 netdev->tx_queue_len = 100;
2355 /* maybe add some timeout factor ? */
2356 break;
2357 }
2358
2359 netif_carrier_on(netdev);
fd2ea0a7 2360 netif_tx_wake_all_queues(netdev);
9d5c8243
AK		 2361
2362 if (!test_bit(__IGB_DOWN, &adapter->state))
2363 mod_timer(&adapter->phy_info_timer,
2364 round_jiffies(jiffies + 2 * HZ));
2365 }
2366 } else {
2367 if (netif_carrier_ok(netdev)) {
2368 adapter->link_speed = 0;
2369 adapter->link_duplex = 0;
527d47c1
AD		 2370 /* Links status message must follow this format */
2371 printk(KERN_INFO "igb: %s NIC Link is Down\n",
2372 netdev->name);
9d5c8243 2373 netif_carrier_off(netdev);
fd2ea0a7 2374 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 2375 if (!test_bit(__IGB_DOWN, &adapter->state))
2376 mod_timer(&adapter->phy_info_timer,
2377 round_jiffies(jiffies + 2 * HZ));
2378 }
2379 }
2380
2381link_up:
2382 igb_update_stats(adapter);
2383
2384 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2385 adapter->tpt_old = adapter->stats.tpt;
2386 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2387 adapter->colc_old = adapter->stats.colc;
2388
2389 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2390 adapter->gorc_old = adapter->stats.gorc;
2391 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2392 adapter->gotc_old = adapter->stats.gotc;
2393
2394 igb_update_adaptive(&adapter->hw);
2395
2396 if (!netif_carrier_ok(netdev)) {
2397 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2398 /* We've lost link, so the controller stops DMA,
2399 * but we've got queued Tx work that's never going
2400 * to get done, so reset controller to flush Tx.
2401 * (Do the reset outside of interrupt context). */
2402 adapter->tx_timeout_count++;
2403 schedule_work(&adapter->reset_task);
2404 }
2405 }
2406
2407 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550
AD		 2408 if (adapter->msix_entries) {
2409 for (i = 0; i < adapter->num_rx_queues; i++)
2410 eics |= adapter->rx_ring[i].eims_value;
2411 wr32(E1000_EICS, eics);
2412 } else {
2413 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2414 }
9d5c8243
AK		 2415
2416 /* Force detection of hung controller every watchdog period */
2417 tx_ring->detect_tx_hung = true;
2418
2419 /* Reset the timer */
2420 if (!test_bit(__IGB_DOWN, &adapter->state))
2421 mod_timer(&adapter->watchdog_timer,
2422 round_jiffies(jiffies + 2 * HZ));
2423}
2424
2425enum latency_range {
2426 lowest_latency = 0,
2427 low_latency = 1,
2428 bulk_latency = 2,
2429 latency_invalid = 255
2430};
2431
2432
6eb5a7f1
AD		 2433/**
2434 * igb_update_ring_itr - update the dynamic ITR value based on packet size
2435 *
2436 * Stores a new ITR value based on strictly on packet size. This
2437 * algorithm is less sophisticated than that used in igb_update_itr,
2438 * due to the difficulty of synchronizing statistics across multiple
2439 * receive rings. The divisors and thresholds used by this fuction
2440 * were determined based on theoretical maximum wire speed and testing
2441 * data, in order to minimize response time while increasing bulk
2442 * throughput.
2443 * This functionality is controlled by the InterruptThrottleRate module
2444 * parameter (see igb_param.c)
2445 * NOTE: This function is called only when operating in a multiqueue
2446 * receive environment.
2447 * @rx_ring: pointer to ring
2448 **/
2449static void igb_update_ring_itr(struct igb_ring *rx_ring)
9d5c8243 2450{
6eb5a7f1
AD		 2451 int new_val = rx_ring->itr_val;
2452 int avg_wire_size = 0;
2453 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 2454
6eb5a7f1
AD		 2455 if (!rx_ring->total_packets)
2456 goto clear_counts; /* no packets, so don't do anything */
9d5c8243 2457
6eb5a7f1
AD		 2458 /* For non-gigabit speeds, just fix the interrupt rate at 4000
2459 * ints/sec - ITR timer value of 120 ticks.
2460 */
2461 if (adapter->link_speed != SPEED_1000) {
2462 new_val = 120;
2463 goto set_itr_val;
9d5c8243 2464 }
6eb5a7f1 2465 avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
9d5c8243 2466
6eb5a7f1
AD		 2467 /* Add 24 bytes to size to account for CRC, preamble, and gap */
2468 avg_wire_size += 24;
2469
2470 /* Don't starve jumbo frames */
2471 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 2472
6eb5a7f1
AD		 2473 /* Give a little boost to mid-size frames */
2474 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2475 new_val = avg_wire_size / 3;
2476 else
2477 new_val = avg_wire_size / 2;
9d5c8243 2478
6eb5a7f1 2479set_itr_val:
9d5c8243
AK		 2480 if (new_val != rx_ring->itr_val) {
2481 rx_ring->itr_val = new_val;
6eb5a7f1 2482 rx_ring->set_itr = 1;
9d5c8243 2483 }
6eb5a7f1
AD		 2484clear_counts:
2485 rx_ring->total_bytes = 0;
2486 rx_ring->total_packets = 0;
9d5c8243
AK		 2487}
2488
2489/**
2490 * igb_update_itr - update the dynamic ITR value based on statistics
2491 * Stores a new ITR value based on packets and byte
2492 * counts during the last interrupt. The advantage of per interrupt
2493 * computation is faster updates and more accurate ITR for the current
2494 * traffic pattern. Constants in this function were computed
2495 * based on theoretical maximum wire speed and thresholds were set based
2496 * on testing data as well as attempting to minimize response time
2497 * while increasing bulk throughput.
2498 * this functionality is controlled by the InterruptThrottleRate module
2499 * parameter (see igb_param.c)
2500 * NOTE: These calculations are only valid when operating in a single-
2501 * queue environment.
2502 * @adapter: pointer to adapter
2503 * @itr_setting: current adapter->itr
2504 * @packets: the number of packets during this measurement interval
2505 * @bytes: the number of bytes during this measurement interval
2506 **/
2507static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2508 int packets, int bytes)
2509{
2510 unsigned int retval = itr_setting;
2511
2512 if (packets == 0)
2513 goto update_itr_done;
2514
2515 switch (itr_setting) {
2516 case lowest_latency:
2517 /* handle TSO and jumbo frames */
2518 if (bytes/packets > 8000)
2519 retval = bulk_latency;
2520 else if ((packets < 5) && (bytes > 512))
2521 retval = low_latency;
2522 break;
2523 case low_latency: /* 50 usec aka 20000 ints/s */
2524 if (bytes > 10000) {
2525 /* this if handles the TSO accounting */
2526 if (bytes/packets > 8000) {
2527 retval = bulk_latency;
2528 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2529 retval = bulk_latency;
2530 } else if ((packets > 35)) {
2531 retval = lowest_latency;
2532 }
2533 } else if (bytes/packets > 2000) {
2534 retval = bulk_latency;
2535 } else if (packets <= 2 && bytes < 512) {
2536 retval = lowest_latency;
2537 }
2538 break;
2539 case bulk_latency: /* 250 usec aka 4000 ints/s */
2540 if (bytes > 25000) {
2541 if (packets > 35)
2542 retval = low_latency;
2543 } else if (bytes < 6000) {
2544 retval = low_latency;
2545 }
2546 break;
2547 }
2548
2549update_itr_done:
2550 return retval;
2551}
2552
6eb5a7f1 2553static void igb_set_itr(struct igb_adapter *adapter)
9d5c8243
AK		 2554{
2555 u16 current_itr;
2556 u32 new_itr = adapter->itr;
2557
2558 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2559 if (adapter->link_speed != SPEED_1000) {
2560 current_itr = 0;
2561 new_itr = 4000;
2562 goto set_itr_now;
2563 }
2564
2565 adapter->rx_itr = igb_update_itr(adapter,
2566 adapter->rx_itr,
2567 adapter->rx_ring->total_packets,
2568 adapter->rx_ring->total_bytes);
9d5c8243 2569
6eb5a7f1 2570 if (adapter->rx_ring->buddy) {
9d5c8243
AK		 2571 adapter->tx_itr = igb_update_itr(adapter,
2572 adapter->tx_itr,
2573 adapter->tx_ring->total_packets,
2574 adapter->tx_ring->total_bytes);
9d5c8243
AK		 2575
2576 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2577 } else {
2578 current_itr = adapter->rx_itr;
2579 }
2580
6eb5a7f1
AD		 2581 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2582 if (adapter->itr_setting == 3 &&
2583 current_itr == lowest_latency)
2584 current_itr = low_latency;
2585
9d5c8243
AK		 2586 switch (current_itr) {
2587 /* counts and packets in update_itr are dependent on these numbers */
2588 case lowest_latency:
2589 new_itr = 70000;
2590 break;
2591 case low_latency:
2592 new_itr = 20000; /* aka hwitr = ~200 */
2593 break;
2594 case bulk_latency:
2595 new_itr = 4000;
2596 break;
2597 default:
2598 break;
2599 }
2600
2601set_itr_now:
6eb5a7f1
AD		 2602 adapter->rx_ring->total_bytes = 0;
2603 adapter->rx_ring->total_packets = 0;
2604 if (adapter->rx_ring->buddy) {
2605 adapter->rx_ring->buddy->total_bytes = 0;
2606 adapter->rx_ring->buddy->total_packets = 0;
2607 }
2608
9d5c8243
AK		 2609 if (new_itr != adapter->itr) {
2610 /* this attempts to bias the interrupt rate towards Bulk
2611 * by adding intermediate steps when interrupt rate is
2612 * increasing */
2613 new_itr = new_itr > adapter->itr ?
2614 min(adapter->itr + (new_itr >> 2), new_itr) :
2615 new_itr;
2616 /* Don't write the value here; it resets the adapter's
2617 * internal timer, and causes us to delay far longer than
2618 * we should between interrupts. Instead, we write the ITR
2619 * value at the beginning of the next interrupt so the timing
2620 * ends up being correct.
2621 */
2622 adapter->itr = new_itr;
6eb5a7f1
AD		 2623 adapter->rx_ring->itr_val = 1000000000 / (new_itr * 256);
2624 adapter->rx_ring->set_itr = 1;
9d5c8243
AK		 2625 }
2626
2627 return;
2628}
2629
2630
2631#define IGB_TX_FLAGS_CSUM 0x00000001
2632#define IGB_TX_FLAGS_VLAN 0x00000002
2633#define IGB_TX_FLAGS_TSO 0x00000004
2634#define IGB_TX_FLAGS_IPV4 0x00000008
2635#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2636#define IGB_TX_FLAGS_VLAN_SHIFT 16
2637
2638static inline int igb_tso_adv(struct igb_adapter *adapter,
2639 struct igb_ring *tx_ring,
2640 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2641{
2642 struct e1000_adv_tx_context_desc *context_desc;
2643 unsigned int i;
2644 int err;
2645 struct igb_buffer *buffer_info;
2646 u32 info = 0, tu_cmd = 0;
2647 u32 mss_l4len_idx, l4len;
2648 *hdr_len = 0;
2649
2650 if (skb_header_cloned(skb)) {
2651 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2652 if (err)
2653 return err;
2654 }
2655
2656 l4len = tcp_hdrlen(skb);
2657 *hdr_len += l4len;
2658
2659 if (skb->protocol == htons(ETH_P_IP)) {
2660 struct iphdr *iph = ip_hdr(skb);
2661 iph->tot_len = 0;
2662 iph->check = 0;
2663 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2664 iph->daddr, 0,
2665 IPPROTO_TCP,
2666 0);
2667 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2668 ipv6_hdr(skb)->payload_len = 0;
2669 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2670 &ipv6_hdr(skb)->daddr,
2671 0, IPPROTO_TCP, 0);
2672 }
2673
2674 i = tx_ring->next_to_use;
2675
2676 buffer_info = &tx_ring->buffer_info[i];
2677 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2678 /* VLAN MACLEN IPLEN */
2679 if (tx_flags & IGB_TX_FLAGS_VLAN)
2680 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2681 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2682 *hdr_len += skb_network_offset(skb);
2683 info |= skb_network_header_len(skb);
2684 *hdr_len += skb_network_header_len(skb);
2685 context_desc->vlan_macip_lens = cpu_to_le32(info);
2686
2687 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2688 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2689
2690 if (skb->protocol == htons(ETH_P_IP))
2691 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2692 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2693
2694 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2695
2696 /* MSS L4LEN IDX */
2697 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2698 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2699
7dfc16fa
AD		 2700 /* Context index must be unique per ring. */
2701 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2702 mss_l4len_idx |= tx_ring->queue_index << 4;
9d5c8243
AK		 2703
2704 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2705 context_desc->seqnum_seed = 0;
2706
2707 buffer_info->time_stamp = jiffies;
2708 buffer_info->dma = 0;
2709 i++;
2710 if (i == tx_ring->count)
2711 i = 0;
2712
2713 tx_ring->next_to_use = i;
2714
2715 return true;
2716}
2717
2718static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2719 struct igb_ring *tx_ring,
2720 struct sk_buff *skb, u32 tx_flags)
2721{
2722 struct e1000_adv_tx_context_desc *context_desc;
2723 unsigned int i;
2724 struct igb_buffer *buffer_info;
2725 u32 info = 0, tu_cmd = 0;
2726
2727 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2728 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2729 i = tx_ring->next_to_use;
2730 buffer_info = &tx_ring->buffer_info[i];
2731 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2732
2733 if (tx_flags & IGB_TX_FLAGS_VLAN)
2734 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2735 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2736 if (skb->ip_summed == CHECKSUM_PARTIAL)
2737 info |= skb_network_header_len(skb);
2738
2739 context_desc->vlan_macip_lens = cpu_to_le32(info);
2740
2741 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2742
2743 if (skb->ip_summed == CHECKSUM_PARTIAL) {
44b0cda3
MW		 2744 switch (skb->protocol) {
2745 case __constant_htons(ETH_P_IP):
9d5c8243 2746 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
44b0cda3
MW		 2747 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2748 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2749 break;
2750 case __constant_htons(ETH_P_IPV6):
2751 /* XXX what about other V6 headers?? */
2752 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
2753 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2754 break;
2755 default:
2756 if (unlikely(net_ratelimit()))
2757 dev_warn(&adapter->pdev->dev,
2758 "partial checksum but proto=%x!\n",
2759 skb->protocol);
2760 break;
2761 }
9d5c8243
AK		 2762 }
2763
2764 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2765 context_desc->seqnum_seed = 0;
7dfc16fa
AD		 2766 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
2767 context_desc->mss_l4len_idx =
2768 cpu_to_le32(tx_ring->queue_index << 4);
9d5c8243
AK		 2769
2770 buffer_info->time_stamp = jiffies;
2771 buffer_info->dma = 0;
2772
2773 i++;
2774 if (i == tx_ring->count)
2775 i = 0;
2776 tx_ring->next_to_use = i;
2777
2778 return true;
2779 }
2780
2781
2782 return false;
2783}
2784
2785#define IGB_MAX_TXD_PWR 16
2786#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2787
2788static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2789 struct igb_ring *tx_ring,
2790 struct sk_buff *skb)
2791{
2792 struct igb_buffer *buffer_info;
2793 unsigned int len = skb_headlen(skb);
2794 unsigned int count = 0, i;
2795 unsigned int f;
2796
2797 i = tx_ring->next_to_use;
2798
2799 buffer_info = &tx_ring->buffer_info[i];
2800 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2801 buffer_info->length = len;
2802 /* set time_stamp *before* dma to help avoid a possible race */
2803 buffer_info->time_stamp = jiffies;
2804 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2805 PCI_DMA_TODEVICE);
2806 count++;
2807 i++;
2808 if (i == tx_ring->count)
2809 i = 0;
2810
2811 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2812 struct skb_frag_struct *frag;
2813
2814 frag = &skb_shinfo(skb)->frags[f];
2815 len = frag->size;
2816
2817 buffer_info = &tx_ring->buffer_info[i];
2818 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2819 buffer_info->length = len;
2820 buffer_info->time_stamp = jiffies;
2821 buffer_info->dma = pci_map_page(adapter->pdev,
2822 frag->page,
2823 frag->page_offset,
2824 len,
2825 PCI_DMA_TODEVICE);
2826
2827 count++;
2828 i++;
2829 if (i == tx_ring->count)
2830 i = 0;
2831 }
2832
2833 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2834 tx_ring->buffer_info[i].skb = skb;
2835
2836 return count;
2837}
2838
2839static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2840 struct igb_ring *tx_ring,
2841 int tx_flags, int count, u32 paylen,
2842 u8 hdr_len)
2843{
2844 union e1000_adv_tx_desc *tx_desc = NULL;
2845 struct igb_buffer *buffer_info;
2846 u32 olinfo_status = 0, cmd_type_len;
2847 unsigned int i;
2848
2849 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2850 E1000_ADVTXD_DCMD_DEXT);
2851
2852 if (tx_flags & IGB_TX_FLAGS_VLAN)
2853 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2854
2855 if (tx_flags & IGB_TX_FLAGS_TSO) {
2856 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2857
2858 /* insert tcp checksum */
2859 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2860
2861 /* insert ip checksum */
2862 if (tx_flags & IGB_TX_FLAGS_IPV4)
2863 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2864
2865 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2866 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2867 }
2868
7dfc16fa
AD		 2869 if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
2870 (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2871 IGB_TX_FLAGS_VLAN)))
661086df 2872 olinfo_status |= tx_ring->queue_index << 4;
9d5c8243
AK		 2873
2874 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2875
2876 i = tx_ring->next_to_use;
2877 while (count--) {
2878 buffer_info = &tx_ring->buffer_info[i];
2879 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2880 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2881 tx_desc->read.cmd_type_len =
2882 cpu_to_le32(cmd_type_len | buffer_info->length);
2883 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2884 i++;
2885 if (i == tx_ring->count)
2886 i = 0;
2887 }
2888
2889 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2890 /* Force memory writes to complete before letting h/w
2891 * know there are new descriptors to fetch. (Only
2892 * applicable for weak-ordered memory model archs,
2893 * such as IA-64). */
2894 wmb();
2895
2896 tx_ring->next_to_use = i;
2897 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2898 /* we need this if more than one processor can write to our tail
2899 * at a time, it syncronizes IO on IA64/Altix systems */
2900 mmiowb();
2901}
2902
2903static int __igb_maybe_stop_tx(struct net_device *netdev,
2904 struct igb_ring *tx_ring, int size)
2905{
2906 struct igb_adapter *adapter = netdev_priv(netdev);
2907
661086df 2908 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 2909
9d5c8243
AK		 2910 /* Herbert's original patch had:
2911 * smp_mb__after_netif_stop_queue();
2912 * but since that doesn't exist yet, just open code it. */
2913 smp_mb();
2914
2915 /* We need to check again in a case another CPU has just
2916 * made room available. */
2917 if (IGB_DESC_UNUSED(tx_ring) < size)
2918 return -EBUSY;
2919
2920 /* A reprieve! */
661086df 2921 netif_wake_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 2922 ++adapter->restart_queue;
2923 return 0;
2924}
2925
2926static int igb_maybe_stop_tx(struct net_device *netdev,
2927 struct igb_ring *tx_ring, int size)
2928{
2929 if (IGB_DESC_UNUSED(tx_ring) >= size)
2930 return 0;
2931 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2932}
2933
2934#define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2935
2936static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2937 struct net_device *netdev,
2938 struct igb_ring *tx_ring)
2939{
2940 struct igb_adapter *adapter = netdev_priv(netdev);
2941 unsigned int tx_flags = 0;
2942 unsigned int len;
9d5c8243
AK		 2943 u8 hdr_len = 0;
2944 int tso = 0;
2945
2946 len = skb_headlen(skb);
2947
2948 if (test_bit(__IGB_DOWN, &adapter->state)) {
2949 dev_kfree_skb_any(skb);
2950 return NETDEV_TX_OK;
2951 }
2952
2953 if (skb->len <= 0) {
2954 dev_kfree_skb_any(skb);
2955 return NETDEV_TX_OK;
2956 }
2957
9d5c8243
AK		 2958 /* need: 1 descriptor per page,
2959 * + 2 desc gap to keep tail from touching head,
2960 * + 1 desc for skb->data,
2961 * + 1 desc for context descriptor,
2962 * otherwise try next time */
2963 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2964 /* this is a hard error */
9d5c8243
AK		 2965 return NETDEV_TX_BUSY;
2966 }
6eb5a7f1 2967 skb_orphan(skb);
9d5c8243
AK		 2968
2969 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2970 tx_flags |= IGB_TX_FLAGS_VLAN;
2971 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2972 }
2973
661086df
PWJ		 2974 if (skb->protocol == htons(ETH_P_IP))
2975 tx_flags |= IGB_TX_FLAGS_IPV4;
2976
9d5c8243
AK		 2977 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2978 &hdr_len) : 0;
2979
2980 if (tso < 0) {
2981 dev_kfree_skb_any(skb);
9d5c8243
AK		 2982 return NETDEV_TX_OK;
2983 }
2984
2985 if (tso)
2986 tx_flags |= IGB_TX_FLAGS_TSO;
2987 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2988 if (skb->ip_summed == CHECKSUM_PARTIAL)
2989 tx_flags |= IGB_TX_FLAGS_CSUM;
2990
9d5c8243
AK		 2991 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2992 igb_tx_map_adv(adapter, tx_ring, skb),
2993 skb->len, hdr_len);
2994
2995 netdev->trans_start = jiffies;
2996
2997 /* Make sure there is space in the ring for the next send. */
2998 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2999
9d5c8243
AK		 3000 return NETDEV_TX_OK;
3001}
3002
3003static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3004{
3005 struct igb_adapter *adapter = netdev_priv(netdev);
661086df
PWJ		 3006 struct igb_ring *tx_ring;
3007
661086df
PWJ		 3008 int r_idx = 0;
3009 r_idx = skb->queue_mapping & (IGB_MAX_TX_QUEUES - 1);
3010 tx_ring = adapter->multi_tx_table[r_idx];
9d5c8243
AK		 3011
3012 /* This goes back to the question of how to logically map a tx queue
3013 * to a flow. Right now, performance is impacted slightly negatively
3014 * if using multiple tx queues. If the stack breaks away from a
3015 * single qdisc implementation, we can look at this again. */
3016 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3017}
3018
3019/**
3020 * igb_tx_timeout - Respond to a Tx Hang
3021 * @netdev: network interface device structure
3022 **/
3023static void igb_tx_timeout(struct net_device *netdev)
3024{
3025 struct igb_adapter *adapter = netdev_priv(netdev);
3026 struct e1000_hw *hw = &adapter->hw;
3027
3028 /* Do the reset outside of interrupt context */
3029 adapter->tx_timeout_count++;
3030 schedule_work(&adapter->reset_task);
3031 wr32(E1000_EICS, adapter->eims_enable_mask &
3032 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
3033}
3034
3035static void igb_reset_task(struct work_struct *work)
3036{
3037 struct igb_adapter *adapter;
3038 adapter = container_of(work, struct igb_adapter, reset_task);
3039
3040 igb_reinit_locked(adapter);
3041}
3042
3043/**
3044 * igb_get_stats - Get System Network Statistics
3045 * @netdev: network interface device structure
3046 *
3047 * Returns the address of the device statistics structure.
3048 * The statistics are actually updated from the timer callback.
3049 **/
3050static struct net_device_stats *
3051igb_get_stats(struct net_device *netdev)
3052{
3053 struct igb_adapter *adapter = netdev_priv(netdev);
3054
3055 /* only return the current stats */
3056 return &adapter->net_stats;
3057}
3058
3059/**
3060 * igb_change_mtu - Change the Maximum Transfer Unit
3061 * @netdev: network interface device structure
3062 * @new_mtu: new value for maximum frame size
3063 *
3064 * Returns 0 on success, negative on failure
3065 **/
3066static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3067{
3068 struct igb_adapter *adapter = netdev_priv(netdev);
3069 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3070
3071 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3072 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3073 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3074 return -EINVAL;
3075 }
3076
3077#define MAX_STD_JUMBO_FRAME_SIZE 9234
3078 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3079 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3080 return -EINVAL;
3081 }
3082
3083 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3084 msleep(1);
3085 /* igb_down has a dependency on max_frame_size */
3086 adapter->max_frame_size = max_frame;
3087 if (netif_running(netdev))
3088 igb_down(adapter);
3089
3090 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3091 * means we reserve 2 more, this pushes us to allocate from the next
3092 * larger slab size.
3093 * i.e. RXBUFFER_2048 --> size-4096 slab
3094 */
3095
3096 if (max_frame <= IGB_RXBUFFER_256)
3097 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3098 else if (max_frame <= IGB_RXBUFFER_512)
3099 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3100 else if (max_frame <= IGB_RXBUFFER_1024)
3101 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3102 else if (max_frame <= IGB_RXBUFFER_2048)
3103 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3104 else
bf36c1a0
AD		 3105#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3106 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3107#else
3108 adapter->rx_buffer_len = PAGE_SIZE / 2;
3109#endif
9d5c8243
AK		 3110 /* adjust allocation if LPE protects us, and we aren't using SBP */
3111 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3112 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3113 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3114
3115 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3116 netdev->mtu, new_mtu);
3117 netdev->mtu = new_mtu;
3118
3119 if (netif_running(netdev))
3120 igb_up(adapter);
3121 else
3122 igb_reset(adapter);
3123
3124 clear_bit(__IGB_RESETTING, &adapter->state);
3125
3126 return 0;
3127}
3128
3129/**
3130 * igb_update_stats - Update the board statistics counters
3131 * @adapter: board private structure
3132 **/
3133
3134void igb_update_stats(struct igb_adapter *adapter)
3135{
3136 struct e1000_hw *hw = &adapter->hw;
3137 struct pci_dev *pdev = adapter->pdev;
3138 u16 phy_tmp;
3139
3140#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3141
3142 /*
3143 * Prevent stats update while adapter is being reset, or if the pci
3144 * connection is down.
3145 */
3146 if (adapter->link_speed == 0)
3147 return;
3148 if (pci_channel_offline(pdev))
3149 return;
3150
3151 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3152 adapter->stats.gprc += rd32(E1000_GPRC);
3153 adapter->stats.gorc += rd32(E1000_GORCL);
3154 rd32(E1000_GORCH); /* clear GORCL */
3155 adapter->stats.bprc += rd32(E1000_BPRC);
3156 adapter->stats.mprc += rd32(E1000_MPRC);
3157 adapter->stats.roc += rd32(E1000_ROC);
3158
3159 adapter->stats.prc64 += rd32(E1000_PRC64);
3160 adapter->stats.prc127 += rd32(E1000_PRC127);
3161 adapter->stats.prc255 += rd32(E1000_PRC255);
3162 adapter->stats.prc511 += rd32(E1000_PRC511);
3163 adapter->stats.prc1023 += rd32(E1000_PRC1023);
3164 adapter->stats.prc1522 += rd32(E1000_PRC1522);
3165 adapter->stats.symerrs += rd32(E1000_SYMERRS);
3166 adapter->stats.sec += rd32(E1000_SEC);
3167
3168 adapter->stats.mpc += rd32(E1000_MPC);
3169 adapter->stats.scc += rd32(E1000_SCC);
3170 adapter->stats.ecol += rd32(E1000_ECOL);
3171 adapter->stats.mcc += rd32(E1000_MCC);
3172 adapter->stats.latecol += rd32(E1000_LATECOL);
3173 adapter->stats.dc += rd32(E1000_DC);
3174 adapter->stats.rlec += rd32(E1000_RLEC);
3175 adapter->stats.xonrxc += rd32(E1000_XONRXC);
3176 adapter->stats.xontxc += rd32(E1000_XONTXC);
3177 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3178 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3179 adapter->stats.fcruc += rd32(E1000_FCRUC);
3180 adapter->stats.gptc += rd32(E1000_GPTC);
3181 adapter->stats.gotc += rd32(E1000_GOTCL);
3182 rd32(E1000_GOTCH); /* clear GOTCL */
3183 adapter->stats.rnbc += rd32(E1000_RNBC);
3184 adapter->stats.ruc += rd32(E1000_RUC);
3185 adapter->stats.rfc += rd32(E1000_RFC);
3186 adapter->stats.rjc += rd32(E1000_RJC);
3187 adapter->stats.tor += rd32(E1000_TORH);
3188 adapter->stats.tot += rd32(E1000_TOTH);
3189 adapter->stats.tpr += rd32(E1000_TPR);
3190
3191 adapter->stats.ptc64 += rd32(E1000_PTC64);
3192 adapter->stats.ptc127 += rd32(E1000_PTC127);
3193 adapter->stats.ptc255 += rd32(E1000_PTC255);
3194 adapter->stats.ptc511 += rd32(E1000_PTC511);
3195 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3196 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3197
3198 adapter->stats.mptc += rd32(E1000_MPTC);
3199 adapter->stats.bptc += rd32(E1000_BPTC);
3200
3201 /* used for adaptive IFS */
3202
3203 hw->mac.tx_packet_delta = rd32(E1000_TPT);
3204 adapter->stats.tpt += hw->mac.tx_packet_delta;
3205 hw->mac.collision_delta = rd32(E1000_COLC);
3206 adapter->stats.colc += hw->mac.collision_delta;
3207
3208 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3209 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3210 adapter->stats.tncrs += rd32(E1000_TNCRS);
3211 adapter->stats.tsctc += rd32(E1000_TSCTC);
3212 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3213
3214 adapter->stats.iac += rd32(E1000_IAC);
3215 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3216 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3217 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3218 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3219 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3220 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3221 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3222 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3223
3224 /* Fill out the OS statistics structure */
3225 adapter->net_stats.multicast = adapter->stats.mprc;
3226 adapter->net_stats.collisions = adapter->stats.colc;
3227
3228 /* Rx Errors */
3229
3230 /* RLEC on some newer hardware can be incorrect so build
3231 * our own version based on RUC and ROC */
3232 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3233 adapter->stats.crcerrs + adapter->stats.algnerrc +
3234 adapter->stats.ruc + adapter->stats.roc +
3235 adapter->stats.cexterr;
3236 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3237 adapter->stats.roc;
3238 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3239 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3240 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3241
3242 /* Tx Errors */
3243 adapter->net_stats.tx_errors = adapter->stats.ecol +
3244 adapter->stats.latecol;
3245 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3246 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3247 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3248
3249 /* Tx Dropped needs to be maintained elsewhere */
3250
3251 /* Phy Stats */
3252 if (hw->phy.media_type == e1000_media_type_copper) {
3253 if ((adapter->link_speed == SPEED_1000) &&
f5f4cf08 3254 (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
9d5c8243
AK		 3255 &phy_tmp))) {
3256 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3257 adapter->phy_stats.idle_errors += phy_tmp;
3258 }
3259 }
3260
3261 /* Management Stats */
3262 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3263 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3264 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3265}
3266
3267
3268static irqreturn_t igb_msix_other(int irq, void *data)
3269{
3270 struct net_device *netdev = data;
3271 struct igb_adapter *adapter = netdev_priv(netdev);
3272 struct e1000_hw *hw = &adapter->hw;
844290e5 3273 u32 icr = rd32(E1000_ICR);
9d5c8243 3274
844290e5
PW		 3275 /* reading ICR causes bit 31 of EICR to be cleared */
3276 if (!(icr & E1000_ICR_LSC))
3277 goto no_link_interrupt;
3278 hw->mac.get_link_status = 1;
3279 /* guard against interrupt when we're going down */
3280 if (!test_bit(__IGB_DOWN, &adapter->state))
3281 mod_timer(&adapter->watchdog_timer, jiffies + 1);
661086df 3282
9d5c8243
AK		 3283no_link_interrupt:
3284 wr32(E1000_IMS, E1000_IMS_LSC);
844290e5 3285 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 3286
3287 return IRQ_HANDLED;
3288}
3289
3290static irqreturn_t igb_msix_tx(int irq, void *data)
3291{
3292 struct igb_ring *tx_ring = data;
3293 struct igb_adapter *adapter = tx_ring->adapter;
3294 struct e1000_hw *hw = &adapter->hw;
3295
421e02f0 3296#ifdef CONFIG_IGB_DCA
7dfc16fa 3297 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3298 igb_update_tx_dca(tx_ring);
3299#endif
9d5c8243
AK		 3300 tx_ring->total_bytes = 0;
3301 tx_ring->total_packets = 0;
661086df
PWJ		 3302
3303 /* auto mask will automatically reenable the interrupt when we write
3304 * EICS */
3b644cf6 3305 if (!igb_clean_tx_irq(tx_ring))
9d5c8243
AK		 3306 /* Ring was not completely cleaned, so fire another interrupt */
3307 wr32(E1000_EICS, tx_ring->eims_value);
661086df 3308 else
9d5c8243 3309 wr32(E1000_EIMS, tx_ring->eims_value);
661086df 3310
9d5c8243
AK		 3311 return IRQ_HANDLED;
3312}
3313
6eb5a7f1
AD		 3314static void igb_write_itr(struct igb_ring *ring)
3315{
3316 struct e1000_hw *hw = &ring->adapter->hw;
3317 if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3318 switch (hw->mac.type) {
3319 case e1000_82576:
3320 wr32(ring->itr_register,
3321 ring->itr_val |
3322 0x80000000);
3323 break;
3324 default:
3325 wr32(ring->itr_register,
3326 ring->itr_val |
3327 (ring->itr_val << 16));
3328 break;
3329 }
3330 ring->set_itr = 0;
3331 }
3332}
3333
9d5c8243
AK		 3334static irqreturn_t igb_msix_rx(int irq, void *data)
3335{
3336 struct igb_ring *rx_ring = data;
3337 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3338
844290e5
PW		 3339 /* Write the ITR value calculated at the end of the
3340 * previous interrupt.
3341 */
9d5c8243 3342
6eb5a7f1 3343 igb_write_itr(rx_ring);
9d5c8243 3344
844290e5
PW		 3345 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi))
3346 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3347
421e02f0 3348#ifdef CONFIG_IGB_DCA
7dfc16fa 3349 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3350 igb_update_rx_dca(rx_ring);
3351#endif
3352 return IRQ_HANDLED;
3353}
3354
421e02f0 3355#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 3356static void igb_update_rx_dca(struct igb_ring *rx_ring)
3357{
3358 u32 dca_rxctrl;
3359 struct igb_adapter *adapter = rx_ring->adapter;
3360 struct e1000_hw *hw = &adapter->hw;
3361 int cpu = get_cpu();
3362 int q = rx_ring - adapter->rx_ring;
3363
3364 if (rx_ring->cpu != cpu) {
3365 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
2d064c06
AD		 3366 if (hw->mac.type == e1000_82576) {
3367 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3368 dca_rxctrl |= dca_get_tag(cpu) <<
3369 E1000_DCA_RXCTRL_CPUID_SHIFT;
3370 } else {
3371 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3372 dca_rxctrl |= dca_get_tag(cpu);
3373 }
fe4506b6
JC		 3374 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3375 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3376 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3377 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3378 rx_ring->cpu = cpu;
3379 }
3380 put_cpu();
3381}
3382
3383static void igb_update_tx_dca(struct igb_ring *tx_ring)
3384{
3385 u32 dca_txctrl;
3386 struct igb_adapter *adapter = tx_ring->adapter;
3387 struct e1000_hw *hw = &adapter->hw;
3388 int cpu = get_cpu();
3389 int q = tx_ring - adapter->tx_ring;
3390
3391 if (tx_ring->cpu != cpu) {
3392 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
2d064c06
AD		 3393 if (hw->mac.type == e1000_82576) {
3394 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3395 dca_txctrl |= dca_get_tag(cpu) <<
3396 E1000_DCA_TXCTRL_CPUID_SHIFT;
3397 } else {
3398 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3399 dca_txctrl |= dca_get_tag(cpu);
3400 }
fe4506b6
JC		 3401 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3402 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3403 tx_ring->cpu = cpu;
3404 }
3405 put_cpu();
3406}
3407
3408static void igb_setup_dca(struct igb_adapter *adapter)
3409{
3410 int i;
3411
7dfc16fa 3412 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 3413 return;
3414
3415 for (i = 0; i < adapter->num_tx_queues; i++) {
3416 adapter->tx_ring[i].cpu = -1;
3417 igb_update_tx_dca(&adapter->tx_ring[i]);
3418 }
3419 for (i = 0; i < adapter->num_rx_queues; i++) {
3420 adapter->rx_ring[i].cpu = -1;
3421 igb_update_rx_dca(&adapter->rx_ring[i]);
3422 }
3423}
3424
3425static int __igb_notify_dca(struct device *dev, void *data)
3426{
3427 struct net_device *netdev = dev_get_drvdata(dev);
3428 struct igb_adapter *adapter = netdev_priv(netdev);
3429 struct e1000_hw *hw = &adapter->hw;
3430 unsigned long event = *(unsigned long *)data;
3431
7dfc16fa
AD		 3432 if (!(adapter->flags & IGB_FLAG_HAS_DCA))
3433 goto out;
3434
fe4506b6
JC		 3435 switch (event) {
3436 case DCA_PROVIDER_ADD:
3437 /* if already enabled, don't do it again */
7dfc16fa 3438 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 3439 break;
7dfc16fa 3440 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3441 /* Always use CB2 mode, difference is masked
3442 * in the CB driver. */
3443 wr32(E1000_DCA_CTRL, 2);
3444 if (dca_add_requester(dev) == 0) {
3445 dev_info(&adapter->pdev->dev, "DCA enabled\n");
3446 igb_setup_dca(adapter);
3447 break;
3448 }
3449 /* Fall Through since DCA is disabled. */
3450 case DCA_PROVIDER_REMOVE:
7dfc16fa 3451 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 3452 /* without this a class_device is left
3453 * hanging around in the sysfs model */
3454 dca_remove_requester(dev);
3455 dev_info(&adapter->pdev->dev, "DCA disabled\n");
7dfc16fa 3456 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
fe4506b6
JC		 3457 wr32(E1000_DCA_CTRL, 1);
3458 }
3459 break;
3460 }
7dfc16fa 3461out:
fe4506b6 3462 return 0;
9d5c8243
AK		 3463}
3464
fe4506b6
JC		 3465static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3466 void *p)
3467{
3468 int ret_val;
3469
3470 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3471 __igb_notify_dca);
3472
3473 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3474}
421e02f0 3475#endif /* CONFIG_IGB_DCA */
9d5c8243
AK		 3476
3477/**
3478 * igb_intr_msi - Interrupt Handler
3479 * @irq: interrupt number
3480 * @data: pointer to a network interface device structure
3481 **/
3482static irqreturn_t igb_intr_msi(int irq, void *data)
3483{
3484 struct net_device *netdev = data;
3485 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3486 struct e1000_hw *hw = &adapter->hw;
3487 /* read ICR disables interrupts using IAM */
3488 u32 icr = rd32(E1000_ICR);
3489
6eb5a7f1 3490 igb_write_itr(adapter->rx_ring);
9d5c8243 3491
9d5c8243
AK		 3492 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3493 hw->mac.get_link_status = 1;
3494 if (!test_bit(__IGB_DOWN, &adapter->state))
3495 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3496 }
3497
844290e5 3498 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3499
3500 return IRQ_HANDLED;
3501}
3502
3503/**
3504 * igb_intr - Interrupt Handler
3505 * @irq: interrupt number
3506 * @data: pointer to a network interface device structure
3507 **/
3508static irqreturn_t igb_intr(int irq, void *data)
3509{
3510 struct net_device *netdev = data;
3511 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 3512 struct e1000_hw *hw = &adapter->hw;
3513 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3514 * need for the IMC write */
3515 u32 icr = rd32(E1000_ICR);
3516 u32 eicr = 0;
3517 if (!icr)
3518 return IRQ_NONE; /* Not our interrupt */
3519
6eb5a7f1 3520 igb_write_itr(adapter->rx_ring);
9d5c8243
AK		 3521
3522 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3523 * not set, then the adapter didn't send an interrupt */
3524 if (!(icr & E1000_ICR_INT_ASSERTED))
3525 return IRQ_NONE;
3526
3527 eicr = rd32(E1000_EICR);
3528
3529 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3530 hw->mac.get_link_status = 1;
3531 /* guard against interrupt when we're going down */
3532 if (!test_bit(__IGB_DOWN, &adapter->state))
3533 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3534 }
3535
844290e5 3536 netif_rx_schedule(netdev, &adapter->rx_ring[0].napi);
9d5c8243
AK		 3537
3538 return IRQ_HANDLED;
3539}
3540
3541/**
661086df
PWJ		 3542 * igb_poll - NAPI Rx polling callback
3543 * @napi: napi polling structure
3544 * @budget: count of how many packets we should handle
9d5c8243 3545 **/
661086df 3546static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 3547{
661086df
PWJ		 3548 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3549 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243 3550 struct net_device *netdev = adapter->netdev;
661086df 3551 int tx_clean_complete, work_done = 0;
9d5c8243 3552
661086df 3553 /* this poll routine only supports one tx and one rx queue */
421e02f0 3554#ifdef CONFIG_IGB_DCA
7dfc16fa 3555 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3556 igb_update_tx_dca(&adapter->tx_ring[0]);
3557#endif
661086df 3558 tx_clean_complete = igb_clean_tx_irq(&adapter->tx_ring[0]);
fe4506b6 3559
421e02f0 3560#ifdef CONFIG_IGB_DCA
7dfc16fa 3561 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3562 igb_update_rx_dca(&adapter->rx_ring[0]);
3563#endif
661086df 3564 igb_clean_rx_irq_adv(&adapter->rx_ring[0], &work_done, budget);
9d5c8243
AK		 3565
3566 /* If no Tx and not enough Rx work done, exit the polling mode */
3567 if ((tx_clean_complete && (work_done < budget)) ||
3568 !netif_running(netdev)) {
9d5c8243 3569 if (adapter->itr_setting & 3)
6eb5a7f1 3570 igb_set_itr(adapter);
9d5c8243
AK		 3571 netif_rx_complete(netdev, napi);
3572 if (!test_bit(__IGB_DOWN, &adapter->state))
3573 igb_irq_enable(adapter);
3574 return 0;
3575 }
3576
3577 return 1;
3578}
3579
3580static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3581{
3582 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3583 struct igb_adapter *adapter = rx_ring->adapter;
3584 struct e1000_hw *hw = &adapter->hw;
3585 struct net_device *netdev = adapter->netdev;
3586 int work_done = 0;
3587
421e02f0 3588#ifdef CONFIG_IGB_DCA
7dfc16fa 3589 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6
JC		 3590 igb_update_rx_dca(rx_ring);
3591#endif
3b644cf6 3592 igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
9d5c8243
AK		 3593
3594
3595 /* If not enough Rx work done, exit the polling mode */
3596 if ((work_done == 0) || !netif_running(netdev)) {
9d5c8243
AK		 3597 netif_rx_complete(netdev, napi);
3598
6eb5a7f1
AD		 3599 if (adapter->itr_setting & 3) {
3600 if (adapter->num_rx_queues == 1)
3601 igb_set_itr(adapter);
3602 else
3603 igb_update_ring_itr(rx_ring);
9d5c8243 3604 }
844290e5
PW		 3605
3606 if (!test_bit(__IGB_DOWN, &adapter->state))
3607 wr32(E1000_EIMS, rx_ring->eims_value);
3608
9d5c8243
AK		 3609 return 0;
3610 }
3611
3612 return 1;
3613}
6d8126f9
AV		 3614
3615static inline u32 get_head(struct igb_ring *tx_ring)
3616{
3617 void *end = (struct e1000_tx_desc *)tx_ring->desc + tx_ring->count;
3618 return le32_to_cpu(*(volatile __le32 *)end);
3619}
3620
9d5c8243
AK		 3621/**
3622 * igb_clean_tx_irq - Reclaim resources after transmit completes
3623 * @adapter: board private structure
3624 * returns true if ring is completely cleaned
3625 **/
3b644cf6 3626static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
9d5c8243 3627{
3b644cf6 3628 struct igb_adapter *adapter = tx_ring->adapter;
9d5c8243 3629 struct e1000_hw *hw = &adapter->hw;
3b644cf6 3630 struct net_device *netdev = adapter->netdev;
9d5c8243
AK		 3631 struct e1000_tx_desc *tx_desc;
3632 struct igb_buffer *buffer_info;
3633 struct sk_buff *skb;
3634 unsigned int i;
3635 u32 head, oldhead;
3636 unsigned int count = 0;
9d5c8243 3637 unsigned int total_bytes = 0, total_packets = 0;
fc7d345d 3638 bool retval = true;
9d5c8243
AK		 3639
3640 rmb();
6d8126f9 3641 head = get_head(tx_ring);
9d5c8243
AK		 3642 i = tx_ring->next_to_clean;
3643 while (1) {
3644 while (i != head) {
9d5c8243
AK		 3645 tx_desc = E1000_TX_DESC(*tx_ring, i);
3646 buffer_info = &tx_ring->buffer_info[i];
3647 skb = buffer_info->skb;
3648
3649 if (skb) {
3650 unsigned int segs, bytecount;
3651 /* gso_segs is currently only valid for tcp */
3652 segs = skb_shinfo(skb)->gso_segs ?: 1;
3653 /* multiply data chunks by size of headers */
3654 bytecount = ((segs - 1) * skb_headlen(skb)) +
3655 skb->len;
3656 total_packets += segs;
3657 total_bytes += bytecount;
3658 }
3659
3660 igb_unmap_and_free_tx_resource(adapter, buffer_info);
9d5c8243
AK		 3661
3662 i++;
3663 if (i == tx_ring->count)
3664 i = 0;
3665
3666 count++;
3667 if (count == IGB_MAX_TX_CLEAN) {
3668 retval = false;
3669 goto done_cleaning;
3670 }
3671 }
3672 oldhead = head;
3673 rmb();
6d8126f9 3674 head = get_head(tx_ring);
9d5c8243
AK		 3675 if (head == oldhead)
3676 goto done_cleaning;
3677 } /* while (1) */
3678
3679done_cleaning:
3680 tx_ring->next_to_clean = i;
3681
fc7d345d 3682 if (unlikely(count &&
9d5c8243
AK		 3683 netif_carrier_ok(netdev) &&
3684 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3685 /* Make sure that anybody stopping the queue after this
3686 * sees the new next_to_clean.
3687 */
3688 smp_mb();
661086df
PWJ		 3689 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
3690 !(test_bit(__IGB_DOWN, &adapter->state))) {
3691 netif_wake_subqueue(netdev, tx_ring->queue_index);
3692 ++adapter->restart_queue;
3693 }
9d5c8243
AK		 3694 }
3695
3696 if (tx_ring->detect_tx_hung) {
3697 /* Detect a transmit hang in hardware, this serializes the
3698 * check with the clearing of time_stamp and movement of i */
3699 tx_ring->detect_tx_hung = false;
3700 if (tx_ring->buffer_info[i].time_stamp &&
3701 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3702 (adapter->tx_timeout_factor * HZ))
3703 && !(rd32(E1000_STATUS) &
3704 E1000_STATUS_TXOFF)) {
3705
3706 tx_desc = E1000_TX_DESC(*tx_ring, i);
3707 /* detected Tx unit hang */
3708 dev_err(&adapter->pdev->dev,
3709 "Detected Tx Unit Hang\n"
2d064c06 3710 " Tx Queue <%d>\n"
9d5c8243
AK		 3711 " TDH <%x>\n"
3712 " TDT <%x>\n"
3713 " next_to_use <%x>\n"
3714 " next_to_clean <%x>\n"
3715 " head (WB) <%x>\n"
3716 "buffer_info[next_to_clean]\n"
3717 " time_stamp <%lx>\n"
3718 " jiffies <%lx>\n"
3719 " desc.status <%x>\n",
2d064c06 3720 tx_ring->queue_index,
9d5c8243
AK		 3721 readl(adapter->hw.hw_addr + tx_ring->head),
3722 readl(adapter->hw.hw_addr + tx_ring->tail),
3723 tx_ring->next_to_use,
3724 tx_ring->next_to_clean,
3725 head,
3726 tx_ring->buffer_info[i].time_stamp,
3727 jiffies,
3728 tx_desc->upper.fields.status);
661086df 3729 netif_stop_subqueue(netdev, tx_ring->queue_index);
9d5c8243
AK		 3730 }
3731 }
3732 tx_ring->total_bytes += total_bytes;
3733 tx_ring->total_packets += total_packets;
e21ed353
AD		 3734 tx_ring->tx_stats.bytes += total_bytes;
3735 tx_ring->tx_stats.packets += total_packets;
9d5c8243
AK		 3736 adapter->net_stats.tx_bytes += total_bytes;
3737 adapter->net_stats.tx_packets += total_packets;
3738 return retval;
3739}
3740
d3352520
AD		 3741#ifdef CONFIG_IGB_LRO
3742 /**
3743 * igb_get_skb_hdr - helper function for LRO header processing
3744 * @skb: pointer to sk_buff to be added to LRO packet
3745 * @iphdr: pointer to ip header structure
3746 * @tcph: pointer to tcp header structure
3747 * @hdr_flags: pointer to header flags
3748 * @priv: pointer to the receive descriptor for the current sk_buff
3749 **/
3750static int igb_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
3751 u64 *hdr_flags, void *priv)
3752{
3753 union e1000_adv_rx_desc *rx_desc = priv;
3754 u16 pkt_type = rx_desc->wb.lower.lo_dword.pkt_info &
3755 (E1000_RXDADV_PKTTYPE_IPV4 | E1000_RXDADV_PKTTYPE_TCP);
3756
3757 /* Verify that this is a valid IPv4 TCP packet */
3758 if (pkt_type != (E1000_RXDADV_PKTTYPE_IPV4 |
3759 E1000_RXDADV_PKTTYPE_TCP))
3760 return -1;
3761
3762 /* Set network headers */
3763 skb_reset_network_header(skb);
3764 skb_set_transport_header(skb, ip_hdrlen(skb));
3765 *iphdr = ip_hdr(skb);
3766 *tcph = tcp_hdr(skb);
3767 *hdr_flags = LRO_IPV4 | LRO_TCP;
3768
3769 return 0;
3770
3771}
3772#endif /* CONFIG_IGB_LRO */
9d5c8243
AK		 3773
3774/**
3775 * igb_receive_skb - helper function to handle rx indications
d3352520 3776 * @ring: pointer to receive ring receving this packet
9d5c8243
AK		 3777 * @status: descriptor status field as written by hardware
3778 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3779 * @skb: pointer to sk_buff to be indicated to stack
3780 **/
d3352520
AD		 3781static void igb_receive_skb(struct igb_ring *ring, u8 status,
3782 union e1000_adv_rx_desc * rx_desc,
3783 struct sk_buff *skb)
3784{
3785 struct igb_adapter * adapter = ring->adapter;
3786 bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
3787
3788#ifdef CONFIG_IGB_LRO
3789 if (adapter->netdev->features & NETIF_F_LRO &&
3790 skb->ip_summed == CHECKSUM_UNNECESSARY) {
3791 if (vlan_extracted)
3792 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
3793 adapter->vlgrp,
3794 le16_to_cpu(rx_desc->wb.upper.vlan),
3795 rx_desc);
3796 else
3797 lro_receive_skb(&ring->lro_mgr,skb, rx_desc);
3798 ring->lro_used = 1;
3799 } else {
3800#endif
3801 if (vlan_extracted)
3802 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3803 le16_to_cpu(rx_desc->wb.upper.vlan));
3804 else
3805
3806 netif_receive_skb(skb);
3807#ifdef CONFIG_IGB_LRO
3808 }
3809#endif
9d5c8243
AK		 3810}
3811
3812
3813static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3814 u32 status_err, struct sk_buff *skb)
3815{
3816 skb->ip_summed = CHECKSUM_NONE;
3817
3818 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3819 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3820 return;
3821 /* TCP/UDP checksum error bit is set */
3822 if (status_err &
3823 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3824 /* let the stack verify checksum errors */
3825 adapter->hw_csum_err++;
3826 return;
3827 }
3828 /* It must be a TCP or UDP packet with a valid checksum */
3829 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3830 skb->ip_summed = CHECKSUM_UNNECESSARY;
3831
3832 adapter->hw_csum_good++;
3833}
3834
3b644cf6
MW		 3835static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
3836 int *work_done, int budget)
9d5c8243 3837{
3b644cf6 3838 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3839 struct net_device *netdev = adapter->netdev;
3840 struct pci_dev *pdev = adapter->pdev;
3841 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3842 struct igb_buffer *buffer_info , *next_buffer;
3843 struct sk_buff *skb;
bf36c1a0 3844 unsigned int i;
9d5c8243
AK		 3845 u32 length, hlen, staterr;
3846 bool cleaned = false;
3847 int cleaned_count = 0;
3848 unsigned int total_bytes = 0, total_packets = 0;
3849
3850 i = rx_ring->next_to_clean;
3851 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3852 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3853
3854 while (staterr & E1000_RXD_STAT_DD) {
3855 if (*work_done >= budget)
3856 break;
3857 (*work_done)++;
3858 buffer_info = &rx_ring->buffer_info[i];
3859
3860 /* HW will not DMA in data larger than the given buffer, even
3861 * if it parses the (NFS, of course) header to be larger. In
3862 * that case, it fills the header buffer and spills the rest
3863 * into the page.
3864 */
7deb07b1
AV		 3865 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
3866 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
9d5c8243
AK		 3867 if (hlen > adapter->rx_ps_hdr_size)
3868 hlen = adapter->rx_ps_hdr_size;
3869
3870 length = le16_to_cpu(rx_desc->wb.upper.length);
3871 cleaned = true;
3872 cleaned_count++;
3873
bf36c1a0
AD		 3874 skb = buffer_info->skb;
3875 prefetch(skb->data - NET_IP_ALIGN);
3876 buffer_info->skb = NULL;
3877 if (!adapter->rx_ps_hdr_size) {
3878 pci_unmap_single(pdev, buffer_info->dma,
3879 adapter->rx_buffer_len +
3880 NET_IP_ALIGN,
3881 PCI_DMA_FROMDEVICE);
3882 skb_put(skb, length);
3883 goto send_up;
9d5c8243
AK		 3884 }
3885
bf36c1a0
AD		 3886 if (!skb_shinfo(skb)->nr_frags) {
3887 pci_unmap_single(pdev, buffer_info->dma,
3888 adapter->rx_ps_hdr_size +
3889 NET_IP_ALIGN,
3890 PCI_DMA_FROMDEVICE);
3891 skb_put(skb, hlen);
3892 }
3893
3894 if (length) {
9d5c8243 3895 pci_unmap_page(pdev, buffer_info->page_dma,
bf36c1a0 3896 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9d5c8243 3897 buffer_info->page_dma = 0;
bf36c1a0
AD		 3898
3899 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
3900 buffer_info->page,
3901 buffer_info->page_offset,
3902 length);
3903
3904 if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
3905 (page_count(buffer_info->page) != 1))
3906 buffer_info->page = NULL;
3907 else
3908 get_page(buffer_info->page);
9d5c8243
AK		 3909
3910 skb->len += length;
3911 skb->data_len += length;
9d5c8243 3912
bf36c1a0 3913 skb->truesize += length;
9d5c8243
AK		 3914 }
3915send_up:
9d5c8243
AK		 3916 i++;
3917 if (i == rx_ring->count)
3918 i = 0;
3919 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3920 prefetch(next_rxd);
3921 next_buffer = &rx_ring->buffer_info[i];
3922
bf36c1a0 3923 if (!(staterr & E1000_RXD_STAT_EOP)) {
b2d56536
AD		 3924 buffer_info->skb = next_buffer->skb;
3925 buffer_info->dma = next_buffer->dma;
3926 next_buffer->skb = skb;
3927 next_buffer->dma = 0;
bf36c1a0
AD		 3928 goto next_desc;
3929 }
3930
9d5c8243
AK		 3931 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3932 dev_kfree_skb_irq(skb);
3933 goto next_desc;
3934 }
9d5c8243
AK		 3935
3936 total_bytes += skb->len;
3937 total_packets++;
3938
3939 igb_rx_checksum_adv(adapter, staterr, skb);
3940
3941 skb->protocol = eth_type_trans(skb, netdev);
3942
d3352520 3943 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
9d5c8243 3944
9d5c8243
AK		 3945next_desc:
3946 rx_desc->wb.upper.status_error = 0;
3947
3948 /* return some buffers to hardware, one at a time is too slow */
3949 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3b644cf6 3950 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3951 cleaned_count = 0;
3952 }
3953
3954 /* use prefetched values */
3955 rx_desc = next_rxd;
3956 buffer_info = next_buffer;
3957
3958 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3959 }
bf36c1a0 3960
9d5c8243
AK		 3961 rx_ring->next_to_clean = i;
3962 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3963
d3352520
AD		 3964#ifdef CONFIG_IGB_LRO
3965 if (rx_ring->lro_used) {
3966 lro_flush_all(&rx_ring->lro_mgr);
3967 rx_ring->lro_used = 0;
3968 }
3969#endif
3970
9d5c8243 3971 if (cleaned_count)
3b644cf6 3972 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
9d5c8243
AK		 3973
3974 rx_ring->total_packets += total_packets;
3975 rx_ring->total_bytes += total_bytes;
3976 rx_ring->rx_stats.packets += total_packets;
3977 rx_ring->rx_stats.bytes += total_bytes;
3978 adapter->net_stats.rx_bytes += total_bytes;
3979 adapter->net_stats.rx_packets += total_packets;
3980 return cleaned;
3981}
3982
3983
3984/**
3985 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3986 * @adapter: address of board private structure
3987 **/
3b644cf6 3988static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
9d5c8243
AK		 3989 int cleaned_count)
3990{
3b644cf6 3991 struct igb_adapter *adapter = rx_ring->adapter;
9d5c8243
AK		 3992 struct net_device *netdev = adapter->netdev;
3993 struct pci_dev *pdev = adapter->pdev;
3994 union e1000_adv_rx_desc *rx_desc;
3995 struct igb_buffer *buffer_info;
3996 struct sk_buff *skb;
3997 unsigned int i;
3998
3999 i = rx_ring->next_to_use;
4000 buffer_info = &rx_ring->buffer_info[i];
4001
4002 while (cleaned_count--) {
4003 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4004
bf36c1a0 4005 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
9d5c8243 4006 if (!buffer_info->page) {
bf36c1a0
AD		 4007 buffer_info->page = alloc_page(GFP_ATOMIC);
4008 if (!buffer_info->page) {
4009 adapter->alloc_rx_buff_failed++;
4010 goto no_buffers;
4011 }
4012 buffer_info->page_offset = 0;
4013 } else {
4014 buffer_info->page_offset ^= PAGE_SIZE / 2;
9d5c8243
AK		 4015 }
4016 buffer_info->page_dma =
4017 pci_map_page(pdev,
4018 buffer_info->page,
bf36c1a0
AD		 4019 buffer_info->page_offset,
4020 PAGE_SIZE / 2,
9d5c8243
AK		 4021 PCI_DMA_FROMDEVICE);
4022 }
4023
4024 if (!buffer_info->skb) {
4025 int bufsz;
4026
4027 if (adapter->rx_ps_hdr_size)
4028 bufsz = adapter->rx_ps_hdr_size;
4029 else
4030 bufsz = adapter->rx_buffer_len;
4031 bufsz += NET_IP_ALIGN;
4032 skb = netdev_alloc_skb(netdev, bufsz);
4033
4034 if (!skb) {
4035 adapter->alloc_rx_buff_failed++;
4036 goto no_buffers;
4037 }
4038
4039 /* Make buffer alignment 2 beyond a 16 byte boundary
4040 * this will result in a 16 byte aligned IP header after
4041 * the 14 byte MAC header is removed
4042 */
4043 skb_reserve(skb, NET_IP_ALIGN);
4044
4045 buffer_info->skb = skb;
4046 buffer_info->dma = pci_map_single(pdev, skb->data,
4047 bufsz,
4048 PCI_DMA_FROMDEVICE);
4049
4050 }
4051 /* Refresh the desc even if buffer_addrs didn't change because
4052 * each write-back erases this info. */
4053 if (adapter->rx_ps_hdr_size) {
4054 rx_desc->read.pkt_addr =
4055 cpu_to_le64(buffer_info->page_dma);
4056 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4057 } else {
4058 rx_desc->read.pkt_addr =
4059 cpu_to_le64(buffer_info->dma);
4060 rx_desc->read.hdr_addr = 0;
4061 }
4062
4063 i++;
4064 if (i == rx_ring->count)
4065 i = 0;
4066 buffer_info = &rx_ring->buffer_info[i];
4067 }
4068
4069no_buffers:
4070 if (rx_ring->next_to_use != i) {
4071 rx_ring->next_to_use = i;
4072 if (i == 0)
4073 i = (rx_ring->count - 1);
4074 else
4075 i--;
4076
4077 /* Force memory writes to complete before letting h/w
4078 * know there are new descriptors to fetch. (Only
4079 * applicable for weak-ordered memory model archs,
4080 * such as IA-64). */
4081 wmb();
4082 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4083 }
4084}
4085
4086/**
4087 * igb_mii_ioctl -
4088 * @netdev:
4089 * @ifreq:
4090 * @cmd:
4091 **/
4092static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4093{
4094 struct igb_adapter *adapter = netdev_priv(netdev);
4095 struct mii_ioctl_data *data = if_mii(ifr);
4096
4097 if (adapter->hw.phy.media_type != e1000_media_type_copper)
4098 return -EOPNOTSUPP;
4099
4100 switch (cmd) {
4101 case SIOCGMIIPHY:
4102 data->phy_id = adapter->hw.phy.addr;
4103 break;
4104 case SIOCGMIIREG:
4105 if (!capable(CAP_NET_ADMIN))
4106 return -EPERM;
f5f4cf08
AD		 4107 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4108 &data->val_out))
9d5c8243
AK		 4109 return -EIO;
4110 break;
4111 case SIOCSMIIREG:
4112 default:
4113 return -EOPNOTSUPP;
4114 }
4115 return 0;
4116}
4117
4118/**
4119 * igb_ioctl -
4120 * @netdev:
4121 * @ifreq:
4122 * @cmd:
4123 **/
4124static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4125{
4126 switch (cmd) {
4127 case SIOCGMIIPHY:
4128 case SIOCGMIIREG:
4129 case SIOCSMIIREG:
4130 return igb_mii_ioctl(netdev, ifr, cmd);
4131 default:
4132 return -EOPNOTSUPP;
4133 }
4134}
4135
4136static void igb_vlan_rx_register(struct net_device *netdev,
4137 struct vlan_group *grp)
4138{
4139 struct igb_adapter *adapter = netdev_priv(netdev);
4140 struct e1000_hw *hw = &adapter->hw;
4141 u32 ctrl, rctl;
4142
4143 igb_irq_disable(adapter);
4144 adapter->vlgrp = grp;
4145
4146 if (grp) {
4147 /* enable VLAN tag insert/strip */
4148 ctrl = rd32(E1000_CTRL);
4149 ctrl |= E1000_CTRL_VME;
4150 wr32(E1000_CTRL, ctrl);
4151
4152 /* enable VLAN receive filtering */
4153 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 4154 rctl &= ~E1000_RCTL_CFIEN;
4155 wr32(E1000_RCTL, rctl);
4156 igb_update_mng_vlan(adapter);
4157 wr32(E1000_RLPML,
4158 adapter->max_frame_size + VLAN_TAG_SIZE);
4159 } else {
4160 /* disable VLAN tag insert/strip */
4161 ctrl = rd32(E1000_CTRL);
4162 ctrl &= ~E1000_CTRL_VME;
4163 wr32(E1000_CTRL, ctrl);
4164
9d5c8243
AK		 4165 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
4166 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4167 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
4168 }
4169 wr32(E1000_RLPML,
4170 adapter->max_frame_size);
4171 }
4172
4173 if (!test_bit(__IGB_DOWN, &adapter->state))
4174 igb_irq_enable(adapter);
4175}
4176
4177static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
4178{
4179 struct igb_adapter *adapter = netdev_priv(netdev);
4180 struct e1000_hw *hw = &adapter->hw;
4181 u32 vfta, index;
4182
4183 if ((adapter->hw.mng_cookie.status &
4184 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4185 (vid == adapter->mng_vlan_id))
4186 return;
4187 /* add VID to filter table */
4188 index = (vid >> 5) & 0x7F;
4189 vfta = array_rd32(E1000_VFTA, index);
4190 vfta |= (1 << (vid & 0x1F));
4191 igb_write_vfta(&adapter->hw, index, vfta);
4192}
4193
4194static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
4195{
4196 struct igb_adapter *adapter = netdev_priv(netdev);
4197 struct e1000_hw *hw = &adapter->hw;
4198 u32 vfta, index;
4199
4200 igb_irq_disable(adapter);
4201 vlan_group_set_device(adapter->vlgrp, vid, NULL);
4202
4203 if (!test_bit(__IGB_DOWN, &adapter->state))
4204 igb_irq_enable(adapter);
4205
4206 if ((adapter->hw.mng_cookie.status &
4207 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
4208 (vid == adapter->mng_vlan_id)) {
4209 /* release control to f/w */
4210 igb_release_hw_control(adapter);
4211 return;
4212 }
4213
4214 /* remove VID from filter table */
4215 index = (vid >> 5) & 0x7F;
4216 vfta = array_rd32(E1000_VFTA, index);
4217 vfta &= ~(1 << (vid & 0x1F));
4218 igb_write_vfta(&adapter->hw, index, vfta);
4219}
4220
4221static void igb_restore_vlan(struct igb_adapter *adapter)
4222{
4223 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4224
4225 if (adapter->vlgrp) {
4226 u16 vid;
4227 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4228 if (!vlan_group_get_device(adapter->vlgrp, vid))
4229 continue;
4230 igb_vlan_rx_add_vid(adapter->netdev, vid);
4231 }
4232 }
4233}
4234
4235int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
4236{
4237 struct e1000_mac_info *mac = &adapter->hw.mac;
4238
4239 mac->autoneg = 0;
4240
4241 /* Fiber NICs only allow 1000 gbps Full duplex */
4242 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
4243 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4244 dev_err(&adapter->pdev->dev,
4245 "Unsupported Speed/Duplex configuration\n");
4246 return -EINVAL;
4247 }
4248
4249 switch (spddplx) {
4250 case SPEED_10 + DUPLEX_HALF:
4251 mac->forced_speed_duplex = ADVERTISE_10_HALF;
4252 break;
4253 case SPEED_10 + DUPLEX_FULL:
4254 mac->forced_speed_duplex = ADVERTISE_10_FULL;
4255 break;
4256 case SPEED_100 + DUPLEX_HALF:
4257 mac->forced_speed_duplex = ADVERTISE_100_HALF;
4258 break;
4259 case SPEED_100 + DUPLEX_FULL:
4260 mac->forced_speed_duplex = ADVERTISE_100_FULL;
4261 break;
4262 case SPEED_1000 + DUPLEX_FULL:
4263 mac->autoneg = 1;
4264 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
4265 break;
4266 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4267 default:
4268 dev_err(&adapter->pdev->dev,
4269 "Unsupported Speed/Duplex configuration\n");
4270 return -EINVAL;
4271 }
4272 return 0;
4273}
4274
4275
4276static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
4277{
4278 struct net_device *netdev = pci_get_drvdata(pdev);
4279 struct igb_adapter *adapter = netdev_priv(netdev);
4280 struct e1000_hw *hw = &adapter->hw;
2d064c06 4281 u32 ctrl, rctl, status;
9d5c8243
AK		 4282 u32 wufc = adapter->wol;
4283#ifdef CONFIG_PM
4284 int retval = 0;
4285#endif
4286
4287 netif_device_detach(netdev);
4288
a88f10ec
AD		 4289 if (netif_running(netdev))
4290 igb_close(netdev);
4291
4292 igb_reset_interrupt_capability(adapter);
4293
4294 igb_free_queues(adapter);
9d5c8243
AK		 4295
4296#ifdef CONFIG_PM
4297 retval = pci_save_state(pdev);
4298 if (retval)
4299 return retval;
4300#endif
4301
4302 status = rd32(E1000_STATUS);
4303 if (status & E1000_STATUS_LU)
4304 wufc &= ~E1000_WUFC_LNKC;
4305
4306 if (wufc) {
4307 igb_setup_rctl(adapter);
4308 igb_set_multi(netdev);
4309
4310 /* turn on all-multi mode if wake on multicast is enabled */
4311 if (wufc & E1000_WUFC_MC) {
4312 rctl = rd32(E1000_RCTL);
4313 rctl |= E1000_RCTL_MPE;
4314 wr32(E1000_RCTL, rctl);
4315 }
4316
4317 ctrl = rd32(E1000_CTRL);
4318 /* advertise wake from D3Cold */
4319 #define E1000_CTRL_ADVD3WUC 0x00100000
4320 /* phy power management enable */
4321 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4322 ctrl |= E1000_CTRL_ADVD3WUC;
4323 wr32(E1000_CTRL, ctrl);
4324
9d5c8243
AK		 4325 /* Allow time for pending master requests to run */
4326 igb_disable_pcie_master(&adapter->hw);
4327
4328 wr32(E1000_WUC, E1000_WUC_PME_EN);
4329 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 4330 } else {
4331 wr32(E1000_WUC, 0);
4332 wr32(E1000_WUFC, 0);
9d5c8243
AK		 4333 }
4334
2d064c06
AD		 4335 /* make sure adapter isn't asleep if manageability/wol is enabled */
4336 if (wufc || adapter->en_mng_pt) {
9d5c8243
AK		 4337 pci_enable_wake(pdev, PCI_D3hot, 1);
4338 pci_enable_wake(pdev, PCI_D3cold, 1);
2d064c06
AD		 4339 } else {
4340 igb_shutdown_fiber_serdes_link_82575(hw);
4341 pci_enable_wake(pdev, PCI_D3hot, 0);
4342 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243
AK		 4343 }
4344
4345 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4346 * would have already happened in close and is redundant. */
4347 igb_release_hw_control(adapter);
4348
4349 pci_disable_device(pdev);
4350
4351 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4352
4353 return 0;
4354}
4355
4356#ifdef CONFIG_PM
4357static int igb_resume(struct pci_dev *pdev)
4358{
4359 struct net_device *netdev = pci_get_drvdata(pdev);
4360 struct igb_adapter *adapter = netdev_priv(netdev);
4361 struct e1000_hw *hw = &adapter->hw;
4362 u32 err;
4363
4364 pci_set_power_state(pdev, PCI_D0);
4365 pci_restore_state(pdev);
42bfd33a
TI		 4366
4367 if (adapter->need_ioport)
4368 err = pci_enable_device(pdev);
4369 else
4370 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 4371 if (err) {
4372 dev_err(&pdev->dev,
4373 "igb: Cannot enable PCI device from suspend\n");
4374 return err;
4375 }
4376 pci_set_master(pdev);
4377
4378 pci_enable_wake(pdev, PCI_D3hot, 0);
4379 pci_enable_wake(pdev, PCI_D3cold, 0);
4380
a88f10ec
AD		 4381 igb_set_interrupt_capability(adapter);
4382
4383 if (igb_alloc_queues(adapter)) {
4384 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4385 return -ENOMEM;
9d5c8243
AK		 4386 }
4387
4388 /* e1000_power_up_phy(adapter); */
4389
4390 igb_reset(adapter);
4391 wr32(E1000_WUS, ~0);
4392
a88f10ec
AD		 4393 if (netif_running(netdev)) {
4394 err = igb_open(netdev);
4395 if (err)
4396 return err;
4397 }
9d5c8243
AK		 4398
4399 netif_device_attach(netdev);
4400
4401 /* let the f/w know that the h/w is now under the control of the
4402 * driver. */
4403 igb_get_hw_control(adapter);
4404
4405 return 0;
4406}
4407#endif
4408
4409static void igb_shutdown(struct pci_dev *pdev)
4410{
4411 igb_suspend(pdev, PMSG_SUSPEND);
4412}
4413
4414#ifdef CONFIG_NET_POLL_CONTROLLER
4415/*
4416 * Polling 'interrupt' - used by things like netconsole to send skbs
4417 * without having to re-enable interrupts. It's not called while
4418 * the interrupt routine is executing.
4419 */
4420static void igb_netpoll(struct net_device *netdev)
4421{
4422 struct igb_adapter *adapter = netdev_priv(netdev);
4423 int i;
4424 int work_done = 0;
4425
4426 igb_irq_disable(adapter);
7dfc16fa
AD		 4427 adapter->flags |= IGB_FLAG_IN_NETPOLL;
4428
9d5c8243 4429 for (i = 0; i < adapter->num_tx_queues; i++)
3b644cf6 4430 igb_clean_tx_irq(&adapter->tx_ring[i]);
9d5c8243
AK		 4431
4432 for (i = 0; i < adapter->num_rx_queues; i++)
3b644cf6 4433 igb_clean_rx_irq_adv(&adapter->rx_ring[i],
9d5c8243
AK		 4434 &work_done,
4435 adapter->rx_ring[i].napi.weight);
4436
7dfc16fa 4437 adapter->flags &= ~IGB_FLAG_IN_NETPOLL;
9d5c8243
AK		 4438 igb_irq_enable(adapter);
4439}
4440#endif /* CONFIG_NET_POLL_CONTROLLER */
4441
4442/**
4443 * igb_io_error_detected - called when PCI error is detected
4444 * @pdev: Pointer to PCI device
4445 * @state: The current pci connection state
4446 *
4447 * This function is called after a PCI bus error affecting
4448 * this device has been detected.
4449 */
4450static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4451 pci_channel_state_t state)
4452{
4453 struct net_device *netdev = pci_get_drvdata(pdev);
4454 struct igb_adapter *adapter = netdev_priv(netdev);
4455
4456 netif_device_detach(netdev);
4457
4458 if (netif_running(netdev))
4459 igb_down(adapter);
4460 pci_disable_device(pdev);
4461
4462 /* Request a slot slot reset. */
4463 return PCI_ERS_RESULT_NEED_RESET;
4464}
4465
4466/**
4467 * igb_io_slot_reset - called after the pci bus has been reset.
4468 * @pdev: Pointer to PCI device
4469 *
4470 * Restart the card from scratch, as if from a cold-boot. Implementation
4471 * resembles the first-half of the igb_resume routine.
4472 */
4473static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4474{
4475 struct net_device *netdev = pci_get_drvdata(pdev);
4476 struct igb_adapter *adapter = netdev_priv(netdev);
4477 struct e1000_hw *hw = &adapter->hw;
40a914fa 4478 pci_ers_result_t result;
42bfd33a 4479 int err;
9d5c8243 4480
42bfd33a
TI		 4481 if (adapter->need_ioport)
4482 err = pci_enable_device(pdev);
4483 else
4484 err = pci_enable_device_mem(pdev);
40a914fa 4485
42bfd33a 4486 if (err) {
9d5c8243
AK		 4487 dev_err(&pdev->dev,
4488 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 4489 result = PCI_ERS_RESULT_DISCONNECT;
4490 } else {
4491 pci_set_master(pdev);
4492 pci_restore_state(pdev);
9d5c8243 4493
40a914fa
AD		 4494 pci_enable_wake(pdev, PCI_D3hot, 0);
4495 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 4496
40a914fa
AD		 4497 igb_reset(adapter);
4498 wr32(E1000_WUS, ~0);
4499 result = PCI_ERS_RESULT_RECOVERED;
4500 }
9d5c8243 4501
40a914fa
AD		 4502 pci_cleanup_aer_uncorrect_error_status(pdev);
4503
4504 return result;
9d5c8243
AK		 4505}
4506
4507/**
4508 * igb_io_resume - called when traffic can start flowing again.
4509 * @pdev: Pointer to PCI device
4510 *
4511 * This callback is called when the error recovery driver tells us that
4512 * its OK to resume normal operation. Implementation resembles the
4513 * second-half of the igb_resume routine.
4514 */
4515static void igb_io_resume(struct pci_dev *pdev)
4516{
4517 struct net_device *netdev = pci_get_drvdata(pdev);
4518 struct igb_adapter *adapter = netdev_priv(netdev);
4519
9d5c8243
AK		 4520 if (netif_running(netdev)) {
4521 if (igb_up(adapter)) {
4522 dev_err(&pdev->dev, "igb_up failed after reset\n");
4523 return;
4524 }
4525 }
4526
4527 netif_device_attach(netdev);
4528
4529 /* let the f/w know that the h/w is now under the control of the
4530 * driver. */
4531 igb_get_hw_control(adapter);
9d5c8243
AK		 4532}
4533
4534/* igb_main.c */
Linux kernel - Deliverables
This page took 0.364241 seconds and 5 git commands to generate.