Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Alchemy Semi Au1000 IrDA driver | |
3 | * | |
4 | * Copyright 2001 MontaVista Software Inc. | |
5 | * Author: MontaVista Software, Inc. | |
6 | * ppopov@mvista.com or source@mvista.com | |
7 | * | |
8 | * This program is free software; you can distribute it and/or modify it | |
9 | * under the terms of the GNU General Public License (Version 2) as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
e8478de3 | 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 | 19 | */ |
cd671c16 | 20 | |
9178af9a | 21 | #include <linux/clk.h> |
cd671c16 | 22 | #include <linux/module.h> |
1da177e4 | 23 | #include <linux/netdevice.h> |
1da177e4 | 24 | #include <linux/interrupt.h> |
cd671c16 ML |
25 | #include <linux/platform_device.h> |
26 | #include <linux/slab.h> | |
27 | #include <linux/time.h> | |
28 | #include <linux/types.h> | |
94d8f2b1 | 29 | #include <linux/ioport.h> |
1da177e4 LT |
30 | |
31 | #include <net/irda/irda.h> | |
32 | #include <net/irda/irmod.h> | |
33 | #include <net/irda/wrapper.h> | |
34 | #include <net/irda/irda_device.h> | |
cd671c16 ML |
35 | #include <asm/mach-au1x00/au1000.h> |
36 | ||
37 | /* registers */ | |
38 | #define IR_RING_PTR_STATUS 0x00 | |
39 | #define IR_RING_BASE_ADDR_H 0x04 | |
40 | #define IR_RING_BASE_ADDR_L 0x08 | |
41 | #define IR_RING_SIZE 0x0C | |
42 | #define IR_RING_PROMPT 0x10 | |
43 | #define IR_RING_ADDR_CMPR 0x14 | |
44 | #define IR_INT_CLEAR 0x18 | |
45 | #define IR_CONFIG_1 0x20 | |
46 | #define IR_SIR_FLAGS 0x24 | |
47 | #define IR_STATUS 0x28 | |
48 | #define IR_READ_PHY_CONFIG 0x2C | |
49 | #define IR_WRITE_PHY_CONFIG 0x30 | |
50 | #define IR_MAX_PKT_LEN 0x34 | |
51 | #define IR_RX_BYTE_CNT 0x38 | |
52 | #define IR_CONFIG_2 0x3C | |
53 | #define IR_ENABLE 0x40 | |
54 | ||
55 | /* Config1 */ | |
56 | #define IR_RX_INVERT_LED (1 << 0) | |
57 | #define IR_TX_INVERT_LED (1 << 1) | |
58 | #define IR_ST (1 << 2) | |
59 | #define IR_SF (1 << 3) | |
60 | #define IR_SIR (1 << 4) | |
61 | #define IR_MIR (1 << 5) | |
62 | #define IR_FIR (1 << 6) | |
63 | #define IR_16CRC (1 << 7) | |
64 | #define IR_TD (1 << 8) | |
65 | #define IR_RX_ALL (1 << 9) | |
66 | #define IR_DMA_ENABLE (1 << 10) | |
67 | #define IR_RX_ENABLE (1 << 11) | |
68 | #define IR_TX_ENABLE (1 << 12) | |
69 | #define IR_LOOPBACK (1 << 14) | |
70 | #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ | |
71 | IR_RX_ALL | IR_RX_ENABLE | IR_SF | \ | |
72 | IR_16CRC) | |
73 | ||
74 | /* ir_status */ | |
75 | #define IR_RX_STATUS (1 << 9) | |
76 | #define IR_TX_STATUS (1 << 10) | |
77 | #define IR_PHYEN (1 << 15) | |
78 | ||
79 | /* ir_write_phy_config */ | |
80 | #define IR_BR(x) (((x) & 0x3f) << 10) /* baud rate */ | |
81 | #define IR_PW(x) (((x) & 0x1f) << 5) /* pulse width */ | |
82 | #define IR_P(x) ((x) & 0x1f) /* preamble bits */ | |
83 | ||
84 | /* Config2 */ | |
85 | #define IR_MODE_INV (1 << 0) | |
86 | #define IR_ONE_PIN (1 << 1) | |
87 | #define IR_PHYCLK_40MHZ (0 << 2) | |
88 | #define IR_PHYCLK_48MHZ (1 << 2) | |
89 | #define IR_PHYCLK_56MHZ (2 << 2) | |
90 | #define IR_PHYCLK_64MHZ (3 << 2) | |
91 | #define IR_DP (1 << 4) | |
92 | #define IR_DA (1 << 5) | |
93 | #define IR_FLT_HIGH (0 << 6) | |
94 | #define IR_FLT_MEDHI (1 << 6) | |
95 | #define IR_FLT_MEDLO (2 << 6) | |
96 | #define IR_FLT_LO (3 << 6) | |
97 | #define IR_IEN (1 << 8) | |
98 | ||
99 | /* ir_enable */ | |
100 | #define IR_HC (1 << 3) /* divide SBUS clock by 2 */ | |
101 | #define IR_CE (1 << 2) /* clock enable */ | |
102 | #define IR_C (1 << 1) /* coherency bit */ | |
103 | #define IR_BE (1 << 0) /* set in big endian mode */ | |
104 | ||
105 | #define NUM_IR_DESC 64 | |
106 | #define RING_SIZE_4 0x0 | |
107 | #define RING_SIZE_16 0x3 | |
108 | #define RING_SIZE_64 0xF | |
109 | #define MAX_NUM_IR_DESC 64 | |
110 | #define MAX_BUF_SIZE 2048 | |
111 | ||
112 | /* Ring descriptor flags */ | |
113 | #define AU_OWN (1 << 7) /* tx,rx */ | |
114 | #define IR_DIS_CRC (1 << 6) /* tx */ | |
115 | #define IR_BAD_CRC (1 << 5) /* tx */ | |
116 | #define IR_NEED_PULSE (1 << 4) /* tx */ | |
117 | #define IR_FORCE_UNDER (1 << 3) /* tx */ | |
118 | #define IR_DISABLE_TX (1 << 2) /* tx */ | |
119 | #define IR_HW_UNDER (1 << 0) /* tx */ | |
120 | #define IR_TX_ERROR (IR_DIS_CRC | IR_BAD_CRC | IR_HW_UNDER) | |
121 | ||
122 | #define IR_PHY_ERROR (1 << 6) /* rx */ | |
123 | #define IR_CRC_ERROR (1 << 5) /* rx */ | |
124 | #define IR_MAX_LEN (1 << 4) /* rx */ | |
125 | #define IR_FIFO_OVER (1 << 3) /* rx */ | |
126 | #define IR_SIR_ERROR (1 << 2) /* rx */ | |
127 | #define IR_RX_ERROR (IR_PHY_ERROR | IR_CRC_ERROR | \ | |
128 | IR_MAX_LEN | IR_FIFO_OVER | IR_SIR_ERROR) | |
129 | ||
130 | struct db_dest { | |
131 | struct db_dest *pnext; | |
132 | volatile u32 *vaddr; | |
133 | dma_addr_t dma_addr; | |
134 | }; | |
135 | ||
136 | struct ring_dest { | |
137 | u8 count_0; /* 7:0 */ | |
138 | u8 count_1; /* 12:8 */ | |
139 | u8 reserved; | |
140 | u8 flags; | |
141 | u8 addr_0; /* 7:0 */ | |
142 | u8 addr_1; /* 15:8 */ | |
143 | u8 addr_2; /* 23:16 */ | |
144 | u8 addr_3; /* 31:24 */ | |
145 | }; | |
146 | ||
147 | /* Private data for each instance */ | |
148 | struct au1k_private { | |
149 | void __iomem *iobase; | |
150 | int irq_rx, irq_tx; | |
151 | ||
152 | struct db_dest *pDBfree; | |
153 | struct db_dest db[2 * NUM_IR_DESC]; | |
154 | volatile struct ring_dest *rx_ring[NUM_IR_DESC]; | |
155 | volatile struct ring_dest *tx_ring[NUM_IR_DESC]; | |
156 | struct db_dest *rx_db_inuse[NUM_IR_DESC]; | |
157 | struct db_dest *tx_db_inuse[NUM_IR_DESC]; | |
158 | u32 rx_head; | |
159 | u32 tx_head; | |
160 | u32 tx_tail; | |
161 | u32 tx_full; | |
162 | ||
163 | iobuff_t rx_buff; | |
164 | ||
165 | struct net_device *netdev; | |
166 | struct timeval stamp; | |
167 | struct timeval now; | |
168 | struct qos_info qos; | |
169 | struct irlap_cb *irlap; | |
170 | ||
171 | u8 open; | |
172 | u32 speed; | |
173 | u32 newspeed; | |
1da177e4 | 174 | |
cd671c16 | 175 | struct timer_list timer; |
1da177e4 | 176 | |
cd671c16 ML |
177 | struct resource *ioarea; |
178 | struct au1k_irda_platform_data *platdata; | |
9178af9a | 179 | struct clk *irda_clk; |
cd671c16 | 180 | }; |
1da177e4 LT |
181 | |
182 | static int qos_mtt_bits = 0x07; /* 1 ms or more */ | |
1da177e4 LT |
183 | |
184 | #define RUN_AT(x) (jiffies + (x)) | |
185 | ||
cd671c16 ML |
186 | static void au1k_irda_plat_set_phy_mode(struct au1k_private *p, int mode) |
187 | { | |
188 | if (p->platdata && p->platdata->set_phy_mode) | |
189 | p->platdata->set_phy_mode(mode); | |
190 | } | |
1da177e4 | 191 | |
cd671c16 ML |
192 | static inline unsigned long irda_read(struct au1k_private *p, |
193 | unsigned long ofs) | |
194 | { | |
195 | /* | |
196 | * IrDA peripheral bug. You have to read the register | |
197 | * twice to get the right value. | |
198 | */ | |
199 | (void)__raw_readl(p->iobase + ofs); | |
200 | return __raw_readl(p->iobase + ofs); | |
1da177e4 LT |
201 | } |
202 | ||
cd671c16 ML |
203 | static inline void irda_write(struct au1k_private *p, unsigned long ofs, |
204 | unsigned long val) | |
205 | { | |
206 | __raw_writel(val, p->iobase + ofs); | |
207 | wmb(); | |
208 | } | |
1da177e4 LT |
209 | |
210 | /* | |
211 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
cd671c16 | 212 | * has the virtual and dma address of a buffer suitable for |
1da177e4 LT |
213 | * both, receive and transmit operations. |
214 | */ | |
cd671c16 | 215 | static struct db_dest *GetFreeDB(struct au1k_private *aup) |
1da177e4 | 216 | { |
cd671c16 ML |
217 | struct db_dest *db; |
218 | db = aup->pDBfree; | |
1da177e4 | 219 | |
cd671c16 ML |
220 | if (db) |
221 | aup->pDBfree = db->pnext; | |
222 | return db; | |
1da177e4 LT |
223 | } |
224 | ||
1da177e4 LT |
225 | /* |
226 | DMA memory allocation, derived from pci_alloc_consistent. | |
227 | However, the Au1000 data cache is coherent (when programmed | |
228 | so), therefore we return KSEG0 address, not KSEG1. | |
229 | */ | |
cd671c16 | 230 | static void *dma_alloc(size_t size, dma_addr_t *dma_handle) |
1da177e4 LT |
231 | { |
232 | void *ret; | |
233 | int gfp = GFP_ATOMIC | GFP_DMA; | |
234 | ||
cd671c16 | 235 | ret = (void *)__get_free_pages(gfp, get_order(size)); |
1da177e4 LT |
236 | |
237 | if (ret != NULL) { | |
238 | memset(ret, 0, size); | |
239 | *dma_handle = virt_to_bus(ret); | |
240 | ret = (void *)KSEG0ADDR(ret); | |
241 | } | |
242 | return ret; | |
243 | } | |
244 | ||
1da177e4 LT |
245 | static void dma_free(void *vaddr, size_t size) |
246 | { | |
247 | vaddr = (void *)KSEG0ADDR(vaddr); | |
248 | free_pages((unsigned long) vaddr, get_order(size)); | |
249 | } | |
250 | ||
251 | ||
cd671c16 | 252 | static void setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base) |
1da177e4 LT |
253 | { |
254 | int i; | |
cd671c16 ML |
255 | for (i = 0; i < NUM_IR_DESC; i++) { |
256 | aup->rx_ring[i] = (volatile struct ring_dest *) | |
257 | (rx_base + sizeof(struct ring_dest) * i); | |
1da177e4 | 258 | } |
cd671c16 ML |
259 | for (i = 0; i < NUM_IR_DESC; i++) { |
260 | aup->tx_ring[i] = (volatile struct ring_dest *) | |
261 | (tx_base + sizeof(struct ring_dest) * i); | |
1da177e4 LT |
262 | } |
263 | } | |
264 | ||
1da177e4 LT |
265 | static int au1k_irda_init_iobuf(iobuff_t *io, int size) |
266 | { | |
267 | io->head = kmalloc(size, GFP_KERNEL); | |
268 | if (io->head != NULL) { | |
cd671c16 ML |
269 | io->truesize = size; |
270 | io->in_frame = FALSE; | |
271 | io->state = OUTSIDE_FRAME; | |
272 | io->data = io->head; | |
1da177e4 LT |
273 | } |
274 | return io->head ? 0 : -ENOMEM; | |
275 | } | |
276 | ||
cd671c16 ML |
277 | /* |
278 | * Set the IrDA communications speed. | |
279 | */ | |
280 | static int au1k_irda_set_speed(struct net_device *dev, int speed) | |
1da177e4 LT |
281 | { |
282 | struct au1k_private *aup = netdev_priv(dev); | |
cd671c16 ML |
283 | volatile struct ring_dest *ptxd; |
284 | unsigned long control; | |
285 | int ret = 0, timeout = 10, i; | |
1da177e4 | 286 | |
cd671c16 ML |
287 | if (speed == aup->speed) |
288 | return ret; | |
1da177e4 | 289 | |
cd671c16 ML |
290 | /* disable PHY first */ |
291 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF); | |
292 | irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN); | |
1da177e4 | 293 | |
cd671c16 ML |
294 | /* disable RX/TX */ |
295 | irda_write(aup, IR_CONFIG_1, | |
296 | irda_read(aup, IR_CONFIG_1) & ~(IR_RX_ENABLE | IR_TX_ENABLE)); | |
297 | msleep(20); | |
298 | while (irda_read(aup, IR_STATUS) & (IR_RX_STATUS | IR_TX_STATUS)) { | |
299 | msleep(20); | |
300 | if (!timeout--) { | |
301 | printk(KERN_ERR "%s: rx/tx disable timeout\n", | |
302 | dev->name); | |
303 | break; | |
304 | } | |
305 | } | |
1da177e4 | 306 | |
cd671c16 ML |
307 | /* disable DMA */ |
308 | irda_write(aup, IR_CONFIG_1, | |
309 | irda_read(aup, IR_CONFIG_1) & ~IR_DMA_ENABLE); | |
310 | msleep(20); | |
1da177e4 | 311 | |
cd671c16 ML |
312 | /* After we disable tx/rx. the index pointers go back to zero. */ |
313 | aup->tx_head = aup->tx_tail = aup->rx_head = 0; | |
314 | for (i = 0; i < NUM_IR_DESC; i++) { | |
315 | ptxd = aup->tx_ring[i]; | |
316 | ptxd->flags = 0; | |
317 | ptxd->count_0 = 0; | |
318 | ptxd->count_1 = 0; | |
319 | } | |
1da177e4 | 320 | |
cd671c16 ML |
321 | for (i = 0; i < NUM_IR_DESC; i++) { |
322 | ptxd = aup->rx_ring[i]; | |
323 | ptxd->count_0 = 0; | |
324 | ptxd->count_1 = 0; | |
325 | ptxd->flags = AU_OWN; | |
326 | } | |
1da177e4 | 327 | |
cd671c16 ML |
328 | if (speed == 4000000) |
329 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_FIR); | |
330 | else | |
331 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR); | |
1da177e4 | 332 | |
cd671c16 ML |
333 | switch (speed) { |
334 | case 9600: | |
335 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(11) | IR_PW(12)); | |
336 | irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); | |
337 | break; | |
338 | case 19200: | |
339 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(5) | IR_PW(12)); | |
340 | irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); | |
341 | break; | |
342 | case 38400: | |
343 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(2) | IR_PW(12)); | |
344 | irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); | |
345 | break; | |
346 | case 57600: | |
347 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_BR(1) | IR_PW(12)); | |
348 | irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); | |
349 | break; | |
350 | case 115200: | |
351 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_PW(12)); | |
352 | irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); | |
353 | break; | |
354 | case 4000000: | |
355 | irda_write(aup, IR_WRITE_PHY_CONFIG, IR_P(15)); | |
356 | irda_write(aup, IR_CONFIG_1, IR_FIR | IR_DMA_ENABLE | | |
357 | IR_RX_ENABLE); | |
358 | break; | |
359 | default: | |
360 | printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed); | |
361 | ret = -EINVAL; | |
362 | break; | |
363 | } | |
1da177e4 | 364 | |
cd671c16 ML |
365 | aup->speed = speed; |
366 | irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) | IR_PHYEN); | |
367 | ||
368 | control = irda_read(aup, IR_STATUS); | |
369 | irda_write(aup, IR_RING_PROMPT, 0); | |
370 | ||
371 | if (control & (1 << 14)) { | |
372 | printk(KERN_ERR "%s: configuration error\n", dev->name); | |
373 | } else { | |
374 | if (control & (1 << 11)) | |
375 | printk(KERN_DEBUG "%s Valid SIR config\n", dev->name); | |
376 | if (control & (1 << 12)) | |
377 | printk(KERN_DEBUG "%s Valid MIR config\n", dev->name); | |
378 | if (control & (1 << 13)) | |
379 | printk(KERN_DEBUG "%s Valid FIR config\n", dev->name); | |
380 | if (control & (1 << 10)) | |
381 | printk(KERN_DEBUG "%s TX enabled\n", dev->name); | |
382 | if (control & (1 << 9)) | |
383 | printk(KERN_DEBUG "%s RX enabled\n", dev->name); | |
1da177e4 | 384 | } |
1da177e4 | 385 | |
cd671c16 ML |
386 | return ret; |
387 | } | |
388 | ||
389 | static void update_rx_stats(struct net_device *dev, u32 status, u32 count) | |
390 | { | |
391 | struct net_device_stats *ps = &dev->stats; | |
392 | ||
393 | ps->rx_packets++; | |
394 | ||
395 | if (status & IR_RX_ERROR) { | |
396 | ps->rx_errors++; | |
397 | if (status & (IR_PHY_ERROR | IR_FIFO_OVER)) | |
398 | ps->rx_missed_errors++; | |
399 | if (status & IR_MAX_LEN) | |
400 | ps->rx_length_errors++; | |
401 | if (status & IR_CRC_ERROR) | |
402 | ps->rx_crc_errors++; | |
403 | } else | |
404 | ps->rx_bytes += count; | |
405 | } | |
406 | ||
407 | static void update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len) | |
408 | { | |
409 | struct net_device_stats *ps = &dev->stats; | |
410 | ||
411 | ps->tx_packets++; | |
412 | ps->tx_bytes += pkt_len; | |
413 | ||
414 | if (status & IR_TX_ERROR) { | |
415 | ps->tx_errors++; | |
416 | ps->tx_aborted_errors++; | |
1da177e4 | 417 | } |
cd671c16 ML |
418 | } |
419 | ||
420 | static void au1k_tx_ack(struct net_device *dev) | |
421 | { | |
422 | struct au1k_private *aup = netdev_priv(dev); | |
423 | volatile struct ring_dest *ptxd; | |
424 | ||
425 | ptxd = aup->tx_ring[aup->tx_tail]; | |
426 | while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) { | |
427 | update_tx_stats(dev, ptxd->flags, | |
428 | (ptxd->count_1 << 8) | ptxd->count_0); | |
429 | ptxd->count_0 = 0; | |
430 | ptxd->count_1 = 0; | |
431 | wmb(); | |
432 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_IR_DESC - 1); | |
433 | ptxd = aup->tx_ring[aup->tx_tail]; | |
434 | ||
435 | if (aup->tx_full) { | |
436 | aup->tx_full = 0; | |
437 | netif_wake_queue(dev); | |
438 | } | |
1da177e4 LT |
439 | } |
440 | ||
cd671c16 ML |
441 | if (aup->tx_tail == aup->tx_head) { |
442 | if (aup->newspeed) { | |
443 | au1k_irda_set_speed(dev, aup->newspeed); | |
444 | aup->newspeed = 0; | |
445 | } else { | |
446 | irda_write(aup, IR_CONFIG_1, | |
447 | irda_read(aup, IR_CONFIG_1) & ~IR_TX_ENABLE); | |
448 | irda_write(aup, IR_CONFIG_1, | |
449 | irda_read(aup, IR_CONFIG_1) | IR_RX_ENABLE); | |
450 | irda_write(aup, IR_RING_PROMPT, 0); | |
451 | } | |
452 | } | |
453 | } | |
1da177e4 | 454 | |
cd671c16 ML |
455 | static int au1k_irda_rx(struct net_device *dev) |
456 | { | |
457 | struct au1k_private *aup = netdev_priv(dev); | |
458 | volatile struct ring_dest *prxd; | |
459 | struct sk_buff *skb; | |
460 | struct db_dest *pDB; | |
461 | u32 flags, count; | |
1da177e4 | 462 | |
cd671c16 ML |
463 | prxd = aup->rx_ring[aup->rx_head]; |
464 | flags = prxd->flags; | |
465 | ||
466 | while (!(flags & AU_OWN)) { | |
467 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
468 | count = (prxd->count_1 << 8) | prxd->count_0; | |
469 | if (!(flags & IR_RX_ERROR)) { | |
470 | /* good frame */ | |
471 | update_rx_stats(dev, flags, count); | |
472 | skb = alloc_skb(count + 1, GFP_ATOMIC); | |
473 | if (skb == NULL) { | |
474 | dev->stats.rx_dropped++; | |
475 | continue; | |
476 | } | |
477 | skb_reserve(skb, 1); | |
478 | if (aup->speed == 4000000) | |
479 | skb_put(skb, count); | |
480 | else | |
481 | skb_put(skb, count - 2); | |
482 | skb_copy_to_linear_data(skb, (void *)pDB->vaddr, | |
483 | count - 2); | |
484 | skb->dev = dev; | |
485 | skb_reset_mac_header(skb); | |
486 | skb->protocol = htons(ETH_P_IRDA); | |
487 | netif_rx(skb); | |
488 | prxd->count_0 = 0; | |
489 | prxd->count_1 = 0; | |
490 | } | |
491 | prxd->flags |= AU_OWN; | |
492 | aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1); | |
493 | irda_write(aup, IR_RING_PROMPT, 0); | |
494 | ||
495 | /* next descriptor */ | |
496 | prxd = aup->rx_ring[aup->rx_head]; | |
497 | flags = prxd->flags; | |
498 | ||
499 | } | |
500 | return 0; | |
1da177e4 LT |
501 | } |
502 | ||
cd671c16 ML |
503 | static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id) |
504 | { | |
505 | struct net_device *dev = dev_id; | |
506 | struct au1k_private *aup = netdev_priv(dev); | |
507 | ||
508 | irda_write(aup, IR_INT_CLEAR, 0); /* ack irda interrupts */ | |
509 | ||
510 | au1k_irda_rx(dev); | |
511 | au1k_tx_ack(dev); | |
512 | ||
513 | return IRQ_HANDLED; | |
514 | } | |
1da177e4 LT |
515 | |
516 | static int au1k_init(struct net_device *dev) | |
517 | { | |
518 | struct au1k_private *aup = netdev_priv(dev); | |
9178af9a ML |
519 | u32 enable, ring_address, phyck; |
520 | struct clk *c; | |
1da177e4 | 521 | int i; |
1da177e4 | 522 | |
9178af9a ML |
523 | c = clk_get(NULL, "irda_clk"); |
524 | if (IS_ERR(c)) | |
525 | return PTR_ERR(c); | |
526 | i = clk_prepare_enable(c); | |
527 | if (i) { | |
528 | clk_put(c); | |
529 | return i; | |
530 | } | |
531 | ||
532 | switch (clk_get_rate(c)) { | |
533 | case 40000000: | |
534 | phyck = IR_PHYCLK_40MHZ; | |
535 | break; | |
536 | case 48000000: | |
537 | phyck = IR_PHYCLK_48MHZ; | |
538 | break; | |
539 | case 56000000: | |
540 | phyck = IR_PHYCLK_56MHZ; | |
541 | break; | |
542 | case 64000000: | |
543 | phyck = IR_PHYCLK_64MHZ; | |
544 | break; | |
545 | default: | |
546 | clk_disable_unprepare(c); | |
547 | clk_put(c); | |
548 | return -EINVAL; | |
549 | } | |
550 | aup->irda_clk = c; | |
551 | ||
cd671c16 | 552 | enable = IR_HC | IR_CE | IR_C; |
1da177e4 | 553 | #ifndef CONFIG_CPU_LITTLE_ENDIAN |
cd671c16 | 554 | enable |= IR_BE; |
1da177e4 LT |
555 | #endif |
556 | aup->tx_head = 0; | |
557 | aup->tx_tail = 0; | |
558 | aup->rx_head = 0; | |
559 | ||
cd671c16 | 560 | for (i = 0; i < NUM_IR_DESC; i++) |
1da177e4 | 561 | aup->rx_ring[i]->flags = AU_OWN; |
1da177e4 | 562 | |
cd671c16 ML |
563 | irda_write(aup, IR_ENABLE, enable); |
564 | msleep(20); | |
1da177e4 | 565 | |
cd671c16 ML |
566 | /* disable PHY */ |
567 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF); | |
568 | irda_write(aup, IR_STATUS, irda_read(aup, IR_STATUS) & ~IR_PHYEN); | |
569 | msleep(20); | |
1da177e4 | 570 | |
cd671c16 | 571 | irda_write(aup, IR_MAX_PKT_LEN, MAX_BUF_SIZE); |
1da177e4 LT |
572 | |
573 | ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]); | |
cd671c16 ML |
574 | irda_write(aup, IR_RING_BASE_ADDR_H, ring_address >> 26); |
575 | irda_write(aup, IR_RING_BASE_ADDR_L, (ring_address >> 10) & 0xffff); | |
1da177e4 | 576 | |
cd671c16 ML |
577 | irda_write(aup, IR_RING_SIZE, |
578 | (RING_SIZE_64 << 8) | (RING_SIZE_64 << 12)); | |
1da177e4 | 579 | |
9178af9a | 580 | irda_write(aup, IR_CONFIG_2, phyck | IR_ONE_PIN); |
cd671c16 | 581 | irda_write(aup, IR_RING_ADDR_CMPR, 0); |
1da177e4 LT |
582 | |
583 | au1k_irda_set_speed(dev, 9600); | |
584 | return 0; | |
585 | } | |
586 | ||
587 | static int au1k_irda_start(struct net_device *dev) | |
588 | { | |
1da177e4 | 589 | struct au1k_private *aup = netdev_priv(dev); |
cd671c16 ML |
590 | char hwname[32]; |
591 | int retval; | |
1da177e4 | 592 | |
cd671c16 ML |
593 | retval = au1k_init(dev); |
594 | if (retval) { | |
1da177e4 LT |
595 | printk(KERN_ERR "%s: error in au1k_init\n", dev->name); |
596 | return retval; | |
597 | } | |
598 | ||
cd671c16 ML |
599 | retval = request_irq(aup->irq_tx, &au1k_irda_interrupt, 0, |
600 | dev->name, dev); | |
601 | if (retval) { | |
602 | printk(KERN_ERR "%s: unable to get IRQ %d\n", | |
1da177e4 LT |
603 | dev->name, dev->irq); |
604 | return retval; | |
605 | } | |
cd671c16 ML |
606 | retval = request_irq(aup->irq_rx, &au1k_irda_interrupt, 0, |
607 | dev->name, dev); | |
608 | if (retval) { | |
609 | free_irq(aup->irq_tx, dev); | |
610 | printk(KERN_ERR "%s: unable to get IRQ %d\n", | |
1da177e4 LT |
611 | dev->name, dev->irq); |
612 | return retval; | |
613 | } | |
614 | ||
615 | /* Give self a hardware name */ | |
616 | sprintf(hwname, "Au1000 SIR/FIR"); | |
617 | aup->irlap = irlap_open(dev, &aup->qos, hwname); | |
618 | netif_start_queue(dev); | |
619 | ||
cd671c16 ML |
620 | /* int enable */ |
621 | irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) | IR_IEN); | |
1da177e4 | 622 | |
cd671c16 ML |
623 | /* power up */ |
624 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR); | |
625 | ||
626 | aup->timer.expires = RUN_AT((3 * HZ)); | |
1da177e4 LT |
627 | aup->timer.data = (unsigned long)dev; |
628 | return 0; | |
629 | } | |
630 | ||
631 | static int au1k_irda_stop(struct net_device *dev) | |
632 | { | |
633 | struct au1k_private *aup = netdev_priv(dev); | |
634 | ||
cd671c16 ML |
635 | au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF); |
636 | ||
1da177e4 | 637 | /* disable interrupts */ |
cd671c16 ML |
638 | irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) & ~IR_IEN); |
639 | irda_write(aup, IR_CONFIG_1, 0); | |
640 | irda_write(aup, IR_ENABLE, 0); /* disable clock */ | |
1da177e4 LT |
641 | |
642 | if (aup->irlap) { | |
643 | irlap_close(aup->irlap); | |
644 | aup->irlap = NULL; | |
645 | } | |
646 | ||
647 | netif_stop_queue(dev); | |
648 | del_timer(&aup->timer); | |
649 | ||
650 | /* disable the interrupt */ | |
cd671c16 ML |
651 | free_irq(aup->irq_tx, dev); |
652 | free_irq(aup->irq_rx, dev); | |
1da177e4 | 653 | |
9178af9a ML |
654 | clk_disable_unprepare(aup->irda_clk); |
655 | clk_put(aup->irda_clk); | |
656 | ||
cd671c16 | 657 | return 0; |
1da177e4 LT |
658 | } |
659 | ||
1da177e4 LT |
660 | /* |
661 | * Au1000 transmit routine. | |
662 | */ | |
663 | static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) | |
664 | { | |
665 | struct au1k_private *aup = netdev_priv(dev); | |
666 | int speed = irda_get_next_speed(skb); | |
cd671c16 ML |
667 | volatile struct ring_dest *ptxd; |
668 | struct db_dest *pDB; | |
669 | u32 len, flags; | |
1da177e4 | 670 | |
cd671c16 | 671 | if (speed != aup->speed && speed != -1) |
1da177e4 | 672 | aup->newspeed = speed; |
1da177e4 LT |
673 | |
674 | if ((skb->len == 0) && (aup->newspeed)) { | |
675 | if (aup->tx_tail == aup->tx_head) { | |
676 | au1k_irda_set_speed(dev, speed); | |
677 | aup->newspeed = 0; | |
678 | } | |
679 | dev_kfree_skb(skb); | |
6ed10654 | 680 | return NETDEV_TX_OK; |
1da177e4 LT |
681 | } |
682 | ||
683 | ptxd = aup->tx_ring[aup->tx_head]; | |
684 | flags = ptxd->flags; | |
685 | ||
686 | if (flags & AU_OWN) { | |
687 | printk(KERN_DEBUG "%s: tx_full\n", dev->name); | |
688 | netif_stop_queue(dev); | |
689 | aup->tx_full = 1; | |
cd671c16 ML |
690 | return 1; |
691 | } else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) { | |
1da177e4 LT |
692 | printk(KERN_DEBUG "%s: tx_full\n", dev->name); |
693 | netif_stop_queue(dev); | |
694 | aup->tx_full = 1; | |
cd671c16 | 695 | return 1; |
1da177e4 LT |
696 | } |
697 | ||
698 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
699 | ||
700 | #if 0 | |
cd671c16 ML |
701 | if (irda_read(aup, IR_RX_BYTE_CNT) != 0) { |
702 | printk(KERN_DEBUG "tx warning: rx byte cnt %x\n", | |
703 | irda_read(aup, IR_RX_BYTE_CNT)); | |
1da177e4 LT |
704 | } |
705 | #endif | |
cd671c16 | 706 | |
1da177e4 LT |
707 | if (aup->speed == 4000000) { |
708 | /* FIR */ | |
cd671c16 | 709 | skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); |
1da177e4 LT |
710 | ptxd->count_0 = skb->len & 0xff; |
711 | ptxd->count_1 = (skb->len >> 8) & 0xff; | |
cd671c16 | 712 | } else { |
1da177e4 LT |
713 | /* SIR */ |
714 | len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE); | |
715 | ptxd->count_0 = len & 0xff; | |
716 | ptxd->count_1 = (len >> 8) & 0xff; | |
717 | ptxd->flags |= IR_DIS_CRC; | |
1da177e4 LT |
718 | } |
719 | ptxd->flags |= AU_OWN; | |
cd671c16 | 720 | wmb(); |
1da177e4 | 721 | |
cd671c16 ML |
722 | irda_write(aup, IR_CONFIG_1, |
723 | irda_read(aup, IR_CONFIG_1) | IR_TX_ENABLE); | |
724 | irda_write(aup, IR_RING_PROMPT, 0); | |
1da177e4 LT |
725 | |
726 | dev_kfree_skb(skb); | |
727 | aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1); | |
6ed10654 | 728 | return NETDEV_TX_OK; |
1da177e4 LT |
729 | } |
730 | ||
1da177e4 LT |
731 | /* |
732 | * The Tx ring has been full longer than the watchdog timeout | |
733 | * value. The transmitter must be hung? | |
734 | */ | |
735 | static void au1k_tx_timeout(struct net_device *dev) | |
736 | { | |
737 | u32 speed; | |
738 | struct au1k_private *aup = netdev_priv(dev); | |
739 | ||
740 | printk(KERN_ERR "%s: tx timeout\n", dev->name); | |
741 | speed = aup->speed; | |
742 | aup->speed = 0; | |
743 | au1k_irda_set_speed(dev, speed); | |
744 | aup->tx_full = 0; | |
745 | netif_wake_queue(dev); | |
746 | } | |
747 | ||
cd671c16 | 748 | static int au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) |
1da177e4 LT |
749 | { |
750 | struct if_irda_req *rq = (struct if_irda_req *)ifreq; | |
751 | struct au1k_private *aup = netdev_priv(dev); | |
752 | int ret = -EOPNOTSUPP; | |
753 | ||
754 | switch (cmd) { | |
755 | case SIOCSBANDWIDTH: | |
756 | if (capable(CAP_NET_ADMIN)) { | |
757 | /* | |
758 | * We are unable to set the speed if the | |
759 | * device is not running. | |
760 | */ | |
761 | if (aup->open) | |
762 | ret = au1k_irda_set_speed(dev, | |
763 | rq->ifr_baudrate); | |
764 | else { | |
765 | printk(KERN_ERR "%s ioctl: !netif_running\n", | |
766 | dev->name); | |
767 | ret = 0; | |
768 | } | |
769 | } | |
770 | break; | |
771 | ||
772 | case SIOCSMEDIABUSY: | |
773 | ret = -EPERM; | |
774 | if (capable(CAP_NET_ADMIN)) { | |
775 | irda_device_set_media_busy(dev, TRUE); | |
776 | ret = 0; | |
777 | } | |
778 | break; | |
779 | ||
780 | case SIOCGRECEIVING: | |
781 | rq->ifr_receiving = 0; | |
782 | break; | |
783 | default: | |
784 | break; | |
785 | } | |
786 | return ret; | |
787 | } | |
788 | ||
cd671c16 ML |
789 | static const struct net_device_ops au1k_irda_netdev_ops = { |
790 | .ndo_open = au1k_irda_start, | |
791 | .ndo_stop = au1k_irda_stop, | |
792 | .ndo_start_xmit = au1k_irda_hard_xmit, | |
793 | .ndo_tx_timeout = au1k_tx_timeout, | |
794 | .ndo_do_ioctl = au1k_irda_ioctl, | |
795 | }; | |
796 | ||
45ac936c | 797 | static int au1k_irda_net_init(struct net_device *dev) |
cd671c16 ML |
798 | { |
799 | struct au1k_private *aup = netdev_priv(dev); | |
800 | struct db_dest *pDB, *pDBfree; | |
801 | int i, err, retval = 0; | |
802 | dma_addr_t temp; | |
803 | ||
804 | err = au1k_irda_init_iobuf(&aup->rx_buff, 14384); | |
805 | if (err) | |
806 | goto out1; | |
807 | ||
808 | dev->netdev_ops = &au1k_irda_netdev_ops; | |
809 | ||
810 | irda_init_max_qos_capabilies(&aup->qos); | |
811 | ||
812 | /* The only value we must override it the baudrate */ | |
813 | aup->qos.baud_rate.bits = IR_9600 | IR_19200 | IR_38400 | | |
814 | IR_57600 | IR_115200 | IR_576000 | (IR_4000000 << 8); | |
815 | ||
816 | aup->qos.min_turn_time.bits = qos_mtt_bits; | |
817 | irda_qos_bits_to_value(&aup->qos); | |
818 | ||
819 | retval = -ENOMEM; | |
820 | ||
821 | /* Tx ring follows rx ring + 512 bytes */ | |
822 | /* we need a 1k aligned buffer */ | |
823 | aup->rx_ring[0] = (struct ring_dest *) | |
824 | dma_alloc(2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest)), | |
825 | &temp); | |
826 | if (!aup->rx_ring[0]) | |
827 | goto out2; | |
828 | ||
829 | /* allocate the data buffers */ | |
830 | aup->db[0].vaddr = | |
c2fd03a0 | 831 | dma_alloc(MAX_BUF_SIZE * 2 * NUM_IR_DESC, &temp); |
cd671c16 ML |
832 | if (!aup->db[0].vaddr) |
833 | goto out3; | |
834 | ||
835 | setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512); | |
836 | ||
837 | pDBfree = NULL; | |
838 | pDB = aup->db; | |
839 | for (i = 0; i < (2 * NUM_IR_DESC); i++) { | |
840 | pDB->pnext = pDBfree; | |
841 | pDBfree = pDB; | |
842 | pDB->vaddr = | |
843 | (u32 *)((unsigned)aup->db[0].vaddr + (MAX_BUF_SIZE * i)); | |
844 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
845 | pDB++; | |
846 | } | |
847 | aup->pDBfree = pDBfree; | |
848 | ||
849 | /* attach a data buffer to each descriptor */ | |
850 | for (i = 0; i < NUM_IR_DESC; i++) { | |
851 | pDB = GetFreeDB(aup); | |
852 | if (!pDB) | |
853 | goto out3; | |
854 | aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); | |
855 | aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr >> 8) & 0xff); | |
856 | aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff); | |
857 | aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff); | |
858 | aup->rx_db_inuse[i] = pDB; | |
859 | } | |
860 | for (i = 0; i < NUM_IR_DESC; i++) { | |
861 | pDB = GetFreeDB(aup); | |
862 | if (!pDB) | |
863 | goto out3; | |
864 | aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); | |
865 | aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr >> 8) & 0xff); | |
866 | aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr >> 16) & 0xff); | |
867 | aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr >> 24) & 0xff); | |
868 | aup->tx_ring[i]->count_0 = 0; | |
869 | aup->tx_ring[i]->count_1 = 0; | |
870 | aup->tx_ring[i]->flags = 0; | |
871 | aup->tx_db_inuse[i] = pDB; | |
872 | } | |
873 | ||
874 | return 0; | |
875 | ||
876 | out3: | |
877 | dma_free((void *)aup->rx_ring[0], | |
878 | 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest))); | |
879 | out2: | |
880 | kfree(aup->rx_buff.head); | |
881 | out1: | |
882 | printk(KERN_ERR "au1k_irda_net_init() failed. Returns %d\n", retval); | |
883 | return retval; | |
884 | } | |
885 | ||
45ac936c | 886 | static int au1k_irda_probe(struct platform_device *pdev) |
cd671c16 ML |
887 | { |
888 | struct au1k_private *aup; | |
889 | struct net_device *dev; | |
890 | struct resource *r; | |
9178af9a | 891 | struct clk *c; |
cd671c16 ML |
892 | int err; |
893 | ||
894 | dev = alloc_irdadev(sizeof(struct au1k_private)); | |
895 | if (!dev) | |
896 | return -ENOMEM; | |
897 | ||
898 | aup = netdev_priv(dev); | |
899 | ||
900 | aup->platdata = pdev->dev.platform_data; | |
901 | ||
902 | err = -EINVAL; | |
903 | r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
904 | if (!r) | |
905 | goto out; | |
906 | ||
907 | aup->irq_tx = r->start; | |
908 | ||
909 | r = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | |
910 | if (!r) | |
911 | goto out; | |
912 | ||
913 | aup->irq_rx = r->start; | |
914 | ||
915 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
916 | if (!r) | |
917 | goto out; | |
918 | ||
919 | err = -EBUSY; | |
94d8f2b1 | 920 | aup->ioarea = request_mem_region(r->start, resource_size(r), |
cd671c16 ML |
921 | pdev->name); |
922 | if (!aup->ioarea) | |
923 | goto out; | |
924 | ||
9178af9a ML |
925 | /* bail out early if clock doesn't exist */ |
926 | c = clk_get(NULL, "irda_clk"); | |
927 | if (IS_ERR(c)) { | |
928 | err = PTR_ERR(c); | |
929 | goto out; | |
930 | } | |
931 | clk_put(c); | |
932 | ||
94d8f2b1 | 933 | aup->iobase = ioremap_nocache(r->start, resource_size(r)); |
cd671c16 ML |
934 | if (!aup->iobase) |
935 | goto out2; | |
936 | ||
937 | dev->irq = aup->irq_rx; | |
938 | ||
939 | err = au1k_irda_net_init(dev); | |
940 | if (err) | |
941 | goto out3; | |
942 | err = register_netdev(dev); | |
943 | if (err) | |
944 | goto out4; | |
945 | ||
946 | platform_set_drvdata(pdev, dev); | |
947 | ||
948 | printk(KERN_INFO "IrDA: Registered device %s\n", dev->name); | |
949 | return 0; | |
950 | ||
951 | out4: | |
952 | dma_free((void *)aup->db[0].vaddr, | |
953 | MAX_BUF_SIZE * 2 * NUM_IR_DESC); | |
954 | dma_free((void *)aup->rx_ring[0], | |
955 | 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest))); | |
956 | kfree(aup->rx_buff.head); | |
957 | out3: | |
958 | iounmap(aup->iobase); | |
959 | out2: | |
960 | release_resource(aup->ioarea); | |
961 | kfree(aup->ioarea); | |
962 | out: | |
963 | free_netdev(dev); | |
964 | return err; | |
965 | } | |
966 | ||
45ac936c | 967 | static int au1k_irda_remove(struct platform_device *pdev) |
cd671c16 ML |
968 | { |
969 | struct net_device *dev = platform_get_drvdata(pdev); | |
970 | struct au1k_private *aup = netdev_priv(dev); | |
971 | ||
972 | unregister_netdev(dev); | |
973 | ||
974 | dma_free((void *)aup->db[0].vaddr, | |
975 | MAX_BUF_SIZE * 2 * NUM_IR_DESC); | |
976 | dma_free((void *)aup->rx_ring[0], | |
977 | 2 * MAX_NUM_IR_DESC * (sizeof(struct ring_dest))); | |
978 | kfree(aup->rx_buff.head); | |
979 | ||
980 | iounmap(aup->iobase); | |
981 | release_resource(aup->ioarea); | |
982 | kfree(aup->ioarea); | |
983 | ||
984 | free_netdev(dev); | |
985 | ||
986 | return 0; | |
987 | } | |
988 | ||
989 | static struct platform_driver au1k_irda_driver = { | |
990 | .driver = { | |
991 | .name = "au1000-irda", | |
992 | .owner = THIS_MODULE, | |
993 | }, | |
994 | .probe = au1k_irda_probe, | |
45ac936c | 995 | .remove = au1k_irda_remove, |
cd671c16 ML |
996 | }; |
997 | ||
95d158df | 998 | module_platform_driver(au1k_irda_driver); |
cd671c16 | 999 | |
1da177e4 LT |
1000 | MODULE_AUTHOR("Pete Popov <ppopov@mvista.com>"); |
1001 | MODULE_DESCRIPTION("Au1000 IrDA Device Driver"); |