ipv6: Fix return of xfrm6_tunnel_rcv()
[deliverable/linux.git] / drivers / net / irda / bfin_sir.h
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1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2009 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/delay.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
5a0e3ad6 19#include <linux/slab.h>
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20
21#include <net/irda/irda.h>
22#include <net/irda/wrapper.h>
23#include <net/irda/irda_device.h>
24
25#include <asm/irq.h>
26#include <asm/cacheflush.h>
27#include <asm/dma.h>
28#include <asm/portmux.h>
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29#include <mach/bfin_serial_5xx.h>
30#undef DRIVER_NAME
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31
32#ifdef CONFIG_SIR_BFIN_DMA
33struct dma_rx_buf {
34 char *buf;
35 int head;
36 int tail;
37};
38#endif
39
40struct bfin_sir_port {
41 unsigned char __iomem *membase;
42 unsigned int irq;
43 unsigned int lsr;
44 unsigned long clk;
45 struct net_device *dev;
46#ifdef CONFIG_SIR_BFIN_DMA
47 int tx_done;
48 struct dma_rx_buf rx_dma_buf;
49 struct timer_list rx_dma_timer;
50 int rx_dma_nrows;
51#endif
52 unsigned int tx_dma_channel;
53 unsigned int rx_dma_channel;
54};
55
56struct bfin_sir_port_res {
57 unsigned long base_addr;
58 int irq;
59 unsigned int rx_dma_channel;
60 unsigned int tx_dma_channel;
61};
62
63struct bfin_sir_self {
64 struct bfin_sir_port *sir_port;
65 spinlock_t lock;
66 unsigned int open;
67 int speed;
68 int newspeed;
69
70 struct sk_buff *txskb;
71 struct sk_buff *rxskb;
72 struct net_device_stats stats;
73 struct device *dev;
74 struct irlap_cb *irlap;
75 struct qos_info qos;
76
77 iobuff_t tx_buff;
78 iobuff_t rx_buff;
79
80 struct work_struct work;
81 int mtt;
82};
83
84#define DRIVER_NAME "bfin_sir"
85
86#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
87#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
88#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
89#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
90#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
91
92#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
93#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
94#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
95#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
96#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
97
98#ifdef CONFIG_BF54x
99#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
100#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
101#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
102#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
103#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
104#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
105
106#define SIR_UART_SET_DLAB(port)
107#define SIR_UART_CLEAR_DLAB(port)
108
109#define SIR_UART_ENABLE_INTS(port, v) SIR_UART_SET_IER(port, v)
110#define SIR_UART_DISABLE_INTS(port) SIR_UART_CLEAR_IER(port, 0xF)
111#define SIR_UART_STOP_TX(port) do { SIR_UART_PUT_LSR(port, TFI); SIR_UART_CLEAR_IER(port, ETBEI); } while (0)
112#define SIR_UART_ENABLE_TX(port) do { SIR_UART_SET_IER(port, ETBEI); } while (0)
113#define SIR_UART_STOP_RX(port) do { SIR_UART_CLEAR_IER(port, ERBFI); } while (0)
114#define SIR_UART_ENABLE_RX(port) do { SIR_UART_SET_IER(port, ERBFI); } while (0)
115#else
116
117#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
118#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
119#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
120
121#define SIR_UART_SET_DLAB(port) do { SIR_UART_PUT_LCR(port, SIR_UART_GET_LCR(port) | DLAB); } while (0)
122#define SIR_UART_CLEAR_DLAB(port) do { SIR_UART_PUT_LCR(port, SIR_UART_GET_LCR(port) & ~DLAB); } while (0)
123
124#define SIR_UART_ENABLE_INTS(port, v) SIR_UART_PUT_IER(port, v)
125#define SIR_UART_DISABLE_INTS(port) SIR_UART_PUT_IER(port, 0)
126#define SIR_UART_STOP_TX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) & ~ETBEI); } while (0)
127#define SIR_UART_ENABLE_TX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) | ETBEI); } while (0)
128#define SIR_UART_STOP_RX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) & ~ERBFI); } while (0)
129#define SIR_UART_ENABLE_RX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) | ERBFI); } while (0)
130
131static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
132{
133 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
134 port->lsr |= (lsr & (BI|FE|PE|OE));
135 return lsr | port->lsr;
136}
137
138static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
139{
140 port->lsr = 0;
141 bfin_read16(port->membase + OFFSET_LSR);
142}
143#endif
144
145static const unsigned short per[][4] = {
146 /* rx pin tx pin NULL uart_number */
147 {P_UART0_RX, P_UART0_TX, 0, 0},
148 {P_UART1_RX, P_UART1_TX, 0, 1},
149 {P_UART2_RX, P_UART2_TX, 0, 2},
150 {P_UART3_RX, P_UART3_TX, 0, 3},
151};
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