iwlwifi: don't include iwl-dev.h from iwl-devtrace.h
[deliverable/linux.git] / drivers / net / irda / bfin_sir.h
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1/*
2 * Blackfin Infra-red Driver
3 *
4 * Copyright 2006-2009 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 *
10 */
11
12#include <linux/serial.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/delay.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19
20#include <net/irda/irda.h>
21#include <net/irda/wrapper.h>
22#include <net/irda/irda_device.h>
23
24#include <asm/irq.h>
25#include <asm/cacheflush.h>
26#include <asm/dma.h>
27#include <asm/portmux.h>
28
29#ifdef CONFIG_SIR_BFIN_DMA
30struct dma_rx_buf {
31 char *buf;
32 int head;
33 int tail;
34};
35#endif
36
37struct bfin_sir_port {
38 unsigned char __iomem *membase;
39 unsigned int irq;
40 unsigned int lsr;
41 unsigned long clk;
42 struct net_device *dev;
43#ifdef CONFIG_SIR_BFIN_DMA
44 int tx_done;
45 struct dma_rx_buf rx_dma_buf;
46 struct timer_list rx_dma_timer;
47 int rx_dma_nrows;
48#endif
49 unsigned int tx_dma_channel;
50 unsigned int rx_dma_channel;
51};
52
53struct bfin_sir_port_res {
54 unsigned long base_addr;
55 int irq;
56 unsigned int rx_dma_channel;
57 unsigned int tx_dma_channel;
58};
59
60struct bfin_sir_self {
61 struct bfin_sir_port *sir_port;
62 spinlock_t lock;
63 unsigned int open;
64 int speed;
65 int newspeed;
66
67 struct sk_buff *txskb;
68 struct sk_buff *rxskb;
69 struct net_device_stats stats;
70 struct device *dev;
71 struct irlap_cb *irlap;
72 struct qos_info qos;
73
74 iobuff_t tx_buff;
75 iobuff_t rx_buff;
76
77 struct work_struct work;
78 int mtt;
79};
80
81#define DRIVER_NAME "bfin_sir"
82
83#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
84#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
85#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
86#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
87#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
88
89#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
90#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
91#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
92#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
93#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
94
95#ifdef CONFIG_BF54x
96#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
97#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
98#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
99#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
100#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
101#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
102
103#define SIR_UART_SET_DLAB(port)
104#define SIR_UART_CLEAR_DLAB(port)
105
106#define SIR_UART_ENABLE_INTS(port, v) SIR_UART_SET_IER(port, v)
107#define SIR_UART_DISABLE_INTS(port) SIR_UART_CLEAR_IER(port, 0xF)
108#define SIR_UART_STOP_TX(port) do { SIR_UART_PUT_LSR(port, TFI); SIR_UART_CLEAR_IER(port, ETBEI); } while (0)
109#define SIR_UART_ENABLE_TX(port) do { SIR_UART_SET_IER(port, ETBEI); } while (0)
110#define SIR_UART_STOP_RX(port) do { SIR_UART_CLEAR_IER(port, ERBFI); } while (0)
111#define SIR_UART_ENABLE_RX(port) do { SIR_UART_SET_IER(port, ERBFI); } while (0)
112#else
113
114#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
115#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
116#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
117
118#define SIR_UART_SET_DLAB(port) do { SIR_UART_PUT_LCR(port, SIR_UART_GET_LCR(port) | DLAB); } while (0)
119#define SIR_UART_CLEAR_DLAB(port) do { SIR_UART_PUT_LCR(port, SIR_UART_GET_LCR(port) & ~DLAB); } while (0)
120
121#define SIR_UART_ENABLE_INTS(port, v) SIR_UART_PUT_IER(port, v)
122#define SIR_UART_DISABLE_INTS(port) SIR_UART_PUT_IER(port, 0)
123#define SIR_UART_STOP_TX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) & ~ETBEI); } while (0)
124#define SIR_UART_ENABLE_TX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) | ETBEI); } while (0)
125#define SIR_UART_STOP_RX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) & ~ERBFI); } while (0)
126#define SIR_UART_ENABLE_RX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) | ERBFI); } while (0)
127
128static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
129{
130 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
131 port->lsr |= (lsr & (BI|FE|PE|OE));
132 return lsr | port->lsr;
133}
134
135static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
136{
137 port->lsr = 0;
138 bfin_read16(port->membase + OFFSET_LSR);
139}
140#endif
141
142static const unsigned short per[][4] = {
143 /* rx pin tx pin NULL uart_number */
144 {P_UART0_RX, P_UART0_TX, 0, 0},
145 {P_UART1_RX, P_UART1_TX, 0, 1},
146 {P_UART2_RX, P_UART2_TX, 0, 2},
147 {P_UART3_RX, P_UART3_TX, 0, 3},
148};
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