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1da177e4 LT |
1 | /********************************************************************* |
2 | * | |
3 | * Filename: nsc-ircc.c | |
4 | * Version: 1.0 | |
5 | * Description: Driver for the NSC PC'108 and PC'338 IrDA chipsets | |
6 | * Status: Stable. | |
7 | * Author: Dag Brattli <dagb@cs.uit.no> | |
8 | * Created at: Sat Nov 7 21:43:15 1998 | |
9 | * Modified at: Wed Mar 1 11:29:34 2000 | |
10 | * Modified by: Dag Brattli <dagb@cs.uit.no> | |
11 | * | |
12 | * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no> | |
13 | * Copyright (c) 1998 Lichen Wang, <lwang@actisys.com> | |
14 | * Copyright (c) 1998 Actisys Corp., www.actisys.com | |
ec4f32d5 | 15 | * Copyright (c) 2000-2004 Jean Tourrilhes <jt@hpl.hp.com> |
1da177e4 LT |
16 | * All Rights Reserved |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License as | |
20 | * published by the Free Software Foundation; either version 2 of | |
21 | * the License, or (at your option) any later version. | |
22 | * | |
96de0e25 | 23 | * Neither Dag Brattli nor University of Tromsø admit liability nor |
1da177e4 LT |
24 | * provide warranty for any of this software. This material is |
25 | * provided "AS-IS" and at no charge. | |
26 | * | |
27 | * Notice that all functions that needs to access the chip in _any_ | |
28 | * way, must save BSR register on entry, and restore it on exit. | |
29 | * It is _very_ important to follow this policy! | |
30 | * | |
31 | * __u8 bank; | |
32 | * | |
33 | * bank = inb(iobase+BSR); | |
34 | * | |
35 | * do_your_stuff_here(); | |
36 | * | |
37 | * outb(bank, iobase+BSR); | |
38 | * | |
39 | * If you find bugs in this file, its very likely that the same bug | |
40 | * will also be in w83977af_ir.c since the implementations are quite | |
41 | * similar. | |
42 | * | |
43 | ********************************************************************/ | |
44 | ||
45 | #include <linux/module.h> | |
5a0e3ad6 | 46 | #include <linux/gfp.h> |
1da177e4 LT |
47 | |
48 | #include <linux/kernel.h> | |
49 | #include <linux/types.h> | |
50 | #include <linux/skbuff.h> | |
51 | #include <linux/netdevice.h> | |
52 | #include <linux/ioport.h> | |
53 | #include <linux/delay.h> | |
1da177e4 | 54 | #include <linux/init.h> |
a6b7a407 | 55 | #include <linux/interrupt.h> |
1da177e4 LT |
56 | #include <linux/rtnetlink.h> |
57 | #include <linux/dma-mapping.h> | |
ec4f32d5 | 58 | #include <linux/pnp.h> |
3b99b93b | 59 | #include <linux/platform_device.h> |
1da177e4 LT |
60 | |
61 | #include <asm/io.h> | |
62 | #include <asm/dma.h> | |
63 | #include <asm/byteorder.h> | |
64 | ||
1da177e4 LT |
65 | #include <net/irda/wrapper.h> |
66 | #include <net/irda/irda.h> | |
67 | #include <net/irda/irda_device.h> | |
68 | ||
69 | #include "nsc-ircc.h" | |
70 | ||
71 | #define CHIP_IO_EXTENT 8 | |
72 | #define BROKEN_DONGLE_ID | |
73 | ||
74 | static char *driver_name = "nsc-ircc"; | |
75 | ||
3b99b93b DT |
76 | /* Power Management */ |
77 | #define NSC_IRCC_DRIVER_NAME "nsc-ircc" | |
78 | static int nsc_ircc_suspend(struct platform_device *dev, pm_message_t state); | |
79 | static int nsc_ircc_resume(struct platform_device *dev); | |
80 | ||
81 | static struct platform_driver nsc_ircc_driver = { | |
82 | .suspend = nsc_ircc_suspend, | |
83 | .resume = nsc_ircc_resume, | |
84 | .driver = { | |
85 | .name = NSC_IRCC_DRIVER_NAME, | |
86 | }, | |
87 | }; | |
88 | ||
1da177e4 LT |
89 | /* Module parameters */ |
90 | static int qos_mtt_bits = 0x07; /* 1 ms or more */ | |
91 | static int dongle_id; | |
92 | ||
93 | /* Use BIOS settions by default, but user may supply module parameters */ | |
0ed79c9b JT |
94 | static unsigned int io[] = { ~0, ~0, ~0, ~0, ~0 }; |
95 | static unsigned int irq[] = { 0, 0, 0, 0, 0 }; | |
96 | static unsigned int dma[] = { 0, 0, 0, 0, 0 }; | |
1da177e4 LT |
97 | |
98 | static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info); | |
99 | static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info); | |
100 | static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info); | |
101 | static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info); | |
102 | static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info); | |
103 | static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info); | |
c17f888f | 104 | #ifdef CONFIG_PNP |
ec4f32d5 | 105 | static int nsc_ircc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id); |
c17f888f | 106 | #endif |
1da177e4 LT |
107 | |
108 | /* These are the known NSC chips */ | |
109 | static nsc_chip_t chips[] = { | |
110 | /* Name, {cfg registers}, chip id index reg, chip id expected value, revision mask */ | |
111 | { "PC87108", { 0x150, 0x398, 0xea }, 0x05, 0x10, 0xf0, | |
112 | nsc_ircc_probe_108, nsc_ircc_init_108 }, | |
113 | { "PC87338", { 0x398, 0x15c, 0x2e }, 0x08, 0xb0, 0xf8, | |
114 | nsc_ircc_probe_338, nsc_ircc_init_338 }, | |
115 | /* Contributed by Steffen Pingel - IBM X40 */ | |
2fd19a68 | 116 | { "PC8738x", { 0x164e, 0x4e, 0x2e }, 0x20, 0xf4, 0xff, |
1da177e4 LT |
117 | nsc_ircc_probe_39x, nsc_ircc_init_39x }, |
118 | /* Contributed by Jan Frey - IBM A30/A31 */ | |
119 | { "PC8739x", { 0x2e, 0x4e, 0x0 }, 0x20, 0xea, 0xff, | |
120 | nsc_ircc_probe_39x, nsc_ircc_init_39x }, | |
d83561a4 BC |
121 | /* IBM ThinkPads using PC8738x (T60/X60/Z60) */ |
122 | { "IBM-PC8738x", { 0x2e, 0x4e, 0x0 }, 0x20, 0xf4, 0xff, | |
123 | nsc_ircc_probe_39x, nsc_ircc_init_39x }, | |
124 | /* IBM ThinkPads using PC8394T (T43/R52/?) */ | |
125 | { "IBM-PC8394T", { 0x2e, 0x4e, 0x0 }, 0x20, 0xf9, 0xff, | |
126 | nsc_ircc_probe_39x, nsc_ircc_init_39x }, | |
1da177e4 LT |
127 | { NULL } |
128 | }; | |
129 | ||
0ed79c9b | 130 | static struct nsc_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL, NULL }; |
1da177e4 LT |
131 | |
132 | static char *dongle_types[] = { | |
133 | "Differential serial interface", | |
134 | "Differential serial interface", | |
135 | "Reserved", | |
136 | "Reserved", | |
137 | "Sharp RY5HD01", | |
138 | "Reserved", | |
139 | "Single-ended serial interface", | |
140 | "Consumer-IR only", | |
141 | "HP HSDL-2300, HP HSDL-3600/HSDL-3610", | |
142 | "IBM31T1100 or Temic TFDS6000/TFDS6500", | |
143 | "Reserved", | |
144 | "Reserved", | |
145 | "HP HSDL-1100/HSDL-2100", | |
146 | "HP HSDL-1100/HSDL-2100", | |
147 | "Supports SIR Mode only", | |
148 | "No dongle connected", | |
149 | }; | |
150 | ||
ec4f32d5 JT |
151 | /* PNP probing */ |
152 | static chipio_t pnp_info; | |
153 | static const struct pnp_device_id nsc_ircc_pnp_table[] = { | |
154 | { .id = "NSC6001", .driver_data = 0 }, | |
02307080 | 155 | { .id = "HWPC224", .driver_data = 0 }, |
1fa98174 | 156 | { .id = "IBM0071", .driver_data = NSC_FORCE_DONGLE_TYPE9 }, |
ec4f32d5 JT |
157 | { } |
158 | }; | |
159 | ||
160 | MODULE_DEVICE_TABLE(pnp, nsc_ircc_pnp_table); | |
161 | ||
162 | static struct pnp_driver nsc_ircc_pnp_driver = { | |
c17f888f | 163 | #ifdef CONFIG_PNP |
ec4f32d5 JT |
164 | .name = "nsc-ircc", |
165 | .id_table = nsc_ircc_pnp_table, | |
166 | .probe = nsc_ircc_pnp_probe, | |
c17f888f | 167 | #endif |
ec4f32d5 JT |
168 | }; |
169 | ||
1da177e4 | 170 | /* Some prototypes */ |
ec4f32d5 | 171 | static int nsc_ircc_open(chipio_t *info); |
1da177e4 LT |
172 | static int nsc_ircc_close(struct nsc_ircc_cb *self); |
173 | static int nsc_ircc_setup(chipio_t *info); | |
174 | static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self); | |
175 | static int nsc_ircc_dma_receive(struct nsc_ircc_cb *self); | |
176 | static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase); | |
6518bbb8 SH |
177 | static netdev_tx_t nsc_ircc_hard_xmit_sir(struct sk_buff *skb, |
178 | struct net_device *dev); | |
179 | static netdev_tx_t nsc_ircc_hard_xmit_fir(struct sk_buff *skb, | |
180 | struct net_device *dev); | |
1da177e4 LT |
181 | static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size); |
182 | static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase); | |
183 | static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 baud); | |
184 | static int nsc_ircc_is_receiving(struct nsc_ircc_cb *self); | |
185 | static int nsc_ircc_read_dongle_id (int iobase); | |
186 | static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id); | |
187 | ||
188 | static int nsc_ircc_net_open(struct net_device *dev); | |
189 | static int nsc_ircc_net_close(struct net_device *dev); | |
190 | static int nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
1da177e4 | 191 | |
ec4f32d5 JT |
192 | /* Globals */ |
193 | static int pnp_registered; | |
194 | static int pnp_succeeded; | |
195 | ||
1da177e4 LT |
196 | /* |
197 | * Function nsc_ircc_init () | |
198 | * | |
199 | * Initialize chip. Just try to find out how many chips we are dealing with | |
200 | * and where they are | |
201 | */ | |
202 | static int __init nsc_ircc_init(void) | |
203 | { | |
204 | chipio_t info; | |
205 | nsc_chip_t *chip; | |
ec4f32d5 | 206 | int ret; |
1da177e4 LT |
207 | int cfg_base; |
208 | int cfg, id; | |
209 | int reg; | |
210 | int i = 0; | |
211 | ||
3b99b93b DT |
212 | ret = platform_driver_register(&nsc_ircc_driver); |
213 | if (ret) { | |
6c91023d JP |
214 | net_err_ratelimited("%s, Can't register driver!\n", |
215 | driver_name); | |
3b99b93b DT |
216 | return ret; |
217 | } | |
218 | ||
ec4f32d5 JT |
219 | /* Register with PnP subsystem to detect disable ports */ |
220 | ret = pnp_register_driver(&nsc_ircc_pnp_driver); | |
221 | ||
803d0abb | 222 | if (!ret) |
ec4f32d5 JT |
223 | pnp_registered = 1; |
224 | ||
225 | ret = -ENODEV; | |
226 | ||
1da177e4 | 227 | /* Probe for all the NSC chipsets we know about */ |
ec4f32d5 | 228 | for (chip = chips; chip->name ; chip++) { |
955a9d20 JP |
229 | pr_debug("%s(), Probing for %s ...\n", __func__, |
230 | chip->name); | |
1da177e4 LT |
231 | |
232 | /* Try all config registers for this chip */ | |
ec4f32d5 | 233 | for (cfg = 0; cfg < ARRAY_SIZE(chip->cfg); cfg++) { |
1da177e4 LT |
234 | cfg_base = chip->cfg[cfg]; |
235 | if (!cfg_base) | |
236 | continue; | |
1da177e4 LT |
237 | |
238 | /* Read index register */ | |
239 | reg = inb(cfg_base); | |
240 | if (reg == 0xff) { | |
955a9d20 JP |
241 | pr_debug("%s() no chip at 0x%03x\n", |
242 | __func__, cfg_base); | |
1da177e4 LT |
243 | continue; |
244 | } | |
245 | ||
246 | /* Read chip identification register */ | |
247 | outb(chip->cid_index, cfg_base); | |
248 | id = inb(cfg_base+1); | |
249 | if ((id & chip->cid_mask) == chip->cid_value) { | |
955a9d20 JP |
250 | pr_debug("%s() Found %s chip, revision=%d\n", |
251 | __func__, chip->name, | |
252 | id & ~chip->cid_mask); | |
ec4f32d5 JT |
253 | |
254 | /* | |
255 | * If we found a correct PnP setting, | |
256 | * we first try it. | |
257 | */ | |
258 | if (pnp_succeeded) { | |
259 | memset(&info, 0, sizeof(chipio_t)); | |
260 | info.cfg_base = cfg_base; | |
261 | info.fir_base = pnp_info.fir_base; | |
262 | info.dma = pnp_info.dma; | |
263 | info.irq = pnp_info.irq; | |
264 | ||
265 | if (info.fir_base < 0x2000) { | |
6c91023d JP |
266 | net_info_ratelimited("%s, chip->init\n", |
267 | driver_name); | |
ec4f32d5 JT |
268 | chip->init(chip, &info); |
269 | } else | |
270 | chip->probe(chip, &info); | |
271 | ||
272 | if (nsc_ircc_open(&info) >= 0) | |
273 | ret = 0; | |
274 | } | |
275 | ||
276 | /* | |
277 | * Opening based on PnP values failed. | |
278 | * Let's fallback to user values, or probe | |
279 | * the chip. | |
280 | */ | |
281 | if (ret) { | |
955a9d20 JP |
282 | pr_debug("%s, PnP init failed\n", |
283 | driver_name); | |
ec4f32d5 JT |
284 | memset(&info, 0, sizeof(chipio_t)); |
285 | info.cfg_base = cfg_base; | |
286 | info.fir_base = io[i]; | |
287 | info.dma = dma[i]; | |
288 | info.irq = irq[i]; | |
289 | ||
290 | /* | |
291 | * If the user supplies the base address, then | |
292 | * we init the chip, if not we probe the values | |
293 | * set by the BIOS | |
294 | */ | |
295 | if (io[i] < 0x2000) { | |
296 | chip->init(chip, &info); | |
297 | } else | |
298 | chip->probe(chip, &info); | |
299 | ||
300 | if (nsc_ircc_open(&info) >= 0) | |
301 | ret = 0; | |
302 | } | |
1da177e4 LT |
303 | i++; |
304 | } else { | |
955a9d20 JP |
305 | pr_debug("%s(), Wrong chip id=0x%02x\n", |
306 | __func__, id); | |
1da177e4 LT |
307 | } |
308 | } | |
ec4f32d5 JT |
309 | } |
310 | ||
311 | if (ret) { | |
3b99b93b | 312 | platform_driver_unregister(&nsc_ircc_driver); |
ec4f32d5 JT |
313 | pnp_unregister_driver(&nsc_ircc_pnp_driver); |
314 | pnp_registered = 0; | |
1da177e4 LT |
315 | } |
316 | ||
317 | return ret; | |
318 | } | |
319 | ||
320 | /* | |
321 | * Function nsc_ircc_cleanup () | |
322 | * | |
323 | * Close all configured chips | |
324 | * | |
325 | */ | |
326 | static void __exit nsc_ircc_cleanup(void) | |
327 | { | |
328 | int i; | |
329 | ||
ec4f32d5 | 330 | for (i = 0; i < ARRAY_SIZE(dev_self); i++) { |
1da177e4 LT |
331 | if (dev_self[i]) |
332 | nsc_ircc_close(dev_self[i]); | |
333 | } | |
ec4f32d5 | 334 | |
3b99b93b DT |
335 | platform_driver_unregister(&nsc_ircc_driver); |
336 | ||
ec4f32d5 JT |
337 | if (pnp_registered) |
338 | pnp_unregister_driver(&nsc_ircc_pnp_driver); | |
339 | ||
340 | pnp_registered = 0; | |
1da177e4 LT |
341 | } |
342 | ||
c279b8c9 SH |
343 | static const struct net_device_ops nsc_ircc_sir_ops = { |
344 | .ndo_open = nsc_ircc_net_open, | |
345 | .ndo_stop = nsc_ircc_net_close, | |
346 | .ndo_start_xmit = nsc_ircc_hard_xmit_sir, | |
347 | .ndo_do_ioctl = nsc_ircc_net_ioctl, | |
348 | }; | |
349 | ||
350 | static const struct net_device_ops nsc_ircc_fir_ops = { | |
351 | .ndo_open = nsc_ircc_net_open, | |
352 | .ndo_stop = nsc_ircc_net_close, | |
353 | .ndo_start_xmit = nsc_ircc_hard_xmit_fir, | |
354 | .ndo_do_ioctl = nsc_ircc_net_ioctl, | |
355 | }; | |
356 | ||
1da177e4 LT |
357 | /* |
358 | * Function nsc_ircc_open (iobase, irq) | |
359 | * | |
360 | * Open driver instance | |
361 | * | |
362 | */ | |
ec4f32d5 | 363 | static int __init nsc_ircc_open(chipio_t *info) |
1da177e4 LT |
364 | { |
365 | struct net_device *dev; | |
366 | struct nsc_ircc_cb *self; | |
1da177e4 | 367 | void *ret; |
ec4f32d5 | 368 | int err, chip_index; |
1da177e4 | 369 | |
ec4f32d5 JT |
370 | for (chip_index = 0; chip_index < ARRAY_SIZE(dev_self); chip_index++) { |
371 | if (!dev_self[chip_index]) | |
372 | break; | |
373 | } | |
374 | ||
375 | if (chip_index == ARRAY_SIZE(dev_self)) { | |
6c91023d JP |
376 | net_err_ratelimited("%s(), maximum number of supported chips reached!\n", |
377 | __func__); | |
ec4f32d5 JT |
378 | return -ENOMEM; |
379 | } | |
380 | ||
6c91023d JP |
381 | net_info_ratelimited("%s, Found chip at base=0x%03x\n", |
382 | driver_name, info->cfg_base); | |
1da177e4 LT |
383 | |
384 | if ((nsc_ircc_setup(info)) == -1) | |
385 | return -1; | |
386 | ||
6c91023d | 387 | net_info_ratelimited("%s, driver loaded (Dag Brattli)\n", driver_name); |
1da177e4 LT |
388 | |
389 | dev = alloc_irdadev(sizeof(struct nsc_ircc_cb)); | |
390 | if (dev == NULL) { | |
6c91023d JP |
391 | net_err_ratelimited("%s(), can't allocate memory for control block!\n", |
392 | __func__); | |
1da177e4 LT |
393 | return -ENOMEM; |
394 | } | |
395 | ||
4cf1653a | 396 | self = netdev_priv(dev); |
1da177e4 LT |
397 | self->netdev = dev; |
398 | spin_lock_init(&self->lock); | |
399 | ||
400 | /* Need to store self somewhere */ | |
ec4f32d5 JT |
401 | dev_self[chip_index] = self; |
402 | self->index = chip_index; | |
1da177e4 LT |
403 | |
404 | /* Initialize IO */ | |
405 | self->io.cfg_base = info->cfg_base; | |
406 | self->io.fir_base = info->fir_base; | |
407 | self->io.irq = info->irq; | |
408 | self->io.fir_ext = CHIP_IO_EXTENT; | |
409 | self->io.dma = info->dma; | |
410 | self->io.fifo_size = 32; | |
411 | ||
412 | /* Reserve the ioports that we need */ | |
413 | ret = request_region(self->io.fir_base, self->io.fir_ext, driver_name); | |
414 | if (!ret) { | |
6c91023d JP |
415 | net_warn_ratelimited("%s(), can't get iobase of 0x%03x\n", |
416 | __func__, self->io.fir_base); | |
1da177e4 LT |
417 | err = -ENODEV; |
418 | goto out1; | |
419 | } | |
420 | ||
421 | /* Initialize QoS for this device */ | |
422 | irda_init_max_qos_capabilies(&self->qos); | |
423 | ||
424 | /* The only value we must override it the baudrate */ | |
425 | self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| | |
426 | IR_115200|IR_576000|IR_1152000 |(IR_4000000 << 8); | |
427 | ||
428 | self->qos.min_turn_time.bits = qos_mtt_bits; | |
429 | irda_qos_bits_to_value(&self->qos); | |
430 | ||
431 | /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */ | |
432 | self->rx_buff.truesize = 14384; | |
433 | self->tx_buff.truesize = 14384; | |
434 | ||
435 | /* Allocate memory if needed */ | |
436 | self->rx_buff.head = | |
ede23fa8 JP |
437 | dma_zalloc_coherent(NULL, self->rx_buff.truesize, |
438 | &self->rx_buff_dma, GFP_KERNEL); | |
1da177e4 LT |
439 | if (self->rx_buff.head == NULL) { |
440 | err = -ENOMEM; | |
441 | goto out2; | |
442 | ||
443 | } | |
1da177e4 LT |
444 | |
445 | self->tx_buff.head = | |
ede23fa8 JP |
446 | dma_zalloc_coherent(NULL, self->tx_buff.truesize, |
447 | &self->tx_buff_dma, GFP_KERNEL); | |
1da177e4 LT |
448 | if (self->tx_buff.head == NULL) { |
449 | err = -ENOMEM; | |
450 | goto out3; | |
451 | } | |
1da177e4 LT |
452 | |
453 | self->rx_buff.in_frame = FALSE; | |
454 | self->rx_buff.state = OUTSIDE_FRAME; | |
455 | self->tx_buff.data = self->tx_buff.head; | |
456 | self->rx_buff.data = self->rx_buff.head; | |
457 | ||
458 | /* Reset Tx queue info */ | |
459 | self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0; | |
460 | self->tx_fifo.tail = self->tx_buff.head; | |
461 | ||
462 | /* Override the network functions we need to use */ | |
c279b8c9 | 463 | dev->netdev_ops = &nsc_ircc_sir_ops; |
1da177e4 LT |
464 | |
465 | err = register_netdev(dev); | |
466 | if (err) { | |
6c91023d JP |
467 | net_err_ratelimited("%s(), register_netdev() failed!\n", |
468 | __func__); | |
1da177e4 LT |
469 | goto out4; |
470 | } | |
6c91023d | 471 | net_info_ratelimited("IrDA: Registered device %s\n", dev->name); |
1da177e4 LT |
472 | |
473 | /* Check if user has supplied a valid dongle id or not */ | |
474 | if ((dongle_id <= 0) || | |
ec4f32d5 | 475 | (dongle_id >= ARRAY_SIZE(dongle_types))) { |
1da177e4 LT |
476 | dongle_id = nsc_ircc_read_dongle_id(self->io.fir_base); |
477 | ||
6c91023d JP |
478 | net_info_ratelimited("%s, Found dongle: %s\n", |
479 | driver_name, dongle_types[dongle_id]); | |
1da177e4 | 480 | } else { |
6c91023d JP |
481 | net_info_ratelimited("%s, Using dongle: %s\n", |
482 | driver_name, dongle_types[dongle_id]); | |
1da177e4 LT |
483 | } |
484 | ||
485 | self->io.dongle_id = dongle_id; | |
486 | nsc_ircc_init_dongle_interface(self->io.fir_base, dongle_id); | |
487 | ||
3b99b93b DT |
488 | self->pldev = platform_device_register_simple(NSC_IRCC_DRIVER_NAME, |
489 | self->index, NULL, 0); | |
490 | if (IS_ERR(self->pldev)) { | |
491 | err = PTR_ERR(self->pldev); | |
492 | goto out5; | |
493 | } | |
494 | platform_set_drvdata(self->pldev, self); | |
1da177e4 | 495 | |
ec4f32d5 | 496 | return chip_index; |
3b99b93b DT |
497 | |
498 | out5: | |
499 | unregister_netdev(dev); | |
1da177e4 LT |
500 | out4: |
501 | dma_free_coherent(NULL, self->tx_buff.truesize, | |
502 | self->tx_buff.head, self->tx_buff_dma); | |
503 | out3: | |
504 | dma_free_coherent(NULL, self->rx_buff.truesize, | |
505 | self->rx_buff.head, self->rx_buff_dma); | |
506 | out2: | |
507 | release_region(self->io.fir_base, self->io.fir_ext); | |
508 | out1: | |
509 | free_netdev(dev); | |
ec4f32d5 | 510 | dev_self[chip_index] = NULL; |
1da177e4 LT |
511 | return err; |
512 | } | |
513 | ||
514 | /* | |
515 | * Function nsc_ircc_close (self) | |
516 | * | |
517 | * Close driver instance | |
518 | * | |
519 | */ | |
520 | static int __exit nsc_ircc_close(struct nsc_ircc_cb *self) | |
521 | { | |
522 | int iobase; | |
523 | ||
1da177e4 LT |
524 | IRDA_ASSERT(self != NULL, return -1;); |
525 | ||
526 | iobase = self->io.fir_base; | |
527 | ||
3b99b93b DT |
528 | platform_device_unregister(self->pldev); |
529 | ||
1da177e4 LT |
530 | /* Remove netdevice */ |
531 | unregister_netdev(self->netdev); | |
532 | ||
533 | /* Release the PORT that this driver is using */ | |
955a9d20 JP |
534 | pr_debug("%s(), Releasing Region %03x\n", |
535 | __func__, self->io.fir_base); | |
1da177e4 LT |
536 | release_region(self->io.fir_base, self->io.fir_ext); |
537 | ||
538 | if (self->tx_buff.head) | |
539 | dma_free_coherent(NULL, self->tx_buff.truesize, | |
540 | self->tx_buff.head, self->tx_buff_dma); | |
541 | ||
542 | if (self->rx_buff.head) | |
543 | dma_free_coherent(NULL, self->rx_buff.truesize, | |
544 | self->rx_buff.head, self->rx_buff_dma); | |
545 | ||
546 | dev_self[self->index] = NULL; | |
547 | free_netdev(self->netdev); | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | /* | |
553 | * Function nsc_ircc_init_108 (iobase, cfg_base, irq, dma) | |
554 | * | |
555 | * Initialize the NSC '108 chip | |
556 | * | |
557 | */ | |
558 | static int nsc_ircc_init_108(nsc_chip_t *chip, chipio_t *info) | |
559 | { | |
560 | int cfg_base = info->cfg_base; | |
561 | __u8 temp=0; | |
562 | ||
563 | outb(2, cfg_base); /* Mode Control Register (MCTL) */ | |
564 | outb(0x00, cfg_base+1); /* Disable device */ | |
565 | ||
566 | /* Base Address and Interrupt Control Register (BAIC) */ | |
567 | outb(CFG_108_BAIC, cfg_base); | |
568 | switch (info->fir_base) { | |
569 | case 0x3e8: outb(0x14, cfg_base+1); break; | |
570 | case 0x2e8: outb(0x15, cfg_base+1); break; | |
571 | case 0x3f8: outb(0x16, cfg_base+1); break; | |
572 | case 0x2f8: outb(0x17, cfg_base+1); break; | |
6c91023d | 573 | default: net_err_ratelimited("%s(), invalid base_address\n", __func__); |
1da177e4 LT |
574 | } |
575 | ||
576 | /* Control Signal Routing Register (CSRT) */ | |
577 | switch (info->irq) { | |
578 | case 3: temp = 0x01; break; | |
579 | case 4: temp = 0x02; break; | |
580 | case 5: temp = 0x03; break; | |
581 | case 7: temp = 0x04; break; | |
582 | case 9: temp = 0x05; break; | |
583 | case 11: temp = 0x06; break; | |
584 | case 15: temp = 0x07; break; | |
6c91023d | 585 | default: net_err_ratelimited("%s(), invalid irq\n", __func__); |
1da177e4 LT |
586 | } |
587 | outb(CFG_108_CSRT, cfg_base); | |
588 | ||
589 | switch (info->dma) { | |
590 | case 0: outb(0x08+temp, cfg_base+1); break; | |
591 | case 1: outb(0x10+temp, cfg_base+1); break; | |
592 | case 3: outb(0x18+temp, cfg_base+1); break; | |
6c91023d | 593 | default: net_err_ratelimited("%s(), invalid dma\n", __func__); |
1da177e4 LT |
594 | } |
595 | ||
596 | outb(CFG_108_MCTL, cfg_base); /* Mode Control Register (MCTL) */ | |
597 | outb(0x03, cfg_base+1); /* Enable device */ | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
602 | /* | |
603 | * Function nsc_ircc_probe_108 (chip, info) | |
604 | * | |
605 | * | |
606 | * | |
607 | */ | |
608 | static int nsc_ircc_probe_108(nsc_chip_t *chip, chipio_t *info) | |
609 | { | |
610 | int cfg_base = info->cfg_base; | |
611 | int reg; | |
612 | ||
613 | /* Read address and interrupt control register (BAIC) */ | |
614 | outb(CFG_108_BAIC, cfg_base); | |
615 | reg = inb(cfg_base+1); | |
616 | ||
617 | switch (reg & 0x03) { | |
618 | case 0: | |
619 | info->fir_base = 0x3e8; | |
620 | break; | |
621 | case 1: | |
622 | info->fir_base = 0x2e8; | |
623 | break; | |
624 | case 2: | |
625 | info->fir_base = 0x3f8; | |
626 | break; | |
627 | case 3: | |
628 | info->fir_base = 0x2f8; | |
629 | break; | |
630 | } | |
631 | info->sir_base = info->fir_base; | |
955a9d20 JP |
632 | pr_debug("%s(), probing fir_base=0x%03x\n", __func__, |
633 | info->fir_base); | |
1da177e4 LT |
634 | |
635 | /* Read control signals routing register (CSRT) */ | |
636 | outb(CFG_108_CSRT, cfg_base); | |
637 | reg = inb(cfg_base+1); | |
638 | ||
639 | switch (reg & 0x07) { | |
640 | case 0: | |
641 | info->irq = -1; | |
642 | break; | |
643 | case 1: | |
644 | info->irq = 3; | |
645 | break; | |
646 | case 2: | |
647 | info->irq = 4; | |
648 | break; | |
649 | case 3: | |
650 | info->irq = 5; | |
651 | break; | |
652 | case 4: | |
653 | info->irq = 7; | |
654 | break; | |
655 | case 5: | |
656 | info->irq = 9; | |
657 | break; | |
658 | case 6: | |
659 | info->irq = 11; | |
660 | break; | |
661 | case 7: | |
662 | info->irq = 15; | |
663 | break; | |
664 | } | |
955a9d20 | 665 | pr_debug("%s(), probing irq=%d\n", __func__, info->irq); |
1da177e4 LT |
666 | |
667 | /* Currently we only read Rx DMA but it will also be used for Tx */ | |
668 | switch ((reg >> 3) & 0x03) { | |
669 | case 0: | |
670 | info->dma = -1; | |
671 | break; | |
672 | case 1: | |
673 | info->dma = 0; | |
674 | break; | |
675 | case 2: | |
676 | info->dma = 1; | |
677 | break; | |
678 | case 3: | |
679 | info->dma = 3; | |
680 | break; | |
681 | } | |
955a9d20 | 682 | pr_debug("%s(), probing dma=%d\n", __func__, info->dma); |
1da177e4 LT |
683 | |
684 | /* Read mode control register (MCTL) */ | |
685 | outb(CFG_108_MCTL, cfg_base); | |
686 | reg = inb(cfg_base+1); | |
687 | ||
688 | info->enabled = reg & 0x01; | |
689 | info->suspended = !((reg >> 1) & 0x01); | |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
694 | /* | |
695 | * Function nsc_ircc_init_338 (chip, info) | |
696 | * | |
697 | * Initialize the NSC '338 chip. Remember that the 87338 needs two | |
698 | * consecutive writes to the data registers while CPU interrupts are | |
699 | * disabled. The 97338 does not require this, but shouldn't be any | |
700 | * harm if we do it anyway. | |
701 | */ | |
702 | static int nsc_ircc_init_338(nsc_chip_t *chip, chipio_t *info) | |
703 | { | |
704 | /* No init yet */ | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | /* | |
710 | * Function nsc_ircc_probe_338 (chip, info) | |
711 | * | |
712 | * | |
713 | * | |
714 | */ | |
715 | static int nsc_ircc_probe_338(nsc_chip_t *chip, chipio_t *info) | |
716 | { | |
717 | int cfg_base = info->cfg_base; | |
718 | int reg, com = 0; | |
719 | int pnp; | |
720 | ||
25985edc | 721 | /* Read function enable register (FER) */ |
1da177e4 LT |
722 | outb(CFG_338_FER, cfg_base); |
723 | reg = inb(cfg_base+1); | |
724 | ||
725 | info->enabled = (reg >> 2) & 0x01; | |
726 | ||
727 | /* Check if we are in Legacy or PnP mode */ | |
728 | outb(CFG_338_PNP0, cfg_base); | |
729 | reg = inb(cfg_base+1); | |
730 | ||
731 | pnp = (reg >> 3) & 0x01; | |
732 | if (pnp) { | |
955a9d20 | 733 | pr_debug("(), Chip is in PnP mode\n"); |
1da177e4 LT |
734 | outb(0x46, cfg_base); |
735 | reg = (inb(cfg_base+1) & 0xfe) << 2; | |
736 | ||
737 | outb(0x47, cfg_base); | |
738 | reg |= ((inb(cfg_base+1) & 0xfc) << 8); | |
739 | ||
740 | info->fir_base = reg; | |
741 | } else { | |
742 | /* Read function address register (FAR) */ | |
743 | outb(CFG_338_FAR, cfg_base); | |
744 | reg = inb(cfg_base+1); | |
745 | ||
746 | switch ((reg >> 4) & 0x03) { | |
747 | case 0: | |
748 | info->fir_base = 0x3f8; | |
749 | break; | |
750 | case 1: | |
751 | info->fir_base = 0x2f8; | |
752 | break; | |
753 | case 2: | |
754 | com = 3; | |
755 | break; | |
756 | case 3: | |
757 | com = 4; | |
758 | break; | |
759 | } | |
760 | ||
761 | if (com) { | |
762 | switch ((reg >> 6) & 0x03) { | |
763 | case 0: | |
764 | if (com == 3) | |
765 | info->fir_base = 0x3e8; | |
766 | else | |
767 | info->fir_base = 0x2e8; | |
768 | break; | |
769 | case 1: | |
770 | if (com == 3) | |
771 | info->fir_base = 0x338; | |
772 | else | |
773 | info->fir_base = 0x238; | |
774 | break; | |
775 | case 2: | |
776 | if (com == 3) | |
777 | info->fir_base = 0x2e8; | |
778 | else | |
779 | info->fir_base = 0x2e0; | |
780 | break; | |
781 | case 3: | |
782 | if (com == 3) | |
783 | info->fir_base = 0x220; | |
784 | else | |
785 | info->fir_base = 0x228; | |
786 | break; | |
787 | } | |
788 | } | |
789 | } | |
790 | info->sir_base = info->fir_base; | |
791 | ||
792 | /* Read PnP register 1 (PNP1) */ | |
793 | outb(CFG_338_PNP1, cfg_base); | |
794 | reg = inb(cfg_base+1); | |
795 | ||
796 | info->irq = reg >> 4; | |
797 | ||
798 | /* Read PnP register 3 (PNP3) */ | |
799 | outb(CFG_338_PNP3, cfg_base); | |
800 | reg = inb(cfg_base+1); | |
801 | ||
802 | info->dma = (reg & 0x07) - 1; | |
803 | ||
804 | /* Read power and test register (PTR) */ | |
805 | outb(CFG_338_PTR, cfg_base); | |
806 | reg = inb(cfg_base+1); | |
807 | ||
808 | info->suspended = reg & 0x01; | |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
813 | ||
814 | /* | |
815 | * Function nsc_ircc_init_39x (chip, info) | |
816 | * | |
817 | * Now that we know it's a '39x (see probe below), we need to | |
818 | * configure it so we can use it. | |
819 | * | |
820 | * The NSC '338 chip is a Super I/O chip with a "bank" architecture, | |
821 | * the configuration of the different functionality (serial, parallel, | |
822 | * floppy...) are each in a different bank (Logical Device Number). | |
823 | * The base address, irq and dma configuration registers are common | |
824 | * to all functionalities (index 0x30 to 0x7F). | |
825 | * There is only one configuration register specific to the | |
826 | * serial port, CFG_39X_SPC. | |
827 | * JeanII | |
828 | * | |
829 | * Note : this code was written by Jan Frey <janfrey@web.de> | |
830 | */ | |
831 | static int nsc_ircc_init_39x(nsc_chip_t *chip, chipio_t *info) | |
832 | { | |
833 | int cfg_base = info->cfg_base; | |
834 | int enabled; | |
835 | ||
7f927fcc | 836 | /* User is sure about his config... accept it. */ |
955a9d20 JP |
837 | pr_debug("%s(): nsc_ircc_init_39x (user settings): io=0x%04x, irq=%d, dma=%d\n", |
838 | __func__, info->fir_base, info->irq, info->dma); | |
1da177e4 LT |
839 | |
840 | /* Access bank for SP2 */ | |
841 | outb(CFG_39X_LDN, cfg_base); | |
842 | outb(0x02, cfg_base+1); | |
843 | ||
844 | /* Configure SP2 */ | |
845 | ||
846 | /* We want to enable the device if not enabled */ | |
847 | outb(CFG_39X_ACT, cfg_base); | |
848 | enabled = inb(cfg_base+1) & 0x01; | |
849 | ||
850 | if (!enabled) { | |
851 | /* Enable the device */ | |
852 | outb(CFG_39X_SIOCF1, cfg_base); | |
853 | outb(0x01, cfg_base+1); | |
854 | /* May want to update info->enabled. Jean II */ | |
855 | } | |
856 | ||
857 | /* Enable UART bank switching (bit 7) ; Sets the chip to normal | |
858 | * power mode (wake up from sleep mode) (bit 1) */ | |
859 | outb(CFG_39X_SPC, cfg_base); | |
860 | outb(0x82, cfg_base+1); | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
865 | /* | |
866 | * Function nsc_ircc_probe_39x (chip, info) | |
867 | * | |
868 | * Test if we really have a '39x chip at the given address | |
869 | * | |
870 | * Note : this code was written by Jan Frey <janfrey@web.de> | |
871 | */ | |
872 | static int nsc_ircc_probe_39x(nsc_chip_t *chip, chipio_t *info) | |
873 | { | |
874 | int cfg_base = info->cfg_base; | |
875 | int reg1, reg2, irq, irqt, dma1, dma2; | |
876 | int enabled, susp; | |
877 | ||
955a9d20 JP |
878 | pr_debug("%s(), nsc_ircc_probe_39x, base=%d\n", |
879 | __func__, cfg_base); | |
1da177e4 LT |
880 | |
881 | /* This function should be executed with irq off to avoid | |
882 | * another driver messing with the Super I/O bank - Jean II */ | |
883 | ||
884 | /* Access bank for SP2 */ | |
885 | outb(CFG_39X_LDN, cfg_base); | |
886 | outb(0x02, cfg_base+1); | |
887 | ||
888 | /* Read infos about SP2 ; store in info struct */ | |
889 | outb(CFG_39X_BASEH, cfg_base); | |
890 | reg1 = inb(cfg_base+1); | |
891 | outb(CFG_39X_BASEL, cfg_base); | |
892 | reg2 = inb(cfg_base+1); | |
893 | info->fir_base = (reg1 << 8) | reg2; | |
894 | ||
895 | outb(CFG_39X_IRQNUM, cfg_base); | |
896 | irq = inb(cfg_base+1); | |
897 | outb(CFG_39X_IRQSEL, cfg_base); | |
898 | irqt = inb(cfg_base+1); | |
899 | info->irq = irq; | |
900 | ||
901 | outb(CFG_39X_DMA0, cfg_base); | |
902 | dma1 = inb(cfg_base+1); | |
903 | outb(CFG_39X_DMA1, cfg_base); | |
904 | dma2 = inb(cfg_base+1); | |
905 | info->dma = dma1 -1; | |
906 | ||
907 | outb(CFG_39X_ACT, cfg_base); | |
908 | info->enabled = enabled = inb(cfg_base+1) & 0x01; | |
909 | ||
910 | outb(CFG_39X_SPC, cfg_base); | |
911 | susp = 1 - ((inb(cfg_base+1) & 0x02) >> 1); | |
912 | ||
955a9d20 JP |
913 | pr_debug("%s(): io=0x%02x%02x, irq=%d (type %d), rxdma=%d, txdma=%d, enabled=%d (suspended=%d)\n", |
914 | __func__, reg1, reg2, irq, irqt, dma1, dma2, enabled, susp); | |
1da177e4 LT |
915 | |
916 | /* Configure SP2 */ | |
917 | ||
918 | /* We want to enable the device if not enabled */ | |
919 | outb(CFG_39X_ACT, cfg_base); | |
920 | enabled = inb(cfg_base+1) & 0x01; | |
921 | ||
922 | if (!enabled) { | |
923 | /* Enable the device */ | |
924 | outb(CFG_39X_SIOCF1, cfg_base); | |
925 | outb(0x01, cfg_base+1); | |
926 | /* May want to update info->enabled. Jean II */ | |
927 | } | |
928 | ||
929 | /* Enable UART bank switching (bit 7) ; Sets the chip to normal | |
930 | * power mode (wake up from sleep mode) (bit 1) */ | |
931 | outb(CFG_39X_SPC, cfg_base); | |
932 | outb(0x82, cfg_base+1); | |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
c17f888f | 937 | #ifdef CONFIG_PNP |
ec4f32d5 JT |
938 | /* PNP probing */ |
939 | static int nsc_ircc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id) | |
940 | { | |
941 | memset(&pnp_info, 0, sizeof(chipio_t)); | |
942 | pnp_info.irq = -1; | |
943 | pnp_info.dma = -1; | |
944 | pnp_succeeded = 1; | |
945 | ||
1fa98174 MG |
946 | if (id->driver_data & NSC_FORCE_DONGLE_TYPE9) |
947 | dongle_id = 0x9; | |
948 | ||
949 | /* There doesn't seem to be any way of getting the cfg_base. | |
ec4f32d5 JT |
950 | * On my box, cfg_base is in the PnP descriptor of the |
951 | * motherboard. Oh well... Jean II */ | |
952 | ||
953 | if (pnp_port_valid(dev, 0) && | |
954 | !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) | |
955 | pnp_info.fir_base = pnp_port_start(dev, 0); | |
956 | ||
957 | if (pnp_irq_valid(dev, 0) && | |
958 | !(pnp_irq_flags(dev, 0) & IORESOURCE_DISABLED)) | |
959 | pnp_info.irq = pnp_irq(dev, 0); | |
960 | ||
961 | if (pnp_dma_valid(dev, 0) && | |
962 | !(pnp_dma_flags(dev, 0) & IORESOURCE_DISABLED)) | |
963 | pnp_info.dma = pnp_dma(dev, 0); | |
964 | ||
955a9d20 JP |
965 | pr_debug("%s() : From PnP, found firbase 0x%03X ; irq %d ; dma %d.\n", |
966 | __func__, pnp_info.fir_base, pnp_info.irq, pnp_info.dma); | |
ec4f32d5 JT |
967 | |
968 | if((pnp_info.fir_base == 0) || | |
969 | (pnp_info.irq == -1) || (pnp_info.dma == -1)) { | |
970 | /* Returning an error will disable the device. Yuck ! */ | |
971 | //return -EINVAL; | |
972 | pnp_succeeded = 0; | |
973 | } | |
974 | ||
975 | return 0; | |
976 | } | |
c17f888f | 977 | #endif |
ec4f32d5 | 978 | |
1da177e4 LT |
979 | /* |
980 | * Function nsc_ircc_setup (info) | |
981 | * | |
982 | * Returns non-negative on success. | |
983 | * | |
984 | */ | |
985 | static int nsc_ircc_setup(chipio_t *info) | |
986 | { | |
987 | int version; | |
988 | int iobase = info->fir_base; | |
989 | ||
990 | /* Read the Module ID */ | |
991 | switch_bank(iobase, BANK3); | |
992 | version = inb(iobase+MID); | |
993 | ||
955a9d20 JP |
994 | pr_debug("%s() Driver %s Found chip version %02x\n", |
995 | __func__, driver_name, version); | |
1da177e4 LT |
996 | |
997 | /* Should be 0x2? */ | |
998 | if (0x20 != (version & 0xf0)) { | |
6c91023d JP |
999 | net_err_ratelimited("%s, Wrong chip version %02x\n", |
1000 | driver_name, version); | |
1da177e4 LT |
1001 | return -1; |
1002 | } | |
1003 | ||
1004 | /* Switch to advanced mode */ | |
1005 | switch_bank(iobase, BANK2); | |
1006 | outb(ECR1_EXT_SL, iobase+ECR1); | |
1007 | switch_bank(iobase, BANK0); | |
1008 | ||
1009 | /* Set FIFO threshold to TX17, RX16, reset and enable FIFO's */ | |
1010 | switch_bank(iobase, BANK0); | |
1011 | outb(FCR_RXTH|FCR_TXTH|FCR_TXSR|FCR_RXSR|FCR_FIFO_EN, iobase+FCR); | |
1012 | ||
1013 | outb(0x03, iobase+LCR); /* 8 bit word length */ | |
1014 | outb(MCR_SIR, iobase+MCR); /* Start at SIR-mode, also clears LSR*/ | |
1015 | ||
1016 | /* Set FIFO size to 32 */ | |
1017 | switch_bank(iobase, BANK2); | |
1018 | outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2); | |
1019 | ||
1020 | /* IRCR2: FEND_MD is not set */ | |
1021 | switch_bank(iobase, BANK5); | |
1022 | outb(0x02, iobase+4); | |
1023 | ||
1024 | /* Make sure that some defaults are OK */ | |
1025 | switch_bank(iobase, BANK6); | |
1026 | outb(0x20, iobase+0); /* Set 32 bits FIR CRC */ | |
1027 | outb(0x0a, iobase+1); /* Set MIR pulse width */ | |
1028 | outb(0x0d, iobase+2); /* Set SIR pulse width to 1.6us */ | |
1029 | outb(0x2a, iobase+4); /* Set beginning frag, and preamble length */ | |
1030 | ||
1031 | /* Enable receive interrupts */ | |
1032 | switch_bank(iobase, BANK0); | |
1033 | outb(IER_RXHDL_IE, iobase+IER); | |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | /* | |
1039 | * Function nsc_ircc_read_dongle_id (void) | |
1040 | * | |
3f79410c | 1041 | * Try to read dongle identification. This procedure needs to be executed |
1da177e4 LT |
1042 | * once after power-on/reset. It also needs to be used whenever you suspect |
1043 | * that the user may have plugged/unplugged the IrDA Dongle. | |
1044 | */ | |
1045 | static int nsc_ircc_read_dongle_id (int iobase) | |
1046 | { | |
1047 | int dongle_id; | |
1048 | __u8 bank; | |
1049 | ||
1050 | bank = inb(iobase+BSR); | |
1051 | ||
1052 | /* Select Bank 7 */ | |
1053 | switch_bank(iobase, BANK7); | |
1054 | ||
1055 | /* IRCFG4: IRSL0_DS and IRSL21_DS are cleared */ | |
1056 | outb(0x00, iobase+7); | |
1057 | ||
1058 | /* ID0, 1, and 2 are pulled up/down very slowly */ | |
1059 | udelay(50); | |
1060 | ||
1061 | /* IRCFG1: read the ID bits */ | |
1062 | dongle_id = inb(iobase+4) & 0x0f; | |
1063 | ||
1064 | #ifdef BROKEN_DONGLE_ID | |
1065 | if (dongle_id == 0x0a) | |
1066 | dongle_id = 0x09; | |
1067 | #endif | |
1068 | /* Go back to bank 0 before returning */ | |
1069 | switch_bank(iobase, BANK0); | |
1070 | ||
1071 | outb(bank, iobase+BSR); | |
1072 | ||
1073 | return dongle_id; | |
1074 | } | |
1075 | ||
1076 | /* | |
1077 | * Function nsc_ircc_init_dongle_interface (iobase, dongle_id) | |
1078 | * | |
1079 | * This function initializes the dongle for the transceiver that is | |
1080 | * used. This procedure needs to be executed once after | |
1081 | * power-on/reset. It also needs to be used whenever you suspect that | |
1082 | * the dongle is changed. | |
1083 | */ | |
1084 | static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id) | |
1085 | { | |
1086 | int bank; | |
1087 | ||
1088 | /* Save current bank */ | |
1089 | bank = inb(iobase+BSR); | |
1090 | ||
1091 | /* Select Bank 7 */ | |
1092 | switch_bank(iobase, BANK7); | |
1093 | ||
1094 | /* IRCFG4: set according to dongle_id */ | |
1095 | switch (dongle_id) { | |
1096 | case 0x00: /* same as */ | |
1097 | case 0x01: /* Differential serial interface */ | |
955a9d20 JP |
1098 | pr_debug("%s(), %s not defined by irda yet\n", |
1099 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1100 | break; |
1101 | case 0x02: /* same as */ | |
1102 | case 0x03: /* Reserved */ | |
955a9d20 JP |
1103 | pr_debug("%s(), %s not defined by irda yet\n", |
1104 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1105 | break; |
1106 | case 0x04: /* Sharp RY5HD01 */ | |
1107 | break; | |
1108 | case 0x05: /* Reserved, but this is what the Thinkpad reports */ | |
955a9d20 JP |
1109 | pr_debug("%s(), %s not defined by irda yet\n", |
1110 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1111 | break; |
1112 | case 0x06: /* Single-ended serial interface */ | |
955a9d20 JP |
1113 | pr_debug("%s(), %s not defined by irda yet\n", |
1114 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1115 | break; |
1116 | case 0x07: /* Consumer-IR only */ | |
955a9d20 JP |
1117 | pr_debug("%s(), %s is not for IrDA mode\n", |
1118 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1119 | break; |
1120 | case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */ | |
955a9d20 JP |
1121 | pr_debug("%s(), %s\n", |
1122 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1123 | break; |
1124 | case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */ | |
1125 | outb(0x28, iobase+7); /* Set irsl[0-2] as output */ | |
1126 | break; | |
1127 | case 0x0A: /* same as */ | |
1128 | case 0x0B: /* Reserved */ | |
955a9d20 JP |
1129 | pr_debug("%s(), %s not defined by irda yet\n", |
1130 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1131 | break; |
1132 | case 0x0C: /* same as */ | |
1133 | case 0x0D: /* HP HSDL-1100/HSDL-2100 */ | |
1134 | /* | |
1135 | * Set irsl0 as input, irsl[1-2] as output, and separate | |
1136 | * inputs are used for SIR and MIR/FIR | |
1137 | */ | |
1138 | outb(0x48, iobase+7); | |
1139 | break; | |
1140 | case 0x0E: /* Supports SIR Mode only */ | |
1141 | outb(0x28, iobase+7); /* Set irsl[0-2] as output */ | |
1142 | break; | |
1143 | case 0x0F: /* No dongle connected */ | |
955a9d20 JP |
1144 | pr_debug("%s(), %s\n", |
1145 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1146 | |
1147 | switch_bank(iobase, BANK0); | |
1148 | outb(0x62, iobase+MCR); | |
1149 | break; | |
1150 | default: | |
955a9d20 JP |
1151 | pr_debug("%s(), invalid dongle_id %#x", |
1152 | __func__, dongle_id); | |
1da177e4 LT |
1153 | } |
1154 | ||
1155 | /* IRCFG1: IRSL1 and 2 are set to IrDA mode */ | |
1156 | outb(0x00, iobase+4); | |
1157 | ||
1158 | /* Restore bank register */ | |
1159 | outb(bank, iobase+BSR); | |
1160 | ||
1161 | } /* set_up_dongle_interface */ | |
1162 | ||
1163 | /* | |
1164 | * Function nsc_ircc_change_dongle_speed (iobase, speed, dongle_id) | |
1165 | * | |
1166 | * Change speed of the attach dongle | |
1167 | * | |
1168 | */ | |
1169 | static void nsc_ircc_change_dongle_speed(int iobase, int speed, int dongle_id) | |
1170 | { | |
1171 | __u8 bank; | |
1172 | ||
1173 | /* Save current bank */ | |
1174 | bank = inb(iobase+BSR); | |
1175 | ||
1176 | /* Select Bank 7 */ | |
1177 | switch_bank(iobase, BANK7); | |
1178 | ||
1179 | /* IRCFG1: set according to dongle_id */ | |
1180 | switch (dongle_id) { | |
1181 | case 0x00: /* same as */ | |
1182 | case 0x01: /* Differential serial interface */ | |
955a9d20 JP |
1183 | pr_debug("%s(), %s not defined by irda yet\n", |
1184 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1185 | break; |
1186 | case 0x02: /* same as */ | |
1187 | case 0x03: /* Reserved */ | |
955a9d20 JP |
1188 | pr_debug("%s(), %s not defined by irda yet\n", |
1189 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1190 | break; |
1191 | case 0x04: /* Sharp RY5HD01 */ | |
1192 | break; | |
1193 | case 0x05: /* Reserved */ | |
955a9d20 JP |
1194 | pr_debug("%s(), %s not defined by irda yet\n", |
1195 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1196 | break; |
1197 | case 0x06: /* Single-ended serial interface */ | |
955a9d20 JP |
1198 | pr_debug("%s(), %s not defined by irda yet\n", |
1199 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1200 | break; |
1201 | case 0x07: /* Consumer-IR only */ | |
955a9d20 JP |
1202 | pr_debug("%s(), %s is not for IrDA mode\n", |
1203 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1204 | break; |
1205 | case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */ | |
955a9d20 JP |
1206 | pr_debug("%s(), %s\n", |
1207 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1208 | outb(0x00, iobase+4); |
1209 | if (speed > 115200) | |
1210 | outb(0x01, iobase+4); | |
1211 | break; | |
1212 | case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */ | |
1213 | outb(0x01, iobase+4); | |
1214 | ||
1215 | if (speed == 4000000) { | |
1216 | /* There was a cli() there, but we now are already | |
1217 | * under spin_lock_irqsave() - JeanII */ | |
1218 | outb(0x81, iobase+4); | |
1219 | outb(0x80, iobase+4); | |
1220 | } else | |
1221 | outb(0x00, iobase+4); | |
1222 | break; | |
1223 | case 0x0A: /* same as */ | |
1224 | case 0x0B: /* Reserved */ | |
955a9d20 JP |
1225 | pr_debug("%s(), %s not defined by irda yet\n", |
1226 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1227 | break; |
1228 | case 0x0C: /* same as */ | |
1229 | case 0x0D: /* HP HSDL-1100/HSDL-2100 */ | |
1230 | break; | |
1231 | case 0x0E: /* Supports SIR Mode only */ | |
1232 | break; | |
1233 | case 0x0F: /* No dongle connected */ | |
955a9d20 JP |
1234 | pr_debug("%s(), %s is not for IrDA mode\n", |
1235 | __func__, dongle_types[dongle_id]); | |
1da177e4 LT |
1236 | |
1237 | switch_bank(iobase, BANK0); | |
1238 | outb(0x62, iobase+MCR); | |
1239 | break; | |
1240 | default: | |
955a9d20 | 1241 | pr_debug("%s(), invalid data_rate\n", __func__); |
1da177e4 LT |
1242 | } |
1243 | /* Restore bank register */ | |
1244 | outb(bank, iobase+BSR); | |
1245 | } | |
1246 | ||
1247 | /* | |
1248 | * Function nsc_ircc_change_speed (self, baud) | |
1249 | * | |
1250 | * Change the speed of the device | |
1251 | * | |
1252 | * This function *must* be called with irq off and spin-lock. | |
1253 | */ | |
1254 | static __u8 nsc_ircc_change_speed(struct nsc_ircc_cb *self, __u32 speed) | |
1255 | { | |
1256 | struct net_device *dev = self->netdev; | |
1257 | __u8 mcr = MCR_SIR; | |
1258 | int iobase; | |
1259 | __u8 bank; | |
1260 | __u8 ier; /* Interrupt enable register */ | |
1261 | ||
955a9d20 | 1262 | pr_debug("%s(), speed=%d\n", __func__, speed); |
1da177e4 LT |
1263 | |
1264 | IRDA_ASSERT(self != NULL, return 0;); | |
1265 | ||
1266 | iobase = self->io.fir_base; | |
1267 | ||
1268 | /* Update accounting for new speed */ | |
1269 | self->io.speed = speed; | |
1270 | ||
1271 | /* Save current bank */ | |
1272 | bank = inb(iobase+BSR); | |
1273 | ||
1274 | /* Disable interrupts */ | |
1275 | switch_bank(iobase, BANK0); | |
1276 | outb(0, iobase+IER); | |
1277 | ||
1278 | /* Select Bank 2 */ | |
1279 | switch_bank(iobase, BANK2); | |
1280 | ||
1281 | outb(0x00, iobase+BGDH); | |
1282 | switch (speed) { | |
1283 | case 9600: outb(0x0c, iobase+BGDL); break; | |
1284 | case 19200: outb(0x06, iobase+BGDL); break; | |
1285 | case 38400: outb(0x03, iobase+BGDL); break; | |
1286 | case 57600: outb(0x02, iobase+BGDL); break; | |
1287 | case 115200: outb(0x01, iobase+BGDL); break; | |
1288 | case 576000: | |
1289 | switch_bank(iobase, BANK5); | |
1290 | ||
1291 | /* IRCR2: MDRS is set */ | |
1292 | outb(inb(iobase+4) | 0x04, iobase+4); | |
1293 | ||
1294 | mcr = MCR_MIR; | |
955a9d20 | 1295 | pr_debug("%s(), handling baud of 576000\n", __func__); |
1da177e4 LT |
1296 | break; |
1297 | case 1152000: | |
1298 | mcr = MCR_MIR; | |
955a9d20 | 1299 | pr_debug("%s(), handling baud of 1152000\n", __func__); |
1da177e4 LT |
1300 | break; |
1301 | case 4000000: | |
1302 | mcr = MCR_FIR; | |
955a9d20 | 1303 | pr_debug("%s(), handling baud of 4000000\n", __func__); |
1da177e4 LT |
1304 | break; |
1305 | default: | |
1306 | mcr = MCR_FIR; | |
955a9d20 JP |
1307 | pr_debug("%s(), unknown baud rate of %d\n", |
1308 | __func__, speed); | |
1da177e4 LT |
1309 | break; |
1310 | } | |
1311 | ||
1312 | /* Set appropriate speed mode */ | |
1313 | switch_bank(iobase, BANK0); | |
1314 | outb(mcr | MCR_TX_DFR, iobase+MCR); | |
1315 | ||
1316 | /* Give some hits to the transceiver */ | |
1317 | nsc_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id); | |
1318 | ||
1319 | /* Set FIFO threshold to TX17, RX16 */ | |
1320 | switch_bank(iobase, BANK0); | |
1321 | outb(0x00, iobase+FCR); | |
1322 | outb(FCR_FIFO_EN, iobase+FCR); | |
1323 | outb(FCR_RXTH| /* Set Rx FIFO threshold */ | |
1324 | FCR_TXTH| /* Set Tx FIFO threshold */ | |
1325 | FCR_TXSR| /* Reset Tx FIFO */ | |
1326 | FCR_RXSR| /* Reset Rx FIFO */ | |
1327 | FCR_FIFO_EN, /* Enable FIFOs */ | |
1328 | iobase+FCR); | |
1329 | ||
1330 | /* Set FIFO size to 32 */ | |
1331 | switch_bank(iobase, BANK2); | |
1332 | outb(EXCR2_RFSIZ|EXCR2_TFSIZ, iobase+EXCR2); | |
1333 | ||
1334 | /* Enable some interrupts so we can receive frames */ | |
1335 | switch_bank(iobase, BANK0); | |
1336 | if (speed > 115200) { | |
1337 | /* Install FIR xmit handler */ | |
c279b8c9 | 1338 | dev->netdev_ops = &nsc_ircc_fir_ops; |
1da177e4 LT |
1339 | ier = IER_SFIF_IE; |
1340 | nsc_ircc_dma_receive(self); | |
1341 | } else { | |
1342 | /* Install SIR xmit handler */ | |
c279b8c9 | 1343 | dev->netdev_ops = &nsc_ircc_sir_ops; |
1da177e4 LT |
1344 | ier = IER_RXHDL_IE; |
1345 | } | |
1346 | /* Set our current interrupt mask */ | |
1347 | outb(ier, iobase+IER); | |
1348 | ||
1349 | /* Restore BSR */ | |
1350 | outb(bank, iobase+BSR); | |
1351 | ||
1352 | /* Make sure interrupt handlers keep the proper interrupt mask */ | |
807540ba | 1353 | return ier; |
1da177e4 LT |
1354 | } |
1355 | ||
1356 | /* | |
1357 | * Function nsc_ircc_hard_xmit (skb, dev) | |
1358 | * | |
1359 | * Transmit the frame! | |
1360 | * | |
1361 | */ | |
6518bbb8 SH |
1362 | static netdev_tx_t nsc_ircc_hard_xmit_sir(struct sk_buff *skb, |
1363 | struct net_device *dev) | |
1da177e4 LT |
1364 | { |
1365 | struct nsc_ircc_cb *self; | |
1366 | unsigned long flags; | |
1367 | int iobase; | |
1368 | __s32 speed; | |
1369 | __u8 bank; | |
1370 | ||
4cf1653a | 1371 | self = netdev_priv(dev); |
1da177e4 | 1372 | |
ec634fe3 | 1373 | IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;); |
1da177e4 LT |
1374 | |
1375 | iobase = self->io.fir_base; | |
1376 | ||
1377 | netif_stop_queue(dev); | |
1378 | ||
1379 | /* Make sure tests *& speed change are atomic */ | |
1380 | spin_lock_irqsave(&self->lock, flags); | |
1381 | ||
1382 | /* Check if we need to change the speed */ | |
1383 | speed = irda_get_next_speed(skb); | |
1384 | if ((speed != self->io.speed) && (speed != -1)) { | |
1385 | /* Check for empty frame. */ | |
1386 | if (!skb->len) { | |
1387 | /* If we just sent a frame, we get called before | |
1388 | * the last bytes get out (because of the SIR FIFO). | |
1389 | * If this is the case, let interrupt handler change | |
1390 | * the speed itself... Jean II */ | |
1391 | if (self->io.direction == IO_RECV) { | |
1392 | nsc_ircc_change_speed(self, speed); | |
1393 | /* TODO : For SIR->SIR, the next packet | |
1394 | * may get corrupted - Jean II */ | |
1395 | netif_wake_queue(dev); | |
1396 | } else { | |
1397 | self->new_speed = speed; | |
1398 | /* Queue will be restarted after speed change | |
1399 | * to make sure packets gets through the | |
1400 | * proper xmit handler - Jean II */ | |
1401 | } | |
1402 | dev->trans_start = jiffies; | |
1403 | spin_unlock_irqrestore(&self->lock, flags); | |
1404 | dev_kfree_skb(skb); | |
6ed10654 | 1405 | return NETDEV_TX_OK; |
1da177e4 LT |
1406 | } else |
1407 | self->new_speed = speed; | |
1408 | } | |
1409 | ||
1410 | /* Save current bank */ | |
1411 | bank = inb(iobase+BSR); | |
1412 | ||
1413 | self->tx_buff.data = self->tx_buff.head; | |
1414 | ||
1415 | self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, | |
1416 | self->tx_buff.truesize); | |
1417 | ||
af049081 | 1418 | dev->stats.tx_bytes += self->tx_buff.len; |
1da177e4 LT |
1419 | |
1420 | /* Add interrupt on tx low level (will fire immediately) */ | |
1421 | switch_bank(iobase, BANK0); | |
1422 | outb(IER_TXLDL_IE, iobase+IER); | |
1423 | ||
1424 | /* Restore bank register */ | |
1425 | outb(bank, iobase+BSR); | |
1426 | ||
1427 | dev->trans_start = jiffies; | |
1428 | spin_unlock_irqrestore(&self->lock, flags); | |
1429 | ||
1430 | dev_kfree_skb(skb); | |
1431 | ||
6ed10654 | 1432 | return NETDEV_TX_OK; |
1da177e4 LT |
1433 | } |
1434 | ||
6518bbb8 SH |
1435 | static netdev_tx_t nsc_ircc_hard_xmit_fir(struct sk_buff *skb, |
1436 | struct net_device *dev) | |
1da177e4 LT |
1437 | { |
1438 | struct nsc_ircc_cb *self; | |
1439 | unsigned long flags; | |
1440 | int iobase; | |
1441 | __s32 speed; | |
1442 | __u8 bank; | |
1443 | int mtt, diff; | |
1444 | ||
4cf1653a | 1445 | self = netdev_priv(dev); |
1da177e4 LT |
1446 | iobase = self->io.fir_base; |
1447 | ||
1448 | netif_stop_queue(dev); | |
1449 | ||
1450 | /* Make sure tests *& speed change are atomic */ | |
1451 | spin_lock_irqsave(&self->lock, flags); | |
1452 | ||
1453 | /* Check if we need to change the speed */ | |
1454 | speed = irda_get_next_speed(skb); | |
1455 | if ((speed != self->io.speed) && (speed != -1)) { | |
1456 | /* Check for empty frame. */ | |
1457 | if (!skb->len) { | |
1458 | /* If we are currently transmitting, defer to | |
1459 | * interrupt handler. - Jean II */ | |
1460 | if(self->tx_fifo.len == 0) { | |
1461 | nsc_ircc_change_speed(self, speed); | |
1462 | netif_wake_queue(dev); | |
1463 | } else { | |
1464 | self->new_speed = speed; | |
1465 | /* Keep queue stopped : | |
1466 | * the speed change operation may change the | |
1467 | * xmit handler, and we want to make sure | |
1468 | * the next packet get through the proper | |
1469 | * Tx path, so block the Tx queue until | |
1470 | * the speed change has been done. | |
1471 | * Jean II */ | |
1472 | } | |
1473 | dev->trans_start = jiffies; | |
1474 | spin_unlock_irqrestore(&self->lock, flags); | |
1475 | dev_kfree_skb(skb); | |
6ed10654 | 1476 | return NETDEV_TX_OK; |
1da177e4 LT |
1477 | } else { |
1478 | /* Change speed after current frame */ | |
1479 | self->new_speed = speed; | |
1480 | } | |
1481 | } | |
1482 | ||
1483 | /* Save current bank */ | |
1484 | bank = inb(iobase+BSR); | |
1485 | ||
1486 | /* Register and copy this frame to DMA memory */ | |
1487 | self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail; | |
1488 | self->tx_fifo.queue[self->tx_fifo.free].len = skb->len; | |
1489 | self->tx_fifo.tail += skb->len; | |
1490 | ||
af049081 | 1491 | dev->stats.tx_bytes += skb->len; |
1da177e4 | 1492 | |
d626f62b ACM |
1493 | skb_copy_from_linear_data(skb, self->tx_fifo.queue[self->tx_fifo.free].start, |
1494 | skb->len); | |
1da177e4 LT |
1495 | self->tx_fifo.len++; |
1496 | self->tx_fifo.free++; | |
1497 | ||
1498 | /* Start transmit only if there is currently no transmit going on */ | |
1499 | if (self->tx_fifo.len == 1) { | |
1500 | /* Check if we must wait the min turn time or not */ | |
1501 | mtt = irda_get_mtt(skb); | |
1502 | if (mtt) { | |
1503 | /* Check how much time we have used already */ | |
1504 | do_gettimeofday(&self->now); | |
1505 | diff = self->now.tv_usec - self->stamp.tv_usec; | |
1506 | if (diff < 0) | |
1507 | diff += 1000000; | |
1508 | ||
1509 | /* Check if the mtt is larger than the time we have | |
1510 | * already used by all the protocol processing | |
1511 | */ | |
1512 | if (mtt > diff) { | |
1513 | mtt -= diff; | |
1514 | ||
1515 | /* | |
1516 | * Use timer if delay larger than 125 us, and | |
1517 | * use udelay for smaller values which should | |
1518 | * be acceptable | |
1519 | */ | |
1520 | if (mtt > 125) { | |
1521 | /* Adjust for timer resolution */ | |
1522 | mtt = mtt / 125; | |
1523 | ||
1524 | /* Setup timer */ | |
1525 | switch_bank(iobase, BANK4); | |
1526 | outb(mtt & 0xff, iobase+TMRL); | |
1527 | outb((mtt >> 8) & 0x0f, iobase+TMRH); | |
1528 | ||
1529 | /* Start timer */ | |
1530 | outb(IRCR1_TMR_EN, iobase+IRCR1); | |
1531 | self->io.direction = IO_XMIT; | |
1532 | ||
1533 | /* Enable timer interrupt */ | |
1534 | switch_bank(iobase, BANK0); | |
1535 | outb(IER_TMR_IE, iobase+IER); | |
1536 | ||
1537 | /* Timer will take care of the rest */ | |
1538 | goto out; | |
1539 | } else | |
1540 | udelay(mtt); | |
1541 | } | |
1542 | } | |
1543 | /* Enable DMA interrupt */ | |
1544 | switch_bank(iobase, BANK0); | |
1545 | outb(IER_DMA_IE, iobase+IER); | |
1546 | ||
1547 | /* Transmit frame */ | |
1548 | nsc_ircc_dma_xmit(self, iobase); | |
1549 | } | |
1550 | out: | |
1551 | /* Not busy transmitting anymore if window is not full, | |
1552 | * and if we don't need to change speed */ | |
1553 | if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0)) | |
1554 | netif_wake_queue(self->netdev); | |
1555 | ||
1556 | /* Restore bank register */ | |
1557 | outb(bank, iobase+BSR); | |
1558 | ||
1559 | dev->trans_start = jiffies; | |
1560 | spin_unlock_irqrestore(&self->lock, flags); | |
1561 | dev_kfree_skb(skb); | |
1562 | ||
6ed10654 | 1563 | return NETDEV_TX_OK; |
1da177e4 LT |
1564 | } |
1565 | ||
1566 | /* | |
1567 | * Function nsc_ircc_dma_xmit (self, iobase) | |
1568 | * | |
1569 | * Transmit data using DMA | |
1570 | * | |
1571 | */ | |
1572 | static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase) | |
1573 | { | |
1574 | int bsr; | |
1575 | ||
1576 | /* Save current bank */ | |
1577 | bsr = inb(iobase+BSR); | |
1578 | ||
1579 | /* Disable DMA */ | |
1580 | switch_bank(iobase, BANK0); | |
1581 | outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); | |
1582 | ||
1583 | self->io.direction = IO_XMIT; | |
1584 | ||
1585 | /* Choose transmit DMA channel */ | |
1586 | switch_bank(iobase, BANK2); | |
1587 | outb(ECR1_DMASWP|ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1); | |
1588 | ||
1589 | irda_setup_dma(self->io.dma, | |
1590 | ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start - | |
1591 | self->tx_buff.head) + self->tx_buff_dma, | |
1592 | self->tx_fifo.queue[self->tx_fifo.ptr].len, | |
1593 | DMA_TX_MODE); | |
1594 | ||
1595 | /* Enable DMA and SIR interaction pulse */ | |
1596 | switch_bank(iobase, BANK0); | |
1597 | outb(inb(iobase+MCR)|MCR_TX_DFR|MCR_DMA_EN|MCR_IR_PLS, iobase+MCR); | |
1598 | ||
1599 | /* Restore bank register */ | |
1600 | outb(bsr, iobase+BSR); | |
1601 | } | |
1602 | ||
1603 | /* | |
1604 | * Function nsc_ircc_pio_xmit (self, iobase) | |
1605 | * | |
1606 | * Transmit data using PIO. Returns the number of bytes that actually | |
1607 | * got transferred | |
1608 | * | |
1609 | */ | |
1610 | static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size) | |
1611 | { | |
1612 | int actual = 0; | |
1613 | __u8 bank; | |
1614 | ||
1da177e4 LT |
1615 | /* Save current bank */ |
1616 | bank = inb(iobase+BSR); | |
1617 | ||
1618 | switch_bank(iobase, BANK0); | |
1619 | if (!(inb_p(iobase+LSR) & LSR_TXEMP)) { | |
955a9d20 JP |
1620 | pr_debug("%s(), warning, FIFO not empty yet!\n", |
1621 | __func__); | |
1da177e4 LT |
1622 | |
1623 | /* FIFO may still be filled to the Tx interrupt threshold */ | |
1624 | fifo_size -= 17; | |
1625 | } | |
1626 | ||
1627 | /* Fill FIFO with current frame */ | |
1628 | while ((fifo_size-- > 0) && (actual < len)) { | |
1629 | /* Transmit next byte */ | |
1630 | outb(buf[actual++], iobase+TXD); | |
1631 | } | |
1632 | ||
955a9d20 JP |
1633 | pr_debug("%s(), fifo_size %d ; %d sent of %d\n", |
1634 | __func__, fifo_size, actual, len); | |
1da177e4 LT |
1635 | |
1636 | /* Restore bank */ | |
1637 | outb(bank, iobase+BSR); | |
1638 | ||
1639 | return actual; | |
1640 | } | |
1641 | ||
1642 | /* | |
1643 | * Function nsc_ircc_dma_xmit_complete (self) | |
1644 | * | |
1645 | * The transfer of a frame in finished. This function will only be called | |
1646 | * by the interrupt handler | |
1647 | * | |
1648 | */ | |
1649 | static int nsc_ircc_dma_xmit_complete(struct nsc_ircc_cb *self) | |
1650 | { | |
1651 | int iobase; | |
1652 | __u8 bank; | |
1653 | int ret = TRUE; | |
1654 | ||
1da177e4 LT |
1655 | iobase = self->io.fir_base; |
1656 | ||
1657 | /* Save current bank */ | |
1658 | bank = inb(iobase+BSR); | |
1659 | ||
1660 | /* Disable DMA */ | |
1661 | switch_bank(iobase, BANK0); | |
1662 | outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); | |
1663 | ||
42b2aa86 | 1664 | /* Check for underrun! */ |
1da177e4 | 1665 | if (inb(iobase+ASCR) & ASCR_TXUR) { |
af049081 SH |
1666 | self->netdev->stats.tx_errors++; |
1667 | self->netdev->stats.tx_fifo_errors++; | |
1da177e4 LT |
1668 | |
1669 | /* Clear bit, by writing 1 into it */ | |
1670 | outb(ASCR_TXUR, iobase+ASCR); | |
1671 | } else { | |
af049081 | 1672 | self->netdev->stats.tx_packets++; |
1da177e4 LT |
1673 | } |
1674 | ||
1675 | /* Finished with this frame, so prepare for next */ | |
1676 | self->tx_fifo.ptr++; | |
1677 | self->tx_fifo.len--; | |
1678 | ||
1679 | /* Any frames to be sent back-to-back? */ | |
1680 | if (self->tx_fifo.len) { | |
1681 | nsc_ircc_dma_xmit(self, iobase); | |
1682 | ||
1683 | /* Not finished yet! */ | |
1684 | ret = FALSE; | |
1685 | } else { | |
1686 | /* Reset Tx FIFO info */ | |
1687 | self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0; | |
1688 | self->tx_fifo.tail = self->tx_buff.head; | |
1689 | } | |
1690 | ||
1691 | /* Make sure we have room for more frames and | |
1692 | * that we don't need to change speed */ | |
1693 | if ((self->tx_fifo.free < MAX_TX_WINDOW) && (self->new_speed == 0)) { | |
1694 | /* Not busy transmitting anymore */ | |
1695 | /* Tell the network layer, that we can accept more frames */ | |
1696 | netif_wake_queue(self->netdev); | |
1697 | } | |
1698 | ||
1699 | /* Restore bank */ | |
1700 | outb(bank, iobase+BSR); | |
1701 | ||
1702 | return ret; | |
1703 | } | |
1704 | ||
1705 | /* | |
1706 | * Function nsc_ircc_dma_receive (self) | |
1707 | * | |
1708 | * Get ready for receiving a frame. The device will initiate a DMA | |
1709 | * if it starts to receive a frame. | |
1710 | * | |
1711 | */ | |
1712 | static int nsc_ircc_dma_receive(struct nsc_ircc_cb *self) | |
1713 | { | |
1714 | int iobase; | |
1715 | __u8 bsr; | |
1716 | ||
1717 | iobase = self->io.fir_base; | |
1718 | ||
1719 | /* Reset Tx FIFO info */ | |
1720 | self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0; | |
1721 | self->tx_fifo.tail = self->tx_buff.head; | |
1722 | ||
1723 | /* Save current bank */ | |
1724 | bsr = inb(iobase+BSR); | |
1725 | ||
1726 | /* Disable DMA */ | |
1727 | switch_bank(iobase, BANK0); | |
1728 | outb(inb(iobase+MCR) & ~MCR_DMA_EN, iobase+MCR); | |
1729 | ||
1730 | /* Choose DMA Rx, DMA Fairness, and Advanced mode */ | |
1731 | switch_bank(iobase, BANK2); | |
1732 | outb(ECR1_DMANF|ECR1_EXT_SL, iobase+ECR1); | |
1733 | ||
1734 | self->io.direction = IO_RECV; | |
1735 | self->rx_buff.data = self->rx_buff.head; | |
1736 | ||
1737 | /* Reset Rx FIFO. This will also flush the ST_FIFO */ | |
1738 | switch_bank(iobase, BANK0); | |
1739 | outb(FCR_RXSR|FCR_FIFO_EN, iobase+FCR); | |
1740 | ||
1741 | self->st_fifo.len = self->st_fifo.pending_bytes = 0; | |
1742 | self->st_fifo.tail = self->st_fifo.head = 0; | |
1743 | ||
1744 | irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize, | |
1745 | DMA_RX_MODE); | |
1746 | ||
1747 | /* Enable DMA */ | |
1748 | switch_bank(iobase, BANK0); | |
1749 | outb(inb(iobase+MCR)|MCR_DMA_EN, iobase+MCR); | |
1750 | ||
1751 | /* Restore bank register */ | |
1752 | outb(bsr, iobase+BSR); | |
1753 | ||
1754 | return 0; | |
1755 | } | |
1756 | ||
1757 | /* | |
1758 | * Function nsc_ircc_dma_receive_complete (self) | |
1759 | * | |
1760 | * Finished with receiving frames | |
1761 | * | |
1762 | * | |
1763 | */ | |
1764 | static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase) | |
1765 | { | |
1766 | struct st_fifo *st_fifo; | |
1767 | struct sk_buff *skb; | |
1768 | __u8 status; | |
1769 | __u8 bank; | |
1770 | int len; | |
1771 | ||
1772 | st_fifo = &self->st_fifo; | |
1773 | ||
1774 | /* Save current bank */ | |
1775 | bank = inb(iobase+BSR); | |
1776 | ||
1777 | /* Read all entries in status FIFO */ | |
1778 | switch_bank(iobase, BANK5); | |
1779 | while ((status = inb(iobase+FRM_ST)) & FRM_ST_VLD) { | |
1780 | /* We must empty the status FIFO no matter what */ | |
1781 | len = inb(iobase+RFLFL) | ((inb(iobase+RFLFH) & 0x1f) << 8); | |
1782 | ||
1783 | if (st_fifo->tail >= MAX_RX_WINDOW) { | |
955a9d20 | 1784 | pr_debug("%s(), window is full!\n", __func__); |
1da177e4 LT |
1785 | continue; |
1786 | } | |
1787 | ||
1788 | st_fifo->entries[st_fifo->tail].status = status; | |
1789 | st_fifo->entries[st_fifo->tail].len = len; | |
1790 | st_fifo->pending_bytes += len; | |
1791 | st_fifo->tail++; | |
1792 | st_fifo->len++; | |
1793 | } | |
1794 | /* Try to process all entries in status FIFO */ | |
1795 | while (st_fifo->len > 0) { | |
1796 | /* Get first entry */ | |
1797 | status = st_fifo->entries[st_fifo->head].status; | |
1798 | len = st_fifo->entries[st_fifo->head].len; | |
1799 | st_fifo->pending_bytes -= len; | |
1800 | st_fifo->head++; | |
1801 | st_fifo->len--; | |
1802 | ||
1803 | /* Check for errors */ | |
1804 | if (status & FRM_ST_ERR_MSK) { | |
1805 | if (status & FRM_ST_LOST_FR) { | |
1806 | /* Add number of lost frames to stats */ | |
af049081 | 1807 | self->netdev->stats.rx_errors += len; |
1da177e4 LT |
1808 | } else { |
1809 | /* Skip frame */ | |
af049081 | 1810 | self->netdev->stats.rx_errors++; |
1da177e4 LT |
1811 | |
1812 | self->rx_buff.data += len; | |
1813 | ||
1814 | if (status & FRM_ST_MAX_LEN) | |
af049081 | 1815 | self->netdev->stats.rx_length_errors++; |
1da177e4 LT |
1816 | |
1817 | if (status & FRM_ST_PHY_ERR) | |
af049081 | 1818 | self->netdev->stats.rx_frame_errors++; |
1da177e4 LT |
1819 | |
1820 | if (status & FRM_ST_BAD_CRC) | |
af049081 | 1821 | self->netdev->stats.rx_crc_errors++; |
1da177e4 LT |
1822 | } |
1823 | /* The errors below can be reported in both cases */ | |
1824 | if (status & FRM_ST_OVR1) | |
af049081 | 1825 | self->netdev->stats.rx_fifo_errors++; |
1da177e4 LT |
1826 | |
1827 | if (status & FRM_ST_OVR2) | |
af049081 | 1828 | self->netdev->stats.rx_fifo_errors++; |
1da177e4 LT |
1829 | } else { |
1830 | /* | |
1831 | * First we must make sure that the frame we | |
1832 | * want to deliver is all in main memory. If we | |
1833 | * cannot tell, then we check if the Rx FIFO is | |
1834 | * empty. If not then we will have to take a nap | |
1835 | * and try again later. | |
1836 | */ | |
1837 | if (st_fifo->pending_bytes < self->io.fifo_size) { | |
1838 | switch_bank(iobase, BANK0); | |
1839 | if (inb(iobase+LSR) & LSR_RXDA) { | |
1840 | /* Put this entry back in fifo */ | |
1841 | st_fifo->head--; | |
1842 | st_fifo->len++; | |
1843 | st_fifo->pending_bytes += len; | |
1844 | st_fifo->entries[st_fifo->head].status = status; | |
1845 | st_fifo->entries[st_fifo->head].len = len; | |
1846 | /* | |
1847 | * DMA not finished yet, so try again | |
1848 | * later, set timer value, resolution | |
1849 | * 125 us | |
1850 | */ | |
1851 | switch_bank(iobase, BANK4); | |
1852 | outb(0x02, iobase+TMRL); /* x 125 us */ | |
1853 | outb(0x00, iobase+TMRH); | |
1854 | ||
1855 | /* Start timer */ | |
1856 | outb(IRCR1_TMR_EN, iobase+IRCR1); | |
1857 | ||
1858 | /* Restore bank register */ | |
1859 | outb(bank, iobase+BSR); | |
1860 | ||
1861 | return FALSE; /* I'll be back! */ | |
1862 | } | |
1863 | } | |
1864 | ||
1865 | /* | |
1866 | * Remember the time we received this frame, so we can | |
1867 | * reduce the min turn time a bit since we will know | |
1868 | * how much time we have used for protocol processing | |
1869 | */ | |
1870 | do_gettimeofday(&self->stamp); | |
1871 | ||
1872 | skb = dev_alloc_skb(len+1); | |
1873 | if (skb == NULL) { | |
af049081 | 1874 | self->netdev->stats.rx_dropped++; |
1da177e4 LT |
1875 | |
1876 | /* Restore bank register */ | |
1877 | outb(bank, iobase+BSR); | |
1878 | ||
1879 | return FALSE; | |
1880 | } | |
1881 | ||
1882 | /* Make sure IP header gets aligned */ | |
1883 | skb_reserve(skb, 1); | |
1884 | ||
1885 | /* Copy frame without CRC */ | |
1886 | if (self->io.speed < 4000000) { | |
1887 | skb_put(skb, len-2); | |
27d7ff46 ACM |
1888 | skb_copy_to_linear_data(skb, |
1889 | self->rx_buff.data, | |
1890 | len - 2); | |
1da177e4 LT |
1891 | } else { |
1892 | skb_put(skb, len-4); | |
27d7ff46 ACM |
1893 | skb_copy_to_linear_data(skb, |
1894 | self->rx_buff.data, | |
1895 | len - 4); | |
1da177e4 LT |
1896 | } |
1897 | ||
1898 | /* Move to next frame */ | |
1899 | self->rx_buff.data += len; | |
af049081 SH |
1900 | self->netdev->stats.rx_bytes += len; |
1901 | self->netdev->stats.rx_packets++; | |
1da177e4 LT |
1902 | |
1903 | skb->dev = self->netdev; | |
459a98ed | 1904 | skb_reset_mac_header(skb); |
1da177e4 LT |
1905 | skb->protocol = htons(ETH_P_IRDA); |
1906 | netif_rx(skb); | |
1da177e4 LT |
1907 | } |
1908 | } | |
1909 | /* Restore bank register */ | |
1910 | outb(bank, iobase+BSR); | |
1911 | ||
1912 | return TRUE; | |
1913 | } | |
1914 | ||
1915 | /* | |
1916 | * Function nsc_ircc_pio_receive (self) | |
1917 | * | |
1918 | * Receive all data in receiver FIFO | |
1919 | * | |
1920 | */ | |
1921 | static void nsc_ircc_pio_receive(struct nsc_ircc_cb *self) | |
1922 | { | |
1923 | __u8 byte; | |
1924 | int iobase; | |
1925 | ||
1926 | iobase = self->io.fir_base; | |
1927 | ||
1928 | /* Receive all characters in Rx FIFO */ | |
1929 | do { | |
1930 | byte = inb(iobase+RXD); | |
af049081 SH |
1931 | async_unwrap_char(self->netdev, &self->netdev->stats, |
1932 | &self->rx_buff, byte); | |
1da177e4 LT |
1933 | } while (inb(iobase+LSR) & LSR_RXDA); /* Data available */ |
1934 | } | |
1935 | ||
1936 | /* | |
1937 | * Function nsc_ircc_sir_interrupt (self, eir) | |
1938 | * | |
1939 | * Handle SIR interrupt | |
1940 | * | |
1941 | */ | |
1942 | static void nsc_ircc_sir_interrupt(struct nsc_ircc_cb *self, int eir) | |
1943 | { | |
1944 | int actual; | |
1945 | ||
1946 | /* Check if transmit FIFO is low on data */ | |
1947 | if (eir & EIR_TXLDL_EV) { | |
1948 | /* Write data left in transmit buffer */ | |
1949 | actual = nsc_ircc_pio_write(self->io.fir_base, | |
1950 | self->tx_buff.data, | |
1951 | self->tx_buff.len, | |
1952 | self->io.fifo_size); | |
1953 | self->tx_buff.data += actual; | |
1954 | self->tx_buff.len -= actual; | |
1955 | ||
1956 | self->io.direction = IO_XMIT; | |
1957 | ||
1958 | /* Check if finished */ | |
1959 | if (self->tx_buff.len > 0) | |
1960 | self->ier = IER_TXLDL_IE; | |
1961 | else { | |
1962 | ||
af049081 | 1963 | self->netdev->stats.tx_packets++; |
1da177e4 LT |
1964 | netif_wake_queue(self->netdev); |
1965 | self->ier = IER_TXEMP_IE; | |
1966 | } | |
1967 | ||
1968 | } | |
1969 | /* Check if transmission has completed */ | |
1970 | if (eir & EIR_TXEMP_EV) { | |
1971 | /* Turn around and get ready to receive some data */ | |
1972 | self->io.direction = IO_RECV; | |
1973 | self->ier = IER_RXHDL_IE; | |
1974 | /* Check if we need to change the speed? | |
1975 | * Need to be after self->io.direction to avoid race with | |
1976 | * nsc_ircc_hard_xmit_sir() - Jean II */ | |
1977 | if (self->new_speed) { | |
955a9d20 | 1978 | pr_debug("%s(), Changing speed!\n", __func__); |
1da177e4 LT |
1979 | self->ier = nsc_ircc_change_speed(self, |
1980 | self->new_speed); | |
1981 | self->new_speed = 0; | |
1982 | netif_wake_queue(self->netdev); | |
1983 | ||
1984 | /* Check if we are going to FIR */ | |
1985 | if (self->io.speed > 115200) { | |
1986 | /* No need to do anymore SIR stuff */ | |
1987 | return; | |
1988 | } | |
1989 | } | |
1990 | } | |
1991 | ||
1992 | /* Rx FIFO threshold or timeout */ | |
1993 | if (eir & EIR_RXHDL_EV) { | |
1994 | nsc_ircc_pio_receive(self); | |
1995 | ||
1996 | /* Keep receiving */ | |
1997 | self->ier = IER_RXHDL_IE; | |
1998 | } | |
1999 | } | |
2000 | ||
2001 | /* | |
2002 | * Function nsc_ircc_fir_interrupt (self, eir) | |
2003 | * | |
2004 | * Handle MIR/FIR interrupt | |
2005 | * | |
2006 | */ | |
2007 | static void nsc_ircc_fir_interrupt(struct nsc_ircc_cb *self, int iobase, | |
2008 | int eir) | |
2009 | { | |
2010 | __u8 bank; | |
2011 | ||
2012 | bank = inb(iobase+BSR); | |
2013 | ||
2014 | /* Status FIFO event*/ | |
2015 | if (eir & EIR_SFIF_EV) { | |
2016 | /* Check if DMA has finished */ | |
2017 | if (nsc_ircc_dma_receive_complete(self, iobase)) { | |
2018 | /* Wait for next status FIFO interrupt */ | |
2019 | self->ier = IER_SFIF_IE; | |
2020 | } else { | |
2021 | self->ier = IER_SFIF_IE | IER_TMR_IE; | |
2022 | } | |
2023 | } else if (eir & EIR_TMR_EV) { /* Timer finished */ | |
2024 | /* Disable timer */ | |
2025 | switch_bank(iobase, BANK4); | |
2026 | outb(0, iobase+IRCR1); | |
2027 | ||
2028 | /* Clear timer event */ | |
2029 | switch_bank(iobase, BANK0); | |
2030 | outb(ASCR_CTE, iobase+ASCR); | |
2031 | ||
2032 | /* Check if this is a Tx timer interrupt */ | |
2033 | if (self->io.direction == IO_XMIT) { | |
2034 | nsc_ircc_dma_xmit(self, iobase); | |
2035 | ||
2036 | /* Interrupt on DMA */ | |
2037 | self->ier = IER_DMA_IE; | |
2038 | } else { | |
2039 | /* Check (again) if DMA has finished */ | |
2040 | if (nsc_ircc_dma_receive_complete(self, iobase)) { | |
2041 | self->ier = IER_SFIF_IE; | |
2042 | } else { | |
2043 | self->ier = IER_SFIF_IE | IER_TMR_IE; | |
2044 | } | |
2045 | } | |
2046 | } else if (eir & EIR_DMA_EV) { | |
2047 | /* Finished with all transmissions? */ | |
2048 | if (nsc_ircc_dma_xmit_complete(self)) { | |
2049 | if(self->new_speed != 0) { | |
2050 | /* As we stop the Tx queue, the speed change | |
2051 | * need to be done when the Tx fifo is | |
2052 | * empty. Ask for a Tx done interrupt */ | |
2053 | self->ier = IER_TXEMP_IE; | |
2054 | } else { | |
2055 | /* Check if there are more frames to be | |
2056 | * transmitted */ | |
2057 | if (irda_device_txqueue_empty(self->netdev)) { | |
2058 | /* Prepare for receive */ | |
2059 | nsc_ircc_dma_receive(self); | |
2060 | self->ier = IER_SFIF_IE; | |
2061 | } else | |
6c91023d JP |
2062 | net_warn_ratelimited("%s(), potential Tx queue lockup !\n", |
2063 | __func__); | |
1da177e4 LT |
2064 | } |
2065 | } else { | |
2066 | /* Not finished yet, so interrupt on DMA again */ | |
2067 | self->ier = IER_DMA_IE; | |
2068 | } | |
2069 | } else if (eir & EIR_TXEMP_EV) { | |
2070 | /* The Tx FIFO has totally drained out, so now we can change | |
2071 | * the speed... - Jean II */ | |
2072 | self->ier = nsc_ircc_change_speed(self, self->new_speed); | |
2073 | self->new_speed = 0; | |
2074 | netif_wake_queue(self->netdev); | |
2075 | /* Note : nsc_ircc_change_speed() restarted Rx fifo */ | |
2076 | } | |
2077 | ||
2078 | outb(bank, iobase+BSR); | |
2079 | } | |
2080 | ||
2081 | /* | |
2082 | * Function nsc_ircc_interrupt (irq, dev_id, regs) | |
2083 | * | |
2084 | * An interrupt from the chip has arrived. Time to do some work | |
2085 | * | |
2086 | */ | |
7d12e780 | 2087 | static irqreturn_t nsc_ircc_interrupt(int irq, void *dev_id) |
1da177e4 | 2088 | { |
c31f28e7 | 2089 | struct net_device *dev = dev_id; |
1da177e4 LT |
2090 | struct nsc_ircc_cb *self; |
2091 | __u8 bsr, eir; | |
2092 | int iobase; | |
2093 | ||
4cf1653a | 2094 | self = netdev_priv(dev); |
1da177e4 LT |
2095 | |
2096 | spin_lock(&self->lock); | |
2097 | ||
2098 | iobase = self->io.fir_base; | |
2099 | ||
2100 | bsr = inb(iobase+BSR); /* Save current bank */ | |
2101 | ||
2102 | switch_bank(iobase, BANK0); | |
2103 | self->ier = inb(iobase+IER); | |
2104 | eir = inb(iobase+EIR) & self->ier; /* Mask out the interesting ones */ | |
2105 | ||
2106 | outb(0, iobase+IER); /* Disable interrupts */ | |
2107 | ||
2108 | if (eir) { | |
2109 | /* Dispatch interrupt handler for the current speed */ | |
2110 | if (self->io.speed > 115200) | |
2111 | nsc_ircc_fir_interrupt(self, iobase, eir); | |
2112 | else | |
2113 | nsc_ircc_sir_interrupt(self, eir); | |
2114 | } | |
2115 | ||
2116 | outb(self->ier, iobase+IER); /* Restore interrupts */ | |
2117 | outb(bsr, iobase+BSR); /* Restore bank register */ | |
2118 | ||
2119 | spin_unlock(&self->lock); | |
2120 | return IRQ_RETVAL(eir); | |
2121 | } | |
2122 | ||
2123 | /* | |
2124 | * Function nsc_ircc_is_receiving (self) | |
2125 | * | |
2126 | * Return TRUE is we are currently receiving a frame | |
2127 | * | |
2128 | */ | |
2129 | static int nsc_ircc_is_receiving(struct nsc_ircc_cb *self) | |
2130 | { | |
2131 | unsigned long flags; | |
2132 | int status = FALSE; | |
2133 | int iobase; | |
2134 | __u8 bank; | |
2135 | ||
2136 | IRDA_ASSERT(self != NULL, return FALSE;); | |
2137 | ||
2138 | spin_lock_irqsave(&self->lock, flags); | |
2139 | ||
2140 | if (self->io.speed > 115200) { | |
2141 | iobase = self->io.fir_base; | |
2142 | ||
2143 | /* Check if rx FIFO is not empty */ | |
2144 | bank = inb(iobase+BSR); | |
2145 | switch_bank(iobase, BANK2); | |
2146 | if ((inb(iobase+RXFLV) & 0x3f) != 0) { | |
2147 | /* We are receiving something */ | |
2148 | status = TRUE; | |
2149 | } | |
2150 | outb(bank, iobase+BSR); | |
2151 | } else | |
2152 | status = (self->rx_buff.state != OUTSIDE_FRAME); | |
2153 | ||
2154 | spin_unlock_irqrestore(&self->lock, flags); | |
2155 | ||
2156 | return status; | |
2157 | } | |
2158 | ||
2159 | /* | |
2160 | * Function nsc_ircc_net_open (dev) | |
2161 | * | |
2162 | * Start the device | |
2163 | * | |
2164 | */ | |
2165 | static int nsc_ircc_net_open(struct net_device *dev) | |
2166 | { | |
2167 | struct nsc_ircc_cb *self; | |
2168 | int iobase; | |
2169 | char hwname[32]; | |
2170 | __u8 bank; | |
2171 | ||
1da177e4 LT |
2172 | |
2173 | IRDA_ASSERT(dev != NULL, return -1;); | |
4cf1653a | 2174 | self = netdev_priv(dev); |
1da177e4 LT |
2175 | |
2176 | IRDA_ASSERT(self != NULL, return 0;); | |
2177 | ||
2178 | iobase = self->io.fir_base; | |
2179 | ||
2180 | if (request_irq(self->io.irq, nsc_ircc_interrupt, 0, dev->name, dev)) { | |
6c91023d JP |
2181 | net_warn_ratelimited("%s, unable to allocate irq=%d\n", |
2182 | driver_name, self->io.irq); | |
1da177e4 LT |
2183 | return -EAGAIN; |
2184 | } | |
2185 | /* | |
2186 | * Always allocate the DMA channel after the IRQ, and clean up on | |
2187 | * failure. | |
2188 | */ | |
2189 | if (request_dma(self->io.dma, dev->name)) { | |
6c91023d JP |
2190 | net_warn_ratelimited("%s, unable to allocate dma=%d\n", |
2191 | driver_name, self->io.dma); | |
1da177e4 LT |
2192 | free_irq(self->io.irq, dev); |
2193 | return -EAGAIN; | |
2194 | } | |
2195 | ||
2196 | /* Save current bank */ | |
2197 | bank = inb(iobase+BSR); | |
2198 | ||
2199 | /* turn on interrupts */ | |
2200 | switch_bank(iobase, BANK0); | |
2201 | outb(IER_LS_IE | IER_RXHDL_IE, iobase+IER); | |
2202 | ||
2203 | /* Restore bank register */ | |
2204 | outb(bank, iobase+BSR); | |
2205 | ||
2206 | /* Ready to play! */ | |
2207 | netif_start_queue(dev); | |
2208 | ||
2209 | /* Give self a hardware name */ | |
2210 | sprintf(hwname, "NSC-FIR @ 0x%03x", self->io.fir_base); | |
2211 | ||
2212 | /* | |
2213 | * Open new IrLAP layer instance, now that everything should be | |
2214 | * initialized properly | |
2215 | */ | |
2216 | self->irlap = irlap_open(dev, &self->qos, hwname); | |
2217 | ||
2218 | return 0; | |
2219 | } | |
2220 | ||
2221 | /* | |
2222 | * Function nsc_ircc_net_close (dev) | |
2223 | * | |
2224 | * Stop the device | |
2225 | * | |
2226 | */ | |
2227 | static int nsc_ircc_net_close(struct net_device *dev) | |
2228 | { | |
2229 | struct nsc_ircc_cb *self; | |
2230 | int iobase; | |
2231 | __u8 bank; | |
2232 | ||
1da177e4 LT |
2233 | |
2234 | IRDA_ASSERT(dev != NULL, return -1;); | |
2235 | ||
4cf1653a | 2236 | self = netdev_priv(dev); |
1da177e4 LT |
2237 | IRDA_ASSERT(self != NULL, return 0;); |
2238 | ||
2239 | /* Stop device */ | |
2240 | netif_stop_queue(dev); | |
2241 | ||
2242 | /* Stop and remove instance of IrLAP */ | |
2243 | if (self->irlap) | |
2244 | irlap_close(self->irlap); | |
2245 | self->irlap = NULL; | |
2246 | ||
2247 | iobase = self->io.fir_base; | |
2248 | ||
2249 | disable_dma(self->io.dma); | |
2250 | ||
2251 | /* Save current bank */ | |
2252 | bank = inb(iobase+BSR); | |
2253 | ||
2254 | /* Disable interrupts */ | |
2255 | switch_bank(iobase, BANK0); | |
2256 | outb(0, iobase+IER); | |
2257 | ||
2258 | free_irq(self->io.irq, dev); | |
2259 | free_dma(self->io.dma); | |
2260 | ||
2261 | /* Restore bank register */ | |
2262 | outb(bank, iobase+BSR); | |
2263 | ||
2264 | return 0; | |
2265 | } | |
2266 | ||
2267 | /* | |
2268 | * Function nsc_ircc_net_ioctl (dev, rq, cmd) | |
2269 | * | |
2270 | * Process IOCTL commands for this device | |
2271 | * | |
2272 | */ | |
2273 | static int nsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2274 | { | |
2275 | struct if_irda_req *irq = (struct if_irda_req *) rq; | |
2276 | struct nsc_ircc_cb *self; | |
2277 | unsigned long flags; | |
2278 | int ret = 0; | |
2279 | ||
2280 | IRDA_ASSERT(dev != NULL, return -1;); | |
2281 | ||
4cf1653a | 2282 | self = netdev_priv(dev); |
1da177e4 LT |
2283 | |
2284 | IRDA_ASSERT(self != NULL, return -1;); | |
2285 | ||
955a9d20 | 2286 | pr_debug("%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd); |
1da177e4 LT |
2287 | |
2288 | switch (cmd) { | |
2289 | case SIOCSBANDWIDTH: /* Set bandwidth */ | |
2290 | if (!capable(CAP_NET_ADMIN)) { | |
2291 | ret = -EPERM; | |
2292 | break; | |
2293 | } | |
2294 | spin_lock_irqsave(&self->lock, flags); | |
2295 | nsc_ircc_change_speed(self, irq->ifr_baudrate); | |
2296 | spin_unlock_irqrestore(&self->lock, flags); | |
2297 | break; | |
2298 | case SIOCSMEDIABUSY: /* Set media busy */ | |
2299 | if (!capable(CAP_NET_ADMIN)) { | |
2300 | ret = -EPERM; | |
2301 | break; | |
2302 | } | |
2303 | irda_device_set_media_busy(self->netdev, TRUE); | |
2304 | break; | |
2305 | case SIOCGRECEIVING: /* Check if we are receiving right now */ | |
2306 | /* This is already protected */ | |
2307 | irq->ifr_receiving = nsc_ircc_is_receiving(self); | |
2308 | break; | |
2309 | default: | |
2310 | ret = -EOPNOTSUPP; | |
2311 | } | |
2312 | return ret; | |
2313 | } | |
2314 | ||
3b99b93b | 2315 | static int nsc_ircc_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 2316 | { |
3b99b93b DT |
2317 | struct nsc_ircc_cb *self = platform_get_drvdata(dev); |
2318 | int bank; | |
2319 | unsigned long flags; | |
2320 | int iobase = self->io.fir_base; | |
1da177e4 LT |
2321 | |
2322 | if (self->io.suspended) | |
3b99b93b | 2323 | return 0; |
1da177e4 | 2324 | |
955a9d20 | 2325 | pr_debug("%s, Suspending\n", driver_name); |
1da177e4 | 2326 | |
3b99b93b DT |
2327 | rtnl_lock(); |
2328 | if (netif_running(self->netdev)) { | |
2329 | netif_device_detach(self->netdev); | |
2330 | spin_lock_irqsave(&self->lock, flags); | |
2331 | /* Save current bank */ | |
2332 | bank = inb(iobase+BSR); | |
2333 | ||
2334 | /* Disable interrupts */ | |
2335 | switch_bank(iobase, BANK0); | |
2336 | outb(0, iobase+IER); | |
2337 | ||
2338 | /* Restore bank register */ | |
2339 | outb(bank, iobase+BSR); | |
2340 | ||
2341 | spin_unlock_irqrestore(&self->lock, flags); | |
2342 | free_irq(self->io.irq, self->netdev); | |
2343 | disable_dma(self->io.dma); | |
2344 | } | |
1da177e4 | 2345 | self->io.suspended = 1; |
3b99b93b DT |
2346 | rtnl_unlock(); |
2347 | ||
2348 | return 0; | |
1da177e4 LT |
2349 | } |
2350 | ||
3b99b93b | 2351 | static int nsc_ircc_resume(struct platform_device *dev) |
1da177e4 | 2352 | { |
3b99b93b DT |
2353 | struct nsc_ircc_cb *self = platform_get_drvdata(dev); |
2354 | unsigned long flags; | |
2355 | ||
1da177e4 | 2356 | if (!self->io.suspended) |
3b99b93b | 2357 | return 0; |
1da177e4 | 2358 | |
955a9d20 | 2359 | pr_debug("%s, Waking up\n", driver_name); |
3b99b93b DT |
2360 | |
2361 | rtnl_lock(); | |
1da177e4 | 2362 | nsc_ircc_setup(&self->io); |
3b99b93b | 2363 | nsc_ircc_init_dongle_interface(self->io.fir_base, self->io.dongle_id); |
1da177e4 | 2364 | |
3b99b93b DT |
2365 | if (netif_running(self->netdev)) { |
2366 | if (request_irq(self->io.irq, nsc_ircc_interrupt, 0, | |
2367 | self->netdev->name, self->netdev)) { | |
6c91023d JP |
2368 | net_warn_ratelimited("%s, unable to allocate irq=%d\n", |
2369 | driver_name, self->io.irq); | |
3b99b93b DT |
2370 | |
2371 | /* | |
2372 | * Don't fail resume process, just kill this | |
2373 | * network interface | |
2374 | */ | |
2375 | unregister_netdevice(self->netdev); | |
2376 | } else { | |
2377 | spin_lock_irqsave(&self->lock, flags); | |
2378 | nsc_ircc_change_speed(self, self->io.speed); | |
2379 | spin_unlock_irqrestore(&self->lock, flags); | |
2380 | netif_device_attach(self->netdev); | |
2381 | } | |
2382 | ||
2383 | } else { | |
2384 | spin_lock_irqsave(&self->lock, flags); | |
2385 | nsc_ircc_change_speed(self, 9600); | |
2386 | spin_unlock_irqrestore(&self->lock, flags); | |
2387 | } | |
1da177e4 | 2388 | self->io.suspended = 0; |
3b99b93b | 2389 | rtnl_unlock(); |
1da177e4 | 2390 | |
3b99b93b | 2391 | return 0; |
1da177e4 LT |
2392 | } |
2393 | ||
2394 | MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>"); | |
2395 | MODULE_DESCRIPTION("NSC IrDA Device Driver"); | |
2396 | MODULE_LICENSE("GPL"); | |
2397 | ||
2398 | ||
2399 | module_param(qos_mtt_bits, int, 0); | |
2400 | MODULE_PARM_DESC(qos_mtt_bits, "Minimum Turn Time"); | |
2401 | module_param_array(io, int, NULL, 0); | |
2402 | MODULE_PARM_DESC(io, "Base I/O addresses"); | |
2403 | module_param_array(irq, int, NULL, 0); | |
2404 | MODULE_PARM_DESC(irq, "IRQ lines"); | |
2405 | module_param_array(dma, int, NULL, 0); | |
2406 | MODULE_PARM_DESC(dma, "DMA channels"); | |
2407 | module_param(dongle_id, int, 0); | |
2408 | MODULE_PARM_DESC(dongle_id, "Type-id of used dongle"); | |
2409 | ||
2410 | module_init(nsc_ircc_init); | |
2411 | module_exit(nsc_ircc_cleanup); | |
2412 |