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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/drzeus/mmc
[deliverable/linux.git] / drivers / net / irda / smsc-ircc2.c
CommitLineData
1da177e4
LT		 1/*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
527b6af4
DT		 7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
1da177e4
LT		 11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
c1e14a6e 14 * Copyright (c) 2006 Linus Walleij
1da177e4
LT		 15 *
16 *
17 * Based on smc-ircc.c:
18 *
19 * Copyright (c) 2001 Stefani Seibold
20 * Copyright (c) 1999-2001 Dag Brattli
527b6af4 21 * Copyright (c) 1998-1999 Thomas Davis,
1da177e4
LT		 22 *
23 * and irport.c:
24 *
25 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
26 *
527b6af4
DT		 27 *
28 * This program is free software; you can redistribute it and/or
29 * modify it under the terms of the GNU General Public License as
30 * published by the Free Software Foundation; either version 2 of
1da177e4 31 * the License, or (at your option) any later version.
527b6af4 32 *
1da177e4
LT		 33 * This program is distributed in the hope that it will be useful,
34 * but WITHOUT ANY WARRANTY; without even the implied warranty of
35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
36 * GNU General Public License for more details.
527b6af4
DT		 37 *
38 * You should have received a copy of the GNU General Public License
39 * along with this program; if not, write to the Free Software
40 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1da177e4
LT		 41 * MA 02111-1307 USA
42 *
43 ********************************************************************/
44
45#include <linux/module.h>
46#include <linux/kernel.h>
47#include <linux/types.h>
48#include <linux/skbuff.h>
49#include <linux/netdevice.h>
50#include <linux/ioport.h>
51#include <linux/delay.h>
52#include <linux/slab.h>
53#include <linux/init.h>
54#include <linux/rtnetlink.h>
55#include <linux/serial_reg.h>
56#include <linux/dma-mapping.h>
d94c77b9 57#include <linux/pnp.h>
d052d1be 58#include <linux/platform_device.h>
1da177e4
LT		 59
60#include <asm/io.h>
61#include <asm/dma.h>
62#include <asm/byteorder.h>
63
64#include <linux/spinlock.h>
65#include <linux/pm.h>
c1e14a6e
LW		 66#ifdef CONFIG_PCI
67#include <linux/pci.h>
68#endif
1da177e4
LT		 69
70#include <net/irda/wrapper.h>
71#include <net/irda/irda.h>
72#include <net/irda/irda_device.h>
73
74#include "smsc-ircc2.h"
75#include "smsc-sio.h"
76
98b77773
DT		 77
78MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
79MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
80MODULE_LICENSE("GPL");
81
cbcdd772 82static int smsc_nopnp = 1;
d0d4f69b
BH		 83module_param_named(nopnp, smsc_nopnp, bool, 0);
84MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
85
916f11c7
BH		 86#define DMA_INVAL 255
87static int ircc_dma = DMA_INVAL;
98b77773
DT		 88module_param(ircc_dma, int, 0);
89MODULE_PARM_DESC(ircc_dma, "DMA channel");
90
916f11c7
BH		 91#define IRQ_INVAL 255
92static int ircc_irq = IRQ_INVAL;
98b77773
DT		 93module_param(ircc_irq, int, 0);
94MODULE_PARM_DESC(ircc_irq, "IRQ line");
95
96static int ircc_fir;
97module_param(ircc_fir, int, 0);
98MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
99
100static int ircc_sir;
101module_param(ircc_sir, int, 0);
102MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
103
104static int ircc_cfg;
105module_param(ircc_cfg, int, 0);
106MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
107
108static int ircc_transceiver;
109module_param(ircc_transceiver, int, 0);
110MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
111
1da177e4
LT		 112/* Types */
113
c1e14a6e
LW		 114#ifdef CONFIG_PCI
115struct smsc_ircc_subsystem_configuration {
116 unsigned short vendor; /* PCI vendor ID */
117 unsigned short device; /* PCI vendor ID */
118 unsigned short subvendor; /* PCI subsystem vendor ID */
119 unsigned short subdevice; /* PCI sybsystem device ID */
120 unsigned short sir_io; /* I/O port for SIR */
121 unsigned short fir_io; /* I/O port for FIR */
122 unsigned char fir_irq; /* FIR IRQ */
123 unsigned char fir_dma; /* FIR DMA */
124 unsigned short cfg_base; /* I/O port for chip configuration */
125 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
126 const char *name; /* name shown as info */
127};
128#endif
129
1da177e4
LT		 130struct smsc_transceiver {
131 char *name;
527b6af4 132 void (*set_for_speed)(int fir_base, u32 speed);
1da177e4
LT		 133 int (*probe)(int fir_base);
134};
1da177e4
LT		 135
136struct smsc_chip {
137 char *name;
138 #if 0
139 u8 type;
140 #endif
141 u16 flags;
142 u8 devid;
143 u8 rev;
144};
1da177e4
LT		 145
146struct smsc_chip_address {
147 unsigned int cfg_base;
148 unsigned int type;
149};
1da177e4
LT		 150
151/* Private data for each instance */
152struct smsc_ircc_cb {
153 struct net_device *netdev; /* Yes! we are some kind of netdevice */
154 struct net_device_stats stats;
155 struct irlap_cb *irlap; /* The link layer we are binded to */
527b6af4 156
1da177e4
LT		 157 chipio_t io; /* IrDA controller information */
158 iobuff_t tx_buff; /* Transmit buffer */
159 iobuff_t rx_buff; /* Receive buffer */
160 dma_addr_t tx_buff_dma;
161 dma_addr_t rx_buff_dma;
162
163 struct qos_info qos; /* QoS capabilities for this device */
164
165 spinlock_t lock; /* For serializing operations */
527b6af4 166
1da177e4
LT		 167 __u32 new_speed;
168 __u32 flags; /* Interface flags */
169
170 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
171 int tx_len; /* Number of frames in tx_buff */
172
173 int transceiver;
6bb3b2cd 174 struct platform_device *pldev;
1da177e4
LT		 175};
176
177/* Constants */
178
6bb3b2cd
DT		 179#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
180
1da177e4
LT		 181#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
182#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
98b77773 183#define SMSC_IRCC2_C_NET_TIMEOUT 0
1da177e4
LT		 184#define SMSC_IRCC2_C_SIR_STOP 0
185
6bb3b2cd
DT		 186static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
187
1da177e4
LT		 188/* Prototypes */
189
190static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
191static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
192static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
193static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
194static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
195static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
80a90589
DT		 196static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
197static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
1da177e4
LT		 198static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
199static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
200static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
80a90589
DT		 201static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
202static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
0fa2f491
DT		 203static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
204static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
7d12e780 205static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
1da177e4
LT		 206static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
207static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
208#if SMSC_IRCC2_C_SIR_STOP
209static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
210#endif
211static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
212static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
213static int smsc_ircc_net_open(struct net_device *dev);
214static int smsc_ircc_net_close(struct net_device *dev);
215static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
216#if SMSC_IRCC2_C_NET_TIMEOUT
217static void smsc_ircc_timeout(struct net_device *dev);
218#endif
219static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
1da177e4
LT		 220static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
221static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
222static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
223static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
224
225/* Probing */
226static int __init smsc_ircc_look_for_chips(void);
b6158d23
DT		 227static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
228static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
229static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
1da177e4
LT		 230static int __init smsc_superio_fdc(unsigned short cfg_base);
231static int __init smsc_superio_lpc(unsigned short cfg_base);
c1e14a6e
LW		 232#ifdef CONFIG_PCI
233static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
234static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
08d09997
LW		 235static void __init preconfigure_ali_port(struct pci_dev *dev,
236 unsigned short port);
c1e14a6e
LW		 237static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
238static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
239 unsigned short ircc_fir,
240 unsigned short ircc_sir,
241 unsigned char ircc_dma,
242 unsigned char ircc_irq);
243#endif
1da177e4
LT		 244
245/* Transceivers specific functions */
246
247static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
248static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
249static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
250static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
251static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
252static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
253
254/* Power Management */
255
3ae5eaec
RK		 256static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
257static int smsc_ircc_resume(struct platform_device *dev);
1da177e4 258
3ae5eaec 259static struct platform_driver smsc_ircc_driver = {
6bb3b2cd
DT		 260 .suspend = smsc_ircc_suspend,
261 .resume = smsc_ircc_resume,
3ae5eaec
RK		 262 .driver = {
263 .name = SMSC_IRCC2_DRIVER_NAME,
264 },
6bb3b2cd 265};
1da177e4
LT		 266
267/* Transceivers for SMSC-ircc */
268
b6158d23 269static struct smsc_transceiver smsc_transceivers[] =
1da177e4 270{
98b77773
DT		 271 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
272 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
273 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
274 { NULL, NULL }
1da177e4 275};
a956f4ca 276#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
1da177e4
LT		 277
278/* SMC SuperIO chipsets definitions */
279
280#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
281#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
282#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
283#define SIR 0 /* SuperIO Chip has only slow IRDA */
284#define FIR 4 /* SuperIO Chip has fast IRDA */
285#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
286
b6158d23 287static struct smsc_chip __initdata fdc_chips_flat[] =
1da177e4
LT		 288{
289 /* Base address 0x3f0 or 0x370 */
290 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
291 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
292 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
293 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
294 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
295 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
296 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
297 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
298 { NULL }
299};
300
b6158d23 301static struct smsc_chip __initdata fdc_chips_paged[] =
1da177e4
LT		 302{
303 /* Base address 0x3f0 or 0x370 */
304 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
305 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
306 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
307 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
308 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
309 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
310 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
311 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
312 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
313 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
314 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
315 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
316 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
317 { NULL }
318};
319
b6158d23 320static struct smsc_chip __initdata lpc_chips_flat[] =
1da177e4
LT		 321{
322 /* Base address 0x2E or 0x4E */
323 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
afdf27c9 324 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
1da177e4
LT		 325 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
326 { NULL }
327};
328
b6158d23 329static struct smsc_chip __initdata lpc_chips_paged[] =
1da177e4
LT		 330{
331 /* Base address 0x2E or 0x4E */
332 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
333 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
334 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
335 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
336 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
337 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
338 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
339 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
340 { NULL }
341};
342
343#define SMSCSIO_TYPE_FDC 1
344#define SMSCSIO_TYPE_LPC 2
345#define SMSCSIO_TYPE_FLAT 4
346#define SMSCSIO_TYPE_PAGED 8
347
b6158d23 348static struct smsc_chip_address __initdata possible_addresses[] =
1da177e4 349{
98b77773
DT		 350 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
353 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
354 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
355 { 0, 0 }
1da177e4
LT		 356};
357
358/* Globals */
359
98b77773
DT		 360static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
361static unsigned short dev_count;
1da177e4
LT		 362
363static inline void register_bank(int iobase, int bank)
364{
98b77773
DT		 365 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
366 iobase + IRCC_MASTER);
1da177e4
LT		 367}
368
d94c77b9
DB		 369/* PNP hotplug support */
370static const struct pnp_device_id smsc_ircc_pnp_table[] = {
371 { .id = "SMCf010", .driver_data = 0 },
372 /* and presumably others */
373 { }
374};
375MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
d0d4f69b
BH		 376
377static int pnp_driver_registered;
378
379static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev,
380 const struct pnp_device_id *dev_id)
381{
382 unsigned int firbase, sirbase;
383 u8 dma, irq;
384
385 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
386 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
387 return -EINVAL;
388
389 sirbase = pnp_port_start(dev, 0);
390 firbase = pnp_port_start(dev, 1);
391 dma = pnp_dma(dev, 0);
392 irq = pnp_irq(dev, 0);
393
394 if (smsc_ircc_open(firbase, sirbase, dma, irq))
395 return -ENODEV;
396
397 return 0;
398}
399
400static struct pnp_driver smsc_ircc_pnp_driver = {
401 .name = "smsc-ircc2",
402 .id_table = smsc_ircc_pnp_table,
403 .probe = smsc_ircc_pnp_probe,
404};
d94c77b9 405
1da177e4
LT		 406
407/*******************************************************************************
408 *
409 *
410 * SMSC-ircc stuff
411 *
412 *
413 *******************************************************************************/
414
d0d4f69b
BH		 415static int __init smsc_ircc_legacy_probe(void)
416{
417 int ret = 0;
418
7c31d2f5
BH		 419#ifdef CONFIG_PCI
420 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
421 /* Ignore errors from preconfiguration */
422 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
423 }
424#endif
425
d0d4f69b
BH		 426 if (ircc_fir > 0 && ircc_sir > 0) {
427 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
428 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
429
430 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
431 ret = -ENODEV;
432 } else {
433 ret = -ENODEV;
434
435 /* try user provided configuration register base address */
436 if (ircc_cfg > 0) {
437 IRDA_MESSAGE(" Overriding configuration address "
438 "0x%04x\n", ircc_cfg);
439 if (!smsc_superio_fdc(ircc_cfg))
440 ret = 0;
441 if (!smsc_superio_lpc(ircc_cfg))
442 ret = 0;
443 }
444
445 if (smsc_ircc_look_for_chips() > 0)
446 ret = 0;
447 }
448 return ret;
449}
450
1da177e4
LT		 451/*
452 * Function smsc_ircc_init ()
453 *
454 * Initialize chip. Just try to find out how many chips we are dealing with
455 * and where they are
456 */
457static int __init smsc_ircc_init(void)
458{
6bb3b2cd 459 int ret;
1da177e4
LT		 460
461 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
462
3ae5eaec 463 ret = platform_driver_register(&smsc_ircc_driver);
6bb3b2cd
DT		 464 if (ret) {
465 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
466 return ret;
467 }
468
98b77773 469 dev_count = 0;
527b6af4 470
d0d4f69b
BH		 471 if (smsc_nopnp || !pnp_platform_devices ||
472 ircc_cfg || ircc_fir || ircc_sir ||
473 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
474 ret = smsc_ircc_legacy_probe();
6bb3b2cd 475 } else {
d0d4f69b
BH		 476 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
477 pnp_driver_registered = 1;
1da177e4 478 }
527b6af4 479
d0d4f69b
BH		 480 if (ret) {
481 if (pnp_driver_registered)
482 pnp_unregister_driver(&smsc_ircc_pnp_driver);
3ae5eaec 483 platform_driver_unregister(&smsc_ircc_driver);
d0d4f69b 484 }
527b6af4 485
1da177e4
LT		 486 return ret;
487}
488
489/*
490 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
491 *
492 * Try to open driver instance
493 *
494 */
495static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
496{
497 struct smsc_ircc_cb *self;
498 struct net_device *dev;
499 int err;
527b6af4 500
1da177e4
LT		 501 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
502
503 err = smsc_ircc_present(fir_base, sir_base);
98b77773 504 if (err)
1da177e4 505 goto err_out;
527b6af4 506
1da177e4 507 err = -ENOMEM;
a956f4ca 508 if (dev_count >= ARRAY_SIZE(dev_self)) {
1da177e4
LT		 509 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
510 goto err_out1;
511 }
512
513 /*
514 * Allocate new instance of the driver
515 */
516 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
517 if (!dev) {
518 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
519 goto err_out1;
520 }
521
522 SET_MODULE_OWNER(dev);
523
524 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
525#if SMSC_IRCC2_C_NET_TIMEOUT
526 dev->tx_timeout = smsc_ircc_timeout;
98b77773 527 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
1da177e4
LT		 528#endif
529 dev->open = smsc_ircc_net_open;
530 dev->stop = smsc_ircc_net_close;
531 dev->do_ioctl = smsc_ircc_net_ioctl;
532 dev->get_stats = smsc_ircc_net_get_stats;
527b6af4 533
da0841a0 534 self = netdev_priv(dev);
1da177e4
LT		 535 self->netdev = dev;
536
537 /* Make ifconfig display some details */
538 dev->base_addr = self->io.fir_base = fir_base;
539 dev->irq = self->io.irq = irq;
540
541 /* Need to store self somewhere */
6bb3b2cd 542 dev_self[dev_count] = self;
1da177e4
LT		 543 spin_lock_init(&self->lock);
544
527b6af4 545 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
1da177e4
LT		 546 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
547
548 self->rx_buff.head =
549 dma_alloc_coherent(NULL, self->rx_buff.truesize,
550 &self->rx_buff_dma, GFP_KERNEL);
551 if (self->rx_buff.head == NULL) {
552 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
553 driver_name);
554 goto err_out2;
555 }
556
557 self->tx_buff.head =
558 dma_alloc_coherent(NULL, self->tx_buff.truesize,
559 &self->tx_buff_dma, GFP_KERNEL);
560 if (self->tx_buff.head == NULL) {
561 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
562 driver_name);
563 goto err_out3;
564 }
565
566 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
567 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
568
569 self->rx_buff.in_frame = FALSE;
570 self->rx_buff.state = OUTSIDE_FRAME;
571 self->tx_buff.data = self->tx_buff.head;
572 self->rx_buff.data = self->rx_buff.head;
527b6af4 573
1da177e4 574 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
1da177e4 575 smsc_ircc_setup_qos(self);
1da177e4 576 smsc_ircc_init_chip(self);
527b6af4 577
98b77773
DT		 578 if (ircc_transceiver > 0 &&
579 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
1da177e4
LT		 580 self->transceiver = ircc_transceiver;
581 else
582 smsc_ircc_probe_transceiver(self);
583
584 err = register_netdev(self->netdev);
98b77773 585 if (err) {
1da177e4
LT		 586 IRDA_ERROR("%s, Network device registration failed!\n",
587 driver_name);
588 goto err_out4;
589 }
590
6bb3b2cd
DT		 591 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
592 dev_count, NULL, 0);
593 if (IS_ERR(self->pldev)) {
594 err = PTR_ERR(self->pldev);
595 goto err_out5;
596 }
3ae5eaec 597 platform_set_drvdata(self->pldev, self);
1da177e4
LT		 598
599 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
6bb3b2cd 600 dev_count++;
1da177e4
LT		 601
602 return 0;
98b77773 603
6bb3b2cd
DT		 604 err_out5:
605 unregister_netdev(self->netdev);
606
1da177e4
LT		 607 err_out4:
608 dma_free_coherent(NULL, self->tx_buff.truesize,
609 self->tx_buff.head, self->tx_buff_dma);
610 err_out3:
611 dma_free_coherent(NULL, self->rx_buff.truesize,
612 self->rx_buff.head, self->rx_buff_dma);
613 err_out2:
614 free_netdev(self->netdev);
6bb3b2cd 615 dev_self[dev_count] = NULL;
1da177e4
LT		 616 err_out1:
617 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
618 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
619 err_out:
620 return err;
621}
622
623/*
624 * Function smsc_ircc_present(fir_base, sir_base)
625 *
626 * Check the smsc-ircc chip presence
627 *
628 */
629static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
630{
631 unsigned char low, high, chip, config, dma, irq, version;
632
633 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
634 driver_name)) {
635 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
636 __FUNCTION__, fir_base);
637 goto out1;
638 }
639
640 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
641 driver_name)) {
642 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
643 __FUNCTION__, sir_base);
644 goto out2;
645 }
646
647 register_bank(fir_base, 3);
648
98b77773
DT		 649 high = inb(fir_base + IRCC_ID_HIGH);
650 low = inb(fir_base + IRCC_ID_LOW);
651 chip = inb(fir_base + IRCC_CHIP_ID);
652 version = inb(fir_base + IRCC_VERSION);
653 config = inb(fir_base + IRCC_INTERFACE);
1da177e4
LT		 654 dma = config & IRCC_INTERFACE_DMA_MASK;
655 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
656
527b6af4 657 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
98b77773 658 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
1da177e4
LT		 659 __FUNCTION__, fir_base);
660 goto out3;
661 }
662 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
663 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
664 chip & 0x0f, version, fir_base, sir_base, dma, irq);
665
666 return 0;
98b77773 667
1da177e4
LT		 668 out3:
669 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
670 out2:
671 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
672 out1:
673 return -ENODEV;
674}
675
676/*
677 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
678 *
679 * Setup I/O
680 *
681 */
527b6af4
DT		 682static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
683 unsigned int fir_base, unsigned int sir_base,
1da177e4
LT		 684 u8 dma, u8 irq)
685{
686 unsigned char config, chip_dma, chip_irq;
687
688 register_bank(fir_base, 3);
98b77773
DT		 689 config = inb(fir_base + IRCC_INTERFACE);
690 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
691 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
1da177e4
LT		 692
693 self->io.fir_base = fir_base;
694 self->io.sir_base = sir_base;
695 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
696 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
697 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
698 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
699
916f11c7 700 if (irq != IRQ_INVAL) {
1da177e4
LT		 701 if (irq != chip_irq)
702 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
703 driver_name, chip_irq, irq);
704 self->io.irq = irq;
98b77773 705 } else
1da177e4 706 self->io.irq = chip_irq;
527b6af4 707
916f11c7 708 if (dma != DMA_INVAL) {
1da177e4
LT		 709 if (dma != chip_dma)
710 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
711 driver_name, chip_dma, dma);
712 self->io.dma = dma;
98b77773 713 } else
1da177e4
LT		 714 self->io.dma = chip_dma;
715
716}
717
718/*
719 * Function smsc_ircc_setup_qos(self)
720 *
721 * Setup qos
722 *
723 */
724static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
725{
726 /* Initialize QoS for this device */
727 irda_init_max_qos_capabilies(&self->qos);
527b6af4 728
1da177e4
LT		 729 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
730 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
731
732 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
733 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
734 irda_qos_bits_to_value(&self->qos);
735}
736
737/*
738 * Function smsc_ircc_init_chip(self)
739 *
740 * Init chip
741 *
742 */
743static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
744{
e812cb52 745 int iobase = self->io.fir_base;
1da177e4
LT		 746
747 register_bank(iobase, 0);
98b77773
DT		 748 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
749 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 750
751 register_bank(iobase, 1);
e812cb52 752 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
98b77773 753 iobase + IRCC_SCE_CFGA);
1da177e4
LT		 754
755#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 756 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
757 iobase + IRCC_SCE_CFGB);
527b6af4 758#else
98b77773
DT		 759 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
760 iobase + IRCC_SCE_CFGB);
527b6af4 761#endif
98b77773
DT		 762 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
763 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
527b6af4 764
1da177e4 765 register_bank(iobase, 4);
e812cb52 766 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
527b6af4 767
1da177e4 768 register_bank(iobase, 0);
e812cb52 769 outb(0, iobase + IRCC_LCR_A);
1da177e4
LT		 770
771 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
527b6af4 772
1da177e4 773 /* Power on device */
98b77773 774 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 775}
776
777/*
778 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
779 *
780 * Process IOCTL commands for this device
781 *
782 */
783static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
784{
785 struct if_irda_req *irq = (struct if_irda_req *) rq;
786 struct smsc_ircc_cb *self;
787 unsigned long flags;
788 int ret = 0;
789
790 IRDA_ASSERT(dev != NULL, return -1;);
791
da0841a0 792 self = netdev_priv(dev);
1da177e4
LT		 793
794 IRDA_ASSERT(self != NULL, return -1;);
795
796 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
527b6af4 797
1da177e4
LT		 798 switch (cmd) {
799 case SIOCSBANDWIDTH: /* Set bandwidth */
800 if (!capable(CAP_NET_ADMIN))
801 ret = -EPERM;
802 else {
803 /* Make sure we are the only one touching
804 * self->io.speed and the hardware - Jean II */
805 spin_lock_irqsave(&self->lock, flags);
806 smsc_ircc_change_speed(self, irq->ifr_baudrate);
807 spin_unlock_irqrestore(&self->lock, flags);
808 }
809 break;
810 case SIOCSMEDIABUSY: /* Set media busy */
811 if (!capable(CAP_NET_ADMIN)) {
812 ret = -EPERM;
813 break;
814 }
815
816 irda_device_set_media_busy(self->netdev, TRUE);
817 break;
818 case SIOCGRECEIVING: /* Check if we are receiving right now */
819 irq->ifr_receiving = smsc_ircc_is_receiving(self);
820 break;
821 #if 0
822 case SIOCSDTRRTS:
823 if (!capable(CAP_NET_ADMIN)) {
824 ret = -EPERM;
825 break;
826 }
827 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
828 break;
829 #endif
830 default:
831 ret = -EOPNOTSUPP;
832 }
527b6af4 833
1da177e4
LT		 834 return ret;
835}
836
837static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
838{
da0841a0 839 struct smsc_ircc_cb *self = netdev_priv(dev);
527b6af4 840
1da177e4
LT		 841 return &self->stats;
842}
843
844#if SMSC_IRCC2_C_NET_TIMEOUT
845/*
846 * Function smsc_ircc_timeout (struct net_device *dev)
847 *
848 * The networking timeout management.
849 *
850 */
851
852static void smsc_ircc_timeout(struct net_device *dev)
853{
da0841a0 854 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 855 unsigned long flags;
856
1da177e4
LT		 857 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
858 dev->name, self->io.speed);
859 spin_lock_irqsave(&self->lock, flags);
860 smsc_ircc_sir_start(self);
861 smsc_ircc_change_speed(self, self->io.speed);
862 dev->trans_start = jiffies;
863 netif_wake_queue(dev);
864 spin_unlock_irqrestore(&self->lock, flags);
865}
866#endif
867
868/*
869 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
870 *
871 * Transmits the current frame until FIFO is full, then
872 * waits until the next transmit interrupt, and continues until the
873 * frame is transmitted.
874 */
875int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
876{
877 struct smsc_ircc_cb *self;
878 unsigned long flags;
1da177e4
LT		 879 s32 speed;
880
881 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
882
883 IRDA_ASSERT(dev != NULL, return 0;);
527b6af4 884
da0841a0 885 self = netdev_priv(dev);
1da177e4
LT		 886 IRDA_ASSERT(self != NULL, return 0;);
887
1da177e4 888 netif_stop_queue(dev);
527b6af4 889
1da177e4
LT		 890 /* Make sure test of self->io.speed & speed change are atomic */
891 spin_lock_irqsave(&self->lock, flags);
892
893 /* Check if we need to change the speed */
894 speed = irda_get_next_speed(skb);
98b77773 895 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 896 /* Check for empty frame */
897 if (!skb->len) {
898 /*
899 * We send frames one by one in SIR mode (no
900 * pipelining), so at this point, if we were sending
901 * a previous frame, we just received the interrupt
902 * telling us it is finished (UART_IIR_THRI).
903 * Therefore, waiting for the transmitter to really
904 * finish draining the fifo won't take too long.
905 * And the interrupt handler is not expected to run.
906 * - Jean II */
907 smsc_ircc_sir_wait_hw_transmitter_finish(self);
908 smsc_ircc_change_speed(self, speed);
909 spin_unlock_irqrestore(&self->lock, flags);
910 dev_kfree_skb(skb);
911 return 0;
1da177e4 912 }
98b77773 913 self->new_speed = speed;
1da177e4
LT		 914 }
915
916 /* Init tx buffer */
917 self->tx_buff.data = self->tx_buff.head;
918
919 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
527b6af4 920 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
1da177e4 921 self->tx_buff.truesize);
527b6af4 922
1da177e4
LT		 923 self->stats.tx_bytes += self->tx_buff.len;
924
925 /* Turn on transmit finished interrupt. Will fire immediately! */
80a90589 926 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
1da177e4
LT		 927
928 spin_unlock_irqrestore(&self->lock, flags);
929
930 dev_kfree_skb(skb);
527b6af4 931
1da177e4
LT		 932 return 0;
933}
934
935/*
936 * Function smsc_ircc_set_fir_speed (self, baud)
937 *
938 * Change the speed of the device
939 *
940 */
941static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
942{
943 int fir_base, ir_mode, ctrl, fast;
944
945 IRDA_ASSERT(self != NULL, return;);
946 fir_base = self->io.fir_base;
947
948 self->io.speed = speed;
949
98b77773 950 switch (speed) {
1da177e4 951 default:
527b6af4 952 case 576000:
1da177e4
LT		 953 ir_mode = IRCC_CFGA_IRDA_HDLC;
954 ctrl = IRCC_CRC;
955 fast = 0;
956 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
957 break;
958 case 1152000:
959 ir_mode = IRCC_CFGA_IRDA_HDLC;
960 ctrl = IRCC_1152 | IRCC_CRC;
961 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
962 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
963 __FUNCTION__);
964 break;
965 case 4000000:
966 ir_mode = IRCC_CFGA_IRDA_4PPM;
967 ctrl = IRCC_CRC;
968 fast = IRCC_LCR_A_FAST;
969 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
970 __FUNCTION__);
971 break;
972 }
973 #if 0
974 Now in tranceiver!
975 /* This causes an interrupt */
976 register_bank(fir_base, 0);
98b77773 977 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
1da177e4 978 #endif
527b6af4 979
1da177e4 980 register_bank(fir_base, 1);
98b77773 981 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
527b6af4 982
1da177e4 983 register_bank(fir_base, 4);
98b77773 984 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
1da177e4
LT		 985}
986
987/*
988 * Function smsc_ircc_fir_start(self)
989 *
990 * Change the speed of the device
991 *
992 */
993static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
994{
995 struct net_device *dev;
996 int fir_base;
997
998 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
999
1000 IRDA_ASSERT(self != NULL, return;);
1001 dev = self->netdev;
1002 IRDA_ASSERT(dev != NULL, return;);
1003
1004 fir_base = self->io.fir_base;
1005
1006 /* Reset everything */
1007
1008 /* Install FIR transmit handler */
527b6af4 1009 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
1da177e4
LT		 1010
1011 /* Clear FIFO */
98b77773 1012 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1da177e4
LT		 1013
1014 /* Enable interrupt */
98b77773 1015 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1da177e4
LT		 1016
1017 register_bank(fir_base, 1);
1018
527b6af4 1019 /* Select the TX/RX interface */
1da177e4 1020#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
98b77773
DT		 1021 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1022 fir_base + IRCC_SCE_CFGB);
527b6af4 1023#else
98b77773
DT		 1024 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1025 fir_base + IRCC_SCE_CFGB);
527b6af4 1026#endif
98b77773 1027 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1da177e4
LT		 1028
1029 /* Enable SCE interrupts */
98b77773 1030 outb(0, fir_base + IRCC_MASTER);
1da177e4 1031 register_bank(fir_base, 0);
98b77773
DT		 1032 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1033 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1da177e4
LT		 1034}
1035
1036/*
1037 * Function smsc_ircc_fir_stop(self, baud)
1038 *
1039 * Change the speed of the device
1040 *
1041 */
1042static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1043{
1044 int fir_base;
1045
1046 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1047
1da177e4
LT		 1048 IRDA_ASSERT(self != NULL, return;);
1049
1050 fir_base = self->io.fir_base;
1051 register_bank(fir_base, 0);
98b77773
DT		 1052 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1053 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1da177e4
LT		 1054}
1055
1056
1057/*
1058 * Function smsc_ircc_change_speed(self, baud)
1059 *
1060 * Change the speed of the device
1061 *
1062 * This function *must* be called with spinlock held, because it may
1063 * be called from the irq handler. - Jean II
1064 */
0fa2f491 1065static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1da177e4 1066{
1da177e4 1067 struct net_device *dev;
1da177e4 1068 int last_speed_was_sir;
527b6af4 1069
1da177e4
LT		 1070 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
1071
1072 IRDA_ASSERT(self != NULL, return;);
1073 dev = self->netdev;
1da177e4
LT		 1074
1075 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1076
1077 #if 0
1078 /* Temp Hack */
1079 speed= 1152000;
1080 self->io.speed = speed;
1081 last_speed_was_sir = 0;
527b6af4 1082 smsc_ircc_fir_start(self);
1da177e4 1083 #endif
527b6af4 1084
98b77773 1085 if (self->io.speed == 0)
1da177e4
LT		 1086 smsc_ircc_sir_start(self);
1087
1088 #if 0
98b77773 1089 if (!last_speed_was_sir) speed = self->io.speed;
1da177e4
LT		 1090 #endif
1091
98b77773
DT		 1092 if (self->io.speed != speed)
1093 smsc_ircc_set_transceiver_for_speed(self, speed);
1da177e4
LT		 1094
1095 self->io.speed = speed;
527b6af4 1096
98b77773
DT		 1097 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1098 if (!last_speed_was_sir) {
1da177e4
LT		 1099 smsc_ircc_fir_stop(self);
1100 smsc_ircc_sir_start(self);
1101 }
527b6af4 1102 smsc_ircc_set_sir_speed(self, speed);
98b77773
DT		 1103 } else {
1104 if (last_speed_was_sir) {
527b6af4 1105 #if SMSC_IRCC2_C_SIR_STOP
1da177e4
LT		 1106 smsc_ircc_sir_stop(self);
1107 #endif
1108 smsc_ircc_fir_start(self);
1109 }
1110 smsc_ircc_set_fir_speed(self, speed);
1111
1112 #if 0
1113 self->tx_buff.len = 10;
1114 self->tx_buff.data = self->tx_buff.head;
527b6af4 1115
80a90589 1116 smsc_ircc_dma_xmit(self, 4000);
1da177e4
LT		 1117 #endif
1118 /* Be ready for incoming frames */
80a90589 1119 smsc_ircc_dma_receive(self);
1da177e4 1120 }
527b6af4 1121
1da177e4
LT		 1122 netif_wake_queue(dev);
1123}
1124
1125/*
1126 * Function smsc_ircc_set_sir_speed (self, speed)
1127 *
1128 * Set speed of IrDA port to specified baudrate
1129 *
1130 */
0fa2f491 1131void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1da177e4 1132{
527b6af4 1133 int iobase;
1da177e4
LT		 1134 int fcr; /* FIFO control reg */
1135 int lcr; /* Line control reg */
1136 int divisor;
1137
1138 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1139
1140 IRDA_ASSERT(self != NULL, return;);
1141 iobase = self->io.sir_base;
527b6af4 1142
1da177e4
LT		 1143 /* Update accounting for new speed */
1144 self->io.speed = speed;
1145
1146 /* Turn off interrupts */
98b77773 1147 outb(0, iobase + UART_IER);
1da177e4 1148
98b77773 1149 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
527b6af4 1150
1da177e4
LT		 1151 fcr = UART_FCR_ENABLE_FIFO;
1152
527b6af4 1153 /*
1da177e4
LT		 1154 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1155 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
527b6af4 1156 * about this timeout since it will always be fast enough.
1da177e4 1157 */
98b77773
DT		 1158 fcr |= self->io.speed < 38400 ?
1159 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
527b6af4 1160
1da177e4
LT		 1161 /* IrDA ports use 8N1 */
1162 lcr = UART_LCR_WLEN8;
527b6af4 1163
98b77773
DT		 1164 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1165 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1166 outb(divisor >> 8, iobase + UART_DLM);
1167 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1168 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1da177e4
LT		 1169
1170 /* Turn on interrups */
98b77773 1171 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1da177e4
LT		 1172
1173 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1174}
1175
1176
1177/*
1178 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1179 *
1180 * Transmit the frame!
1181 *
1182 */
1183static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1184{
1185 struct smsc_ircc_cb *self;
1186 unsigned long flags;
1187 s32 speed;
1da177e4
LT		 1188 int mtt;
1189
1190 IRDA_ASSERT(dev != NULL, return 0;);
da0841a0 1191 self = netdev_priv(dev);
1da177e4
LT		 1192 IRDA_ASSERT(self != NULL, return 0;);
1193
1da177e4
LT		 1194 netif_stop_queue(dev);
1195
1196 /* Make sure test of self->io.speed & speed change are atomic */
1197 spin_lock_irqsave(&self->lock, flags);
1198
1199 /* Check if we need to change the speed after this frame */
1200 speed = irda_get_next_speed(skb);
98b77773 1201 if (speed != self->io.speed && speed != -1) {
1da177e4
LT		 1202 /* Check for empty frame */
1203 if (!skb->len) {
1204 /* Note : you should make sure that speed changes
1205 * are not going to corrupt any outgoing frame.
1206 * Look at nsc-ircc for the gory details - Jean II */
527b6af4 1207 smsc_ircc_change_speed(self, speed);
1da177e4
LT		 1208 spin_unlock_irqrestore(&self->lock, flags);
1209 dev_kfree_skb(skb);
1210 return 0;
98b77773
DT		 1211 }
1212
1213 self->new_speed = speed;
1da177e4 1214 }
527b6af4 1215
d626f62b 1216 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1da177e4
LT		 1217
1218 self->tx_buff.len = skb->len;
1219 self->tx_buff.data = self->tx_buff.head;
527b6af4
DT		 1220
1221 mtt = irda_get_mtt(skb);
1da177e4
LT		 1222 if (mtt) {
1223 int bofs;
1224
527b6af4 1225 /*
1da177e4
LT		 1226 * Compute how many BOFs (STA or PA's) we need to waste the
1227 * min turn time given the speed of the link.
1228 */
1229 bofs = mtt * (self->io.speed / 1000) / 8000;
1230 if (bofs > 4095)
1231 bofs = 4095;
1232
80a90589 1233 smsc_ircc_dma_xmit(self, bofs);
1da177e4
LT		 1234 } else {
1235 /* Transmit frame */
80a90589 1236 smsc_ircc_dma_xmit(self, 0);
1da177e4 1237 }
98b77773 1238
1da177e4
LT		 1239 spin_unlock_irqrestore(&self->lock, flags);
1240 dev_kfree_skb(skb);
1241
1242 return 0;
1243}
1244
1245/*
80a90589 1246 * Function smsc_ircc_dma_xmit (self, bofs)
1da177e4
LT		 1247 *
1248 * Transmit data using DMA
1249 *
1250 */
80a90589 1251static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1da177e4 1252{
80a90589 1253 int iobase = self->io.fir_base;
1da177e4
LT		 1254 u8 ctrl;
1255
1256 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1257#if 1
1258 /* Disable Rx */
1259 register_bank(iobase, 0);
98b77773 1260 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1261#endif
1262 register_bank(iobase, 1);
98b77773
DT		 1263 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1264 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1265
1266 self->io.direction = IO_XMIT;
1267
1268 /* Set BOF additional count for generating the min turn time */
1269 register_bank(iobase, 4);
98b77773
DT		 1270 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1271 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1272 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1da177e4
LT		 1273
1274 /* Set max Tx frame size */
98b77773
DT		 1275 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1276 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1da177e4
LT		 1277
1278 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
527b6af4 1279
1da177e4
LT		 1280 /* Enable burst mode chip Tx DMA */
1281 register_bank(iobase, 1);
98b77773
DT		 1282 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1283 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1284
1285 /* Setup DMA controller (must be done after enabling chip DMA) */
1286 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1287 DMA_TX_MODE);
1288
1289 /* Enable interrupt */
1290
1291 register_bank(iobase, 0);
98b77773
DT		 1292 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1293 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
527b6af4 1294
1da177e4 1295 /* Enable transmit */
98b77773 1296 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1da177e4
LT		 1297}
1298
1299/*
1300 * Function smsc_ircc_dma_xmit_complete (self)
1301 *
527b6af4 1302 * The transfer of a frame in finished. This function will only be called
1da177e4
LT		 1303 * by the interrupt handler
1304 *
1305 */
80a90589 1306static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1da177e4 1307{
80a90589
DT		 1308 int iobase = self->io.fir_base;
1309
1da177e4
LT		 1310 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1311#if 0
1312 /* Disable Tx */
1313 register_bank(iobase, 0);
98b77773 1314 outb(0x00, iobase + IRCC_LCR_B);
1da177e4 1315#endif
80a90589
DT		 1316 register_bank(iobase, 1);
1317 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1318 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1319
1320 /* Check for underrun! */
1321 register_bank(iobase, 0);
98b77773 1322 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1da177e4
LT		 1323 self->stats.tx_errors++;
1324 self->stats.tx_fifo_errors++;
1325
1326 /* Reset error condition */
1327 register_bank(iobase, 0);
98b77773
DT		 1328 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1329 outb(0x00, iobase + IRCC_MASTER);
1da177e4
LT		 1330 } else {
1331 self->stats.tx_packets++;
98b77773 1332 self->stats.tx_bytes += self->tx_buff.len;
1da177e4
LT		 1333 }
1334
1335 /* Check if it's time to change the speed */
1336 if (self->new_speed) {
527b6af4 1337 smsc_ircc_change_speed(self, self->new_speed);
1da177e4
LT		 1338 self->new_speed = 0;
1339 }
1340
1341 netif_wake_queue(self->netdev);
1342}
1343
1344/*
1345 * Function smsc_ircc_dma_receive(self)
1346 *
1347 * Get ready for receiving a frame. The device will initiate a DMA
1348 * if it starts to receive a frame.
1349 *
1350 */
80a90589 1351static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1da177e4 1352{
80a90589 1353 int iobase = self->io.fir_base;
1da177e4
LT		 1354#if 0
1355 /* Turn off chip DMA */
1356 register_bank(iobase, 1);
98b77773
DT		 1357 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1358 iobase + IRCC_SCE_CFGB);
1da177e4 1359#endif
527b6af4 1360
1da177e4
LT		 1361 /* Disable Tx */
1362 register_bank(iobase, 0);
98b77773 1363 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1364
1365 /* Turn off chip DMA */
1366 register_bank(iobase, 1);
98b77773
DT		 1367 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1368 iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1369
1370 self->io.direction = IO_RECV;
1371 self->rx_buff.data = self->rx_buff.head;
1372
1373 /* Set max Rx frame size */
1374 register_bank(iobase, 4);
98b77773
DT		 1375 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1376 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1da177e4
LT		 1377
1378 /* Setup DMA controller */
1379 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1380 DMA_RX_MODE);
1381
1382 /* Enable burst mode chip Rx DMA */
1383 register_bank(iobase, 1);
98b77773
DT		 1384 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1385 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1da177e4
LT		 1386
1387 /* Enable interrupt */
1388 register_bank(iobase, 0);
98b77773
DT		 1389 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1390 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1da177e4
LT		 1391
1392 /* Enable receiver */
1393 register_bank(iobase, 0);
527b6af4 1394 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
98b77773 1395 iobase + IRCC_LCR_B);
527b6af4 1396
1da177e4
LT		 1397 return 0;
1398}
1399
1400/*
80a90589 1401 * Function smsc_ircc_dma_receive_complete(self)
1da177e4
LT		 1402 *
1403 * Finished with receiving frames
1404 *
1405 */
80a90589 1406static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1da177e4
LT		 1407{
1408 struct sk_buff *skb;
1409 int len, msgcnt, lsr;
80a90589 1410 int iobase = self->io.fir_base;
527b6af4 1411
1da177e4 1412 register_bank(iobase, 0);
527b6af4 1413
1da177e4
LT		 1414 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1415#if 0
1416 /* Disable Rx */
1417 register_bank(iobase, 0);
98b77773 1418 outb(0x00, iobase + IRCC_LCR_B);
1da177e4
LT		 1419#endif
1420 register_bank(iobase, 0);
98b77773
DT		 1421 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1422 lsr= inb(iobase + IRCC_LSR);
1423 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1da177e4
LT		 1424
1425 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1426 get_dma_residue(self->io.dma));
1427
1428 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1429
98b77773
DT		 1430 /* Look for errors */
1431 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1da177e4 1432 self->stats.rx_errors++;
98b77773
DT		 1433 if (lsr & IRCC_LSR_FRAME_ERROR)
1434 self->stats.rx_frame_errors++;
1435 if (lsr & IRCC_LSR_CRC_ERROR)
1436 self->stats.rx_crc_errors++;
1437 if (lsr & IRCC_LSR_SIZE_ERROR)
1438 self->stats.rx_length_errors++;
1439 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1440 self->stats.rx_length_errors++;
1da177e4
LT		 1441 return;
1442 }
98b77773 1443
1da177e4 1444 /* Remove CRC */
98b77773 1445 len -= self->io.speed < 4000000 ? 2 : 4;
1da177e4 1446
98b77773 1447 if (len < 2 || len > 2050) {
1da177e4
LT		 1448 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1449 return;
1450 }
1451 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1452
98b77773
DT		 1453 skb = dev_alloc_skb(len + 1);
1454 if (!skb) {
1da177e4
LT		 1455 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1456 __FUNCTION__);
1457 return;
527b6af4 1458 }
1da177e4 1459 /* Make sure IP header gets aligned */
527b6af4 1460 skb_reserve(skb, 1);
1da177e4
LT		 1461
1462 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1463 self->stats.rx_packets++;
1464 self->stats.rx_bytes += len;
1465
1466 skb->dev = self->netdev;
459a98ed 1467 skb_reset_mac_header(skb);
1da177e4
LT		 1468 skb->protocol = htons(ETH_P_IRDA);
1469 netif_rx(skb);
1470}
1471
1472/*
1473 * Function smsc_ircc_sir_receive (self)
1474 *
1475 * Receive one frame from the infrared port
1476 *
1477 */
527b6af4 1478static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1da177e4
LT		 1479{
1480 int boguscount = 0;
1481 int iobase;
1482
1483 IRDA_ASSERT(self != NULL, return;);
1484
1485 iobase = self->io.sir_base;
1486
527b6af4
DT		 1487 /*
1488 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1489 * async_unwrap_char will deliver all found frames
1da177e4
LT		 1490 */
1491 do {
527b6af4 1492 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
98b77773 1493 inb(iobase + UART_RX));
1da177e4
LT		 1494
1495 /* Make sure we don't stay here to long */
1496 if (boguscount++ > 32) {
1497 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1498 break;
1499 }
98b77773 1500 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1da177e4
LT		 1501}
1502
1503
1504/*
1505 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1506 *
1507 * An interrupt from the chip has arrived. Time to do some work
1508 *
1509 */
7d12e780 1510static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id)
1da177e4
LT		 1511{
1512 struct net_device *dev = (struct net_device *) dev_id;
1513 struct smsc_ircc_cb *self;
1514 int iobase, iir, lcra, lsr;
1515 irqreturn_t ret = IRQ_NONE;
1516
1517 if (dev == NULL) {
527b6af4 1518 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1da177e4
LT		 1519 driver_name, irq);
1520 goto irq_ret;
1521 }
da0841a0
DT		 1522
1523 self = netdev_priv(dev);
1da177e4
LT		 1524 IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1525
1526 /* Serialise the interrupt handler in various CPUs, stop Tx path */
527b6af4 1527 spin_lock(&self->lock);
1da177e4
LT		 1528
1529 /* Check if we should use the SIR interrupt handler */
98b77773 1530 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1da177e4
LT		 1531 ret = smsc_ircc_interrupt_sir(dev);
1532 goto irq_ret_unlock;
1533 }
1534
1535 iobase = self->io.fir_base;
1536
1537 register_bank(iobase, 0);
98b77773 1538 iir = inb(iobase + IRCC_IIR);
527b6af4 1539 if (iir == 0)
1da177e4
LT		 1540 goto irq_ret_unlock;
1541 ret = IRQ_HANDLED;
1542
1543 /* Disable interrupts */
98b77773
DT		 1544 outb(0, iobase + IRCC_IER);
1545 lcra = inb(iobase + IRCC_LCR_A);
1546 lsr = inb(iobase + IRCC_LSR);
527b6af4 1547
1da177e4
LT		 1548 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1549
1550 if (iir & IRCC_IIR_EOM) {
1551 if (self->io.direction == IO_RECV)
80a90589 1552 smsc_ircc_dma_receive_complete(self);
1da177e4 1553 else
80a90589 1554 smsc_ircc_dma_xmit_complete(self);
527b6af4 1555
80a90589 1556 smsc_ircc_dma_receive(self);
1da177e4
LT		 1557 }
1558
1559 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1560 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1561 }
1562
1563 /* Enable interrupts again */
1564
1565 register_bank(iobase, 0);
98b77773 1566 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1da177e4
LT		 1567
1568 irq_ret_unlock:
1569 spin_unlock(&self->lock);
1570 irq_ret:
1571 return ret;
1572}
1573
1574/*
7d12e780 1575 * Function irport_interrupt_sir (irq, dev_id)
1da177e4
LT		 1576 *
1577 * Interrupt handler for SIR modes
1578 */
1579static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1580{
da0841a0 1581 struct smsc_ircc_cb *self = netdev_priv(dev);
1da177e4
LT		 1582 int boguscount = 0;
1583 int iobase;
1584 int iir, lsr;
1585
1586 /* Already locked comming here in smsc_ircc_interrupt() */
1587 /*spin_lock(&self->lock);*/
1588
1589 iobase = self->io.sir_base;
1590
98b77773 1591 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1592 if (iir == 0)
1593 return IRQ_NONE;
1594 while (iir) {
1595 /* Clear interrupt */
98b77773 1596 lsr = inb(iobase + UART_LSR);
1da177e4 1597
527b6af4 1598 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1da177e4
LT		 1599 __FUNCTION__, iir, lsr, iobase);
1600
1601 switch (iir) {
1602 case UART_IIR_RLSI:
1603 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1604 break;
1605 case UART_IIR_RDI:
1606 /* Receive interrupt */
1607 smsc_ircc_sir_receive(self);
1608 break;
1609 case UART_IIR_THRI:
1610 if (lsr & UART_LSR_THRE)
1611 /* Transmitter ready for data */
1612 smsc_ircc_sir_write_wakeup(self);
1613 break;
1614 default:
1615 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1616 __FUNCTION__, iir);
1617 break;
527b6af4
DT		 1618 }
1619
1da177e4
LT		 1620 /* Make sure we don't stay here to long */
1621 if (boguscount++ > 100)
1622 break;
1623
527b6af4 1624 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1da177e4
LT		 1625 }
1626 /*spin_unlock(&self->lock);*/
1627 return IRQ_HANDLED;
1628}
1629
1630
1631#if 0 /* unused */
1632/*
1633 * Function ircc_is_receiving (self)
1634 *
1635 * Return TRUE is we are currently receiving a frame
1636 *
1637 */
1638static int ircc_is_receiving(struct smsc_ircc_cb *self)
1639{
1640 int status = FALSE;
1641 /* int iobase; */
1642
1643 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1644
1645 IRDA_ASSERT(self != NULL, return FALSE;);
1646
1647 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1648 get_dma_residue(self->io.dma));
1649
1650 status = (self->rx_buff.state != OUTSIDE_FRAME);
527b6af4 1651
1da177e4
LT		 1652 return status;
1653}
1654#endif /* unused */
1655
e812cb52
DT		 1656static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1657{
1658 int error;
1659
1660 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1661 self->netdev->name, self->netdev);
1662 if (error)
1663 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1664 __FUNCTION__, self->io.irq, error);
1665
1666 return error;
1667}
1668
1669static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1670{
1671 unsigned long flags;
1672
1673 spin_lock_irqsave(&self->lock, flags);
1674
1675 self->io.speed = 0;
1676 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1677
1678 spin_unlock_irqrestore(&self->lock, flags);
1679}
1680
1681static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1682{
1683 int iobase = self->io.fir_base;
1684 unsigned long flags;
1685
1686 spin_lock_irqsave(&self->lock, flags);
1687
1688 register_bank(iobase, 0);
1689 outb(0, iobase + IRCC_IER);
1690 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1691 outb(0x00, iobase + IRCC_MASTER);
1692
1693 spin_unlock_irqrestore(&self->lock, flags);
1694}
1695
1da177e4
LT		 1696
1697/*
1698 * Function smsc_ircc_net_open (dev)
1699 *
1700 * Start the device
1701 *
1702 */
1703static int smsc_ircc_net_open(struct net_device *dev)
1704{
1705 struct smsc_ircc_cb *self;
1da177e4 1706 char hwname[16];
1da177e4
LT		 1707
1708 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1709
1da177e4 1710 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1711 self = netdev_priv(dev);
1da177e4 1712 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1713
e812cb52
DT		 1714 if (self->io.suspended) {
1715 IRDA_DEBUG(0, "%s(), device is suspended\n", __FUNCTION__);
1716 return -EAGAIN;
1717 }
1718
527b6af4 1719 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1da177e4
LT		 1720 (void *) dev)) {
1721 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1722 __FUNCTION__, self->io.irq);
1723 return -EAGAIN;
1724 }
1725
e812cb52 1726 smsc_ircc_start_interrupts(self);
527b6af4 1727
1da177e4
LT		 1728 /* Give self a hardware name */
1729 /* It would be cool to offer the chip revision here - Jean II */
1730 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1731
527b6af4 1732 /*
1da177e4 1733 * Open new IrLAP layer instance, now that everything should be
527b6af4 1734 * initialized properly
1da177e4
LT		 1735 */
1736 self->irlap = irlap_open(dev, &self->qos, hwname);
1737
1738 /*
1739 * Always allocate the DMA channel after the IRQ,
1740 * and clean up on failure.
1741 */
1742 if (request_dma(self->io.dma, dev->name)) {
1743 smsc_ircc_net_close(dev);
1744
1745 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1746 __FUNCTION__, self->io.dma);
1747 return -EAGAIN;
1748 }
527b6af4 1749
1da177e4
LT		 1750 netif_start_queue(dev);
1751
1752 return 0;
1753}
1754
1755/*
1756 * Function smsc_ircc_net_close (dev)
1757 *
1758 * Stop the device
1759 *
1760 */
1761static int smsc_ircc_net_close(struct net_device *dev)
1762{
1763 struct smsc_ircc_cb *self;
1da177e4
LT		 1764
1765 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
527b6af4 1766
1da177e4 1767 IRDA_ASSERT(dev != NULL, return -1;);
da0841a0 1768 self = netdev_priv(dev);
1da177e4 1769 IRDA_ASSERT(self != NULL, return 0;);
527b6af4 1770
1da177e4
LT		 1771 /* Stop device */
1772 netif_stop_queue(dev);
527b6af4 1773
1da177e4
LT		 1774 /* Stop and remove instance of IrLAP */
1775 if (self->irlap)
1776 irlap_close(self->irlap);
1777 self->irlap = NULL;
1778
e812cb52
DT		 1779 smsc_ircc_stop_interrupts(self);
1780
1781 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1782 if (!self->io.suspended)
1783 free_irq(self->io.irq, dev);
1784
1da177e4 1785 disable_dma(self->io.dma);
1da177e4
LT		 1786 free_dma(self->io.dma);
1787
1788 return 0;
1789}
1790
3ae5eaec 1791static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1792{
3ae5eaec 1793 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
6bb3b2cd 1794
9480e307 1795 if (!self->io.suspended) {
e812cb52
DT		 1796 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1797
1798 rtnl_lock();
1799 if (netif_running(self->netdev)) {
1800 netif_device_detach(self->netdev);
1801 smsc_ircc_stop_interrupts(self);
1802 free_irq(self->io.irq, self->netdev);
1803 disable_dma(self->io.dma);
1804 }
98b77773 1805 self->io.suspended = 1;
e812cb52 1806 rtnl_unlock();
98b77773 1807 }
6bb3b2cd
DT		 1808
1809 return 0;
1da177e4
LT		 1810}
1811
3ae5eaec 1812static int smsc_ircc_resume(struct platform_device *dev)
1da177e4 1813{
3ae5eaec 1814 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1da177e4 1815
9480e307 1816 if (self->io.suspended) {
e812cb52
DT		 1817 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1818
1819 rtnl_lock();
1820 smsc_ircc_init_chip(self);
1821 if (netif_running(self->netdev)) {
1822 if (smsc_ircc_request_irq(self)) {
1823 /*
1824 * Don't fail resume process, just kill this
1825 * network interface
1826 */
1827 unregister_netdevice(self->netdev);
1828 } else {
1829 enable_dma(self->io.dma);
1830 smsc_ircc_start_interrupts(self);
1831 netif_device_attach(self->netdev);
1832 }
1833 }
6bb3b2cd 1834 self->io.suspended = 0;
e812cb52 1835 rtnl_unlock();
6bb3b2cd 1836 }
1da177e4
LT		 1837 return 0;
1838}
1839
1840/*
1841 * Function smsc_ircc_close (self)
1842 *
1843 * Close driver instance
1844 *
1845 */
1846static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1847{
1da177e4
LT		 1848 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1849
1850 IRDA_ASSERT(self != NULL, return -1;);
1851
6bb3b2cd 1852 platform_device_unregister(self->pldev);
1da177e4
LT		 1853
1854 /* Remove netdevice */
1855 unregister_netdev(self->netdev);
1856
e812cb52 1857 smsc_ircc_stop_interrupts(self);
1da177e4
LT		 1858
1859 /* Release the PORTS that this driver is using */
1860 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1861 self->io.fir_base);
1862
1863 release_region(self->io.fir_base, self->io.fir_ext);
1864
527b6af4 1865 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1da177e4
LT		 1866 self->io.sir_base);
1867
1868 release_region(self->io.sir_base, self->io.sir_ext);
1869
1870 if (self->tx_buff.head)
1871 dma_free_coherent(NULL, self->tx_buff.truesize,
1872 self->tx_buff.head, self->tx_buff_dma);
527b6af4 1873
1da177e4
LT		 1874 if (self->rx_buff.head)
1875 dma_free_coherent(NULL, self->rx_buff.truesize,
1876 self->rx_buff.head, self->rx_buff_dma);
1877
1878 free_netdev(self->netdev);
1879
1880 return 0;
1881}
1882
1883static void __exit smsc_ircc_cleanup(void)
1884{
1885 int i;
1886
1887 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1888
98b77773 1889 for (i = 0; i < 2; i++) {
1da177e4
LT		 1890 if (dev_self[i])
1891 smsc_ircc_close(dev_self[i]);
1892 }
6bb3b2cd 1893
d0d4f69b
BH		 1894 if (pnp_driver_registered)
1895 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1896
3ae5eaec 1897 platform_driver_unregister(&smsc_ircc_driver);
1da177e4
LT		 1898}
1899
1900/*
1901 * Start SIR operations
1902 *
1903 * This function *must* be called with spinlock held, because it may
1904 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1905 */
1906void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1907{
1908 struct net_device *dev;
1909 int fir_base, sir_base;
1910
1911 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1912
527b6af4 1913 IRDA_ASSERT(self != NULL, return;);
98b77773 1914 dev = self->netdev;
527b6af4 1915 IRDA_ASSERT(dev != NULL, return;);
1da177e4
LT		 1916 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1917
1918 fir_base = self->io.fir_base;
1919 sir_base = self->io.sir_base;
1920
1921 /* Reset everything */
98b77773 1922 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1da177e4
LT		 1923
1924 #if SMSC_IRCC2_C_SIR_STOP
1925 /*smsc_ircc_sir_stop(self);*/
1926 #endif
1927
1928 register_bank(fir_base, 1);
98b77773 1929 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1da177e4
LT		 1930
1931 /* Initialize UART */
98b77773
DT		 1932 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1933 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
527b6af4 1934
1da177e4 1935 /* Turn on interrups */
98b77773 1936 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1da177e4
LT		 1937
1938 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1939
98b77773 1940 outb(0x00, fir_base + IRCC_MASTER);
1da177e4
LT		 1941}
1942
1943#if SMSC_IRCC2_C_SIR_STOP
1944void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1945{
1946 int iobase;
1947
1948 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1949 iobase = self->io.sir_base;
1950
1951 /* Reset UART */
98b77773 1952 outb(0, iobase + UART_MCR);
527b6af4 1953
1da177e4 1954 /* Turn off interrupts */
98b77773 1955 outb(0, iobase + UART_IER);
1da177e4
LT		 1956}
1957#endif
1958
1959/*
1960 * Function smsc_sir_write_wakeup (self)
1961 *
1962 * Called by the SIR interrupt handler when there's room for more data.
1963 * If we have more packets to send, we send them here.
1964 *
1965 */
1966static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1967{
1968 int actual = 0;
1969 int iobase;
1970 int fcr;
1971
1972 IRDA_ASSERT(self != NULL, return;);
1973
1974 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1975
1976 iobase = self->io.sir_base;
1977
1978 /* Finished with frame? */
1979 if (self->tx_buff.len > 0) {
1980 /* Write data left in transmit buffer */
527b6af4 1981 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1da177e4
LT		 1982 self->tx_buff.data, self->tx_buff.len);
1983 self->tx_buff.data += actual;
1984 self->tx_buff.len -= actual;
1985 } else {
527b6af4 1986
1da177e4 1987 /*if (self->tx_buff.len ==0) {*/
527b6af4
DT		 1988
1989 /*
1990 * Now serial buffer is almost free & we can start
1da177e4
LT		 1991 * transmission of another packet. But first we must check
1992 * if we need to change the speed of the hardware
1993 */
1994 if (self->new_speed) {
1995 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1996 __FUNCTION__, self->new_speed);
1997 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1998 smsc_ircc_change_speed(self, self->new_speed);
1999 self->new_speed = 0;
2000 } else {
2001 /* Tell network layer that we want more frames */
2002 netif_wake_queue(self->netdev);
2003 }
2004 self->stats.tx_packets++;
2005
98b77773
DT		 2006 if (self->io.speed <= 115200) {
2007 /*
2008 * Reset Rx FIFO to make sure that all reflected transmit data
2009 * is discarded. This is needed for half duplex operation
2010 */
2011 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2012 fcr |= self->io.speed < 38400 ?
2013 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1da177e4 2014
98b77773 2015 outb(fcr, iobase + UART_FCR);
1da177e4 2016
98b77773
DT		 2017 /* Turn on receive interrupts */
2018 outb(UART_IER_RDI, iobase + UART_IER);
1da177e4
LT		 2019 }
2020 }
2021}
2022
2023/*
2024 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2025 *
2026 * Fill Tx FIFO with transmit data
2027 *
2028 */
2029static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2030{
2031 int actual = 0;
527b6af4 2032
1da177e4 2033 /* Tx FIFO should be empty! */
98b77773 2034 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
1da177e4
LT		 2035 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
2036 return 0;
2037 }
527b6af4 2038
1da177e4 2039 /* Fill FIFO with current frame */
98b77773 2040 while (fifo_size-- > 0 && actual < len) {
1da177e4 2041 /* Transmit next byte */
98b77773 2042 outb(buf[actual], iobase + UART_TX);
1da177e4
LT		 2043 actual++;
2044 }
2045 return actual;
2046}
2047
2048/*
2049 * Function smsc_ircc_is_receiving (self)
2050 *
2051 * Returns true is we are currently receiving data
2052 *
2053 */
2054static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2055{
2056 return (self->rx_buff.state != OUTSIDE_FRAME);
2057}
2058
2059
2060/*
2061 * Function smsc_ircc_probe_transceiver(self)
2062 *
2063 * Tries to find the used Transceiver
2064 *
2065 */
2066static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2067{
2068 unsigned int i;
527b6af4 2069
1da177e4 2070 IRDA_ASSERT(self != NULL, return;);
527b6af4 2071
98b77773
DT		 2072 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2073 if (smsc_transceivers[i].probe(self->io.fir_base)) {
1da177e4
LT		 2074 IRDA_MESSAGE(" %s transceiver found\n",
2075 smsc_transceivers[i].name);
98b77773 2076 self->transceiver= i + 1;
1da177e4
LT		 2077 return;
2078 }
98b77773 2079
1da177e4
LT		 2080 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2081 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
527b6af4 2082
98b77773 2083 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1da177e4
LT		 2084}
2085
2086
2087/*
2088 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2089 *
2090 * Set the transceiver according to the speed
2091 *
2092 */
2093static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2094{
2095 unsigned int trx;
527b6af4 2096
1da177e4 2097 trx = self->transceiver;
98b77773
DT		 2098 if (trx > 0)
2099 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1da177e4
LT		 2100}
2101
2102/*
2103 * Function smsc_ircc_wait_hw_transmitter_finish ()
2104 *
2105 * Wait for the real end of HW transmission
2106 *
2107 * The UART is a strict FIFO, and we get called only when we have finished
2108 * pushing data to the FIFO, so the maximum amount of time we must wait
2109 * is only for the FIFO to drain out.
2110 *
2111 * We use a simple calibrated loop. We may need to adjust the loop
2112 * delay (udelay) to balance I/O traffic and latency. And we also need to
2113 * adjust the maximum timeout.
2114 * It would probably be better to wait for the proper interrupt,
2115 * but it doesn't seem to be available.
2116 *
2117 * We can't use jiffies or kernel timers because :
2118 * 1) We are called from the interrupt handler, which disable softirqs,
2119 * so jiffies won't be increased
2120 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2121 * want to wait that long to detect stuck hardware.
2122 * Jean II
2123 */
2124
2125static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2126{
98b77773 2127 int iobase = self->io.sir_base;
1da177e4 2128 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
527b6af4 2129
1da177e4 2130 /* Calibrated busy loop */
98b77773 2131 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1da177e4
LT		 2132 udelay(1);
2133
98b77773 2134 if (count == 0)
1da177e4
LT		 2135 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
2136}
2137
2138
2139/* PROBING
2140 *
d94c77b9
DB		 2141 * REVISIT we can be told about the device by PNP, and should use that info
2142 * instead of probing hardware and creating a platform_device ...
1da177e4
LT		 2143 */
2144
2145static int __init smsc_ircc_look_for_chips(void)
2146{
b6158d23 2147 struct smsc_chip_address *address;
98b77773 2148 char *type;
1da177e4 2149 unsigned int cfg_base, found;
527b6af4 2150
1da177e4
LT		 2151 found = 0;
2152 address = possible_addresses;
527b6af4 2153
98b77773 2154 while (address->cfg_base) {
1da177e4 2155 cfg_base = address->cfg_base;
527b6af4 2156
1da177e4 2157 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
527b6af4 2158
98b77773 2159 if (address->type & SMSCSIO_TYPE_FDC) {
1da177e4 2160 type = "FDC";
98b77773
DT		 2161 if (address->type & SMSCSIO_TYPE_FLAT)
2162 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2163 found++;
2164
2165 if (address->type & SMSCSIO_TYPE_PAGED)
2166 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2167 found++;
1da177e4 2168 }
98b77773 2169 if (address->type & SMSCSIO_TYPE_LPC) {
1da177e4 2170 type = "LPC";
98b77773
DT		 2171 if (address->type & SMSCSIO_TYPE_FLAT)
2172 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2173 found++;
2174
2175 if (address->type & SMSCSIO_TYPE_PAGED)
2176 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2177 found++;
1da177e4
LT		 2178 }
2179 address++;
2180 }
2181 return found;
527b6af4 2182}
1da177e4
LT		 2183
2184/*
2185 * Function smsc_superio_flat (chip, base, type)
2186 *
2187 * Try to get configuration of a smc SuperIO chip with flat register model
2188 *
2189 */
b6158d23 2190static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
1da177e4
LT		 2191{
2192 unsigned short firbase, sirbase;
2193 u8 mode, dma, irq;
2194 int ret = -ENODEV;
2195
2196 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2197
98b77773 2198 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
1da177e4
LT		 2199 return ret;
2200
2201 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
98b77773 2202 mode = inb(cfgbase + 1);
527b6af4 2203
1da177e4 2204 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
527b6af4 2205
98b77773 2206 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
1da177e4
LT		 2207 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2208
2209 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
98b77773 2210 sirbase = inb(cfgbase + 1) << 2;
1da177e4 2211
527b6af4 2212 /* FIR iobase */
1da177e4 2213 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
98b77773 2214 firbase = inb(cfgbase + 1) << 3;
1da177e4
LT		 2215
2216 /* DMA */
2217 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
98b77773 2218 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
527b6af4 2219
1da177e4
LT		 2220 /* IRQ */
2221 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
98b77773 2222 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
1da177e4
LT		 2223
2224 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2225
98b77773
DT		 2226 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2227 ret = 0;
527b6af4 2228
1da177e4
LT		 2229 /* Exit configuration */
2230 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2231
2232 return ret;
2233}
2234
2235/*
2236 * Function smsc_superio_paged (chip, base, type)
2237 *
2238 * Try to get configuration of a smc SuperIO chip with paged register model
2239 *
2240 */
b6158d23 2241static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
1da177e4
LT		 2242{
2243 unsigned short fir_io, sir_io;
2244 int ret = -ENODEV;
527b6af4 2245
1da177e4
LT		 2246 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2247
98b77773 2248 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
1da177e4 2249 return ret;
527b6af4 2250
1da177e4
LT		 2251 /* Select logical device (UART2) */
2252 outb(0x07, cfg_base);
2253 outb(0x05, cfg_base + 1);
527b6af4 2254
1da177e4
LT		 2255 /* SIR iobase */
2256 outb(0x60, cfg_base);
98b77773 2257 sir_io = inb(cfg_base + 1) << 8;
1da177e4
LT		 2258 outb(0x61, cfg_base);
2259 sir_io |= inb(cfg_base + 1);
527b6af4 2260
1da177e4
LT		 2261 /* Read FIR base */
2262 outb(0x62, cfg_base);
2263 fir_io = inb(cfg_base + 1) << 8;
2264 outb(0x63, cfg_base);
2265 fir_io |= inb(cfg_base + 1);
2266 outb(0x2b, cfg_base); /* ??? */
2267
98b77773
DT		 2268 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2269 ret = 0;
527b6af4 2270
1da177e4
LT		 2271 /* Exit configuration */
2272 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2273
2274 return ret;
2275}
2276
2277
98b77773 2278static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
1da177e4
LT		 2279{
2280 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2281
2282 outb(reg, cfg_base);
98b77773 2283 return inb(cfg_base) != reg ? -1 : 0;
1da177e4
LT		 2284}
2285
b6158d23 2286static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
1da177e4 2287{
98b77773 2288 u8 devid, xdevid, rev;
1da177e4
LT		 2289
2290 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2291
2292 /* Leave configuration */
2293
2294 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2295
2296 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2297 return NULL;
2298
2299 outb(reg, cfg_base);
2300
98b77773 2301 xdevid = inb(cfg_base + 1);
1da177e4
LT		 2302
2303 /* Enter configuration */
2304
2305 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2306
2307 #if 0
2308 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2309 return NULL;
2310 #endif
527b6af4 2311
1da177e4
LT		 2312 /* probe device ID */
2313
98b77773 2314 if (smsc_access(cfg_base, reg))
1da177e4
LT		 2315 return NULL;
2316
98b77773 2317 devid = inb(cfg_base + 1);
527b6af4 2318
98b77773 2319 if (devid == 0 || devid == 0xff) /* typical values for unused port */
1da177e4
LT		 2320 return NULL;
2321
2322 /* probe revision ID */
2323
98b77773 2324 if (smsc_access(cfg_base, reg + 1))
1da177e4
LT		 2325 return NULL;
2326
98b77773 2327 rev = inb(cfg_base + 1);
1da177e4 2328
98b77773 2329 if (rev >= 128) /* i think this will make no sense */
1da177e4
LT		 2330 return NULL;
2331
98b77773 2332 if (devid == xdevid) /* protection against false positives */
1da177e4
LT		 2333 return NULL;
2334
2335 /* Check for expected device ID; are there others? */
2336
98b77773 2337 while (chip->devid != devid) {
1da177e4
LT		 2338
2339 chip++;
2340
98b77773 2341 if (chip->name == NULL)
1da177e4
LT		 2342 return NULL;
2343 }
2344
98b77773
DT		 2345 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2346 devid, rev, cfg_base, type, chip->name);
1da177e4 2347
98b77773 2348 if (chip->rev > rev) {
527b6af4 2349 IRDA_MESSAGE("Revision higher than expected\n");
1da177e4
LT		 2350 return NULL;
2351 }
527b6af4 2352
98b77773 2353 if (chip->flags & NoIRDA)
1da177e4
LT		 2354 IRDA_MESSAGE("chipset does not support IRDA\n");
2355
2356 return chip;
2357}
2358
2359static int __init smsc_superio_fdc(unsigned short cfg_base)
2360{
2361 int ret = -1;
2362
2363 if (!request_region(cfg_base, 2, driver_name)) {
2364 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2365 __FUNCTION__, cfg_base);
2366 } else {
98b77773
DT		 2367 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2368 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
1da177e4
LT		 2369 ret = 0;
2370
2371 release_region(cfg_base, 2);
2372 }
2373
2374 return ret;
2375}
2376
2377static int __init smsc_superio_lpc(unsigned short cfg_base)
2378{
2379 int ret = -1;
2380
2381 if (!request_region(cfg_base, 2, driver_name)) {
2382 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2383 __FUNCTION__, cfg_base);
2384 } else {
98b77773
DT		 2385 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2386 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
1da177e4 2387 ret = 0;
98b77773 2388
1da177e4
LT		 2389 release_region(cfg_base, 2);
2390 }
2391 return ret;
2392}
2393
c1e14a6e
LW		 2394/*
2395 * Look for some specific subsystem setups that need
2396 * pre-configuration not properly done by the BIOS (especially laptops)
2397 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2398 * and tosh2450-smcinit.c. The table lists the device entries
08d09997
LW		 2399 * for ISA bridges with an LPC (Low Pin Count) controller which
2400 * handles the communication with the SMSC device. After the LPC
2401 * controller is initialized through PCI, the SMSC device is initialized
2402 * through a dedicated port in the ISA port-mapped I/O area, this latter
2403 * area is used to configure the SMSC device with default
2404 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2405 * used different sets of parameters and different control port
2406 * addresses making a subsystem device table necessary.
c1e14a6e
LW		 2407 */
2408#ifdef CONFIG_PCI
2409#define PCIID_VENDOR_INTEL 0x8086
2410#define PCIID_VENDOR_ALI 0x10b9
c5d965ca 2411static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
895de090
LWLE		 2412 /*
2413 * Subsystems needing entries:
2414 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2415 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2416 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2417 */
2418 {
2419 /* Guessed entry */
2420 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2421 .device = 0x24cc,
2422 .subvendor = 0x103c,
2423 .subdevice = 0x08bc,
2424 .sir_io = 0x02f8,
2425 .fir_io = 0x0130,
2426 .fir_irq = 0x05,
2427 .fir_dma = 0x03,
2428 .cfg_base = 0x004e,
2429 .preconfigure = preconfigure_through_82801,
2430 .name = "HP nx5000 family",
2431 },
c1e14a6e
LW		 2432 {
2433 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2434 .device = 0x24cc,
2435 .subvendor = 0x103c,
2436 .subdevice = 0x088c,
08d09997
LW		 2437 /* Quite certain these are the same for nc8000 as for nc6000 */
2438 .sir_io = 0x02f8,
c1e14a6e 2439 .fir_io = 0x0130,
08d09997 2440 .fir_irq = 0x05,
c1e14a6e
LW		 2441 .fir_dma = 0x03,
2442 .cfg_base = 0x004e,
2443 .preconfigure = preconfigure_through_82801,
895de090 2444 .name = "HP nc8000 family",
c1e14a6e
LW		 2445 },
2446 {
2447 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2448 .device = 0x24cc,
2449 .subvendor = 0x103c,
2450 .subdevice = 0x0890,
2451 .sir_io = 0x02f8,
2452 .fir_io = 0x0130,
08d09997 2453 .fir_irq = 0x05,
c1e14a6e
LW		 2454 .fir_dma = 0x03,
2455 .cfg_base = 0x004e,
2456 .preconfigure = preconfigure_through_82801,
895de090
LWLE		 2457 .name = "HP nc6000 family",
2458 },
2459 {
2460 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2461 .device = 0x24cc,
2462 .subvendor = 0x0e11,
2463 .subdevice = 0x0860,
2464 /* I assume these are the same for x1000 as for the others */
2465 .sir_io = 0x02e8,
2466 .fir_io = 0x02f8,
2467 .fir_irq = 0x07,
2468 .fir_dma = 0x03,
2469 .cfg_base = 0x002e,
2470 .preconfigure = preconfigure_through_82801,
2471 .name = "Compaq x1000 family",
c1e14a6e
LW		 2472 },
2473 {
08d09997
LW		 2474 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2475 .vendor = PCIID_VENDOR_INTEL,
c1e14a6e
LW		 2476 .device = 0x24c0,
2477 .subvendor = 0x1179,
08d09997 2478 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2479 .sir_io = 0x03f8,
2480 .fir_io = 0x0130,
2481 .fir_irq = 0x07,
2482 .fir_dma = 0x01,
2483 .cfg_base = 0x002e,
2484 .preconfigure = preconfigure_through_82801,
08d09997 2485 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
c1e14a6e
LW		 2486 },
2487 {
2488 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
08d09997 2489 .device = 0x248c,
c1e14a6e 2490 .subvendor = 0x1179,
08d09997 2491 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2492 .sir_io = 0x03f8,
2493 .fir_io = 0x0130,
2494 .fir_irq = 0x03,
2495 .fir_dma = 0x03,
2496 .cfg_base = 0x002e,
2497 .preconfigure = preconfigure_through_82801,
08d09997 2498 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
c1e14a6e
LW		 2499 },
2500 {
08d09997
LW		 2501 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2502 .vendor = PCIID_VENDOR_INTEL,
2503 .device = 0x24cc,
2504 .subvendor = 0x1179,
2505 .subdevice = 0xffff, /* 0xffff is "any" */
2506 .sir_io = 0x03f8,
2507 .fir_io = 0x0130,
2508 .fir_irq = 0x03,
2509 .fir_dma = 0x03,
2510 .cfg_base = 0x002e,
2511 .preconfigure = preconfigure_through_82801,
2512 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2513 },
2514 {
2515 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2516 .vendor = PCIID_VENDOR_ALI,
c1e14a6e
LW		 2517 .device = 0x1533,
2518 .subvendor = 0x1179,
08d09997 2519 .subdevice = 0xffff, /* 0xffff is "any" */
c1e14a6e
LW		 2520 .sir_io = 0x02e8,
2521 .fir_io = 0x02f8,
2522 .fir_irq = 0x07,
2523 .fir_dma = 0x03,
2524 .cfg_base = 0x002e,
2525 .preconfigure = preconfigure_through_ali,
08d09997 2526 .name = "Toshiba laptop with ALi ISA bridge",
c1e14a6e
LW		 2527 },
2528 { } // Terminator
2529};
2530
2531
2532/*
08d09997
LW		 2533 * This sets up the basic SMSC parameters
2534 * (FIR port, SIR port, FIR DMA, FIR IRQ)
c1e14a6e
LW		 2535 * through the chip configuration port.
2536 */
08d09997
LW		 2537static int __init preconfigure_smsc_chip(struct
2538 smsc_ircc_subsystem_configuration
2539 *conf)
c1e14a6e
LW		 2540{
2541 unsigned short iobase = conf->cfg_base;
2542 unsigned char tmpbyte;
2543
2544 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2545 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2546 tmpbyte = inb(iobase +1); // Read device ID
08d09997
LW		 2547 IRDA_DEBUG(0,
2548 "Detected Chip id: 0x%02x, setting up registers...\n",
2549 tmpbyte);
c1e14a6e
LW		 2550
2551 /* Disable UART1 and set up SIR I/O port */
2552 outb(0x24, iobase); // select CR24 - UART1 base addr
2553 outb(0x00, iobase + 1); // disable UART1
2554 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2555 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2556 tmpbyte = inb(iobase + 1);
2557 if (tmpbyte != (conf->sir_io >> 2) ) {
2558 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
08d09997 2559 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
c1e14a6e
LW		 2560 return -ENXIO;
2561 }
2562
2563 /* Set up FIR IRQ channel for UART2 */
2564 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2565 tmpbyte = inb(iobase + 1);
2566 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2567 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2568 outb(tmpbyte, iobase + 1);
2569 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2570 if (tmpbyte != conf->fir_irq) {
2571 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2572 return -ENXIO;
2573 }
2574
2575 /* Set up FIR I/O port */
2576 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2577 outb((conf->fir_io >> 3), iobase + 1);
2578 tmpbyte = inb(iobase + 1);
2579 if (tmpbyte != (conf->fir_io >> 3) ) {
2580 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2581 return -ENXIO;
2582 }
2583
2584 /* Set up FIR DMA channel */
2585 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2586 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2587 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2588 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2589 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2590 return -ENXIO;
2591 }
2592
2593 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2594 tmpbyte = inb(iobase + 1);
08d09997
LW		 2595 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2596 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
c1e14a6e
LW		 2597 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2598
2599 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2600 tmpbyte = inb(iobase + 1);
2601 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2602
2603 /* This one was not part of tosh1800 */
2604 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2605 tmpbyte = inb(iobase + 1);
2606 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2607
2608 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2609 tmpbyte = inb(iobase + 1);
2610 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2611
2612 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2613 tmpbyte = inb(iobase + 1);
2614 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2615
2616 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2617
2618 return 0;
2619}
2620
08d09997 2621/* 82801CAM generic registers */
c1e14a6e
LW		 2622#define VID 0x00
2623#define DID 0x02
08d09997
LW		 2624#define PIRQ_A_D_ROUT 0x60
2625#define SIRQ_CNTL 0x64
2626#define PIRQ_E_H_ROUT 0x68
c1e14a6e 2627#define PCI_DMA_C 0x90
08d09997 2628/* LPC-specific registers */
c1e14a6e 2629#define COM_DEC 0xe0
08d09997 2630#define GEN1_DEC 0xe4
c1e14a6e
LW		 2631#define LPC_EN 0xe6
2632#define GEN2_DEC 0xec
2633/*
08d09997
LW		 2634 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2635 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2636 * They all work the same way!
c1e14a6e
LW		 2637 */
2638static int __init preconfigure_through_82801(struct pci_dev *dev,
08d09997
LW		 2639 struct
2640 smsc_ircc_subsystem_configuration
2641 *conf)
c1e14a6e
LW		 2642{
2643 unsigned short tmpword;
08d09997 2644 unsigned char tmpbyte;
c1e14a6e 2645
08d09997
LW		 2646 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2647 /*
2648 * Select the range for the COMA COM port (SIR)
2649 * Register COM_DEC:
2650 * Bit 7: reserved
2651 * Bit 6-4, COMB decode range
2652 * Bit 3: reserved
2653 * Bit 2-0, COMA decode range
2654 *
2655 * Decode ranges:
2656 * 000 = 0x3f8-0x3ff (COM1)
2657 * 001 = 0x2f8-0x2ff (COM2)
2658 * 010 = 0x220-0x227
2659 * 011 = 0x228-0x22f
2660 * 100 = 0x238-0x23f
2661 * 101 = 0x2e8-0x2ef (COM4)
2662 * 110 = 0x338-0x33f
2663 * 111 = 0x3e8-0x3ef (COM3)
2664 */
2665 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2666 tmpbyte &= 0xf8; /* mask COMA bits */
2667 switch(conf->sir_io) {
2668 case 0x3f8:
2669 tmpbyte |= 0x00;
2670 break;
2671 case 0x2f8:
2672 tmpbyte |= 0x01;
2673 break;
2674 case 0x220:
2675 tmpbyte |= 0x02;
2676 break;
2677 case 0x228:
2678 tmpbyte |= 0x03;
2679 break;
2680 case 0x238:
2681 tmpbyte |= 0x04;
2682 break;
2683 case 0x2e8:
2684 tmpbyte |= 0x05;
2685 break;
2686 case 0x338:
2687 tmpbyte |= 0x06;
2688 break;
2689 case 0x3e8:
2690 tmpbyte |= 0x07;
2691 break;
2692 default:
2693 tmpbyte |= 0x01; /* COM2 default */
2694 }
2695 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2696 pci_write_config_byte(dev, COM_DEC, tmpbyte);
c1e14a6e 2697
08d09997
LW		 2698 /* Enable Low Pin Count interface */
2699 pci_read_config_word(dev, LPC_EN, &tmpword);
2700 /* These seem to be set up at all times,
2701 * just make sure it is properly set.
2702 */
2703 switch(conf->cfg_base) {
2704 case 0x04e:
2705 tmpword |= 0x2000;
2706 break;
2707 case 0x02e:
2708 tmpword |= 0x1000;
2709 break;
2710 case 0x062:
2711 tmpword |= 0x0800;
2712 break;
2713 case 0x060:
2714 tmpword |= 0x0400;
2715 break;
2716 default:
2717 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2718 conf->cfg_base);
2719 break;
2720 }
2721 tmpword &= 0xfffd; /* disable LPC COMB */
2722 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2723 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
c1e14a6e
LW		 2724 pci_write_config_word(dev, LPC_EN, tmpword);
2725
08d09997
LW		 2726 /*
2727 * Configure LPC DMA channel
2728 * PCI_DMA_C bits:
2729 * Bit 15-14: DMA channel 7 select
2730 * Bit 13-12: DMA channel 6 select
2731 * Bit 11-10: DMA channel 5 select
2732 * Bit 9-8: Reserved
2733 * Bit 7-6: DMA channel 3 select
2734 * Bit 5-4: DMA channel 2 select
2735 * Bit 3-2: DMA channel 1 select
2736 * Bit 1-0: DMA channel 0 select
2737 * 00 = Reserved value
2738 * 01 = PC/PCI DMA
2739 * 10 = Reserved value
2740 * 11 = LPC I/F DMA
2741 */
2742 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2743 switch(conf->fir_dma) {
2744 case 0x07:
2745 tmpword |= 0xc000;
2746 break;
2747 case 0x06:
2748 tmpword |= 0x3000;
2749 break;
2750 case 0x05:
2751 tmpword |= 0x0c00;
2752 break;
2753 case 0x03:
2754 tmpword |= 0x00c0;
2755 break;
2756 case 0x02:
2757 tmpword |= 0x0030;
2758 break;
2759 case 0x01:
2760 tmpword |= 0x000c;
2761 break;
2762 case 0x00:
2763 tmpword |= 0x0003;
2764 break;
2765 default:
2766 break; /* do not change settings */
2767 }
2768 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2769 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2770
2771 /*
2772 * GEN2_DEC bits:
2773 * Bit 15-4: Generic I/O range
2774 * Bit 3-1: reserved (read as 0)
2775 * Bit 0: enable GEN2 range on LPC I/F
2776 */
2777 tmpword = conf->fir_io & 0xfff8;
2778 tmpword |= 0x0001;
2779 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2780 pci_write_config_word(dev, GEN2_DEC, tmpword);
c1e14a6e
LW		 2781
2782 /* Pre-configure chip */
08d09997
LW		 2783 return preconfigure_smsc_chip(conf);
2784}
c1e14a6e 2785
08d09997
LW		 2786/*
2787 * Pre-configure a certain port on the ALi 1533 bridge.
2788 * This is based on reverse-engineering since ALi does not
2789 * provide any data sheet for the 1533 chip.
2790 */
2791static void __init preconfigure_ali_port(struct pci_dev *dev,
2792 unsigned short port)
2793{
2794 unsigned char reg;
2795 /* These bits obviously control the different ports */
2796 unsigned char mask;
2797 unsigned char tmpbyte;
2798
2799 switch(port) {
2800 case 0x0130:
2801 case 0x0178:
2802 reg = 0xb0;
2803 mask = 0x80;
2804 break;
2805 case 0x03f8:
2806 reg = 0xb4;
2807 mask = 0x80;
2808 break;
2809 case 0x02f8:
2810 reg = 0xb4;
2811 mask = 0x30;
2812 break;
2813 case 0x02e8:
2814 reg = 0xb4;
2815 mask = 0x08;
2816 break;
2817 default:
2818 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2819 return;
2820 }
2821
2822 pci_read_config_byte(dev, reg, &tmpbyte);
2823 /* Turn on the right bits */
2824 tmpbyte |= mask;
2825 pci_write_config_byte(dev, reg, tmpbyte);
2826 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2827 return;
c1e14a6e
LW		 2828}
2829
2830static int __init preconfigure_through_ali(struct pci_dev *dev,
08d09997
LW		 2831 struct
2832 smsc_ircc_subsystem_configuration
2833 *conf)
c1e14a6e 2834{
08d09997
LW		 2835 /* Configure the two ports on the ALi 1533 */
2836 preconfigure_ali_port(dev, conf->sir_io);
2837 preconfigure_ali_port(dev, conf->fir_io);
2838
2839 /* Pre-configure chip */
2840 return preconfigure_smsc_chip(conf);
c1e14a6e
LW		 2841}
2842
2843static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2844 unsigned short ircc_fir,
2845 unsigned short ircc_sir,
2846 unsigned char ircc_dma,
2847 unsigned char ircc_irq)
2848{
2849 struct pci_dev *dev = NULL;
2850 unsigned short ss_vendor = 0x0000;
2851 unsigned short ss_device = 0x0000;
2852 int ret = 0;
2853
2854 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2855
2856 while (dev != NULL) {
2857 struct smsc_ircc_subsystem_configuration *conf;
2858
2859 /*
08d09997
LW		 2860 * Cache the subsystem vendor/device:
2861 * some manufacturers fail to set this for all components,
2862 * so we save it in case there is just 0x0000 0x0000 on the
2863 * device we want to check.
c1e14a6e
LW		 2864 */
2865 if (dev->subsystem_vendor != 0x0000U) {
2866 ss_vendor = dev->subsystem_vendor;
2867 ss_device = dev->subsystem_device;
2868 }
2869 conf = subsystem_configurations;
2870 for( ; conf->subvendor; conf++) {
2871 if(conf->vendor == dev->vendor &&
2872 conf->device == dev->device &&
08d09997
LW		 2873 conf->subvendor == ss_vendor &&
2874 /* Sometimes these are cached values */
2875 (conf->subdevice == ss_device ||
2876 conf->subdevice == 0xffff)) {
2877 struct smsc_ircc_subsystem_configuration
2878 tmpconf;
c1e14a6e 2879
08d09997
LW		 2880 memcpy(&tmpconf, conf,
2881 sizeof(struct smsc_ircc_subsystem_configuration));
c1e14a6e 2882
08d09997
LW		 2883 /*
2884 * Override the default values with anything
2885 * passed in as parameter
2886 */
c1e14a6e
LW		 2887 if (ircc_cfg != 0)
2888 tmpconf.cfg_base = ircc_cfg;
2889 if (ircc_fir != 0)
2890 tmpconf.fir_io = ircc_fir;
2891 if (ircc_sir != 0)
2892 tmpconf.sir_io = ircc_sir;
916f11c7 2893 if (ircc_dma != DMA_INVAL)
c1e14a6e 2894 tmpconf.fir_dma = ircc_dma;
916f11c7 2895 if (ircc_irq != IRQ_INVAL)
c1e14a6e
LW		 2896 tmpconf.fir_irq = ircc_irq;
2897
2898 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2899 if (conf->preconfigure)
2900 ret = conf->preconfigure(dev, &tmpconf);
2901 else
2902 ret = -ENODEV;
2903 }
2904 }
2905 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2906 }
2907
2908 return ret;
2909}
2910#endif // CONFIG_PCI
2911
1da177e4
LT		 2912/************************************************
2913 *
2914 * Transceivers specific functions
2915 *
2916 ************************************************/
2917
2918
2919/*
2920 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2921 *
2922 * Program transceiver through smsc-ircc ATC circuitry
2923 *
2924 */
2925
2926static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2927{
2928 unsigned long jiffies_now, jiffies_timeout;
98b77773 2929 u8 val;
527b6af4 2930
98b77773
DT		 2931 jiffies_now = jiffies;
2932 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
527b6af4 2933
1da177e4
LT		 2934 /* ATC */
2935 register_bank(fir_base, 4);
98b77773
DT		 2936 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2937 fir_base + IRCC_ATC);
2938
2939 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2940 !time_after(jiffies, jiffies_timeout))
2941 /* empty */;
2942
2943 if (val)
1da177e4 2944 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
98b77773 2945 inb(fir_base + IRCC_ATC));
1da177e4
LT		 2946}
2947
2948/*
2949 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2950 *
2951 * Probe transceiver smsc-ircc ATC circuitry
2952 *
2953 */
2954
2955static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2956{
2957 return 0;
2958}
2959
2960/*
2961 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2962 *
527b6af4 2963 * Set transceiver
1da177e4
LT		 2964 *
2965 */
2966
2967static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2968{
98b77773 2969 u8 fast_mode;
527b6af4 2970
98b77773
DT		 2971 switch (speed) {
2972 default:
2973 case 576000 :
527b6af4 2974 fast_mode = 0;
1da177e4 2975 break;
98b77773
DT		 2976 case 1152000 :
2977 case 4000000 :
1da177e4
LT		 2978 fast_mode = IRCC_LCR_A_FAST;
2979 break;
1da177e4
LT		 2980 }
2981 register_bank(fir_base, 0);
98b77773 2982 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 2983}
2984
2985/*
2986 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2987 *
527b6af4 2988 * Probe transceiver
1da177e4
LT		 2989 *
2990 */
2991
2992static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2993{
2994 return 0;
2995}
2996
2997/*
2998 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2999 *
527b6af4 3000 * Set transceiver
1da177e4
LT		 3001 *
3002 */
3003
3004static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
3005{
98b77773 3006 u8 fast_mode;
527b6af4 3007
98b77773
DT		 3008 switch (speed) {
3009 default:
3010 case 576000 :
527b6af4 3011 fast_mode = 0;
1da177e4 3012 break;
98b77773
DT		 3013 case 1152000 :
3014 case 4000000 :
1da177e4
LT		 3015 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3016 break;
527b6af4 3017
1da177e4
LT		 3018 }
3019 /* This causes an interrupt */
3020 register_bank(fir_base, 0);
98b77773 3021 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
1da177e4
LT		 3022}
3023
3024/*
3025 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3026 *
527b6af4 3027 * Probe transceiver
1da177e4
LT		 3028 *
3029 */
3030
3031static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3032{
3033 return 0;
3034}
3035
3036
3037module_init(smsc_ircc_init);
3038module_exit(smsc_ircc_cleanup);
Linux kernel - Deliverables
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