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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
8c47eaa7 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #ifndef _IXGBE_H_ | |
29 | #define _IXGBE_H_ | |
30 | ||
f62bbb5e | 31 | #include <linux/bitops.h> |
9a799d71 AK |
32 | #include <linux/types.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/netdevice.h> | |
b25ebfd2 | 35 | #include <linux/cpumask.h> |
6fabd715 | 36 | #include <linux/aer.h> |
f62bbb5e | 37 | #include <linux/if_vlan.h> |
9a799d71 AK |
38 | |
39 | #include "ixgbe_type.h" | |
40 | #include "ixgbe_common.h" | |
2f90b865 | 41 | #include "ixgbe_dcb.h" |
eacd73f7 YZ |
42 | #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) |
43 | #define IXGBE_FCOE | |
44 | #include "ixgbe_fcoe.h" | |
45 | #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ | |
5dd2d332 | 46 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
47 | #include <linux/dca.h> |
48 | #endif | |
9a799d71 | 49 | |
849c4542 ET |
50 | /* common prefix used by pr_<> macros */ |
51 | #undef pr_fmt | |
52 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9a799d71 AK |
53 | |
54 | /* TX/RX descriptor defines */ | |
6bacb300 | 55 | #define IXGBE_DEFAULT_TXD 512 |
9a799d71 AK |
56 | #define IXGBE_MAX_TXD 4096 |
57 | #define IXGBE_MIN_TXD 64 | |
58 | ||
6bacb300 | 59 | #define IXGBE_DEFAULT_RXD 512 |
9a799d71 AK |
60 | #define IXGBE_MAX_RXD 4096 |
61 | #define IXGBE_MIN_RXD 64 | |
62 | ||
9a799d71 | 63 | /* flow control */ |
2b9ade93 | 64 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 | 65 | #define IXGBE_MAX_FCRTL 0x7FF80 |
2b9ade93 | 66 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 67 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 68 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
69 | #define IXGBE_MIN_FCPAUSE 0 |
70 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
71 | ||
72 | /* Supported Rx Buffer Sizes */ | |
13958070 | 73 | #define IXGBE_RXBUFFER_512 512 /* Used for packet split */ |
9a799d71 | 74 | #define IXGBE_RXBUFFER_2048 2048 |
e76678dd AD |
75 | #define IXGBE_RXBUFFER_4096 4096 |
76 | #define IXGBE_RXBUFFER_8192 8192 | |
32344a39 | 77 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ |
9a799d71 | 78 | |
13958070 AD |
79 | /* |
80 | * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we | |
81 | * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, | |
82 | * this adds up to 512 bytes of extra data meaning the smallest allocation | |
83 | * we could have is 1K. | |
84 | * i.e. RXBUFFER_512 --> size-1024 slab | |
85 | */ | |
86 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512 | |
9a799d71 AK |
87 | |
88 | #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) | |
89 | ||
9a799d71 AK |
90 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
91 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
92 | ||
93 | #define IXGBE_TX_FLAGS_CSUM (u32)(1) | |
94 | #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1) | |
95 | #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2) | |
96 | #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3) | |
eacd73f7 YZ |
97 | #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4) |
98 | #define IXGBE_TX_FLAGS_FSO (u32)(1 << 5) | |
9a799d71 | 99 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
2f90b865 | 100 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 |
9a799d71 AK |
101 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
102 | ||
0a924578 PWJ |
103 | #define IXGBE_MAX_RSC_INT_RATE 162760 |
104 | ||
7f870475 GR |
105 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
106 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
107 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
108 | #define MAX_EMULATION_MAC_ADDRS 16 | |
109 | #define VMDQ_P(p) ((p) + adapter->num_vfs) | |
110 | ||
111 | struct vf_data_storage { | |
112 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
113 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
114 | u16 num_vf_mc_hashes; | |
115 | u16 default_vf_vlan_id; | |
116 | u16 vlans_enabled; | |
7f870475 | 117 | bool clear_to_send; |
7f01648a | 118 | bool pf_set_mac; |
7f01648a GR |
119 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
120 | u16 pf_qos; | |
7f870475 GR |
121 | }; |
122 | ||
9a799d71 AK |
123 | /* wrapper around a pointer to a socket buffer, |
124 | * so a DMA handle can be stored along with the buffer */ | |
125 | struct ixgbe_tx_buffer { | |
126 | struct sk_buff *skb; | |
127 | dma_addr_t dma; | |
128 | unsigned long time_stamp; | |
129 | u16 length; | |
130 | u16 next_to_watch; | |
8ad494b0 AD |
131 | unsigned int bytecount; |
132 | u16 gso_segs; | |
133 | u8 mapped_as_page; | |
9a799d71 AK |
134 | }; |
135 | ||
136 | struct ixgbe_rx_buffer { | |
137 | struct sk_buff *skb; | |
138 | dma_addr_t dma; | |
139 | struct page *page; | |
140 | dma_addr_t page_dma; | |
762f4c57 | 141 | unsigned int page_offset; |
9a799d71 AK |
142 | }; |
143 | ||
144 | struct ixgbe_queue_stats { | |
145 | u64 packets; | |
146 | u64 bytes; | |
147 | }; | |
148 | ||
5b7da515 AD |
149 | struct ixgbe_tx_queue_stats { |
150 | u64 restart_queue; | |
151 | u64 tx_busy; | |
c84d324c JF |
152 | u64 completed; |
153 | u64 tx_done_old; | |
5b7da515 AD |
154 | }; |
155 | ||
156 | struct ixgbe_rx_queue_stats { | |
157 | u64 rsc_count; | |
158 | u64 rsc_flush; | |
159 | u64 non_eop_descs; | |
160 | u64 alloc_rx_page_failed; | |
161 | u64 alloc_rx_buff_failed; | |
162 | }; | |
163 | ||
7d637bcc AD |
164 | enum ixbge_ring_state_t { |
165 | __IXGBE_TX_FDIR_INIT_DONE, | |
166 | __IXGBE_TX_DETECT_HANG, | |
c84d324c | 167 | __IXGBE_HANG_CHECK_ARMED, |
7d637bcc AD |
168 | __IXGBE_RX_PS_ENABLED, |
169 | __IXGBE_RX_RSC_ENABLED, | |
170 | }; | |
171 | ||
172 | #define ring_is_ps_enabled(ring) \ | |
173 | test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state) | |
174 | #define set_ring_ps_enabled(ring) \ | |
175 | set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state) | |
176 | #define clear_ring_ps_enabled(ring) \ | |
177 | clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state) | |
178 | #define check_for_tx_hang(ring) \ | |
179 | test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
180 | #define set_check_for_tx_hang(ring) \ | |
181 | set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
182 | #define clear_check_for_tx_hang(ring) \ | |
183 | clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
184 | #define ring_is_rsc_enabled(ring) \ | |
185 | test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
186 | #define set_ring_rsc_enabled(ring) \ | |
187 | set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
188 | #define clear_ring_rsc_enabled(ring) \ | |
189 | clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
9a799d71 | 190 | struct ixgbe_ring { |
9a799d71 | 191 | void *desc; /* descriptor ring memory */ |
b6ec895e | 192 | struct device *dev; /* device for DMA mapping */ |
fc77dc3c | 193 | struct net_device *netdev; /* netdev ring belongs to */ |
9a799d71 AK |
194 | union { |
195 | struct ixgbe_tx_buffer *tx_buffer_info; | |
196 | struct ixgbe_rx_buffer *rx_buffer_info; | |
197 | }; | |
7d637bcc | 198 | unsigned long state; |
ae540af1 JB |
199 | u8 atr_sample_rate; |
200 | u8 atr_count; | |
201 | u16 count; /* amount of descriptors */ | |
202 | u16 rx_buf_len; | |
203 | u16 next_to_use; | |
204 | u16 next_to_clean; | |
205 | ||
206 | u8 queue_index; /* needed for multiqueue queue management */ | |
7d637bcc AD |
207 | u8 reg_idx; /* holds the special value that gets |
208 | * the hardware register offset | |
209 | * associated with this ring, which is | |
210 | * different for DCB and RSS modes | |
211 | */ | |
212 | ||
213 | u16 work_limit; /* max work per interrupt */ | |
9a799d71 | 214 | |
84ea2591 | 215 | u8 __iomem *tail; |
9a799d71 | 216 | |
f494e8fa AV |
217 | unsigned int total_bytes; |
218 | unsigned int total_packets; | |
9a799d71 AK |
219 | |
220 | struct ixgbe_queue_stats stats; | |
de1036b1 | 221 | struct u64_stats_sync syncp; |
5b7da515 AD |
222 | union { |
223 | struct ixgbe_tx_queue_stats tx_stats; | |
224 | struct ixgbe_rx_queue_stats rx_stats; | |
225 | }; | |
5b7da515 | 226 | int numa_node; |
ae540af1 JB |
227 | unsigned int size; /* length in bytes */ |
228 | dma_addr_t dma; /* phys. address of descriptor ring */ | |
1a51502b | 229 | struct rcu_head rcu; |
33cf09c9 | 230 | struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */ |
7ca3bc58 | 231 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 232 | |
c7e4358a SN |
233 | enum ixgbe_ring_f_enum { |
234 | RING_F_NONE = 0, | |
235 | RING_F_DCB, | |
7f870475 | 236 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 237 | RING_F_RSS, |
c4cf55e5 | 238 | RING_F_FDIR, |
0331a832 YZ |
239 | #ifdef IXGBE_FCOE |
240 | RING_F_FCOE, | |
241 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
242 | |
243 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
244 | }; | |
245 | ||
2f90b865 | 246 | #define IXGBE_MAX_DCB_INDICES 8 |
021230d4 | 247 | #define IXGBE_MAX_RSS_INDICES 16 |
7f870475 | 248 | #define IXGBE_MAX_VMDQ_INDICES 64 |
c4cf55e5 | 249 | #define IXGBE_MAX_FDIR_INDICES 64 |
0331a832 YZ |
250 | #ifdef IXGBE_FCOE |
251 | #define IXGBE_MAX_FCOE_INDICES 8 | |
e0fce695 JF |
252 | #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) |
253 | #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) | |
254 | #else | |
255 | #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES | |
256 | #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES | |
0331a832 | 257 | #endif /* IXGBE_FCOE */ |
021230d4 AV |
258 | struct ixgbe_ring_feature { |
259 | int indices; | |
260 | int mask; | |
7ca3bc58 | 261 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 262 | |
021230d4 | 263 | |
2f90b865 AD |
264 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
265 | ? 8 : 1) | |
266 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS | |
267 | ||
021230d4 AV |
268 | /* MAX_MSIX_Q_VECTORS of these are allocated, |
269 | * but we only use one per queue-specific vector. | |
270 | */ | |
271 | struct ixgbe_q_vector { | |
272 | struct ixgbe_adapter *adapter; | |
fe49f04a AD |
273 | unsigned int v_idx; /* index of q_vector within array, also used for |
274 | * finding the bit in EICR and friends that | |
275 | * represents the vector for this ring */ | |
33cf09c9 AD |
276 | #ifdef CONFIG_IXGBE_DCA |
277 | int cpu; /* CPU for DCA */ | |
278 | #endif | |
021230d4 AV |
279 | struct napi_struct napi; |
280 | DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */ | |
281 | DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */ | |
282 | u8 rxr_count; /* Rx ring count assigned to this vector */ | |
283 | u8 txr_count; /* Tx ring count assigned to this vector */ | |
30efa5a3 JB |
284 | u8 tx_itr; |
285 | u8 rx_itr; | |
021230d4 | 286 | u32 eitr; |
b25ebfd2 | 287 | cpumask_var_t affinity_mask; |
d0759ebb | 288 | char name[IFNAMSIZ + 9]; |
021230d4 AV |
289 | }; |
290 | ||
9a799d71 | 291 | /* Helper macros to switch between ints/sec and what the register uses. |
509ee935 JB |
292 | * And yes, it's the same math going both ways. The lowest value |
293 | * supported by all of the ixgbe hardware is 8. | |
9a799d71 AK |
294 | */ |
295 | #define EITR_INTS_PER_SEC_TO_REG(_eitr) \ | |
509ee935 | 296 | ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8) |
9a799d71 AK |
297 | #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG |
298 | ||
299 | #define IXGBE_DESC_UNUSED(R) \ | |
300 | ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ | |
301 | (R)->next_to_clean - (R)->next_to_use - 1) | |
302 | ||
303 | #define IXGBE_RX_DESC_ADV(R, i) \ | |
31f05a2d | 304 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
9a799d71 | 305 | #define IXGBE_TX_DESC_ADV(R, i) \ |
31f05a2d | 306 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
9a799d71 | 307 | #define IXGBE_TX_CTXTDESC_ADV(R, i) \ |
31f05a2d | 308 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
9a799d71 AK |
309 | |
310 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128 | |
63f39bd1 YZ |
311 | #ifdef IXGBE_FCOE |
312 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
313 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
314 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 315 | |
021230d4 AV |
316 | #define OTHER_VECTOR 1 |
317 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
318 | ||
e8e26350 PW |
319 | #define MAX_MSIX_VECTORS_82599 64 |
320 | #define MAX_MSIX_Q_VECTORS_82599 64 | |
eb7f139c PWJ |
321 | #define MAX_MSIX_VECTORS_82598 18 |
322 | #define MAX_MSIX_Q_VECTORS_82598 16 | |
323 | ||
e8e26350 PW |
324 | #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599 |
325 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 | |
eb7f139c | 326 | |
021230d4 | 327 | #define MIN_MSIX_Q_VECTORS 2 |
021230d4 AV |
328 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
329 | ||
9a799d71 AK |
330 | /* board specific private data structure */ |
331 | struct ixgbe_adapter { | |
332 | struct timer_list watchdog_timer; | |
f62bbb5e | 333 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
9a799d71 | 334 | u16 bd_number; |
9a799d71 | 335 | struct work_struct reset_task; |
7a921c93 | 336 | struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; |
2f90b865 AD |
337 | struct ixgbe_dcb_config dcb_cfg; |
338 | struct ixgbe_dcb_config temp_dcb_cfg; | |
339 | u8 dcb_set_bitmap; | |
264857b8 | 340 | enum ixgbe_fc_mode last_lfc_mode; |
9a799d71 | 341 | |
f494e8fa | 342 | /* Interrupt Throttle Rate */ |
f7554a2b NS |
343 | u32 rx_itr_setting; |
344 | u32 tx_itr_setting; | |
f494e8fa AV |
345 | u16 eitr_low; |
346 | u16 eitr_high; | |
347 | ||
9a799d71 | 348 | /* TX */ |
4a0b9ca0 | 349 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
30efa5a3 | 350 | int num_tx_queues; |
9a799d71 AK |
351 | u32 tx_timeout_count; |
352 | bool detect_tx_hung; | |
353 | ||
7ca3bc58 JB |
354 | u64 restart_queue; |
355 | u64 lsc_int; | |
356 | ||
9a799d71 | 357 | /* RX */ |
4a0b9ca0 | 358 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp; |
30efa5a3 | 359 | int num_rx_queues; |
7f870475 GR |
360 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
361 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 362 | u64 hw_csum_rx_error; |
e8e26350 | 363 | u64 hw_rx_no_dma_resources; |
9a799d71 | 364 | u64 non_eop_descs; |
021230d4 | 365 | int num_msix_vectors; |
eb7f139c | 366 | int max_msix_q_vectors; /* true count of q_vectors for device */ |
c7e4358a | 367 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
9a799d71 AK |
368 | struct msix_entry *msix_entries; |
369 | ||
9a799d71 AK |
370 | u32 alloc_rx_page_failed; |
371 | u32 alloc_rx_buff_failed; | |
372 | ||
021230d4 AV |
373 | /* Some features need tri-state capability, |
374 | * thus the additional *_CAPABLE flags. | |
375 | */ | |
9a799d71 | 376 | u32 flags; |
96b0e0f6 JB |
377 | #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1) |
378 | #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1) | |
379 | #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2) | |
380 | #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3) | |
381 | #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4) | |
382 | #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6) | |
383 | #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7) | |
384 | #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8) | |
385 | #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9) | |
386 | #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10) | |
387 | #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11) | |
388 | #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12) | |
389 | #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13) | |
e8e26350 | 390 | #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14) |
96b0e0f6 JB |
391 | #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16) |
392 | #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17) | |
393 | #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18) | |
394 | #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19) | |
0befdb3e | 395 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20) |
96b0e0f6 | 396 | #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22) |
10eec955 JF |
397 | #define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23) |
398 | #define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24) | |
399 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25) | |
400 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26) | |
401 | #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27) | |
402 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28) | |
403 | #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29) | |
404 | #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30) | |
96b0e0f6 | 405 | |
df647b5c PWJ |
406 | u32 flags2; |
407 | #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1) | |
408 | #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) | |
119fc60a | 409 | #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) |
96b0e0f6 JB |
410 | /* default to trying for four seconds */ |
411 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
9a799d71 AK |
412 | |
413 | /* OS defined structs */ | |
414 | struct net_device *netdev; | |
415 | struct pci_dev *pdev; | |
9a799d71 | 416 | |
da4dd0f7 PWJ |
417 | u32 test_icr; |
418 | struct ixgbe_ring test_tx_ring; | |
419 | struct ixgbe_ring test_rx_ring; | |
420 | ||
9a799d71 AK |
421 | /* structs defined in ixgbe_hw.h */ |
422 | struct ixgbe_hw hw; | |
423 | u16 msg_enable; | |
424 | struct ixgbe_hw_stats stats; | |
021230d4 AV |
425 | |
426 | /* Interrupt Throttle Rate */ | |
f7554a2b NS |
427 | u32 rx_eitr_param; |
428 | u32 tx_eitr_param; | |
9a799d71 AK |
429 | |
430 | unsigned long state; | |
431 | u64 tx_busy; | |
30efa5a3 JB |
432 | unsigned int tx_ring_count; |
433 | unsigned int rx_ring_count; | |
cf8280ee JB |
434 | |
435 | u32 link_speed; | |
436 | bool link_up; | |
437 | unsigned long link_check_timeout; | |
438 | ||
439 | struct work_struct watchdog_task; | |
c4900be0 DS |
440 | struct work_struct sfp_task; |
441 | struct timer_list sfp_timer; | |
e8e26350 PW |
442 | struct work_struct multispeed_fiber_task; |
443 | struct work_struct sfp_config_module_task; | |
c4cf55e5 PWJ |
444 | u32 fdir_pballoc; |
445 | u32 atr_sample_rate; | |
446 | spinlock_t fdir_perfect_lock; | |
447 | struct work_struct fdir_reinit_task; | |
d0ed8937 YZ |
448 | #ifdef IXGBE_FCOE |
449 | struct ixgbe_fcoe fcoe; | |
450 | #endif /* IXGBE_FCOE */ | |
94b982b2 MC |
451 | u64 rsc_total_count; |
452 | u64 rsc_total_flush; | |
e8e26350 | 453 | u32 wol; |
34b0368c | 454 | u16 eeprom_version; |
7f870475 | 455 | |
1a6c14a2 | 456 | int node; |
119fc60a MC |
457 | struct work_struct check_overtemp_task; |
458 | u32 interrupt_event; | |
d0759ebb | 459 | char lsc_int_name[IFNAMSIZ + 9]; |
1a6c14a2 | 460 | |
7f870475 GR |
461 | /* SR-IOV */ |
462 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
463 | unsigned int num_vfs; | |
464 | struct vf_data_storage *vfinfo; | |
9a799d71 AK |
465 | }; |
466 | ||
467 | enum ixbge_state_t { | |
468 | __IXGBE_TESTING, | |
469 | __IXGBE_RESETTING, | |
c4900be0 DS |
470 | __IXGBE_DOWN, |
471 | __IXGBE_SFP_MODULE_NOT_FOUND | |
9a799d71 AK |
472 | }; |
473 | ||
aa80175a AD |
474 | struct ixgbe_rsc_cb { |
475 | dma_addr_t dma; | |
476 | u16 skb_cnt; | |
477 | bool delay_unmap; | |
478 | }; | |
479 | #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb) | |
480 | ||
9a799d71 | 481 | enum ixgbe_boards { |
3957d63d | 482 | board_82598, |
e8e26350 | 483 | board_82599, |
fe15e8e1 | 484 | board_X540, |
9a799d71 AK |
485 | }; |
486 | ||
3957d63d | 487 | extern struct ixgbe_info ixgbe_82598_info; |
e8e26350 | 488 | extern struct ixgbe_info ixgbe_82599_info; |
fe15e8e1 | 489 | extern struct ixgbe_info ixgbe_X540_info; |
7a6b6f51 | 490 | #ifdef CONFIG_IXGBE_DCB |
32953543 | 491 | extern const struct dcbnl_rtnl_ops dcbnl_ops; |
2f90b865 AD |
492 | extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, |
493 | struct ixgbe_dcb_config *dst_dcb_cfg, | |
494 | int tc_max); | |
495 | #endif | |
9a799d71 AK |
496 | |
497 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 498 | extern const char ixgbe_driver_version[]; |
9a799d71 AK |
499 | |
500 | extern int ixgbe_up(struct ixgbe_adapter *adapter); | |
501 | extern void ixgbe_down(struct ixgbe_adapter *adapter); | |
d4f80882 | 502 | extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); |
9a799d71 | 503 | extern void ixgbe_reset(struct ixgbe_adapter *adapter); |
9a799d71 | 504 | extern void ixgbe_set_ethtool_ops(struct net_device *netdev); |
b6ec895e AD |
505 | extern int ixgbe_setup_rx_resources(struct ixgbe_ring *); |
506 | extern int ixgbe_setup_tx_resources(struct ixgbe_ring *); | |
507 | extern void ixgbe_free_rx_resources(struct ixgbe_ring *); | |
508 | extern void ixgbe_free_tx_resources(struct ixgbe_ring *); | |
84418e3b AD |
509 | extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); |
510 | extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); | |
2d39d576 YZ |
511 | extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
512 | struct ixgbe_ring *); | |
b4617240 | 513 | extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); |
2f90b865 | 514 | extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); |
7a921c93 | 515 | extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
84418e3b | 516 | extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, |
84418e3b AD |
517 | struct ixgbe_adapter *, |
518 | struct ixgbe_ring *); | |
b6ec895e | 519 | extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, |
84418e3b | 520 | struct ixgbe_tx_buffer *); |
fc77dc3c | 521 | extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); |
fe49f04a AD |
522 | extern void ixgbe_write_eitr(struct ixgbe_q_vector *); |
523 | extern int ethtool_ioctl(struct ifreq *ifr); | |
c84d324c | 524 | extern u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 index); |
ffff4772 PWJ |
525 | extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); |
526 | extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc); | |
527 | extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc); | |
528 | extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, | |
69830529 AD |
529 | union ixgbe_atr_hash_dword input, |
530 | union ixgbe_atr_hash_dword common, | |
ffff4772 | 531 | u8 queue); |
9a713e7c | 532 | extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, |
905e4a41 | 533 | union ixgbe_atr_input *input, |
9a713e7c PW |
534 | struct ixgbe_atr_input_masks *input_masks, |
535 | u16 soft_id, u8 queue); | |
b93a2226 DS |
536 | extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
537 | struct ixgbe_ring *ring); | |
538 | extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter, | |
539 | struct ixgbe_ring *ring); | |
7f870475 | 540 | extern void ixgbe_set_rx_mode(struct net_device *netdev); |
eacd73f7 YZ |
541 | #ifdef IXGBE_FCOE |
542 | extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); | |
543 | extern int ixgbe_fso(struct ixgbe_adapter *adapter, | |
544 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, | |
545 | u32 tx_flags, u8 *hdr_len); | |
332d4a7d YZ |
546 | extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter); |
547 | extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
548 | union ixgbe_adv_rx_desc *rx_desc, | |
549 | struct sk_buff *skb); | |
550 | extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, | |
551 | struct scatterlist *sgl, unsigned int sgc); | |
552 | extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); | |
8450ff8c YZ |
553 | extern int ixgbe_fcoe_enable(struct net_device *netdev); |
554 | extern int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 YZ |
555 | #ifdef CONFIG_IXGBE_DCB |
556 | extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); | |
557 | extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
558 | #endif /* CONFIG_IXGBE_DCB */ | |
61a1fa10 | 559 | extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
eacd73f7 | 560 | #endif /* IXGBE_FCOE */ |
9a799d71 AK |
561 | |
562 | #endif /* _IXGBE_H_ */ |