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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_82599.c
CommitLineData
11afc1b1
PW		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
11afc1b1
PW		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
096a58fd 34#include "ixgbe_mbx.h"
11afc1b1
PW		 35
36#define IXGBE_82599_MAX_TX_QUEUES 128
37#define IXGBE_82599_MAX_RX_QUEUES 128
38#define IXGBE_82599_RAR_ENTRIES 128
39#define IXGBE_82599_MC_TBL_SIZE 128
40#define IXGBE_82599_VFT_TBL_SIZE 128
41
5d5b7c39
ET		 42static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
cd7e1f0b
DS		 49static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
5d5b7c39
ET		 53static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
8620a103
MC		 56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
11afc1b1
PW		 59static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed *speed,
61 bool *autoneg);
8620a103
MC		 62static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
63 ixgbe_link_speed speed,
64 bool autoneg,
65 bool autoneg_wait_to_complete);
794caeb2 66static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
11afc1b1 67
7b25cdba 68static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 69{
70 struct ixgbe_mac_info *mac = &hw->mac;
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
8620a103 73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
61fac744
PW		 74 mac->ops.disable_tx_laser =
75 &ixgbe_disable_tx_laser_multispeed_fiber;
76 mac->ops.enable_tx_laser =
77 &ixgbe_enable_tx_laser_multispeed_fiber;
1097cd17 78 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
11afc1b1 79 } else {
61fac744
PW		 80 mac->ops.disable_tx_laser = NULL;
81 mac->ops.enable_tx_laser = NULL;
1097cd17 82 mac->ops.flap_tx_laser = NULL;
cd7e1f0b
DS		 83 if ((mac->ops.get_media_type(hw) ==
84 ixgbe_media_type_backplane) &&
85 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
86 hw->phy.smart_speed == ixgbe_smart_speed_on))
87 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
88 else
89 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
11afc1b1
PW		 90 }
91}
92
7b25cdba 93static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 94{
95 s32 ret_val = 0;
96 u16 list_offset, data_offset, data_value;
97
98 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
99 ixgbe_init_mac_link_ops_82599(hw);
553b4497
PW		 100
101 hw->phy.ops.reset = NULL;
102
11afc1b1
PW		 103 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
104 &data_offset);
105
106 if (ret_val != 0)
107 goto setup_sfp_out;
108
aa5aec88
PWJ		 109 /* PHY config will finish before releasing the semaphore */
110 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
111 if (ret_val != 0) {
112 ret_val = IXGBE_ERR_SWFW_SYNC;
113 goto setup_sfp_out;
114 }
115
11afc1b1
PW		 116 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
117 while (data_value != 0xffff) {
118 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
119 IXGBE_WRITE_FLUSH(hw);
120 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
121 }
1479ad4f
PWJ		 122 /* Now restart DSP by setting Restart_AN */
123 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
124 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
aa5aec88
PWJ		 125
126 /* Release the semaphore */
127 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
128 /* Delay obtaining semaphore again to allow FW access */
129 msleep(hw->eeprom.semaphore_delay);
11afc1b1
PW		 130 }
131
132setup_sfp_out:
133 return ret_val;
134}
135
11afc1b1
PW		 136static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
137{
138 struct ixgbe_mac_info *mac = &hw->mac;
11afc1b1 139
04f165ef 140 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1 141
04f165ef
PW		 142 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
143 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
144 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
145 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
146 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
21ce849b 147 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
11afc1b1 148
04f165ef
PW		 149 return 0;
150}
11afc1b1 151
04f165ef
PW		 152/**
153 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
154 * @hw: pointer to hardware structure
155 *
156 * Initialize any function pointers that were not able to be
157 * set during get_invariants because the PHY/SFP type was
158 * not known. Perform the SFP init if necessary.
159 *
160 **/
7b25cdba 161static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
04f165ef
PW		 162{
163 struct ixgbe_mac_info *mac = &hw->mac;
164 struct ixgbe_phy_info *phy = &hw->phy;
165 s32 ret_val = 0;
11afc1b1 166
04f165ef
PW		 167 /* Identify the PHY or SFP module */
168 ret_val = phy->ops.identify(hw);
169
170 /* Setup function pointers based on detected SFP module and speeds */
171 ixgbe_init_mac_link_ops_82599(hw);
11afc1b1
PW		 172
173 /* If copper media, overwrite with copper function pointers */
174 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
175 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
11afc1b1
PW		 176 mac->ops.get_link_capabilities =
177 &ixgbe_get_copper_link_capabilities_82599;
178 }
179
04f165ef 180 /* Set necessary function pointers based on phy type */
11afc1b1
PW		 181 switch (hw->phy.type) {
182 case ixgbe_phy_tn:
183 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
184 phy->ops.get_firmware_version =
04f165ef 185 &ixgbe_get_phy_firmware_version_tnx;
11afc1b1
PW		 186 break;
187 default:
188 break;
189 }
190
11afc1b1
PW		 191 return ret_val;
192}
193
194/**
195 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
196 * @hw: pointer to hardware structure
197 * @speed: pointer to link speed
198 * @negotiation: true when autoneg or autotry is enabled
199 *
200 * Determines the link capabilities by reading the AUTOC register.
201 **/
7b25cdba
DS		 202static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
203 ixgbe_link_speed *speed,
204 bool *negotiation)
11afc1b1
PW		 205{
206 s32 status = 0;
1eb99d5a 207 u32 autoc = 0;
11afc1b1 208
cb836a97
DS		 209 /* Determine 1G link capabilities off of SFP+ type */
210 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
211 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
212 *speed = IXGBE_LINK_SPEED_1GB_FULL;
213 *negotiation = true;
214 goto out;
215 }
216
1eb99d5a
PW		 217 /*
218 * Determine link capabilities based on the stored value of AUTOC,
219 * which represents EEPROM defaults. If AUTOC value has not been
220 * stored, use the current register value.
221 */
222 if (hw->mac.orig_link_settings_stored)
223 autoc = hw->mac.orig_autoc;
224 else
225 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
226
227 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
11afc1b1
PW		 228 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
229 *speed = IXGBE_LINK_SPEED_1GB_FULL;
230 *negotiation = false;
231 break;
232
233 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
234 *speed = IXGBE_LINK_SPEED_10GB_FULL;
235 *negotiation = false;
236 break;
237
238 case IXGBE_AUTOC_LMS_1G_AN:
239 *speed = IXGBE_LINK_SPEED_1GB_FULL;
240 *negotiation = true;
241 break;
242
243 case IXGBE_AUTOC_LMS_10G_SERIAL:
244 *speed = IXGBE_LINK_SPEED_10GB_FULL;
245 *negotiation = false;
246 break;
247
248 case IXGBE_AUTOC_LMS_KX4_KX_KR:
249 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
250 *speed = IXGBE_LINK_SPEED_UNKNOWN;
1eb99d5a 251 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 252 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 253 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 254 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 255 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 256 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
257 *negotiation = true;
258 break;
259
260 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
261 *speed = IXGBE_LINK_SPEED_100_FULL;
1eb99d5a 262 if (autoc & IXGBE_AUTOC_KR_SUPP)
11afc1b1 263 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 264 if (autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 265 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
1eb99d5a 266 if (autoc & IXGBE_AUTOC_KX_SUPP)
11afc1b1
PW		 267 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
268 *negotiation = true;
269 break;
270
271 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
272 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
273 *negotiation = false;
274 break;
275
276 default:
277 status = IXGBE_ERR_LINK_SETUP;
278 goto out;
279 break;
280 }
281
282 if (hw->phy.multispeed_fiber) {
283 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
284 IXGBE_LINK_SPEED_1GB_FULL;
285 *negotiation = true;
286 }
287
288out:
289 return status;
290}
291
292/**
293 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
294 * @hw: pointer to hardware structure
295 * @speed: pointer to link speed
296 * @autoneg: boolean auto-negotiation value
297 *
298 * Determines the link capabilities by reading the AUTOC register.
299 **/
300static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
301 ixgbe_link_speed *speed,
302 bool *autoneg)
303{
304 s32 status = IXGBE_ERR_LINK_SETUP;
305 u16 speed_ability;
306
307 *speed = 0;
308 *autoneg = true;
309
6b73e10d 310 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
11afc1b1
PW		 311 &speed_ability);
312
313 if (status == 0) {
6b73e10d 314 if (speed_ability & MDIO_SPEED_10G)
11afc1b1 315 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
6b73e10d 316 if (speed_ability & MDIO_PMA_SPEED_1000)
11afc1b1
PW		 317 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
318 }
319
320 return status;
321}
322
323/**
324 * ixgbe_get_media_type_82599 - Get media type
325 * @hw: pointer to hardware structure
326 *
327 * Returns the media type (fiber, copper, backplane)
328 **/
7b25cdba 329static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 330{
331 enum ixgbe_media_type media_type;
332
333 /* Detect if there is a copper PHY attached. */
334 if (hw->phy.type == ixgbe_phy_cu_unknown ||
335 hw->phy.type == ixgbe_phy_tn) {
336 media_type = ixgbe_media_type_copper;
337 goto out;
338 }
339
340 switch (hw->device_id) {
11afc1b1 341 case IXGBE_DEV_ID_82599_KX4:
dbfec662 342 case IXGBE_DEV_ID_82599_KX4_MEZZ:
312eb931 343 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
74757d49 344 case IXGBE_DEV_ID_82599_KR:
1fcf03e6 345 case IXGBE_DEV_ID_82599_XAUI_LOM:
11afc1b1
PW		 346 /* Default device ID is mezzanine card KX/KX4 */
347 media_type = ixgbe_media_type_backplane;
348 break;
349 case IXGBE_DEV_ID_82599_SFP:
38ad1c8e 350 case IXGBE_DEV_ID_82599_SFP_EM:
11afc1b1
PW		 351 media_type = ixgbe_media_type_fiber;
352 break;
8911184f 353 case IXGBE_DEV_ID_82599_CX4:
6b1be199 354 media_type = ixgbe_media_type_cx4;
8911184f 355 break;
11afc1b1
PW		 356 default:
357 media_type = ixgbe_media_type_unknown;
358 break;
359 }
360out:
361 return media_type;
362}
363
364/**
8620a103 365 * ixgbe_start_mac_link_82599 - Setup MAC link settings
11afc1b1 366 * @hw: pointer to hardware structure
8620a103 367 * @autoneg_wait_to_complete: true when waiting for completion is needed
11afc1b1
PW		 368 *
369 * Configures link settings based on values in the ixgbe_hw struct.
370 * Restarts the link. Performs autonegotiation if needed.
371 **/
5d5b7c39 372static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
8620a103 373 bool autoneg_wait_to_complete)
11afc1b1
PW		 374{
375 u32 autoc_reg;
376 u32 links_reg;
377 u32 i;
378 s32 status = 0;
379
380 /* Restart link */
381 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
382 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
383 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
384
385 /* Only poll for autoneg to complete if specified to do so */
8620a103 386 if (autoneg_wait_to_complete) {
11afc1b1
PW		 387 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
388 IXGBE_AUTOC_LMS_KX4_KX_KR ||
389 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
390 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
391 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
392 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
393 links_reg = 0; /* Just in case Autoneg time = 0 */
394 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
395 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
396 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
397 break;
398 msleep(100);
399 }
400 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
401 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
402 hw_dbg(hw, "Autoneg did not complete.\n");
403 }
404 }
405 }
406
11afc1b1
PW		 407 /* Add delay to filter out noises during initial link setup */
408 msleep(50);
409
410 return status;
411}
412
61fac744
PW		 413 /**
414 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
415 * @hw: pointer to hardware structure
416 *
417 * The base drivers may require better control over SFP+ module
418 * PHY states. This includes selectively shutting down the Tx
419 * laser on the PHY, effectively halting physical link.
420 **/
5d5b7c39 421static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 422{
423 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
424
425 /* Disable tx laser; allow 100us to go dark per spec */
426 esdp_reg |= IXGBE_ESDP_SDP3;
427 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
428 IXGBE_WRITE_FLUSH(hw);
429 udelay(100);
430}
431
432/**
433 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
434 * @hw: pointer to hardware structure
435 *
436 * The base drivers may require better control over SFP+ module
437 * PHY states. This includes selectively turning on the Tx
438 * laser on the PHY, effectively starting physical link.
439 **/
5d5b7c39 440static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
61fac744
PW		 441{
442 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
443
444 /* Enable tx laser; allow 100ms to light up */
445 esdp_reg &= ~IXGBE_ESDP_SDP3;
446 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
447 IXGBE_WRITE_FLUSH(hw);
448 msleep(100);
449}
450
1097cd17
MC		 451/**
452 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
453 * @hw: pointer to hardware structure
454 *
455 * When the driver changes the link speeds that it can support,
456 * it sets autotry_restart to true to indicate that we need to
457 * initiate a new autotry session with the link partner. To do
458 * so, we set the speed then disable and re-enable the tx laser, to
459 * alert the link partner that it also needs to restart autotry on its
460 * end. This is consistent with true clause 37 autoneg, which also
461 * involves a loss of signal.
462 **/
5d5b7c39 463static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
1097cd17 464{
1097cd17
MC		 465 hw_dbg(hw, "ixgbe_flap_tx_laser_multispeed_fiber\n");
466
467 if (hw->mac.autotry_restart) {
61fac744
PW		 468 ixgbe_disable_tx_laser_multispeed_fiber(hw);
469 ixgbe_enable_tx_laser_multispeed_fiber(hw);
1097cd17
MC		 470 hw->mac.autotry_restart = false;
471 }
472}
473
11afc1b1 474/**
8620a103 475 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
11afc1b1
PW		 476 * @hw: pointer to hardware structure
477 * @speed: new link speed
478 * @autoneg: true if autonegotiation enabled
479 * @autoneg_wait_to_complete: true when waiting for completion is needed
480 *
481 * Set the link speed in the AUTOC register and restarts link.
482 **/
8620a103
MC		 483s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
484 ixgbe_link_speed speed,
485 bool autoneg,
486 bool autoneg_wait_to_complete)
11afc1b1
PW		 487{
488 s32 status = 0;
489 ixgbe_link_speed phy_link_speed;
490 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
491 u32 speedcnt = 0;
492 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
493 bool link_up = false;
494 bool negotiation;
50ac58ba 495 int i;
11afc1b1
PW		 496
497 /* Mask off requested but non-supported speeds */
498 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
499 speed &= phy_link_speed;
500
501 /*
502 * Try each speed one by one, highest priority first. We do this in
503 * software because 10gb fiber doesn't support speed autonegotiation.
504 */
505 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
506 speedcnt++;
507 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
508
50ac58ba
PWJ		 509 /* If we already have link at this speed, just jump out */
510 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
511
512 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
513 goto out;
514
515 /* Set the module link speed */
11afc1b1
PW		 516 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
517 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 518 IXGBE_WRITE_FLUSH(hw);
11afc1b1 519
50ac58ba
PWJ		 520 /* Allow module to change analog characteristics (1G->10G) */
521 msleep(40);
11afc1b1 522
8620a103
MC		 523 status = ixgbe_setup_mac_link_82599(hw,
524 IXGBE_LINK_SPEED_10GB_FULL,
525 autoneg,
526 autoneg_wait_to_complete);
50ac58ba 527 if (status != 0)
c3c74327 528 return status;
50ac58ba
PWJ		 529
530 /* Flap the tx laser if it has not already been done */
1097cd17 531 hw->mac.ops.flap_tx_laser(hw);
50ac58ba 532
cd7e1f0b
DS		 533 /*
534 * Wait for the controller to acquire link. Per IEEE 802.3ap,
535 * Section 73.10.2, we may have to wait up to 500ms if KR is
536 * attempted. 82599 uses the same timing for 10g SFI.
537 */
538
50ac58ba
PWJ		 539 for (i = 0; i < 5; i++) {
540 /* Wait for the link partner to also set speed */
541 msleep(100);
542
543 /* If we have link, just jump out */
544 hw->mac.ops.check_link(hw, &phy_link_speed,
545 &link_up, false);
546 if (link_up)
547 goto out;
548 }
11afc1b1
PW		 549 }
550
551 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
552 speedcnt++;
553 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
554 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
555
50ac58ba
PWJ		 556 /* If we already have link at this speed, just jump out */
557 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
558
559 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
560 goto out;
561
562 /* Set the module link speed */
11afc1b1
PW		 563 esdp_reg &= ~IXGBE_ESDP_SDP5;
564 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
565 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
1097cd17 566 IXGBE_WRITE_FLUSH(hw);
11afc1b1 567
50ac58ba
PWJ		 568 /* Allow module to change analog characteristics (10G->1G) */
569 msleep(40);
11afc1b1 570
8620a103 571 status = ixgbe_setup_mac_link_82599(hw,
50ac58ba
PWJ		 572 IXGBE_LINK_SPEED_1GB_FULL,
573 autoneg,
574 autoneg_wait_to_complete);
575 if (status != 0)
c3c74327 576 return status;
50ac58ba
PWJ		 577
578 /* Flap the tx laser if it has not already been done */
1097cd17 579 hw->mac.ops.flap_tx_laser(hw);
50ac58ba
PWJ		 580
581 /* Wait for the link partner to also set speed */
582 msleep(100);
11afc1b1
PW		 583
584 /* If we have link, just jump out */
585 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
586 if (link_up)
587 goto out;
588 }
589
590 /*
591 * We didn't get link. Configure back to the highest speed we tried,
592 * (if there was more than one). We call ourselves back with just the
593 * single highest speed that the user requested.
594 */
595 if (speedcnt > 1)
8620a103
MC		 596 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
597 highest_link_speed,
598 autoneg,
599 autoneg_wait_to_complete);
11afc1b1
PW		 600
601out:
c3c74327
MC		 602 /* Set autoneg_advertised value based on input link speed */
603 hw->phy.autoneg_advertised = 0;
604
605 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
606 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
607
608 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
609 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
610
11afc1b1
PW		 611 return status;
612}
613
cd7e1f0b
DS		 614/**
615 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
616 * @hw: pointer to hardware structure
617 * @speed: new link speed
618 * @autoneg: true if autonegotiation enabled
619 * @autoneg_wait_to_complete: true when waiting for completion is needed
620 *
621 * Implements the Intel SmartSpeed algorithm.
622 **/
623static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
624 ixgbe_link_speed speed, bool autoneg,
625 bool autoneg_wait_to_complete)
626{
627 s32 status = 0;
628 ixgbe_link_speed link_speed;
629 s32 i, j;
630 bool link_up = false;
631 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
c4ee6a53 632 struct ixgbe_adapter *adapter = hw->back;
cd7e1f0b
DS		 633
634 hw_dbg(hw, "ixgbe_setup_mac_link_smartspeed.\n");
635
636 /* Set autoneg_advertised value based on input link speed */
637 hw->phy.autoneg_advertised = 0;
638
639 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
640 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
641
642 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
643 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
644
645 if (speed & IXGBE_LINK_SPEED_100_FULL)
646 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
647
648 /*
649 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
650 * autoneg advertisement if link is unable to be established at the
651 * highest negotiated rate. This can sometimes happen due to integrity
652 * issues with the physical media connection.
653 */
654
655 /* First, try to get link with full advertisement */
656 hw->phy.smart_speed_active = false;
657 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
658 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
659 autoneg_wait_to_complete);
660 if (status)
661 goto out;
662
663 /*
664 * Wait for the controller to acquire link. Per IEEE 802.3ap,
665 * Section 73.10.2, we may have to wait up to 500ms if KR is
666 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
667 * Table 9 in the AN MAS.
668 */
669 for (i = 0; i < 5; i++) {
670 mdelay(100);
671
672 /* If we have link, just jump out */
673 hw->mac.ops.check_link(hw, &link_speed,
674 &link_up, false);
675 if (link_up)
676 goto out;
677 }
678 }
679
680 /*
681 * We didn't get link. If we advertised KR plus one of KX4/KX
682 * (or BX4/BX), then disable KR and try again.
683 */
684 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
685 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
686 goto out;
687
688 /* Turn SmartSpeed on to disable KR support */
689 hw->phy.smart_speed_active = true;
690 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
691 autoneg_wait_to_complete);
692 if (status)
693 goto out;
694
695 /*
696 * Wait for the controller to acquire link. 600ms will allow for
697 * the AN link_fail_inhibit_timer as well for multiple cycles of
698 * parallel detect, both 10g and 1g. This allows for the maximum
699 * connect attempts as defined in the AN MAS table 73-7.
700 */
701 for (i = 0; i < 6; i++) {
702 mdelay(100);
703
704 /* If we have link, just jump out */
705 hw->mac.ops.check_link(hw, &link_speed,
706 &link_up, false);
707 if (link_up)
708 goto out;
709 }
710
711 /* We didn't get link. Turn SmartSpeed back off. */
712 hw->phy.smart_speed_active = false;
713 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
714 autoneg_wait_to_complete);
715
716out:
c4ee6a53 717 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
396e799c 718 e_info(hw, "Smartspeed has downgraded the link speed from "
849c4542 719 "the maximum advertised\n");
cd7e1f0b
DS		 720 return status;
721}
722
11afc1b1 723/**
8620a103 724 * ixgbe_setup_mac_link_82599 - Set MAC link speed
11afc1b1
PW		 725 * @hw: pointer to hardware structure
726 * @speed: new link speed
727 * @autoneg: true if autonegotiation enabled
728 * @autoneg_wait_to_complete: true when waiting for completion is needed
729 *
730 * Set the link speed in the AUTOC register and restarts link.
731 **/
5d5b7c39 732static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
8620a103
MC		 733 ixgbe_link_speed speed, bool autoneg,
734 bool autoneg_wait_to_complete)
11afc1b1
PW		 735{
736 s32 status = 0;
737 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
738 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
50ac58ba 739 u32 start_autoc = autoc;
1eb99d5a 740 u32 orig_autoc = 0;
11afc1b1
PW		 741 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
742 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
743 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
744 u32 links_reg;
745 u32 i;
746 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
747
748 /* Check to see if speed passed in is supported. */
749 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
750 speed &= link_capabilities;
751
50ac58ba
PWJ		 752 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
753 status = IXGBE_ERR_LINK_SETUP;
754 goto out;
755 }
756
1eb99d5a
PW		 757 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
758 if (hw->mac.orig_link_settings_stored)
759 orig_autoc = hw->mac.orig_autoc;
760 else
761 orig_autoc = autoc;
762
763
50ac58ba
PWJ		 764 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
765 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
766 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
11afc1b1
PW		 767 /* Set KX4/KX/KR support according to speed requested */
768 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
769 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1eb99d5a 770 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
11afc1b1 771 autoc |= IXGBE_AUTOC_KX4_SUPP;
cd7e1f0b
DS		 772 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
773 (hw->phy.smart_speed_active == false))
11afc1b1
PW		 774 autoc |= IXGBE_AUTOC_KR_SUPP;
775 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
776 autoc |= IXGBE_AUTOC_KX_SUPP;
777 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
778 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
779 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
780 /* Switch from 1G SFI to 10G SFI if requested */
781 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
782 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
783 autoc &= ~IXGBE_AUTOC_LMS_MASK;
784 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
785 }
786 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
787 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
788 /* Switch from 10G SFI to 1G SFI if requested */
789 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
790 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
791 autoc &= ~IXGBE_AUTOC_LMS_MASK;
792 if (autoneg)
793 autoc |= IXGBE_AUTOC_LMS_1G_AN;
794 else
795 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
796 }
797 }
798
50ac58ba 799 if (autoc != start_autoc) {
11afc1b1
PW		 800 /* Restart link */
801 autoc |= IXGBE_AUTOC_AN_RESTART;
802 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
803
804 /* Only poll for autoneg to complete if specified to do so */
805 if (autoneg_wait_to_complete) {
806 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
807 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
808 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
809 links_reg = 0; /*Just in case Autoneg time=0*/
810 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
811 links_reg =
812 IXGBE_READ_REG(hw, IXGBE_LINKS);
813 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
814 break;
815 msleep(100);
816 }
817 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
818 status =
819 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
820 hw_dbg(hw, "Autoneg did not "
821 "complete.\n");
822 }
823 }
824 }
825
11afc1b1
PW		 826 /* Add delay to filter out noises during initial link setup */
827 msleep(50);
828 }
829
50ac58ba 830out:
11afc1b1
PW		 831 return status;
832}
833
834/**
8620a103 835 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
11afc1b1
PW		 836 * @hw: pointer to hardware structure
837 * @speed: new link speed
838 * @autoneg: true if autonegotiation enabled
839 * @autoneg_wait_to_complete: true if waiting is needed to complete
840 *
841 * Restarts link on PHY and MAC based on settings passed in.
842 **/
8620a103
MC		 843static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
844 ixgbe_link_speed speed,
845 bool autoneg,
846 bool autoneg_wait_to_complete)
11afc1b1
PW		 847{
848 s32 status;
849
850 /* Setup the PHY according to input speed */
851 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
852 autoneg_wait_to_complete);
853 /* Set up MAC */
8620a103 854 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
11afc1b1
PW		 855
856 return status;
857}
858
859/**
860 * ixgbe_reset_hw_82599 - Perform hardware reset
861 * @hw: pointer to hardware structure
862 *
863 * Resets the hardware by resetting the transmit and receive units, masks
864 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
865 * reset.
866 **/
7b25cdba 867static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 868{
869 s32 status = 0;
c9205697 870 u32 ctrl;
11afc1b1
PW		 871 u32 i;
872 u32 autoc;
873 u32 autoc2;
874
875 /* Call adapter stop to disable tx/rx and clear interrupts */
876 hw->mac.ops.stop_adapter(hw);
877
553b4497 878 /* PHY ops must be identified and initialized prior to reset */
04f165ef 879
553b4497
PW		 880 /* Init PHY and function pointers, perform SFP setup */
881 status = hw->phy.ops.init(hw);
04f165ef 882
553b4497
PW		 883 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
884 goto reset_hw_out;
04f165ef 885
553b4497
PW		 886 /* Setup SFP module if there is one present. */
887 if (hw->phy.sfp_setup_needed) {
888 status = hw->mac.ops.setup_sfp(hw);
889 hw->phy.sfp_setup_needed = false;
04f165ef 890 }
11afc1b1 891
553b4497
PW		 892 /* Reset PHY */
893 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
894 hw->phy.ops.reset(hw);
895
11afc1b1
PW		 896 /*
897 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
898 * access and verify no pending requests before reset
899 */
04f165ef
PW		 900 status = ixgbe_disable_pcie_master(hw);
901 if (status != 0) {
11afc1b1
PW		 902 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
903 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
904 }
905
906 /*
907 * Issue global reset to the MAC. This needs to be a SW reset.
908 * If link reset is used, it might reset the MAC when mng is using it
909 */
910 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
911 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
912 IXGBE_WRITE_FLUSH(hw);
913
914 /* Poll for reset bit to self-clear indicating reset is complete */
915 for (i = 0; i < 10; i++) {
916 udelay(1);
917 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
918 if (!(ctrl & IXGBE_CTRL_RST))
919 break;
920 }
921 if (ctrl & IXGBE_CTRL_RST) {
922 status = IXGBE_ERR_RESET_FAILED;
923 hw_dbg(hw, "Reset polling failed to complete.\n");
924 }
11afc1b1
PW		 925
926 msleep(50);
927
11afc1b1
PW		 928 /*
929 * Store the original AUTOC/AUTOC2 values if they have not been
930 * stored off yet. Otherwise restore the stored original
931 * values since the reset operation sets back to defaults.
932 */
933 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
934 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
935 if (hw->mac.orig_link_settings_stored == false) {
936 hw->mac.orig_autoc = autoc;
937 hw->mac.orig_autoc2 = autoc2;
938 hw->mac.orig_link_settings_stored = true;
4df10466 939 } else {
11afc1b1
PW		 940 if (autoc != hw->mac.orig_autoc)
941 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
942 IXGBE_AUTOC_AN_RESTART));
943
944 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
945 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
946 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
947 autoc2 |= (hw->mac.orig_autoc2 &
948 IXGBE_AUTOC2_UPPER_MASK);
949 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
950 }
951 }
952
aca6bee7
WJP		 953 /*
954 * Store MAC address from RAR0, clear receive address registers, and
955 * clear the multicast table. Also reset num_rar_entries to 128,
956 * since we modify this value when programming the SAN MAC address.
957 */
958 hw->mac.num_rar_entries = 128;
959 hw->mac.ops.init_rx_addrs(hw);
960
11afc1b1
PW		 961 /* Store the permanent mac address */
962 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
963
0365e6e4
PW		 964 /* Store the permanent SAN mac address */
965 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
966
aca6bee7
WJP		 967 /* Add the SAN MAC address to the RAR only if it's a valid address */
968 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
969 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
970 hw->mac.san_addr, 0, IXGBE_RAH_AV);
971
972 /* Reserve the last RAR for the SAN MAC address */
973 hw->mac.num_rar_entries--;
974 }
975
383ff34b
YZ		 976 /* Store the alternative WWNN/WWPN prefix */
977 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
978 &hw->mac.wwpn_prefix);
979
04f165ef 980reset_hw_out:
11afc1b1
PW		 981 return status;
982}
983
ffff4772
PWJ		 984/**
985 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
986 * @hw: pointer to hardware structure
987 **/
988s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
989{
990 int i;
991 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
992 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
993
994 /*
995 * Before starting reinitialization process,
996 * FDIRCMD.CMD must be zero.
997 */
998 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
999 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1000 IXGBE_FDIRCMD_CMD_MASK))
1001 break;
1002 udelay(10);
1003 }
1004 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1005 hw_dbg(hw ,"Flow Director previous command isn't complete, "
d6dbee86 1006 "aborting table re-initialization.\n");
ffff4772
PWJ		 1007 return IXGBE_ERR_FDIR_REINIT_FAILED;
1008 }
1009
1010 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1011 IXGBE_WRITE_FLUSH(hw);
1012 /*
1013 * 82599 adapters flow director init flow cannot be restarted,
1014 * Workaround 82599 silicon errata by performing the following steps
1015 * before re-writing the FDIRCTRL control register with the same value.
1016 * - write 1 to bit 8 of FDIRCMD register &
1017 * - write 0 to bit 8 of FDIRCMD register
1018 */
1019 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1020 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1021 IXGBE_FDIRCMD_CLEARHT));
1022 IXGBE_WRITE_FLUSH(hw);
1023 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1024 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1025 ~IXGBE_FDIRCMD_CLEARHT));
1026 IXGBE_WRITE_FLUSH(hw);
1027 /*
1028 * Clear FDIR Hash register to clear any leftover hashes
1029 * waiting to be programmed.
1030 */
1031 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1032 IXGBE_WRITE_FLUSH(hw);
1033
1034 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1035 IXGBE_WRITE_FLUSH(hw);
1036
1037 /* Poll init-done after we write FDIRCTRL register */
1038 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1039 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1040 IXGBE_FDIRCTRL_INIT_DONE)
1041 break;
1042 udelay(10);
1043 }
1044 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1045 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1046 return IXGBE_ERR_FDIR_REINIT_FAILED;
1047 }
1048
1049 /* Clear FDIR statistics registers (read to clear) */
1050 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1051 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1052 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1053 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1054 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1055
1056 return 0;
1057}
1058
1059/**
1060 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1061 * @hw: pointer to hardware structure
1062 * @pballoc: which mode to allocate filters with
1063 **/
1064s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1065{
1066 u32 fdirctrl = 0;
1067 u32 pbsize;
1068 int i;
1069
1070 /*
1071 * Before enabling Flow Director, the Rx Packet Buffer size
1072 * must be reduced. The new value is the current size minus
1073 * flow director memory usage size.
1074 */
1075 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1076 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1077 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1078
1079 /*
1080 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1081 * intialized to zero for non DCB mode otherwise actual total RX PB
1082 * would be bigger than programmed and filter space would run into
1083 * the PB 0 region.
1084 */
1085 for (i = 1; i < 8; i++)
1086 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1087
1088 /* Send interrupt when 64 filters are left */
1089 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1090
1091 /* Set the maximum length per hash bucket to 0xA filters */
1092 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1093
1094 switch (pballoc) {
1095 case IXGBE_FDIR_PBALLOC_64K:
1096 /* 8k - 1 signature filters */
1097 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1098 break;
1099 case IXGBE_FDIR_PBALLOC_128K:
1100 /* 16k - 1 signature filters */
1101 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1102 break;
1103 case IXGBE_FDIR_PBALLOC_256K:
1104 /* 32k - 1 signature filters */
1105 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1106 break;
1107 default:
1108 /* bad value */
1109 return IXGBE_ERR_CONFIG;
1110 };
1111
1112 /* Move the flexible bytes to use the ethertype - shift 6 words */
1113 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1114
1115 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1116
1117 /* Prime the keys for hashing */
1118 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1119 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1120 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1121 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1122
1123 /*
1124 * Poll init-done after we write the register. Estimated times:
1125 * 10G: PBALLOC = 11b, timing is 60us
1126 * 1G: PBALLOC = 11b, timing is 600us
1127 * 100M: PBALLOC = 11b, timing is 6ms
1128 *
1129 * Multiple these timings by 4 if under full Rx load
1130 *
1131 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1132 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1133 * this might not finish in our poll time, but we can live with that
1134 * for now.
1135 */
1136 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1137 IXGBE_WRITE_FLUSH(hw);
1138 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1139 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1140 IXGBE_FDIRCTRL_INIT_DONE)
1141 break;
1142 msleep(1);
1143 }
1144 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1145 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1146
1147 return 0;
1148}
1149
1150/**
1151 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1152 * @hw: pointer to hardware structure
1153 * @pballoc: which mode to allocate filters with
1154 **/
1155s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1156{
1157 u32 fdirctrl = 0;
1158 u32 pbsize;
1159 int i;
1160
1161 /*
1162 * Before enabling Flow Director, the Rx Packet Buffer size
1163 * must be reduced. The new value is the current size minus
1164 * flow director memory usage size.
1165 */
1166 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1167 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1168 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1169
1170 /*
1171 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1172 * intialized to zero for non DCB mode otherwise actual total RX PB
1173 * would be bigger than programmed and filter space would run into
1174 * the PB 0 region.
1175 */
1176 for (i = 1; i < 8; i++)
1177 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1178
1179 /* Send interrupt when 64 filters are left */
1180 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1181
9a713e7c
PW		 1182 /* Initialize the drop queue to Rx queue 127 */
1183 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1184
ffff4772
PWJ		 1185 switch (pballoc) {
1186 case IXGBE_FDIR_PBALLOC_64K:
1187 /* 2k - 1 perfect filters */
1188 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1189 break;
1190 case IXGBE_FDIR_PBALLOC_128K:
1191 /* 4k - 1 perfect filters */
1192 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1193 break;
1194 case IXGBE_FDIR_PBALLOC_256K:
1195 /* 8k - 1 perfect filters */
1196 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1197 break;
1198 default:
1199 /* bad value */
1200 return IXGBE_ERR_CONFIG;
1201 };
1202
1203 /* Turn perfect match filtering on */
1204 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1205 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1206
1207 /* Move the flexible bytes to use the ethertype - shift 6 words */
1208 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1209
1210 /* Prime the keys for hashing */
1211 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1212 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1213 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1214 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1215
1216 /*
1217 * Poll init-done after we write the register. Estimated times:
1218 * 10G: PBALLOC = 11b, timing is 60us
1219 * 1G: PBALLOC = 11b, timing is 600us
1220 * 100M: PBALLOC = 11b, timing is 6ms
1221 *
1222 * Multiple these timings by 4 if under full Rx load
1223 *
1224 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1225 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1226 * this might not finish in our poll time, but we can live with that
1227 * for now.
1228 */
1229
1230 /* Set the maximum length per hash bucket to 0xA filters */
1231 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1232
1233 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1234 IXGBE_WRITE_FLUSH(hw);
1235 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1236 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1237 IXGBE_FDIRCTRL_INIT_DONE)
1238 break;
1239 msleep(1);
1240 }
1241 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1242 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1243
1244 return 0;
1245}
1246
1247
1248/**
1249 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1250 * @stream: input bitstream to compute the hash on
1251 * @key: 32-bit hash key
1252 **/
7b25cdba
DS		 1253static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1254 u32 key)
ffff4772
PWJ		 1255{
1256 /*
1257 * The algorithm is as follows:
1258 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1259 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1260 * and A[n] x B[n] is bitwise AND between same length strings
1261 *
1262 * K[n] is 16 bits, defined as:
1263 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1264 * for n modulo 32 < 15, K[n] =
1265 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1266 *
1267 * S[n] is 16 bits, defined as:
1268 * for n >= 15, S[n] = S[n:n - 15]
1269 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1270 *
1271 * To simplify for programming, the algorithm is implemented
1272 * in software this way:
1273 *
1274 * Key[31:0], Stream[335:0]
1275 *
1276 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1277 * int_key[350:0] = tmp_key[351:1]
1278 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1279 *
1280 * hash[15:0] = 0;
1281 * for (i = 0; i < 351; i++) {
1282 * if (int_key[i])
1283 * hash ^= int_stream[(i + 15):i];
1284 * }
1285 */
1286
1287 union {
1288 u64 fill[6];
1289 u32 key[11];
1290 u8 key_stream[44];
1291 } tmp_key;
1292
1293 u8 *stream = (u8 *)atr_input;
1294 u8 int_key[44]; /* upper-most bit unused */
1295 u8 hash_str[46]; /* upper-most 2 bits unused */
1296 u16 hash_result = 0;
1297 int i, j, k, h;
1298
1299 /*
1300 * Initialize the fill member to prevent warnings
1301 * on some compilers
1302 */
1303 tmp_key.fill[0] = 0;
1304
1305 /* First load the temporary key stream */
1306 for (i = 0; i < 6; i++) {
1307 u64 fillkey = ((u64)key << 32) | key;
1308 tmp_key.fill[i] = fillkey;
1309 }
1310
1311 /*
1312 * Set the interim key for the hashing. Bit 352 is unused, so we must
1313 * shift and compensate when building the key.
1314 */
1315
1316 int_key[0] = tmp_key.key_stream[0] >> 1;
1317 for (i = 1, j = 0; i < 44; i++) {
1318 unsigned int this_key = tmp_key.key_stream[j] << 7;
1319 j++;
1320 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1321 }
1322
1323 /*
1324 * Set the interim bit string for the hashing. Bits 368 and 367 are
1325 * unused, so shift and compensate when building the string.
1326 */
1327 hash_str[0] = (stream[40] & 0x7f) >> 1;
1328 for (i = 1, j = 40; i < 46; i++) {
1329 unsigned int this_str = stream[j] << 7;
1330 j++;
1331 if (j > 41)
1332 j = 0;
1333 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1334 }
1335
1336 /*
1337 * Now compute the hash. i is the index into hash_str, j is into our
1338 * key stream, k is counting the number of bits, and h interates within
1339 * each byte.
1340 */
1341 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1342 for (h = 0; h < 8 && k < 351; h++, k++) {
1343 if (int_key[j] & (1 << h)) {
1344 /*
1345 * Key bit is set, XOR in the current 16-bit
1346 * string. Example of processing:
1347 * h = 0,
1348 * tmp = (hash_str[i - 2] & 0 << 16) |
1349 * (hash_str[i - 1] & 0xff << 8) |
1350 * (hash_str[i] & 0xff >> 0)
1351 * So tmp = hash_str[15 + k:k], since the
1352 * i + 2 clause rolls off the 16-bit value
1353 * h = 7,
1354 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1355 * (hash_str[i - 1] & 0xff << 1) |
1356 * (hash_str[i] & 0x80 >> 7)
1357 */
1358 int tmp = (hash_str[i] >> h);
1359 tmp |= (hash_str[i - 1] << (8 - h));
1360 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1361 << (16 - h);
1362 hash_result ^= (u16)tmp;
1363 }
1364 }
1365 }
1366
1367 return hash_result;
1368}
1369
1370/**
1371 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1372 * @input: input stream to modify
1373 * @vlan: the VLAN id to load
1374 **/
1375s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1376{
1377 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1378 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1379
1380 return 0;
1381}
1382
1383/**
1384 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1385 * @input: input stream to modify
1386 * @src_addr: the IP address to load
1387 **/
1388s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1389{
1390 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1391 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1392 (src_addr >> 16) & 0xff;
1393 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1394 (src_addr >> 8) & 0xff;
1395 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1396
1397 return 0;
1398}
1399
1400/**
1401 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1402 * @input: input stream to modify
1403 * @dst_addr: the IP address to load
1404 **/
1405s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1406{
1407 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1408 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1409 (dst_addr >> 16) & 0xff;
1410 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1411 (dst_addr >> 8) & 0xff;
1412 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1413
1414 return 0;
1415}
1416
ffff4772
PWJ		 1417/**
1418 * ixgbe_atr_set_src_port_82599 - Sets the source port
1419 * @input: input stream to modify
1420 * @src_port: the source port to load
1421 **/
1422s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1423{
1424 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1425 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1426
1427 return 0;
1428}
1429
1430/**
1431 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1432 * @input: input stream to modify
1433 * @dst_port: the destination port to load
1434 **/
1435s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1436{
1437 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1438 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1439
1440 return 0;
1441}
1442
1443/**
1444 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1445 * @input: input stream to modify
1446 * @flex_bytes: the flexible bytes to load
1447 **/
1448s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1449{
1450 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1451 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1452
1453 return 0;
1454}
1455
ffff4772
PWJ		 1456/**
1457 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1458 * @input: input stream to modify
1459 * @l4type: the layer 4 type value to load
1460 **/
1461s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1462{
1463 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1464
1465 return 0;
1466}
1467
1468/**
1469 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1470 * @input: input stream to search
1471 * @vlan: the VLAN id to load
1472 **/
9a713e7c 1473static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
ffff4772
PWJ		 1474{
1475 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1476 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1477
1478 return 0;
1479}
1480
1481/**
1482 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1483 * @input: input stream to search
1484 * @src_addr: the IP address to load
1485 **/
7b25cdba
DS		 1486static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1487 u32 *src_addr)
ffff4772
PWJ		 1488{
1489 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1490 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1491 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1492 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1493
1494 return 0;
1495}
1496
1497/**
1498 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1499 * @input: input stream to search
1500 * @dst_addr: the IP address to load
1501 **/
7b25cdba
DS		 1502static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1503 u32 *dst_addr)
ffff4772
PWJ		 1504{
1505 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1506 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1507 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1508 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1509
1510 return 0;
1511}
1512
1513/**
1514 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1515 * @input: input stream to search
1516 * @src_addr_1: the first 4 bytes of the IP address to load
1517 * @src_addr_2: the second 4 bytes of the IP address to load
1518 * @src_addr_3: the third 4 bytes of the IP address to load
1519 * @src_addr_4: the fourth 4 bytes of the IP address to load
1520 **/
7b25cdba
DS		 1521static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1522 u32 *src_addr_1, u32 *src_addr_2,
1523 u32 *src_addr_3, u32 *src_addr_4)
ffff4772
PWJ		 1524{
1525 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1526 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1527 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1528 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1529
1530 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1531 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1532 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1533 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1534
1535 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1536 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1537 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1538 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1539
1540 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1541 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1542 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1543 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1544
1545 return 0;
1546}
1547
ffff4772
PWJ		 1548/**
1549 * ixgbe_atr_get_src_port_82599 - Gets the source port
1550 * @input: input stream to modify
1551 * @src_port: the source port to load
1552 *
1553 * Even though the input is given in big-endian, the FDIRPORT registers
1554 * expect the ports to be programmed in little-endian. Hence the need to swap
1555 * endianness when retrieving the data. This can be confusing since the
1556 * internal hash engine expects it to be big-endian.
1557 **/
7b25cdba
DS		 1558static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1559 u16 *src_port)
ffff4772
PWJ		 1560{
1561 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1562 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1563
1564 return 0;
1565}
1566
1567/**
1568 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1569 * @input: input stream to modify
1570 * @dst_port: the destination port to load
1571 *
1572 * Even though the input is given in big-endian, the FDIRPORT registers
1573 * expect the ports to be programmed in little-endian. Hence the need to swap
1574 * endianness when retrieving the data. This can be confusing since the
1575 * internal hash engine expects it to be big-endian.
1576 **/
7b25cdba
DS		 1577static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1578 u16 *dst_port)
ffff4772
PWJ		 1579{
1580 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1581 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1582
1583 return 0;
1584}
1585
1586/**
1587 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1588 * @input: input stream to modify
1589 * @flex_bytes: the flexible bytes to load
1590 **/
7b25cdba
DS		 1591static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1592 u16 *flex_byte)
ffff4772
PWJ		 1593{
1594 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1595 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1596
1597 return 0;
1598}
1599
ffff4772
PWJ		 1600/**
1601 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1602 * @input: input stream to modify
1603 * @l4type: the layer 4 type value to load
1604 **/
7b25cdba
DS		 1605static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1606 u8 *l4type)
ffff4772
PWJ		 1607{
1608 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1609
1610 return 0;
1611}
1612
1613/**
1614 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1615 * @hw: pointer to hardware structure
1616 * @stream: input bitstream
1617 * @queue: queue index to direct traffic to
1618 **/
1619s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1620 struct ixgbe_atr_input *input,
1621 u8 queue)
1622{
1623 u64 fdirhashcmd;
1624 u64 fdircmd;
1625 u32 fdirhash;
1626 u16 bucket_hash, sig_hash;
1627 u8 l4type;
1628
1629 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1630 IXGBE_ATR_BUCKET_HASH_KEY);
1631
1632 /* bucket_hash is only 15 bits */
1633 bucket_hash &= IXGBE_ATR_HASH_MASK;
1634
1635 sig_hash = ixgbe_atr_compute_hash_82599(input,
1636 IXGBE_ATR_SIGNATURE_HASH_KEY);
1637
1638 /* Get the l4type in order to program FDIRCMD properly */
1639 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1640 ixgbe_atr_get_l4type_82599(input, &l4type);
1641
1642 /*
1643 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1644 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1645 */
1646 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1647
1648 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1649 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1650
1651 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1652 case IXGBE_ATR_L4TYPE_TCP:
1653 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1654 break;
1655 case IXGBE_ATR_L4TYPE_UDP:
1656 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1657 break;
1658 case IXGBE_ATR_L4TYPE_SCTP:
1659 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1660 break;
1661 default:
1662 hw_dbg(hw, "Error on l4type input\n");
1663 return IXGBE_ERR_CONFIG;
1664 }
1665
1666 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1667 fdircmd |= IXGBE_FDIRCMD_IPV6;
1668
1669 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1670 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1671
1672 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1673
1674 return 0;
1675}
1676
1677/**
1678 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1679 * @hw: pointer to hardware structure
1680 * @input: input bitstream
9a713e7c
PW		 1681 * @input_masks: bitwise masks for relevant fields
1682 * @soft_id: software index into the silicon hash tables for filter storage
ffff4772
PWJ		 1683 * @queue: queue index to direct traffic to
1684 *
1685 * Note that the caller to this function must lock before calling, since the
1686 * hardware writes must be protected from one another.
1687 **/
1688s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
9a713e7c
PW		 1689 struct ixgbe_atr_input *input,
1690 struct ixgbe_atr_input_masks *input_masks,
1691 u16 soft_id, u8 queue)
ffff4772
PWJ		 1692{
1693 u32 fdircmd = 0;
1694 u32 fdirhash;
9a713e7c 1695 u32 src_ipv4 = 0, dst_ipv4 = 0;
ffff4772
PWJ		 1696 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1697 u16 src_port, dst_port, vlan_id, flex_bytes;
1698 u16 bucket_hash;
1699 u8 l4type;
9a713e7c 1700 u8 fdirm = 0;
ffff4772
PWJ		 1701
1702 /* Get our input values */
1703 ixgbe_atr_get_l4type_82599(input, &l4type);
1704
1705 /*
1706 * Check l4type formatting, and bail out before we touch the hardware
1707 * if there's a configuration issue
1708 */
1709 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1710 case IXGBE_ATR_L4TYPE_TCP:
1711 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1712 break;
1713 case IXGBE_ATR_L4TYPE_UDP:
1714 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1715 break;
1716 case IXGBE_ATR_L4TYPE_SCTP:
1717 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1718 break;
1719 default:
1720 hw_dbg(hw, "Error on l4type input\n");
1721 return IXGBE_ERR_CONFIG;
1722 }
1723
1724 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1725 IXGBE_ATR_BUCKET_HASH_KEY);
1726
1727 /* bucket_hash is only 15 bits */
1728 bucket_hash &= IXGBE_ATR_HASH_MASK;
1729
1730 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
1731 ixgbe_atr_get_src_port_82599(input, &src_port);
1732 ixgbe_atr_get_dst_port_82599(input, &dst_port);
1733 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
1734
1735 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1736
1737 /* Now figure out if we're IPv4 or IPv6 */
1738 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
1739 /* IPv6 */
1740 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
1741 &src_ipv6_3, &src_ipv6_4);
1742
1743 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
1744 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
1745 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
1746 /* The last 4 bytes is the same register as IPv4 */
1747 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
1748
1749 fdircmd |= IXGBE_FDIRCMD_IPV6;
1750 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
1751 } else {
1752 /* IPv4 */
1753 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
1754 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
ffff4772
PWJ		 1755 }
1756
1757 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
1758 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
1759
1760 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
1761 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
1762 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
9a713e7c
PW		 1763 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
1764
1765 /*
be2902da
BH		 1766 * Program the relevant mask registers. L4type cannot be
1767 * masked out in this implementation.
9a713e7c
PW		 1768 *
1769 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1770 * point in time.
1771 */
be2902da
BH		 1772 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
1773 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
9a713e7c
PW		 1774
1775 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1776 case IXGBE_ATR_L4TYPE_TCP:
be2902da
BH		 1777 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, input_masks->src_port_mask);
1778 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
1779 (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
1780 (input_masks->dst_port_mask << 16)));
9a713e7c
PW		 1781 break;
1782 case IXGBE_ATR_L4TYPE_UDP:
be2902da
BH		 1783 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, input_masks->src_port_mask);
1784 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
1785 (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
1786 (input_masks->src_port_mask << 16)));
9a713e7c
PW		 1787 break;
1788 default:
1789 /* this already would have failed above */
1790 break;
1791 }
1792
1793 /* Program the last mask register, FDIRM */
be2902da 1794 if (input_masks->vlan_id_mask)
9a713e7c
PW		 1795 /* Mask both VLAN and VLANP - bits 0 and 1 */
1796 fdirm |= 0x3;
1797
be2902da 1798 if (input_masks->data_mask)
9a713e7c
PW		 1799 /* Flex bytes need masking, so mask the whole thing - bit 4 */
1800 fdirm |= 0x10;
1801
1802 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1803 fdirm |= 0x24;
1804
1805 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
ffff4772
PWJ		 1806
1807 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
1808 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
1809 fdircmd |= IXGBE_FDIRCMD_LAST;
1810 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
1811 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1812
1813 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1814 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1815
1816 return 0;
1817}
11afc1b1
PW		 1818/**
1819 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1820 * @hw: pointer to hardware structure
1821 * @reg: analog register to read
1822 * @val: read value
1823 *
1824 * Performs read operation to Omer analog register specified.
1825 **/
7b25cdba 1826static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
11afc1b1
PW		 1827{
1828 u32 core_ctl;
1829
1830 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1831 (reg << 8));
1832 IXGBE_WRITE_FLUSH(hw);
1833 udelay(10);
1834 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1835 *val = (u8)core_ctl;
1836
1837 return 0;
1838}
1839
1840/**
1841 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1842 * @hw: pointer to hardware structure
1843 * @reg: atlas register to write
1844 * @val: value to write
1845 *
1846 * Performs write operation to Omer analog register specified.
1847 **/
7b25cdba 1848static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
11afc1b1
PW		 1849{
1850 u32 core_ctl;
1851
1852 core_ctl = (reg << 8) | val;
1853 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1854 IXGBE_WRITE_FLUSH(hw);
1855 udelay(10);
1856
1857 return 0;
1858}
1859
1860/**
1861 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1862 * @hw: pointer to hardware structure
1863 *
1864 * Starts the hardware using the generic start_hw function.
1865 * Then performs device-specific:
1866 * Clears the rate limiter registers.
1867 **/
7b25cdba 1868static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1869{
1870 u32 q_num;
794caeb2 1871 s32 ret_val;
11afc1b1 1872
794caeb2 1873 ret_val = ixgbe_start_hw_generic(hw);
11afc1b1
PW		 1874
1875 /* Clear the rate limiters */
1876 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1877 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1878 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1879 }
1880 IXGBE_WRITE_FLUSH(hw);
1881
50ac58ba
PWJ		 1882 /* We need to run link autotry after the driver loads */
1883 hw->mac.autotry_restart = true;
1884
794caeb2
PWJ		 1885 if (ret_val == 0)
1886 ret_val = ixgbe_verify_fw_version_82599(hw);
1887
1888 return ret_val;
11afc1b1
PW		 1889}
1890
1891/**
1892 * ixgbe_identify_phy_82599 - Get physical layer module
1893 * @hw: pointer to hardware structure
1894 *
1895 * Determines the physical layer module found on the current adapter.
1896 **/
7b25cdba 1897static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1898{
1899 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1900 status = ixgbe_identify_phy_generic(hw);
1901 if (status != 0)
1902 status = ixgbe_identify_sfp_module_generic(hw);
1903 return status;
1904}
1905
1906/**
1907 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1908 * @hw: pointer to hardware structure
1909 *
1910 * Determines physical layer capabilities of the current configuration.
1911 **/
7b25cdba 1912static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
11afc1b1
PW		 1913{
1914 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
04193058
PWJ		 1915 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1916 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1917 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1918 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1919 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1920 u16 ext_ability = 0;
1339b9e9 1921 u8 comp_codes_10g = 0;
cb836a97 1922 u8 comp_codes_1g = 0;
11afc1b1 1923
04193058
PWJ		 1924 hw->phy.ops.identify(hw);
1925
1926 if (hw->phy.type == ixgbe_phy_tn ||
1927 hw->phy.type == ixgbe_phy_cu_unknown) {
6b73e10d
BH		 1928 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1929 &ext_ability);
1930 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
04193058 1931 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
6b73e10d 1932 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
04193058 1933 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
6b73e10d 1934 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
04193058
PWJ		 1935 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1936 goto out;
1937 }
1938
1939 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1940 case IXGBE_AUTOC_LMS_1G_AN:
1941 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1942 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1943 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1944 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1945 goto out;
1946 } else
1947 /* SFI mode so read SFP module */
1948 goto sfp_check;
11afc1b1 1949 break;
04193058
PWJ		 1950 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1951 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1952 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1953 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1954 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1fcf03e6
PWJ		 1955 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1956 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
04193058
PWJ		 1957 goto out;
1958 break;
1959 case IXGBE_AUTOC_LMS_10G_SERIAL:
1960 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1961 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1962 goto out;
1963 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1964 goto sfp_check;
1965 break;
1966 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1967 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1968 if (autoc & IXGBE_AUTOC_KX_SUPP)
1969 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1970 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1971 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1972 if (autoc & IXGBE_AUTOC_KR_SUPP)
1973 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1974 goto out;
1975 break;
1976 default:
1977 goto out;
1978 break;
1979 }
11afc1b1 1980
04193058
PWJ		 1981sfp_check:
1982 /* SFP check must be done last since DA modules are sometimes used to
1983 * test KR mode - we need to id KR mode correctly before SFP module.
1984 * Call identify_sfp because the pluggable module may have changed */
1985 hw->phy.ops.identify_sfp(hw);
1986 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1987 goto out;
1988
1989 switch (hw->phy.type) {
ea0a04df
DS		 1990 case ixgbe_phy_sfp_passive_tyco:
1991 case ixgbe_phy_sfp_passive_unknown:
04193058
PWJ		 1992 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1993 break;
ea0a04df
DS		 1994 case ixgbe_phy_sfp_ftl_active:
1995 case ixgbe_phy_sfp_active_unknown:
1996 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1997 break;
04193058
PWJ		 1998 case ixgbe_phy_sfp_avago:
1999 case ixgbe_phy_sfp_ftl:
2000 case ixgbe_phy_sfp_intel:
2001 case ixgbe_phy_sfp_unknown:
cb836a97
DS		 2002 hw->phy.ops.read_i2c_eeprom(hw,
2003 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
04193058
PWJ		 2004 hw->phy.ops.read_i2c_eeprom(hw,
2005 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2006 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
11afc1b1 2007 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
04193058 2008 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
11afc1b1 2009 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
cb836a97
DS		 2010 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2011 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
11afc1b1
PW		 2012 break;
2013 default:
11afc1b1
PW		 2014 break;
2015 }
2016
04193058 2017out:
11afc1b1
PW		 2018 return physical_layer;
2019}
2020
2021/**
2022 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2023 * @hw: pointer to hardware structure
2024 * @regval: register value to write to RXCTRL
2025 *
2026 * Enables the Rx DMA unit for 82599
2027 **/
7b25cdba 2028static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
11afc1b1
PW		 2029{
2030#define IXGBE_MAX_SECRX_POLL 30
2031 int i;
2032 int secrxreg;
2033
2034 /*
2035 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2036 * If traffic is incoming before we enable the Rx unit, it could hang
2037 * the Rx DMA unit. Therefore, make sure the security engine is
2038 * completely disabled prior to enabling the Rx unit.
2039 */
2040 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2041 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2042 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2043 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2044 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2045 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2046 break;
2047 else
2048 udelay(10);
2049 }
2050
2051 /* For informational purposes only */
2052 if (i >= IXGBE_MAX_SECRX_POLL)
2053 hw_dbg(hw, "Rx unit being enabled before security "
2054 "path fully disabled. Continuing with init.\n");
2055
2056 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2057 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2058 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2059 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2060 IXGBE_WRITE_FLUSH(hw);
2061
2062 return 0;
2063}
2064
04193058
PWJ		 2065/**
2066 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2067 * @hw: pointer to hardware structure
2068 * @device_caps: the EEPROM word with the extra device capabilities
2069 *
2070 * This function will read the EEPROM location for the device capabilities,
2071 * and return the word through device_caps.
2072 **/
7b25cdba 2073static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
04193058
PWJ		 2074{
2075 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2076
2077 return 0;
2078}
2079
794caeb2
PWJ		 2080/**
2081 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2082 * @hw: pointer to hardware structure
2083 *
2084 * Verifies that installed the firmware version is 0.6 or higher
2085 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2086 *
2087 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2088 * if the FW version is not supported.
2089 **/
2090static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2091{
2092 s32 status = IXGBE_ERR_EEPROM_VERSION;
2093 u16 fw_offset, fw_ptp_cfg_offset;
2094 u16 fw_version = 0;
2095
2096 /* firmware check is only necessary for SFI devices */
2097 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2098 status = 0;
2099 goto fw_version_out;
2100 }
2101
2102 /* get the offset to the Firmware Module block */
2103 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2104
2105 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2106 goto fw_version_out;
2107
2108 /* get the offset to the Pass Through Patch Configuration block */
2109 hw->eeprom.ops.read(hw, (fw_offset +
2110 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2111 &fw_ptp_cfg_offset);
2112
2113 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2114 goto fw_version_out;
2115
2116 /* get the firmware version */
2117 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2118 IXGBE_FW_PATCH_VERSION_4),
2119 &fw_version);
2120
2121 if (fw_version > 0x5)
2122 status = 0;
2123
2124fw_version_out:
2125 return status;
2126}
2127
383ff34b
YZ		 2128/**
2129 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2130 * the EEPROM
2131 * @hw: pointer to hardware structure
2132 * @wwnn_prefix: the alternative WWNN prefix
2133 * @wwpn_prefix: the alternative WWPN prefix
2134 *
2135 * This function will read the EEPROM from the alternative SAN MAC address
2136 * block to check the support for the alternative WWNN/WWPN prefix support.
2137 **/
2138static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2139 u16 *wwpn_prefix)
2140{
2141 u16 offset, caps;
2142 u16 alt_san_mac_blk_offset;
2143
2144 /* clear output first */
2145 *wwnn_prefix = 0xFFFF;
2146 *wwpn_prefix = 0xFFFF;
2147
2148 /* check if alternative SAN MAC is supported */
2149 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2150 &alt_san_mac_blk_offset);
2151
2152 if ((alt_san_mac_blk_offset == 0) ||
2153 (alt_san_mac_blk_offset == 0xFFFF))
2154 goto wwn_prefix_out;
2155
2156 /* check capability in alternative san mac address block */
2157 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2158 hw->eeprom.ops.read(hw, offset, &caps);
2159 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2160 goto wwn_prefix_out;
2161
2162 /* get the corresponding prefix for WWNN/WWPN */
2163 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2164 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2165
2166 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2167 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2168
2169wwn_prefix_out:
2170 return 0;
2171}
2172
11afc1b1
PW		 2173static struct ixgbe_mac_operations mac_ops_82599 = {
2174 .init_hw = &ixgbe_init_hw_generic,
2175 .reset_hw = &ixgbe_reset_hw_82599,
2176 .start_hw = &ixgbe_start_hw_82599,
2177 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2178 .get_media_type = &ixgbe_get_media_type_82599,
2179 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2180 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2181 .get_mac_addr = &ixgbe_get_mac_addr_generic,
21ce849b 2182 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
04193058 2183 .get_device_caps = &ixgbe_get_device_caps_82599,
383ff34b 2184 .get_wwn_prefix = &ixgbe_get_wwn_prefix_82599,
11afc1b1
PW		 2185 .stop_adapter = &ixgbe_stop_adapter_generic,
2186 .get_bus_info = &ixgbe_get_bus_info_generic,
2187 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2188 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2189 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2190 .setup_link = &ixgbe_setup_mac_link_82599,
21ce849b 2191 .check_link = &ixgbe_check_mac_link_generic,
11afc1b1
PW		 2192 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2193 .led_on = &ixgbe_led_on_generic,
2194 .led_off = &ixgbe_led_off_generic,
87c12017
PW		 2195 .blink_led_start = &ixgbe_blink_led_start_generic,
2196 .blink_led_stop = &ixgbe_blink_led_stop_generic,
11afc1b1
PW		 2197 .set_rar = &ixgbe_set_rar_generic,
2198 .clear_rar = &ixgbe_clear_rar_generic,
21ce849b
MC		 2199 .set_vmdq = &ixgbe_set_vmdq_generic,
2200 .clear_vmdq = &ixgbe_clear_vmdq_generic,
11afc1b1
PW		 2201 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2202 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2203 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2204 .enable_mc = &ixgbe_enable_mc_generic,
2205 .disable_mc = &ixgbe_disable_mc_generic,
21ce849b
MC		 2206 .clear_vfta = &ixgbe_clear_vfta_generic,
2207 .set_vfta = &ixgbe_set_vfta_generic,
2208 .fc_enable = &ixgbe_fc_enable_generic,
2209 .init_uta_tables = &ixgbe_init_uta_tables_generic,
11afc1b1
PW		 2210 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2211};
2212
2213static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2214 .init_params = &ixgbe_init_eeprom_params_generic,
21ce849b 2215 .read = &ixgbe_read_eerd_generic,
11afc1b1
PW		 2216 .write = &ixgbe_write_eeprom_generic,
2217 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2218 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2219};
2220
2221static struct ixgbe_phy_operations phy_ops_82599 = {
2222 .identify = &ixgbe_identify_phy_82599,
2223 .identify_sfp = &ixgbe_identify_sfp_module_generic,
21ce849b 2224 .init = &ixgbe_init_phy_ops_82599,
11afc1b1
PW		 2225 .reset = &ixgbe_reset_phy_generic,
2226 .read_reg = &ixgbe_read_phy_reg_generic,
2227 .write_reg = &ixgbe_write_phy_reg_generic,
2228 .setup_link = &ixgbe_setup_phy_link_generic,
2229 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2230 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2231 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2232 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2233 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
119fc60a 2234 .check_overtemp = &ixgbe_tn_check_overtemp,
11afc1b1
PW		 2235};
2236
2237struct ixgbe_info ixgbe_82599_info = {
2238 .mac = ixgbe_mac_82599EB,
2239 .get_invariants = &ixgbe_get_invariants_82599,
2240 .mac_ops = &mac_ops_82599,
2241 .eeprom_ops = &eeprom_ops_82599,
2242 .phy_ops = &phy_ops_82599,
096a58fd 2243 .mbx_ops = &mbx_ops_82599,
11afc1b1 2244};
Linux kernel - Deliverables
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