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ixgbevf: Fix IPv6 GSO type checks
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
ccffad25
JP		 31#include <linux/list.h>
32#include <linux/netdevice.h>
9a799d71 33
11afc1b1 34#include "ixgbe.h"
9a799d71
AK		 35#include "ixgbe_common.h"
36#include "ixgbe_phy.h"
37
9a799d71 38static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
c44ade9e 39static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 40static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 42static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
45 u16 count);
46static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 50static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
51
c44ade9e
JB		 52static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
53static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
9a799d71 54static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
c44ade9e 55static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
7b25cdba 56static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
9a799d71
AK		 57
58/**
c44ade9e 59 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 60 * @hw: pointer to hardware structure
61 *
62 * Starts the hardware by filling the bus info structure and media type, clears
63 * all on chip counters, initializes receive address registers, multicast
64 * table, VLAN filter table, calls routine to set up link and flow control
65 * settings, and leaves transmit and receive units disabled and uninitialized
66 **/
c44ade9e 67s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 68{
69 u32 ctrl_ext;
70
71 /* Set the media type */
72 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
73
74 /* Identify the PHY */
c44ade9e 75 hw->phy.ops.identify(hw);
9a799d71 76
9a799d71 77 /* Clear the VLAN filter table */
c44ade9e 78 hw->mac.ops.clear_vfta(hw);
9a799d71 79
9a799d71 80 /* Clear statistics registers */
c44ade9e 81 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 82
83 /* Set No Snoop Disable */
84 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
85 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
86 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 87 IXGBE_WRITE_FLUSH(hw);
9a799d71 88
620fa036
MC		 89 /* Setup flow control */
90 ixgbe_setup_fc(hw, 0);
91
9a799d71
AK		 92 /* Clear adapter stopped flag */
93 hw->adapter_stopped = false;
94
95 return 0;
96}
97
98/**
c44ade9e 99 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 100 * @hw: pointer to hardware structure
101 *
c44ade9e 102 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 103 * structure and media type, clears all on chip counters, initializes receive
104 * address registers, multicast table, VLAN filter table, calls routine to set
105 * up link and flow control settings, and leaves transmit and receive units
106 * disabled and uninitialized
107 **/
c44ade9e 108s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 109{
794caeb2
PWJ		 110 s32 status;
111
9a799d71 112 /* Reset the hardware */
794caeb2 113 status = hw->mac.ops.reset_hw(hw);
9a799d71 114
794caeb2
PWJ		 115 if (status == 0) {
116 /* Start the HW */
117 status = hw->mac.ops.start_hw(hw);
118 }
9a799d71 119
794caeb2 120 return status;
9a799d71
AK		 121}
122
123/**
c44ade9e 124 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 125 * @hw: pointer to hardware structure
126 *
127 * Clears all hardware statistics counters by reading them from the hardware
128 * Statistics counters are clear on read.
129 **/
c44ade9e 130s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 131{
132 u16 i = 0;
133
134 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
135 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
136 IXGBE_READ_REG(hw, IXGBE_ERRBC);
137 IXGBE_READ_REG(hw, IXGBE_MSPDC);
138 for (i = 0; i < 8; i++)
139 IXGBE_READ_REG(hw, IXGBE_MPC(i));
140
141 IXGBE_READ_REG(hw, IXGBE_MLFC);
142 IXGBE_READ_REG(hw, IXGBE_MRFC);
143 IXGBE_READ_REG(hw, IXGBE_RLEC);
144 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
145 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
146 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
147 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
148
149 for (i = 0; i < 8; i++) {
150 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
151 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
152 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
153 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
154 }
155
156 IXGBE_READ_REG(hw, IXGBE_PRC64);
157 IXGBE_READ_REG(hw, IXGBE_PRC127);
158 IXGBE_READ_REG(hw, IXGBE_PRC255);
159 IXGBE_READ_REG(hw, IXGBE_PRC511);
160 IXGBE_READ_REG(hw, IXGBE_PRC1023);
161 IXGBE_READ_REG(hw, IXGBE_PRC1522);
162 IXGBE_READ_REG(hw, IXGBE_GPRC);
163 IXGBE_READ_REG(hw, IXGBE_BPRC);
164 IXGBE_READ_REG(hw, IXGBE_MPRC);
165 IXGBE_READ_REG(hw, IXGBE_GPTC);
166 IXGBE_READ_REG(hw, IXGBE_GORCL);
167 IXGBE_READ_REG(hw, IXGBE_GORCH);
168 IXGBE_READ_REG(hw, IXGBE_GOTCL);
169 IXGBE_READ_REG(hw, IXGBE_GOTCH);
170 for (i = 0; i < 8; i++)
171 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
172 IXGBE_READ_REG(hw, IXGBE_RUC);
173 IXGBE_READ_REG(hw, IXGBE_RFC);
174 IXGBE_READ_REG(hw, IXGBE_ROC);
175 IXGBE_READ_REG(hw, IXGBE_RJC);
176 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
177 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
178 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
179 IXGBE_READ_REG(hw, IXGBE_TORL);
180 IXGBE_READ_REG(hw, IXGBE_TORH);
181 IXGBE_READ_REG(hw, IXGBE_TPR);
182 IXGBE_READ_REG(hw, IXGBE_TPT);
183 IXGBE_READ_REG(hw, IXGBE_PTC64);
184 IXGBE_READ_REG(hw, IXGBE_PTC127);
185 IXGBE_READ_REG(hw, IXGBE_PTC255);
186 IXGBE_READ_REG(hw, IXGBE_PTC511);
187 IXGBE_READ_REG(hw, IXGBE_PTC1023);
188 IXGBE_READ_REG(hw, IXGBE_PTC1522);
189 IXGBE_READ_REG(hw, IXGBE_MPTC);
190 IXGBE_READ_REG(hw, IXGBE_BPTC);
191 for (i = 0; i < 16; i++) {
192 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
193 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
194 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
195 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
196 }
197
198 return 0;
199}
200
201/**
c44ade9e
JB		 202 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
203 * @hw: pointer to hardware structure
204 * @pba_num: stores the part number from the EEPROM
205 *
206 * Reads the part number from the EEPROM.
207 **/
208s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
209{
210 s32 ret_val;
211 u16 data;
212
213 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
214 if (ret_val) {
215 hw_dbg(hw, "NVM Read Error\n");
216 return ret_val;
217 }
218 *pba_num = (u32)(data << 16);
219
220 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
221 if (ret_val) {
222 hw_dbg(hw, "NVM Read Error\n");
223 return ret_val;
224 }
225 *pba_num |= data;
226
227 return 0;
228}
229
230/**
231 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 232 * @hw: pointer to hardware structure
233 * @mac_addr: Adapter MAC address
234 *
235 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
236 * A reset of the adapter must be performed prior to calling this function
237 * in order for the MAC address to have been loaded from the EEPROM into RAR0
238 **/
c44ade9e 239s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 240{
241 u32 rar_high;
242 u32 rar_low;
243 u16 i;
244
245 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
246 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
247
248 for (i = 0; i < 4; i++)
249 mac_addr[i] = (u8)(rar_low >> (i*8));
250
251 for (i = 0; i < 2; i++)
252 mac_addr[i+4] = (u8)(rar_high >> (i*8));
253
254 return 0;
255}
256
11afc1b1
PW		 257/**
258 * ixgbe_get_bus_info_generic - Generic set PCI bus info
259 * @hw: pointer to hardware structure
260 *
261 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
262 **/
263s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
264{
265 struct ixgbe_adapter *adapter = hw->back;
266 struct ixgbe_mac_info *mac = &hw->mac;
267 u16 link_status;
268
269 hw->bus.type = ixgbe_bus_type_pci_express;
270
271 /* Get the negotiated link width and speed from PCI config space */
272 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
273 &link_status);
274
275 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
276 case IXGBE_PCI_LINK_WIDTH_1:
277 hw->bus.width = ixgbe_bus_width_pcie_x1;
278 break;
279 case IXGBE_PCI_LINK_WIDTH_2:
280 hw->bus.width = ixgbe_bus_width_pcie_x2;
281 break;
282 case IXGBE_PCI_LINK_WIDTH_4:
283 hw->bus.width = ixgbe_bus_width_pcie_x4;
284 break;
285 case IXGBE_PCI_LINK_WIDTH_8:
286 hw->bus.width = ixgbe_bus_width_pcie_x8;
287 break;
288 default:
289 hw->bus.width = ixgbe_bus_width_unknown;
290 break;
291 }
292
293 switch (link_status & IXGBE_PCI_LINK_SPEED) {
294 case IXGBE_PCI_LINK_SPEED_2500:
295 hw->bus.speed = ixgbe_bus_speed_2500;
296 break;
297 case IXGBE_PCI_LINK_SPEED_5000:
298 hw->bus.speed = ixgbe_bus_speed_5000;
299 break;
300 default:
301 hw->bus.speed = ixgbe_bus_speed_unknown;
302 break;
303 }
304
305 mac->ops.set_lan_id(hw);
306
307 return 0;
308}
309
310/**
311 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
312 * @hw: pointer to the HW structure
313 *
314 * Determines the LAN function id by reading memory-mapped registers
315 * and swaps the port value if requested.
316 **/
317void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
318{
319 struct ixgbe_bus_info *bus = &hw->bus;
320 u32 reg;
321
322 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
323 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
324 bus->lan_id = bus->func;
325
326 /* check for a port swap */
327 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
328 if (reg & IXGBE_FACTPS_LFS)
329 bus->func ^= 0x1;
330}
331
9a799d71 332/**
c44ade9e 333 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 334 * @hw: pointer to hardware structure
335 *
336 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
337 * disables transmit and receive units. The adapter_stopped flag is used by
338 * the shared code and drivers to determine if the adapter is in a stopped
339 * state and should not touch the hardware.
340 **/
c44ade9e 341s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71
AK		 342{
343 u32 number_of_queues;
344 u32 reg_val;
345 u16 i;
346
347 /*
348 * Set the adapter_stopped flag so other driver functions stop touching
349 * the hardware
350 */
351 hw->adapter_stopped = true;
352
353 /* Disable the receive unit */
354 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
355 reg_val &= ~(IXGBE_RXCTRL_RXEN);
356 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
c44ade9e 357 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 358 msleep(2);
359
360 /* Clear interrupt mask to stop from interrupts being generated */
361 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
362
363 /* Clear any pending interrupts */
364 IXGBE_READ_REG(hw, IXGBE_EICR);
365
366 /* Disable the transmit unit. Each queue must be disabled. */
c44ade9e 367 number_of_queues = hw->mac.max_tx_queues;
9a799d71
AK		 368 for (i = 0; i < number_of_queues; i++) {
369 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
370 if (reg_val & IXGBE_TXDCTL_ENABLE) {
371 reg_val &= ~IXGBE_TXDCTL_ENABLE;
372 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
373 }
374 }
375
c44ade9e
JB		 376 /*
377 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
378 * access and verify no pending requests
379 */
380 if (ixgbe_disable_pcie_master(hw) != 0)
381 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
382
9a799d71
AK		 383 return 0;
384}
385
386/**
c44ade9e 387 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 388 * @hw: pointer to hardware structure
389 * @index: led number to turn on
390 **/
c44ade9e 391s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 392{
393 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
394
395 /* To turn on the LED, set mode to ON. */
396 led_reg &= ~IXGBE_LED_MODE_MASK(index);
397 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
398 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 399 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 400
401 return 0;
402}
403
404/**
c44ade9e 405 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 406 * @hw: pointer to hardware structure
407 * @index: led number to turn off
408 **/
c44ade9e 409s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 410{
411 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
412
413 /* To turn off the LED, set mode to OFF. */
414 led_reg &= ~IXGBE_LED_MODE_MASK(index);
415 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
416 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 417 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 418
419 return 0;
420}
421
9a799d71 422/**
c44ade9e 423 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 424 * @hw: pointer to hardware structure
425 *
426 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
427 * ixgbe_hw struct in order to set up EEPROM access.
428 **/
c44ade9e 429s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 430{
431 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
432 u32 eec;
433 u16 eeprom_size;
434
435 if (eeprom->type == ixgbe_eeprom_uninitialized) {
436 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 437 /* Set default semaphore delay to 10ms which is a well
438 * tested value */
439 eeprom->semaphore_delay = 10;
9a799d71
AK		 440
441 /*
442 * Check for EEPROM present first.
443 * If not present leave as none
444 */
445 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
446 if (eec & IXGBE_EEC_PRES) {
447 eeprom->type = ixgbe_eeprom_spi;
448
449 /*
450 * SPI EEPROM is assumed here. This code would need to
451 * change if a future EEPROM is not SPI.
452 */
453 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
454 IXGBE_EEC_SIZE_SHIFT);
455 eeprom->word_size = 1 << (eeprom_size +
456 IXGBE_EEPROM_WORD_SIZE_SHIFT);
457 }
458
459 if (eec & IXGBE_EEC_ADDR_SIZE)
460 eeprom->address_bits = 16;
461 else
462 eeprom->address_bits = 8;
463 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
464 "%d\n", eeprom->type, eeprom->word_size,
465 eeprom->address_bits);
466 }
467
468 return 0;
469}
470
11afc1b1
PW		 471/**
472 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
473 * @hw: pointer to hardware structure
474 * @offset: offset within the EEPROM to be written to
475 * @data: 16 bit word to be written to the EEPROM
476 *
477 * If ixgbe_eeprom_update_checksum is not called after this function, the
478 * EEPROM will most likely contain an invalid checksum.
479 **/
480s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
481{
482 s32 status;
483 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
484
485 hw->eeprom.ops.init_params(hw);
486
487 if (offset >= hw->eeprom.word_size) {
488 status = IXGBE_ERR_EEPROM;
489 goto out;
490 }
491
492 /* Prepare the EEPROM for writing */
493 status = ixgbe_acquire_eeprom(hw);
494
495 if (status == 0) {
496 if (ixgbe_ready_eeprom(hw) != 0) {
497 ixgbe_release_eeprom(hw);
498 status = IXGBE_ERR_EEPROM;
499 }
500 }
501
502 if (status == 0) {
503 ixgbe_standby_eeprom(hw);
504
505 /* Send the WRITE ENABLE command (8 bit opcode ) */
506 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
507 IXGBE_EEPROM_OPCODE_BITS);
508
509 ixgbe_standby_eeprom(hw);
510
511 /*
512 * Some SPI eeproms use the 8th address bit embedded in the
513 * opcode
514 */
515 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
516 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
517
518 /* Send the Write command (8-bit opcode + addr) */
519 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
520 IXGBE_EEPROM_OPCODE_BITS);
521 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
522 hw->eeprom.address_bits);
523
524 /* Send the data */
525 data = (data >> 8) | (data << 8);
526 ixgbe_shift_out_eeprom_bits(hw, data, 16);
527 ixgbe_standby_eeprom(hw);
528
529 msleep(hw->eeprom.semaphore_delay);
530 /* Done with writing - release the EEPROM */
531 ixgbe_release_eeprom(hw);
532 }
533
534out:
535 return status;
536}
537
9a799d71 538/**
c44ade9e
JB		 539 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
540 * @hw: pointer to hardware structure
541 * @offset: offset within the EEPROM to be read
542 * @data: read 16 bit value from EEPROM
543 *
544 * Reads 16 bit value from EEPROM through bit-bang method
545 **/
546s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
547 u16 *data)
548{
549 s32 status;
550 u16 word_in;
551 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
552
553 hw->eeprom.ops.init_params(hw);
554
555 if (offset >= hw->eeprom.word_size) {
556 status = IXGBE_ERR_EEPROM;
557 goto out;
558 }
559
560 /* Prepare the EEPROM for reading */
561 status = ixgbe_acquire_eeprom(hw);
562
563 if (status == 0) {
564 if (ixgbe_ready_eeprom(hw) != 0) {
565 ixgbe_release_eeprom(hw);
566 status = IXGBE_ERR_EEPROM;
567 }
568 }
569
570 if (status == 0) {
571 ixgbe_standby_eeprom(hw);
572
573 /*
574 * Some SPI eeproms use the 8th address bit embedded in the
575 * opcode
576 */
577 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
578 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
579
580 /* Send the READ command (opcode + addr) */
581 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
582 IXGBE_EEPROM_OPCODE_BITS);
583 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
584 hw->eeprom.address_bits);
585
586 /* Read the data. */
587 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
588 *data = (word_in >> 8) | (word_in << 8);
589
590 /* End this read operation */
591 ixgbe_release_eeprom(hw);
592 }
593
594out:
595 return status;
596}
597
598/**
599 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
9a799d71
AK		 600 * @hw: pointer to hardware structure
601 * @offset: offset of word in the EEPROM to read
602 * @data: word read from the EEPROM
603 *
604 * Reads a 16 bit word from the EEPROM using the EERD register.
605 **/
c44ade9e 606s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
9a799d71
AK		 607{
608 u32 eerd;
609 s32 status;
610
c44ade9e
JB		 611 hw->eeprom.ops.init_params(hw);
612
613 if (offset >= hw->eeprom.word_size) {
614 status = IXGBE_ERR_EEPROM;
615 goto out;
616 }
617
9a799d71
AK		 618 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
619 IXGBE_EEPROM_READ_REG_START;
620
621 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
622 status = ixgbe_poll_eeprom_eerd_done(hw);
623
624 if (status == 0)
625 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
b4617240 626 IXGBE_EEPROM_READ_REG_DATA);
9a799d71
AK		 627 else
628 hw_dbg(hw, "Eeprom read timed out\n");
629
c44ade9e 630out:
9a799d71
AK		 631 return status;
632}
633
634/**
635 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
636 * @hw: pointer to hardware structure
637 *
638 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
639 **/
640static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
641{
642 u32 i;
643 u32 reg;
644 s32 status = IXGBE_ERR_EEPROM;
645
646 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
647 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
648 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
649 status = 0;
650 break;
651 }
652 udelay(5);
653 }
654 return status;
655}
656
c44ade9e
JB		 657/**
658 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
659 * @hw: pointer to hardware structure
660 *
661 * Prepares EEPROM for access using bit-bang method. This function should
662 * be called before issuing a command to the EEPROM.
663 **/
664static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
665{
666 s32 status = 0;
fc1f2095 667 u32 eec = 0;
c44ade9e
JB		 668 u32 i;
669
670 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
671 status = IXGBE_ERR_SWFW_SYNC;
672
673 if (status == 0) {
674 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
675
676 /* Request EEPROM Access */
677 eec |= IXGBE_EEC_REQ;
678 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
679
680 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
681 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
682 if (eec & IXGBE_EEC_GNT)
683 break;
684 udelay(5);
685 }
686
687 /* Release if grant not acquired */
688 if (!(eec & IXGBE_EEC_GNT)) {
689 eec &= ~IXGBE_EEC_REQ;
690 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
691 hw_dbg(hw, "Could not acquire EEPROM grant\n");
692
693 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
694 status = IXGBE_ERR_EEPROM;
695 }
696 }
697
698 /* Setup EEPROM for Read/Write */
699 if (status == 0) {
700 /* Clear CS and SK */
701 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
702 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
703 IXGBE_WRITE_FLUSH(hw);
704 udelay(1);
705 }
706 return status;
707}
708
9a799d71
AK		 709/**
710 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
711 * @hw: pointer to hardware structure
712 *
713 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
714 **/
715static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
716{
717 s32 status = IXGBE_ERR_EEPROM;
718 u32 timeout;
719 u32 i;
720 u32 swsm;
721
722 /* Set timeout value based on size of EEPROM */
723 timeout = hw->eeprom.word_size + 1;
724
725 /* Get SMBI software semaphore between device drivers first */
726 for (i = 0; i < timeout; i++) {
727 /*
728 * If the SMBI bit is 0 when we read it, then the bit will be
729 * set and we have the semaphore
730 */
731 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
732 if (!(swsm & IXGBE_SWSM_SMBI)) {
733 status = 0;
734 break;
735 }
736 msleep(1);
737 }
738
739 /* Now get the semaphore between SW/FW through the SWESMBI bit */
740 if (status == 0) {
741 for (i = 0; i < timeout; i++) {
742 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
743
744 /* Set the SW EEPROM semaphore bit to request access */
745 swsm |= IXGBE_SWSM_SWESMBI;
746 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
747
748 /*
749 * If we set the bit successfully then we got the
750 * semaphore.
751 */
752 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
753 if (swsm & IXGBE_SWSM_SWESMBI)
754 break;
755
756 udelay(50);
757 }
758
759 /*
760 * Release semaphores and return error if SW EEPROM semaphore
761 * was not granted because we don't have access to the EEPROM
762 */
763 if (i >= timeout) {
764 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
b4617240 765 "not granted.\n");
9a799d71
AK		 766 ixgbe_release_eeprom_semaphore(hw);
767 status = IXGBE_ERR_EEPROM;
768 }
769 }
770
771 return status;
772}
773
774/**
775 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
776 * @hw: pointer to hardware structure
777 *
778 * This function clears hardware semaphore bits.
779 **/
780static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
781{
782 u32 swsm;
783
784 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
785
786 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
787 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
788 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 789 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 790}
791
c44ade9e
JB		 792/**
793 * ixgbe_ready_eeprom - Polls for EEPROM ready
794 * @hw: pointer to hardware structure
795 **/
796static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
797{
798 s32 status = 0;
799 u16 i;
800 u8 spi_stat_reg;
801
802 /*
803 * Read "Status Register" repeatedly until the LSB is cleared. The
804 * EEPROM will signal that the command has been completed by clearing
805 * bit 0 of the internal status register. If it's not cleared within
806 * 5 milliseconds, then error out.
807 */
808 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
809 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
810 IXGBE_EEPROM_OPCODE_BITS);
811 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
812 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
813 break;
814
815 udelay(5);
816 ixgbe_standby_eeprom(hw);
817 };
818
819 /*
820 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
821 * devices (and only 0-5mSec on 5V devices)
822 */
823 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
824 hw_dbg(hw, "SPI EEPROM Status error\n");
825 status = IXGBE_ERR_EEPROM;
826 }
827
828 return status;
829}
830
831/**
832 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
833 * @hw: pointer to hardware structure
834 **/
835static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
836{
837 u32 eec;
838
839 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
840
841 /* Toggle CS to flush commands */
842 eec |= IXGBE_EEC_CS;
843 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
844 IXGBE_WRITE_FLUSH(hw);
845 udelay(1);
846 eec &= ~IXGBE_EEC_CS;
847 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
848 IXGBE_WRITE_FLUSH(hw);
849 udelay(1);
850}
851
852/**
853 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
854 * @hw: pointer to hardware structure
855 * @data: data to send to the EEPROM
856 * @count: number of bits to shift out
857 **/
858static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
859 u16 count)
860{
861 u32 eec;
862 u32 mask;
863 u32 i;
864
865 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
866
867 /*
868 * Mask is used to shift "count" bits of "data" out to the EEPROM
869 * one bit at a time. Determine the starting bit based on count
870 */
871 mask = 0x01 << (count - 1);
872
873 for (i = 0; i < count; i++) {
874 /*
875 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
876 * "1", and then raising and then lowering the clock (the SK
877 * bit controls the clock input to the EEPROM). A "0" is
878 * shifted out to the EEPROM by setting "DI" to "0" and then
879 * raising and then lowering the clock.
880 */
881 if (data & mask)
882 eec |= IXGBE_EEC_DI;
883 else
884 eec &= ~IXGBE_EEC_DI;
885
886 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
887 IXGBE_WRITE_FLUSH(hw);
888
889 udelay(1);
890
891 ixgbe_raise_eeprom_clk(hw, &eec);
892 ixgbe_lower_eeprom_clk(hw, &eec);
893
894 /*
895 * Shift mask to signify next bit of data to shift in to the
896 * EEPROM
897 */
898 mask = mask >> 1;
899 };
900
901 /* We leave the "DI" bit set to "0" when we leave this routine. */
902 eec &= ~IXGBE_EEC_DI;
903 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
904 IXGBE_WRITE_FLUSH(hw);
905}
906
907/**
908 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
909 * @hw: pointer to hardware structure
910 **/
911static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
912{
913 u32 eec;
914 u32 i;
915 u16 data = 0;
916
917 /*
918 * In order to read a register from the EEPROM, we need to shift
919 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
920 * the clock input to the EEPROM (setting the SK bit), and then reading
921 * the value of the "DO" bit. During this "shifting in" process the
922 * "DI" bit should always be clear.
923 */
924 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
925
926 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
927
928 for (i = 0; i < count; i++) {
929 data = data << 1;
930 ixgbe_raise_eeprom_clk(hw, &eec);
931
932 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
933
934 eec &= ~(IXGBE_EEC_DI);
935 if (eec & IXGBE_EEC_DO)
936 data |= 1;
937
938 ixgbe_lower_eeprom_clk(hw, &eec);
939 }
940
941 return data;
942}
943
944/**
945 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
946 * @hw: pointer to hardware structure
947 * @eec: EEC register's current value
948 **/
949static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
950{
951 /*
952 * Raise the clock input to the EEPROM
953 * (setting the SK bit), then delay
954 */
955 *eec = *eec | IXGBE_EEC_SK;
956 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
957 IXGBE_WRITE_FLUSH(hw);
958 udelay(1);
959}
960
961/**
962 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
963 * @hw: pointer to hardware structure
964 * @eecd: EECD's current value
965 **/
966static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
967{
968 /*
969 * Lower the clock input to the EEPROM (clearing the SK bit), then
970 * delay
971 */
972 *eec = *eec & ~IXGBE_EEC_SK;
973 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
974 IXGBE_WRITE_FLUSH(hw);
975 udelay(1);
976}
977
978/**
979 * ixgbe_release_eeprom - Release EEPROM, release semaphores
980 * @hw: pointer to hardware structure
981 **/
982static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
983{
984 u32 eec;
985
986 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
987
988 eec |= IXGBE_EEC_CS; /* Pull CS high */
989 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
990
991 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
992 IXGBE_WRITE_FLUSH(hw);
993
994 udelay(1);
995
996 /* Stop requesting EEPROM access */
997 eec &= ~IXGBE_EEC_REQ;
998 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
999
1000 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1001}
1002
9a799d71
AK		 1003/**
1004 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1005 * @hw: pointer to hardware structure
1006 **/
1007static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1008{
1009 u16 i;
1010 u16 j;
1011 u16 checksum = 0;
1012 u16 length = 0;
1013 u16 pointer = 0;
1014 u16 word = 0;
1015
1016 /* Include 0x0-0x3F in the checksum */
1017 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1018 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1019 hw_dbg(hw, "EEPROM read failed\n");
1020 break;
1021 }
1022 checksum += word;
1023 }
1024
1025 /* Include all data from pointers except for the fw pointer */
1026 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1027 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1028
1029 /* Make sure the pointer seems valid */
1030 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1031 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1032
1033 if (length != 0xFFFF && length != 0) {
1034 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1035 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1036 checksum += word;
1037 }
1038 }
1039 }
1040 }
1041
1042 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1043
1044 return checksum;
1045}
1046
1047/**
c44ade9e 1048 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1049 * @hw: pointer to hardware structure
1050 * @checksum_val: calculated checksum
1051 *
1052 * Performs checksum calculation and validates the EEPROM checksum. If the
1053 * caller does not need checksum_val, the value can be NULL.
1054 **/
c44ade9e
JB		 1055s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1056 u16 *checksum_val)
9a799d71
AK		 1057{
1058 s32 status;
1059 u16 checksum;
1060 u16 read_checksum = 0;
1061
1062 /*
1063 * Read the first word from the EEPROM. If this times out or fails, do
1064 * not continue or we could be in for a very long wait while every
1065 * EEPROM read fails
1066 */
c44ade9e 1067 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1068
1069 if (status == 0) {
1070 checksum = ixgbe_calc_eeprom_checksum(hw);
1071
c44ade9e 1072 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1073
1074 /*
1075 * Verify read checksum from EEPROM is the same as
1076 * calculated checksum
1077 */
1078 if (read_checksum != checksum)
1079 status = IXGBE_ERR_EEPROM_CHECKSUM;
1080
1081 /* If the user cares, return the calculated checksum */
1082 if (checksum_val)
1083 *checksum_val = checksum;
1084 } else {
1085 hw_dbg(hw, "EEPROM read failed\n");
1086 }
1087
1088 return status;
1089}
1090
c44ade9e
JB		 1091/**
1092 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1093 * @hw: pointer to hardware structure
1094 **/
1095s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1096{
1097 s32 status;
1098 u16 checksum;
1099
1100 /*
1101 * Read the first word from the EEPROM. If this times out or fails, do
1102 * not continue or we could be in for a very long wait while every
1103 * EEPROM read fails
1104 */
1105 status = hw->eeprom.ops.read(hw, 0, &checksum);
1106
1107 if (status == 0) {
1108 checksum = ixgbe_calc_eeprom_checksum(hw);
1109 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1110 checksum);
1111 } else {
1112 hw_dbg(hw, "EEPROM read failed\n");
1113 }
1114
1115 return status;
1116}
1117
9a799d71
AK		 1118/**
1119 * ixgbe_validate_mac_addr - Validate MAC address
1120 * @mac_addr: pointer to MAC address.
1121 *
1122 * Tests a MAC address to ensure it is a valid Individual Address
1123 **/
1124s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1125{
1126 s32 status = 0;
1127
1128 /* Make sure it is not a multicast address */
1129 if (IXGBE_IS_MULTICAST(mac_addr))
1130 status = IXGBE_ERR_INVALID_MAC_ADDR;
1131 /* Not a broadcast address */
1132 else if (IXGBE_IS_BROADCAST(mac_addr))
1133 status = IXGBE_ERR_INVALID_MAC_ADDR;
1134 /* Reject the zero address */
1135 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
c44ade9e 1136 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
9a799d71
AK		 1137 status = IXGBE_ERR_INVALID_MAC_ADDR;
1138
1139 return status;
1140}
1141
1142/**
c44ade9e 1143 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1144 * @hw: pointer to hardware structure
9a799d71 1145 * @index: Receive address register to write
c44ade9e
JB		 1146 * @addr: Address to put into receive address register
1147 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1148 * @enable_addr: set flag that address is active
1149 *
1150 * Puts an ethernet address into a receive address register.
1151 **/
c44ade9e
JB		 1152s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1153 u32 enable_addr)
9a799d71
AK		 1154{
1155 u32 rar_low, rar_high;
c44ade9e
JB		 1156 u32 rar_entries = hw->mac.num_rar_entries;
1157
1158 /* setup VMDq pool selection before this RAR gets enabled */
1159 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1160
c44ade9e
JB		 1161 /* Make sure we are using a valid rar index range */
1162 if (index < rar_entries) {
b4617240 1163 /*
c44ade9e
JB		 1164 * HW expects these in little endian so we reverse the byte
1165 * order from network order (big endian) to little endian
b4617240
PW		 1166 */
1167 rar_low = ((u32)addr[0] |
1168 ((u32)addr[1] << 8) |
1169 ((u32)addr[2] << 16) |
1170 ((u32)addr[3] << 24));
c44ade9e
JB		 1171 /*
1172 * Some parts put the VMDq setting in the extra RAH bits,
1173 * so save everything except the lower 16 bits that hold part
1174 * of the address and the address valid bit.
1175 */
1176 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1177 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1178 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1179
b4617240
PW		 1180 if (enable_addr != 0)
1181 rar_high |= IXGBE_RAH_AV;
9a799d71 1182
b4617240
PW		 1183 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1184 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1185 } else {
1186 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1187 }
1188
1189 return 0;
1190}
1191
1192/**
1193 * ixgbe_clear_rar_generic - Remove Rx address register
1194 * @hw: pointer to hardware structure
1195 * @index: Receive address register to write
1196 *
1197 * Clears an ethernet address from a receive address register.
1198 **/
1199s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1200{
1201 u32 rar_high;
1202 u32 rar_entries = hw->mac.num_rar_entries;
1203
1204 /* Make sure we are using a valid rar index range */
1205 if (index < rar_entries) {
1206 /*
1207 * Some parts put the VMDq setting in the extra RAH bits,
1208 * so save everything except the lower 16 bits that hold part
1209 * of the address and the address valid bit.
1210 */
1211 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1212 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1213
1214 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1215 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1216 } else {
1217 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1218 }
1219
1220 /* clear VMDq pool/queue selection for this RAR */
1221 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1222
1223 return 0;
1224}
1225
1226/**
c44ade9e
JB		 1227 * ixgbe_enable_rar - Enable Rx address register
1228 * @hw: pointer to hardware structure
1229 * @index: index into the RAR table
1230 *
1231 * Enables the select receive address register.
1232 **/
1233static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1234{
1235 u32 rar_high;
1236
1237 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1238 rar_high |= IXGBE_RAH_AV;
1239 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1240}
1241
1242/**
1243 * ixgbe_disable_rar - Disable Rx address register
1244 * @hw: pointer to hardware structure
1245 * @index: index into the RAR table
1246 *
1247 * Disables the select receive address register.
1248 **/
1249static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1250{
1251 u32 rar_high;
1252
1253 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1254 rar_high &= (~IXGBE_RAH_AV);
1255 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1256}
1257
1258/**
1259 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1260 * @hw: pointer to hardware structure
1261 *
1262 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1263 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1264 * the receiver is in reset when the routine is called.
1265 **/
c44ade9e 1266s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1267{
1268 u32 i;
2c5645cf 1269 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1270
1271 /*
1272 * If the current mac address is valid, assume it is a software override
1273 * to the permanent address.
1274 * Otherwise, use the permanent address from the eeprom.
1275 */
1276 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1277 IXGBE_ERR_INVALID_MAC_ADDR) {
1278 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1279 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1280
ce7194d8 1281 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1282 } else {
1283 /* Setup the receive address. */
1284 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1285 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1286
c44ade9e 1287 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71 1288 }
c44ade9e 1289 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1290
1291 hw->addr_ctrl.rar_used_count = 1;
1292
1293 /* Zero out the other receive addresses. */
c44ade9e 1294 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1295 for (i = 1; i < rar_entries; i++) {
1296 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1297 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1298 }
1299
1300 /* Clear the MTA */
1301 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1302 hw->addr_ctrl.mta_in_use = 0;
1303 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1304
1305 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1306 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1307 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1308
c44ade9e
JB		 1309 if (hw->mac.ops.init_uta_tables)
1310 hw->mac.ops.init_uta_tables(hw);
1311
9a799d71
AK		 1312 return 0;
1313}
1314
2c5645cf
CL		 1315/**
1316 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1317 * @hw: pointer to hardware structure
1318 * @addr: new address
1319 *
1320 * Adds it to unused receive address register or goes into promiscuous mode.
1321 **/
c44ade9e 1322static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2c5645cf
CL		 1323{
1324 u32 rar_entries = hw->mac.num_rar_entries;
1325 u32 rar;
1326
1327 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1328 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1329
1330 /*
1331 * Place this address in the RAR if there is room,
1332 * else put the controller into promiscuous mode
1333 */
1334 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1335 rar = hw->addr_ctrl.rar_used_count -
1336 hw->addr_ctrl.mc_addr_in_rar_count;
c44ade9e 1337 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2c5645cf
CL		 1338 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1339 hw->addr_ctrl.rar_used_count++;
1340 } else {
1341 hw->addr_ctrl.overflow_promisc++;
1342 }
1343
1344 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1345}
1346
1347/**
c44ade9e 1348 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2c5645cf 1349 * @hw: pointer to hardware structure
a00d2102 1350 * @uc_list: the list of new addresses
2c5645cf
CL		 1351 *
1352 * The given list replaces any existing list. Clears the secondary addrs from
1353 * receive address registers. Uses unused receive address registers for the
1354 * first secondary addresses, and falls back to promiscuous mode as needed.
1355 *
1356 * Drivers using secondary unicast addresses must set user_set_promisc when
1357 * manually putting the device into promiscuous mode.
1358 **/
ccffad25
JP		 1359s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
1360 struct list_head *uc_list)
2c5645cf 1361{
2c5645cf
CL		 1362 u32 i;
1363 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1364 u32 uc_addr_in_use;
1365 u32 fctrl;
ccffad25 1366 struct netdev_hw_addr *ha;
2c5645cf
CL		 1367
1368 /*
1369 * Clear accounting of old secondary address list,
1370 * don't count RAR[0]
1371 */
495dce12 1372 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2c5645cf
CL		 1373 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1374 hw->addr_ctrl.overflow_promisc = 0;
1375
1376 /* Zero out the other receive addresses */
91152c32
SN		 1377 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use + 1);
1378 for (i = 0; i < uc_addr_in_use; i++) {
1379 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
1380 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2c5645cf
CL		 1381 }
1382
1383 /* Add the new addresses */
ccffad25 1384 list_for_each_entry(ha, uc_list, list) {
2c5645cf 1385 hw_dbg(hw, " Adding the secondary addresses:\n");
ccffad25 1386 ixgbe_add_uc_addr(hw, ha->addr, 0);
2c5645cf
CL		 1387 }
1388
1389 if (hw->addr_ctrl.overflow_promisc) {
1390 /* enable promisc if not already in overflow or set by user */
1391 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1392 hw_dbg(hw, " Entering address overflow promisc mode\n");
1393 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1394 fctrl |= IXGBE_FCTRL_UPE;
1395 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1396 }
1397 } else {
1398 /* only disable if set by overflow, not by user */
1399 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1400 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1401 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1402 fctrl &= ~IXGBE_FCTRL_UPE;
1403 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1404 }
1405 }
1406
c44ade9e 1407 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
2c5645cf
CL		 1408 return 0;
1409}
1410
9a799d71
AK		 1411/**
1412 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1413 * @hw: pointer to hardware structure
1414 * @mc_addr: the multicast address
1415 *
1416 * Extracts the 12 bits, from a multicast address, to determine which
1417 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1418 * incoming rx multicast addresses, to determine the bit-vector to check in
1419 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1420 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1421 * to mc_filter_type.
1422 **/
1423static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1424{
1425 u32 vector = 0;
1426
1427 switch (hw->mac.mc_filter_type) {
b4617240 1428 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1429 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1430 break;
b4617240 1431 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1432 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1433 break;
b4617240 1434 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1435 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1436 break;
b4617240 1437 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1438 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1439 break;
b4617240 1440 default: /* Invalid mc_filter_type */
9a799d71
AK		 1441 hw_dbg(hw, "MC filter type param set incorrectly\n");
1442 break;
1443 }
1444
1445 /* vector can only be 12-bits or boundary will be exceeded */
1446 vector &= 0xFFF;
1447 return vector;
1448}
1449
1450/**
1451 * ixgbe_set_mta - Set bit-vector in multicast table
1452 * @hw: pointer to hardware structure
1453 * @hash_value: Multicast address hash value
1454 *
1455 * Sets the bit-vector in the multicast table.
1456 **/
1457static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1458{
1459 u32 vector;
1460 u32 vector_bit;
1461 u32 vector_reg;
1462 u32 mta_reg;
1463
1464 hw->addr_ctrl.mta_in_use++;
1465
1466 vector = ixgbe_mta_vector(hw, mc_addr);
1467 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1468
1469 /*
1470 * The MTA is a register array of 128 32-bit registers. It is treated
1471 * like an array of 4096 bits. We want to set bit
1472 * BitArray[vector_value]. So we figure out what register the bit is
1473 * in, read it, OR in the new bit, then write back the new value. The
1474 * register is determined by the upper 7 bits of the vector value and
1475 * the bit within that register are determined by the lower 5 bits of
1476 * the value.
1477 */
1478 vector_reg = (vector >> 5) & 0x7F;
1479 vector_bit = vector & 0x1F;
1480 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1481 mta_reg |= (1 << vector_bit);
1482 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1483}
1484
9a799d71 1485/**
c44ade9e 1486 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71
AK		 1487 * @hw: pointer to hardware structure
1488 * @mc_addr_list: the list of new multicast addresses
1489 * @mc_addr_count: number of addresses
2c5645cf 1490 * @next: iterator function to walk the multicast address list
9a799d71
AK		 1491 *
1492 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1493 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1494 * registers for the first multicast addresses, and hashes the rest into the
1495 * multicast table.
1496 **/
c44ade9e 1497s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
b4617240 1498 u32 mc_addr_count, ixgbe_mc_addr_itr next)
9a799d71
AK		 1499{
1500 u32 i;
2c5645cf 1501 u32 vmdq;
9a799d71
AK		 1502
1503 /*
1504 * Set the new number of MC addresses that we are being requested to
1505 * use.
1506 */
1507 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
9a799d71
AK		 1508 hw->addr_ctrl.mta_in_use = 0;
1509
9a799d71
AK		 1510 /* Clear the MTA */
1511 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1512 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1513 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1514
1515 /* Add the new addresses */
1516 for (i = 0; i < mc_addr_count; i++) {
1517 hw_dbg(hw, " Adding the multicast addresses:\n");
495dce12 1518 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
9a799d71
AK		 1519 }
1520
1521 /* Enable mta */
1522 if (hw->addr_ctrl.mta_in_use > 0)
1523 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 1524 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 1525
c44ade9e 1526 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1527 return 0;
1528}
1529
1530/**
c44ade9e 1531 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 1532 * @hw: pointer to hardware structure
1533 *
c44ade9e 1534 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 1535 **/
c44ade9e 1536s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1537{
c44ade9e
JB		 1538 u32 i;
1539 u32 rar_entries = hw->mac.num_rar_entries;
1540 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 1541
c44ade9e
JB		 1542 if (a->mc_addr_in_rar_count > 0)
1543 for (i = (rar_entries - a->mc_addr_in_rar_count);
1544 i < rar_entries; i++)
1545 ixgbe_enable_rar(hw, i);
9a799d71 1546
c44ade9e
JB		 1547 if (a->mta_in_use > 0)
1548 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1549 hw->mac.mc_filter_type);
9a799d71
AK		 1550
1551 return 0;
1552}
1553
1554/**
c44ade9e 1555 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 1556 * @hw: pointer to hardware structure
9a799d71 1557 *
c44ade9e 1558 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 1559 **/
c44ade9e 1560s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1561{
c44ade9e
JB		 1562 u32 i;
1563 u32 rar_entries = hw->mac.num_rar_entries;
1564 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 1565
c44ade9e
JB		 1566 if (a->mc_addr_in_rar_count > 0)
1567 for (i = (rar_entries - a->mc_addr_in_rar_count);
1568 i < rar_entries; i++)
1569 ixgbe_disable_rar(hw, i);
9a799d71 1570
c44ade9e
JB		 1571 if (a->mta_in_use > 0)
1572 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 1573
1574 return 0;
1575}
1576
11afc1b1 1577/**
620fa036 1578 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1
PW		 1579 * @hw: pointer to hardware structure
1580 * @packetbuf_num: packet buffer number (0-7)
1581 *
1582 * Enable flow control according to the current settings.
1583 **/
620fa036 1584s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1585{
1586 s32 ret_val = 0;
620fa036 1587 u32 mflcn_reg, fccfg_reg;
11afc1b1 1588 u32 reg;
70b77628
PWJ		 1589 u32 rx_pba_size;
1590
1591#ifdef CONFIG_DCB
1592 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1593 goto out;
1594
1595#endif /* CONFIG_DCB */
620fa036
MC		 1596 /* Negotiate the fc mode to use */
1597 ret_val = ixgbe_fc_autoneg(hw);
1598 if (ret_val)
1599 goto out;
11afc1b1 1600
620fa036 1601 /* Disable any previous flow control settings */
11afc1b1
PW		 1602 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1603 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1604
1605 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1606 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1607
1608 /*
1609 * The possible values of fc.current_mode are:
1610 * 0: Flow control is completely disabled
1611 * 1: Rx flow control is enabled (we can receive pause frames,
1612 * but not send pause frames).
bb3daa4a
PW		 1613 * 2: Tx flow control is enabled (we can send pause frames but
1614 * we do not support receiving pause frames).
11afc1b1 1615 * 3: Both Rx and Tx flow control (symmetric) are enabled.
bb3daa4a 1616 * 4: Priority Flow Control is enabled.
11afc1b1
PW		 1617 * other: Invalid.
1618 */
1619 switch (hw->fc.current_mode) {
1620 case ixgbe_fc_none:
620fa036
MC		 1621 /*
1622 * Flow control is disabled by software override or autoneg.
1623 * The code below will actually disable it in the HW.
1624 */
11afc1b1
PW		 1625 break;
1626 case ixgbe_fc_rx_pause:
1627 /*
1628 * Rx Flow control is enabled and Tx Flow control is
1629 * disabled by software override. Since there really
1630 * isn't a way to advertise that we are capable of RX
1631 * Pause ONLY, we will advertise that we support both
1632 * symmetric and asymmetric Rx PAUSE. Later, we will
1633 * disable the adapter's ability to send PAUSE frames.
1634 */
1635 mflcn_reg |= IXGBE_MFLCN_RFCE;
1636 break;
1637 case ixgbe_fc_tx_pause:
1638 /*
1639 * Tx Flow control is enabled, and Rx Flow control is
1640 * disabled by software override.
1641 */
1642 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1643 break;
1644 case ixgbe_fc_full:
1645 /* Flow control (both Rx and Tx) is enabled by SW override. */
1646 mflcn_reg |= IXGBE_MFLCN_RFCE;
1647 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1648 break;
bb3daa4a
PW		 1649#ifdef CONFIG_DCB
1650 case ixgbe_fc_pfc:
1651 goto out;
1652 break;
620fa036 1653#endif /* CONFIG_DCB */
11afc1b1
PW		 1654 default:
1655 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 1656 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 1657 goto out;
1658 break;
1659 }
1660
620fa036 1661 /* Set 802.3x based flow control settings. */
2132d381 1662 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 1663 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1664 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1665
70b77628
PWJ		 1666 reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
1667 /* Thresholds are different for link flow control when in DCB mode */
1668 if (reg & IXGBE_MTQC_RT_ENA) {
620fa036
MC		 1669 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1670
70b77628 1671 /* Always disable XON for LFC when in DCB mode */
620fa036
MC		 1672 reg = (rx_pba_size >> 5) & 0xFFE0;
1673 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
264857b8 1674
70b77628
PWJ		 1675 reg = (rx_pba_size >> 2) & 0xFFE0;
1676 if (hw->fc.current_mode & ixgbe_fc_tx_pause)
1677 reg |= IXGBE_FCRTH_FCEN;
1678 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
1679 } else {
1680 /*
1681 * Set up and enable Rx high/low water mark thresholds,
1682 * enable XON.
1683 */
1684 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1685 if (hw->fc.send_xon) {
1686 IXGBE_WRITE_REG(hw,
1687 IXGBE_FCRTL_82599(packetbuf_num),
1688 (hw->fc.low_water |
1689 IXGBE_FCRTL_XONE));
1690 } else {
1691 IXGBE_WRITE_REG(hw,
1692 IXGBE_FCRTL_82599(packetbuf_num),
1693 hw->fc.low_water);
1694 }
1695
1696 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1697 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1698 }
11afc1b1
PW		 1699 }
1700
1701 /* Configure pause time (2 TCs per register) */
70b77628 1702 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
11afc1b1
PW		 1703 if ((packetbuf_num & 1) == 0)
1704 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1705 else
1706 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1707 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1708
1709 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1710
1711out:
1712 return ret_val;
1713}
1714
0ecc061d
PWJ		 1715/**
1716 * ixgbe_fc_autoneg - Configure flow control
1717 * @hw: pointer to hardware structure
1718 *
620fa036
MC		 1719 * Compares our advertised flow control capabilities to those advertised by
1720 * our link partner, and determines the proper flow control mode to use.
0ecc061d
PWJ		 1721 **/
1722s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1723{
1724 s32 ret_val = 0;
620fa036
MC		 1725 ixgbe_link_speed speed;
1726 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
539e5f02 1727 u32 links2, anlp1_reg, autoc_reg, links;
620fa036 1728 bool link_up;
0ecc061d
PWJ		 1729
1730 /*
620fa036
MC		 1731 * AN should have completed when the cable was plugged in.
1732 * Look for reasons to bail out. Bail out if:
1733 * - FC autoneg is disabled, or if
539e5f02 1734 * - link is not up.
620fa036 1735 *
539e5f02 1736 * Since we're being called from an LSC, link is already known to be up.
620fa036 1737 * So use link_up_wait_to_complete=false.
0ecc061d 1738 */
620fa036 1739 hw->mac.ops.check_link(hw, &speed, &link_up, false);
539e5f02
PWJ		 1740
1741 if (hw->fc.disable_fc_autoneg || (!link_up)) {
620fa036
MC		 1742 hw->fc.fc_was_autonegged = false;
1743 hw->fc.current_mode = hw->fc.requested_mode;
0ecc061d
PWJ		 1744 goto out;
1745 }
1746
539e5f02
PWJ		 1747 /*
1748 * On backplane, bail out if
1749 * - backplane autoneg was not completed, or if
000c486d 1750 * - we are 82599 and link partner is not AN enabled
539e5f02
PWJ		 1751 */
1752 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1753 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
000c486d 1754 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
539e5f02
PWJ		 1755 hw->fc.fc_was_autonegged = false;
1756 hw->fc.current_mode = hw->fc.requested_mode;
1757 goto out;
1758 }
000c486d
DS		 1759
1760 if (hw->mac.type == ixgbe_mac_82599EB) {
1761 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
1762 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
1763 hw->fc.fc_was_autonegged = false;
1764 hw->fc.current_mode = hw->fc.requested_mode;
1765 goto out;
1766 }
1767 }
539e5f02
PWJ		 1768 }
1769
1770 /*
1771 * On multispeed fiber at 1g, bail out if
1772 * - link is up but AN did not complete, or if
1773 * - link is up and AN completed but timed out
1774 */
1775 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) {
1776 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1777 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1778 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1779 hw->fc.fc_was_autonegged = false;
1780 hw->fc.current_mode = hw->fc.requested_mode;
1781 goto out;
1782 }
1783 }
1784
9bbe3a57
PW		 1785 /*
1786 * Bail out on
1787 * - copper or CX4 adapters
1788 * - fiber adapters running at 10gig
1789 */
1790 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
1791 (hw->phy.media_type == ixgbe_media_type_cx4) ||
1792 ((hw->phy.media_type == ixgbe_media_type_fiber) &&
1793 (speed == IXGBE_LINK_SPEED_10GB_FULL))) {
1794 hw->fc.fc_was_autonegged = false;
1795 hw->fc.current_mode = hw->fc.requested_mode;
1796 goto out;
1797 }
1798
0ecc061d
PWJ		 1799 /*
1800 * Read the AN advertisement and LP ability registers and resolve
1801 * local flow control settings accordingly
1802 */
539e5f02
PWJ		 1803 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1804 (hw->phy.media_type != ixgbe_media_type_backplane)) {
1805 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1806 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1807 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1808 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1809 /*
1810 * Now we need to check if the user selected Rx ONLY
1811 * of pause frames. In this case, we had to advertise
1812 * FULL flow control because we could not advertise RX
1813 * ONLY. Hence, we must now check to see if we need to
1814 * turn OFF the TRANSMISSION of PAUSE frames.
1815 */
1816 if (hw->fc.requested_mode == ixgbe_fc_full) {
1817 hw->fc.current_mode = ixgbe_fc_full;
1818 hw_dbg(hw, "Flow Control = FULL.\n");
1819 } else {
1820 hw->fc.current_mode = ixgbe_fc_rx_pause;
1821 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1822 }
1823 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1824 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1825 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1826 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1827 hw->fc.current_mode = ixgbe_fc_tx_pause;
1828 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1829 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1830 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1831 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1832 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1833 hw->fc.current_mode = ixgbe_fc_rx_pause;
1834 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1835 } else {
1836 hw->fc.current_mode = ixgbe_fc_none;
1837 hw_dbg(hw, "Flow Control = NONE.\n");
1838 }
1839 }
1840
1841 if (hw->phy.media_type == ixgbe_media_type_backplane) {
0ecc061d 1842 /*
539e5f02
PWJ		 1843 * Read the 10g AN autoc and LP ability registers and resolve
1844 * local flow control settings accordingly
0ecc061d 1845 */
539e5f02
PWJ		 1846 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1847 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
1848
1849 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1850 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) {
1851 /*
1852 * Now we need to check if the user selected Rx ONLY
1853 * of pause frames. In this case, we had to advertise
1854 * FULL flow control because we could not advertise RX
1855 * ONLY. Hence, we must now check to see if we need to
1856 * turn OFF the TRANSMISSION of PAUSE frames.
1857 */
1858 if (hw->fc.requested_mode == ixgbe_fc_full) {
1859 hw->fc.current_mode = ixgbe_fc_full;
1860 hw_dbg(hw, "Flow Control = FULL.\n");
1861 } else {
1862 hw->fc.current_mode = ixgbe_fc_rx_pause;
1863 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1864 }
1865 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1866 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1867 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1868 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
1869 hw->fc.current_mode = ixgbe_fc_tx_pause;
1870 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1871 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1872 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1873 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1874 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
0ecc061d
PWJ		 1875 hw->fc.current_mode = ixgbe_fc_rx_pause;
1876 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
539e5f02
PWJ		 1877 } else {
1878 hw->fc.current_mode = ixgbe_fc_none;
1879 hw_dbg(hw, "Flow Control = NONE.\n");
0ecc061d 1880 }
0ecc061d 1881 }
620fa036
MC		 1882 /* Record that current_mode is the result of a successful autoneg */
1883 hw->fc.fc_was_autonegged = true;
1884
0ecc061d
PWJ		 1885out:
1886 return ret_val;
1887}
1888
11afc1b1 1889/**
620fa036 1890 * ixgbe_setup_fc - Set up flow control
11afc1b1
PW		 1891 * @hw: pointer to hardware structure
1892 *
620fa036 1893 * Called at init time to set up flow control.
11afc1b1 1894 **/
7b25cdba 1895static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1896{
1897 s32 ret_val = 0;
620fa036 1898 u32 reg;
11afc1b1 1899
bb3daa4a
PW		 1900#ifdef CONFIG_DCB
1901 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1902 hw->fc.current_mode = hw->fc.requested_mode;
1903 goto out;
1904 }
1905
1906#endif
11afc1b1
PW		 1907 /* Validate the packetbuf configuration */
1908 if (packetbuf_num < 0 || packetbuf_num > 7) {
1909 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1910 "is 0-7\n", packetbuf_num);
1911 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1912 goto out;
1913 }
1914
1915 /*
1916 * Validate the water mark configuration. Zero water marks are invalid
1917 * because it causes the controller to just blast out fc packets.
1918 */
1919 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
620fa036
MC		 1920 hw_dbg(hw, "Invalid water mark configuration\n");
1921 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1922 goto out;
11afc1b1
PW		 1923 }
1924
1925 /*
1926 * Validate the requested mode. Strict IEEE mode does not allow
620fa036 1927 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
11afc1b1
PW		 1928 */
1929 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1930 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1931 "IEEE mode\n");
1932 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1933 goto out;
1934 }
1935
1936 /*
1937 * 10gig parts do not have a word in the EEPROM to determine the
1938 * default flow control setting, so we explicitly set it to full.
1939 */
1940 if (hw->fc.requested_mode == ixgbe_fc_default)
1941 hw->fc.requested_mode = ixgbe_fc_full;
1942
1943 /*
620fa036
MC		 1944 * Set up the 1G flow control advertisement registers so the HW will be
1945 * able to do fc autoneg once the cable is plugged in. If we end up
1946 * using 10g instead, this is harmless.
11afc1b1 1947 */
620fa036 1948 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
11afc1b1 1949
620fa036
MC		 1950 /*
1951 * The possible values of fc.requested_mode are:
1952 * 0: Flow control is completely disabled
1953 * 1: Rx flow control is enabled (we can receive pause frames,
1954 * but not send pause frames).
1955 * 2: Tx flow control is enabled (we can send pause frames but
1956 * we do not support receiving pause frames).
1957 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1958#ifdef CONFIG_DCB
1959 * 4: Priority Flow Control is enabled.
1960#endif
1961 * other: Invalid.
1962 */
1963 switch (hw->fc.requested_mode) {
1964 case ixgbe_fc_none:
1965 /* Flow control completely disabled by software override. */
1966 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1967 break;
1968 case ixgbe_fc_rx_pause:
1969 /*
1970 * Rx Flow control is enabled and Tx Flow control is
1971 * disabled by software override. Since there really
1972 * isn't a way to advertise that we are capable of RX
1973 * Pause ONLY, we will advertise that we support both
1974 * symmetric and asymmetric Rx PAUSE. Later, we will
1975 * disable the adapter's ability to send PAUSE frames.
1976 */
1977 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1978 break;
1979 case ixgbe_fc_tx_pause:
1980 /*
1981 * Tx Flow control is enabled, and Rx Flow control is
1982 * disabled by software override.
1983 */
1984 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1985 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1986 break;
1987 case ixgbe_fc_full:
1988 /* Flow control (both Rx and Tx) is enabled by SW override. */
1989 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1990 break;
1991#ifdef CONFIG_DCB
1992 case ixgbe_fc_pfc:
11afc1b1 1993 goto out;
620fa036
MC		 1994 break;
1995#endif /* CONFIG_DCB */
1996 default:
1997 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 1998 ret_val = IXGBE_ERR_CONFIG;
620fa036
MC		 1999 goto out;
2000 break;
2001 }
2002
2003 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2004 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
11afc1b1 2005
620fa036
MC		 2006 /* Disable AN timeout */
2007 if (hw->fc.strict_ieee)
2008 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
2009
2010 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2011 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
11afc1b1 2012
539e5f02
PWJ		 2013 /*
2014 * Set up the 10G flow control advertisement registers so the HW
2015 * can do fc autoneg once the cable is plugged in. If we end up
2016 * using 1g instead, this is harmless.
2017 */
2018 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2019
2020 /*
2021 * The possible values of fc.requested_mode are:
2022 * 0: Flow control is completely disabled
2023 * 1: Rx flow control is enabled (we can receive pause frames,
2024 * but not send pause frames).
2025 * 2: Tx flow control is enabled (we can send pause frames but
2026 * we do not support receiving pause frames).
2027 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2028 * other: Invalid.
2029 */
2030 switch (hw->fc.requested_mode) {
2031 case ixgbe_fc_none:
2032 /* Flow control completely disabled by software override. */
2033 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2034 break;
2035 case ixgbe_fc_rx_pause:
2036 /*
2037 * Rx Flow control is enabled and Tx Flow control is
2038 * disabled by software override. Since there really
2039 * isn't a way to advertise that we are capable of RX
2040 * Pause ONLY, we will advertise that we support both
2041 * symmetric and asymmetric Rx PAUSE. Later, we will
2042 * disable the adapter's ability to send PAUSE frames.
2043 */
2044 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2045 break;
2046 case ixgbe_fc_tx_pause:
2047 /*
2048 * Tx Flow control is enabled, and Rx Flow control is
2049 * disabled by software override.
2050 */
2051 reg |= (IXGBE_AUTOC_ASM_PAUSE);
2052 reg &= ~(IXGBE_AUTOC_SYM_PAUSE);
2053 break;
2054 case ixgbe_fc_full:
2055 /* Flow control (both Rx and Tx) is enabled by SW override. */
2056 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2057 break;
2058#ifdef CONFIG_DCB
2059 case ixgbe_fc_pfc:
2060 goto out;
2061 break;
2062#endif /* CONFIG_DCB */
2063 default:
2064 hw_dbg(hw, "Flow control param set incorrectly\n");
2065 ret_val = IXGBE_ERR_CONFIG;
2066 goto out;
2067 break;
2068 }
2069 /*
2070 * AUTOC restart handles negotiation of 1G and 10G. There is
2071 * no need to set the PCS1GCTL register.
2072 */
2073 reg |= IXGBE_AUTOC_AN_RESTART;
2074 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg);
2075 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2076
11afc1b1
PW		 2077out:
2078 return ret_val;
2079}
2080
9a799d71
AK		 2081/**
2082 * ixgbe_disable_pcie_master - Disable PCI-express master access
2083 * @hw: pointer to hardware structure
2084 *
2085 * Disables PCI-Express master access and verifies there are no pending
2086 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2087 * bit hasn't caused the master requests to be disabled, else 0
2088 * is returned signifying master requests disabled.
2089 **/
2090s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2091{
c44ade9e
JB		 2092 u32 i;
2093 u32 reg_val;
2094 u32 number_of_queues;
9a799d71
AK		 2095 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2096
c44ade9e
JB		 2097 /* Disable the receive unit by stopping each queue */
2098 number_of_queues = hw->mac.max_rx_queues;
2099 for (i = 0; i < number_of_queues; i++) {
2100 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2101 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2102 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2103 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2104 }
2105 }
2106
2107 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2108 reg_val |= IXGBE_CTRL_GIO_DIS;
2109 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
9a799d71
AK		 2110
2111 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2112 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
2113 status = 0;
2114 break;
2115 }
2116 udelay(100);
2117 }
2118
2119 return status;
2120}
2121
2122
2123/**
c44ade9e 2124 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2125 * @hw: pointer to hardware structure
c44ade9e 2126 * @mask: Mask to specify which semaphore to acquire
9a799d71 2127 *
c44ade9e 2128 * Acquires the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 2129 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2130 **/
2131s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2132{
2133 u32 gssr;
2134 u32 swmask = mask;
2135 u32 fwmask = mask << 5;
2136 s32 timeout = 200;
2137
2138 while (timeout) {
2139 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2140 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2141
2142 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2143 if (!(gssr & (fwmask | swmask)))
2144 break;
2145
2146 /*
2147 * Firmware currently using resource (fwmask) or other software
2148 * thread currently using resource (swmask)
2149 */
2150 ixgbe_release_eeprom_semaphore(hw);
2151 msleep(5);
2152 timeout--;
2153 }
2154
2155 if (!timeout) {
2156 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
539e5f02 2157 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2158 }
2159
2160 gssr |= swmask;
2161 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2162
2163 ixgbe_release_eeprom_semaphore(hw);
2164 return 0;
2165}
2166
2167/**
2168 * ixgbe_release_swfw_sync - Release SWFW semaphore
2169 * @hw: pointer to hardware structure
c44ade9e 2170 * @mask: Mask to specify which semaphore to release
9a799d71 2171 *
c44ade9e 2172 * Releases the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 2173 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2174 **/
2175void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2176{
2177 u32 gssr;
2178 u32 swmask = mask;
2179
2180 ixgbe_get_eeprom_semaphore(hw);
2181
2182 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2183 gssr &= ~swmask;
2184 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2185
2186 ixgbe_release_eeprom_semaphore(hw);
2187}
2188
11afc1b1
PW		 2189/**
2190 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2191 * @hw: pointer to hardware structure
2192 * @regval: register value to write to RXCTRL
2193 *
2194 * Enables the Rx DMA unit
2195 **/
2196s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2197{
2198 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2199
2200 return 0;
2201}
87c12017
PW		 2202
2203/**
2204 * ixgbe_blink_led_start_generic - Blink LED based on index.
2205 * @hw: pointer to hardware structure
2206 * @index: led number to blink
2207 **/
2208s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2209{
2210 ixgbe_link_speed speed = 0;
2211 bool link_up = 0;
2212 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2213 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2214
2215 /*
2216 * Link must be up to auto-blink the LEDs;
2217 * Force it if link is down.
2218 */
2219 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2220
2221 if (!link_up) {
50ac58ba 2222 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017
PW		 2223 autoc_reg |= IXGBE_AUTOC_FLU;
2224 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2225 msleep(10);
2226 }
2227
2228 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2229 led_reg |= IXGBE_LED_BLINK(index);
2230 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2231 IXGBE_WRITE_FLUSH(hw);
2232
2233 return 0;
2234}
2235
2236/**
2237 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2238 * @hw: pointer to hardware structure
2239 * @index: led number to stop blinking
2240 **/
2241s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2242{
2243 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2244 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2245
2246 autoc_reg &= ~IXGBE_AUTOC_FLU;
2247 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2248 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2249
2250 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2251 led_reg &= ~IXGBE_LED_BLINK(index);
2252 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2253 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2254 IXGBE_WRITE_FLUSH(hw);
2255
2256 return 0;
2257}
Linux kernel - Deliverables
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