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ixgbe: X540 Cleanup
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
ccffad25 31#include <linux/netdevice.h>
9a799d71 32
11afc1b1 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
c44ade9e 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 48
9a799d71 49static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
7b25cdba 50static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
9a799d71
AK		 51
52/**
c44ade9e 53 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 54 * @hw: pointer to hardware structure
55 *
56 * Starts the hardware by filling the bus info structure and media type, clears
57 * all on chip counters, initializes receive address registers, multicast
58 * table, VLAN filter table, calls routine to set up link and flow control
59 * settings, and leaves transmit and receive units disabled and uninitialized
60 **/
c44ade9e 61s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 62{
63 u32 ctrl_ext;
64
65 /* Set the media type */
66 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
67
68 /* Identify the PHY */
c44ade9e 69 hw->phy.ops.identify(hw);
9a799d71 70
9a799d71 71 /* Clear the VLAN filter table */
c44ade9e 72 hw->mac.ops.clear_vfta(hw);
9a799d71 73
9a799d71 74 /* Clear statistics registers */
c44ade9e 75 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 76
77 /* Set No Snoop Disable */
78 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
79 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
80 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 81 IXGBE_WRITE_FLUSH(hw);
9a799d71 82
620fa036
MC		 83 /* Setup flow control */
84 ixgbe_setup_fc(hw, 0);
85
9a799d71
AK		 86 /* Clear adapter stopped flag */
87 hw->adapter_stopped = false;
88
89 return 0;
90}
91
92/**
c44ade9e 93 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 94 * @hw: pointer to hardware structure
95 *
c44ade9e 96 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 97 * structure and media type, clears all on chip counters, initializes receive
98 * address registers, multicast table, VLAN filter table, calls routine to set
99 * up link and flow control settings, and leaves transmit and receive units
100 * disabled and uninitialized
101 **/
c44ade9e 102s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 103{
794caeb2
PWJ		 104 s32 status;
105
9a799d71 106 /* Reset the hardware */
794caeb2 107 status = hw->mac.ops.reset_hw(hw);
9a799d71 108
794caeb2
PWJ		 109 if (status == 0) {
110 /* Start the HW */
111 status = hw->mac.ops.start_hw(hw);
112 }
9a799d71 113
794caeb2 114 return status;
9a799d71
AK		 115}
116
117/**
c44ade9e 118 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 119 * @hw: pointer to hardware structure
120 *
121 * Clears all hardware statistics counters by reading them from the hardware
122 * Statistics counters are clear on read.
123 **/
c44ade9e 124s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 125{
126 u16 i = 0;
127
128 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
129 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
130 IXGBE_READ_REG(hw, IXGBE_ERRBC);
131 IXGBE_READ_REG(hw, IXGBE_MSPDC);
132 for (i = 0; i < 8; i++)
133 IXGBE_READ_REG(hw, IXGBE_MPC(i));
134
135 IXGBE_READ_REG(hw, IXGBE_MLFC);
136 IXGBE_READ_REG(hw, IXGBE_MRFC);
137 IXGBE_READ_REG(hw, IXGBE_RLEC);
138 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
139 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
140 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
141 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
142
143 for (i = 0; i < 8; i++) {
144 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
145 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
146 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
147 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
148 }
149
150 IXGBE_READ_REG(hw, IXGBE_PRC64);
151 IXGBE_READ_REG(hw, IXGBE_PRC127);
152 IXGBE_READ_REG(hw, IXGBE_PRC255);
153 IXGBE_READ_REG(hw, IXGBE_PRC511);
154 IXGBE_READ_REG(hw, IXGBE_PRC1023);
155 IXGBE_READ_REG(hw, IXGBE_PRC1522);
156 IXGBE_READ_REG(hw, IXGBE_GPRC);
157 IXGBE_READ_REG(hw, IXGBE_BPRC);
158 IXGBE_READ_REG(hw, IXGBE_MPRC);
159 IXGBE_READ_REG(hw, IXGBE_GPTC);
160 IXGBE_READ_REG(hw, IXGBE_GORCL);
161 IXGBE_READ_REG(hw, IXGBE_GORCH);
162 IXGBE_READ_REG(hw, IXGBE_GOTCL);
163 IXGBE_READ_REG(hw, IXGBE_GOTCH);
164 for (i = 0; i < 8; i++)
165 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
166 IXGBE_READ_REG(hw, IXGBE_RUC);
167 IXGBE_READ_REG(hw, IXGBE_RFC);
168 IXGBE_READ_REG(hw, IXGBE_ROC);
169 IXGBE_READ_REG(hw, IXGBE_RJC);
170 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
171 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
172 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
173 IXGBE_READ_REG(hw, IXGBE_TORL);
174 IXGBE_READ_REG(hw, IXGBE_TORH);
175 IXGBE_READ_REG(hw, IXGBE_TPR);
176 IXGBE_READ_REG(hw, IXGBE_TPT);
177 IXGBE_READ_REG(hw, IXGBE_PTC64);
178 IXGBE_READ_REG(hw, IXGBE_PTC127);
179 IXGBE_READ_REG(hw, IXGBE_PTC255);
180 IXGBE_READ_REG(hw, IXGBE_PTC511);
181 IXGBE_READ_REG(hw, IXGBE_PTC1023);
182 IXGBE_READ_REG(hw, IXGBE_PTC1522);
183 IXGBE_READ_REG(hw, IXGBE_MPTC);
184 IXGBE_READ_REG(hw, IXGBE_BPTC);
185 for (i = 0; i < 16; i++) {
186 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
187 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
188 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
189 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
190 }
191
192 return 0;
193}
194
195/**
289700db 196 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 197 * @hw: pointer to hardware structure
289700db
DS		 198 * @pba_num: stores the part number string from the EEPROM
199 * @pba_num_size: part number string buffer length
c44ade9e 200 *
289700db 201 * Reads the part number string from the EEPROM.
c44ade9e 202 **/
289700db
DS		 203s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
204 u32 pba_num_size)
c44ade9e
JB		 205{
206 s32 ret_val;
207 u16 data;
289700db
DS		 208 u16 pba_ptr;
209 u16 offset;
210 u16 length;
211
212 if (pba_num == NULL) {
213 hw_dbg(hw, "PBA string buffer was null\n");
214 return IXGBE_ERR_INVALID_ARGUMENT;
215 }
c44ade9e
JB		 216
217 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
218 if (ret_val) {
219 hw_dbg(hw, "NVM Read Error\n");
220 return ret_val;
221 }
c44ade9e 222
289700db 223 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 224 if (ret_val) {
225 hw_dbg(hw, "NVM Read Error\n");
226 return ret_val;
227 }
289700db
DS		 228
229 /*
230 * if data is not ptr guard the PBA must be in legacy format which
231 * means pba_ptr is actually our second data word for the PBA number
232 * and we can decode it into an ascii string
233 */
234 if (data != IXGBE_PBANUM_PTR_GUARD) {
235 hw_dbg(hw, "NVM PBA number is not stored as string\n");
236
237 /* we will need 11 characters to store the PBA */
238 if (pba_num_size < 11) {
239 hw_dbg(hw, "PBA string buffer too small\n");
240 return IXGBE_ERR_NO_SPACE;
241 }
242
243 /* extract hex string from data and pba_ptr */
244 pba_num[0] = (data >> 12) & 0xF;
245 pba_num[1] = (data >> 8) & 0xF;
246 pba_num[2] = (data >> 4) & 0xF;
247 pba_num[3] = data & 0xF;
248 pba_num[4] = (pba_ptr >> 12) & 0xF;
249 pba_num[5] = (pba_ptr >> 8) & 0xF;
250 pba_num[6] = '-';
251 pba_num[7] = 0;
252 pba_num[8] = (pba_ptr >> 4) & 0xF;
253 pba_num[9] = pba_ptr & 0xF;
254
255 /* put a null character on the end of our string */
256 pba_num[10] = '\0';
257
258 /* switch all the data but the '-' to hex char */
259 for (offset = 0; offset < 10; offset++) {
260 if (pba_num[offset] < 0xA)
261 pba_num[offset] += '0';
262 else if (pba_num[offset] < 0x10)
263 pba_num[offset] += 'A' - 0xA;
264 }
265
266 return 0;
267 }
268
269 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
270 if (ret_val) {
271 hw_dbg(hw, "NVM Read Error\n");
272 return ret_val;
273 }
274
275 if (length == 0xFFFF || length == 0) {
276 hw_dbg(hw, "NVM PBA number section invalid length\n");
277 return IXGBE_ERR_PBA_SECTION;
278 }
279
280 /* check if pba_num buffer is big enough */
281 if (pba_num_size < (((u32)length * 2) - 1)) {
282 hw_dbg(hw, "PBA string buffer too small\n");
283 return IXGBE_ERR_NO_SPACE;
284 }
285
286 /* trim pba length from start of string */
287 pba_ptr++;
288 length--;
289
290 for (offset = 0; offset < length; offset++) {
291 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
292 if (ret_val) {
293 hw_dbg(hw, "NVM Read Error\n");
294 return ret_val;
295 }
296 pba_num[offset * 2] = (u8)(data >> 8);
297 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
298 }
299 pba_num[offset * 2] = '\0';
c44ade9e
JB		 300
301 return 0;
302}
303
304/**
305 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 306 * @hw: pointer to hardware structure
307 * @mac_addr: Adapter MAC address
308 *
309 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
310 * A reset of the adapter must be performed prior to calling this function
311 * in order for the MAC address to have been loaded from the EEPROM into RAR0
312 **/
c44ade9e 313s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 314{
315 u32 rar_high;
316 u32 rar_low;
317 u16 i;
318
319 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
320 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
321
322 for (i = 0; i < 4; i++)
323 mac_addr[i] = (u8)(rar_low >> (i*8));
324
325 for (i = 0; i < 2; i++)
326 mac_addr[i+4] = (u8)(rar_high >> (i*8));
327
328 return 0;
329}
330
11afc1b1
PW		 331/**
332 * ixgbe_get_bus_info_generic - Generic set PCI bus info
333 * @hw: pointer to hardware structure
334 *
335 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
336 **/
337s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
338{
339 struct ixgbe_adapter *adapter = hw->back;
340 struct ixgbe_mac_info *mac = &hw->mac;
341 u16 link_status;
342
343 hw->bus.type = ixgbe_bus_type_pci_express;
344
345 /* Get the negotiated link width and speed from PCI config space */
346 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
347 &link_status);
348
349 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
350 case IXGBE_PCI_LINK_WIDTH_1:
351 hw->bus.width = ixgbe_bus_width_pcie_x1;
352 break;
353 case IXGBE_PCI_LINK_WIDTH_2:
354 hw->bus.width = ixgbe_bus_width_pcie_x2;
355 break;
356 case IXGBE_PCI_LINK_WIDTH_4:
357 hw->bus.width = ixgbe_bus_width_pcie_x4;
358 break;
359 case IXGBE_PCI_LINK_WIDTH_8:
360 hw->bus.width = ixgbe_bus_width_pcie_x8;
361 break;
362 default:
363 hw->bus.width = ixgbe_bus_width_unknown;
364 break;
365 }
366
367 switch (link_status & IXGBE_PCI_LINK_SPEED) {
368 case IXGBE_PCI_LINK_SPEED_2500:
369 hw->bus.speed = ixgbe_bus_speed_2500;
370 break;
371 case IXGBE_PCI_LINK_SPEED_5000:
372 hw->bus.speed = ixgbe_bus_speed_5000;
373 break;
374 default:
375 hw->bus.speed = ixgbe_bus_speed_unknown;
376 break;
377 }
378
379 mac->ops.set_lan_id(hw);
380
381 return 0;
382}
383
384/**
385 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
386 * @hw: pointer to the HW structure
387 *
388 * Determines the LAN function id by reading memory-mapped registers
389 * and swaps the port value if requested.
390 **/
391void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
392{
393 struct ixgbe_bus_info *bus = &hw->bus;
394 u32 reg;
395
396 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
397 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
398 bus->lan_id = bus->func;
399
400 /* check for a port swap */
401 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
402 if (reg & IXGBE_FACTPS_LFS)
403 bus->func ^= 0x1;
404}
405
9a799d71 406/**
c44ade9e 407 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 408 * @hw: pointer to hardware structure
409 *
410 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
411 * disables transmit and receive units. The adapter_stopped flag is used by
412 * the shared code and drivers to determine if the adapter is in a stopped
413 * state and should not touch the hardware.
414 **/
c44ade9e 415s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71
AK		 416{
417 u32 number_of_queues;
418 u32 reg_val;
419 u16 i;
420
421 /*
422 * Set the adapter_stopped flag so other driver functions stop touching
423 * the hardware
424 */
425 hw->adapter_stopped = true;
426
427 /* Disable the receive unit */
428 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
429 reg_val &= ~(IXGBE_RXCTRL_RXEN);
430 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
c44ade9e 431 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 432 msleep(2);
433
434 /* Clear interrupt mask to stop from interrupts being generated */
435 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
436
437 /* Clear any pending interrupts */
438 IXGBE_READ_REG(hw, IXGBE_EICR);
439
440 /* Disable the transmit unit. Each queue must be disabled. */
c44ade9e 441 number_of_queues = hw->mac.max_tx_queues;
9a799d71
AK		 442 for (i = 0; i < number_of_queues; i++) {
443 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
444 if (reg_val & IXGBE_TXDCTL_ENABLE) {
445 reg_val &= ~IXGBE_TXDCTL_ENABLE;
446 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
447 }
448 }
449
c44ade9e
JB		 450 /*
451 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
452 * access and verify no pending requests
453 */
a4297dc2 454 ixgbe_disable_pcie_master(hw);
c44ade9e 455
9a799d71
AK		 456 return 0;
457}
458
459/**
c44ade9e 460 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 461 * @hw: pointer to hardware structure
462 * @index: led number to turn on
463 **/
c44ade9e 464s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 465{
466 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
467
468 /* To turn on the LED, set mode to ON. */
469 led_reg &= ~IXGBE_LED_MODE_MASK(index);
470 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
471 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 472 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 473
474 return 0;
475}
476
477/**
c44ade9e 478 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 479 * @hw: pointer to hardware structure
480 * @index: led number to turn off
481 **/
c44ade9e 482s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 483{
484 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
485
486 /* To turn off the LED, set mode to OFF. */
487 led_reg &= ~IXGBE_LED_MODE_MASK(index);
488 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
489 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 490 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 491
492 return 0;
493}
494
9a799d71 495/**
c44ade9e 496 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 497 * @hw: pointer to hardware structure
498 *
499 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
500 * ixgbe_hw struct in order to set up EEPROM access.
501 **/
c44ade9e 502s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 503{
504 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
505 u32 eec;
506 u16 eeprom_size;
507
508 if (eeprom->type == ixgbe_eeprom_uninitialized) {
509 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 510 /* Set default semaphore delay to 10ms which is a well
511 * tested value */
512 eeprom->semaphore_delay = 10;
9a799d71
AK		 513
514 /*
515 * Check for EEPROM present first.
516 * If not present leave as none
517 */
518 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
519 if (eec & IXGBE_EEC_PRES) {
520 eeprom->type = ixgbe_eeprom_spi;
521
522 /*
523 * SPI EEPROM is assumed here. This code would need to
524 * change if a future EEPROM is not SPI.
525 */
526 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
527 IXGBE_EEC_SIZE_SHIFT);
528 eeprom->word_size = 1 << (eeprom_size +
529 IXGBE_EEPROM_WORD_SIZE_SHIFT);
530 }
531
532 if (eec & IXGBE_EEC_ADDR_SIZE)
533 eeprom->address_bits = 16;
534 else
535 eeprom->address_bits = 8;
536 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
537 "%d\n", eeprom->type, eeprom->word_size,
538 eeprom->address_bits);
539 }
540
541 return 0;
542}
543
11afc1b1
PW		 544/**
545 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
546 * @hw: pointer to hardware structure
547 * @offset: offset within the EEPROM to be written to
548 * @data: 16 bit word to be written to the EEPROM
549 *
550 * If ixgbe_eeprom_update_checksum is not called after this function, the
551 * EEPROM will most likely contain an invalid checksum.
552 **/
553s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
554{
555 s32 status;
556 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
557
558 hw->eeprom.ops.init_params(hw);
559
560 if (offset >= hw->eeprom.word_size) {
561 status = IXGBE_ERR_EEPROM;
562 goto out;
563 }
564
565 /* Prepare the EEPROM for writing */
566 status = ixgbe_acquire_eeprom(hw);
567
568 if (status == 0) {
569 if (ixgbe_ready_eeprom(hw) != 0) {
570 ixgbe_release_eeprom(hw);
571 status = IXGBE_ERR_EEPROM;
572 }
573 }
574
575 if (status == 0) {
576 ixgbe_standby_eeprom(hw);
577
578 /* Send the WRITE ENABLE command (8 bit opcode ) */
579 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
580 IXGBE_EEPROM_OPCODE_BITS);
581
582 ixgbe_standby_eeprom(hw);
583
584 /*
585 * Some SPI eeproms use the 8th address bit embedded in the
586 * opcode
587 */
588 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
589 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
590
591 /* Send the Write command (8-bit opcode + addr) */
592 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
593 IXGBE_EEPROM_OPCODE_BITS);
594 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
595 hw->eeprom.address_bits);
596
597 /* Send the data */
598 data = (data >> 8) | (data << 8);
599 ixgbe_shift_out_eeprom_bits(hw, data, 16);
600 ixgbe_standby_eeprom(hw);
601
11afc1b1
PW		 602 /* Done with writing - release the EEPROM */
603 ixgbe_release_eeprom(hw);
604 }
605
606out:
607 return status;
608}
609
9a799d71 610/**
c44ade9e
JB		 611 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
612 * @hw: pointer to hardware structure
613 * @offset: offset within the EEPROM to be read
614 * @data: read 16 bit value from EEPROM
615 *
616 * Reads 16 bit value from EEPROM through bit-bang method
617 **/
618s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
619 u16 *data)
620{
621 s32 status;
622 u16 word_in;
623 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
624
625 hw->eeprom.ops.init_params(hw);
626
627 if (offset >= hw->eeprom.word_size) {
628 status = IXGBE_ERR_EEPROM;
629 goto out;
630 }
631
632 /* Prepare the EEPROM for reading */
633 status = ixgbe_acquire_eeprom(hw);
634
635 if (status == 0) {
636 if (ixgbe_ready_eeprom(hw) != 0) {
637 ixgbe_release_eeprom(hw);
638 status = IXGBE_ERR_EEPROM;
639 }
640 }
641
642 if (status == 0) {
643 ixgbe_standby_eeprom(hw);
644
645 /*
646 * Some SPI eeproms use the 8th address bit embedded in the
647 * opcode
648 */
649 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
650 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
651
652 /* Send the READ command (opcode + addr) */
653 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
654 IXGBE_EEPROM_OPCODE_BITS);
655 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
656 hw->eeprom.address_bits);
657
658 /* Read the data. */
659 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
660 *data = (word_in >> 8) | (word_in << 8);
661
662 /* End this read operation */
663 ixgbe_release_eeprom(hw);
664 }
665
666out:
667 return status;
668}
669
670/**
21ce849b 671 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
9a799d71
AK		 672 * @hw: pointer to hardware structure
673 * @offset: offset of word in the EEPROM to read
674 * @data: word read from the EEPROM
675 *
676 * Reads a 16 bit word from the EEPROM using the EERD register.
677 **/
21ce849b 678s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
9a799d71
AK		 679{
680 u32 eerd;
681 s32 status;
682
c44ade9e
JB		 683 hw->eeprom.ops.init_params(hw);
684
685 if (offset >= hw->eeprom.word_size) {
686 status = IXGBE_ERR_EEPROM;
687 goto out;
688 }
689
21ce849b
MC		 690 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
691 IXGBE_EEPROM_RW_REG_START;
9a799d71
AK		 692
693 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
21ce849b 694 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71
AK		 695
696 if (status == 0)
697 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
21ce849b 698 IXGBE_EEPROM_RW_REG_DATA);
9a799d71
AK		 699 else
700 hw_dbg(hw, "Eeprom read timed out\n");
701
c44ade9e 702out:
9a799d71
AK		 703 return status;
704}
705
706/**
21ce849b 707 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 708 * @hw: pointer to hardware structure
21ce849b 709 * @ee_reg: EEPROM flag for polling
9a799d71 710 *
21ce849b
MC		 711 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
712 * read or write is done respectively.
9a799d71 713 **/
a391f1d5 714s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 715{
716 u32 i;
717 u32 reg;
718 s32 status = IXGBE_ERR_EEPROM;
719
21ce849b
MC		 720 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
721 if (ee_reg == IXGBE_NVM_POLL_READ)
722 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
723 else
724 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
725
726 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
9a799d71
AK		 727 status = 0;
728 break;
729 }
730 udelay(5);
731 }
732 return status;
733}
734
c44ade9e
JB		 735/**
736 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
737 * @hw: pointer to hardware structure
738 *
739 * Prepares EEPROM for access using bit-bang method. This function should
740 * be called before issuing a command to the EEPROM.
741 **/
742static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
743{
744 s32 status = 0;
dbf893ee 745 u32 eec;
c44ade9e
JB		 746 u32 i;
747
748 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
749 status = IXGBE_ERR_SWFW_SYNC;
750
751 if (status == 0) {
752 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
753
754 /* Request EEPROM Access */
755 eec |= IXGBE_EEC_REQ;
756 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
757
758 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
759 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
760 if (eec & IXGBE_EEC_GNT)
761 break;
762 udelay(5);
763 }
764
765 /* Release if grant not acquired */
766 if (!(eec & IXGBE_EEC_GNT)) {
767 eec &= ~IXGBE_EEC_REQ;
768 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
769 hw_dbg(hw, "Could not acquire EEPROM grant\n");
770
771 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
772 status = IXGBE_ERR_EEPROM;
773 }
c44ade9e 774
dbf893ee
ET		 775 /* Setup EEPROM for Read/Write */
776 if (status == 0) {
777 /* Clear CS and SK */
778 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
779 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
780 IXGBE_WRITE_FLUSH(hw);
781 udelay(1);
782 }
c44ade9e
JB		 783 }
784 return status;
785}
786
9a799d71
AK		 787/**
788 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
789 * @hw: pointer to hardware structure
790 *
791 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
792 **/
793static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
794{
795 s32 status = IXGBE_ERR_EEPROM;
dbf893ee 796 u32 timeout = 2000;
9a799d71
AK		 797 u32 i;
798 u32 swsm;
799
9a799d71
AK		 800 /* Get SMBI software semaphore between device drivers first */
801 for (i = 0; i < timeout; i++) {
802 /*
803 * If the SMBI bit is 0 when we read it, then the bit will be
804 * set and we have the semaphore
805 */
806 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
807 if (!(swsm & IXGBE_SWSM_SMBI)) {
808 status = 0;
809 break;
810 }
dbf893ee 811 udelay(50);
9a799d71
AK		 812 }
813
814 /* Now get the semaphore between SW/FW through the SWESMBI bit */
815 if (status == 0) {
816 for (i = 0; i < timeout; i++) {
817 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
818
819 /* Set the SW EEPROM semaphore bit to request access */
820 swsm |= IXGBE_SWSM_SWESMBI;
821 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
822
823 /*
824 * If we set the bit successfully then we got the
825 * semaphore.
826 */
827 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
828 if (swsm & IXGBE_SWSM_SWESMBI)
829 break;
830
831 udelay(50);
832 }
833
834 /*
835 * Release semaphores and return error if SW EEPROM semaphore
836 * was not granted because we don't have access to the EEPROM
837 */
838 if (i >= timeout) {
dbf893ee 839 hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
b4617240 840 "not granted.\n");
9a799d71
AK		 841 ixgbe_release_eeprom_semaphore(hw);
842 status = IXGBE_ERR_EEPROM;
843 }
dbf893ee
ET		 844 } else {
845 hw_dbg(hw, "Software semaphore SMBI between device drivers "
846 "not granted.\n");
9a799d71
AK		 847 }
848
849 return status;
850}
851
852/**
853 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
854 * @hw: pointer to hardware structure
855 *
856 * This function clears hardware semaphore bits.
857 **/
858static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
859{
860 u32 swsm;
861
862 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
863
864 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
865 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
866 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 867 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 868}
869
c44ade9e
JB		 870/**
871 * ixgbe_ready_eeprom - Polls for EEPROM ready
872 * @hw: pointer to hardware structure
873 **/
874static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
875{
876 s32 status = 0;
877 u16 i;
878 u8 spi_stat_reg;
879
880 /*
881 * Read "Status Register" repeatedly until the LSB is cleared. The
882 * EEPROM will signal that the command has been completed by clearing
883 * bit 0 of the internal status register. If it's not cleared within
884 * 5 milliseconds, then error out.
885 */
886 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
887 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
888 IXGBE_EEPROM_OPCODE_BITS);
889 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
890 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
891 break;
892
893 udelay(5);
894 ixgbe_standby_eeprom(hw);
895 };
896
897 /*
898 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
899 * devices (and only 0-5mSec on 5V devices)
900 */
901 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
902 hw_dbg(hw, "SPI EEPROM Status error\n");
903 status = IXGBE_ERR_EEPROM;
904 }
905
906 return status;
907}
908
909/**
910 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
911 * @hw: pointer to hardware structure
912 **/
913static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
914{
915 u32 eec;
916
917 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
918
919 /* Toggle CS to flush commands */
920 eec |= IXGBE_EEC_CS;
921 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
922 IXGBE_WRITE_FLUSH(hw);
923 udelay(1);
924 eec &= ~IXGBE_EEC_CS;
925 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
926 IXGBE_WRITE_FLUSH(hw);
927 udelay(1);
928}
929
930/**
931 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
932 * @hw: pointer to hardware structure
933 * @data: data to send to the EEPROM
934 * @count: number of bits to shift out
935 **/
936static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
937 u16 count)
938{
939 u32 eec;
940 u32 mask;
941 u32 i;
942
943 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
944
945 /*
946 * Mask is used to shift "count" bits of "data" out to the EEPROM
947 * one bit at a time. Determine the starting bit based on count
948 */
949 mask = 0x01 << (count - 1);
950
951 for (i = 0; i < count; i++) {
952 /*
953 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
954 * "1", and then raising and then lowering the clock (the SK
955 * bit controls the clock input to the EEPROM). A "0" is
956 * shifted out to the EEPROM by setting "DI" to "0" and then
957 * raising and then lowering the clock.
958 */
959 if (data & mask)
960 eec |= IXGBE_EEC_DI;
961 else
962 eec &= ~IXGBE_EEC_DI;
963
964 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
965 IXGBE_WRITE_FLUSH(hw);
966
967 udelay(1);
968
969 ixgbe_raise_eeprom_clk(hw, &eec);
970 ixgbe_lower_eeprom_clk(hw, &eec);
971
972 /*
973 * Shift mask to signify next bit of data to shift in to the
974 * EEPROM
975 */
976 mask = mask >> 1;
977 };
978
979 /* We leave the "DI" bit set to "0" when we leave this routine. */
980 eec &= ~IXGBE_EEC_DI;
981 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
982 IXGBE_WRITE_FLUSH(hw);
983}
984
985/**
986 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
987 * @hw: pointer to hardware structure
988 **/
989static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
990{
991 u32 eec;
992 u32 i;
993 u16 data = 0;
994
995 /*
996 * In order to read a register from the EEPROM, we need to shift
997 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
998 * the clock input to the EEPROM (setting the SK bit), and then reading
999 * the value of the "DO" bit. During this "shifting in" process the
1000 * "DI" bit should always be clear.
1001 */
1002 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1003
1004 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1005
1006 for (i = 0; i < count; i++) {
1007 data = data << 1;
1008 ixgbe_raise_eeprom_clk(hw, &eec);
1009
1010 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1011
1012 eec &= ~(IXGBE_EEC_DI);
1013 if (eec & IXGBE_EEC_DO)
1014 data |= 1;
1015
1016 ixgbe_lower_eeprom_clk(hw, &eec);
1017 }
1018
1019 return data;
1020}
1021
1022/**
1023 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1024 * @hw: pointer to hardware structure
1025 * @eec: EEC register's current value
1026 **/
1027static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1028{
1029 /*
1030 * Raise the clock input to the EEPROM
1031 * (setting the SK bit), then delay
1032 */
1033 *eec = *eec | IXGBE_EEC_SK;
1034 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1035 IXGBE_WRITE_FLUSH(hw);
1036 udelay(1);
1037}
1038
1039/**
1040 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1041 * @hw: pointer to hardware structure
1042 * @eecd: EECD's current value
1043 **/
1044static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1045{
1046 /*
1047 * Lower the clock input to the EEPROM (clearing the SK bit), then
1048 * delay
1049 */
1050 *eec = *eec & ~IXGBE_EEC_SK;
1051 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1052 IXGBE_WRITE_FLUSH(hw);
1053 udelay(1);
1054}
1055
1056/**
1057 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1058 * @hw: pointer to hardware structure
1059 **/
1060static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1061{
1062 u32 eec;
1063
1064 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1065
1066 eec |= IXGBE_EEC_CS; /* Pull CS high */
1067 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1068
1069 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1070 IXGBE_WRITE_FLUSH(hw);
1071
1072 udelay(1);
1073
1074 /* Stop requesting EEPROM access */
1075 eec &= ~IXGBE_EEC_REQ;
1076 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1077
1078 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee
ET		 1079
1080 /* Delay before attempt to obtain semaphore again to allow FW access */
1081 msleep(hw->eeprom.semaphore_delay);
c44ade9e
JB		 1082}
1083
9a799d71 1084/**
dbf893ee 1085 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1086 * @hw: pointer to hardware structure
1087 **/
a391f1d5 1088u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1089{
1090 u16 i;
1091 u16 j;
1092 u16 checksum = 0;
1093 u16 length = 0;
1094 u16 pointer = 0;
1095 u16 word = 0;
1096
1097 /* Include 0x0-0x3F in the checksum */
1098 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1099 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1100 hw_dbg(hw, "EEPROM read failed\n");
1101 break;
1102 }
1103 checksum += word;
1104 }
1105
1106 /* Include all data from pointers except for the fw pointer */
1107 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1108 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1109
1110 /* Make sure the pointer seems valid */
1111 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1112 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1113
1114 if (length != 0xFFFF && length != 0) {
1115 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1116 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1117 checksum += word;
1118 }
1119 }
1120 }
1121 }
1122
1123 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1124
1125 return checksum;
1126}
1127
1128/**
c44ade9e 1129 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1130 * @hw: pointer to hardware structure
1131 * @checksum_val: calculated checksum
1132 *
1133 * Performs checksum calculation and validates the EEPROM checksum. If the
1134 * caller does not need checksum_val, the value can be NULL.
1135 **/
c44ade9e
JB		 1136s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1137 u16 *checksum_val)
9a799d71
AK		 1138{
1139 s32 status;
1140 u16 checksum;
1141 u16 read_checksum = 0;
1142
1143 /*
1144 * Read the first word from the EEPROM. If this times out or fails, do
1145 * not continue or we could be in for a very long wait while every
1146 * EEPROM read fails
1147 */
c44ade9e 1148 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1149
1150 if (status == 0) {
a391f1d5 1151 checksum = hw->eeprom.ops.calc_checksum(hw);
9a799d71 1152
c44ade9e 1153 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1154
1155 /*
1156 * Verify read checksum from EEPROM is the same as
1157 * calculated checksum
1158 */
1159 if (read_checksum != checksum)
1160 status = IXGBE_ERR_EEPROM_CHECKSUM;
1161
1162 /* If the user cares, return the calculated checksum */
1163 if (checksum_val)
1164 *checksum_val = checksum;
1165 } else {
1166 hw_dbg(hw, "EEPROM read failed\n");
1167 }
1168
1169 return status;
1170}
1171
c44ade9e
JB		 1172/**
1173 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1174 * @hw: pointer to hardware structure
1175 **/
1176s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1177{
1178 s32 status;
1179 u16 checksum;
1180
1181 /*
1182 * Read the first word from the EEPROM. If this times out or fails, do
1183 * not continue or we could be in for a very long wait while every
1184 * EEPROM read fails
1185 */
1186 status = hw->eeprom.ops.read(hw, 0, &checksum);
1187
1188 if (status == 0) {
a391f1d5 1189 checksum = hw->eeprom.ops.calc_checksum(hw);
c44ade9e 1190 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
8c7bea32 1191 checksum);
c44ade9e
JB		 1192 } else {
1193 hw_dbg(hw, "EEPROM read failed\n");
1194 }
1195
1196 return status;
1197}
1198
9a799d71
AK		 1199/**
1200 * ixgbe_validate_mac_addr - Validate MAC address
1201 * @mac_addr: pointer to MAC address.
1202 *
1203 * Tests a MAC address to ensure it is a valid Individual Address
1204 **/
1205s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1206{
1207 s32 status = 0;
1208
1209 /* Make sure it is not a multicast address */
1210 if (IXGBE_IS_MULTICAST(mac_addr))
1211 status = IXGBE_ERR_INVALID_MAC_ADDR;
1212 /* Not a broadcast address */
1213 else if (IXGBE_IS_BROADCAST(mac_addr))
1214 status = IXGBE_ERR_INVALID_MAC_ADDR;
1215 /* Reject the zero address */
1216 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
c44ade9e 1217 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
9a799d71
AK		 1218 status = IXGBE_ERR_INVALID_MAC_ADDR;
1219
1220 return status;
1221}
1222
1223/**
c44ade9e 1224 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1225 * @hw: pointer to hardware structure
9a799d71 1226 * @index: Receive address register to write
c44ade9e
JB		 1227 * @addr: Address to put into receive address register
1228 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1229 * @enable_addr: set flag that address is active
1230 *
1231 * Puts an ethernet address into a receive address register.
1232 **/
c44ade9e
JB		 1233s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1234 u32 enable_addr)
9a799d71
AK		 1235{
1236 u32 rar_low, rar_high;
c44ade9e
JB		 1237 u32 rar_entries = hw->mac.num_rar_entries;
1238
c700f4e6
ET		 1239 /* Make sure we are using a valid rar index range */
1240 if (index >= rar_entries) {
1241 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1242 return IXGBE_ERR_INVALID_ARGUMENT;
1243 }
1244
c44ade9e
JB		 1245 /* setup VMDq pool selection before this RAR gets enabled */
1246 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1247
c700f4e6
ET		 1248 /*
1249 * HW expects these in little endian so we reverse the byte
1250 * order from network order (big endian) to little endian
1251 */
1252 rar_low = ((u32)addr[0] |
1253 ((u32)addr[1] << 8) |
1254 ((u32)addr[2] << 16) |
1255 ((u32)addr[3] << 24));
1256 /*
1257 * Some parts put the VMDq setting in the extra RAH bits,
1258 * so save everything except the lower 16 bits that hold part
1259 * of the address and the address valid bit.
1260 */
1261 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1262 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1263 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1264
c700f4e6
ET		 1265 if (enable_addr != 0)
1266 rar_high |= IXGBE_RAH_AV;
9a799d71 1267
c700f4e6
ET		 1268 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1269 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1270
1271 return 0;
1272}
1273
1274/**
1275 * ixgbe_clear_rar_generic - Remove Rx address register
1276 * @hw: pointer to hardware structure
1277 * @index: Receive address register to write
1278 *
1279 * Clears an ethernet address from a receive address register.
1280 **/
1281s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1282{
1283 u32 rar_high;
1284 u32 rar_entries = hw->mac.num_rar_entries;
1285
1286 /* Make sure we are using a valid rar index range */
c700f4e6 1287 if (index >= rar_entries) {
c44ade9e 1288 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1289 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1290 }
1291
c700f4e6
ET		 1292 /*
1293 * Some parts put the VMDq setting in the extra RAH bits,
1294 * so save everything except the lower 16 bits that hold part
1295 * of the address and the address valid bit.
1296 */
1297 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1298 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1299
1300 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1301 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1302
c44ade9e
JB		 1303 /* clear VMDq pool/queue selection for this RAR */
1304 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1305
1306 return 0;
1307}
1308
c44ade9e
JB		 1309/**
1310 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1311 * @hw: pointer to hardware structure
1312 *
1313 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1314 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1315 * the receiver is in reset when the routine is called.
1316 **/
c44ade9e 1317s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1318{
1319 u32 i;
2c5645cf 1320 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1321
1322 /*
1323 * If the current mac address is valid, assume it is a software override
1324 * to the permanent address.
1325 * Otherwise, use the permanent address from the eeprom.
1326 */
1327 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1328 IXGBE_ERR_INVALID_MAC_ADDR) {
1329 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1330 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1331
ce7194d8 1332 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1333 } else {
1334 /* Setup the receive address. */
1335 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1336 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1337
c44ade9e 1338 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1339
1340 /* clear VMDq pool/queue selection for RAR 0 */
1341 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1342 }
c44ade9e 1343 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1344
1345 hw->addr_ctrl.rar_used_count = 1;
1346
1347 /* Zero out the other receive addresses. */
c44ade9e 1348 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1349 for (i = 1; i < rar_entries; i++) {
1350 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1351 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1352 }
1353
1354 /* Clear the MTA */
9a799d71
AK		 1355 hw->addr_ctrl.mta_in_use = 0;
1356 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1357
1358 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1359 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1360 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1361
c44ade9e
JB		 1362 if (hw->mac.ops.init_uta_tables)
1363 hw->mac.ops.init_uta_tables(hw);
1364
9a799d71
AK		 1365 return 0;
1366}
1367
1368/**
1369 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1370 * @hw: pointer to hardware structure
1371 * @mc_addr: the multicast address
1372 *
1373 * Extracts the 12 bits, from a multicast address, to determine which
1374 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1375 * incoming rx multicast addresses, to determine the bit-vector to check in
1376 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1377 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1378 * to mc_filter_type.
1379 **/
1380static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1381{
1382 u32 vector = 0;
1383
1384 switch (hw->mac.mc_filter_type) {
b4617240 1385 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1386 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1387 break;
b4617240 1388 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1389 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1390 break;
b4617240 1391 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1392 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1393 break;
b4617240 1394 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1395 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1396 break;
b4617240 1397 default: /* Invalid mc_filter_type */
9a799d71
AK		 1398 hw_dbg(hw, "MC filter type param set incorrectly\n");
1399 break;
1400 }
1401
1402 /* vector can only be 12-bits or boundary will be exceeded */
1403 vector &= 0xFFF;
1404 return vector;
1405}
1406
1407/**
1408 * ixgbe_set_mta - Set bit-vector in multicast table
1409 * @hw: pointer to hardware structure
1410 * @hash_value: Multicast address hash value
1411 *
1412 * Sets the bit-vector in the multicast table.
1413 **/
1414static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1415{
1416 u32 vector;
1417 u32 vector_bit;
1418 u32 vector_reg;
9a799d71
AK		 1419
1420 hw->addr_ctrl.mta_in_use++;
1421
1422 vector = ixgbe_mta_vector(hw, mc_addr);
1423 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1424
1425 /*
1426 * The MTA is a register array of 128 32-bit registers. It is treated
1427 * like an array of 4096 bits. We want to set bit
1428 * BitArray[vector_value]. So we figure out what register the bit is
1429 * in, read it, OR in the new bit, then write back the new value. The
1430 * register is determined by the upper 7 bits of the vector value and
1431 * the bit within that register are determined by the lower 5 bits of
1432 * the value.
1433 */
1434 vector_reg = (vector >> 5) & 0x7F;
1435 vector_bit = vector & 0x1F;
80960ab0 1436 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 1437}
1438
9a799d71 1439/**
c44ade9e 1440 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1441 * @hw: pointer to hardware structure
2853eb89 1442 * @netdev: pointer to net device structure
9a799d71
AK		 1443 *
1444 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1445 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1446 * registers for the first multicast addresses, and hashes the rest into the
1447 * multicast table.
1448 **/
2853eb89
JP		 1449s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1450 struct net_device *netdev)
9a799d71 1451{
22bedad3 1452 struct netdev_hw_addr *ha;
9a799d71 1453 u32 i;
9a799d71
AK		 1454
1455 /*
1456 * Set the new number of MC addresses that we are being requested to
1457 * use.
1458 */
2853eb89 1459 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 1460 hw->addr_ctrl.mta_in_use = 0;
1461
80960ab0 1462 /* Clear mta_shadow */
9a799d71 1463 hw_dbg(hw, " Clearing MTA\n");
80960ab0 1464 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 1465
80960ab0 1466 /* Update mta shadow */
22bedad3 1467 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 1468 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 1469 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 1470 }
1471
1472 /* Enable mta */
80960ab0
ET		 1473 for (i = 0; i < hw->mac.mcft_size; i++)
1474 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
1475 hw->mac.mta_shadow[i]);
1476
9a799d71
AK		 1477 if (hw->addr_ctrl.mta_in_use > 0)
1478 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 1479 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 1480
c44ade9e 1481 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1482 return 0;
1483}
1484
1485/**
c44ade9e 1486 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 1487 * @hw: pointer to hardware structure
1488 *
c44ade9e 1489 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 1490 **/
c44ade9e 1491s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1492{
c44ade9e 1493 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 1494
c44ade9e
JB		 1495 if (a->mta_in_use > 0)
1496 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1497 hw->mac.mc_filter_type);
9a799d71
AK		 1498
1499 return 0;
1500}
1501
1502/**
c44ade9e 1503 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 1504 * @hw: pointer to hardware structure
9a799d71 1505 *
c44ade9e 1506 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 1507 **/
c44ade9e 1508s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1509{
c44ade9e 1510 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 1511
c44ade9e
JB		 1512 if (a->mta_in_use > 0)
1513 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 1514
1515 return 0;
1516}
1517
11afc1b1 1518/**
620fa036 1519 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1
PW		 1520 * @hw: pointer to hardware structure
1521 * @packetbuf_num: packet buffer number (0-7)
1522 *
1523 * Enable flow control according to the current settings.
1524 **/
620fa036 1525s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1526{
1527 s32 ret_val = 0;
620fa036 1528 u32 mflcn_reg, fccfg_reg;
11afc1b1 1529 u32 reg;
70b77628 1530 u32 rx_pba_size;
16b61beb 1531 u32 fcrtl, fcrth;
70b77628
PWJ		 1532
1533#ifdef CONFIG_DCB
1534 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1535 goto out;
1536
1537#endif /* CONFIG_DCB */
620fa036
MC		 1538 /* Negotiate the fc mode to use */
1539 ret_val = ixgbe_fc_autoneg(hw);
1540 if (ret_val)
1541 goto out;
11afc1b1 1542
620fa036 1543 /* Disable any previous flow control settings */
11afc1b1
PW		 1544 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1545 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1546
1547 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1548 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1549
1550 /*
1551 * The possible values of fc.current_mode are:
1552 * 0: Flow control is completely disabled
1553 * 1: Rx flow control is enabled (we can receive pause frames,
1554 * but not send pause frames).
bb3daa4a
PW		 1555 * 2: Tx flow control is enabled (we can send pause frames but
1556 * we do not support receiving pause frames).
11afc1b1 1557 * 3: Both Rx and Tx flow control (symmetric) are enabled.
8c7bea32 1558#ifdef CONFIG_DCB
bb3daa4a 1559 * 4: Priority Flow Control is enabled.
8c7bea32 1560#endif
11afc1b1
PW		 1561 * other: Invalid.
1562 */
1563 switch (hw->fc.current_mode) {
1564 case ixgbe_fc_none:
620fa036
MC		 1565 /*
1566 * Flow control is disabled by software override or autoneg.
1567 * The code below will actually disable it in the HW.
1568 */
11afc1b1
PW		 1569 break;
1570 case ixgbe_fc_rx_pause:
1571 /*
1572 * Rx Flow control is enabled and Tx Flow control is
1573 * disabled by software override. Since there really
1574 * isn't a way to advertise that we are capable of RX
1575 * Pause ONLY, we will advertise that we support both
1576 * symmetric and asymmetric Rx PAUSE. Later, we will
1577 * disable the adapter's ability to send PAUSE frames.
1578 */
1579 mflcn_reg |= IXGBE_MFLCN_RFCE;
1580 break;
1581 case ixgbe_fc_tx_pause:
1582 /*
1583 * Tx Flow control is enabled, and Rx Flow control is
1584 * disabled by software override.
1585 */
1586 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1587 break;
1588 case ixgbe_fc_full:
1589 /* Flow control (both Rx and Tx) is enabled by SW override. */
1590 mflcn_reg |= IXGBE_MFLCN_RFCE;
1591 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1592 break;
bb3daa4a
PW		 1593#ifdef CONFIG_DCB
1594 case ixgbe_fc_pfc:
1595 goto out;
1596 break;
620fa036 1597#endif /* CONFIG_DCB */
11afc1b1
PW		 1598 default:
1599 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 1600 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 1601 goto out;
1602 break;
1603 }
1604
620fa036 1605 /* Set 802.3x based flow control settings. */
2132d381 1606 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 1607 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1608 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1609
16b61beb
JF		 1610 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1611 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
620fa036 1612
16b61beb
JF		 1613 fcrth = (rx_pba_size - hw->fc.high_water) << 10;
1614 fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
264857b8 1615
16b61beb
JF		 1616 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1617 fcrth |= IXGBE_FCRTH_FCEN;
1618 if (hw->fc.send_xon)
1619 fcrtl |= IXGBE_FCRTL_XONE;
11afc1b1
PW		 1620 }
1621
16b61beb
JF		 1622 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
1623 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
1624
11afc1b1 1625 /* Configure pause time (2 TCs per register) */
70b77628 1626 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
11afc1b1
PW		 1627 if ((packetbuf_num & 1) == 0)
1628 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1629 else
1630 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1631 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1632
1633 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1634
1635out:
1636 return ret_val;
1637}
1638
0ecc061d
PWJ		 1639/**
1640 * ixgbe_fc_autoneg - Configure flow control
1641 * @hw: pointer to hardware structure
1642 *
620fa036
MC		 1643 * Compares our advertised flow control capabilities to those advertised by
1644 * our link partner, and determines the proper flow control mode to use.
0ecc061d
PWJ		 1645 **/
1646s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1647{
1648 s32 ret_val = 0;
620fa036
MC		 1649 ixgbe_link_speed speed;
1650 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
539e5f02 1651 u32 links2, anlp1_reg, autoc_reg, links;
620fa036 1652 bool link_up;
0ecc061d
PWJ		 1653
1654 /*
620fa036
MC		 1655 * AN should have completed when the cable was plugged in.
1656 * Look for reasons to bail out. Bail out if:
1657 * - FC autoneg is disabled, or if
539e5f02 1658 * - link is not up.
620fa036 1659 *
539e5f02 1660 * Since we're being called from an LSC, link is already known to be up.
620fa036 1661 * So use link_up_wait_to_complete=false.
0ecc061d 1662 */
620fa036 1663 hw->mac.ops.check_link(hw, &speed, &link_up, false);
539e5f02
PWJ		 1664
1665 if (hw->fc.disable_fc_autoneg || (!link_up)) {
620fa036
MC		 1666 hw->fc.fc_was_autonegged = false;
1667 hw->fc.current_mode = hw->fc.requested_mode;
0ecc061d
PWJ		 1668 goto out;
1669 }
1670
539e5f02
PWJ		 1671 /*
1672 * On backplane, bail out if
1673 * - backplane autoneg was not completed, or if
000c486d 1674 * - we are 82599 and link partner is not AN enabled
539e5f02
PWJ		 1675 */
1676 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1677 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
000c486d 1678 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
539e5f02
PWJ		 1679 hw->fc.fc_was_autonegged = false;
1680 hw->fc.current_mode = hw->fc.requested_mode;
1681 goto out;
1682 }
000c486d
DS		 1683
1684 if (hw->mac.type == ixgbe_mac_82599EB) {
1685 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
1686 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
1687 hw->fc.fc_was_autonegged = false;
1688 hw->fc.current_mode = hw->fc.requested_mode;
1689 goto out;
1690 }
1691 }
539e5f02
PWJ		 1692 }
1693
1694 /*
1695 * On multispeed fiber at 1g, bail out if
1696 * - link is up but AN did not complete, or if
1697 * - link is up and AN completed but timed out
1698 */
1699 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) {
1700 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1701 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1702 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1703 hw->fc.fc_was_autonegged = false;
1704 hw->fc.current_mode = hw->fc.requested_mode;
1705 goto out;
1706 }
1707 }
1708
9bbe3a57
PW		 1709 /*
1710 * Bail out on
1711 * - copper or CX4 adapters
1712 * - fiber adapters running at 10gig
1713 */
1714 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
1715 (hw->phy.media_type == ixgbe_media_type_cx4) ||
1716 ((hw->phy.media_type == ixgbe_media_type_fiber) &&
1717 (speed == IXGBE_LINK_SPEED_10GB_FULL))) {
1718 hw->fc.fc_was_autonegged = false;
1719 hw->fc.current_mode = hw->fc.requested_mode;
1720 goto out;
1721 }
1722
0ecc061d
PWJ		 1723 /*
1724 * Read the AN advertisement and LP ability registers and resolve
1725 * local flow control settings accordingly
1726 */
539e5f02
PWJ		 1727 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1728 (hw->phy.media_type != ixgbe_media_type_backplane)) {
1729 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1730 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1731 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1732 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1733 /*
1734 * Now we need to check if the user selected Rx ONLY
1735 * of pause frames. In this case, we had to advertise
1736 * FULL flow control because we could not advertise RX
1737 * ONLY. Hence, we must now check to see if we need to
1738 * turn OFF the TRANSMISSION of PAUSE frames.
1739 */
1740 if (hw->fc.requested_mode == ixgbe_fc_full) {
1741 hw->fc.current_mode = ixgbe_fc_full;
1742 hw_dbg(hw, "Flow Control = FULL.\n");
1743 } else {
1744 hw->fc.current_mode = ixgbe_fc_rx_pause;
1745 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1746 }
1747 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1748 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1749 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1750 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1751 hw->fc.current_mode = ixgbe_fc_tx_pause;
1752 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1753 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1754 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1755 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1756 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1757 hw->fc.current_mode = ixgbe_fc_rx_pause;
1758 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1759 } else {
1760 hw->fc.current_mode = ixgbe_fc_none;
1761 hw_dbg(hw, "Flow Control = NONE.\n");
1762 }
1763 }
1764
1765 if (hw->phy.media_type == ixgbe_media_type_backplane) {
0ecc061d 1766 /*
539e5f02
PWJ		 1767 * Read the 10g AN autoc and LP ability registers and resolve
1768 * local flow control settings accordingly
0ecc061d 1769 */
539e5f02
PWJ		 1770 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1771 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
1772
1773 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1774 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) {
1775 /*
1776 * Now we need to check if the user selected Rx ONLY
1777 * of pause frames. In this case, we had to advertise
1778 * FULL flow control because we could not advertise RX
1779 * ONLY. Hence, we must now check to see if we need to
1780 * turn OFF the TRANSMISSION of PAUSE frames.
1781 */
1782 if (hw->fc.requested_mode == ixgbe_fc_full) {
1783 hw->fc.current_mode = ixgbe_fc_full;
1784 hw_dbg(hw, "Flow Control = FULL.\n");
1785 } else {
1786 hw->fc.current_mode = ixgbe_fc_rx_pause;
1787 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1788 }
1789 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1790 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1791 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1792 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
1793 hw->fc.current_mode = ixgbe_fc_tx_pause;
1794 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1795 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1796 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1797 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1798 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
0ecc061d
PWJ		 1799 hw->fc.current_mode = ixgbe_fc_rx_pause;
1800 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
539e5f02
PWJ		 1801 } else {
1802 hw->fc.current_mode = ixgbe_fc_none;
1803 hw_dbg(hw, "Flow Control = NONE.\n");
0ecc061d 1804 }
0ecc061d 1805 }
620fa036
MC		 1806 /* Record that current_mode is the result of a successful autoneg */
1807 hw->fc.fc_was_autonegged = true;
1808
0ecc061d
PWJ		 1809out:
1810 return ret_val;
1811}
1812
11afc1b1 1813/**
620fa036 1814 * ixgbe_setup_fc - Set up flow control
11afc1b1
PW		 1815 * @hw: pointer to hardware structure
1816 *
620fa036 1817 * Called at init time to set up flow control.
11afc1b1 1818 **/
7b25cdba 1819static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1820{
1821 s32 ret_val = 0;
620fa036 1822 u32 reg;
11afc1b1 1823
bb3daa4a
PW		 1824#ifdef CONFIG_DCB
1825 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1826 hw->fc.current_mode = hw->fc.requested_mode;
1827 goto out;
1828 }
1829
1830#endif
11afc1b1
PW		 1831 /* Validate the packetbuf configuration */
1832 if (packetbuf_num < 0 || packetbuf_num > 7) {
1833 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1834 "is 0-7\n", packetbuf_num);
1835 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1836 goto out;
1837 }
1838
1839 /*
1840 * Validate the water mark configuration. Zero water marks are invalid
1841 * because it causes the controller to just blast out fc packets.
1842 */
1843 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
620fa036
MC		 1844 hw_dbg(hw, "Invalid water mark configuration\n");
1845 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1846 goto out;
11afc1b1
PW		 1847 }
1848
1849 /*
1850 * Validate the requested mode. Strict IEEE mode does not allow
620fa036 1851 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
11afc1b1
PW		 1852 */
1853 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1854 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1855 "IEEE mode\n");
1856 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1857 goto out;
1858 }
1859
1860 /*
1861 * 10gig parts do not have a word in the EEPROM to determine the
1862 * default flow control setting, so we explicitly set it to full.
1863 */
1864 if (hw->fc.requested_mode == ixgbe_fc_default)
1865 hw->fc.requested_mode = ixgbe_fc_full;
1866
1867 /*
620fa036
MC		 1868 * Set up the 1G flow control advertisement registers so the HW will be
1869 * able to do fc autoneg once the cable is plugged in. If we end up
1870 * using 10g instead, this is harmless.
11afc1b1 1871 */
620fa036 1872 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
11afc1b1 1873
620fa036
MC		 1874 /*
1875 * The possible values of fc.requested_mode are:
1876 * 0: Flow control is completely disabled
1877 * 1: Rx flow control is enabled (we can receive pause frames,
1878 * but not send pause frames).
1879 * 2: Tx flow control is enabled (we can send pause frames but
1880 * we do not support receiving pause frames).
1881 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1882#ifdef CONFIG_DCB
1883 * 4: Priority Flow Control is enabled.
1884#endif
1885 * other: Invalid.
1886 */
1887 switch (hw->fc.requested_mode) {
1888 case ixgbe_fc_none:
1889 /* Flow control completely disabled by software override. */
1890 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1891 break;
1892 case ixgbe_fc_rx_pause:
1893 /*
1894 * Rx Flow control is enabled and Tx Flow control is
1895 * disabled by software override. Since there really
1896 * isn't a way to advertise that we are capable of RX
1897 * Pause ONLY, we will advertise that we support both
1898 * symmetric and asymmetric Rx PAUSE. Later, we will
1899 * disable the adapter's ability to send PAUSE frames.
1900 */
1901 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1902 break;
1903 case ixgbe_fc_tx_pause:
1904 /*
1905 * Tx Flow control is enabled, and Rx Flow control is
1906 * disabled by software override.
1907 */
1908 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1909 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1910 break;
1911 case ixgbe_fc_full:
1912 /* Flow control (both Rx and Tx) is enabled by SW override. */
1913 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1914 break;
1915#ifdef CONFIG_DCB
1916 case ixgbe_fc_pfc:
11afc1b1 1917 goto out;
620fa036
MC		 1918 break;
1919#endif /* CONFIG_DCB */
1920 default:
1921 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 1922 ret_val = IXGBE_ERR_CONFIG;
620fa036
MC		 1923 goto out;
1924 break;
1925 }
1926
1927 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
1928 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
11afc1b1 1929
620fa036
MC		 1930 /* Disable AN timeout */
1931 if (hw->fc.strict_ieee)
1932 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
1933
1934 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
1935 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
11afc1b1 1936
539e5f02
PWJ		 1937 /*
1938 * Set up the 10G flow control advertisement registers so the HW
1939 * can do fc autoneg once the cable is plugged in. If we end up
1940 * using 1g instead, this is harmless.
1941 */
1942 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1943
1944 /*
1945 * The possible values of fc.requested_mode are:
1946 * 0: Flow control is completely disabled
1947 * 1: Rx flow control is enabled (we can receive pause frames,
1948 * but not send pause frames).
1949 * 2: Tx flow control is enabled (we can send pause frames but
1950 * we do not support receiving pause frames).
1951 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1952 * other: Invalid.
1953 */
1954 switch (hw->fc.requested_mode) {
1955 case ixgbe_fc_none:
1956 /* Flow control completely disabled by software override. */
1957 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
1958 break;
1959 case ixgbe_fc_rx_pause:
1960 /*
1961 * Rx Flow control is enabled and Tx Flow control is
1962 * disabled by software override. Since there really
1963 * isn't a way to advertise that we are capable of RX
1964 * Pause ONLY, we will advertise that we support both
1965 * symmetric and asymmetric Rx PAUSE. Later, we will
1966 * disable the adapter's ability to send PAUSE frames.
1967 */
1968 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
1969 break;
1970 case ixgbe_fc_tx_pause:
1971 /*
1972 * Tx Flow control is enabled, and Rx Flow control is
1973 * disabled by software override.
1974 */
1975 reg |= (IXGBE_AUTOC_ASM_PAUSE);
1976 reg &= ~(IXGBE_AUTOC_SYM_PAUSE);
1977 break;
1978 case ixgbe_fc_full:
1979 /* Flow control (both Rx and Tx) is enabled by SW override. */
1980 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
1981 break;
1982#ifdef CONFIG_DCB
1983 case ixgbe_fc_pfc:
1984 goto out;
1985 break;
1986#endif /* CONFIG_DCB */
1987 default:
1988 hw_dbg(hw, "Flow control param set incorrectly\n");
1989 ret_val = IXGBE_ERR_CONFIG;
1990 goto out;
1991 break;
1992 }
1993 /*
1994 * AUTOC restart handles negotiation of 1G and 10G. There is
1995 * no need to set the PCS1GCTL register.
1996 */
1997 reg |= IXGBE_AUTOC_AN_RESTART;
1998 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg);
1999 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2000
11afc1b1
PW		 2001out:
2002 return ret_val;
2003}
2004
9a799d71
AK		 2005/**
2006 * ixgbe_disable_pcie_master - Disable PCI-express master access
2007 * @hw: pointer to hardware structure
2008 *
2009 * Disables PCI-Express master access and verifies there are no pending
2010 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2011 * bit hasn't caused the master requests to be disabled, else 0
2012 * is returned signifying master requests disabled.
2013 **/
2014s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2015{
a4297dc2 2016 struct ixgbe_adapter *adapter = hw->back;
c44ade9e
JB		 2017 u32 i;
2018 u32 reg_val;
2019 u32 number_of_queues;
a4297dc2
ET		 2020 s32 status = 0;
2021 u16 dev_status = 0;
2022
2023 /* Just jump out if bus mastering is already disabled */
2024 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2025 goto out;
9a799d71 2026
c44ade9e
JB		 2027 /* Disable the receive unit by stopping each queue */
2028 number_of_queues = hw->mac.max_rx_queues;
2029 for (i = 0; i < number_of_queues; i++) {
2030 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2031 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2032 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2033 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2034 }
2035 }
2036
2037 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2038 reg_val |= IXGBE_CTRL_GIO_DIS;
2039 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
9a799d71
AK		 2040
2041 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2
ET		 2042 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2043 goto check_device_status;
2044 udelay(100);
2045 }
2046
2047 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2048 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2049
2050 /*
2051 * Before proceeding, make sure that the PCIe block does not have
2052 * transactions pending.
2053 */
2054check_device_status:
2055 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2056 pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
2057 &dev_status);
2058 if (!(dev_status & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
9a799d71 2059 break;
9a799d71
AK		 2060 udelay(100);
2061 }
2062
a4297dc2
ET		 2063 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
2064 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2065 else
2066 goto out;
2067
2068 /*
2069 * Two consecutive resets are required via CTRL.RST per datasheet
2070 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2071 * of this need. The first reset prevents new master requests from
2072 * being issued by our device. We then must wait 1usec for any
2073 * remaining completions from the PCIe bus to trickle in, and then reset
2074 * again to clear out any effects they may have had on our device.
2075 */
2076 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2077
2078out:
9a799d71
AK		 2079 return status;
2080}
2081
2082
2083/**
c44ade9e 2084 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2085 * @hw: pointer to hardware structure
c44ade9e 2086 * @mask: Mask to specify which semaphore to acquire
9a799d71 2087 *
c44ade9e 2088 * Acquires the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 2089 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2090 **/
2091s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2092{
2093 u32 gssr;
2094 u32 swmask = mask;
2095 u32 fwmask = mask << 5;
2096 s32 timeout = 200;
2097
2098 while (timeout) {
dbf893ee
ET		 2099 /*
2100 * SW EEPROM semaphore bit is used for access to all
2101 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2102 */
9a799d71 2103 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2104 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2105
2106 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2107 if (!(gssr & (fwmask | swmask)))
2108 break;
2109
2110 /*
2111 * Firmware currently using resource (fwmask) or other software
2112 * thread currently using resource (swmask)
2113 */
2114 ixgbe_release_eeprom_semaphore(hw);
2115 msleep(5);
2116 timeout--;
2117 }
2118
2119 if (!timeout) {
dbf893ee 2120 hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
539e5f02 2121 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2122 }
2123
2124 gssr |= swmask;
2125 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2126
2127 ixgbe_release_eeprom_semaphore(hw);
2128 return 0;
2129}
2130
2131/**
2132 * ixgbe_release_swfw_sync - Release SWFW semaphore
2133 * @hw: pointer to hardware structure
c44ade9e 2134 * @mask: Mask to specify which semaphore to release
9a799d71 2135 *
c44ade9e 2136 * Releases the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 2137 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2138 **/
2139void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2140{
2141 u32 gssr;
2142 u32 swmask = mask;
2143
2144 ixgbe_get_eeprom_semaphore(hw);
2145
2146 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2147 gssr &= ~swmask;
2148 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2149
2150 ixgbe_release_eeprom_semaphore(hw);
2151}
2152
11afc1b1
PW		 2153/**
2154 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2155 * @hw: pointer to hardware structure
2156 * @regval: register value to write to RXCTRL
2157 *
2158 * Enables the Rx DMA unit
2159 **/
2160s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2161{
2162 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2163
2164 return 0;
2165}
87c12017
PW		 2166
2167/**
2168 * ixgbe_blink_led_start_generic - Blink LED based on index.
2169 * @hw: pointer to hardware structure
2170 * @index: led number to blink
2171 **/
2172s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2173{
2174 ixgbe_link_speed speed = 0;
2175 bool link_up = 0;
2176 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2177 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2178
2179 /*
2180 * Link must be up to auto-blink the LEDs;
2181 * Force it if link is down.
2182 */
2183 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2184
2185 if (!link_up) {
50ac58ba 2186 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017
PW		 2187 autoc_reg |= IXGBE_AUTOC_FLU;
2188 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2189 msleep(10);
2190 }
2191
2192 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2193 led_reg |= IXGBE_LED_BLINK(index);
2194 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2195 IXGBE_WRITE_FLUSH(hw);
2196
2197 return 0;
2198}
2199
2200/**
2201 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2202 * @hw: pointer to hardware structure
2203 * @index: led number to stop blinking
2204 **/
2205s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2206{
2207 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2208 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2209
2210 autoc_reg &= ~IXGBE_AUTOC_FLU;
2211 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2212 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2213
2214 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2215 led_reg &= ~IXGBE_LED_BLINK(index);
2216 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2217 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2218 IXGBE_WRITE_FLUSH(hw);
2219
2220 return 0;
2221}
21ce849b
MC		 2222
2223/**
2224 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2225 * @hw: pointer to hardware structure
2226 * @san_mac_offset: SAN MAC address offset
2227 *
2228 * This function will read the EEPROM location for the SAN MAC address
2229 * pointer, and returns the value at that location. This is used in both
2230 * get and set mac_addr routines.
2231 **/
2232static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2233 u16 *san_mac_offset)
2234{
2235 /*
2236 * First read the EEPROM pointer to see if the MAC addresses are
2237 * available.
2238 */
2239 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2240
2241 return 0;
2242}
2243
2244/**
2245 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2246 * @hw: pointer to hardware structure
2247 * @san_mac_addr: SAN MAC address
2248 *
2249 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2250 * per-port, so set_lan_id() must be called before reading the addresses.
2251 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2252 * upon for non-SFP connections, so we must call it here.
2253 **/
2254s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2255{
2256 u16 san_mac_data, san_mac_offset;
2257 u8 i;
2258
2259 /*
2260 * First read the EEPROM pointer to see if the MAC addresses are
2261 * available. If they're not, no point in calling set_lan_id() here.
2262 */
2263 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2264
2265 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2266 /*
2267 * No addresses available in this EEPROM. It's not an
2268 * error though, so just wipe the local address and return.
2269 */
2270 for (i = 0; i < 6; i++)
2271 san_mac_addr[i] = 0xFF;
2272
2273 goto san_mac_addr_out;
2274 }
2275
2276 /* make sure we know which port we need to program */
2277 hw->mac.ops.set_lan_id(hw);
2278 /* apply the port offset to the address offset */
2279 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2280 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2281 for (i = 0; i < 3; i++) {
2282 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2283 san_mac_addr[i * 2] = (u8)(san_mac_data);
2284 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2285 san_mac_offset++;
2286 }
2287
2288san_mac_addr_out:
2289 return 0;
2290}
2291
2292/**
2293 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2294 * @hw: pointer to hardware structure
2295 *
2296 * Read PCIe configuration space, and get the MSI-X vector count from
2297 * the capabilities table.
2298 **/
2299u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2300{
2301 struct ixgbe_adapter *adapter = hw->back;
2302 u16 msix_count;
2303 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
2304 &msix_count);
2305 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2306
2307 /* MSI-X count is zero-based in HW, so increment to give proper value */
2308 msix_count++;
2309
2310 return msix_count;
2311}
2312
2313/**
2314 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2315 * @hw: pointer to hardware struct
2316 * @rar: receive address register index to disassociate
2317 * @vmdq: VMDq pool index to remove from the rar
2318 **/
2319s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2320{
2321 u32 mpsar_lo, mpsar_hi;
2322 u32 rar_entries = hw->mac.num_rar_entries;
2323
c700f4e6
ET		 2324 /* Make sure we are using a valid rar index range */
2325 if (rar >= rar_entries) {
2326 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2327 return IXGBE_ERR_INVALID_ARGUMENT;
2328 }
21ce849b 2329
c700f4e6
ET		 2330 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2331 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2332
c700f4e6
ET		 2333 if (!mpsar_lo && !mpsar_hi)
2334 goto done;
21ce849b 2335
c700f4e6
ET		 2336 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2337 if (mpsar_lo) {
2338 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2339 mpsar_lo = 0;
2340 }
2341 if (mpsar_hi) {
2342 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2343 mpsar_hi = 0;
2344 }
2345 } else if (vmdq < 32) {
2346 mpsar_lo &= ~(1 << vmdq);
2347 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2348 } else {
c700f4e6
ET		 2349 mpsar_hi &= ~(1 << (vmdq - 32));
2350 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2351 }
2352
c700f4e6
ET		 2353 /* was that the last pool using this rar? */
2354 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2355 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2356done:
2357 return 0;
2358}
2359
2360/**
2361 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2362 * @hw: pointer to hardware struct
2363 * @rar: receive address register index to associate with a VMDq index
2364 * @vmdq: VMDq pool index
2365 **/
2366s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2367{
2368 u32 mpsar;
2369 u32 rar_entries = hw->mac.num_rar_entries;
2370
c700f4e6
ET		 2371 /* Make sure we are using a valid rar index range */
2372 if (rar >= rar_entries) {
21ce849b 2373 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2374 return IXGBE_ERR_INVALID_ARGUMENT;
2375 }
2376
2377 if (vmdq < 32) {
2378 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2379 mpsar |= 1 << vmdq;
2380 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2381 } else {
2382 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2383 mpsar |= 1 << (vmdq - 32);
2384 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2385 }
2386 return 0;
2387}
2388
2389/**
2390 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2391 * @hw: pointer to hardware structure
2392 **/
2393s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2394{
2395 int i;
2396
21ce849b
MC		 2397 for (i = 0; i < 128; i++)
2398 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2399
2400 return 0;
2401}
2402
2403/**
2404 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2405 * @hw: pointer to hardware structure
2406 * @vlan: VLAN id to write to VLAN filter
2407 *
2408 * return the VLVF index where this VLAN id should be placed
2409 *
2410 **/
5d5b7c39 2411static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 2412{
2413 u32 bits = 0;
2414 u32 first_empty_slot = 0;
2415 s32 regindex;
2416
2417 /* short cut the special case */
2418 if (vlan == 0)
2419 return 0;
2420
2421 /*
2422 * Search for the vlan id in the VLVF entries. Save off the first empty
2423 * slot found along the way
2424 */
2425 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2426 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2427 if (!bits && !(first_empty_slot))
2428 first_empty_slot = regindex;
2429 else if ((bits & 0x0FFF) == vlan)
2430 break;
2431 }
2432
2433 /*
2434 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2435 * in the VLVF. Else use the first empty VLVF register for this
2436 * vlan id.
2437 */
2438 if (regindex >= IXGBE_VLVF_ENTRIES) {
2439 if (first_empty_slot)
2440 regindex = first_empty_slot;
2441 else {
2442 hw_dbg(hw, "No space in VLVF.\n");
2443 regindex = IXGBE_ERR_NO_SPACE;
2444 }
2445 }
2446
2447 return regindex;
2448}
2449
2450/**
2451 * ixgbe_set_vfta_generic - Set VLAN filter table
2452 * @hw: pointer to hardware structure
2453 * @vlan: VLAN id to write to VLAN filter
2454 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2455 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2456 *
2457 * Turn on/off specified VLAN in the VLAN filter table.
2458 **/
2459s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
2460 bool vlan_on)
2461{
2462 s32 regindex;
2463 u32 bitindex;
2464 u32 vfta;
2465 u32 bits;
2466 u32 vt;
2467 u32 targetbit;
2468 bool vfta_changed = false;
2469
2470 if (vlan > 4095)
2471 return IXGBE_ERR_PARAM;
2472
2473 /*
2474 * this is a 2 part operation - first the VFTA, then the
2475 * VLVF and VLVFB if VT Mode is set
2476 * We don't write the VFTA until we know the VLVF part succeeded.
2477 */
2478
2479 /* Part 1
2480 * The VFTA is a bitstring made up of 128 32-bit registers
2481 * that enable the particular VLAN id, much like the MTA:
2482 * bits[11-5]: which register
2483 * bits[4-0]: which bit in the register
2484 */
2485 regindex = (vlan >> 5) & 0x7F;
2486 bitindex = vlan & 0x1F;
2487 targetbit = (1 << bitindex);
2488 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
2489
2490 if (vlan_on) {
2491 if (!(vfta & targetbit)) {
2492 vfta |= targetbit;
2493 vfta_changed = true;
2494 }
2495 } else {
2496 if ((vfta & targetbit)) {
2497 vfta &= ~targetbit;
2498 vfta_changed = true;
2499 }
2500 }
2501
2502 /* Part 2
2503 * If VT Mode is set
2504 * Either vlan_on
2505 * make sure the vlan is in VLVF
2506 * set the vind bit in the matching VLVFB
2507 * Or !vlan_on
2508 * clear the pool bit and possibly the vind
2509 */
2510 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2511 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
2512 s32 vlvf_index;
2513
2514 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
2515 if (vlvf_index < 0)
2516 return vlvf_index;
2517
2518 if (vlan_on) {
2519 /* set the pool bit */
2520 if (vind < 32) {
2521 bits = IXGBE_READ_REG(hw,
2522 IXGBE_VLVFB(vlvf_index*2));
2523 bits |= (1 << vind);
2524 IXGBE_WRITE_REG(hw,
2525 IXGBE_VLVFB(vlvf_index*2),
2526 bits);
2527 } else {
2528 bits = IXGBE_READ_REG(hw,
2529 IXGBE_VLVFB((vlvf_index*2)+1));
2530 bits |= (1 << (vind-32));
2531 IXGBE_WRITE_REG(hw,
2532 IXGBE_VLVFB((vlvf_index*2)+1),
2533 bits);
2534 }
2535 } else {
2536 /* clear the pool bit */
2537 if (vind < 32) {
2538 bits = IXGBE_READ_REG(hw,
2539 IXGBE_VLVFB(vlvf_index*2));
2540 bits &= ~(1 << vind);
2541 IXGBE_WRITE_REG(hw,
2542 IXGBE_VLVFB(vlvf_index*2),
2543 bits);
2544 bits |= IXGBE_READ_REG(hw,
2545 IXGBE_VLVFB((vlvf_index*2)+1));
2546 } else {
2547 bits = IXGBE_READ_REG(hw,
2548 IXGBE_VLVFB((vlvf_index*2)+1));
2549 bits &= ~(1 << (vind-32));
2550 IXGBE_WRITE_REG(hw,
2551 IXGBE_VLVFB((vlvf_index*2)+1),
2552 bits);
2553 bits |= IXGBE_READ_REG(hw,
2554 IXGBE_VLVFB(vlvf_index*2));
2555 }
2556 }
2557
2558 /*
2559 * If there are still bits set in the VLVFB registers
2560 * for the VLAN ID indicated we need to see if the
2561 * caller is requesting that we clear the VFTA entry bit.
2562 * If the caller has requested that we clear the VFTA
2563 * entry bit but there are still pools/VFs using this VLAN
2564 * ID entry then ignore the request. We're not worried
2565 * about the case where we're turning the VFTA VLAN ID
2566 * entry bit on, only when requested to turn it off as
2567 * there may be multiple pools and/or VFs using the
2568 * VLAN ID entry. In that case we cannot clear the
2569 * VFTA bit until all pools/VFs using that VLAN ID have also
2570 * been cleared. This will be indicated by "bits" being
2571 * zero.
2572 */
2573 if (bits) {
2574 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
2575 (IXGBE_VLVF_VIEN | vlan));
2576 if (!vlan_on) {
2577 /* someone wants to clear the vfta entry
2578 * but some pools/VFs are still using it.
2579 * Ignore it. */
2580 vfta_changed = false;
2581 }
2582 }
2583 else
2584 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
2585 }
2586
2587 if (vfta_changed)
2588 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
2589
2590 return 0;
2591}
2592
2593/**
2594 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2595 * @hw: pointer to hardware structure
2596 *
2597 * Clears the VLAN filer table, and the VMDq index associated with the filter
2598 **/
2599s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
2600{
2601 u32 offset;
2602
2603 for (offset = 0; offset < hw->mac.vft_size; offset++)
2604 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
2605
2606 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
2607 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
2608 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
2609 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
2610 }
2611
2612 return 0;
2613}
2614
2615/**
2616 * ixgbe_check_mac_link_generic - Determine link and speed status
2617 * @hw: pointer to hardware structure
2618 * @speed: pointer to link speed
2619 * @link_up: true when link is up
2620 * @link_up_wait_to_complete: bool used to wait for link up or not
2621 *
2622 * Reads the links register to determine if link is up and the current speed
2623 **/
2624s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 2625 bool *link_up, bool link_up_wait_to_complete)
21ce849b 2626{
48de36c5 2627 u32 links_reg, links_orig;
21ce849b
MC		 2628 u32 i;
2629
48de36c5
ET		 2630 /* clear the old state */
2631 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
2632
21ce849b 2633 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 2634
2635 if (links_orig != links_reg) {
2636 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
2637 links_orig, links_reg);
2638 }
2639
21ce849b
MC		 2640 if (link_up_wait_to_complete) {
2641 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
2642 if (links_reg & IXGBE_LINKS_UP) {
2643 *link_up = true;
2644 break;
2645 } else {
2646 *link_up = false;
2647 }
2648 msleep(100);
2649 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
2650 }
2651 } else {
2652 if (links_reg & IXGBE_LINKS_UP)
2653 *link_up = true;
2654 else
2655 *link_up = false;
2656 }
2657
2658 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2659 IXGBE_LINKS_SPEED_10G_82599)
2660 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2661 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
63d778df 2662 IXGBE_LINKS_SPEED_1G_82599)
21ce849b 2663 *speed = IXGBE_LINK_SPEED_1GB_FULL;
63d778df
ET		 2664 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
2665 IXGBE_LINKS_SPEED_100_82599)
21ce849b 2666 *speed = IXGBE_LINK_SPEED_100_FULL;
63d778df
ET		 2667 else
2668 *speed = IXGBE_LINK_SPEED_UNKNOWN;
21ce849b
MC		 2669
2670 /* if link is down, zero out the current_mode */
2671 if (*link_up == false) {
2672 hw->fc.current_mode = ixgbe_fc_none;
2673 hw->fc.fc_was_autonegged = false;
2674 }
2675
2676 return 0;
2677}
a391f1d5
DS		 2678
2679/**
2680 * ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
2681 * the EEPROM
2682 * @hw: pointer to hardware structure
2683 * @wwnn_prefix: the alternative WWNN prefix
2684 * @wwpn_prefix: the alternative WWPN prefix
2685 *
2686 * This function will read the EEPROM from the alternative SAN MAC address
2687 * block to check the support for the alternative WWNN/WWPN prefix support.
2688 **/
2689s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
2690 u16 *wwpn_prefix)
2691{
2692 u16 offset, caps;
2693 u16 alt_san_mac_blk_offset;
2694
2695 /* clear output first */
2696 *wwnn_prefix = 0xFFFF;
2697 *wwpn_prefix = 0xFFFF;
2698
2699 /* check if alternative SAN MAC is supported */
2700 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
2701 &alt_san_mac_blk_offset);
2702
2703 if ((alt_san_mac_blk_offset == 0) ||
2704 (alt_san_mac_blk_offset == 0xFFFF))
2705 goto wwn_prefix_out;
2706
2707 /* check capability in alternative san mac address block */
2708 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2709 hw->eeprom.ops.read(hw, offset, &caps);
2710 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2711 goto wwn_prefix_out;
2712
2713 /* get the corresponding prefix for WWNN/WWPN */
2714 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2715 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
2716
2717 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2718 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
2719
2720wwn_prefix_out:
2721 return 0;
2722}
a985b6c3
GR		 2723
2724/**
2725 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2726 * @hw: pointer to hardware structure
2727 * @enable: enable or disable switch for anti-spoofing
2728 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
2729 *
2730 **/
2731void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
2732{
2733 int j;
2734 int pf_target_reg = pf >> 3;
2735 int pf_target_shift = pf % 8;
2736 u32 pfvfspoof = 0;
2737
2738 if (hw->mac.type == ixgbe_mac_82598EB)
2739 return;
2740
2741 if (enable)
2742 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
2743
2744 /*
2745 * PFVFSPOOF register array is size 8 with 8 bits assigned to
2746 * MAC anti-spoof enables in each register array element.
2747 */
2748 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
2749 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
2750
2751 /* If not enabling anti-spoofing then done */
2752 if (!enable)
2753 return;
2754
2755 /*
2756 * The PF should be allowed to spoof so that it can support
2757 * emulation mode NICs. Reset the bit assigned to the PF
2758 */
2759 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
2760 pfvfspoof ^= (1 << pf_target_shift);
2761 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
2762}
2763
2764/**
2765 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
2766 * @hw: pointer to hardware structure
2767 * @enable: enable or disable switch for VLAN anti-spoofing
2768 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
2769 *
2770 **/
2771void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
2772{
2773 int vf_target_reg = vf >> 3;
2774 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
2775 u32 pfvfspoof;
2776
2777 if (hw->mac.type == ixgbe_mac_82598EB)
2778 return;
2779
2780 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2781 if (enable)
2782 pfvfspoof |= (1 << vf_target_shift);
2783 else
2784 pfvfspoof &= ~(1 << vf_target_shift);
2785 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2786}
Linux kernel - Deliverables
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