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net: move address list functions to a separate file
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
ccffad25 31#include <linux/netdevice.h>
9a799d71 32
11afc1b1 33#include "ixgbe.h"
9a799d71
AK		 34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
9a799d71 37static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
c44ade9e 38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 41static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
44 u16 count);
45static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 49static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
50
c44ade9e
JB		 51static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
52static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
9a799d71 53static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
c44ade9e 54static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
7b25cdba 55static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
9a799d71
AK		 56
57/**
c44ade9e 58 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 59 * @hw: pointer to hardware structure
60 *
61 * Starts the hardware by filling the bus info structure and media type, clears
62 * all on chip counters, initializes receive address registers, multicast
63 * table, VLAN filter table, calls routine to set up link and flow control
64 * settings, and leaves transmit and receive units disabled and uninitialized
65 **/
c44ade9e 66s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 67{
68 u32 ctrl_ext;
69
70 /* Set the media type */
71 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
72
73 /* Identify the PHY */
c44ade9e 74 hw->phy.ops.identify(hw);
9a799d71 75
9a799d71 76 /* Clear the VLAN filter table */
c44ade9e 77 hw->mac.ops.clear_vfta(hw);
9a799d71 78
9a799d71 79 /* Clear statistics registers */
c44ade9e 80 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 81
82 /* Set No Snoop Disable */
83 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
84 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
85 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 86 IXGBE_WRITE_FLUSH(hw);
9a799d71 87
620fa036
MC		 88 /* Setup flow control */
89 ixgbe_setup_fc(hw, 0);
90
9a799d71
AK		 91 /* Clear adapter stopped flag */
92 hw->adapter_stopped = false;
93
94 return 0;
95}
96
97/**
c44ade9e 98 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 99 * @hw: pointer to hardware structure
100 *
c44ade9e 101 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 102 * structure and media type, clears all on chip counters, initializes receive
103 * address registers, multicast table, VLAN filter table, calls routine to set
104 * up link and flow control settings, and leaves transmit and receive units
105 * disabled and uninitialized
106 **/
c44ade9e 107s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 108{
794caeb2
PWJ		 109 s32 status;
110
9a799d71 111 /* Reset the hardware */
794caeb2 112 status = hw->mac.ops.reset_hw(hw);
9a799d71 113
794caeb2
PWJ		 114 if (status == 0) {
115 /* Start the HW */
116 status = hw->mac.ops.start_hw(hw);
117 }
9a799d71 118
794caeb2 119 return status;
9a799d71
AK		 120}
121
122/**
c44ade9e 123 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 124 * @hw: pointer to hardware structure
125 *
126 * Clears all hardware statistics counters by reading them from the hardware
127 * Statistics counters are clear on read.
128 **/
c44ade9e 129s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 130{
131 u16 i = 0;
132
133 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
134 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
135 IXGBE_READ_REG(hw, IXGBE_ERRBC);
136 IXGBE_READ_REG(hw, IXGBE_MSPDC);
137 for (i = 0; i < 8; i++)
138 IXGBE_READ_REG(hw, IXGBE_MPC(i));
139
140 IXGBE_READ_REG(hw, IXGBE_MLFC);
141 IXGBE_READ_REG(hw, IXGBE_MRFC);
142 IXGBE_READ_REG(hw, IXGBE_RLEC);
143 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
144 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
145 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
146 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
147
148 for (i = 0; i < 8; i++) {
149 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
150 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
151 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
152 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
153 }
154
155 IXGBE_READ_REG(hw, IXGBE_PRC64);
156 IXGBE_READ_REG(hw, IXGBE_PRC127);
157 IXGBE_READ_REG(hw, IXGBE_PRC255);
158 IXGBE_READ_REG(hw, IXGBE_PRC511);
159 IXGBE_READ_REG(hw, IXGBE_PRC1023);
160 IXGBE_READ_REG(hw, IXGBE_PRC1522);
161 IXGBE_READ_REG(hw, IXGBE_GPRC);
162 IXGBE_READ_REG(hw, IXGBE_BPRC);
163 IXGBE_READ_REG(hw, IXGBE_MPRC);
164 IXGBE_READ_REG(hw, IXGBE_GPTC);
165 IXGBE_READ_REG(hw, IXGBE_GORCL);
166 IXGBE_READ_REG(hw, IXGBE_GORCH);
167 IXGBE_READ_REG(hw, IXGBE_GOTCL);
168 IXGBE_READ_REG(hw, IXGBE_GOTCH);
169 for (i = 0; i < 8; i++)
170 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
171 IXGBE_READ_REG(hw, IXGBE_RUC);
172 IXGBE_READ_REG(hw, IXGBE_RFC);
173 IXGBE_READ_REG(hw, IXGBE_ROC);
174 IXGBE_READ_REG(hw, IXGBE_RJC);
175 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
176 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
177 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
178 IXGBE_READ_REG(hw, IXGBE_TORL);
179 IXGBE_READ_REG(hw, IXGBE_TORH);
180 IXGBE_READ_REG(hw, IXGBE_TPR);
181 IXGBE_READ_REG(hw, IXGBE_TPT);
182 IXGBE_READ_REG(hw, IXGBE_PTC64);
183 IXGBE_READ_REG(hw, IXGBE_PTC127);
184 IXGBE_READ_REG(hw, IXGBE_PTC255);
185 IXGBE_READ_REG(hw, IXGBE_PTC511);
186 IXGBE_READ_REG(hw, IXGBE_PTC1023);
187 IXGBE_READ_REG(hw, IXGBE_PTC1522);
188 IXGBE_READ_REG(hw, IXGBE_MPTC);
189 IXGBE_READ_REG(hw, IXGBE_BPTC);
190 for (i = 0; i < 16; i++) {
191 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
192 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
193 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
194 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
195 }
196
197 return 0;
198}
199
200/**
c44ade9e
JB		 201 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
202 * @hw: pointer to hardware structure
203 * @pba_num: stores the part number from the EEPROM
204 *
205 * Reads the part number from the EEPROM.
206 **/
207s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
208{
209 s32 ret_val;
210 u16 data;
211
212 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
213 if (ret_val) {
214 hw_dbg(hw, "NVM Read Error\n");
215 return ret_val;
216 }
217 *pba_num = (u32)(data << 16);
218
219 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
220 if (ret_val) {
221 hw_dbg(hw, "NVM Read Error\n");
222 return ret_val;
223 }
224 *pba_num |= data;
225
226 return 0;
227}
228
229/**
230 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 231 * @hw: pointer to hardware structure
232 * @mac_addr: Adapter MAC address
233 *
234 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
235 * A reset of the adapter must be performed prior to calling this function
236 * in order for the MAC address to have been loaded from the EEPROM into RAR0
237 **/
c44ade9e 238s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 239{
240 u32 rar_high;
241 u32 rar_low;
242 u16 i;
243
244 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
245 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
246
247 for (i = 0; i < 4; i++)
248 mac_addr[i] = (u8)(rar_low >> (i*8));
249
250 for (i = 0; i < 2; i++)
251 mac_addr[i+4] = (u8)(rar_high >> (i*8));
252
253 return 0;
254}
255
11afc1b1
PW		 256/**
257 * ixgbe_get_bus_info_generic - Generic set PCI bus info
258 * @hw: pointer to hardware structure
259 *
260 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
261 **/
262s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
263{
264 struct ixgbe_adapter *adapter = hw->back;
265 struct ixgbe_mac_info *mac = &hw->mac;
266 u16 link_status;
267
268 hw->bus.type = ixgbe_bus_type_pci_express;
269
270 /* Get the negotiated link width and speed from PCI config space */
271 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
272 &link_status);
273
274 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
275 case IXGBE_PCI_LINK_WIDTH_1:
276 hw->bus.width = ixgbe_bus_width_pcie_x1;
277 break;
278 case IXGBE_PCI_LINK_WIDTH_2:
279 hw->bus.width = ixgbe_bus_width_pcie_x2;
280 break;
281 case IXGBE_PCI_LINK_WIDTH_4:
282 hw->bus.width = ixgbe_bus_width_pcie_x4;
283 break;
284 case IXGBE_PCI_LINK_WIDTH_8:
285 hw->bus.width = ixgbe_bus_width_pcie_x8;
286 break;
287 default:
288 hw->bus.width = ixgbe_bus_width_unknown;
289 break;
290 }
291
292 switch (link_status & IXGBE_PCI_LINK_SPEED) {
293 case IXGBE_PCI_LINK_SPEED_2500:
294 hw->bus.speed = ixgbe_bus_speed_2500;
295 break;
296 case IXGBE_PCI_LINK_SPEED_5000:
297 hw->bus.speed = ixgbe_bus_speed_5000;
298 break;
299 default:
300 hw->bus.speed = ixgbe_bus_speed_unknown;
301 break;
302 }
303
304 mac->ops.set_lan_id(hw);
305
306 return 0;
307}
308
309/**
310 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
311 * @hw: pointer to the HW structure
312 *
313 * Determines the LAN function id by reading memory-mapped registers
314 * and swaps the port value if requested.
315 **/
316void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
317{
318 struct ixgbe_bus_info *bus = &hw->bus;
319 u32 reg;
320
321 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
322 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
323 bus->lan_id = bus->func;
324
325 /* check for a port swap */
326 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
327 if (reg & IXGBE_FACTPS_LFS)
328 bus->func ^= 0x1;
329}
330
9a799d71 331/**
c44ade9e 332 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 333 * @hw: pointer to hardware structure
334 *
335 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
336 * disables transmit and receive units. The adapter_stopped flag is used by
337 * the shared code and drivers to determine if the adapter is in a stopped
338 * state and should not touch the hardware.
339 **/
c44ade9e 340s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71
AK		 341{
342 u32 number_of_queues;
343 u32 reg_val;
344 u16 i;
345
346 /*
347 * Set the adapter_stopped flag so other driver functions stop touching
348 * the hardware
349 */
350 hw->adapter_stopped = true;
351
352 /* Disable the receive unit */
353 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
354 reg_val &= ~(IXGBE_RXCTRL_RXEN);
355 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
c44ade9e 356 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 357 msleep(2);
358
359 /* Clear interrupt mask to stop from interrupts being generated */
360 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
361
362 /* Clear any pending interrupts */
363 IXGBE_READ_REG(hw, IXGBE_EICR);
364
365 /* Disable the transmit unit. Each queue must be disabled. */
c44ade9e 366 number_of_queues = hw->mac.max_tx_queues;
9a799d71
AK		 367 for (i = 0; i < number_of_queues; i++) {
368 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
369 if (reg_val & IXGBE_TXDCTL_ENABLE) {
370 reg_val &= ~IXGBE_TXDCTL_ENABLE;
371 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
372 }
373 }
374
c44ade9e
JB		 375 /*
376 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
377 * access and verify no pending requests
378 */
379 if (ixgbe_disable_pcie_master(hw) != 0)
380 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
381
9a799d71
AK		 382 return 0;
383}
384
385/**
c44ade9e 386 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 387 * @hw: pointer to hardware structure
388 * @index: led number to turn on
389 **/
c44ade9e 390s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 391{
392 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
393
394 /* To turn on the LED, set mode to ON. */
395 led_reg &= ~IXGBE_LED_MODE_MASK(index);
396 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
397 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 398 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 399
400 return 0;
401}
402
403/**
c44ade9e 404 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 405 * @hw: pointer to hardware structure
406 * @index: led number to turn off
407 **/
c44ade9e 408s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 409{
410 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
411
412 /* To turn off the LED, set mode to OFF. */
413 led_reg &= ~IXGBE_LED_MODE_MASK(index);
414 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
415 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 416 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 417
418 return 0;
419}
420
9a799d71 421/**
c44ade9e 422 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 423 * @hw: pointer to hardware structure
424 *
425 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
426 * ixgbe_hw struct in order to set up EEPROM access.
427 **/
c44ade9e 428s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 429{
430 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
431 u32 eec;
432 u16 eeprom_size;
433
434 if (eeprom->type == ixgbe_eeprom_uninitialized) {
435 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 436 /* Set default semaphore delay to 10ms which is a well
437 * tested value */
438 eeprom->semaphore_delay = 10;
9a799d71
AK		 439
440 /*
441 * Check for EEPROM present first.
442 * If not present leave as none
443 */
444 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
445 if (eec & IXGBE_EEC_PRES) {
446 eeprom->type = ixgbe_eeprom_spi;
447
448 /*
449 * SPI EEPROM is assumed here. This code would need to
450 * change if a future EEPROM is not SPI.
451 */
452 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
453 IXGBE_EEC_SIZE_SHIFT);
454 eeprom->word_size = 1 << (eeprom_size +
455 IXGBE_EEPROM_WORD_SIZE_SHIFT);
456 }
457
458 if (eec & IXGBE_EEC_ADDR_SIZE)
459 eeprom->address_bits = 16;
460 else
461 eeprom->address_bits = 8;
462 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
463 "%d\n", eeprom->type, eeprom->word_size,
464 eeprom->address_bits);
465 }
466
467 return 0;
468}
469
11afc1b1
PW		 470/**
471 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
472 * @hw: pointer to hardware structure
473 * @offset: offset within the EEPROM to be written to
474 * @data: 16 bit word to be written to the EEPROM
475 *
476 * If ixgbe_eeprom_update_checksum is not called after this function, the
477 * EEPROM will most likely contain an invalid checksum.
478 **/
479s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
480{
481 s32 status;
482 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
483
484 hw->eeprom.ops.init_params(hw);
485
486 if (offset >= hw->eeprom.word_size) {
487 status = IXGBE_ERR_EEPROM;
488 goto out;
489 }
490
491 /* Prepare the EEPROM for writing */
492 status = ixgbe_acquire_eeprom(hw);
493
494 if (status == 0) {
495 if (ixgbe_ready_eeprom(hw) != 0) {
496 ixgbe_release_eeprom(hw);
497 status = IXGBE_ERR_EEPROM;
498 }
499 }
500
501 if (status == 0) {
502 ixgbe_standby_eeprom(hw);
503
504 /* Send the WRITE ENABLE command (8 bit opcode ) */
505 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
506 IXGBE_EEPROM_OPCODE_BITS);
507
508 ixgbe_standby_eeprom(hw);
509
510 /*
511 * Some SPI eeproms use the 8th address bit embedded in the
512 * opcode
513 */
514 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
515 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
516
517 /* Send the Write command (8-bit opcode + addr) */
518 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
519 IXGBE_EEPROM_OPCODE_BITS);
520 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
521 hw->eeprom.address_bits);
522
523 /* Send the data */
524 data = (data >> 8) | (data << 8);
525 ixgbe_shift_out_eeprom_bits(hw, data, 16);
526 ixgbe_standby_eeprom(hw);
527
528 msleep(hw->eeprom.semaphore_delay);
529 /* Done with writing - release the EEPROM */
530 ixgbe_release_eeprom(hw);
531 }
532
533out:
534 return status;
535}
536
9a799d71 537/**
c44ade9e
JB		 538 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
539 * @hw: pointer to hardware structure
540 * @offset: offset within the EEPROM to be read
541 * @data: read 16 bit value from EEPROM
542 *
543 * Reads 16 bit value from EEPROM through bit-bang method
544 **/
545s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
546 u16 *data)
547{
548 s32 status;
549 u16 word_in;
550 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
551
552 hw->eeprom.ops.init_params(hw);
553
554 if (offset >= hw->eeprom.word_size) {
555 status = IXGBE_ERR_EEPROM;
556 goto out;
557 }
558
559 /* Prepare the EEPROM for reading */
560 status = ixgbe_acquire_eeprom(hw);
561
562 if (status == 0) {
563 if (ixgbe_ready_eeprom(hw) != 0) {
564 ixgbe_release_eeprom(hw);
565 status = IXGBE_ERR_EEPROM;
566 }
567 }
568
569 if (status == 0) {
570 ixgbe_standby_eeprom(hw);
571
572 /*
573 * Some SPI eeproms use the 8th address bit embedded in the
574 * opcode
575 */
576 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
577 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
578
579 /* Send the READ command (opcode + addr) */
580 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
581 IXGBE_EEPROM_OPCODE_BITS);
582 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
583 hw->eeprom.address_bits);
584
585 /* Read the data. */
586 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
587 *data = (word_in >> 8) | (word_in << 8);
588
589 /* End this read operation */
590 ixgbe_release_eeprom(hw);
591 }
592
593out:
594 return status;
595}
596
597/**
598 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
9a799d71
AK		 599 * @hw: pointer to hardware structure
600 * @offset: offset of word in the EEPROM to read
601 * @data: word read from the EEPROM
602 *
603 * Reads a 16 bit word from the EEPROM using the EERD register.
604 **/
c44ade9e 605s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
9a799d71
AK		 606{
607 u32 eerd;
608 s32 status;
609
c44ade9e
JB		 610 hw->eeprom.ops.init_params(hw);
611
612 if (offset >= hw->eeprom.word_size) {
613 status = IXGBE_ERR_EEPROM;
614 goto out;
615 }
616
9a799d71
AK		 617 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
618 IXGBE_EEPROM_READ_REG_START;
619
620 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
621 status = ixgbe_poll_eeprom_eerd_done(hw);
622
623 if (status == 0)
624 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
b4617240 625 IXGBE_EEPROM_READ_REG_DATA);
9a799d71
AK		 626 else
627 hw_dbg(hw, "Eeprom read timed out\n");
628
c44ade9e 629out:
9a799d71
AK		 630 return status;
631}
632
633/**
634 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
635 * @hw: pointer to hardware structure
636 *
637 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
638 **/
639static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
640{
641 u32 i;
642 u32 reg;
643 s32 status = IXGBE_ERR_EEPROM;
644
645 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
646 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
647 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
648 status = 0;
649 break;
650 }
651 udelay(5);
652 }
653 return status;
654}
655
c44ade9e
JB		 656/**
657 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
658 * @hw: pointer to hardware structure
659 *
660 * Prepares EEPROM for access using bit-bang method. This function should
661 * be called before issuing a command to the EEPROM.
662 **/
663static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
664{
665 s32 status = 0;
fc1f2095 666 u32 eec = 0;
c44ade9e
JB		 667 u32 i;
668
669 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
670 status = IXGBE_ERR_SWFW_SYNC;
671
672 if (status == 0) {
673 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
674
675 /* Request EEPROM Access */
676 eec |= IXGBE_EEC_REQ;
677 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
678
679 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
680 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
681 if (eec & IXGBE_EEC_GNT)
682 break;
683 udelay(5);
684 }
685
686 /* Release if grant not acquired */
687 if (!(eec & IXGBE_EEC_GNT)) {
688 eec &= ~IXGBE_EEC_REQ;
689 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
690 hw_dbg(hw, "Could not acquire EEPROM grant\n");
691
692 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
693 status = IXGBE_ERR_EEPROM;
694 }
695 }
696
697 /* Setup EEPROM for Read/Write */
698 if (status == 0) {
699 /* Clear CS and SK */
700 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
701 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
702 IXGBE_WRITE_FLUSH(hw);
703 udelay(1);
704 }
705 return status;
706}
707
9a799d71
AK		 708/**
709 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
710 * @hw: pointer to hardware structure
711 *
712 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
713 **/
714static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
715{
716 s32 status = IXGBE_ERR_EEPROM;
717 u32 timeout;
718 u32 i;
719 u32 swsm;
720
721 /* Set timeout value based on size of EEPROM */
722 timeout = hw->eeprom.word_size + 1;
723
724 /* Get SMBI software semaphore between device drivers first */
725 for (i = 0; i < timeout; i++) {
726 /*
727 * If the SMBI bit is 0 when we read it, then the bit will be
728 * set and we have the semaphore
729 */
730 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
731 if (!(swsm & IXGBE_SWSM_SMBI)) {
732 status = 0;
733 break;
734 }
735 msleep(1);
736 }
737
738 /* Now get the semaphore between SW/FW through the SWESMBI bit */
739 if (status == 0) {
740 for (i = 0; i < timeout; i++) {
741 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
742
743 /* Set the SW EEPROM semaphore bit to request access */
744 swsm |= IXGBE_SWSM_SWESMBI;
745 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
746
747 /*
748 * If we set the bit successfully then we got the
749 * semaphore.
750 */
751 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
752 if (swsm & IXGBE_SWSM_SWESMBI)
753 break;
754
755 udelay(50);
756 }
757
758 /*
759 * Release semaphores and return error if SW EEPROM semaphore
760 * was not granted because we don't have access to the EEPROM
761 */
762 if (i >= timeout) {
763 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
b4617240 764 "not granted.\n");
9a799d71
AK		 765 ixgbe_release_eeprom_semaphore(hw);
766 status = IXGBE_ERR_EEPROM;
767 }
768 }
769
770 return status;
771}
772
773/**
774 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
775 * @hw: pointer to hardware structure
776 *
777 * This function clears hardware semaphore bits.
778 **/
779static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
780{
781 u32 swsm;
782
783 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
784
785 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
786 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
787 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 788 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 789}
790
c44ade9e
JB		 791/**
792 * ixgbe_ready_eeprom - Polls for EEPROM ready
793 * @hw: pointer to hardware structure
794 **/
795static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
796{
797 s32 status = 0;
798 u16 i;
799 u8 spi_stat_reg;
800
801 /*
802 * Read "Status Register" repeatedly until the LSB is cleared. The
803 * EEPROM will signal that the command has been completed by clearing
804 * bit 0 of the internal status register. If it's not cleared within
805 * 5 milliseconds, then error out.
806 */
807 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
808 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
809 IXGBE_EEPROM_OPCODE_BITS);
810 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
811 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
812 break;
813
814 udelay(5);
815 ixgbe_standby_eeprom(hw);
816 };
817
818 /*
819 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
820 * devices (and only 0-5mSec on 5V devices)
821 */
822 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
823 hw_dbg(hw, "SPI EEPROM Status error\n");
824 status = IXGBE_ERR_EEPROM;
825 }
826
827 return status;
828}
829
830/**
831 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
832 * @hw: pointer to hardware structure
833 **/
834static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
835{
836 u32 eec;
837
838 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
839
840 /* Toggle CS to flush commands */
841 eec |= IXGBE_EEC_CS;
842 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
843 IXGBE_WRITE_FLUSH(hw);
844 udelay(1);
845 eec &= ~IXGBE_EEC_CS;
846 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
847 IXGBE_WRITE_FLUSH(hw);
848 udelay(1);
849}
850
851/**
852 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
853 * @hw: pointer to hardware structure
854 * @data: data to send to the EEPROM
855 * @count: number of bits to shift out
856 **/
857static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
858 u16 count)
859{
860 u32 eec;
861 u32 mask;
862 u32 i;
863
864 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
865
866 /*
867 * Mask is used to shift "count" bits of "data" out to the EEPROM
868 * one bit at a time. Determine the starting bit based on count
869 */
870 mask = 0x01 << (count - 1);
871
872 for (i = 0; i < count; i++) {
873 /*
874 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
875 * "1", and then raising and then lowering the clock (the SK
876 * bit controls the clock input to the EEPROM). A "0" is
877 * shifted out to the EEPROM by setting "DI" to "0" and then
878 * raising and then lowering the clock.
879 */
880 if (data & mask)
881 eec |= IXGBE_EEC_DI;
882 else
883 eec &= ~IXGBE_EEC_DI;
884
885 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
886 IXGBE_WRITE_FLUSH(hw);
887
888 udelay(1);
889
890 ixgbe_raise_eeprom_clk(hw, &eec);
891 ixgbe_lower_eeprom_clk(hw, &eec);
892
893 /*
894 * Shift mask to signify next bit of data to shift in to the
895 * EEPROM
896 */
897 mask = mask >> 1;
898 };
899
900 /* We leave the "DI" bit set to "0" when we leave this routine. */
901 eec &= ~IXGBE_EEC_DI;
902 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
903 IXGBE_WRITE_FLUSH(hw);
904}
905
906/**
907 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
908 * @hw: pointer to hardware structure
909 **/
910static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
911{
912 u32 eec;
913 u32 i;
914 u16 data = 0;
915
916 /*
917 * In order to read a register from the EEPROM, we need to shift
918 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
919 * the clock input to the EEPROM (setting the SK bit), and then reading
920 * the value of the "DO" bit. During this "shifting in" process the
921 * "DI" bit should always be clear.
922 */
923 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
924
925 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
926
927 for (i = 0; i < count; i++) {
928 data = data << 1;
929 ixgbe_raise_eeprom_clk(hw, &eec);
930
931 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
932
933 eec &= ~(IXGBE_EEC_DI);
934 if (eec & IXGBE_EEC_DO)
935 data |= 1;
936
937 ixgbe_lower_eeprom_clk(hw, &eec);
938 }
939
940 return data;
941}
942
943/**
944 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
945 * @hw: pointer to hardware structure
946 * @eec: EEC register's current value
947 **/
948static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
949{
950 /*
951 * Raise the clock input to the EEPROM
952 * (setting the SK bit), then delay
953 */
954 *eec = *eec | IXGBE_EEC_SK;
955 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
956 IXGBE_WRITE_FLUSH(hw);
957 udelay(1);
958}
959
960/**
961 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
962 * @hw: pointer to hardware structure
963 * @eecd: EECD's current value
964 **/
965static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
966{
967 /*
968 * Lower the clock input to the EEPROM (clearing the SK bit), then
969 * delay
970 */
971 *eec = *eec & ~IXGBE_EEC_SK;
972 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
973 IXGBE_WRITE_FLUSH(hw);
974 udelay(1);
975}
976
977/**
978 * ixgbe_release_eeprom - Release EEPROM, release semaphores
979 * @hw: pointer to hardware structure
980 **/
981static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
982{
983 u32 eec;
984
985 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
986
987 eec |= IXGBE_EEC_CS; /* Pull CS high */
988 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
989
990 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
991 IXGBE_WRITE_FLUSH(hw);
992
993 udelay(1);
994
995 /* Stop requesting EEPROM access */
996 eec &= ~IXGBE_EEC_REQ;
997 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
998
999 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1000}
1001
9a799d71
AK		 1002/**
1003 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1004 * @hw: pointer to hardware structure
1005 **/
1006static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1007{
1008 u16 i;
1009 u16 j;
1010 u16 checksum = 0;
1011 u16 length = 0;
1012 u16 pointer = 0;
1013 u16 word = 0;
1014
1015 /* Include 0x0-0x3F in the checksum */
1016 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1017 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1018 hw_dbg(hw, "EEPROM read failed\n");
1019 break;
1020 }
1021 checksum += word;
1022 }
1023
1024 /* Include all data from pointers except for the fw pointer */
1025 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1026 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1027
1028 /* Make sure the pointer seems valid */
1029 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1030 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1031
1032 if (length != 0xFFFF && length != 0) {
1033 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1034 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1035 checksum += word;
1036 }
1037 }
1038 }
1039 }
1040
1041 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1042
1043 return checksum;
1044}
1045
1046/**
c44ade9e 1047 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1048 * @hw: pointer to hardware structure
1049 * @checksum_val: calculated checksum
1050 *
1051 * Performs checksum calculation and validates the EEPROM checksum. If the
1052 * caller does not need checksum_val, the value can be NULL.
1053 **/
c44ade9e
JB		 1054s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1055 u16 *checksum_val)
9a799d71
AK		 1056{
1057 s32 status;
1058 u16 checksum;
1059 u16 read_checksum = 0;
1060
1061 /*
1062 * Read the first word from the EEPROM. If this times out or fails, do
1063 * not continue or we could be in for a very long wait while every
1064 * EEPROM read fails
1065 */
c44ade9e 1066 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1067
1068 if (status == 0) {
1069 checksum = ixgbe_calc_eeprom_checksum(hw);
1070
c44ade9e 1071 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1072
1073 /*
1074 * Verify read checksum from EEPROM is the same as
1075 * calculated checksum
1076 */
1077 if (read_checksum != checksum)
1078 status = IXGBE_ERR_EEPROM_CHECKSUM;
1079
1080 /* If the user cares, return the calculated checksum */
1081 if (checksum_val)
1082 *checksum_val = checksum;
1083 } else {
1084 hw_dbg(hw, "EEPROM read failed\n");
1085 }
1086
1087 return status;
1088}
1089
c44ade9e
JB		 1090/**
1091 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1092 * @hw: pointer to hardware structure
1093 **/
1094s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1095{
1096 s32 status;
1097 u16 checksum;
1098
1099 /*
1100 * Read the first word from the EEPROM. If this times out or fails, do
1101 * not continue or we could be in for a very long wait while every
1102 * EEPROM read fails
1103 */
1104 status = hw->eeprom.ops.read(hw, 0, &checksum);
1105
1106 if (status == 0) {
1107 checksum = ixgbe_calc_eeprom_checksum(hw);
1108 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1109 checksum);
1110 } else {
1111 hw_dbg(hw, "EEPROM read failed\n");
1112 }
1113
1114 return status;
1115}
1116
9a799d71
AK		 1117/**
1118 * ixgbe_validate_mac_addr - Validate MAC address
1119 * @mac_addr: pointer to MAC address.
1120 *
1121 * Tests a MAC address to ensure it is a valid Individual Address
1122 **/
1123s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1124{
1125 s32 status = 0;
1126
1127 /* Make sure it is not a multicast address */
1128 if (IXGBE_IS_MULTICAST(mac_addr))
1129 status = IXGBE_ERR_INVALID_MAC_ADDR;
1130 /* Not a broadcast address */
1131 else if (IXGBE_IS_BROADCAST(mac_addr))
1132 status = IXGBE_ERR_INVALID_MAC_ADDR;
1133 /* Reject the zero address */
1134 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
c44ade9e 1135 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
9a799d71
AK		 1136 status = IXGBE_ERR_INVALID_MAC_ADDR;
1137
1138 return status;
1139}
1140
1141/**
c44ade9e 1142 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1143 * @hw: pointer to hardware structure
9a799d71 1144 * @index: Receive address register to write
c44ade9e
JB		 1145 * @addr: Address to put into receive address register
1146 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1147 * @enable_addr: set flag that address is active
1148 *
1149 * Puts an ethernet address into a receive address register.
1150 **/
c44ade9e
JB		 1151s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1152 u32 enable_addr)
9a799d71
AK		 1153{
1154 u32 rar_low, rar_high;
c44ade9e
JB		 1155 u32 rar_entries = hw->mac.num_rar_entries;
1156
1157 /* setup VMDq pool selection before this RAR gets enabled */
1158 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1159
c44ade9e
JB		 1160 /* Make sure we are using a valid rar index range */
1161 if (index < rar_entries) {
b4617240 1162 /*
c44ade9e
JB		 1163 * HW expects these in little endian so we reverse the byte
1164 * order from network order (big endian) to little endian
b4617240
PW		 1165 */
1166 rar_low = ((u32)addr[0] |
1167 ((u32)addr[1] << 8) |
1168 ((u32)addr[2] << 16) |
1169 ((u32)addr[3] << 24));
c44ade9e
JB		 1170 /*
1171 * Some parts put the VMDq setting in the extra RAH bits,
1172 * so save everything except the lower 16 bits that hold part
1173 * of the address and the address valid bit.
1174 */
1175 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1176 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1177 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1178
b4617240
PW		 1179 if (enable_addr != 0)
1180 rar_high |= IXGBE_RAH_AV;
9a799d71 1181
b4617240
PW		 1182 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1183 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1184 } else {
1185 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1186 }
1187
1188 return 0;
1189}
1190
1191/**
1192 * ixgbe_clear_rar_generic - Remove Rx address register
1193 * @hw: pointer to hardware structure
1194 * @index: Receive address register to write
1195 *
1196 * Clears an ethernet address from a receive address register.
1197 **/
1198s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1199{
1200 u32 rar_high;
1201 u32 rar_entries = hw->mac.num_rar_entries;
1202
1203 /* Make sure we are using a valid rar index range */
1204 if (index < rar_entries) {
1205 /*
1206 * Some parts put the VMDq setting in the extra RAH bits,
1207 * so save everything except the lower 16 bits that hold part
1208 * of the address and the address valid bit.
1209 */
1210 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1211 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1212
1213 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1214 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1215 } else {
1216 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1217 }
1218
1219 /* clear VMDq pool/queue selection for this RAR */
1220 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1221
1222 return 0;
1223}
1224
1225/**
c44ade9e
JB		 1226 * ixgbe_enable_rar - Enable Rx address register
1227 * @hw: pointer to hardware structure
1228 * @index: index into the RAR table
1229 *
1230 * Enables the select receive address register.
1231 **/
1232static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1233{
1234 u32 rar_high;
1235
1236 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1237 rar_high |= IXGBE_RAH_AV;
1238 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1239}
1240
1241/**
1242 * ixgbe_disable_rar - Disable Rx address register
1243 * @hw: pointer to hardware structure
1244 * @index: index into the RAR table
1245 *
1246 * Disables the select receive address register.
1247 **/
1248static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1249{
1250 u32 rar_high;
1251
1252 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1253 rar_high &= (~IXGBE_RAH_AV);
1254 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1255}
1256
1257/**
1258 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1259 * @hw: pointer to hardware structure
1260 *
1261 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1262 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1263 * the receiver is in reset when the routine is called.
1264 **/
c44ade9e 1265s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1266{
1267 u32 i;
2c5645cf 1268 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1269
1270 /*
1271 * If the current mac address is valid, assume it is a software override
1272 * to the permanent address.
1273 * Otherwise, use the permanent address from the eeprom.
1274 */
1275 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1276 IXGBE_ERR_INVALID_MAC_ADDR) {
1277 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1278 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1279
ce7194d8 1280 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1281 } else {
1282 /* Setup the receive address. */
1283 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1284 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1285
c44ade9e 1286 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71 1287 }
c44ade9e 1288 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1289
1290 hw->addr_ctrl.rar_used_count = 1;
1291
1292 /* Zero out the other receive addresses. */
c44ade9e 1293 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1294 for (i = 1; i < rar_entries; i++) {
1295 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1296 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1297 }
1298
1299 /* Clear the MTA */
1300 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1301 hw->addr_ctrl.mta_in_use = 0;
1302 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1303
1304 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1305 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1306 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1307
c44ade9e
JB		 1308 if (hw->mac.ops.init_uta_tables)
1309 hw->mac.ops.init_uta_tables(hw);
1310
9a799d71
AK		 1311 return 0;
1312}
1313
2c5645cf
CL		 1314/**
1315 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1316 * @hw: pointer to hardware structure
1317 * @addr: new address
1318 *
1319 * Adds it to unused receive address register or goes into promiscuous mode.
1320 **/
c44ade9e 1321static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2c5645cf
CL		 1322{
1323 u32 rar_entries = hw->mac.num_rar_entries;
1324 u32 rar;
1325
1326 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1327 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1328
1329 /*
1330 * Place this address in the RAR if there is room,
1331 * else put the controller into promiscuous mode
1332 */
1333 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1334 rar = hw->addr_ctrl.rar_used_count -
1335 hw->addr_ctrl.mc_addr_in_rar_count;
c44ade9e 1336 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2c5645cf
CL		 1337 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1338 hw->addr_ctrl.rar_used_count++;
1339 } else {
1340 hw->addr_ctrl.overflow_promisc++;
1341 }
1342
1343 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1344}
1345
1346/**
c44ade9e 1347 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2c5645cf 1348 * @hw: pointer to hardware structure
32e7bfc4 1349 * @netdev: pointer to net device structure
2c5645cf
CL		 1350 *
1351 * The given list replaces any existing list. Clears the secondary addrs from
1352 * receive address registers. Uses unused receive address registers for the
1353 * first secondary addresses, and falls back to promiscuous mode as needed.
1354 *
1355 * Drivers using secondary unicast addresses must set user_set_promisc when
1356 * manually putting the device into promiscuous mode.
1357 **/
ccffad25 1358s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
32e7bfc4 1359 struct net_device *netdev)
2c5645cf 1360{
2c5645cf
CL		 1361 u32 i;
1362 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1363 u32 uc_addr_in_use;
1364 u32 fctrl;
ccffad25 1365 struct netdev_hw_addr *ha;
2c5645cf
CL		 1366
1367 /*
1368 * Clear accounting of old secondary address list,
1369 * don't count RAR[0]
1370 */
495dce12 1371 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2c5645cf
CL		 1372 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1373 hw->addr_ctrl.overflow_promisc = 0;
1374
1375 /* Zero out the other receive addresses */
91152c32
SN		 1376 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use + 1);
1377 for (i = 0; i < uc_addr_in_use; i++) {
1378 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
1379 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2c5645cf
CL		 1380 }
1381
1382 /* Add the new addresses */
32e7bfc4 1383 netdev_for_each_uc_addr(ha, netdev) {
2c5645cf 1384 hw_dbg(hw, " Adding the secondary addresses:\n");
ccffad25 1385 ixgbe_add_uc_addr(hw, ha->addr, 0);
2c5645cf
CL		 1386 }
1387
1388 if (hw->addr_ctrl.overflow_promisc) {
1389 /* enable promisc if not already in overflow or set by user */
1390 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1391 hw_dbg(hw, " Entering address overflow promisc mode\n");
1392 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1393 fctrl |= IXGBE_FCTRL_UPE;
1394 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1395 }
1396 } else {
1397 /* only disable if set by overflow, not by user */
1398 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1399 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1400 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1401 fctrl &= ~IXGBE_FCTRL_UPE;
1402 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1403 }
1404 }
1405
c44ade9e 1406 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
2c5645cf
CL		 1407 return 0;
1408}
1409
9a799d71
AK		 1410/**
1411 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1412 * @hw: pointer to hardware structure
1413 * @mc_addr: the multicast address
1414 *
1415 * Extracts the 12 bits, from a multicast address, to determine which
1416 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1417 * incoming rx multicast addresses, to determine the bit-vector to check in
1418 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1419 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1420 * to mc_filter_type.
1421 **/
1422static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1423{
1424 u32 vector = 0;
1425
1426 switch (hw->mac.mc_filter_type) {
b4617240 1427 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1428 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1429 break;
b4617240 1430 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1431 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1432 break;
b4617240 1433 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1434 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1435 break;
b4617240 1436 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1437 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1438 break;
b4617240 1439 default: /* Invalid mc_filter_type */
9a799d71
AK		 1440 hw_dbg(hw, "MC filter type param set incorrectly\n");
1441 break;
1442 }
1443
1444 /* vector can only be 12-bits or boundary will be exceeded */
1445 vector &= 0xFFF;
1446 return vector;
1447}
1448
1449/**
1450 * ixgbe_set_mta - Set bit-vector in multicast table
1451 * @hw: pointer to hardware structure
1452 * @hash_value: Multicast address hash value
1453 *
1454 * Sets the bit-vector in the multicast table.
1455 **/
1456static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1457{
1458 u32 vector;
1459 u32 vector_bit;
1460 u32 vector_reg;
1461 u32 mta_reg;
1462
1463 hw->addr_ctrl.mta_in_use++;
1464
1465 vector = ixgbe_mta_vector(hw, mc_addr);
1466 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1467
1468 /*
1469 * The MTA is a register array of 128 32-bit registers. It is treated
1470 * like an array of 4096 bits. We want to set bit
1471 * BitArray[vector_value]. So we figure out what register the bit is
1472 * in, read it, OR in the new bit, then write back the new value. The
1473 * register is determined by the upper 7 bits of the vector value and
1474 * the bit within that register are determined by the lower 5 bits of
1475 * the value.
1476 */
1477 vector_reg = (vector >> 5) & 0x7F;
1478 vector_bit = vector & 0x1F;
1479 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1480 mta_reg |= (1 << vector_bit);
1481 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1482}
1483
9a799d71 1484/**
c44ade9e 1485 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1486 * @hw: pointer to hardware structure
2853eb89 1487 * @netdev: pointer to net device structure
9a799d71
AK		 1488 *
1489 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1490 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1491 * registers for the first multicast addresses, and hashes the rest into the
1492 * multicast table.
1493 **/
2853eb89
JP		 1494s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1495 struct net_device *netdev)
9a799d71 1496{
2853eb89 1497 struct dev_addr_list *dmi;
9a799d71 1498 u32 i;
9a799d71
AK		 1499
1500 /*
1501 * Set the new number of MC addresses that we are being requested to
1502 * use.
1503 */
2853eb89 1504 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 1505 hw->addr_ctrl.mta_in_use = 0;
1506
9a799d71
AK		 1507 /* Clear the MTA */
1508 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1509 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1510 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1511
1512 /* Add the new addresses */
2853eb89 1513 netdev_for_each_mc_addr(dmi, netdev) {
9a799d71 1514 hw_dbg(hw, " Adding the multicast addresses:\n");
2853eb89 1515 ixgbe_set_mta(hw, dmi->dmi_addr);
9a799d71
AK		 1516 }
1517
1518 /* Enable mta */
1519 if (hw->addr_ctrl.mta_in_use > 0)
1520 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 1521 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 1522
c44ade9e 1523 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1524 return 0;
1525}
1526
1527/**
c44ade9e 1528 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 1529 * @hw: pointer to hardware structure
1530 *
c44ade9e 1531 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 1532 **/
c44ade9e 1533s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1534{
c44ade9e
JB		 1535 u32 i;
1536 u32 rar_entries = hw->mac.num_rar_entries;
1537 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 1538
c44ade9e
JB		 1539 if (a->mc_addr_in_rar_count > 0)
1540 for (i = (rar_entries - a->mc_addr_in_rar_count);
1541 i < rar_entries; i++)
1542 ixgbe_enable_rar(hw, i);
9a799d71 1543
c44ade9e
JB		 1544 if (a->mta_in_use > 0)
1545 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1546 hw->mac.mc_filter_type);
9a799d71
AK		 1547
1548 return 0;
1549}
1550
1551/**
c44ade9e 1552 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 1553 * @hw: pointer to hardware structure
9a799d71 1554 *
c44ade9e 1555 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 1556 **/
c44ade9e 1557s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1558{
c44ade9e
JB		 1559 u32 i;
1560 u32 rar_entries = hw->mac.num_rar_entries;
1561 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 1562
c44ade9e
JB		 1563 if (a->mc_addr_in_rar_count > 0)
1564 for (i = (rar_entries - a->mc_addr_in_rar_count);
1565 i < rar_entries; i++)
1566 ixgbe_disable_rar(hw, i);
9a799d71 1567
c44ade9e
JB		 1568 if (a->mta_in_use > 0)
1569 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 1570
1571 return 0;
1572}
1573
11afc1b1 1574/**
620fa036 1575 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1
PW		 1576 * @hw: pointer to hardware structure
1577 * @packetbuf_num: packet buffer number (0-7)
1578 *
1579 * Enable flow control according to the current settings.
1580 **/
620fa036 1581s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1582{
1583 s32 ret_val = 0;
620fa036 1584 u32 mflcn_reg, fccfg_reg;
11afc1b1 1585 u32 reg;
70b77628
PWJ		 1586 u32 rx_pba_size;
1587
1588#ifdef CONFIG_DCB
1589 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1590 goto out;
1591
1592#endif /* CONFIG_DCB */
620fa036
MC		 1593 /* Negotiate the fc mode to use */
1594 ret_val = ixgbe_fc_autoneg(hw);
1595 if (ret_val)
1596 goto out;
11afc1b1 1597
620fa036 1598 /* Disable any previous flow control settings */
11afc1b1
PW		 1599 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1600 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1601
1602 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1603 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1604
1605 /*
1606 * The possible values of fc.current_mode are:
1607 * 0: Flow control is completely disabled
1608 * 1: Rx flow control is enabled (we can receive pause frames,
1609 * but not send pause frames).
bb3daa4a
PW		 1610 * 2: Tx flow control is enabled (we can send pause frames but
1611 * we do not support receiving pause frames).
11afc1b1 1612 * 3: Both Rx and Tx flow control (symmetric) are enabled.
bb3daa4a 1613 * 4: Priority Flow Control is enabled.
11afc1b1
PW		 1614 * other: Invalid.
1615 */
1616 switch (hw->fc.current_mode) {
1617 case ixgbe_fc_none:
620fa036
MC		 1618 /*
1619 * Flow control is disabled by software override or autoneg.
1620 * The code below will actually disable it in the HW.
1621 */
11afc1b1
PW		 1622 break;
1623 case ixgbe_fc_rx_pause:
1624 /*
1625 * Rx Flow control is enabled and Tx Flow control is
1626 * disabled by software override. Since there really
1627 * isn't a way to advertise that we are capable of RX
1628 * Pause ONLY, we will advertise that we support both
1629 * symmetric and asymmetric Rx PAUSE. Later, we will
1630 * disable the adapter's ability to send PAUSE frames.
1631 */
1632 mflcn_reg |= IXGBE_MFLCN_RFCE;
1633 break;
1634 case ixgbe_fc_tx_pause:
1635 /*
1636 * Tx Flow control is enabled, and Rx Flow control is
1637 * disabled by software override.
1638 */
1639 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1640 break;
1641 case ixgbe_fc_full:
1642 /* Flow control (both Rx and Tx) is enabled by SW override. */
1643 mflcn_reg |= IXGBE_MFLCN_RFCE;
1644 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1645 break;
bb3daa4a
PW		 1646#ifdef CONFIG_DCB
1647 case ixgbe_fc_pfc:
1648 goto out;
1649 break;
620fa036 1650#endif /* CONFIG_DCB */
11afc1b1
PW		 1651 default:
1652 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 1653 ret_val = IXGBE_ERR_CONFIG;
11afc1b1
PW		 1654 goto out;
1655 break;
1656 }
1657
620fa036 1658 /* Set 802.3x based flow control settings. */
2132d381 1659 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 1660 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1661 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1662
70b77628
PWJ		 1663 reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
1664 /* Thresholds are different for link flow control when in DCB mode */
1665 if (reg & IXGBE_MTQC_RT_ENA) {
620fa036
MC		 1666 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1667
70b77628 1668 /* Always disable XON for LFC when in DCB mode */
620fa036
MC		 1669 reg = (rx_pba_size >> 5) & 0xFFE0;
1670 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
264857b8 1671
70b77628
PWJ		 1672 reg = (rx_pba_size >> 2) & 0xFFE0;
1673 if (hw->fc.current_mode & ixgbe_fc_tx_pause)
1674 reg |= IXGBE_FCRTH_FCEN;
1675 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
1676 } else {
1677 /*
1678 * Set up and enable Rx high/low water mark thresholds,
1679 * enable XON.
1680 */
1681 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1682 if (hw->fc.send_xon) {
1683 IXGBE_WRITE_REG(hw,
1684 IXGBE_FCRTL_82599(packetbuf_num),
1685 (hw->fc.low_water |
1686 IXGBE_FCRTL_XONE));
1687 } else {
1688 IXGBE_WRITE_REG(hw,
1689 IXGBE_FCRTL_82599(packetbuf_num),
1690 hw->fc.low_water);
1691 }
1692
1693 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1694 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1695 }
11afc1b1
PW		 1696 }
1697
1698 /* Configure pause time (2 TCs per register) */
70b77628 1699 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
11afc1b1
PW		 1700 if ((packetbuf_num & 1) == 0)
1701 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1702 else
1703 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1704 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1705
1706 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1707
1708out:
1709 return ret_val;
1710}
1711
0ecc061d
PWJ		 1712/**
1713 * ixgbe_fc_autoneg - Configure flow control
1714 * @hw: pointer to hardware structure
1715 *
620fa036
MC		 1716 * Compares our advertised flow control capabilities to those advertised by
1717 * our link partner, and determines the proper flow control mode to use.
0ecc061d
PWJ		 1718 **/
1719s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1720{
1721 s32 ret_val = 0;
620fa036
MC		 1722 ixgbe_link_speed speed;
1723 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
539e5f02 1724 u32 links2, anlp1_reg, autoc_reg, links;
620fa036 1725 bool link_up;
0ecc061d
PWJ		 1726
1727 /*
620fa036
MC		 1728 * AN should have completed when the cable was plugged in.
1729 * Look for reasons to bail out. Bail out if:
1730 * - FC autoneg is disabled, or if
539e5f02 1731 * - link is not up.
620fa036 1732 *
539e5f02 1733 * Since we're being called from an LSC, link is already known to be up.
620fa036 1734 * So use link_up_wait_to_complete=false.
0ecc061d 1735 */
620fa036 1736 hw->mac.ops.check_link(hw, &speed, &link_up, false);
539e5f02
PWJ		 1737
1738 if (hw->fc.disable_fc_autoneg || (!link_up)) {
620fa036
MC		 1739 hw->fc.fc_was_autonegged = false;
1740 hw->fc.current_mode = hw->fc.requested_mode;
0ecc061d
PWJ		 1741 goto out;
1742 }
1743
539e5f02
PWJ		 1744 /*
1745 * On backplane, bail out if
1746 * - backplane autoneg was not completed, or if
000c486d 1747 * - we are 82599 and link partner is not AN enabled
539e5f02
PWJ		 1748 */
1749 if (hw->phy.media_type == ixgbe_media_type_backplane) {
1750 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
000c486d 1751 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
539e5f02
PWJ		 1752 hw->fc.fc_was_autonegged = false;
1753 hw->fc.current_mode = hw->fc.requested_mode;
1754 goto out;
1755 }
000c486d
DS		 1756
1757 if (hw->mac.type == ixgbe_mac_82599EB) {
1758 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
1759 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
1760 hw->fc.fc_was_autonegged = false;
1761 hw->fc.current_mode = hw->fc.requested_mode;
1762 goto out;
1763 }
1764 }
539e5f02
PWJ		 1765 }
1766
1767 /*
1768 * On multispeed fiber at 1g, bail out if
1769 * - link is up but AN did not complete, or if
1770 * - link is up and AN completed but timed out
1771 */
1772 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) {
1773 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1774 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1775 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1776 hw->fc.fc_was_autonegged = false;
1777 hw->fc.current_mode = hw->fc.requested_mode;
1778 goto out;
1779 }
1780 }
1781
9bbe3a57
PW		 1782 /*
1783 * Bail out on
1784 * - copper or CX4 adapters
1785 * - fiber adapters running at 10gig
1786 */
1787 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
1788 (hw->phy.media_type == ixgbe_media_type_cx4) ||
1789 ((hw->phy.media_type == ixgbe_media_type_fiber) &&
1790 (speed == IXGBE_LINK_SPEED_10GB_FULL))) {
1791 hw->fc.fc_was_autonegged = false;
1792 hw->fc.current_mode = hw->fc.requested_mode;
1793 goto out;
1794 }
1795
0ecc061d
PWJ		 1796 /*
1797 * Read the AN advertisement and LP ability registers and resolve
1798 * local flow control settings accordingly
1799 */
539e5f02
PWJ		 1800 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1801 (hw->phy.media_type != ixgbe_media_type_backplane)) {
1802 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1803 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1804 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1805 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1806 /*
1807 * Now we need to check if the user selected Rx ONLY
1808 * of pause frames. In this case, we had to advertise
1809 * FULL flow control because we could not advertise RX
1810 * ONLY. Hence, we must now check to see if we need to
1811 * turn OFF the TRANSMISSION of PAUSE frames.
1812 */
1813 if (hw->fc.requested_mode == ixgbe_fc_full) {
1814 hw->fc.current_mode = ixgbe_fc_full;
1815 hw_dbg(hw, "Flow Control = FULL.\n");
1816 } else {
1817 hw->fc.current_mode = ixgbe_fc_rx_pause;
1818 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1819 }
1820 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1821 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1822 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1823 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1824 hw->fc.current_mode = ixgbe_fc_tx_pause;
1825 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1826 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1827 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1828 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1829 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1830 hw->fc.current_mode = ixgbe_fc_rx_pause;
1831 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1832 } else {
1833 hw->fc.current_mode = ixgbe_fc_none;
1834 hw_dbg(hw, "Flow Control = NONE.\n");
1835 }
1836 }
1837
1838 if (hw->phy.media_type == ixgbe_media_type_backplane) {
0ecc061d 1839 /*
539e5f02
PWJ		 1840 * Read the 10g AN autoc and LP ability registers and resolve
1841 * local flow control settings accordingly
0ecc061d 1842 */
539e5f02
PWJ		 1843 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1844 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
1845
1846 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1847 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) {
1848 /*
1849 * Now we need to check if the user selected Rx ONLY
1850 * of pause frames. In this case, we had to advertise
1851 * FULL flow control because we could not advertise RX
1852 * ONLY. Hence, we must now check to see if we need to
1853 * turn OFF the TRANSMISSION of PAUSE frames.
1854 */
1855 if (hw->fc.requested_mode == ixgbe_fc_full) {
1856 hw->fc.current_mode = ixgbe_fc_full;
1857 hw_dbg(hw, "Flow Control = FULL.\n");
1858 } else {
1859 hw->fc.current_mode = ixgbe_fc_rx_pause;
1860 hw_dbg(hw, "Flow Control=RX PAUSE only\n");
1861 }
1862 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1863 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1864 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1865 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
1866 hw->fc.current_mode = ixgbe_fc_tx_pause;
1867 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1868 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) &&
1869 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) &&
1870 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) &&
1871 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) {
0ecc061d
PWJ		 1872 hw->fc.current_mode = ixgbe_fc_rx_pause;
1873 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
539e5f02
PWJ		 1874 } else {
1875 hw->fc.current_mode = ixgbe_fc_none;
1876 hw_dbg(hw, "Flow Control = NONE.\n");
0ecc061d 1877 }
0ecc061d 1878 }
620fa036
MC		 1879 /* Record that current_mode is the result of a successful autoneg */
1880 hw->fc.fc_was_autonegged = true;
1881
0ecc061d
PWJ		 1882out:
1883 return ret_val;
1884}
1885
11afc1b1 1886/**
620fa036 1887 * ixgbe_setup_fc - Set up flow control
11afc1b1
PW		 1888 * @hw: pointer to hardware structure
1889 *
620fa036 1890 * Called at init time to set up flow control.
11afc1b1 1891 **/
7b25cdba 1892static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
11afc1b1
PW		 1893{
1894 s32 ret_val = 0;
620fa036 1895 u32 reg;
11afc1b1 1896
bb3daa4a
PW		 1897#ifdef CONFIG_DCB
1898 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1899 hw->fc.current_mode = hw->fc.requested_mode;
1900 goto out;
1901 }
1902
1903#endif
11afc1b1
PW		 1904 /* Validate the packetbuf configuration */
1905 if (packetbuf_num < 0 || packetbuf_num > 7) {
1906 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1907 "is 0-7\n", packetbuf_num);
1908 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1909 goto out;
1910 }
1911
1912 /*
1913 * Validate the water mark configuration. Zero water marks are invalid
1914 * because it causes the controller to just blast out fc packets.
1915 */
1916 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
620fa036
MC		 1917 hw_dbg(hw, "Invalid water mark configuration\n");
1918 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1919 goto out;
11afc1b1
PW		 1920 }
1921
1922 /*
1923 * Validate the requested mode. Strict IEEE mode does not allow
620fa036 1924 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
11afc1b1
PW		 1925 */
1926 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1927 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1928 "IEEE mode\n");
1929 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1930 goto out;
1931 }
1932
1933 /*
1934 * 10gig parts do not have a word in the EEPROM to determine the
1935 * default flow control setting, so we explicitly set it to full.
1936 */
1937 if (hw->fc.requested_mode == ixgbe_fc_default)
1938 hw->fc.requested_mode = ixgbe_fc_full;
1939
1940 /*
620fa036
MC		 1941 * Set up the 1G flow control advertisement registers so the HW will be
1942 * able to do fc autoneg once the cable is plugged in. If we end up
1943 * using 10g instead, this is harmless.
11afc1b1 1944 */
620fa036 1945 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
11afc1b1 1946
620fa036
MC		 1947 /*
1948 * The possible values of fc.requested_mode are:
1949 * 0: Flow control is completely disabled
1950 * 1: Rx flow control is enabled (we can receive pause frames,
1951 * but not send pause frames).
1952 * 2: Tx flow control is enabled (we can send pause frames but
1953 * we do not support receiving pause frames).
1954 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1955#ifdef CONFIG_DCB
1956 * 4: Priority Flow Control is enabled.
1957#endif
1958 * other: Invalid.
1959 */
1960 switch (hw->fc.requested_mode) {
1961 case ixgbe_fc_none:
1962 /* Flow control completely disabled by software override. */
1963 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1964 break;
1965 case ixgbe_fc_rx_pause:
1966 /*
1967 * Rx Flow control is enabled and Tx Flow control is
1968 * disabled by software override. Since there really
1969 * isn't a way to advertise that we are capable of RX
1970 * Pause ONLY, we will advertise that we support both
1971 * symmetric and asymmetric Rx PAUSE. Later, we will
1972 * disable the adapter's ability to send PAUSE frames.
1973 */
1974 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1975 break;
1976 case ixgbe_fc_tx_pause:
1977 /*
1978 * Tx Flow control is enabled, and Rx Flow control is
1979 * disabled by software override.
1980 */
1981 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1982 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1983 break;
1984 case ixgbe_fc_full:
1985 /* Flow control (both Rx and Tx) is enabled by SW override. */
1986 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1987 break;
1988#ifdef CONFIG_DCB
1989 case ixgbe_fc_pfc:
11afc1b1 1990 goto out;
620fa036
MC		 1991 break;
1992#endif /* CONFIG_DCB */
1993 default:
1994 hw_dbg(hw, "Flow control param set incorrectly\n");
539e5f02 1995 ret_val = IXGBE_ERR_CONFIG;
620fa036
MC		 1996 goto out;
1997 break;
1998 }
1999
2000 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2001 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
11afc1b1 2002
620fa036
MC		 2003 /* Disable AN timeout */
2004 if (hw->fc.strict_ieee)
2005 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
2006
2007 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2008 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
11afc1b1 2009
539e5f02
PWJ		 2010 /*
2011 * Set up the 10G flow control advertisement registers so the HW
2012 * can do fc autoneg once the cable is plugged in. If we end up
2013 * using 1g instead, this is harmless.
2014 */
2015 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2016
2017 /*
2018 * The possible values of fc.requested_mode are:
2019 * 0: Flow control is completely disabled
2020 * 1: Rx flow control is enabled (we can receive pause frames,
2021 * but not send pause frames).
2022 * 2: Tx flow control is enabled (we can send pause frames but
2023 * we do not support receiving pause frames).
2024 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2025 * other: Invalid.
2026 */
2027 switch (hw->fc.requested_mode) {
2028 case ixgbe_fc_none:
2029 /* Flow control completely disabled by software override. */
2030 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2031 break;
2032 case ixgbe_fc_rx_pause:
2033 /*
2034 * Rx Flow control is enabled and Tx Flow control is
2035 * disabled by software override. Since there really
2036 * isn't a way to advertise that we are capable of RX
2037 * Pause ONLY, we will advertise that we support both
2038 * symmetric and asymmetric Rx PAUSE. Later, we will
2039 * disable the adapter's ability to send PAUSE frames.
2040 */
2041 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2042 break;
2043 case ixgbe_fc_tx_pause:
2044 /*
2045 * Tx Flow control is enabled, and Rx Flow control is
2046 * disabled by software override.
2047 */
2048 reg |= (IXGBE_AUTOC_ASM_PAUSE);
2049 reg &= ~(IXGBE_AUTOC_SYM_PAUSE);
2050 break;
2051 case ixgbe_fc_full:
2052 /* Flow control (both Rx and Tx) is enabled by SW override. */
2053 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE);
2054 break;
2055#ifdef CONFIG_DCB
2056 case ixgbe_fc_pfc:
2057 goto out;
2058 break;
2059#endif /* CONFIG_DCB */
2060 default:
2061 hw_dbg(hw, "Flow control param set incorrectly\n");
2062 ret_val = IXGBE_ERR_CONFIG;
2063 goto out;
2064 break;
2065 }
2066 /*
2067 * AUTOC restart handles negotiation of 1G and 10G. There is
2068 * no need to set the PCS1GCTL register.
2069 */
2070 reg |= IXGBE_AUTOC_AN_RESTART;
2071 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg);
2072 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2073
11afc1b1
PW		 2074out:
2075 return ret_val;
2076}
2077
9a799d71
AK		 2078/**
2079 * ixgbe_disable_pcie_master - Disable PCI-express master access
2080 * @hw: pointer to hardware structure
2081 *
2082 * Disables PCI-Express master access and verifies there are no pending
2083 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2084 * bit hasn't caused the master requests to be disabled, else 0
2085 * is returned signifying master requests disabled.
2086 **/
2087s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2088{
c44ade9e
JB		 2089 u32 i;
2090 u32 reg_val;
2091 u32 number_of_queues;
9a799d71
AK		 2092 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2093
c44ade9e
JB		 2094 /* Disable the receive unit by stopping each queue */
2095 number_of_queues = hw->mac.max_rx_queues;
2096 for (i = 0; i < number_of_queues; i++) {
2097 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2098 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2099 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2100 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2101 }
2102 }
2103
2104 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2105 reg_val |= IXGBE_CTRL_GIO_DIS;
2106 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
9a799d71
AK		 2107
2108 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2109 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
2110 status = 0;
2111 break;
2112 }
2113 udelay(100);
2114 }
2115
2116 return status;
2117}
2118
2119
2120/**
c44ade9e 2121 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2122 * @hw: pointer to hardware structure
c44ade9e 2123 * @mask: Mask to specify which semaphore to acquire
9a799d71 2124 *
c44ade9e 2125 * Acquires the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 2126 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2127 **/
2128s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2129{
2130 u32 gssr;
2131 u32 swmask = mask;
2132 u32 fwmask = mask << 5;
2133 s32 timeout = 200;
2134
2135 while (timeout) {
2136 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2137 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2138
2139 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2140 if (!(gssr & (fwmask | swmask)))
2141 break;
2142
2143 /*
2144 * Firmware currently using resource (fwmask) or other software
2145 * thread currently using resource (swmask)
2146 */
2147 ixgbe_release_eeprom_semaphore(hw);
2148 msleep(5);
2149 timeout--;
2150 }
2151
2152 if (!timeout) {
2153 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
539e5f02 2154 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2155 }
2156
2157 gssr |= swmask;
2158 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2159
2160 ixgbe_release_eeprom_semaphore(hw);
2161 return 0;
2162}
2163
2164/**
2165 * ixgbe_release_swfw_sync - Release SWFW semaphore
2166 * @hw: pointer to hardware structure
c44ade9e 2167 * @mask: Mask to specify which semaphore to release
9a799d71 2168 *
c44ade9e 2169 * Releases the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 2170 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2171 **/
2172void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2173{
2174 u32 gssr;
2175 u32 swmask = mask;
2176
2177 ixgbe_get_eeprom_semaphore(hw);
2178
2179 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2180 gssr &= ~swmask;
2181 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2182
2183 ixgbe_release_eeprom_semaphore(hw);
2184}
2185
11afc1b1
PW		 2186/**
2187 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2188 * @hw: pointer to hardware structure
2189 * @regval: register value to write to RXCTRL
2190 *
2191 * Enables the Rx DMA unit
2192 **/
2193s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2194{
2195 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2196
2197 return 0;
2198}
87c12017
PW		 2199
2200/**
2201 * ixgbe_blink_led_start_generic - Blink LED based on index.
2202 * @hw: pointer to hardware structure
2203 * @index: led number to blink
2204 **/
2205s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2206{
2207 ixgbe_link_speed speed = 0;
2208 bool link_up = 0;
2209 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2210 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2211
2212 /*
2213 * Link must be up to auto-blink the LEDs;
2214 * Force it if link is down.
2215 */
2216 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2217
2218 if (!link_up) {
50ac58ba 2219 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017
PW		 2220 autoc_reg |= IXGBE_AUTOC_FLU;
2221 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2222 msleep(10);
2223 }
2224
2225 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2226 led_reg |= IXGBE_LED_BLINK(index);
2227 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2228 IXGBE_WRITE_FLUSH(hw);
2229
2230 return 0;
2231}
2232
2233/**
2234 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2235 * @hw: pointer to hardware structure
2236 * @index: led number to stop blinking
2237 **/
2238s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2239{
2240 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2241 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2242
2243 autoc_reg &= ~IXGBE_AUTOC_FLU;
2244 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2245 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2246
2247 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2248 led_reg &= ~IXGBE_LED_BLINK(index);
2249 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2250 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2251 IXGBE_WRITE_FLUSH(hw);
2252
2253 return 0;
2254}
Linux kernel - Deliverables
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