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bonding: use bond_is_lb() when it's appropriate
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
3efac5a0 4 Copyright(c) 1999 - 2009 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
11afc1b1 32#include "ixgbe.h"
9a799d71
AK		 33#include "ixgbe_common.h"
34#include "ixgbe_phy.h"
35
9a799d71 36static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
c44ade9e 37static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 38static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
39static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 40static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
41static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
43 u16 count);
44static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
45static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
46static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 48static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
49
c44ade9e
JB		 50static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
51static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
9a799d71 52static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
c44ade9e 53static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
9a799d71
AK		 54
55/**
c44ade9e 56 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 57 * @hw: pointer to hardware structure
58 *
59 * Starts the hardware by filling the bus info structure and media type, clears
60 * all on chip counters, initializes receive address registers, multicast
61 * table, VLAN filter table, calls routine to set up link and flow control
62 * settings, and leaves transmit and receive units disabled and uninitialized
63 **/
c44ade9e 64s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 65{
66 u32 ctrl_ext;
67
68 /* Set the media type */
69 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
70
71 /* Identify the PHY */
c44ade9e 72 hw->phy.ops.identify(hw);
9a799d71 73
9a799d71 74 /* Clear the VLAN filter table */
c44ade9e 75 hw->mac.ops.clear_vfta(hw);
9a799d71 76
9a799d71 77 /* Clear statistics registers */
c44ade9e 78 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 79
80 /* Set No Snoop Disable */
81 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
82 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
83 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 84 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 85
86 /* Clear adapter stopped flag */
87 hw->adapter_stopped = false;
88
89 return 0;
90}
91
92/**
c44ade9e 93 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 94 * @hw: pointer to hardware structure
95 *
c44ade9e 96 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 97 * structure and media type, clears all on chip counters, initializes receive
98 * address registers, multicast table, VLAN filter table, calls routine to set
99 * up link and flow control settings, and leaves transmit and receive units
100 * disabled and uninitialized
101 **/
c44ade9e 102s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71
AK		 103{
104 /* Reset the hardware */
c44ade9e 105 hw->mac.ops.reset_hw(hw);
9a799d71
AK		 106
107 /* Start the HW */
c44ade9e 108 hw->mac.ops.start_hw(hw);
9a799d71
AK		 109
110 return 0;
111}
112
113/**
c44ade9e 114 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 115 * @hw: pointer to hardware structure
116 *
117 * Clears all hardware statistics counters by reading them from the hardware
118 * Statistics counters are clear on read.
119 **/
c44ade9e 120s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 121{
122 u16 i = 0;
123
124 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
125 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
126 IXGBE_READ_REG(hw, IXGBE_ERRBC);
127 IXGBE_READ_REG(hw, IXGBE_MSPDC);
128 for (i = 0; i < 8; i++)
129 IXGBE_READ_REG(hw, IXGBE_MPC(i));
130
131 IXGBE_READ_REG(hw, IXGBE_MLFC);
132 IXGBE_READ_REG(hw, IXGBE_MRFC);
133 IXGBE_READ_REG(hw, IXGBE_RLEC);
134 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
135 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
136 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
137 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
138
139 for (i = 0; i < 8; i++) {
140 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
141 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
142 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
143 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
144 }
145
146 IXGBE_READ_REG(hw, IXGBE_PRC64);
147 IXGBE_READ_REG(hw, IXGBE_PRC127);
148 IXGBE_READ_REG(hw, IXGBE_PRC255);
149 IXGBE_READ_REG(hw, IXGBE_PRC511);
150 IXGBE_READ_REG(hw, IXGBE_PRC1023);
151 IXGBE_READ_REG(hw, IXGBE_PRC1522);
152 IXGBE_READ_REG(hw, IXGBE_GPRC);
153 IXGBE_READ_REG(hw, IXGBE_BPRC);
154 IXGBE_READ_REG(hw, IXGBE_MPRC);
155 IXGBE_READ_REG(hw, IXGBE_GPTC);
156 IXGBE_READ_REG(hw, IXGBE_GORCL);
157 IXGBE_READ_REG(hw, IXGBE_GORCH);
158 IXGBE_READ_REG(hw, IXGBE_GOTCL);
159 IXGBE_READ_REG(hw, IXGBE_GOTCH);
160 for (i = 0; i < 8; i++)
161 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
162 IXGBE_READ_REG(hw, IXGBE_RUC);
163 IXGBE_READ_REG(hw, IXGBE_RFC);
164 IXGBE_READ_REG(hw, IXGBE_ROC);
165 IXGBE_READ_REG(hw, IXGBE_RJC);
166 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
167 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
168 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
169 IXGBE_READ_REG(hw, IXGBE_TORL);
170 IXGBE_READ_REG(hw, IXGBE_TORH);
171 IXGBE_READ_REG(hw, IXGBE_TPR);
172 IXGBE_READ_REG(hw, IXGBE_TPT);
173 IXGBE_READ_REG(hw, IXGBE_PTC64);
174 IXGBE_READ_REG(hw, IXGBE_PTC127);
175 IXGBE_READ_REG(hw, IXGBE_PTC255);
176 IXGBE_READ_REG(hw, IXGBE_PTC511);
177 IXGBE_READ_REG(hw, IXGBE_PTC1023);
178 IXGBE_READ_REG(hw, IXGBE_PTC1522);
179 IXGBE_READ_REG(hw, IXGBE_MPTC);
180 IXGBE_READ_REG(hw, IXGBE_BPTC);
181 for (i = 0; i < 16; i++) {
182 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
183 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
184 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
185 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
186 }
187
188 return 0;
189}
190
191/**
c44ade9e
JB		 192 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
193 * @hw: pointer to hardware structure
194 * @pba_num: stores the part number from the EEPROM
195 *
196 * Reads the part number from the EEPROM.
197 **/
198s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
199{
200 s32 ret_val;
201 u16 data;
202
203 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
204 if (ret_val) {
205 hw_dbg(hw, "NVM Read Error\n");
206 return ret_val;
207 }
208 *pba_num = (u32)(data << 16);
209
210 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
211 if (ret_val) {
212 hw_dbg(hw, "NVM Read Error\n");
213 return ret_val;
214 }
215 *pba_num |= data;
216
217 return 0;
218}
219
220/**
221 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 222 * @hw: pointer to hardware structure
223 * @mac_addr: Adapter MAC address
224 *
225 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
226 * A reset of the adapter must be performed prior to calling this function
227 * in order for the MAC address to have been loaded from the EEPROM into RAR0
228 **/
c44ade9e 229s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 230{
231 u32 rar_high;
232 u32 rar_low;
233 u16 i;
234
235 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
236 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
237
238 for (i = 0; i < 4; i++)
239 mac_addr[i] = (u8)(rar_low >> (i*8));
240
241 for (i = 0; i < 2; i++)
242 mac_addr[i+4] = (u8)(rar_high >> (i*8));
243
244 return 0;
245}
246
11afc1b1
PW		 247/**
248 * ixgbe_get_bus_info_generic - Generic set PCI bus info
249 * @hw: pointer to hardware structure
250 *
251 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
252 **/
253s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
254{
255 struct ixgbe_adapter *adapter = hw->back;
256 struct ixgbe_mac_info *mac = &hw->mac;
257 u16 link_status;
258
259 hw->bus.type = ixgbe_bus_type_pci_express;
260
261 /* Get the negotiated link width and speed from PCI config space */
262 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
263 &link_status);
264
265 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
266 case IXGBE_PCI_LINK_WIDTH_1:
267 hw->bus.width = ixgbe_bus_width_pcie_x1;
268 break;
269 case IXGBE_PCI_LINK_WIDTH_2:
270 hw->bus.width = ixgbe_bus_width_pcie_x2;
271 break;
272 case IXGBE_PCI_LINK_WIDTH_4:
273 hw->bus.width = ixgbe_bus_width_pcie_x4;
274 break;
275 case IXGBE_PCI_LINK_WIDTH_8:
276 hw->bus.width = ixgbe_bus_width_pcie_x8;
277 break;
278 default:
279 hw->bus.width = ixgbe_bus_width_unknown;
280 break;
281 }
282
283 switch (link_status & IXGBE_PCI_LINK_SPEED) {
284 case IXGBE_PCI_LINK_SPEED_2500:
285 hw->bus.speed = ixgbe_bus_speed_2500;
286 break;
287 case IXGBE_PCI_LINK_SPEED_5000:
288 hw->bus.speed = ixgbe_bus_speed_5000;
289 break;
290 default:
291 hw->bus.speed = ixgbe_bus_speed_unknown;
292 break;
293 }
294
295 mac->ops.set_lan_id(hw);
296
297 return 0;
298}
299
300/**
301 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
302 * @hw: pointer to the HW structure
303 *
304 * Determines the LAN function id by reading memory-mapped registers
305 * and swaps the port value if requested.
306 **/
307void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
308{
309 struct ixgbe_bus_info *bus = &hw->bus;
310 u32 reg;
311
312 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
313 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
314 bus->lan_id = bus->func;
315
316 /* check for a port swap */
317 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
318 if (reg & IXGBE_FACTPS_LFS)
319 bus->func ^= 0x1;
320}
321
9a799d71 322/**
c44ade9e 323 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 324 * @hw: pointer to hardware structure
325 *
326 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
327 * disables transmit and receive units. The adapter_stopped flag is used by
328 * the shared code and drivers to determine if the adapter is in a stopped
329 * state and should not touch the hardware.
330 **/
c44ade9e 331s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71
AK		 332{
333 u32 number_of_queues;
334 u32 reg_val;
335 u16 i;
336
337 /*
338 * Set the adapter_stopped flag so other driver functions stop touching
339 * the hardware
340 */
341 hw->adapter_stopped = true;
342
343 /* Disable the receive unit */
344 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
345 reg_val &= ~(IXGBE_RXCTRL_RXEN);
346 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
c44ade9e 347 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 348 msleep(2);
349
350 /* Clear interrupt mask to stop from interrupts being generated */
351 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
352
353 /* Clear any pending interrupts */
354 IXGBE_READ_REG(hw, IXGBE_EICR);
355
356 /* Disable the transmit unit. Each queue must be disabled. */
c44ade9e 357 number_of_queues = hw->mac.max_tx_queues;
9a799d71
AK		 358 for (i = 0; i < number_of_queues; i++) {
359 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
360 if (reg_val & IXGBE_TXDCTL_ENABLE) {
361 reg_val &= ~IXGBE_TXDCTL_ENABLE;
362 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
363 }
364 }
365
c44ade9e
JB		 366 /*
367 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
368 * access and verify no pending requests
369 */
370 if (ixgbe_disable_pcie_master(hw) != 0)
371 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
372
9a799d71
AK		 373 return 0;
374}
375
376/**
c44ade9e 377 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 378 * @hw: pointer to hardware structure
379 * @index: led number to turn on
380 **/
c44ade9e 381s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 382{
383 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
384
385 /* To turn on the LED, set mode to ON. */
386 led_reg &= ~IXGBE_LED_MODE_MASK(index);
387 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
388 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 389 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 390
391 return 0;
392}
393
394/**
c44ade9e 395 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 396 * @hw: pointer to hardware structure
397 * @index: led number to turn off
398 **/
c44ade9e 399s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 400{
401 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
402
403 /* To turn off the LED, set mode to OFF. */
404 led_reg &= ~IXGBE_LED_MODE_MASK(index);
405 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
406 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 407 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 408
409 return 0;
410}
411
9a799d71 412/**
c44ade9e 413 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 414 * @hw: pointer to hardware structure
415 *
416 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
417 * ixgbe_hw struct in order to set up EEPROM access.
418 **/
c44ade9e 419s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 420{
421 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
422 u32 eec;
423 u16 eeprom_size;
424
425 if (eeprom->type == ixgbe_eeprom_uninitialized) {
426 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 427 /* Set default semaphore delay to 10ms which is a well
428 * tested value */
429 eeprom->semaphore_delay = 10;
9a799d71
AK		 430
431 /*
432 * Check for EEPROM present first.
433 * If not present leave as none
434 */
435 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
436 if (eec & IXGBE_EEC_PRES) {
437 eeprom->type = ixgbe_eeprom_spi;
438
439 /*
440 * SPI EEPROM is assumed here. This code would need to
441 * change if a future EEPROM is not SPI.
442 */
443 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
444 IXGBE_EEC_SIZE_SHIFT);
445 eeprom->word_size = 1 << (eeprom_size +
446 IXGBE_EEPROM_WORD_SIZE_SHIFT);
447 }
448
449 if (eec & IXGBE_EEC_ADDR_SIZE)
450 eeprom->address_bits = 16;
451 else
452 eeprom->address_bits = 8;
453 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
454 "%d\n", eeprom->type, eeprom->word_size,
455 eeprom->address_bits);
456 }
457
458 return 0;
459}
460
11afc1b1
PW		 461/**
462 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
463 * @hw: pointer to hardware structure
464 * @offset: offset within the EEPROM to be written to
465 * @data: 16 bit word to be written to the EEPROM
466 *
467 * If ixgbe_eeprom_update_checksum is not called after this function, the
468 * EEPROM will most likely contain an invalid checksum.
469 **/
470s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
471{
472 s32 status;
473 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
474
475 hw->eeprom.ops.init_params(hw);
476
477 if (offset >= hw->eeprom.word_size) {
478 status = IXGBE_ERR_EEPROM;
479 goto out;
480 }
481
482 /* Prepare the EEPROM for writing */
483 status = ixgbe_acquire_eeprom(hw);
484
485 if (status == 0) {
486 if (ixgbe_ready_eeprom(hw) != 0) {
487 ixgbe_release_eeprom(hw);
488 status = IXGBE_ERR_EEPROM;
489 }
490 }
491
492 if (status == 0) {
493 ixgbe_standby_eeprom(hw);
494
495 /* Send the WRITE ENABLE command (8 bit opcode ) */
496 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
497 IXGBE_EEPROM_OPCODE_BITS);
498
499 ixgbe_standby_eeprom(hw);
500
501 /*
502 * Some SPI eeproms use the 8th address bit embedded in the
503 * opcode
504 */
505 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
506 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
507
508 /* Send the Write command (8-bit opcode + addr) */
509 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
510 IXGBE_EEPROM_OPCODE_BITS);
511 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
512 hw->eeprom.address_bits);
513
514 /* Send the data */
515 data = (data >> 8) | (data << 8);
516 ixgbe_shift_out_eeprom_bits(hw, data, 16);
517 ixgbe_standby_eeprom(hw);
518
519 msleep(hw->eeprom.semaphore_delay);
520 /* Done with writing - release the EEPROM */
521 ixgbe_release_eeprom(hw);
522 }
523
524out:
525 return status;
526}
527
9a799d71 528/**
c44ade9e
JB		 529 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
530 * @hw: pointer to hardware structure
531 * @offset: offset within the EEPROM to be read
532 * @data: read 16 bit value from EEPROM
533 *
534 * Reads 16 bit value from EEPROM through bit-bang method
535 **/
536s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
537 u16 *data)
538{
539 s32 status;
540 u16 word_in;
541 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
542
543 hw->eeprom.ops.init_params(hw);
544
545 if (offset >= hw->eeprom.word_size) {
546 status = IXGBE_ERR_EEPROM;
547 goto out;
548 }
549
550 /* Prepare the EEPROM for reading */
551 status = ixgbe_acquire_eeprom(hw);
552
553 if (status == 0) {
554 if (ixgbe_ready_eeprom(hw) != 0) {
555 ixgbe_release_eeprom(hw);
556 status = IXGBE_ERR_EEPROM;
557 }
558 }
559
560 if (status == 0) {
561 ixgbe_standby_eeprom(hw);
562
563 /*
564 * Some SPI eeproms use the 8th address bit embedded in the
565 * opcode
566 */
567 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
568 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
569
570 /* Send the READ command (opcode + addr) */
571 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
572 IXGBE_EEPROM_OPCODE_BITS);
573 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
574 hw->eeprom.address_bits);
575
576 /* Read the data. */
577 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
578 *data = (word_in >> 8) | (word_in << 8);
579
580 /* End this read operation */
581 ixgbe_release_eeprom(hw);
582 }
583
584out:
585 return status;
586}
587
588/**
589 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
9a799d71
AK		 590 * @hw: pointer to hardware structure
591 * @offset: offset of word in the EEPROM to read
592 * @data: word read from the EEPROM
593 *
594 * Reads a 16 bit word from the EEPROM using the EERD register.
595 **/
c44ade9e 596s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
9a799d71
AK		 597{
598 u32 eerd;
599 s32 status;
600
c44ade9e
JB		 601 hw->eeprom.ops.init_params(hw);
602
603 if (offset >= hw->eeprom.word_size) {
604 status = IXGBE_ERR_EEPROM;
605 goto out;
606 }
607
9a799d71
AK		 608 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
609 IXGBE_EEPROM_READ_REG_START;
610
611 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
612 status = ixgbe_poll_eeprom_eerd_done(hw);
613
614 if (status == 0)
615 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
b4617240 616 IXGBE_EEPROM_READ_REG_DATA);
9a799d71
AK		 617 else
618 hw_dbg(hw, "Eeprom read timed out\n");
619
c44ade9e 620out:
9a799d71
AK		 621 return status;
622}
623
624/**
625 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
626 * @hw: pointer to hardware structure
627 *
628 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
629 **/
630static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
631{
632 u32 i;
633 u32 reg;
634 s32 status = IXGBE_ERR_EEPROM;
635
636 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
637 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
638 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
639 status = 0;
640 break;
641 }
642 udelay(5);
643 }
644 return status;
645}
646
c44ade9e
JB		 647/**
648 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
649 * @hw: pointer to hardware structure
650 *
651 * Prepares EEPROM for access using bit-bang method. This function should
652 * be called before issuing a command to the EEPROM.
653 **/
654static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
655{
656 s32 status = 0;
fc1f2095 657 u32 eec = 0;
c44ade9e
JB		 658 u32 i;
659
660 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
661 status = IXGBE_ERR_SWFW_SYNC;
662
663 if (status == 0) {
664 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
665
666 /* Request EEPROM Access */
667 eec |= IXGBE_EEC_REQ;
668 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
669
670 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
671 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
672 if (eec & IXGBE_EEC_GNT)
673 break;
674 udelay(5);
675 }
676
677 /* Release if grant not acquired */
678 if (!(eec & IXGBE_EEC_GNT)) {
679 eec &= ~IXGBE_EEC_REQ;
680 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
681 hw_dbg(hw, "Could not acquire EEPROM grant\n");
682
683 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
684 status = IXGBE_ERR_EEPROM;
685 }
686 }
687
688 /* Setup EEPROM for Read/Write */
689 if (status == 0) {
690 /* Clear CS and SK */
691 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
692 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
693 IXGBE_WRITE_FLUSH(hw);
694 udelay(1);
695 }
696 return status;
697}
698
9a799d71
AK		 699/**
700 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
701 * @hw: pointer to hardware structure
702 *
703 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
704 **/
705static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
706{
707 s32 status = IXGBE_ERR_EEPROM;
708 u32 timeout;
709 u32 i;
710 u32 swsm;
711
712 /* Set timeout value based on size of EEPROM */
713 timeout = hw->eeprom.word_size + 1;
714
715 /* Get SMBI software semaphore between device drivers first */
716 for (i = 0; i < timeout; i++) {
717 /*
718 * If the SMBI bit is 0 when we read it, then the bit will be
719 * set and we have the semaphore
720 */
721 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
722 if (!(swsm & IXGBE_SWSM_SMBI)) {
723 status = 0;
724 break;
725 }
726 msleep(1);
727 }
728
729 /* Now get the semaphore between SW/FW through the SWESMBI bit */
730 if (status == 0) {
731 for (i = 0; i < timeout; i++) {
732 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
733
734 /* Set the SW EEPROM semaphore bit to request access */
735 swsm |= IXGBE_SWSM_SWESMBI;
736 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
737
738 /*
739 * If we set the bit successfully then we got the
740 * semaphore.
741 */
742 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
743 if (swsm & IXGBE_SWSM_SWESMBI)
744 break;
745
746 udelay(50);
747 }
748
749 /*
750 * Release semaphores and return error if SW EEPROM semaphore
751 * was not granted because we don't have access to the EEPROM
752 */
753 if (i >= timeout) {
754 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
b4617240 755 "not granted.\n");
9a799d71
AK		 756 ixgbe_release_eeprom_semaphore(hw);
757 status = IXGBE_ERR_EEPROM;
758 }
759 }
760
761 return status;
762}
763
764/**
765 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
766 * @hw: pointer to hardware structure
767 *
768 * This function clears hardware semaphore bits.
769 **/
770static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
771{
772 u32 swsm;
773
774 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
775
776 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
777 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
778 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 779 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 780}
781
c44ade9e
JB		 782/**
783 * ixgbe_ready_eeprom - Polls for EEPROM ready
784 * @hw: pointer to hardware structure
785 **/
786static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
787{
788 s32 status = 0;
789 u16 i;
790 u8 spi_stat_reg;
791
792 /*
793 * Read "Status Register" repeatedly until the LSB is cleared. The
794 * EEPROM will signal that the command has been completed by clearing
795 * bit 0 of the internal status register. If it's not cleared within
796 * 5 milliseconds, then error out.
797 */
798 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
799 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
800 IXGBE_EEPROM_OPCODE_BITS);
801 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
802 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
803 break;
804
805 udelay(5);
806 ixgbe_standby_eeprom(hw);
807 };
808
809 /*
810 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
811 * devices (and only 0-5mSec on 5V devices)
812 */
813 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
814 hw_dbg(hw, "SPI EEPROM Status error\n");
815 status = IXGBE_ERR_EEPROM;
816 }
817
818 return status;
819}
820
821/**
822 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
823 * @hw: pointer to hardware structure
824 **/
825static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
826{
827 u32 eec;
828
829 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
830
831 /* Toggle CS to flush commands */
832 eec |= IXGBE_EEC_CS;
833 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
834 IXGBE_WRITE_FLUSH(hw);
835 udelay(1);
836 eec &= ~IXGBE_EEC_CS;
837 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
838 IXGBE_WRITE_FLUSH(hw);
839 udelay(1);
840}
841
842/**
843 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
844 * @hw: pointer to hardware structure
845 * @data: data to send to the EEPROM
846 * @count: number of bits to shift out
847 **/
848static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
849 u16 count)
850{
851 u32 eec;
852 u32 mask;
853 u32 i;
854
855 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
856
857 /*
858 * Mask is used to shift "count" bits of "data" out to the EEPROM
859 * one bit at a time. Determine the starting bit based on count
860 */
861 mask = 0x01 << (count - 1);
862
863 for (i = 0; i < count; i++) {
864 /*
865 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
866 * "1", and then raising and then lowering the clock (the SK
867 * bit controls the clock input to the EEPROM). A "0" is
868 * shifted out to the EEPROM by setting "DI" to "0" and then
869 * raising and then lowering the clock.
870 */
871 if (data & mask)
872 eec |= IXGBE_EEC_DI;
873 else
874 eec &= ~IXGBE_EEC_DI;
875
876 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
877 IXGBE_WRITE_FLUSH(hw);
878
879 udelay(1);
880
881 ixgbe_raise_eeprom_clk(hw, &eec);
882 ixgbe_lower_eeprom_clk(hw, &eec);
883
884 /*
885 * Shift mask to signify next bit of data to shift in to the
886 * EEPROM
887 */
888 mask = mask >> 1;
889 };
890
891 /* We leave the "DI" bit set to "0" when we leave this routine. */
892 eec &= ~IXGBE_EEC_DI;
893 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
894 IXGBE_WRITE_FLUSH(hw);
895}
896
897/**
898 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
899 * @hw: pointer to hardware structure
900 **/
901static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
902{
903 u32 eec;
904 u32 i;
905 u16 data = 0;
906
907 /*
908 * In order to read a register from the EEPROM, we need to shift
909 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
910 * the clock input to the EEPROM (setting the SK bit), and then reading
911 * the value of the "DO" bit. During this "shifting in" process the
912 * "DI" bit should always be clear.
913 */
914 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
915
916 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
917
918 for (i = 0; i < count; i++) {
919 data = data << 1;
920 ixgbe_raise_eeprom_clk(hw, &eec);
921
922 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
923
924 eec &= ~(IXGBE_EEC_DI);
925 if (eec & IXGBE_EEC_DO)
926 data |= 1;
927
928 ixgbe_lower_eeprom_clk(hw, &eec);
929 }
930
931 return data;
932}
933
934/**
935 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
936 * @hw: pointer to hardware structure
937 * @eec: EEC register's current value
938 **/
939static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
940{
941 /*
942 * Raise the clock input to the EEPROM
943 * (setting the SK bit), then delay
944 */
945 *eec = *eec | IXGBE_EEC_SK;
946 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
947 IXGBE_WRITE_FLUSH(hw);
948 udelay(1);
949}
950
951/**
952 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
953 * @hw: pointer to hardware structure
954 * @eecd: EECD's current value
955 **/
956static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
957{
958 /*
959 * Lower the clock input to the EEPROM (clearing the SK bit), then
960 * delay
961 */
962 *eec = *eec & ~IXGBE_EEC_SK;
963 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
964 IXGBE_WRITE_FLUSH(hw);
965 udelay(1);
966}
967
968/**
969 * ixgbe_release_eeprom - Release EEPROM, release semaphores
970 * @hw: pointer to hardware structure
971 **/
972static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
973{
974 u32 eec;
975
976 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
977
978 eec |= IXGBE_EEC_CS; /* Pull CS high */
979 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
980
981 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
982 IXGBE_WRITE_FLUSH(hw);
983
984 udelay(1);
985
986 /* Stop requesting EEPROM access */
987 eec &= ~IXGBE_EEC_REQ;
988 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
989
990 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
991}
992
9a799d71
AK		 993/**
994 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
995 * @hw: pointer to hardware structure
996 **/
997static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
998{
999 u16 i;
1000 u16 j;
1001 u16 checksum = 0;
1002 u16 length = 0;
1003 u16 pointer = 0;
1004 u16 word = 0;
1005
1006 /* Include 0x0-0x3F in the checksum */
1007 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
c44ade9e 1008 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
9a799d71
AK		 1009 hw_dbg(hw, "EEPROM read failed\n");
1010 break;
1011 }
1012 checksum += word;
1013 }
1014
1015 /* Include all data from pointers except for the fw pointer */
1016 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
c44ade9e 1017 hw->eeprom.ops.read(hw, i, &pointer);
9a799d71
AK		 1018
1019 /* Make sure the pointer seems valid */
1020 if (pointer != 0xFFFF && pointer != 0) {
c44ade9e 1021 hw->eeprom.ops.read(hw, pointer, &length);
9a799d71
AK		 1022
1023 if (length != 0xFFFF && length != 0) {
1024 for (j = pointer+1; j <= pointer+length; j++) {
c44ade9e 1025 hw->eeprom.ops.read(hw, j, &word);
9a799d71
AK		 1026 checksum += word;
1027 }
1028 }
1029 }
1030 }
1031
1032 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1033
1034 return checksum;
1035}
1036
1037/**
c44ade9e 1038 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1039 * @hw: pointer to hardware structure
1040 * @checksum_val: calculated checksum
1041 *
1042 * Performs checksum calculation and validates the EEPROM checksum. If the
1043 * caller does not need checksum_val, the value can be NULL.
1044 **/
c44ade9e
JB		 1045s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1046 u16 *checksum_val)
9a799d71
AK		 1047{
1048 s32 status;
1049 u16 checksum;
1050 u16 read_checksum = 0;
1051
1052 /*
1053 * Read the first word from the EEPROM. If this times out or fails, do
1054 * not continue or we could be in for a very long wait while every
1055 * EEPROM read fails
1056 */
c44ade9e 1057 status = hw->eeprom.ops.read(hw, 0, &checksum);
9a799d71
AK		 1058
1059 if (status == 0) {
1060 checksum = ixgbe_calc_eeprom_checksum(hw);
1061
c44ade9e 1062 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
9a799d71
AK		 1063
1064 /*
1065 * Verify read checksum from EEPROM is the same as
1066 * calculated checksum
1067 */
1068 if (read_checksum != checksum)
1069 status = IXGBE_ERR_EEPROM_CHECKSUM;
1070
1071 /* If the user cares, return the calculated checksum */
1072 if (checksum_val)
1073 *checksum_val = checksum;
1074 } else {
1075 hw_dbg(hw, "EEPROM read failed\n");
1076 }
1077
1078 return status;
1079}
1080
c44ade9e
JB		 1081/**
1082 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1083 * @hw: pointer to hardware structure
1084 **/
1085s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1086{
1087 s32 status;
1088 u16 checksum;
1089
1090 /*
1091 * Read the first word from the EEPROM. If this times out or fails, do
1092 * not continue or we could be in for a very long wait while every
1093 * EEPROM read fails
1094 */
1095 status = hw->eeprom.ops.read(hw, 0, &checksum);
1096
1097 if (status == 0) {
1098 checksum = ixgbe_calc_eeprom_checksum(hw);
1099 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1100 checksum);
1101 } else {
1102 hw_dbg(hw, "EEPROM read failed\n");
1103 }
1104
1105 return status;
1106}
1107
9a799d71
AK		 1108/**
1109 * ixgbe_validate_mac_addr - Validate MAC address
1110 * @mac_addr: pointer to MAC address.
1111 *
1112 * Tests a MAC address to ensure it is a valid Individual Address
1113 **/
1114s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1115{
1116 s32 status = 0;
1117
1118 /* Make sure it is not a multicast address */
1119 if (IXGBE_IS_MULTICAST(mac_addr))
1120 status = IXGBE_ERR_INVALID_MAC_ADDR;
1121 /* Not a broadcast address */
1122 else if (IXGBE_IS_BROADCAST(mac_addr))
1123 status = IXGBE_ERR_INVALID_MAC_ADDR;
1124 /* Reject the zero address */
1125 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
c44ade9e 1126 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
9a799d71
AK		 1127 status = IXGBE_ERR_INVALID_MAC_ADDR;
1128
1129 return status;
1130}
1131
1132/**
c44ade9e 1133 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1134 * @hw: pointer to hardware structure
9a799d71 1135 * @index: Receive address register to write
c44ade9e
JB		 1136 * @addr: Address to put into receive address register
1137 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1138 * @enable_addr: set flag that address is active
1139 *
1140 * Puts an ethernet address into a receive address register.
1141 **/
c44ade9e
JB		 1142s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1143 u32 enable_addr)
9a799d71
AK		 1144{
1145 u32 rar_low, rar_high;
c44ade9e
JB		 1146 u32 rar_entries = hw->mac.num_rar_entries;
1147
1148 /* setup VMDq pool selection before this RAR gets enabled */
1149 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1150
c44ade9e
JB		 1151 /* Make sure we are using a valid rar index range */
1152 if (index < rar_entries) {
b4617240 1153 /*
c44ade9e
JB		 1154 * HW expects these in little endian so we reverse the byte
1155 * order from network order (big endian) to little endian
b4617240
PW		 1156 */
1157 rar_low = ((u32)addr[0] |
1158 ((u32)addr[1] << 8) |
1159 ((u32)addr[2] << 16) |
1160 ((u32)addr[3] << 24));
c44ade9e
JB		 1161 /*
1162 * Some parts put the VMDq setting in the extra RAH bits,
1163 * so save everything except the lower 16 bits that hold part
1164 * of the address and the address valid bit.
1165 */
1166 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1167 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1168 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1169
b4617240
PW		 1170 if (enable_addr != 0)
1171 rar_high |= IXGBE_RAH_AV;
9a799d71 1172
b4617240
PW		 1173 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1174 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1175 } else {
1176 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1177 }
1178
1179 return 0;
1180}
1181
1182/**
1183 * ixgbe_clear_rar_generic - Remove Rx address register
1184 * @hw: pointer to hardware structure
1185 * @index: Receive address register to write
1186 *
1187 * Clears an ethernet address from a receive address register.
1188 **/
1189s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1190{
1191 u32 rar_high;
1192 u32 rar_entries = hw->mac.num_rar_entries;
1193
1194 /* Make sure we are using a valid rar index range */
1195 if (index < rar_entries) {
1196 /*
1197 * Some parts put the VMDq setting in the extra RAH bits,
1198 * so save everything except the lower 16 bits that hold part
1199 * of the address and the address valid bit.
1200 */
1201 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1202 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1203
1204 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1205 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1206 } else {
1207 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1208 }
1209
1210 /* clear VMDq pool/queue selection for this RAR */
1211 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1212
1213 return 0;
1214}
1215
1216/**
c44ade9e
JB		 1217 * ixgbe_enable_rar - Enable Rx address register
1218 * @hw: pointer to hardware structure
1219 * @index: index into the RAR table
1220 *
1221 * Enables the select receive address register.
1222 **/
1223static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1224{
1225 u32 rar_high;
1226
1227 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1228 rar_high |= IXGBE_RAH_AV;
1229 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1230}
1231
1232/**
1233 * ixgbe_disable_rar - Disable Rx address register
1234 * @hw: pointer to hardware structure
1235 * @index: index into the RAR table
1236 *
1237 * Disables the select receive address register.
1238 **/
1239static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1240{
1241 u32 rar_high;
1242
1243 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1244 rar_high &= (~IXGBE_RAH_AV);
1245 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1246}
1247
1248/**
1249 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1250 * @hw: pointer to hardware structure
1251 *
1252 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1253 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1254 * the receiver is in reset when the routine is called.
1255 **/
c44ade9e 1256s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1257{
1258 u32 i;
2c5645cf 1259 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1260
1261 /*
1262 * If the current mac address is valid, assume it is a software override
1263 * to the permanent address.
1264 * Otherwise, use the permanent address from the eeprom.
1265 */
1266 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1267 IXGBE_ERR_INVALID_MAC_ADDR) {
1268 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1269 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71
AK		 1270
1271 hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
b4617240
PW		 1272 hw->mac.addr[0], hw->mac.addr[1],
1273 hw->mac.addr[2]);
9a799d71 1274 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
b4617240 1275 hw->mac.addr[4], hw->mac.addr[5]);
9a799d71
AK		 1276 } else {
1277 /* Setup the receive address. */
1278 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1279 hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
b4617240
PW		 1280 hw->mac.addr[0], hw->mac.addr[1],
1281 hw->mac.addr[2]);
9a799d71 1282 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
b4617240 1283 hw->mac.addr[4], hw->mac.addr[5]);
9a799d71 1284
c44ade9e 1285 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71 1286 }
c44ade9e 1287 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1288
1289 hw->addr_ctrl.rar_used_count = 1;
1290
1291 /* Zero out the other receive addresses. */
c44ade9e 1292 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1293 for (i = 1; i < rar_entries; i++) {
1294 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1295 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1296 }
1297
1298 /* Clear the MTA */
1299 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1300 hw->addr_ctrl.mta_in_use = 0;
1301 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1302
1303 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1304 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1305 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1306
c44ade9e
JB		 1307 if (hw->mac.ops.init_uta_tables)
1308 hw->mac.ops.init_uta_tables(hw);
1309
9a799d71
AK		 1310 return 0;
1311}
1312
2c5645cf
CL		 1313/**
1314 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1315 * @hw: pointer to hardware structure
1316 * @addr: new address
1317 *
1318 * Adds it to unused receive address register or goes into promiscuous mode.
1319 **/
c44ade9e 1320static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2c5645cf
CL		 1321{
1322 u32 rar_entries = hw->mac.num_rar_entries;
1323 u32 rar;
1324
1325 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1326 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1327
1328 /*
1329 * Place this address in the RAR if there is room,
1330 * else put the controller into promiscuous mode
1331 */
1332 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1333 rar = hw->addr_ctrl.rar_used_count -
1334 hw->addr_ctrl.mc_addr_in_rar_count;
c44ade9e 1335 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2c5645cf
CL		 1336 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1337 hw->addr_ctrl.rar_used_count++;
1338 } else {
1339 hw->addr_ctrl.overflow_promisc++;
1340 }
1341
1342 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1343}
1344
1345/**
c44ade9e 1346 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2c5645cf
CL		 1347 * @hw: pointer to hardware structure
1348 * @addr_list: the list of new addresses
1349 * @addr_count: number of addresses
1350 * @next: iterator function to walk the address list
1351 *
1352 * The given list replaces any existing list. Clears the secondary addrs from
1353 * receive address registers. Uses unused receive address registers for the
1354 * first secondary addresses, and falls back to promiscuous mode as needed.
1355 *
1356 * Drivers using secondary unicast addresses must set user_set_promisc when
1357 * manually putting the device into promiscuous mode.
1358 **/
c44ade9e 1359s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2c5645cf
CL		 1360 u32 addr_count, ixgbe_mc_addr_itr next)
1361{
1362 u8 *addr;
1363 u32 i;
1364 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1365 u32 uc_addr_in_use;
1366 u32 fctrl;
1367 u32 vmdq;
1368
1369 /*
1370 * Clear accounting of old secondary address list,
1371 * don't count RAR[0]
1372 */
495dce12 1373 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2c5645cf
CL		 1374 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1375 hw->addr_ctrl.overflow_promisc = 0;
1376
1377 /* Zero out the other receive addresses */
1378 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use);
1379 for (i = 1; i <= uc_addr_in_use; i++) {
1380 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1381 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1382 }
1383
1384 /* Add the new addresses */
1385 for (i = 0; i < addr_count; i++) {
1386 hw_dbg(hw, " Adding the secondary addresses:\n");
1387 addr = next(hw, &addr_list, &vmdq);
c44ade9e 1388 ixgbe_add_uc_addr(hw, addr, vmdq);
2c5645cf
CL		 1389 }
1390
1391 if (hw->addr_ctrl.overflow_promisc) {
1392 /* enable promisc if not already in overflow or set by user */
1393 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1394 hw_dbg(hw, " Entering address overflow promisc mode\n");
1395 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1396 fctrl |= IXGBE_FCTRL_UPE;
1397 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1398 }
1399 } else {
1400 /* only disable if set by overflow, not by user */
1401 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1402 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1403 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1404 fctrl &= ~IXGBE_FCTRL_UPE;
1405 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1406 }
1407 }
1408
c44ade9e 1409 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
2c5645cf
CL		 1410 return 0;
1411}
1412
9a799d71
AK		 1413/**
1414 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1415 * @hw: pointer to hardware structure
1416 * @mc_addr: the multicast address
1417 *
1418 * Extracts the 12 bits, from a multicast address, to determine which
1419 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1420 * incoming rx multicast addresses, to determine the bit-vector to check in
1421 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1422 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1423 * to mc_filter_type.
1424 **/
1425static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1426{
1427 u32 vector = 0;
1428
1429 switch (hw->mac.mc_filter_type) {
b4617240 1430 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1431 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1432 break;
b4617240 1433 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1434 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1435 break;
b4617240 1436 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1437 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1438 break;
b4617240 1439 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1440 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1441 break;
b4617240 1442 default: /* Invalid mc_filter_type */
9a799d71
AK		 1443 hw_dbg(hw, "MC filter type param set incorrectly\n");
1444 break;
1445 }
1446
1447 /* vector can only be 12-bits or boundary will be exceeded */
1448 vector &= 0xFFF;
1449 return vector;
1450}
1451
1452/**
1453 * ixgbe_set_mta - Set bit-vector in multicast table
1454 * @hw: pointer to hardware structure
1455 * @hash_value: Multicast address hash value
1456 *
1457 * Sets the bit-vector in the multicast table.
1458 **/
1459static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1460{
1461 u32 vector;
1462 u32 vector_bit;
1463 u32 vector_reg;
1464 u32 mta_reg;
1465
1466 hw->addr_ctrl.mta_in_use++;
1467
1468 vector = ixgbe_mta_vector(hw, mc_addr);
1469 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1470
1471 /*
1472 * The MTA is a register array of 128 32-bit registers. It is treated
1473 * like an array of 4096 bits. We want to set bit
1474 * BitArray[vector_value]. So we figure out what register the bit is
1475 * in, read it, OR in the new bit, then write back the new value. The
1476 * register is determined by the upper 7 bits of the vector value and
1477 * the bit within that register are determined by the lower 5 bits of
1478 * the value.
1479 */
1480 vector_reg = (vector >> 5) & 0x7F;
1481 vector_bit = vector & 0x1F;
1482 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1483 mta_reg |= (1 << vector_bit);
1484 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1485}
1486
9a799d71 1487/**
c44ade9e 1488 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71
AK		 1489 * @hw: pointer to hardware structure
1490 * @mc_addr_list: the list of new multicast addresses
1491 * @mc_addr_count: number of addresses
2c5645cf 1492 * @next: iterator function to walk the multicast address list
9a799d71
AK		 1493 *
1494 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1495 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1496 * registers for the first multicast addresses, and hashes the rest into the
1497 * multicast table.
1498 **/
c44ade9e 1499s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
b4617240 1500 u32 mc_addr_count, ixgbe_mc_addr_itr next)
9a799d71
AK		 1501{
1502 u32 i;
2c5645cf 1503 u32 vmdq;
9a799d71
AK		 1504
1505 /*
1506 * Set the new number of MC addresses that we are being requested to
1507 * use.
1508 */
1509 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
9a799d71
AK		 1510 hw->addr_ctrl.mta_in_use = 0;
1511
9a799d71
AK		 1512 /* Clear the MTA */
1513 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1514 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1515 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1516
1517 /* Add the new addresses */
1518 for (i = 0; i < mc_addr_count; i++) {
1519 hw_dbg(hw, " Adding the multicast addresses:\n");
495dce12 1520 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
9a799d71
AK		 1521 }
1522
1523 /* Enable mta */
1524 if (hw->addr_ctrl.mta_in_use > 0)
1525 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
b4617240 1526 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 1527
c44ade9e 1528 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 1529 return 0;
1530}
1531
1532/**
c44ade9e 1533 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 1534 * @hw: pointer to hardware structure
1535 *
c44ade9e 1536 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 1537 **/
c44ade9e 1538s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1539{
c44ade9e
JB		 1540 u32 i;
1541 u32 rar_entries = hw->mac.num_rar_entries;
1542 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 1543
c44ade9e
JB		 1544 if (a->mc_addr_in_rar_count > 0)
1545 for (i = (rar_entries - a->mc_addr_in_rar_count);
1546 i < rar_entries; i++)
1547 ixgbe_enable_rar(hw, i);
9a799d71 1548
c44ade9e
JB		 1549 if (a->mta_in_use > 0)
1550 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1551 hw->mac.mc_filter_type);
9a799d71
AK		 1552
1553 return 0;
1554}
1555
1556/**
c44ade9e 1557 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 1558 * @hw: pointer to hardware structure
9a799d71 1559 *
c44ade9e 1560 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 1561 **/
c44ade9e 1562s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 1563{
c44ade9e
JB		 1564 u32 i;
1565 u32 rar_entries = hw->mac.num_rar_entries;
1566 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 1567
c44ade9e
JB		 1568 if (a->mc_addr_in_rar_count > 0)
1569 for (i = (rar_entries - a->mc_addr_in_rar_count);
1570 i < rar_entries; i++)
1571 ixgbe_disable_rar(hw, i);
9a799d71 1572
c44ade9e
JB		 1573 if (a->mta_in_use > 0)
1574 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 1575
1576 return 0;
1577}
1578
11afc1b1
PW		 1579/**
1580 * ixgbe_fc_enable - Enable flow control
1581 * @hw: pointer to hardware structure
1582 * @packetbuf_num: packet buffer number (0-7)
1583 *
1584 * Enable flow control according to the current settings.
1585 **/
1586s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
1587{
1588 s32 ret_val = 0;
1589 u32 mflcn_reg;
1590 u32 fccfg_reg;
1591 u32 reg;
70b77628
PWJ		 1592 u32 rx_pba_size;
1593
1594#ifdef CONFIG_DCB
1595 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1596 goto out;
1597
1598#endif /* CONFIG_DCB */
11afc1b1
PW		 1599
1600 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1601 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1602
1603 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1604 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1605
1606 /*
1607 * The possible values of fc.current_mode are:
1608 * 0: Flow control is completely disabled
1609 * 1: Rx flow control is enabled (we can receive pause frames,
1610 * but not send pause frames).
bb3daa4a
PW		 1611 * 2: Tx flow control is enabled (we can send pause frames but
1612 * we do not support receiving pause frames).
11afc1b1 1613 * 3: Both Rx and Tx flow control (symmetric) are enabled.
bb3daa4a 1614 * 4: Priority Flow Control is enabled.
11afc1b1
PW		 1615 * other: Invalid.
1616 */
1617 switch (hw->fc.current_mode) {
1618 case ixgbe_fc_none:
1619 /* Flow control completely disabled by software override. */
1620 break;
1621 case ixgbe_fc_rx_pause:
1622 /*
1623 * Rx Flow control is enabled and Tx Flow control is
1624 * disabled by software override. Since there really
1625 * isn't a way to advertise that we are capable of RX
1626 * Pause ONLY, we will advertise that we support both
1627 * symmetric and asymmetric Rx PAUSE. Later, we will
1628 * disable the adapter's ability to send PAUSE frames.
1629 */
1630 mflcn_reg |= IXGBE_MFLCN_RFCE;
1631 break;
1632 case ixgbe_fc_tx_pause:
1633 /*
1634 * Tx Flow control is enabled, and Rx Flow control is
1635 * disabled by software override.
1636 */
1637 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1638 break;
1639 case ixgbe_fc_full:
1640 /* Flow control (both Rx and Tx) is enabled by SW override. */
1641 mflcn_reg |= IXGBE_MFLCN_RFCE;
1642 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1643 break;
bb3daa4a
PW		 1644#ifdef CONFIG_DCB
1645 case ixgbe_fc_pfc:
1646 goto out;
1647 break;
1648#endif
11afc1b1
PW		 1649 default:
1650 hw_dbg(hw, "Flow control param set incorrectly\n");
1651 ret_val = -IXGBE_ERR_CONFIG;
1652 goto out;
1653 break;
1654 }
1655
1656 /* Enable 802.3x based flow control settings. */
2132d381 1657 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 1658 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1659 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1660
70b77628
PWJ		 1661 reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
1662 /* Thresholds are different for link flow control when in DCB mode */
1663 if (reg & IXGBE_MTQC_RT_ENA) {
70b77628 1664 /* Always disable XON for LFC when in DCB mode */
264857b8
PWJ		 1665 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), 0);
1666
1667 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
70b77628
PWJ		 1668 reg = (rx_pba_size >> 2) & 0xFFE0;
1669 if (hw->fc.current_mode & ixgbe_fc_tx_pause)
1670 reg |= IXGBE_FCRTH_FCEN;
1671 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
1672 } else {
1673 /*
1674 * Set up and enable Rx high/low water mark thresholds,
1675 * enable XON.
1676 */
1677 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1678 if (hw->fc.send_xon) {
1679 IXGBE_WRITE_REG(hw,
1680 IXGBE_FCRTL_82599(packetbuf_num),
1681 (hw->fc.low_water |
1682 IXGBE_FCRTL_XONE));
1683 } else {
1684 IXGBE_WRITE_REG(hw,
1685 IXGBE_FCRTL_82599(packetbuf_num),
1686 hw->fc.low_water);
1687 }
1688
1689 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1690 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1691 }
11afc1b1
PW		 1692 }
1693
1694 /* Configure pause time (2 TCs per register) */
70b77628 1695 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
11afc1b1
PW		 1696 if ((packetbuf_num & 1) == 0)
1697 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1698 else
1699 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1700 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1701
1702 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1703
1704out:
1705 return ret_val;
1706}
1707
0ecc061d
PWJ		 1708/**
1709 * ixgbe_fc_autoneg - Configure flow control
1710 * @hw: pointer to hardware structure
1711 *
1712 * Negotiates flow control capabilities with link partner using autoneg and
1713 * applies the results.
1714 **/
1715s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1716{
1717 s32 ret_val = 0;
1718 u32 i, reg, pcs_anadv_reg, pcs_lpab_reg;
1719
1720 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1721
1722 /*
1723 * The possible values of fc.current_mode are:
1724 * 0: Flow control is completely disabled
1725 * 1: Rx flow control is enabled (we can receive pause frames,
1726 * but not send pause frames).
1727 * 2: Tx flow control is enabled (we can send pause frames but
1728 * we do not support receiving pause frames).
1729 * 3: Both Rx and Tx flow control (symmetric) are enabled.
bb3daa4a 1730 * 4: Priority Flow Control is enabled.
0ecc061d
PWJ		 1731 * other: Invalid.
1732 */
1733 switch (hw->fc.current_mode) {
1734 case ixgbe_fc_none:
1735 /* Flow control completely disabled by software override. */
1736 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1737 break;
1738 case ixgbe_fc_rx_pause:
1739 /*
1740 * Rx Flow control is enabled and Tx Flow control is
1741 * disabled by software override. Since there really
1742 * isn't a way to advertise that we are capable of RX
1743 * Pause ONLY, we will advertise that we support both
1744 * symmetric and asymmetric Rx PAUSE. Later, we will
1745 * disable the adapter's ability to send PAUSE frames.
1746 */
1747 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1748 break;
1749 case ixgbe_fc_tx_pause:
1750 /*
1751 * Tx Flow control is enabled, and Rx Flow control is
1752 * disabled by software override.
1753 */
1754 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1755 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1756 break;
1757 case ixgbe_fc_full:
1758 /* Flow control (both Rx and Tx) is enabled by SW override. */
1759 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1760 break;
bb3daa4a
PW		 1761#ifdef CONFIG_DCB
1762 case ixgbe_fc_pfc:
1763 goto out;
1764 break;
1765#endif
0ecc061d
PWJ		 1766 default:
1767 hw_dbg(hw, "Flow control param set incorrectly\n");
1768 ret_val = -IXGBE_ERR_CONFIG;
1769 goto out;
1770 break;
1771 }
1772
1773 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
1774 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
1775
1776 /* Set PCS register for autoneg */
1777 /* Enable and restart autoneg */
1778 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
1779
1780 /* Disable AN timeout */
1781 if (hw->fc.strict_ieee)
1782 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
1783
1784 hw_dbg(hw, "Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1785 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
1786
1787 /* See if autonegotiation has succeeded */
1788 hw->mac.autoneg_succeeded = 0;
1789 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1790 msleep(10);
1791 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1792 if ((reg & (IXGBE_PCS1GLSTA_LINK_OK |
1793 IXGBE_PCS1GLSTA_AN_COMPLETE)) ==
1794 (IXGBE_PCS1GLSTA_LINK_OK |
1795 IXGBE_PCS1GLSTA_AN_COMPLETE)) {
1796 if (!(reg & IXGBE_PCS1GLSTA_AN_TIMED_OUT))
1797 hw->mac.autoneg_succeeded = 1;
1798 break;
1799 }
1800 }
1801
1802 if (!hw->mac.autoneg_succeeded) {
1803 /* Autoneg failed to achieve a link, so we turn fc off */
1804 hw->fc.current_mode = ixgbe_fc_none;
1805 hw_dbg(hw, "Flow Control = NONE.\n");
1806 goto out;
1807 }
1808
1809 /*
1810 * Read the AN advertisement and LP ability registers and resolve
1811 * local flow control settings accordingly
1812 */
1813 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1814 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1815 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1816 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1817 /*
1818 * Now we need to check if the user selected Rx ONLY
1819 * of pause frames. In this case, we had to advertise
1820 * FULL flow control because we could not advertise RX
1821 * ONLY. Hence, we must now check to see if we need to
1822 * turn OFF the TRANSMISSION of PAUSE frames.
1823 */
1824 if (hw->fc.requested_mode == ixgbe_fc_full) {
1825 hw->fc.current_mode = ixgbe_fc_full;
1826 hw_dbg(hw, "Flow Control = FULL.\n");
1827 } else {
1828 hw->fc.current_mode = ixgbe_fc_rx_pause;
1829 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1830 }
1831 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1832 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1833 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1834 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1835 hw->fc.current_mode = ixgbe_fc_tx_pause;
1836 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1837 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1838 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1839 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1840 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1841 hw->fc.current_mode = ixgbe_fc_rx_pause;
1842 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1843 } else {
1844 hw->fc.current_mode = ixgbe_fc_none;
1845 hw_dbg(hw, "Flow Control = NONE.\n");
1846 }
1847
1848out:
1849 return ret_val;
1850}
1851
11afc1b1
PW		 1852/**
1853 * ixgbe_setup_fc_generic - Set up flow control
1854 * @hw: pointer to hardware structure
1855 *
1856 * Sets up flow control.
1857 **/
1858s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1859{
1860 s32 ret_val = 0;
1861 ixgbe_link_speed speed;
1862 bool link_up;
1863
bb3daa4a
PW		 1864#ifdef CONFIG_DCB
1865 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1866 hw->fc.current_mode = hw->fc.requested_mode;
1867 goto out;
1868 }
1869
1870#endif
11afc1b1
PW		 1871 /* Validate the packetbuf configuration */
1872 if (packetbuf_num < 0 || packetbuf_num > 7) {
1873 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1874 "is 0-7\n", packetbuf_num);
1875 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1876 goto out;
1877 }
1878
1879 /*
1880 * Validate the water mark configuration. Zero water marks are invalid
1881 * because it causes the controller to just blast out fc packets.
1882 */
1883 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
d3e9c56c
PW		 1884 if (hw->fc.requested_mode != ixgbe_fc_none) {
1885 hw_dbg(hw, "Invalid water mark configuration\n");
1886 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1887 goto out;
1888 }
11afc1b1
PW		 1889 }
1890
1891 /*
1892 * Validate the requested mode. Strict IEEE mode does not allow
1893 * ixgbe_fc_rx_pause because it will cause testing anomalies.
1894 */
1895 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1896 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1897 "IEEE mode\n");
1898 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1899 goto out;
1900 }
1901
1902 /*
1903 * 10gig parts do not have a word in the EEPROM to determine the
1904 * default flow control setting, so we explicitly set it to full.
1905 */
1906 if (hw->fc.requested_mode == ixgbe_fc_default)
1907 hw->fc.requested_mode = ixgbe_fc_full;
1908
1909 /*
1910 * Save off the requested flow control mode for use later. Depending
1911 * on the link partner's capabilities, we may or may not use this mode.
1912 */
1913 hw->fc.current_mode = hw->fc.requested_mode;
1914
1915 /* Decide whether to use autoneg or not. */
1916 hw->mac.ops.check_link(hw, &speed, &link_up, false);
71fd570b
DS		 1917 if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber &&
1918 (speed == IXGBE_LINK_SPEED_1GB_FULL))
11afc1b1
PW		 1919 ret_val = ixgbe_fc_autoneg(hw);
1920
1921 if (ret_val)
1922 goto out;
1923
1924 ret_val = ixgbe_fc_enable(hw, packetbuf_num);
1925
1926out:
1927 return ret_val;
1928}
1929
9a799d71
AK		 1930/**
1931 * ixgbe_disable_pcie_master - Disable PCI-express master access
1932 * @hw: pointer to hardware structure
1933 *
1934 * Disables PCI-Express master access and verifies there are no pending
1935 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1936 * bit hasn't caused the master requests to be disabled, else 0
1937 * is returned signifying master requests disabled.
1938 **/
1939s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
1940{
c44ade9e
JB		 1941 u32 i;
1942 u32 reg_val;
1943 u32 number_of_queues;
9a799d71
AK		 1944 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
1945
c44ade9e
JB		 1946 /* Disable the receive unit by stopping each queue */
1947 number_of_queues = hw->mac.max_rx_queues;
1948 for (i = 0; i < number_of_queues; i++) {
1949 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1950 if (reg_val & IXGBE_RXDCTL_ENABLE) {
1951 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1952 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1953 }
1954 }
1955
1956 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
1957 reg_val |= IXGBE_CTRL_GIO_DIS;
1958 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
9a799d71
AK		 1959
1960 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1961 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
1962 status = 0;
1963 break;
1964 }
1965 udelay(100);
1966 }
1967
1968 return status;
1969}
1970
1971
1972/**
c44ade9e 1973 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 1974 * @hw: pointer to hardware structure
c44ade9e 1975 * @mask: Mask to specify which semaphore to acquire
9a799d71 1976 *
c44ade9e 1977 * Acquires the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 1978 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1979 **/
1980s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1981{
1982 u32 gssr;
1983 u32 swmask = mask;
1984 u32 fwmask = mask << 5;
1985 s32 timeout = 200;
1986
1987 while (timeout) {
1988 if (ixgbe_get_eeprom_semaphore(hw))
1989 return -IXGBE_ERR_SWFW_SYNC;
1990
1991 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1992 if (!(gssr & (fwmask | swmask)))
1993 break;
1994
1995 /*
1996 * Firmware currently using resource (fwmask) or other software
1997 * thread currently using resource (swmask)
1998 */
1999 ixgbe_release_eeprom_semaphore(hw);
2000 msleep(5);
2001 timeout--;
2002 }
2003
2004 if (!timeout) {
2005 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
2006 return -IXGBE_ERR_SWFW_SYNC;
2007 }
2008
2009 gssr |= swmask;
2010 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2011
2012 ixgbe_release_eeprom_semaphore(hw);
2013 return 0;
2014}
2015
2016/**
2017 * ixgbe_release_swfw_sync - Release SWFW semaphore
2018 * @hw: pointer to hardware structure
c44ade9e 2019 * @mask: Mask to specify which semaphore to release
9a799d71 2020 *
c44ade9e 2021 * Releases the SWFW semaphore thought the GSSR register for the specified
9a799d71
AK		 2022 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2023 **/
2024void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2025{
2026 u32 gssr;
2027 u32 swmask = mask;
2028
2029 ixgbe_get_eeprom_semaphore(hw);
2030
2031 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2032 gssr &= ~swmask;
2033 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2034
2035 ixgbe_release_eeprom_semaphore(hw);
2036}
2037
11afc1b1
PW		 2038/**
2039 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2040 * @hw: pointer to hardware structure
2041 * @regval: register value to write to RXCTRL
2042 *
2043 * Enables the Rx DMA unit
2044 **/
2045s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2046{
2047 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2048
2049 return 0;
2050}
87c12017
PW		 2051
2052/**
2053 * ixgbe_blink_led_start_generic - Blink LED based on index.
2054 * @hw: pointer to hardware structure
2055 * @index: led number to blink
2056 **/
2057s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2058{
2059 ixgbe_link_speed speed = 0;
2060 bool link_up = 0;
2061 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2062 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2063
2064 /*
2065 * Link must be up to auto-blink the LEDs;
2066 * Force it if link is down.
2067 */
2068 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2069
2070 if (!link_up) {
2071 autoc_reg |= IXGBE_AUTOC_FLU;
2072 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2073 msleep(10);
2074 }
2075
2076 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2077 led_reg |= IXGBE_LED_BLINK(index);
2078 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2079 IXGBE_WRITE_FLUSH(hw);
2080
2081 return 0;
2082}
2083
2084/**
2085 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2086 * @hw: pointer to hardware structure
2087 * @index: led number to stop blinking
2088 **/
2089s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2090{
2091 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2092 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2093
2094 autoc_reg &= ~IXGBE_AUTOC_FLU;
2095 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2096 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2097
2098 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2099 led_reg &= ~IXGBE_LED_BLINK(index);
2100 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2101 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2102 IXGBE_WRITE_FLUSH(hw);
2103
2104 return 0;
2105}
Linux kernel - Deliverables
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