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1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
4 | Copyright(c) 1999 - 2009 Intel Corporation. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #ifndef _IXGBE_FCOE_H | |
29 | #define _IXGBE_FCOE_H | |
30 | ||
31 | #include <scsi/fc/fc_fcoe.h> | |
32 | ||
33 | /* shift bits within STAT fo FCSTAT */ | |
34 | #define IXGBE_RXDADV_FCSTAT_SHIFT 4 | |
35 | ||
36 | /* ddp user buffer */ | |
37 | #define IXGBE_BUFFCNT_MAX 256 /* 8 bits bufcnt */ | |
38 | #define IXGBE_FCPTR_ALIGN 16 | |
39 | #define IXGBE_FCPTR_MAX (IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t)) | |
40 | #define IXGBE_FCBUFF_4KB 0x0 | |
41 | #define IXGBE_FCBUFF_8KB 0x1 | |
42 | #define IXGBE_FCBUFF_16KB 0x2 | |
43 | #define IXGBE_FCBUFF_64KB 0x3 | |
44 | #define IXGBE_FCBUFF_MAX 65536 /* 64KB max */ | |
45 | #define IXGBE_FCBUFF_MIN 4096 /* 4KB min */ | |
46 | #define IXGBE_FCOE_DDP_MAX 512 /* 9 bits xid */ | |
47 | ||
48 | /* fcerr */ | |
49 | #define IXGBE_FCERR_BADCRC 0x00100000 | |
50 | ||
51 | struct ixgbe_fcoe_ddp { | |
52 | int len; | |
53 | u32 err; | |
54 | unsigned int sgc; | |
55 | struct scatterlist *sgl; | |
56 | dma_addr_t udp; | |
d0ed8937 | 57 | u64 *udl; |
e92cbeac YZ |
58 | }; |
59 | ||
60 | struct ixgbe_fcoe { | |
61 | spinlock_t lock; | |
62 | struct pci_pool *pool; | |
63 | struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX]; | |
64 | }; | |
65 | ||
66 | #endif /* _IXGBE_FCOE_H */ |