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DCB: Add support for DCB BCN
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
b4617240 4 Copyright(c) 1999 - 2008 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/ipv6.h>
38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
40#include <linux/ethtool.h>
41#include <linux/if_vlan.h>
42
43#include "ixgbe.h"
44#include "ixgbe_common.h"
45
46char ixgbe_driver_name[] = "ixgbe";
9c8eb720 47static const char ixgbe_driver_string[] =
b4617240 48 "Intel(R) 10 Gigabit PCI Express Network Driver";
9a799d71 49
51ac6445 50#define DRV_VERSION "1.3.30-k2"
9c8eb720 51const char ixgbe_driver_version[] = DRV_VERSION;
b4617240 52static char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation.";
9a799d71
AK		 53
54static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 55 [board_82598] = &ixgbe_82598_info,
9a799d71
AK		 56};
57
58/* ixgbe_pci_tbl - PCI Device ID Table
59 *
60 * Wildcard entries (PCI_ANY_ID) should come last
61 * Last entry must be all 0s
62 *
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
65 */
66static struct pci_device_id ixgbe_pci_tbl[] = {
67 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 68 board_82598 },
9a799d71 69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 70 board_82598 },
0befdb3e
JB		 71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
72 board_82598 },
9a799d71 73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 74 board_82598 },
8d792cd9
JB		 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
76 board_82598 },
b95f5fcb
JB		 77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
78 board_82598 },
9a799d71
AK		 79
80 /* required last entry */
81 {0, }
82};
83MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
84
5dd2d332 85#ifdef CONFIG_IXGBE_DCA
bd0362dd 86static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
b4617240 87 void *p);
bd0362dd
JC		 88static struct notifier_block dca_notifier = {
89 .notifier_call = ixgbe_notify_dca,
90 .next = NULL,
91 .priority = 0
92};
93#endif
94
9a799d71
AK		 95MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
96MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
97MODULE_LICENSE("GPL");
98MODULE_VERSION(DRV_VERSION);
99
100#define DEFAULT_DEBUG_LEVEL_SHIFT 3
101
5eba3699
AV		 102static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
103{
104 u32 ctrl_ext;
105
106 /* Let firmware take over control of h/w */
107 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
108 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 109 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 110}
111
112static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
113{
114 u32 ctrl_ext;
115
116 /* Let firmware know the driver has taken over */
117 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
118 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
b4617240 119 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 120}
9a799d71 121
9a799d71 122static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
b4617240 123 u8 msix_vector)
9a799d71
AK		 124{
125 u32 ivar, index;
126
127 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
128 index = (int_alloc_entry >> 2) & 0x1F;
129 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
130 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
131 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
132 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
133}
134
135static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
b4617240
PW		 136 struct ixgbe_tx_buffer
137 *tx_buffer_info)
9a799d71
AK		 138{
139 if (tx_buffer_info->dma) {
e01c31a5 140 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
b4617240 141 tx_buffer_info->length, PCI_DMA_TODEVICE);
9a799d71
AK		 142 tx_buffer_info->dma = 0;
143 }
144 if (tx_buffer_info->skb) {
145 dev_kfree_skb_any(tx_buffer_info->skb);
146 tx_buffer_info->skb = NULL;
147 }
148 /* tx_buffer_info must be completely set up in the transmit path */
149}
150
151static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
b4617240
PW		 152 struct ixgbe_ring *tx_ring,
153 unsigned int eop)
9a799d71 154{
e01c31a5
JB		 155 struct ixgbe_hw *hw = &adapter->hw;
156 u32 head, tail;
157
9a799d71 158 /* Detect a transmit hang in hardware, this serializes the
e01c31a5
JB		 159 * check with the clearing of time_stamp and movement of eop */
160 head = IXGBE_READ_REG(hw, tx_ring->head);
161 tail = IXGBE_READ_REG(hw, tx_ring->tail);
9a799d71 162 adapter->detect_tx_hung = false;
e01c31a5
JB		 163 if ((head != tail) &&
164 tx_ring->tx_buffer_info[eop].time_stamp &&
9a799d71
AK		 165 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
166 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
167 /* detected Tx unit hang */
e01c31a5
JB		 168 union ixgbe_adv_tx_desc *tx_desc;
169 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
9a799d71 170 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
e01c31a5
JB		 171 " Tx Queue <%d>\n"
172 " TDH, TDT <%x>, <%x>\n"
9a799d71
AK		 173 " next_to_use <%x>\n"
174 " next_to_clean <%x>\n"
175 "tx_buffer_info[next_to_clean]\n"
176 " time_stamp <%lx>\n"
e01c31a5
JB		 177 " jiffies <%lx>\n",
178 tx_ring->queue_index,
179 head, tail,
180 tx_ring->next_to_use, eop,
181 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
9a799d71
AK		 182 return true;
183 }
184
185 return false;
186}
187
b4617240
PW		 188#define IXGBE_MAX_TXD_PWR 14
189#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
e092be60
AV		 190
191/* Tx Descriptors needed, worst case */
192#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
193 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
194#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
b4617240 195 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
e092be60 196
e01c31a5
JB		 197#define GET_TX_HEAD_FROM_RING(ring) (\
198 *(volatile u32 *) \
199 ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
200static void ixgbe_tx_timeout(struct net_device *netdev);
201
9a799d71
AK		 202/**
203 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
204 * @adapter: board private structure
e01c31a5 205 * @tx_ring: tx ring to clean
9a799d71
AK		 206 **/
207static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
e01c31a5 208 struct ixgbe_ring *tx_ring)
9a799d71 209{
e01c31a5 210 union ixgbe_adv_tx_desc *tx_desc;
9a799d71 211 struct ixgbe_tx_buffer *tx_buffer_info;
e01c31a5
JB		 212 struct net_device *netdev = adapter->netdev;
213 struct sk_buff *skb;
214 unsigned int i;
215 u32 head, oldhead;
216 unsigned int count = 0;
217 unsigned int total_bytes = 0, total_packets = 0;
9a799d71 218
e01c31a5
JB		 219 rmb();
220 head = GET_TX_HEAD_FROM_RING(tx_ring);
221 head = le32_to_cpu(head);
9a799d71 222 i = tx_ring->next_to_clean;
e01c31a5
JB		 223 while (1) {
224 while (i != head) {
9a799d71
AK		 225 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
226 tx_buffer_info = &tx_ring->tx_buffer_info[i];
e01c31a5 227 skb = tx_buffer_info->skb;
9a799d71 228
e01c31a5 229 if (skb) {
e092be60 230 unsigned int segs, bytecount;
e01c31a5
JB		 231
232 /* gso_segs is currently only valid for tcp */
e092be60
AV		 233 segs = skb_shinfo(skb)->gso_segs ?: 1;
234 /* multiply data chunks by size of headers */
235 bytecount = ((segs - 1) * skb_headlen(skb)) +
e01c31a5
JB		 236 skb->len;
237 total_packets += segs;
238 total_bytes += bytecount;
e092be60 239 }
e01c31a5 240
9a799d71 241 ixgbe_unmap_and_free_tx_resource(adapter,
e01c31a5 242 tx_buffer_info);
9a799d71
AK		 243
244 i++;
245 if (i == tx_ring->count)
246 i = 0;
9a799d71 247
e01c31a5
JB		 248 count++;
249 if (count == tx_ring->count)
250 goto done_cleaning;
251 }
252 oldhead = head;
253 rmb();
254 head = GET_TX_HEAD_FROM_RING(tx_ring);
255 head = le32_to_cpu(head);
256 if (head == oldhead)
257 goto done_cleaning;
258 } /* while (1) */
259
260done_cleaning:
9a799d71
AK		 261 tx_ring->next_to_clean = i;
262
e092be60 263#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
e01c31a5
JB		 264 if (unlikely(count && netif_carrier_ok(netdev) &&
265 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 266 /* Make sure that anybody stopping the queue after this
267 * sees the new next_to_clean.
268 */
269 smp_mb();
30eba97a
AV		 270 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
271 !test_bit(__IXGBE_DOWN, &adapter->state)) {
272 netif_wake_subqueue(netdev, tx_ring->queue_index);
e01c31a5 273 ++adapter->restart_queue;
30eba97a 274 }
e092be60 275 }
9a799d71 276
e01c31a5
JB		 277 if (adapter->detect_tx_hung) {
278 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
279 /* schedule immediate reset if we believe we hung */
280 DPRINTK(PROBE, INFO,
281 "tx hang %d detected, resetting adapter\n",
282 adapter->tx_timeout_count + 1);
283 ixgbe_tx_timeout(adapter->netdev);
284 }
285 }
9a799d71 286
e01c31a5
JB		 287 /* re-arm the interrupt */
288 if ((total_packets >= tx_ring->work_limit) ||
289 (count == tx_ring->count))
290 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
9a799d71 291
e01c31a5
JB		 292 tx_ring->total_bytes += total_bytes;
293 tx_ring->total_packets += total_packets;
294 tx_ring->stats.bytes += total_bytes;
295 tx_ring->stats.packets += total_packets;
296 adapter->net_stats.tx_bytes += total_bytes;
297 adapter->net_stats.tx_packets += total_packets;
298 return (total_packets ? true : false);
9a799d71
AK		 299}
300
5dd2d332 301#ifdef CONFIG_IXGBE_DCA
bd0362dd 302static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
b4617240 303 struct ixgbe_ring *rx_ring)
bd0362dd
JC		 304{
305 u32 rxctrl;
306 int cpu = get_cpu();
3a581073 307 int q = rx_ring - adapter->rx_ring;
bd0362dd 308
3a581073 309 if (rx_ring->cpu != cpu) {
bd0362dd
JC		 310 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
311 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
96b0e0f6 312 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 313 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
314 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
315 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
3a581073 316 rx_ring->cpu = cpu;
bd0362dd
JC		 317 }
318 put_cpu();
319}
320
321static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
b4617240 322 struct ixgbe_ring *tx_ring)
bd0362dd
JC		 323{
324 u32 txctrl;
325 int cpu = get_cpu();
3a581073 326 int q = tx_ring - adapter->tx_ring;
bd0362dd 327
3a581073 328 if (tx_ring->cpu != cpu) {
bd0362dd
JC		 329 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
330 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
96b0e0f6 331 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
bd0362dd
JC		 332 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
333 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
3a581073 334 tx_ring->cpu = cpu;
bd0362dd
JC		 335 }
336 put_cpu();
337}
338
339static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
340{
341 int i;
342
343 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
344 return;
345
346 for (i = 0; i < adapter->num_tx_queues; i++) {
347 adapter->tx_ring[i].cpu = -1;
348 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
349 }
350 for (i = 0; i < adapter->num_rx_queues; i++) {
351 adapter->rx_ring[i].cpu = -1;
352 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
353 }
354}
355
356static int __ixgbe_notify_dca(struct device *dev, void *data)
357{
358 struct net_device *netdev = dev_get_drvdata(dev);
359 struct ixgbe_adapter *adapter = netdev_priv(netdev);
360 unsigned long event = *(unsigned long *)data;
361
362 switch (event) {
363 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 364 /* if we're already enabled, don't do it again */
365 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
366 break;
bd0362dd
JC		 367 /* Always use CB2 mode, difference is masked
368 * in the CB driver. */
369 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
652f093f 370 if (dca_add_requester(dev) == 0) {
96b0e0f6 371 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 372 ixgbe_setup_dca(adapter);
373 break;
374 }
375 /* Fall Through since DCA is disabled. */
376 case DCA_PROVIDER_REMOVE:
377 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
378 dca_remove_requester(dev);
379 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
380 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
381 }
382 break;
383 }
384
652f093f 385 return 0;
bd0362dd
JC		 386}
387
5dd2d332 388#endif /* CONFIG_IXGBE_DCA */
9a799d71
AK		 389/**
390 * ixgbe_receive_skb - Send a completed packet up the stack
391 * @adapter: board private structure
392 * @skb: packet to send up
177db6ff
MC		 393 * @status: hardware indication of status of receive
394 * @rx_ring: rx descriptor ring (for a specific queue) to setup
395 * @rx_desc: rx descriptor
9a799d71
AK		 396 **/
397static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
b4617240
PW		 398 struct sk_buff *skb, u8 status,
399 struct ixgbe_ring *ring,
177db6ff 400 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 401{
177db6ff
MC		 402 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
403 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 404
177db6ff
MC		 405 if (adapter->netdev->features & NETIF_F_LRO &&
406 skb->ip_summed == CHECKSUM_UNNECESSARY) {
2f90b865 407 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 408 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
409 adapter->vlgrp, tag,
410 rx_desc);
9a799d71 411 else
177db6ff
MC		 412 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
413 ring->lro_used = true;
414 } else {
415 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
2f90b865 416 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 417 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
418 else
419 netif_receive_skb(skb);
420 } else {
2f90b865 421 if (adapter->vlgrp && is_vlan && (tag != 0))
177db6ff
MC		 422 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
423 else
424 netif_rx(skb);
425 }
9a799d71
AK		 426 }
427}
428
e59bd25d
AV		 429/**
430 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
431 * @adapter: address of board private structure
432 * @status_err: hardware indication of status of receive
433 * @skb: skb currently being received and modified
434 **/
9a799d71 435static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
712744be 436 u32 status_err, struct sk_buff *skb)
9a799d71
AK		 437{
438 skb->ip_summed = CHECKSUM_NONE;
439
712744be
JB		 440 /* Rx csum disabled */
441 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 442 return;
e59bd25d
AV		 443
444 /* if IP and error */
445 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
446 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 447 adapter->hw_csum_rx_error++;
448 return;
449 }
e59bd25d
AV		 450
451 if (!(status_err & IXGBE_RXD_STAT_L4CS))
452 return;
453
454 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
455 adapter->hw_csum_rx_error++;
456 return;
457 }
458
9a799d71 459 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 460 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 461 adapter->hw_csum_rx_good++;
462}
463
464/**
465 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
466 * @adapter: address of board private structure
467 **/
468static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
7c6e0a43
JB		 469 struct ixgbe_ring *rx_ring,
470 int cleaned_count)
9a799d71 471{
9a799d71
AK		 472 struct pci_dev *pdev = adapter->pdev;
473 union ixgbe_adv_rx_desc *rx_desc;
3a581073 474 struct ixgbe_rx_buffer *bi;
9a799d71 475 unsigned int i;
7c6e0a43 476 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
9a799d71
AK		 477
478 i = rx_ring->next_to_use;
3a581073 479 bi = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 480
481 while (cleaned_count--) {
482 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
483
762f4c57 484 if (!bi->page_dma &&
3a581073 485 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
3a581073 486 if (!bi->page) {
762f4c57
JB		 487 bi->page = alloc_page(GFP_ATOMIC);
488 if (!bi->page) {
489 adapter->alloc_rx_page_failed++;
490 goto no_buffers;
491 }
492 bi->page_offset = 0;
493 } else {
494 /* use a half page if we're re-using */
495 bi->page_offset ^= (PAGE_SIZE / 2);
9a799d71 496 }
762f4c57
JB		 497
498 bi->page_dma = pci_map_page(pdev, bi->page,
499 bi->page_offset,
500 (PAGE_SIZE / 2),
501 PCI_DMA_FROMDEVICE);
9a799d71
AK		 502 }
503
3a581073 504 if (!bi->skb) {
74ce8dd2
JB		 505 struct sk_buff *skb = netdev_alloc_skb(adapter->netdev,
506 bufsz);
9a799d71
AK		 507
508 if (!skb) {
509 adapter->alloc_rx_buff_failed++;
510 goto no_buffers;
511 }
512
513 /*
514 * Make buffer alignment 2 beyond a 16 byte boundary
515 * this will result in a 16 byte aligned IP header after
516 * the 14 byte MAC header is removed
517 */
518 skb_reserve(skb, NET_IP_ALIGN);
519
3a581073
JB		 520 bi->skb = skb;
521 bi->dma = pci_map_single(pdev, skb->data, bufsz,
522 PCI_DMA_FROMDEVICE);
9a799d71
AK		 523 }
524 /* Refresh the desc even if buffer_addrs didn't change because
525 * each write-back erases this info. */
526 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3a581073
JB		 527 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
528 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 529 } else {
3a581073 530 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 531 }
532
533 i++;
534 if (i == rx_ring->count)
535 i = 0;
3a581073 536 bi = &rx_ring->rx_buffer_info[i];
9a799d71 537 }
7c6e0a43 538
9a799d71
AK		 539no_buffers:
540 if (rx_ring->next_to_use != i) {
541 rx_ring->next_to_use = i;
542 if (i-- == 0)
543 i = (rx_ring->count - 1);
544
545 /*
546 * Force memory writes to complete before letting h/w
547 * know there are new descriptors to fetch. (Only
548 * applicable for weak-ordered memory model archs,
549 * such as IA-64).
550 */
551 wmb();
552 writel(i, adapter->hw.hw_addr + rx_ring->tail);
553 }
554}
555
7c6e0a43
JB		 556static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
557{
558 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
559}
560
561static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
562{
563 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
564}
565
9a799d71 566static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
b4617240
PW		 567 struct ixgbe_ring *rx_ring,
568 int *work_done, int work_to_do)
9a799d71 569{
9a799d71
AK		 570 struct pci_dev *pdev = adapter->pdev;
571 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
572 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
573 struct sk_buff *skb;
574 unsigned int i;
7c6e0a43 575 u32 len, staterr;
177db6ff
MC		 576 u16 hdr_info;
577 bool cleaned = false;
9a799d71 578 int cleaned_count = 0;
d2f4fbe2 579 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
9a799d71
AK		 580
581 i = rx_ring->next_to_clean;
9a799d71
AK		 582 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
583 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
584 rx_buffer_info = &rx_ring->rx_buffer_info[i];
9a799d71
AK		 585
586 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 587 u32 upper_len = 0;
9a799d71
AK		 588 if (*work_done >= work_to_do)
589 break;
590 (*work_done)++;
591
592 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43
JB		 593 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
594 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
762f4c57 595 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
9a799d71
AK		 596 if (hdr_info & IXGBE_RXDADV_SPH)
597 adapter->rx_hdr_split++;
598 if (len > IXGBE_RX_HDR_SIZE)
599 len = IXGBE_RX_HDR_SIZE;
600 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 601 } else {
9a799d71 602 len = le16_to_cpu(rx_desc->wb.upper.length);
7c6e0a43 603 }
9a799d71
AK		 604
605 cleaned = true;
606 skb = rx_buffer_info->skb;
607 prefetch(skb->data - NET_IP_ALIGN);
608 rx_buffer_info->skb = NULL;
609
610 if (len && !skb_shinfo(skb)->nr_frags) {
611 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 612 rx_ring->rx_buf_len + NET_IP_ALIGN,
613 PCI_DMA_FROMDEVICE);
9a799d71
AK		 614 skb_put(skb, len);
615 }
616
617 if (upper_len) {
618 pci_unmap_page(pdev, rx_buffer_info->page_dma,
762f4c57 619 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
9a799d71
AK		 620 rx_buffer_info->page_dma = 0;
621 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
762f4c57
JB		 622 rx_buffer_info->page,
623 rx_buffer_info->page_offset,
624 upper_len);
625
626 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
627 (page_count(rx_buffer_info->page) != 1))
628 rx_buffer_info->page = NULL;
629 else
630 get_page(rx_buffer_info->page);
9a799d71
AK		 631
632 skb->len += upper_len;
633 skb->data_len += upper_len;
634 skb->truesize += upper_len;
635 }
636
637 i++;
638 if (i == rx_ring->count)
639 i = 0;
640 next_buffer = &rx_ring->rx_buffer_info[i];
641
642 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
643 prefetch(next_rxd);
644
645 cleaned_count++;
646 if (staterr & IXGBE_RXD_STAT_EOP) {
647 rx_ring->stats.packets++;
648 rx_ring->stats.bytes += skb->len;
649 } else {
650 rx_buffer_info->skb = next_buffer->skb;
651 rx_buffer_info->dma = next_buffer->dma;
652 next_buffer->skb = skb;
762f4c57 653 next_buffer->dma = 0;
9a799d71
AK		 654 adapter->non_eop_descs++;
655 goto next_desc;
656 }
657
658 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
659 dev_kfree_skb_irq(skb);
660 goto next_desc;
661 }
662
663 ixgbe_rx_checksum(adapter, staterr, skb);
d2f4fbe2
AV		 664
665 /* probably a little skewed due to removing CRC */
666 total_rx_bytes += skb->len;
667 total_rx_packets++;
668
74ce8dd2 669 skb->protocol = eth_type_trans(skb, adapter->netdev);
177db6ff 670 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 671
672next_desc:
673 rx_desc->wb.upper.status_error = 0;
674
675 /* return some buffers to hardware, one at a time is too slow */
676 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
677 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
678 cleaned_count = 0;
679 }
680
681 /* use prefetched values */
682 rx_desc = next_rxd;
683 rx_buffer_info = next_buffer;
684
685 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 686 }
687
688 if (rx_ring->lro_used) {
689 lro_flush_all(&rx_ring->lro_mgr);
690 rx_ring->lro_used = false;
9a799d71
AK		 691 }
692
693 rx_ring->next_to_clean = i;
694 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
695
696 if (cleaned_count)
697 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
698
f494e8fa
AV		 699 rx_ring->total_packets += total_rx_packets;
700 rx_ring->total_bytes += total_rx_bytes;
701 adapter->net_stats.rx_bytes += total_rx_bytes;
702 adapter->net_stats.rx_packets += total_rx_packets;
703
9a799d71
AK		 704 return cleaned;
705}
706
021230d4 707static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 708/**
709 * ixgbe_configure_msix - Configure MSI-X hardware
710 * @adapter: board private structure
711 *
712 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
713 * interrupts.
714 **/
715static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
716{
021230d4
AV		 717 struct ixgbe_q_vector *q_vector;
718 int i, j, q_vectors, v_idx, r_idx;
719 u32 mask;
9a799d71 720
021230d4 721 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 722
021230d4
AV		 723 /* Populate the IVAR table and set the ITR values to the
724 * corresponding register.
725 */
726 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
727 q_vector = &adapter->q_vector[v_idx];
728 /* XXX for_each_bit(...) */
729 r_idx = find_first_bit(q_vector->rxr_idx,
b4617240 730 adapter->num_rx_queues);
021230d4
AV		 731
732 for (i = 0; i < q_vector->rxr_count; i++) {
733 j = adapter->rx_ring[r_idx].reg_idx;
734 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
735 r_idx = find_next_bit(q_vector->rxr_idx,
b4617240
PW		 736 adapter->num_rx_queues,
737 r_idx + 1);
021230d4
AV		 738 }
739 r_idx = find_first_bit(q_vector->txr_idx,
b4617240 740 adapter->num_tx_queues);
021230d4
AV		 741
742 for (i = 0; i < q_vector->txr_count; i++) {
743 j = adapter->tx_ring[r_idx].reg_idx;
744 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
745 r_idx = find_next_bit(q_vector->txr_idx,
b4617240
PW		 746 adapter->num_tx_queues,
747 r_idx + 1);
021230d4
AV		 748 }
749
30efa5a3 750 /* if this is a tx only vector halve the interrupt rate */
021230d4 751 if (q_vector->txr_count && !q_vector->rxr_count)
30efa5a3 752 q_vector->eitr = (adapter->eitr_param >> 1);
021230d4 753 else
30efa5a3
JB		 754 /* rx only */
755 q_vector->eitr = adapter->eitr_param;
021230d4
AV		 756
757 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
b4617240 758 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
9a799d71
AK		 759 }
760
021230d4
AV		 761 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
762 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
763
41fb9248 764 /* set up to autoclear timer, and the vectors */
021230d4 765 mask = IXGBE_EIMS_ENABLE_MASK;
41fb9248 766 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 767 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 768}
769
f494e8fa
AV		 770enum latency_range {
771 lowest_latency = 0,
772 low_latency = 1,
773 bulk_latency = 2,
774 latency_invalid = 255
775};
776
777/**
778 * ixgbe_update_itr - update the dynamic ITR value based on statistics
779 * @adapter: pointer to adapter
780 * @eitr: eitr setting (ints per sec) to give last timeslice
781 * @itr_setting: current throttle rate in ints/second
782 * @packets: the number of packets during this measurement interval
783 * @bytes: the number of bytes during this measurement interval
784 *
785 * Stores a new ITR value based on packets and byte
786 * counts during the last interrupt. The advantage of per interrupt
787 * computation is faster updates and more accurate ITR for the current
788 * traffic pattern. Constants in this function were computed
789 * based on theoretical maximum wire speed and thresholds were set based
790 * on testing data as well as attempting to minimize response time
791 * while increasing bulk throughput.
792 * this functionality is controlled by the InterruptThrottleRate module
793 * parameter (see ixgbe_param.c)
794 **/
795static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
b4617240
PW		 796 u32 eitr, u8 itr_setting,
797 int packets, int bytes)
f494e8fa
AV		 798{
799 unsigned int retval = itr_setting;
800 u32 timepassed_us;
801 u64 bytes_perint;
802
803 if (packets == 0)
804 goto update_itr_done;
805
806
807 /* simple throttlerate management
808 * 0-20MB/s lowest (100000 ints/s)
809 * 20-100MB/s low (20000 ints/s)
810 * 100-1249MB/s bulk (8000 ints/s)
811 */
812 /* what was last interrupt timeslice? */
813 timepassed_us = 1000000/eitr;
814 bytes_perint = bytes / timepassed_us; /* bytes/usec */
815
816 switch (itr_setting) {
817 case lowest_latency:
818 if (bytes_perint > adapter->eitr_low)
819 retval = low_latency;
820 break;
821 case low_latency:
822 if (bytes_perint > adapter->eitr_high)
823 retval = bulk_latency;
824 else if (bytes_perint <= adapter->eitr_low)
825 retval = lowest_latency;
826 break;
827 case bulk_latency:
828 if (bytes_perint <= adapter->eitr_high)
829 retval = low_latency;
830 break;
831 }
832
833update_itr_done:
834 return retval;
835}
836
837static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
838{
839 struct ixgbe_adapter *adapter = q_vector->adapter;
840 struct ixgbe_hw *hw = &adapter->hw;
841 u32 new_itr;
842 u8 current_itr, ret_itr;
843 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
b4617240 844 sizeof(struct ixgbe_q_vector);
f494e8fa
AV		 845 struct ixgbe_ring *rx_ring, *tx_ring;
846
847 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
848 for (i = 0; i < q_vector->txr_count; i++) {
849 tx_ring = &(adapter->tx_ring[r_idx]);
850 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 851 q_vector->tx_itr,
852 tx_ring->total_packets,
853 tx_ring->total_bytes);
f494e8fa
AV		 854 /* if the result for this queue would decrease interrupt
855 * rate for this vector then use that result */
30efa5a3 856 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
b4617240 857 q_vector->tx_itr - 1 : ret_itr);
f494e8fa 858 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 859 r_idx + 1);
f494e8fa
AV		 860 }
861
862 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
863 for (i = 0; i < q_vector->rxr_count; i++) {
864 rx_ring = &(adapter->rx_ring[r_idx]);
865 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
b4617240
PW		 866 q_vector->rx_itr,
867 rx_ring->total_packets,
868 rx_ring->total_bytes);
f494e8fa
AV		 869 /* if the result for this queue would decrease interrupt
870 * rate for this vector then use that result */
30efa5a3 871 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
b4617240 872 q_vector->rx_itr - 1 : ret_itr);
f494e8fa 873 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
b4617240 874 r_idx + 1);
f494e8fa
AV		 875 }
876
30efa5a3 877 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 878
879 switch (current_itr) {
880 /* counts and packets in update_itr are dependent on these numbers */
881 case lowest_latency:
882 new_itr = 100000;
883 break;
884 case low_latency:
885 new_itr = 20000; /* aka hwitr = ~200 */
886 break;
887 case bulk_latency:
888 default:
889 new_itr = 8000;
890 break;
891 }
892
893 if (new_itr != q_vector->eitr) {
894 u32 itr_reg;
895 /* do an exponential smoothing */
896 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
897 q_vector->eitr = new_itr;
898 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
899 /* must write high and low 16 bits to reset counter */
900 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
b4617240 901 itr_reg);
f494e8fa
AV		 902 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
903 }
904
905 return;
906}
907
0befdb3e
JB		 908static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
909{
910 struct ixgbe_hw *hw = &adapter->hw;
911
912 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
913 (eicr & IXGBE_EICR_GPI_SDP1)) {
914 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
915 /* write to clear the interrupt */
916 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
917 }
918}
cf8280ee
JB		 919
920static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
921{
922 struct ixgbe_hw *hw = &adapter->hw;
923
924 adapter->lsc_int++;
925 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
926 adapter->link_check_timeout = jiffies;
927 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
928 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
929 schedule_work(&adapter->watchdog_task);
930 }
931}
932
9a799d71
AK		 933static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
934{
935 struct net_device *netdev = data;
936 struct ixgbe_adapter *adapter = netdev_priv(netdev);
937 struct ixgbe_hw *hw = &adapter->hw;
938 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
939
cf8280ee
JB		 940 if (eicr & IXGBE_EICR_LSC)
941 ixgbe_check_lsc(adapter);
d4f80882 942
0befdb3e
JB		 943 ixgbe_check_fan_failure(adapter, eicr);
944
d4f80882
AV		 945 if (!test_bit(__IXGBE_DOWN, &adapter->state))
946 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
9a799d71
AK		 947
948 return IRQ_HANDLED;
949}
950
951static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
952{
021230d4
AV		 953 struct ixgbe_q_vector *q_vector = data;
954 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 955 struct ixgbe_ring *tx_ring;
021230d4
AV		 956 int i, r_idx;
957
958 if (!q_vector->txr_count)
959 return IRQ_HANDLED;
960
961 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
962 for (i = 0; i < q_vector->txr_count; i++) {
3a581073 963 tx_ring = &(adapter->tx_ring[r_idx]);
5dd2d332 964#ifdef CONFIG_IXGBE_DCA
bd0362dd 965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 966 ixgbe_update_tx_dca(adapter, tx_ring);
bd0362dd 967#endif
3a581073
JB		 968 tx_ring->total_bytes = 0;
969 tx_ring->total_packets = 0;
970 ixgbe_clean_tx_irq(adapter, tx_ring);
021230d4 971 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
b4617240 972 r_idx + 1);
021230d4 973 }
9a799d71 974
9a799d71
AK		 975 return IRQ_HANDLED;
976}
977
021230d4
AV		 978/**
979 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
980 * @irq: unused
981 * @data: pointer to our q_vector struct for this interrupt vector
982 **/
9a799d71
AK		 983static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
984{
021230d4
AV		 985 struct ixgbe_q_vector *q_vector = data;
986 struct ixgbe_adapter *adapter = q_vector->adapter;
3a581073 987 struct ixgbe_ring *rx_ring;
021230d4 988 int r_idx;
30efa5a3 989 int i;
021230d4
AV		 990
991 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
30efa5a3
JB		 992 for (i = 0; i < q_vector->rxr_count; i++) {
993 rx_ring = &(adapter->rx_ring[r_idx]);
994 rx_ring->total_bytes = 0;
995 rx_ring->total_packets = 0;
996 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
997 r_idx + 1);
998 }
999
021230d4
AV		 1000 if (!q_vector->rxr_count)
1001 return IRQ_HANDLED;
1002
30efa5a3 1003 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1004 rx_ring = &(adapter->rx_ring[r_idx]);
021230d4 1005 /* disable interrupts on this vector only */
3a581073 1006 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
021230d4
AV		 1007 netif_rx_schedule(adapter->netdev, &q_vector->napi);
1008
1009 return IRQ_HANDLED;
1010}
1011
1012static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1013{
1014 ixgbe_msix_clean_rx(irq, data);
1015 ixgbe_msix_clean_tx(irq, data);
9a799d71 1016
9a799d71
AK		 1017 return IRQ_HANDLED;
1018}
1019
021230d4
AV		 1020/**
1021 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1022 * @napi: napi struct with our devices info in it
1023 * @budget: amount of work driver is allowed to do this pass, in packets
1024 *
f0848276
JB		 1025 * This function is optimized for cleaning one queue only on a single
1026 * q_vector!!!
021230d4 1027 **/
9a799d71
AK		 1028static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1029{
021230d4 1030 struct ixgbe_q_vector *q_vector =
b4617240 1031 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 1032 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276 1033 struct ixgbe_ring *rx_ring = NULL;
9a799d71 1034 int work_done = 0;
021230d4 1035 long r_idx;
9a799d71 1036
021230d4 1037 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
3a581073 1038 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1039#ifdef CONFIG_IXGBE_DCA
bd0362dd 1040 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3a581073 1041 ixgbe_update_rx_dca(adapter, rx_ring);
bd0362dd 1042#endif
9a799d71 1043
3a581073 1044 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
9a799d71 1045
021230d4
AV		 1046 /* If all Rx work done, exit the polling mode */
1047 if (work_done < budget) {
1048 netif_rx_complete(adapter->netdev, napi);
30efa5a3 1049 if (adapter->itr_setting & 3)
f494e8fa 1050 ixgbe_set_itr_msix(q_vector);
9a799d71 1051 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3a581073 1052 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
9a799d71
AK		 1053 }
1054
1055 return work_done;
1056}
1057
f0848276
JB		 1058/**
1059 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1060 * @napi: napi struct with our devices info in it
1061 * @budget: amount of work driver is allowed to do this pass, in packets
1062 *
1063 * This function will clean more than one rx queue associated with a
1064 * q_vector.
1065 **/
1066static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1067{
1068 struct ixgbe_q_vector *q_vector =
1069 container_of(napi, struct ixgbe_q_vector, napi);
1070 struct ixgbe_adapter *adapter = q_vector->adapter;
f0848276
JB		 1071 struct ixgbe_ring *rx_ring = NULL;
1072 int work_done = 0, i;
1073 long r_idx;
1074 u16 enable_mask = 0;
1075
1076 /* attempt to distribute budget to each queue fairly, but don't allow
1077 * the budget to go below 1 because we'll exit polling */
1078 budget /= (q_vector->rxr_count ?: 1);
1079 budget = max(budget, 1);
1080 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1081 for (i = 0; i < q_vector->rxr_count; i++) {
1082 rx_ring = &(adapter->rx_ring[r_idx]);
5dd2d332 1083#ifdef CONFIG_IXGBE_DCA
f0848276
JB		 1084 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1085 ixgbe_update_rx_dca(adapter, rx_ring);
1086#endif
1087 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
1088 enable_mask |= rx_ring->v_idx;
1089 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1090 r_idx + 1);
1091 }
1092
1093 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1094 rx_ring = &(adapter->rx_ring[r_idx]);
1095 /* If all Rx work done, exit the polling mode */
7f821875 1096 if (work_done < budget) {
74ce8dd2 1097 netif_rx_complete(adapter->netdev, napi);
f0848276
JB		 1098 if (adapter->itr_setting & 3)
1099 ixgbe_set_itr_msix(q_vector);
1100 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1101 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1102 return 0;
1103 }
1104
1105 return work_done;
1106}
021230d4 1107static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
b4617240 1108 int r_idx)
021230d4
AV		 1109{
1110 a->q_vector[v_idx].adapter = a;
1111 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1112 a->q_vector[v_idx].rxr_count++;
1113 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1114}
1115
1116static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
b4617240 1117 int r_idx)
021230d4
AV		 1118{
1119 a->q_vector[v_idx].adapter = a;
1120 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1121 a->q_vector[v_idx].txr_count++;
1122 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1123}
1124
9a799d71 1125/**
021230d4
AV		 1126 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1127 * @adapter: board private structure to initialize
1128 * @vectors: allotted vector count for descriptor rings
9a799d71 1129 *
021230d4
AV		 1130 * This function maps descriptor rings to the queue-specific vectors
1131 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1132 * one vector per ring/queue, but on a constrained vector budget, we
1133 * group the rings as "efficiently" as possible. You would add new
1134 * mapping configurations in here.
9a799d71 1135 **/
021230d4 1136static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
b4617240 1137 int vectors)
021230d4
AV		 1138{
1139 int v_start = 0;
1140 int rxr_idx = 0, txr_idx = 0;
1141 int rxr_remaining = adapter->num_rx_queues;
1142 int txr_remaining = adapter->num_tx_queues;
1143 int i, j;
1144 int rqpv, tqpv;
1145 int err = 0;
1146
1147 /* No mapping required if MSI-X is disabled. */
1148 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1149 goto out;
9a799d71 1150
021230d4
AV		 1151 /*
1152 * The ideal configuration...
1153 * We have enough vectors to map one per queue.
1154 */
1155 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1156 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1157 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 1158
021230d4
AV		 1159 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1160 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 1161
9a799d71 1162 goto out;
021230d4 1163 }
9a799d71 1164
021230d4
AV		 1165 /*
1166 * If we don't have enough vectors for a 1-to-1
1167 * mapping, we'll have to group them so there are
1168 * multiple queues per vector.
1169 */
1170 /* Re-adjusting *qpv takes care of the remainder. */
1171 for (i = v_start; i < vectors; i++) {
1172 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1173 for (j = 0; j < rqpv; j++) {
1174 map_vector_to_rxq(adapter, i, rxr_idx);
1175 rxr_idx++;
1176 rxr_remaining--;
1177 }
1178 }
1179 for (i = v_start; i < vectors; i++) {
1180 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1181 for (j = 0; j < tqpv; j++) {
1182 map_vector_to_txq(adapter, i, txr_idx);
1183 txr_idx++;
1184 txr_remaining--;
9a799d71 1185 }
9a799d71
AK		 1186 }
1187
021230d4
AV		 1188out:
1189 return err;
1190}
1191
1192/**
1193 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1194 * @adapter: board private structure
1195 *
1196 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1197 * interrupts from the kernel.
1198 **/
1199static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1200{
1201 struct net_device *netdev = adapter->netdev;
1202 irqreturn_t (*handler)(int, void *);
1203 int i, vector, q_vectors, err;
1204
1205 /* Decrement for Other and TCP Timer vectors */
1206 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1207
1208 /* Map the Tx/Rx rings to the vectors we were allotted. */
1209 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1210 if (err)
1211 goto out;
1212
1213#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
b4617240
PW		 1214 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1215 &ixgbe_msix_clean_many)
021230d4
AV		 1216 for (vector = 0; vector < q_vectors; vector++) {
1217 handler = SET_HANDLER(&adapter->q_vector[vector]);
1218 sprintf(adapter->name[vector], "%s:v%d-%s",
b4617240
PW		 1219 netdev->name, vector,
1220 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1221 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
021230d4 1222 err = request_irq(adapter->msix_entries[vector].vector,
b4617240
PW		 1223 handler, 0, adapter->name[vector],
1224 &(adapter->q_vector[vector]));
9a799d71
AK		 1225 if (err) {
1226 DPRINTK(PROBE, ERR,
b4617240
PW		 1227 "request_irq failed for MSIX interrupt "
1228 "Error: %d\n", err);
021230d4 1229 goto free_queue_irqs;
9a799d71 1230 }
9a799d71
AK		 1231 }
1232
021230d4
AV		 1233 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1234 err = request_irq(adapter->msix_entries[vector].vector,
b4617240 1235 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
9a799d71
AK		 1236 if (err) {
1237 DPRINTK(PROBE, ERR,
1238 "request_irq for msix_lsc failed: %d\n", err);
021230d4 1239 goto free_queue_irqs;
9a799d71
AK		 1240 }
1241
9a799d71
AK		 1242 return 0;
1243
021230d4
AV		 1244free_queue_irqs:
1245 for (i = vector - 1; i >= 0; i--)
1246 free_irq(adapter->msix_entries[--vector].vector,
b4617240 1247 &(adapter->q_vector[i]));
021230d4
AV		 1248 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1249 pci_disable_msix(adapter->pdev);
9a799d71
AK		 1250 kfree(adapter->msix_entries);
1251 adapter->msix_entries = NULL;
021230d4 1252out:
9a799d71
AK		 1253 return err;
1254}
1255
f494e8fa
AV		 1256static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1257{
1258 struct ixgbe_hw *hw = &adapter->hw;
1259 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1260 u8 current_itr;
1261 u32 new_itr = q_vector->eitr;
1262 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1263 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1264
30efa5a3 1265 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1266 q_vector->tx_itr,
1267 tx_ring->total_packets,
1268 tx_ring->total_bytes);
30efa5a3 1269 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
b4617240
PW		 1270 q_vector->rx_itr,
1271 rx_ring->total_packets,
1272 rx_ring->total_bytes);
f494e8fa 1273
30efa5a3 1274 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
f494e8fa
AV		 1275
1276 switch (current_itr) {
1277 /* counts and packets in update_itr are dependent on these numbers */
1278 case lowest_latency:
1279 new_itr = 100000;
1280 break;
1281 case low_latency:
1282 new_itr = 20000; /* aka hwitr = ~200 */
1283 break;
1284 case bulk_latency:
1285 new_itr = 8000;
1286 break;
1287 default:
1288 break;
1289 }
1290
1291 if (new_itr != q_vector->eitr) {
1292 u32 itr_reg;
1293 /* do an exponential smoothing */
1294 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1295 q_vector->eitr = new_itr;
1296 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1297 /* must write high and low 16 bits to reset counter */
1298 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1299 }
1300
1301 return;
1302}
1303
79aefa45
AD		 1304/**
1305 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1306 * @adapter: board private structure
1307 **/
1308static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1309{
1310 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1311 IXGBE_WRITE_FLUSH(&adapter->hw);
1312 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1313 int i;
1314 for (i = 0; i < adapter->num_msix_vectors; i++)
1315 synchronize_irq(adapter->msix_entries[i].vector);
1316 } else {
1317 synchronize_irq(adapter->pdev->irq);
1318 }
1319}
1320
1321/**
1322 * ixgbe_irq_enable - Enable default interrupt generation settings
1323 * @adapter: board private structure
1324 **/
1325static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1326{
1327 u32 mask;
1328 mask = IXGBE_EIMS_ENABLE_MASK;
6ab33d51
DM		 1329 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1330 mask |= IXGBE_EIMS_GPI_SDP1;
79aefa45
AD		 1331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1332 IXGBE_WRITE_FLUSH(&adapter->hw);
1333}
021230d4 1334
9a799d71 1335/**
021230d4 1336 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 1337 * @irq: interrupt number
1338 * @data: pointer to a network interface device structure
1339 * @pt_regs: CPU registers structure
1340 **/
1341static irqreturn_t ixgbe_intr(int irq, void *data)
1342{
1343 struct net_device *netdev = data;
1344 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1345 struct ixgbe_hw *hw = &adapter->hw;
1346 u32 eicr;
1347
021230d4
AV		 1348 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1349 * therefore no explict interrupt disable is necessary */
1350 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e
JB		 1351 if (!eicr) {
1352 /* shared interrupt alert!
1353 * make sure interrupts are enabled because the read will
1354 * have disabled interrupts due to EIAM */
1355 ixgbe_irq_enable(adapter);
9a799d71 1356 return IRQ_NONE; /* Not our interrupt */
f47cf66e 1357 }
9a799d71 1358
cf8280ee
JB		 1359 if (eicr & IXGBE_EICR_LSC)
1360 ixgbe_check_lsc(adapter);
021230d4 1361
0befdb3e
JB		 1362 ixgbe_check_fan_failure(adapter, eicr);
1363
021230d4 1364 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
f494e8fa
AV		 1365 adapter->tx_ring[0].total_packets = 0;
1366 adapter->tx_ring[0].total_bytes = 0;
1367 adapter->rx_ring[0].total_packets = 0;
1368 adapter->rx_ring[0].total_bytes = 0;
021230d4
AV		 1369 /* would disable interrupts here but EIAM disabled it */
1370 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
9a799d71
AK		 1371 }
1372
1373 return IRQ_HANDLED;
1374}
1375
021230d4
AV		 1376static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1377{
1378 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1379
1380 for (i = 0; i < q_vectors; i++) {
1381 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1382 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1383 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1384 q_vector->rxr_count = 0;
1385 q_vector->txr_count = 0;
1386 }
1387}
1388
9a799d71
AK		 1389/**
1390 * ixgbe_request_irq - initialize interrupts
1391 * @adapter: board private structure
1392 *
1393 * Attempts to configure interrupts using the best available
1394 * capabilities of the hardware and kernel.
1395 **/
021230d4 1396static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 1397{
1398 struct net_device *netdev = adapter->netdev;
021230d4 1399 int err;
9a799d71 1400
021230d4
AV		 1401 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1402 err = ixgbe_request_msix_irqs(adapter);
1403 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1404 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
b4617240 1405 netdev->name, netdev);
021230d4
AV		 1406 } else {
1407 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
b4617240 1408 netdev->name, netdev);
9a799d71
AK		 1409 }
1410
9a799d71
AK		 1411 if (err)
1412 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1413
9a799d71
AK		 1414 return err;
1415}
1416
1417static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1418{
1419 struct net_device *netdev = adapter->netdev;
1420
1421 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 1422 int i, q_vectors;
9a799d71 1423
021230d4
AV		 1424 q_vectors = adapter->num_msix_vectors;
1425
1426 i = q_vectors - 1;
9a799d71 1427 free_irq(adapter->msix_entries[i].vector, netdev);
9a799d71 1428
021230d4
AV		 1429 i--;
1430 for (; i >= 0; i--) {
1431 free_irq(adapter->msix_entries[i].vector,
b4617240 1432 &(adapter->q_vector[i]));
021230d4
AV		 1433 }
1434
1435 ixgbe_reset_q_vectors(adapter);
1436 } else {
1437 free_irq(adapter->pdev->irq, netdev);
9a799d71
AK		 1438 }
1439}
1440
9a799d71
AK		 1441/**
1442 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1443 *
1444 **/
1445static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1446{
9a799d71
AK		 1447 struct ixgbe_hw *hw = &adapter->hw;
1448
021230d4 1449 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
30efa5a3 1450 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
9a799d71
AK		 1451
1452 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
021230d4
AV		 1453 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1454
1455 map_vector_to_rxq(adapter, 0, 0);
1456 map_vector_to_txq(adapter, 0, 0);
1457
1458 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 1459}
1460
1461/**
3a581073 1462 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 1463 * @adapter: board private structure
1464 *
1465 * Configure the Tx unit of the MAC after a reset.
1466 **/
1467static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1468{
e01c31a5 1469 u64 tdba, tdwba;
9a799d71 1470 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1471 u32 i, j, tdlen, txctrl;
9a799d71
AK		 1472
1473 /* Setup the HW Tx Head and Tail descriptor pointers */
1474 for (i = 0; i < adapter->num_tx_queues; i++) {
e01c31a5
JB		 1475 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1476 j = ring->reg_idx;
1477 tdba = ring->dma;
1478 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
021230d4 1479 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
e01c31a5 1480 (tdba & DMA_32BIT_MASK));
021230d4 1481 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
e01c31a5
JB		 1482 tdwba = ring->dma +
1483 (ring->count * sizeof(union ixgbe_adv_tx_desc));
1484 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1485 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1486 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
021230d4
AV		 1487 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1488 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1489 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1490 adapter->tx_ring[i].head = IXGBE_TDH(j);
1491 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1492 /* Disable Tx Head Writeback RO bit, since this hoses
1493 * bookkeeping if things aren't delivered in order.
1494 */
e01c31a5 1495 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
021230d4 1496 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
e01c31a5 1497 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
9a799d71 1498 }
9a799d71
AK		 1499}
1500
cc41ac7c
JB		 1501#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1502
1503static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1504{
1505 struct ixgbe_ring *rx_ring;
1506 u32 srrctl;
1507 int queue0;
3be1adfb
AD		 1508 unsigned long mask;
1509
1510 /* program one srrctl register per VMDq index */
1511 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1512 long shift, len;
1513 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1514 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1515 shift = find_first_bit(&mask, len);
1516 queue0 = index & mask;
1517 index = (index & mask) >> shift;
1518 /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
cc41ac7c 1519 } else {
3be1adfb
AD		 1520 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1521 queue0 = index & mask;
1522 index = index & mask;
cc41ac7c 1523 }
3be1adfb 1524
cc41ac7c
JB		 1525 rx_ring = &adapter->rx_ring[queue0];
1526
1527 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1528
1529 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1530 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1531
1532 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1533 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1534 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1535 srrctl |= ((IXGBE_RX_HDR_SIZE <<
b4617240
PW		 1536 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1537 IXGBE_SRRCTL_BSIZEHDR_MASK);
cc41ac7c
JB		 1538 } else {
1539 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1540
1541 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1542 srrctl |= IXGBE_RXBUFFER_2048 >>
1543 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1544 else
1545 srrctl |= rx_ring->rx_buf_len >>
1546 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1547 }
1548 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1549}
9a799d71 1550
177db6ff
MC		 1551/**
1552 * ixgbe_get_skb_hdr - helper function for LRO header processing
1553 * @skb: pointer to sk_buff to be added to LRO packet
b4617240 1554 * @iphdr: pointer to ip header structure
177db6ff
MC		 1555 * @tcph: pointer to tcp header structure
1556 * @hdr_flags: pointer to header flags
1557 * @priv: private data
1558 **/
1559static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1560 u64 *hdr_flags, void *priv)
1561{
1562 union ixgbe_adv_rx_desc *rx_desc = priv;
1563
1564 /* Verify that this is a valid IPv4 TCP packet */
e9990a9c
JB		 1565 if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) &&
1566 (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP)))
177db6ff
MC		 1567 return -1;
1568
1569 /* Set network headers */
1570 skb_reset_network_header(skb);
1571 skb_set_transport_header(skb, ip_hdrlen(skb));
1572 *iphdr = ip_hdr(skb);
1573 *tcph = tcp_hdr(skb);
1574 *hdr_flags = LRO_IPV4 | LRO_TCP;
1575 return 0;
1576}
1577
cc41ac7c 1578#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
b4617240 1579 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
cc41ac7c 1580
9a799d71 1581/**
3a581073 1582 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
9a799d71
AK		 1583 * @adapter: board private structure
1584 *
1585 * Configure the Rx unit of the MAC after a reset.
1586 **/
1587static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1588{
1589 u64 rdba;
1590 struct ixgbe_hw *hw = &adapter->hw;
1591 struct net_device *netdev = adapter->netdev;
1592 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 1593 int i, j;
9a799d71 1594 u32 rdlen, rxctrl, rxcsum;
7c6e0a43
JB		 1595 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1596 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1597 0x6A3E67EA, 0x14364D17, 0x3BED200D};
9a799d71 1598 u32 fctrl, hlreg0;
9a799d71 1599 u32 pages;
cc41ac7c
JB		 1600 u32 reta = 0, mrqc;
1601 u32 rdrxctl;
7c6e0a43 1602 int rx_buf_len;
9a799d71
AK		 1603
1604 /* Decide whether to use packet split mode or not */
762f4c57 1605 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 1606
1607 /* Set the RX buffer length according to the mode */
1608 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 1609 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71
AK		 1610 } else {
1611 if (netdev->mtu <= ETH_DATA_LEN)
7c6e0a43 1612 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 1613 else
7c6e0a43 1614 rx_buf_len = ALIGN(max_frame, 1024);
9a799d71
AK		 1615 }
1616
1617 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1618 fctrl |= IXGBE_FCTRL_BAM;
021230d4 1619 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
9a799d71
AK		 1620 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1621
1622 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1623 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1624 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1625 else
1626 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1627 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1628
1629 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1630
9a799d71
AK		 1631 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1632 /* disable receives while setting up the descriptors */
1633 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1634 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1635
1636 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1637 * the Base and Length of the Rx Descriptor Ring */
1638 for (i = 0; i < adapter->num_rx_queues; i++) {
1639 rdba = adapter->rx_ring[i].dma;
7c6e0a43
JB		 1640 j = adapter->rx_ring[i].reg_idx;
1641 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1642 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1643 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1644 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1645 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1646 adapter->rx_ring[i].head = IXGBE_RDH(j);
1647 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1648 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
e9990a9c
JB		 1649 /* Intitial LRO Settings */
1650 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1651 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1652 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1653 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1654 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1655 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1656 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1657 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1658 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
cc41ac7c
JB		 1659
1660 ixgbe_configure_srrctl(adapter, j);
9a799d71
AK		 1661 }
1662
cc41ac7c
JB		 1663 /*
1664 * For VMDq support of different descriptor types or
1665 * buffer sizes through the use of multiple SRRCTL
1666 * registers, RDRXCTL.MVMEN must be set to 1
1667 *
1668 * also, the manual doesn't mention it clearly but DCA hints
1669 * will only use queue 0's tags unless this bit is set. Side
1670 * effects of setting this bit are only that SRRCTL must be
1671 * fully programmed [0..15]
1672 */
2f90b865
AD		 1673 if (adapter->flags &
1674 (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED)) {
1675 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1676 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1677 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1678 }
177db6ff 1679
021230d4 1680 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
9a799d71 1681 /* Fill out redirection table */
021230d4
AV		 1682 for (i = 0, j = 0; i < 128; i++, j++) {
1683 if (j == adapter->ring_feature[RING_F_RSS].indices)
1684 j = 0;
1685 /* reta = 4-byte sliding window of
1686 * 0x00..(indices-1)(indices-1)00..etc. */
1687 reta = (reta << 8) | (j * 0x11);
1688 if ((i & 3) == 3)
1689 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
9a799d71
AK		 1690 }
1691
1692 /* Fill out hash function seeds */
1693 for (i = 0; i < 10; i++)
7c6e0a43 1694 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
9a799d71
AK		 1695
1696 mrqc = IXGBE_MRQC_RSSEN
1697 /* Perform hash on these packet types */
7c6e0a43
JB		 1698 | IXGBE_MRQC_RSS_FIELD_IPV4
1699 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1700 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1701 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1702 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1703 | IXGBE_MRQC_RSS_FIELD_IPV6
1704 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1705 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1706 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
9a799d71 1707 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
021230d4 1708 }
9a799d71 1709
021230d4
AV		 1710 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1711
1712 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1713 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1714 /* Disable indicating checksum in descriptor, enables
1715 * RSS hash */
9a799d71 1716 rxcsum |= IXGBE_RXCSUM_PCSD;
9a799d71 1717 }
021230d4
AV		 1718 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1719 /* Enable IPv4 payload checksum for UDP fragments
1720 * if PCSD is not set */
1721 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1722 }
1723
1724 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
9a799d71
AK		 1725}
1726
1727static void ixgbe_vlan_rx_register(struct net_device *netdev,
b4617240 1728 struct vlan_group *grp)
9a799d71
AK		 1729{
1730 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1731 u32 ctrl;
1732
d4f80882
AV		 1733 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1734 ixgbe_irq_disable(adapter);
9a799d71
AK		 1735 adapter->vlgrp = grp;
1736
2f90b865
AD		 1737 /*
1738 * For a DCB driver, always enable VLAN tag stripping so we can
1739 * still receive traffic from a DCB-enabled host even if we're
1740 * not in DCB mode.
1741 */
1742 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1743 ctrl |= IXGBE_VLNCTRL_VME;
1744 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1745 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1746
9a799d71
AK		 1747 if (grp) {
1748 /* enable VLAN tag insert/strip */
1749 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
746b9f02 1750 ctrl |= IXGBE_VLNCTRL_VME;
9a799d71
AK		 1751 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1752 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1753 }
1754
d4f80882
AV		 1755 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1756 ixgbe_irq_enable(adapter);
9a799d71
AK		 1757}
1758
1759static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1760{
1761 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1762 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 1763
1764 /* add VID to filter table */
c44ade9e 1765 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
9a799d71
AK		 1766}
1767
1768static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1769{
1770 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1771 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 1772
d4f80882
AV		 1773 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1774 ixgbe_irq_disable(adapter);
1775
9a799d71 1776 vlan_group_set_device(adapter->vlgrp, vid, NULL);
d4f80882
AV		 1777
1778 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1779 ixgbe_irq_enable(adapter);
9a799d71
AK		 1780
1781 /* remove VID from filter table */
c44ade9e 1782 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
9a799d71
AK		 1783}
1784
1785static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1786{
1787 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1788
1789 if (adapter->vlgrp) {
1790 u16 vid;
1791 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1792 if (!vlan_group_get_device(adapter->vlgrp, vid))
1793 continue;
1794 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1795 }
1796 }
1797}
1798
2c5645cf
CL		 1799static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1800{
1801 struct dev_mc_list *mc_ptr;
1802 u8 *addr = *mc_addr_ptr;
1803 *vmdq = 0;
1804
1805 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1806 if (mc_ptr->next)
1807 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1808 else
1809 *mc_addr_ptr = NULL;
1810
1811 return addr;
1812}
1813
9a799d71 1814/**
2c5645cf 1815 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 1816 * @netdev: network interface device structure
1817 *
2c5645cf
CL		 1818 * The set_rx_method entry point is called whenever the unicast/multicast
1819 * address list or the network interface flags are updated. This routine is
1820 * responsible for configuring the hardware for proper unicast, multicast and
1821 * promiscuous mode.
9a799d71 1822 **/
2c5645cf 1823static void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 1824{
1825 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1826 struct ixgbe_hw *hw = &adapter->hw;
3d01625a 1827 u32 fctrl, vlnctrl;
2c5645cf
CL		 1828 u8 *addr_list = NULL;
1829 int addr_count = 0;
9a799d71
AK		 1830
1831 /* Check for Promiscuous and All Multicast modes */
1832
1833 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3d01625a 1834 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71
AK		 1835
1836 if (netdev->flags & IFF_PROMISC) {
2c5645cf 1837 hw->addr_ctrl.user_set_promisc = 1;
9a799d71 1838 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3d01625a 1839 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
9a799d71 1840 } else {
746b9f02
PM		 1841 if (netdev->flags & IFF_ALLMULTI) {
1842 fctrl |= IXGBE_FCTRL_MPE;
1843 fctrl &= ~IXGBE_FCTRL_UPE;
1844 } else {
1845 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1846 }
3d01625a 1847 vlnctrl |= IXGBE_VLNCTRL_VFE;
2c5645cf 1848 hw->addr_ctrl.user_set_promisc = 0;
9a799d71
AK		 1849 }
1850
1851 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3d01625a 1852 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
9a799d71 1853
2c5645cf
CL		 1854 /* reprogram secondary unicast list */
1855 addr_count = netdev->uc_count;
1856 if (addr_count)
1857 addr_list = netdev->uc_list->dmi_addr;
c44ade9e
JB		 1858 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1859 ixgbe_addr_list_itr);
9a799d71 1860
2c5645cf
CL		 1861 /* reprogram multicast list */
1862 addr_count = netdev->mc_count;
1863 if (addr_count)
1864 addr_list = netdev->mc_list->dmi_addr;
c44ade9e
JB		 1865 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1866 ixgbe_addr_list_itr);
9a799d71
AK		 1867}
1868
021230d4
AV		 1869static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1870{
1871 int q_idx;
1872 struct ixgbe_q_vector *q_vector;
1873 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1874
1875 /* legacy and MSI only use one vector */
1876 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1877 q_vectors = 1;
1878
1879 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 1880 struct napi_struct *napi;
021230d4
AV		 1881 q_vector = &adapter->q_vector[q_idx];
1882 if (!q_vector->rxr_count)
1883 continue;
f0848276
JB		 1884 napi = &q_vector->napi;
1885 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1886 (q_vector->rxr_count > 1))
1887 napi->poll = &ixgbe_clean_rxonly_many;
1888
1889 napi_enable(napi);
021230d4
AV		 1890 }
1891}
1892
1893static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1894{
1895 int q_idx;
1896 struct ixgbe_q_vector *q_vector;
1897 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1898
1899 /* legacy and MSI only use one vector */
1900 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1901 q_vectors = 1;
1902
1903 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1904 q_vector = &adapter->q_vector[q_idx];
1905 if (!q_vector->rxr_count)
1906 continue;
1907 napi_disable(&q_vector->napi);
1908 }
1909}
1910
2f90b865
AD		 1911#ifdef CONFIG_IXGBE_DCBNL
1912/*
1913 * ixgbe_configure_dcb - Configure DCB hardware
1914 * @adapter: ixgbe adapter struct
1915 *
1916 * This is called by the driver on open to configure the DCB hardware.
1917 * This is also called by the gennetlink interface when reconfiguring
1918 * the DCB state.
1919 */
1920static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
1921{
1922 struct ixgbe_hw *hw = &adapter->hw;
1923 u32 txdctl, vlnctrl;
1924 int i, j;
1925
1926 ixgbe_dcb_check_config(&adapter->dcb_cfg);
1927 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
1928 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
1929
1930 /* reconfigure the hardware */
1931 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
1932
1933 for (i = 0; i < adapter->num_tx_queues; i++) {
1934 j = adapter->tx_ring[i].reg_idx;
1935 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
1936 /* PThresh workaround for Tx hang with DFP enabled. */
1937 txdctl |= 32;
1938 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1939 }
1940 /* Enable VLAN tag insert/strip */
1941 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1942 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1943 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1944 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1945 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
1946}
1947
1948#endif
9a799d71
AK		 1949static void ixgbe_configure(struct ixgbe_adapter *adapter)
1950{
1951 struct net_device *netdev = adapter->netdev;
1952 int i;
1953
2c5645cf 1954 ixgbe_set_rx_mode(netdev);
9a799d71
AK		 1955
1956 ixgbe_restore_vlan(adapter);
2f90b865
AD		 1957#ifdef CONFIG_IXGBE_DCBNL
1958 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1959 netif_set_gso_max_size(netdev, 32768);
1960 ixgbe_configure_dcb(adapter);
1961 } else {
1962 netif_set_gso_max_size(netdev, 65536);
1963 }
1964#else
1965 netif_set_gso_max_size(netdev, 65536);
1966#endif
9a799d71
AK		 1967
1968 ixgbe_configure_tx(adapter);
1969 ixgbe_configure_rx(adapter);
1970 for (i = 0; i < adapter->num_rx_queues; i++)
1971 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
b4617240 1972 (adapter->rx_ring[i].count - 1));
9a799d71
AK		 1973}
1974
1975static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1976{
1977 struct net_device *netdev = adapter->netdev;
9a799d71 1978 struct ixgbe_hw *hw = &adapter->hw;
021230d4 1979 int i, j = 0;
9a799d71 1980 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4
AV		 1981 u32 txdctl, rxdctl, mhadd;
1982 u32 gpie;
9a799d71 1983
5eba3699
AV		 1984 ixgbe_get_hw_control(adapter);
1985
021230d4
AV		 1986 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1987 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
9a799d71
AK		 1988 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1989 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
b4617240 1990 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
9a799d71
AK		 1991 } else {
1992 /* MSI only */
021230d4 1993 gpie = 0;
9a799d71 1994 }
021230d4
AV		 1995 /* XXX: to interrupt immediately for EICS writes, enable this */
1996 /* gpie |= IXGBE_GPIE_EIMEN; */
1997 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
9a799d71
AK		 1998 }
1999
021230d4
AV		 2000 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2001 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2002 * specifically only auto mask tx and rx interrupts */
2003 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2004 }
9a799d71 2005
0befdb3e
JB		 2006 /* Enable fan failure interrupt if media type is copper */
2007 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2008 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2009 gpie |= IXGBE_SDP1_GPIEN;
2010 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2011 }
2012
021230d4 2013 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
9a799d71
AK		 2014 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2015 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2016 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2017
2018 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2019 }
2020
2021 for (i = 0; i < adapter->num_tx_queues; i++) {
021230d4
AV		 2022 j = adapter->tx_ring[i].reg_idx;
2023 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
e01c31a5
JB		 2024 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2025 txdctl |= (8 << 16);
9a799d71 2026 txdctl |= IXGBE_TXDCTL_ENABLE;
021230d4 2027 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
9a799d71
AK		 2028 }
2029
2030 for (i = 0; i < adapter->num_rx_queues; i++) {
021230d4
AV		 2031 j = adapter->rx_ring[i].reg_idx;
2032 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2033 /* enable PTHRESH=32 descriptors (half the internal cache)
2034 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2035 * this also removes a pesky rx_no_buffer_count increment */
2036 rxdctl |= 0x0020;
9a799d71 2037 rxdctl |= IXGBE_RXDCTL_ENABLE;
021230d4 2038 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
9a799d71
AK		 2039 }
2040 /* enable all receives */
2041 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2042 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2043 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
2044
2045 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2046 ixgbe_configure_msix(adapter);
2047 else
2048 ixgbe_configure_msi_and_legacy(adapter);
2049
2050 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 2051 ixgbe_napi_enable_all(adapter);
2052
2053 /* clear any pending interrupts, may auto mask */
2054 IXGBE_READ_REG(hw, IXGBE_EICR);
2055
9a799d71
AK		 2056 ixgbe_irq_enable(adapter);
2057
2058 /* bring the link up in the watchdog, this could race with our first
2059 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 2060 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2061 adapter->link_check_timeout = jiffies;
9a799d71
AK		 2062 mod_timer(&adapter->watchdog_timer, jiffies);
2063 return 0;
2064}
2065
d4f80882
AV		 2066void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2067{
2068 WARN_ON(in_interrupt());
2069 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2070 msleep(1);
2071 ixgbe_down(adapter);
2072 ixgbe_up(adapter);
2073 clear_bit(__IXGBE_RESETTING, &adapter->state);
2074}
2075
9a799d71
AK		 2076int ixgbe_up(struct ixgbe_adapter *adapter)
2077{
2078 /* hardware has been reset, we need to reload some things */
2079 ixgbe_configure(adapter);
2080
2081 return ixgbe_up_complete(adapter);
2082}
2083
2084void ixgbe_reset(struct ixgbe_adapter *adapter)
2085{
c44ade9e
JB		 2086 struct ixgbe_hw *hw = &adapter->hw;
2087 if (hw->mac.ops.init_hw(hw))
2088 dev_err(&adapter->pdev->dev, "Hardware Error\n");
9a799d71
AK		 2089
2090 /* reprogram the RAR[0] in case user changed it. */
c44ade9e 2091 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 2092
2093}
2094
9a799d71
AK		 2095/**
2096 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2097 * @adapter: board private structure
2098 * @rx_ring: ring to free buffers from
2099 **/
2100static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
b4617240 2101 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2102{
2103 struct pci_dev *pdev = adapter->pdev;
2104 unsigned long size;
2105 unsigned int i;
2106
2107 /* Free all the Rx ring sk_buffs */
2108
2109 for (i = 0; i < rx_ring->count; i++) {
2110 struct ixgbe_rx_buffer *rx_buffer_info;
2111
2112 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2113 if (rx_buffer_info->dma) {
2114 pci_unmap_single(pdev, rx_buffer_info->dma,
b4617240
PW		 2115 rx_ring->rx_buf_len,
2116 PCI_DMA_FROMDEVICE);
9a799d71
AK		 2117 rx_buffer_info->dma = 0;
2118 }
2119 if (rx_buffer_info->skb) {
2120 dev_kfree_skb(rx_buffer_info->skb);
2121 rx_buffer_info->skb = NULL;
2122 }
2123 if (!rx_buffer_info->page)
2124 continue;
762f4c57
JB		 2125 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2126 PCI_DMA_FROMDEVICE);
9a799d71 2127 rx_buffer_info->page_dma = 0;
9a799d71
AK		 2128 put_page(rx_buffer_info->page);
2129 rx_buffer_info->page = NULL;
762f4c57 2130 rx_buffer_info->page_offset = 0;
9a799d71
AK		 2131 }
2132
2133 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2134 memset(rx_ring->rx_buffer_info, 0, size);
2135
2136 /* Zero out the descriptor ring */
2137 memset(rx_ring->desc, 0, rx_ring->size);
2138
2139 rx_ring->next_to_clean = 0;
2140 rx_ring->next_to_use = 0;
2141
2142 writel(0, adapter->hw.hw_addr + rx_ring->head);
2143 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2144}
2145
2146/**
2147 * ixgbe_clean_tx_ring - Free Tx Buffers
2148 * @adapter: board private structure
2149 * @tx_ring: ring to be cleaned
2150 **/
2151static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
b4617240 2152 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2153{
2154 struct ixgbe_tx_buffer *tx_buffer_info;
2155 unsigned long size;
2156 unsigned int i;
2157
2158 /* Free all the Tx ring sk_buffs */
2159
2160 for (i = 0; i < tx_ring->count; i++) {
2161 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2162 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2163 }
2164
2165 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2166 memset(tx_ring->tx_buffer_info, 0, size);
2167
2168 /* Zero out the descriptor ring */
2169 memset(tx_ring->desc, 0, tx_ring->size);
2170
2171 tx_ring->next_to_use = 0;
2172 tx_ring->next_to_clean = 0;
2173
2174 writel(0, adapter->hw.hw_addr + tx_ring->head);
2175 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2176}
2177
2178/**
021230d4 2179 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 2180 * @adapter: board private structure
2181 **/
021230d4 2182static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2183{
2184 int i;
2185
021230d4
AV		 2186 for (i = 0; i < adapter->num_rx_queues; i++)
2187 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
9a799d71
AK		 2188}
2189
2190/**
021230d4 2191 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 2192 * @adapter: board private structure
2193 **/
021230d4 2194static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 2195{
2196 int i;
2197
021230d4
AV		 2198 for (i = 0; i < adapter->num_tx_queues; i++)
2199 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
9a799d71
AK		 2200}
2201
2202void ixgbe_down(struct ixgbe_adapter *adapter)
2203{
2204 struct net_device *netdev = adapter->netdev;
7f821875 2205 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2206 u32 rxctrl;
7f821875
JB		 2207 u32 txdctl;
2208 int i, j;
9a799d71
AK		 2209
2210 /* signal that we are down to the interrupt handler */
2211 set_bit(__IXGBE_DOWN, &adapter->state);
2212
2213 /* disable receives */
7f821875
JB		 2214 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2215 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71
AK		 2216
2217 netif_tx_disable(netdev);
2218
7f821875 2219 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 2220 msleep(10);
2221
7f821875
JB		 2222 netif_tx_stop_all_queues(netdev);
2223
9a799d71
AK		 2224 ixgbe_irq_disable(adapter);
2225
021230d4 2226 ixgbe_napi_disable_all(adapter);
7f821875 2227
9a799d71 2228 del_timer_sync(&adapter->watchdog_timer);
cf8280ee 2229 cancel_work_sync(&adapter->watchdog_task);
9a799d71 2230
7f821875
JB		 2231 /* disable transmits in the hardware now that interrupts are off */
2232 for (i = 0; i < adapter->num_tx_queues; i++) {
2233 j = adapter->tx_ring[i].reg_idx;
2234 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2235 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2236 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2237 }
2238
9a799d71 2239 netif_carrier_off(netdev);
9a799d71 2240
5dd2d332 2241#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2242 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2243 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2244 dca_remove_requester(&adapter->pdev->dev);
2245 }
2246
2247#endif
6f4a0e45
PL		 2248 if (!pci_channel_offline(adapter->pdev))
2249 ixgbe_reset(adapter);
9a799d71
AK		 2250 ixgbe_clean_all_tx_rings(adapter);
2251 ixgbe_clean_all_rx_rings(adapter);
2252
5dd2d332 2253#ifdef CONFIG_IXGBE_DCA
96b0e0f6
JB		 2254 /* since we reset the hardware DCA settings were cleared */
2255 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2256 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2257 /* always use CB2 mode, difference is masked
2258 * in the CB driver */
b4617240 2259 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
96b0e0f6
JB		 2260 ixgbe_setup_dca(adapter);
2261 }
2262#endif
9a799d71
AK		 2263}
2264
9a799d71 2265/**
021230d4
AV		 2266 * ixgbe_poll - NAPI Rx polling callback
2267 * @napi: structure for representing this polling device
2268 * @budget: how many packets driver is allowed to clean
2269 *
2270 * This function is used for legacy and MSI, NAPI mode
9a799d71 2271 **/
021230d4 2272static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 2273{
021230d4 2274 struct ixgbe_q_vector *q_vector = container_of(napi,
b4617240 2275 struct ixgbe_q_vector, napi);
021230d4 2276 struct ixgbe_adapter *adapter = q_vector->adapter;
74ce8dd2 2277 int tx_cleaned, work_done = 0;
9a799d71 2278
5dd2d332 2279#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 2280 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2281 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2282 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2283 }
2284#endif
2285
d2c7ddd6 2286 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
021230d4 2287 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
9a799d71 2288
d2c7ddd6
DM		 2289 if (tx_cleaned)
2290 work_done = budget;
2291
53e52c72
DM		 2292 /* If budget not fully consumed, exit the polling mode */
2293 if (work_done < budget) {
021230d4 2294 netif_rx_complete(adapter->netdev, napi);
30efa5a3 2295 if (adapter->itr_setting & 3)
f494e8fa 2296 ixgbe_set_itr(adapter);
d4f80882
AV		 2297 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2298 ixgbe_irq_enable(adapter);
9a799d71 2299 }
9a799d71
AK		 2300 return work_done;
2301}
2302
2303/**
2304 * ixgbe_tx_timeout - Respond to a Tx Hang
2305 * @netdev: network interface device structure
2306 **/
2307static void ixgbe_tx_timeout(struct net_device *netdev)
2308{
2309 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2310
2311 /* Do the reset outside of interrupt context */
2312 schedule_work(&adapter->reset_task);
2313}
2314
2315static void ixgbe_reset_task(struct work_struct *work)
2316{
2317 struct ixgbe_adapter *adapter;
2318 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2319
2f90b865
AD		 2320 /* If we're already down or resetting, just bail */
2321 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
2322 test_bit(__IXGBE_RESETTING, &adapter->state))
2323 return;
2324
9a799d71
AK		 2325 adapter->tx_timeout_count++;
2326
d4f80882 2327 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2328}
2329
b9804972
JB		 2330static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2331{
2332 int nrq = 1, ntq = 1;
2333 int feature_mask = 0, rss_i, rss_m;
2f90b865 2334 int dcb_i, dcb_m;
b9804972
JB		 2335
2336 /* Number of supported queues */
2337 switch (adapter->hw.mac.type) {
2338 case ixgbe_mac_82598EB:
2f90b865
AD		 2339 dcb_i = adapter->ring_feature[RING_F_DCB].indices;
2340 dcb_m = 0;
b9804972
JB		 2341 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2342 rss_m = 0;
2343 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2f90b865 2344 feature_mask |= IXGBE_FLAG_DCB_ENABLED;
b9804972
JB		 2345
2346 switch (adapter->flags & feature_mask) {
2f90b865
AD		 2347 case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_DCB_ENABLED):
2348 dcb_m = 0x7 << 3;
2349 rss_i = min(8, rss_i);
2350 rss_m = 0x7;
2351 nrq = dcb_i * rss_i;
2352 ntq = min(MAX_TX_QUEUES, dcb_i * rss_i);
2353 break;
2354 case (IXGBE_FLAG_DCB_ENABLED):
2355 dcb_m = 0x7 << 3;
2356 nrq = dcb_i;
2357 ntq = dcb_i;
2358 break;
b9804972
JB		 2359 case (IXGBE_FLAG_RSS_ENABLED):
2360 rss_m = 0xF;
2361 nrq = rss_i;
2362 ntq = rss_i;
2363 break;
2364 case 0:
2365 default:
2f90b865
AD		 2366 dcb_i = 0;
2367 dcb_m = 0;
b9804972
JB		 2368 rss_i = 0;
2369 rss_m = 0;
2370 nrq = 1;
2371 ntq = 1;
2372 break;
2373 }
2374
2f90b865
AD		 2375 /* Sanity check, we should never have zero queues */
2376 nrq = (nrq ?:1);
2377 ntq = (ntq ?:1);
2378
2379 adapter->ring_feature[RING_F_DCB].indices = dcb_i;
2380 adapter->ring_feature[RING_F_DCB].mask = dcb_m;
b9804972
JB		 2381 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2382 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2383 break;
2384 default:
2385 nrq = 1;
2386 ntq = 1;
2387 break;
2388 }
2389
2390 adapter->num_rx_queues = nrq;
2391 adapter->num_tx_queues = ntq;
2392}
2393
021230d4 2394static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
b4617240 2395 int vectors)
021230d4
AV		 2396{
2397 int err, vector_threshold;
2398
2399 /* We'll want at least 3 (vector_threshold):
2400 * 1) TxQ[0] Cleanup
2401 * 2) RxQ[0] Cleanup
2402 * 3) Other (Link Status Change, etc.)
2403 * 4) TCP Timer (optional)
2404 */
2405 vector_threshold = MIN_MSIX_COUNT;
2406
2407 /* The more we get, the more we will assign to Tx/Rx Cleanup
2408 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2409 * Right now, we simply care about how many we'll get; we'll
2410 * set them up later while requesting irq's.
2411 */
2412 while (vectors >= vector_threshold) {
2413 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
b4617240 2414 vectors);
021230d4
AV		 2415 if (!err) /* Success in acquiring all requested vectors. */
2416 break;
2417 else if (err < 0)
2418 vectors = 0; /* Nasty failure, quit now */
2419 else /* err == number of vectors we should try again with */
2420 vectors = err;
2421 }
2422
2423 if (vectors < vector_threshold) {
2424 /* Can't allocate enough MSI-X interrupts? Oh well.
2425 * This just means we'll go with either a single MSI
2426 * vector or fall back to legacy interrupts.
2427 */
2428 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2429 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2430 kfree(adapter->msix_entries);
2431 adapter->msix_entries = NULL;
2f90b865 2432 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4 2433 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
b9804972 2434 ixgbe_set_num_queues(adapter);
021230d4
AV		 2435 } else {
2436 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2437 adapter->num_msix_vectors = vectors;
2438 }
2439}
2440
021230d4
AV		 2441/**
2442 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2443 * @adapter: board private structure to initialize
2444 *
2445 * Once we know the feature-set enabled for the device, we'll cache
2446 * the register offset the descriptor ring is assigned to.
2447 **/
2448static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2449{
021230d4
AV		 2450 int feature_mask = 0, rss_i;
2451 int i, txr_idx, rxr_idx;
2f90b865 2452 int dcb_i;
021230d4
AV		 2453
2454 /* Number of supported queues */
2455 switch (adapter->hw.mac.type) {
2456 case ixgbe_mac_82598EB:
2f90b865 2457 dcb_i = adapter->ring_feature[RING_F_DCB].indices;
021230d4
AV		 2458 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2459 txr_idx = 0;
2460 rxr_idx = 0;
2f90b865 2461 feature_mask |= IXGBE_FLAG_DCB_ENABLED;
021230d4
AV		 2462 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2463 switch (adapter->flags & feature_mask) {
2f90b865
AD		 2464 case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_DCB_ENABLED):
2465 for (i = 0; i < dcb_i; i++) {
2466 int j;
2467 /* Rx first */
2468 for (j = 0; j < adapter->num_rx_queues; j++) {
2469 adapter->rx_ring[rxr_idx].reg_idx =
2470 i << 3 | j;
2471 rxr_idx++;
2472 }
2473 /* Tx now */
2474 for (j = 0; j < adapter->num_tx_queues; j++) {
2475 adapter->tx_ring[txr_idx].reg_idx =
2476 i << 2 | (j >> 1);
2477 if (j & 1)
2478 txr_idx++;
2479 }
2480 }
2481 case (IXGBE_FLAG_DCB_ENABLED):
2482 /* the number of queues is assumed to be symmetric */
2483 for (i = 0; i < dcb_i; i++) {
2484 adapter->rx_ring[i].reg_idx = i << 3;
2485 adapter->tx_ring[i].reg_idx = i << 2;
2486 }
2487 break;
021230d4
AV		 2488 case (IXGBE_FLAG_RSS_ENABLED):
2489 for (i = 0; i < adapter->num_rx_queues; i++)
2490 adapter->rx_ring[i].reg_idx = i;
2491 for (i = 0; i < adapter->num_tx_queues; i++)
2492 adapter->tx_ring[i].reg_idx = i;
2493 break;
2494 case 0:
2495 default:
2496 break;
2497 }
2498 break;
2499 default:
2500 break;
2501 }
2502}
2503
9a799d71
AK		 2504/**
2505 * ixgbe_alloc_queues - Allocate memory for all rings
2506 * @adapter: board private structure to initialize
2507 *
2508 * We allocate one ring per queue at run-time since we don't know the
2509 * number of queues at compile-time. The polling_netdev array is
2510 * intended for Multiqueue, but should work fine with a single queue.
2511 **/
2f90b865 2512static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71
AK		 2513{
2514 int i;
2515
2516 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
b4617240 2517 sizeof(struct ixgbe_ring), GFP_KERNEL);
9a799d71 2518 if (!adapter->tx_ring)
021230d4 2519 goto err_tx_ring_allocation;
9a799d71
AK		 2520
2521 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
b4617240 2522 sizeof(struct ixgbe_ring), GFP_KERNEL);
021230d4
AV		 2523 if (!adapter->rx_ring)
2524 goto err_rx_ring_allocation;
9a799d71 2525
021230d4 2526 for (i = 0; i < adapter->num_tx_queues; i++) {
b9804972 2527 adapter->tx_ring[i].count = adapter->tx_ring_count;
021230d4
AV		 2528 adapter->tx_ring[i].queue_index = i;
2529 }
b9804972 2530
9a799d71 2531 for (i = 0; i < adapter->num_rx_queues; i++) {
b9804972 2532 adapter->rx_ring[i].count = adapter->rx_ring_count;
021230d4
AV		 2533 adapter->rx_ring[i].queue_index = i;
2534 }
2535
2536 ixgbe_cache_ring_register(adapter);
2537
2538 return 0;
2539
2540err_rx_ring_allocation:
2541 kfree(adapter->tx_ring);
2542err_tx_ring_allocation:
2543 return -ENOMEM;
2544}
2545
2546/**
2547 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2548 * @adapter: board private structure to initialize
2549 *
2550 * Attempt to configure the interrupts using the best available
2551 * capabilities of the hardware and the kernel.
2552 **/
2553static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
b4617240 2554 *adapter)
021230d4
AV		 2555{
2556 int err = 0;
2557 int vector, v_budget;
2558
2559 /*
2560 * It's easy to be greedy for MSI-X vectors, but it really
2561 * doesn't do us much good if we have a lot more vectors
2562 * than CPU's. So let's be conservative and only ask for
2563 * (roughly) twice the number of vectors as there are CPU's.
2564 */
2565 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
b4617240 2566 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
021230d4
AV		 2567
2568 /*
2569 * At the same time, hardware can only support a maximum of
2570 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2571 * we can easily reach upwards of 64 Rx descriptor queues and
2572 * 32 Tx queues. Thus, we cap it off in those rare cases where
2573 * the cpu count also exceeds our vector limit.
2574 */
2575 v_budget = min(v_budget, MAX_MSIX_COUNT);
2576
2577 /* A failure in MSI-X entry allocation isn't fatal, but it does
2578 * mean we disable MSI-X capabilities of the adapter. */
2579 adapter->msix_entries = kcalloc(v_budget,
b4617240 2580 sizeof(struct msix_entry), GFP_KERNEL);
021230d4 2581 if (!adapter->msix_entries) {
2f90b865 2582 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
021230d4
AV		 2583 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2584 ixgbe_set_num_queues(adapter);
2585 kfree(adapter->tx_ring);
2586 kfree(adapter->rx_ring);
2587 err = ixgbe_alloc_queues(adapter);
2588 if (err) {
2589 DPRINTK(PROBE, ERR, "Unable to allocate memory "
b4617240 2590 "for queues\n");
021230d4
AV		 2591 goto out;
2592 }
2593
2594 goto try_msi;
2595 }
2596
2597 for (vector = 0; vector < v_budget; vector++)
2598 adapter->msix_entries[vector].entry = vector;
2599
2600 ixgbe_acquire_msix_vectors(adapter, v_budget);
2601
2602 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2603 goto out;
2604
2605try_msi:
2606 err = pci_enable_msi(adapter->pdev);
2607 if (!err) {
2608 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2609 } else {
2610 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
b4617240 2611 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 2612 /* reset err */
2613 err = 0;
2614 }
2615
2616out:
30eba97a 2617 /* Notify the stack of the (possibly) reduced Tx Queue count. */
fd2ea0a7 2618 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
021230d4
AV		 2619
2620 return err;
2621}
2622
2f90b865 2623void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 2624{
2625 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2626 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2627 pci_disable_msix(adapter->pdev);
2628 kfree(adapter->msix_entries);
2629 adapter->msix_entries = NULL;
2630 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2631 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2632 pci_disable_msi(adapter->pdev);
2633 }
2634 return;
2635}
2636
2637/**
2638 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2639 * @adapter: board private structure to initialize
2640 *
2641 * We determine which interrupt scheme to use based on...
2642 * - Kernel support (MSI, MSI-X)
2643 * - which can be user-defined (via MODULE_PARAM)
2644 * - Hardware queue count (num_*_queues)
2645 * - defined by miscellaneous hardware support/features (RSS, etc.)
2646 **/
2f90b865 2647int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 2648{
2649 int err;
2650
2651 /* Number of supported queues */
2652 ixgbe_set_num_queues(adapter);
2653
2654 err = ixgbe_alloc_queues(adapter);
2655 if (err) {
2656 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2657 goto err_alloc_queues;
2658 }
2659
2660 err = ixgbe_set_interrupt_capability(adapter);
2661 if (err) {
2662 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2663 goto err_set_interrupt;
9a799d71
AK		 2664 }
2665
021230d4 2666 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
b4617240
PW		 2667 "Tx Queue count = %u\n",
2668 (adapter->num_rx_queues > 1) ? "Enabled" :
2669 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 2670
2671 set_bit(__IXGBE_DOWN, &adapter->state);
2672
9a799d71 2673 return 0;
021230d4
AV		 2674
2675err_set_interrupt:
2676 kfree(adapter->tx_ring);
2677 kfree(adapter->rx_ring);
2678err_alloc_queues:
2679 return err;
9a799d71
AK		 2680}
2681
2682/**
2683 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2684 * @adapter: board private structure to initialize
2685 *
2686 * ixgbe_sw_init initializes the Adapter private data structure.
2687 * Fields are initialized based on PCI device information and
2688 * OS network device settings (MTU size).
2689 **/
2690static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2691{
2692 struct ixgbe_hw *hw = &adapter->hw;
2693 struct pci_dev *pdev = adapter->pdev;
021230d4 2694 unsigned int rss;
2f90b865
AD		 2695#ifdef CONFIG_IXGBE_DCBNL
2696 int j;
2697 struct tc_configuration *tc;
2698#endif
021230d4 2699
c44ade9e
JB		 2700 /* PCI config space info */
2701
2702 hw->vendor_id = pdev->vendor;
2703 hw->device_id = pdev->device;
2704 hw->revision_id = pdev->revision;
2705 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2706 hw->subsystem_device_id = pdev->subsystem_device;
2707
021230d4
AV		 2708 /* Set capability flags */
2709 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2710 adapter->ring_feature[RING_F_RSS].indices = rss;
2711 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2f90b865
AD		 2712 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
2713
2714#ifdef CONFIG_IXGBE_DCBNL
2715 /* Configure DCB traffic classes */
2716 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
2717 tc = &adapter->dcb_cfg.tc_config[j];
2718 tc->path[DCB_TX_CONFIG].bwg_id = 0;
2719 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
2720 tc->path[DCB_RX_CONFIG].bwg_id = 0;
2721 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
2722 tc->dcb_pfc = pfc_disabled;
2723 }
2724 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
2725 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
2726 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
2727 adapter->dcb_cfg.round_robin_enable = false;
2728 adapter->dcb_set_bitmap = 0x00;
2729 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
2730 adapter->ring_feature[RING_F_DCB].indices);
2731
2732#endif
0befdb3e
JB		 2733 if (hw->mac.ops.get_media_type &&
2734 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper))
2735 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
9a799d71
AK		 2736
2737 /* default flow control settings */
2b9ade93
JB		 2738 hw->fc.original_type = ixgbe_fc_none;
2739 hw->fc.type = ixgbe_fc_none;
2740 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2741 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2742 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2743 hw->fc.send_xon = true;
9a799d71 2744
021230d4 2745 /* select 10G link by default */
9a799d71 2746 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
9a799d71 2747
30efa5a3
JB		 2748 /* enable itr by default in dynamic mode */
2749 adapter->itr_setting = 1;
2750 adapter->eitr_param = 20000;
2751
2752 /* set defaults for eitr in MegaBytes */
2753 adapter->eitr_low = 10;
2754 adapter->eitr_high = 20;
2755
2756 /* set default ring sizes */
2757 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2758 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2759
9a799d71 2760 /* initialize eeprom parameters */
c44ade9e 2761 if (ixgbe_init_eeprom_params_generic(hw)) {
9a799d71
AK		 2762 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2763 return -EIO;
2764 }
2765
021230d4 2766 /* enable rx csum by default */
9a799d71
AK		 2767 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2768
9a799d71
AK		 2769 set_bit(__IXGBE_DOWN, &adapter->state);
2770
2771 return 0;
2772}
2773
2774/**
2775 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2776 * @adapter: board private structure
3a581073 2777 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2778 *
2779 * Return 0 on success, negative on failure
2780 **/
2781int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
e01c31a5 2782 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2783{
2784 struct pci_dev *pdev = adapter->pdev;
2785 int size;
2786
3a581073
JB		 2787 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2788 tx_ring->tx_buffer_info = vmalloc(size);
e01c31a5
JB		 2789 if (!tx_ring->tx_buffer_info)
2790 goto err;
3a581073 2791 memset(tx_ring->tx_buffer_info, 0, size);
9a799d71
AK		 2792
2793 /* round up to nearest 4K */
e01c31a5
JB		 2794 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2795 sizeof(u32);
3a581073 2796 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 2797
3a581073
JB		 2798 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2799 &tx_ring->dma);
e01c31a5
JB		 2800 if (!tx_ring->desc)
2801 goto err;
9a799d71 2802
3a581073
JB		 2803 tx_ring->next_to_use = 0;
2804 tx_ring->next_to_clean = 0;
2805 tx_ring->work_limit = tx_ring->count;
9a799d71 2806 return 0;
e01c31a5
JB		 2807
2808err:
2809 vfree(tx_ring->tx_buffer_info);
2810 tx_ring->tx_buffer_info = NULL;
2811 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2812 "descriptor ring\n");
2813 return -ENOMEM;
9a799d71
AK		 2814}
2815
69888674
AD		 2816/**
2817 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
2818 * @adapter: board private structure
2819 *
2820 * If this function returns with an error, then it's possible one or
2821 * more of the rings is populated (while the rest are not). It is the
2822 * callers duty to clean those orphaned rings.
2823 *
2824 * Return 0 on success, negative on failure
2825 **/
2826static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2827{
2828 int i, err = 0;
2829
2830 for (i = 0; i < adapter->num_tx_queues; i++) {
2831 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2832 if (!err)
2833 continue;
2834 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
2835 break;
2836 }
2837
2838 return err;
2839}
2840
9a799d71
AK		 2841/**
2842 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2843 * @adapter: board private structure
3a581073 2844 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 2845 *
2846 * Returns 0 on success, negative on failure
2847 **/
2848int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
b4617240 2849 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2850{
2851 struct pci_dev *pdev = adapter->pdev;
021230d4 2852 int size;
9a799d71 2853
177db6ff 2854 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
3a581073
JB		 2855 rx_ring->lro_mgr.lro_arr = vmalloc(size);
2856 if (!rx_ring->lro_mgr.lro_arr)
177db6ff 2857 return -ENOMEM;
3a581073 2858 memset(rx_ring->lro_mgr.lro_arr, 0, size);
177db6ff 2859
3a581073
JB		 2860 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2861 rx_ring->rx_buffer_info = vmalloc(size);
2862 if (!rx_ring->rx_buffer_info) {
9a799d71 2863 DPRINTK(PROBE, ERR,
b4617240 2864 "vmalloc allocation failed for the rx desc ring\n");
177db6ff 2865 goto alloc_failed;
9a799d71 2866 }
3a581073 2867 memset(rx_ring->rx_buffer_info, 0, size);
9a799d71 2868
9a799d71 2869 /* Round up to nearest 4K */
3a581073
JB		 2870 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2871 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 2872
3a581073 2873 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
9a799d71 2874
3a581073 2875 if (!rx_ring->desc) {
9a799d71 2876 DPRINTK(PROBE, ERR,
b4617240 2877 "Memory allocation failed for the rx desc ring\n");
3a581073 2878 vfree(rx_ring->rx_buffer_info);
177db6ff 2879 goto alloc_failed;
9a799d71
AK		 2880 }
2881
3a581073
JB		 2882 rx_ring->next_to_clean = 0;
2883 rx_ring->next_to_use = 0;
9a799d71
AK		 2884
2885 return 0;
177db6ff
MC		 2886
2887alloc_failed:
3a581073
JB		 2888 vfree(rx_ring->lro_mgr.lro_arr);
2889 rx_ring->lro_mgr.lro_arr = NULL;
177db6ff 2890 return -ENOMEM;
9a799d71
AK		 2891}
2892
69888674
AD		 2893/**
2894 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
2895 * @adapter: board private structure
2896 *
2897 * If this function returns with an error, then it's possible one or
2898 * more of the rings is populated (while the rest are not). It is the
2899 * callers duty to clean those orphaned rings.
2900 *
2901 * Return 0 on success, negative on failure
2902 **/
2903
2904static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2905{
2906 int i, err = 0;
2907
2908 for (i = 0; i < adapter->num_rx_queues; i++) {
2909 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2910 if (!err)
2911 continue;
2912 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
2913 break;
2914 }
2915
2916 return err;
2917}
2918
9a799d71
AK		 2919/**
2920 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2921 * @adapter: board private structure
2922 * @tx_ring: Tx descriptor ring for a specific queue
2923 *
2924 * Free all transmit software resources
2925 **/
c431f97e
JB		 2926void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2927 struct ixgbe_ring *tx_ring)
9a799d71
AK		 2928{
2929 struct pci_dev *pdev = adapter->pdev;
2930
2931 ixgbe_clean_tx_ring(adapter, tx_ring);
2932
2933 vfree(tx_ring->tx_buffer_info);
2934 tx_ring->tx_buffer_info = NULL;
2935
2936 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2937
2938 tx_ring->desc = NULL;
2939}
2940
2941/**
2942 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2943 * @adapter: board private structure
2944 *
2945 * Free all transmit software resources
2946 **/
2947static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2948{
2949 int i;
2950
2951 for (i = 0; i < adapter->num_tx_queues; i++)
2952 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2953}
2954
2955/**
b4617240 2956 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 2957 * @adapter: board private structure
2958 * @rx_ring: ring to clean the resources from
2959 *
2960 * Free all receive software resources
2961 **/
c431f97e
JB		 2962void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2963 struct ixgbe_ring *rx_ring)
9a799d71
AK		 2964{
2965 struct pci_dev *pdev = adapter->pdev;
2966
177db6ff
MC		 2967 vfree(rx_ring->lro_mgr.lro_arr);
2968 rx_ring->lro_mgr.lro_arr = NULL;
2969
9a799d71
AK		 2970 ixgbe_clean_rx_ring(adapter, rx_ring);
2971
2972 vfree(rx_ring->rx_buffer_info);
2973 rx_ring->rx_buffer_info = NULL;
2974
2975 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2976
2977 rx_ring->desc = NULL;
2978}
2979
2980/**
2981 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2982 * @adapter: board private structure
2983 *
2984 * Free all receive software resources
2985 **/
2986static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2987{
2988 int i;
2989
2990 for (i = 0; i < adapter->num_rx_queues; i++)
2991 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2992}
2993
9a799d71
AK		 2994/**
2995 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2996 * @netdev: network interface device structure
2997 * @new_mtu: new value for maximum frame size
2998 *
2999 * Returns 0 on success, negative on failure
3000 **/
3001static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
3002{
3003 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3004 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3005
42c783c5
JB		 3006 /* MTU < 68 is an error and causes problems on some kernels */
3007 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
9a799d71
AK		 3008 return -EINVAL;
3009
021230d4 3010 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
b4617240 3011 netdev->mtu, new_mtu);
021230d4 3012 /* must set new MTU before calling down or up */
9a799d71
AK		 3013 netdev->mtu = new_mtu;
3014
d4f80882
AV		 3015 if (netif_running(netdev))
3016 ixgbe_reinit_locked(adapter);
9a799d71
AK		 3017
3018 return 0;
3019}
3020
3021/**
3022 * ixgbe_open - Called when a network interface is made active
3023 * @netdev: network interface device structure
3024 *
3025 * Returns 0 on success, negative value on failure
3026 *
3027 * The open entry point is called when a network interface is made
3028 * active by the system (IFF_UP). At this point all resources needed
3029 * for transmit and receive operations are allocated, the interrupt
3030 * handler is registered with the OS, the watchdog timer is started,
3031 * and the stack is notified that the interface is ready.
3032 **/
3033static int ixgbe_open(struct net_device *netdev)
3034{
3035 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3036 int err;
4bebfaa5
AK		 3037
3038 /* disallow open during test */
3039 if (test_bit(__IXGBE_TESTING, &adapter->state))
3040 return -EBUSY;
9a799d71 3041
9a799d71
AK		 3042 /* allocate transmit descriptors */
3043 err = ixgbe_setup_all_tx_resources(adapter);
3044 if (err)
3045 goto err_setup_tx;
3046
9a799d71
AK		 3047 /* allocate receive descriptors */
3048 err = ixgbe_setup_all_rx_resources(adapter);
3049 if (err)
3050 goto err_setup_rx;
3051
3052 ixgbe_configure(adapter);
3053
021230d4 3054 err = ixgbe_request_irq(adapter);
9a799d71
AK		 3055 if (err)
3056 goto err_req_irq;
3057
9a799d71
AK		 3058 err = ixgbe_up_complete(adapter);
3059 if (err)
3060 goto err_up;
3061
d55b53ff
JK		 3062 netif_tx_start_all_queues(netdev);
3063
9a799d71
AK		 3064 return 0;
3065
3066err_up:
5eba3699 3067 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3068 ixgbe_free_irq(adapter);
3069err_req_irq:
3070 ixgbe_free_all_rx_resources(adapter);
3071err_setup_rx:
3072 ixgbe_free_all_tx_resources(adapter);
3073err_setup_tx:
3074 ixgbe_reset(adapter);
3075
3076 return err;
3077}
3078
3079/**
3080 * ixgbe_close - Disables a network interface
3081 * @netdev: network interface device structure
3082 *
3083 * Returns 0, this is not allowed to fail
3084 *
3085 * The close entry point is called when an interface is de-activated
3086 * by the OS. The hardware is still under the drivers control, but
3087 * needs to be disabled. A global MAC reset is issued to stop the
3088 * hardware, and all transmit and receive resources are freed.
3089 **/
3090static int ixgbe_close(struct net_device *netdev)
3091{
3092 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 3093
3094 ixgbe_down(adapter);
3095 ixgbe_free_irq(adapter);
3096
3097 ixgbe_free_all_tx_resources(adapter);
3098 ixgbe_free_all_rx_resources(adapter);
3099
5eba3699 3100 ixgbe_release_hw_control(adapter);
9a799d71
AK		 3101
3102 return 0;
3103}
3104
b3c8b4ba
AD		 3105/**
3106 * ixgbe_napi_add_all - prep napi structs for use
3107 * @adapter: private struct
3108 * helper function to napi_add each possible q_vector->napi
3109 */
2f90b865 3110void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3111{
3112 int q_idx, q_vectors;
3113 int (*poll)(struct napi_struct *, int);
3114
3115 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3116 poll = &ixgbe_clean_rxonly;
3117 /* Only enable as many vectors as we have rx queues. */
3118 q_vectors = adapter->num_rx_queues;
3119 } else {
3120 poll = &ixgbe_poll;
3121 /* only one q_vector for legacy modes */
3122 q_vectors = 1;
3123 }
3124
3125 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3126 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3127 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3128 }
3129}
3130
2f90b865 3131void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
b3c8b4ba
AD		 3132{
3133 int q_idx;
3134 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3135
3136 /* legacy and MSI only use one vector */
3137 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3138 q_vectors = 1;
3139
3140 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3141 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
3142 if (!q_vector->rxr_count)
3143 continue;
3144 netif_napi_del(&q_vector->napi);
3145 }
3146}
3147
3148#ifdef CONFIG_PM
3149static int ixgbe_resume(struct pci_dev *pdev)
3150{
3151 struct net_device *netdev = pci_get_drvdata(pdev);
3152 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3153 u32 err;
3154
3155 pci_set_power_state(pdev, PCI_D0);
3156 pci_restore_state(pdev);
3157 err = pci_enable_device(pdev);
3158 if (err) {
69888674 3159 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
b3c8b4ba
AD		 3160 "suspend\n");
3161 return err;
3162 }
3163 pci_set_master(pdev);
3164
3165 pci_enable_wake(pdev, PCI_D3hot, 0);
3166 pci_enable_wake(pdev, PCI_D3cold, 0);
3167
3168 err = ixgbe_init_interrupt_scheme(adapter);
3169 if (err) {
3170 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3171 "device\n");
3172 return err;
3173 }
3174
3175 ixgbe_napi_add_all(adapter);
3176 ixgbe_reset(adapter);
3177
3178 if (netif_running(netdev)) {
3179 err = ixgbe_open(adapter->netdev);
3180 if (err)
3181 return err;
3182 }
3183
3184 netif_device_attach(netdev);
3185
3186 return 0;
3187}
3188
3189#endif /* CONFIG_PM */
3190static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3191{
3192 struct net_device *netdev = pci_get_drvdata(pdev);
3193 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3194#ifdef CONFIG_PM
3195 int retval = 0;
3196#endif
3197
3198 netif_device_detach(netdev);
3199
3200 if (netif_running(netdev)) {
3201 ixgbe_down(adapter);
3202 ixgbe_free_irq(adapter);
3203 ixgbe_free_all_tx_resources(adapter);
3204 ixgbe_free_all_rx_resources(adapter);
3205 }
3206 ixgbe_reset_interrupt_capability(adapter);
3207 ixgbe_napi_del_all(adapter);
3208 kfree(adapter->tx_ring);
3209 kfree(adapter->rx_ring);
3210
3211#ifdef CONFIG_PM
3212 retval = pci_save_state(pdev);
3213 if (retval)
3214 return retval;
3215#endif
3216
3217 pci_enable_wake(pdev, PCI_D3hot, 0);
3218 pci_enable_wake(pdev, PCI_D3cold, 0);
3219
3220 ixgbe_release_hw_control(adapter);
3221
3222 pci_disable_device(pdev);
3223
3224 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3225
3226 return 0;
3227}
3228
3229static void ixgbe_shutdown(struct pci_dev *pdev)
3230{
3231 ixgbe_suspend(pdev, PMSG_SUSPEND);
3232}
3233
9a799d71
AK		 3234/**
3235 * ixgbe_update_stats - Update the board statistics counters.
3236 * @adapter: board private structure
3237 **/
3238void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3239{
3240 struct ixgbe_hw *hw = &adapter->hw;
6f11eef7
AV		 3241 u64 total_mpc = 0;
3242 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
9a799d71
AK		 3243
3244 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 3245 for (i = 0; i < 8; i++) {
3246 /* for packet buffers not used, the register should read 0 */
3247 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3248 missed_rx += mpc;
3249 adapter->stats.mpc[i] += mpc;
3250 total_mpc += adapter->stats.mpc[i];
3251 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2f90b865
AD		 3252 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3253 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
3254 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3255 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3256 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
3257 IXGBE_PXONRXC(i));
3258 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
3259 IXGBE_PXONTXC(i));
3260 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
3261 IXGBE_PXOFFRXC(i));
3262 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
3263 IXGBE_PXOFFTXC(i));
6f11eef7
AV		 3264 }
3265 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3266 /* work around hardware counting issue */
3267 adapter->stats.gprc -= missed_rx;
3268
3269 /* 82598 hardware only has a 32 bit counter in the high register */
9a799d71 3270 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6f11eef7
AV		 3271 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3272 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
9a799d71
AK		 3273 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3274 adapter->stats.bprc += bprc;
3275 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3276 adapter->stats.mprc -= bprc;
3277 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3278 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3279 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3280 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3281 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3282 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3283 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
9a799d71
AK		 3284 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3285 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
9a799d71 3286 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6f11eef7
AV		 3287 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3288 adapter->stats.lxontxc += lxon;
3289 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3290 adapter->stats.lxofftxc += lxoff;
9a799d71
AK		 3291 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3292 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6f11eef7
AV		 3293 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3294 /*
3295 * 82598 errata - tx of flow control packets is included in tx counters
3296 */
3297 xon_off_tot = lxon + lxoff;
3298 adapter->stats.gptc -= xon_off_tot;
3299 adapter->stats.mptc -= xon_off_tot;
3300 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
9a799d71
AK		 3301 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3302 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3303 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
9a799d71
AK		 3304 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3305 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6f11eef7 3306 adapter->stats.ptc64 -= xon_off_tot;
9a799d71
AK		 3307 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3308 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3309 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3310 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3311 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
9a799d71
AK		 3312 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3313
3314 /* Fill out the OS statistics structure */
9a799d71
AK		 3315 adapter->net_stats.multicast = adapter->stats.mprc;
3316
3317 /* Rx Errors */
3318 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
b4617240 3319 adapter->stats.rlec;
9a799d71
AK		 3320 adapter->net_stats.rx_dropped = 0;
3321 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3322 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
6f11eef7 3323 adapter->net_stats.rx_missed_errors = total_mpc;
9a799d71
AK		 3324}
3325
3326/**
3327 * ixgbe_watchdog - Timer Call-back
3328 * @data: pointer to adapter cast into an unsigned long
3329 **/
3330static void ixgbe_watchdog(unsigned long data)
3331{
3332 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
cf8280ee
JB		 3333 struct ixgbe_hw *hw = &adapter->hw;
3334
3335 /* Do the watchdog outside of interrupt context due to the lovely
3336 * delays that some of the newer hardware requires */
3337 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3338 /* Cause software interrupt to ensure rx rings are cleaned */
3339 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3340 u32 eics =
3341 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3342 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3343 } else {
3344 /* For legacy and MSI interrupts don't set any bits that
3345 * are enabled for EIAM, because this operation would
3346 * set *both* EIMS and EICS for any bit in EIAM */
3347 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3348 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3349 }
3350 /* Reset the timer */
3351 mod_timer(&adapter->watchdog_timer,
3352 round_jiffies(jiffies + 2 * HZ));
3353 }
9a799d71 3354
cf8280ee
JB		 3355 schedule_work(&adapter->watchdog_task);
3356}
3357
3358/**
69888674
AD		 3359 * ixgbe_watchdog_task - worker thread to bring link up
3360 * @work: pointer to work_struct containing our data
cf8280ee
JB		 3361 **/
3362static void ixgbe_watchdog_task(struct work_struct *work)
3363{
3364 struct ixgbe_adapter *adapter = container_of(work,
3365 struct ixgbe_adapter,
3366 watchdog_task);
3367 struct net_device *netdev = adapter->netdev;
3368 struct ixgbe_hw *hw = &adapter->hw;
3369 u32 link_speed = adapter->link_speed;
3370 bool link_up = adapter->link_up;
3371
3372 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3373
3374 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3375 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3376 if (link_up ||
3377 time_after(jiffies, (adapter->link_check_timeout +
3378 IXGBE_TRY_LINK_TIMEOUT))) {
3379 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3380 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3381 }
3382 adapter->link_up = link_up;
3383 adapter->link_speed = link_speed;
3384 }
9a799d71
AK		 3385
3386 if (link_up) {
3387 if (!netif_carrier_ok(netdev)) {
cf8280ee
JB		 3388 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3389 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
9a799d71
AK		 3390#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3391#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3392 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
cf8280ee
JB		 3393 "Flow Control: %s\n",
3394 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3395 "10 Gbps" :
3396 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3397 "1 Gbps" : "unknown speed")),
3398 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3399 (FLOW_RX ? "RX" :
3400 (FLOW_TX ? "TX" : "None"))));
9a799d71
AK		 3401
3402 netif_carrier_on(netdev);
2f90b865 3403 netif_tx_wake_all_queues(netdev);
9a799d71
AK		 3404 } else {
3405 /* Force detection of hung controller */
3406 adapter->detect_tx_hung = true;
3407 }
3408 } else {
cf8280ee
JB		 3409 adapter->link_up = false;
3410 adapter->link_speed = 0;
9a799d71
AK		 3411 if (netif_carrier_ok(netdev)) {
3412 DPRINTK(LINK, INFO, "NIC Link is Down\n");
3413 netif_carrier_off(netdev);
2f90b865 3414 netif_tx_stop_all_queues(netdev);
9a799d71
AK		 3415 }
3416 }
3417
3418 ixgbe_update_stats(adapter);
cf8280ee 3419 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
9a799d71
AK		 3420}
3421
9a799d71 3422static int ixgbe_tso(struct ixgbe_adapter *adapter,
b4617240
PW		 3423 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3424 u32 tx_flags, u8 *hdr_len)
9a799d71
AK		 3425{
3426 struct ixgbe_adv_tx_context_desc *context_desc;
3427 unsigned int i;
3428 int err;
3429 struct ixgbe_tx_buffer *tx_buffer_info;
9f8cdf4f
JB		 3430 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3431 u32 mss_l4len_idx, l4len;
9a799d71
AK		 3432
3433 if (skb_is_gso(skb)) {
3434 if (skb_header_cloned(skb)) {
3435 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3436 if (err)
3437 return err;
3438 }
3439 l4len = tcp_hdrlen(skb);
3440 *hdr_len += l4len;
3441
8327d000 3442 if (skb->protocol == htons(ETH_P_IP)) {
9a799d71
AK		 3443 struct iphdr *iph = ip_hdr(skb);
3444 iph->tot_len = 0;
3445 iph->check = 0;
3446 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
b4617240
PW		 3447 iph->daddr, 0,
3448 IPPROTO_TCP,
3449 0);
9a799d71
AK		 3450 adapter->hw_tso_ctxt++;
3451 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3452 ipv6_hdr(skb)->payload_len = 0;
3453 tcp_hdr(skb)->check =
3454 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
b4617240
PW		 3455 &ipv6_hdr(skb)->daddr,
3456 0, IPPROTO_TCP, 0);
9a799d71
AK		 3457 adapter->hw_tso6_ctxt++;
3458 }
3459
3460 i = tx_ring->next_to_use;
3461
3462 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3463 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3464
3465 /* VLAN MACLEN IPLEN */
3466 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3467 vlan_macip_lens |=
3468 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3469 vlan_macip_lens |= ((skb_network_offset(skb)) <<
b4617240 3470 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3471 *hdr_len += skb_network_offset(skb);
3472 vlan_macip_lens |=
3473 (skb_transport_header(skb) - skb_network_header(skb));
3474 *hdr_len +=
3475 (skb_transport_header(skb) - skb_network_header(skb));
3476 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3477 context_desc->seqnum_seed = 0;
3478
3479 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
9f8cdf4f 3480 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
b4617240 3481 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71 3482
8327d000 3483 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3484 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3485 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3486 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3487
3488 /* MSS L4LEN IDX */
9f8cdf4f 3489 mss_l4len_idx =
9a799d71
AK		 3490 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3491 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4eeae6fd
PW		 3492 /* use index 1 for TSO */
3493 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3494 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3495
3496 tx_buffer_info->time_stamp = jiffies;
3497 tx_buffer_info->next_to_watch = i;
3498
3499 i++;
3500 if (i == tx_ring->count)
3501 i = 0;
3502 tx_ring->next_to_use = i;
3503
3504 return true;
3505 }
3506 return false;
3507}
3508
3509static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
b4617240
PW		 3510 struct ixgbe_ring *tx_ring,
3511 struct sk_buff *skb, u32 tx_flags)
9a799d71
AK		 3512{
3513 struct ixgbe_adv_tx_context_desc *context_desc;
3514 unsigned int i;
3515 struct ixgbe_tx_buffer *tx_buffer_info;
3516 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3517
3518 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3519 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3520 i = tx_ring->next_to_use;
3521 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3522 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3523
3524 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3525 vlan_macip_lens |=
3526 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3527 vlan_macip_lens |= (skb_network_offset(skb) <<
b4617240 3528 IXGBE_ADVTXD_MACLEN_SHIFT);
9a799d71
AK		 3529 if (skb->ip_summed == CHECKSUM_PARTIAL)
3530 vlan_macip_lens |= (skb_transport_header(skb) -
b4617240 3531 skb_network_header(skb));
9a799d71
AK		 3532
3533 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3534 context_desc->seqnum_seed = 0;
3535
3536 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
b4617240 3537 IXGBE_ADVTXD_DTYP_CTXT);
9a799d71
AK		 3538
3539 if (skb->ip_summed == CHECKSUM_PARTIAL) {
41825d71
AK		 3540 switch (skb->protocol) {
3541 case __constant_htons(ETH_P_IP):
9a799d71 3542 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
41825d71
AK		 3543 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3544 type_tucmd_mlhl |=
b4617240 3545 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3546 break;
41825d71
AK		 3547 case __constant_htons(ETH_P_IPV6):
3548 /* XXX what about other V6 headers?? */
3549 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3550 type_tucmd_mlhl |=
b4617240 3551 IXGBE_ADVTXD_TUCMD_L4T_TCP;
41825d71 3552 break;
41825d71
AK		 3553 default:
3554 if (unlikely(net_ratelimit())) {
3555 DPRINTK(PROBE, WARNING,
3556 "partial checksum but proto=%x!\n",
3557 skb->protocol);
3558 }
3559 break;
3560 }
9a799d71
AK		 3561 }
3562
3563 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4eeae6fd 3564 /* use index zero for tx checksum offload */
9a799d71
AK		 3565 context_desc->mss_l4len_idx = 0;
3566
3567 tx_buffer_info->time_stamp = jiffies;
3568 tx_buffer_info->next_to_watch = i;
9f8cdf4f 3569
9a799d71
AK		 3570 adapter->hw_csum_tx_good++;
3571 i++;
3572 if (i == tx_ring->count)
3573 i = 0;
3574 tx_ring->next_to_use = i;
3575
3576 return true;
3577 }
9f8cdf4f 3578
9a799d71
AK		 3579 return false;
3580}
3581
3582static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
b4617240
PW		 3583 struct ixgbe_ring *tx_ring,
3584 struct sk_buff *skb, unsigned int first)
9a799d71
AK		 3585{
3586 struct ixgbe_tx_buffer *tx_buffer_info;
3587 unsigned int len = skb->len;
3588 unsigned int offset = 0, size, count = 0, i;
3589 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3590 unsigned int f;
3591
3592 len -= skb->data_len;
3593
3594 i = tx_ring->next_to_use;
3595
3596 while (len) {
3597 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3598 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3599
3600 tx_buffer_info->length = size;
3601 tx_buffer_info->dma = pci_map_single(adapter->pdev,
b4617240
PW		 3602 skb->data + offset,
3603 size, PCI_DMA_TODEVICE);
9a799d71
AK		 3604 tx_buffer_info->time_stamp = jiffies;
3605 tx_buffer_info->next_to_watch = i;
3606
3607 len -= size;
3608 offset += size;
3609 count++;
3610 i++;
3611 if (i == tx_ring->count)
3612 i = 0;
3613 }
3614
3615 for (f = 0; f < nr_frags; f++) {
3616 struct skb_frag_struct *frag;
3617
3618 frag = &skb_shinfo(skb)->frags[f];
3619 len = frag->size;
3620 offset = frag->page_offset;
3621
3622 while (len) {
3623 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3624 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3625
3626 tx_buffer_info->length = size;
3627 tx_buffer_info->dma = pci_map_page(adapter->pdev,
b4617240
PW		 3628 frag->page,
3629 offset,
3630 size,
3631 PCI_DMA_TODEVICE);
9a799d71
AK		 3632 tx_buffer_info->time_stamp = jiffies;
3633 tx_buffer_info->next_to_watch = i;
3634
3635 len -= size;
3636 offset += size;
3637 count++;
3638 i++;
3639 if (i == tx_ring->count)
3640 i = 0;
3641 }
3642 }
3643 if (i == 0)
3644 i = tx_ring->count - 1;
3645 else
3646 i = i - 1;
3647 tx_ring->tx_buffer_info[i].skb = skb;
3648 tx_ring->tx_buffer_info[first].next_to_watch = i;
3649
3650 return count;
3651}
3652
3653static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
b4617240
PW		 3654 struct ixgbe_ring *tx_ring,
3655 int tx_flags, int count, u32 paylen, u8 hdr_len)
9a799d71
AK		 3656{
3657 union ixgbe_adv_tx_desc *tx_desc = NULL;
3658 struct ixgbe_tx_buffer *tx_buffer_info;
3659 u32 olinfo_status = 0, cmd_type_len = 0;
3660 unsigned int i;
3661 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3662
3663 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3664
3665 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3666
3667 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3668 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3669
3670 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3671 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3672
3673 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3674 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71 3675
4eeae6fd
PW		 3676 /* use index 1 context for tso */
3677 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
9a799d71
AK		 3678 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3679 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
b4617240 3680 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3681
3682 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3683 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
b4617240 3684 IXGBE_ADVTXD_POPTS_SHIFT;
9a799d71
AK		 3685
3686 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3687
3688 i = tx_ring->next_to_use;
3689 while (count--) {
3690 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3691 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3692 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3693 tx_desc->read.cmd_type_len =
b4617240 3694 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
9a799d71 3695 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
9a799d71
AK		 3696 i++;
3697 if (i == tx_ring->count)
3698 i = 0;
3699 }
3700
3701 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3702
3703 /*
3704 * Force memory writes to complete before letting h/w
3705 * know there are new descriptors to fetch. (Only
3706 * applicable for weak-ordered memory model archs,
3707 * such as IA-64).
3708 */
3709 wmb();
3710
3711 tx_ring->next_to_use = i;
3712 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3713}
3714
e092be60 3715static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3716 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3717{
3718 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3719
30eba97a 3720 netif_stop_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3721 /* Herbert's original patch had:
3722 * smp_mb__after_netif_stop_queue();
3723 * but since that doesn't exist yet, just open code it. */
3724 smp_mb();
3725
3726 /* We need to check again in a case another CPU has just
3727 * made room available. */
3728 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3729 return -EBUSY;
3730
3731 /* A reprieve! - use start_queue because it doesn't call schedule */
af72166f 3732 netif_start_subqueue(netdev, tx_ring->queue_index);
e092be60
AV		 3733 ++adapter->restart_queue;
3734 return 0;
3735}
3736
3737static int ixgbe_maybe_stop_tx(struct net_device *netdev,
b4617240 3738 struct ixgbe_ring *tx_ring, int size)
e092be60
AV		 3739{
3740 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3741 return 0;
3742 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3743}
3744
9a799d71
AK		 3745static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3746{
3747 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3748 struct ixgbe_ring *tx_ring;
9a799d71
AK		 3749 unsigned int first;
3750 unsigned int tx_flags = 0;
30eba97a
AV		 3751 u8 hdr_len = 0;
3752 int r_idx = 0, tso;
9a799d71
AK		 3753 int count = 0;
3754 unsigned int f;
9f8cdf4f 3755
30eba97a 3756 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
30eba97a 3757 tx_ring = &adapter->tx_ring[r_idx];
9a799d71 3758
9f8cdf4f
JB		 3759 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3760 tx_flags |= vlan_tx_tag_get(skb);
2f90b865
AD		 3761 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3762 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
3763 tx_flags |= (skb->queue_mapping << 13);
3764 }
3765 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3766 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3767 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3768 tx_flags |= (skb->queue_mapping << 13);
9f8cdf4f
JB		 3769 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3770 tx_flags |= IXGBE_TX_FLAGS_VLAN;
9a799d71 3771 }
9f8cdf4f
JB		 3772 /* three things can cause us to need a context descriptor */
3773 if (skb_is_gso(skb) ||
3774 (skb->ip_summed == CHECKSUM_PARTIAL) ||
3775 (tx_flags & IXGBE_TX_FLAGS_VLAN))
9a799d71
AK		 3776 count++;
3777
9f8cdf4f
JB		 3778 count += TXD_USE_COUNT(skb_headlen(skb));
3779 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
9a799d71
AK		 3780 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3781
e092be60 3782 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
9a799d71 3783 adapter->tx_busy++;
9a799d71
AK		 3784 return NETDEV_TX_BUSY;
3785 }
9a799d71 3786
8327d000 3787 if (skb->protocol == htons(ETH_P_IP))
9a799d71
AK		 3788 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3789 first = tx_ring->next_to_use;
3790 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3791 if (tso < 0) {
3792 dev_kfree_skb_any(skb);
3793 return NETDEV_TX_OK;
3794 }
3795
3796 if (tso)
3797 tx_flags |= IXGBE_TX_FLAGS_TSO;
3798 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
b4617240 3799 (skb->ip_summed == CHECKSUM_PARTIAL))
9a799d71
AK		 3800 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3801
3802 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
b4617240
PW		 3803 ixgbe_tx_map(adapter, tx_ring, skb, first),
3804 skb->len, hdr_len);
9a799d71
AK		 3805
3806 netdev->trans_start = jiffies;
3807
e092be60 3808 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
9a799d71
AK		 3809
3810 return NETDEV_TX_OK;
3811}
3812
3813/**
3814 * ixgbe_get_stats - Get System Network Statistics
3815 * @netdev: network interface device structure
3816 *
3817 * Returns the address of the device statistics structure.
3818 * The statistics are actually updated from the timer callback.
3819 **/
3820static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3821{
3822 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3823
3824 /* only return the current stats */
3825 return &adapter->net_stats;
3826}
3827
3828/**
3829 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3830 * @netdev: network interface device structure
3831 * @p: pointer to an address structure
3832 *
3833 * Returns 0 on success, negative on failure
3834 **/
3835static int ixgbe_set_mac(struct net_device *netdev, void *p)
3836{
3837 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 3838 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3839 struct sockaddr *addr = p;
3840
3841 if (!is_valid_ether_addr(addr->sa_data))
3842 return -EADDRNOTAVAIL;
3843
3844 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 3845 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 3846
b4617240 3847 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
9a799d71
AK		 3848
3849 return 0;
3850}
3851
3852#ifdef CONFIG_NET_POLL_CONTROLLER
3853/*
3854 * Polling 'interrupt' - used by things like netconsole to send skbs
3855 * without having to re-enable interrupts. It's not called while
3856 * the interrupt routine is executing.
3857 */
3858static void ixgbe_netpoll(struct net_device *netdev)
3859{
3860 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3861
3862 disable_irq(adapter->pdev->irq);
3863 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3864 ixgbe_intr(adapter->pdev->irq, netdev);
3865 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3866 enable_irq(adapter->pdev->irq);
3867}
3868#endif
3869
c44ade9e
JB		 3870/**
3871 * ixgbe_link_config - set up initial link with default speed and duplex
3872 * @hw: pointer to private hardware struct
3873 *
3874 * Returns 0 on success, negative on failure
3875 **/
3876static int ixgbe_link_config(struct ixgbe_hw *hw)
3877{
3878 u32 autoneg = IXGBE_LINK_SPEED_10GB_FULL;
3879
3880 /* must always autoneg for both 1G and 10G link */
3881 hw->mac.autoneg = true;
3882
0befdb3e
JB		 3883 if ((hw->mac.type == ixgbe_mac_82598EB) &&
3884 (hw->phy.media_type == ixgbe_media_type_copper))
3885 autoneg = IXGBE_LINK_SPEED_82598_AUTONEG;
3886
c44ade9e
JB		 3887 return hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3888}
3889
0edc3527
SH		 3890static const struct net_device_ops ixgbe_netdev_ops = {
3891 .ndo_open = ixgbe_open,
3892 .ndo_stop = ixgbe_close,
00829823 3893 .ndo_start_xmit = ixgbe_xmit_frame,
0edc3527
SH		 3894 .ndo_get_stats = ixgbe_get_stats,
3895 .ndo_set_multicast_list = ixgbe_set_rx_mode,
3896 .ndo_validate_addr = eth_validate_addr,
3897 .ndo_set_mac_address = ixgbe_set_mac,
3898 .ndo_change_mtu = ixgbe_change_mtu,
3899 .ndo_tx_timeout = ixgbe_tx_timeout,
3900 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
3901 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
3902 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
3903#ifdef CONFIG_NET_POLL_CONTROLLER
3904 .ndo_poll_controller = ixgbe_netpoll,
3905#endif
3906};
3907
9a799d71
AK		 3908/**
3909 * ixgbe_probe - Device Initialization Routine
3910 * @pdev: PCI device information struct
3911 * @ent: entry in ixgbe_pci_tbl
3912 *
3913 * Returns 0 on success, negative on failure
3914 *
3915 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3916 * The OS initialization, configuring of the adapter private structure,
3917 * and a hardware reset occur.
3918 **/
3919static int __devinit ixgbe_probe(struct pci_dev *pdev,
b4617240 3920 const struct pci_device_id *ent)
9a799d71
AK		 3921{
3922 struct net_device *netdev;
3923 struct ixgbe_adapter *adapter = NULL;
3924 struct ixgbe_hw *hw;
3925 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 3926 static int cards_found;
3927 int i, err, pci_using_dac;
3928 u16 link_status, link_speed, link_width;
c44ade9e 3929 u32 part_num, eec;
9a799d71
AK		 3930
3931 err = pci_enable_device(pdev);
3932 if (err)
3933 return err;
3934
3935 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3936 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3937 pci_using_dac = 1;
3938 } else {
3939 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3940 if (err) {
3941 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3942 if (err) {
b4617240
PW		 3943 dev_err(&pdev->dev, "No usable DMA "
3944 "configuration, aborting\n");
9a799d71
AK		 3945 goto err_dma;
3946 }
3947 }
3948 pci_using_dac = 0;
3949 }
3950
3951 err = pci_request_regions(pdev, ixgbe_driver_name);
3952 if (err) {
3953 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3954 goto err_pci_reg;
3955 }
3956
3957 pci_set_master(pdev);
fb3b27bc 3958 pci_save_state(pdev);
9a799d71 3959
30eba97a 3960 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
9a799d71
AK		 3961 if (!netdev) {
3962 err = -ENOMEM;
3963 goto err_alloc_etherdev;
3964 }
3965
9a799d71
AK		 3966 SET_NETDEV_DEV(netdev, &pdev->dev);
3967
3968 pci_set_drvdata(pdev, netdev);
3969 adapter = netdev_priv(netdev);
3970
3971 adapter->netdev = netdev;
3972 adapter->pdev = pdev;
3973 hw = &adapter->hw;
3974 hw->back = adapter;
3975 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3976
05857980
JK		 3977 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3978 pci_resource_len(pdev, 0));
9a799d71
AK		 3979 if (!hw->hw_addr) {
3980 err = -EIO;
3981 goto err_ioremap;
3982 }
3983
3984 for (i = 1; i <= 5; i++) {
3985 if (pci_resource_len(pdev, i) == 0)
3986 continue;
3987 }
3988
0edc3527 3989 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 3990 ixgbe_set_ethtool_ops(netdev);
9a799d71 3991 netdev->watchdog_timeo = 5 * HZ;
9a799d71
AK		 3992 strcpy(netdev->name, pci_name(pdev));
3993
9a799d71
AK		 3994 adapter->bd_number = cards_found;
3995
9a799d71
AK		 3996 /* Setup hw api */
3997 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 3998 hw->mac.type = ii->mac;
9a799d71 3999
c44ade9e
JB		 4000 /* EEPROM */
4001 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
4002 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
4003 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
4004 if (!(eec & (1 << 8)))
4005 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
4006
4007 /* PHY */
4008 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4009 /* phy->sfp_type = ixgbe_sfp_type_unknown; */
4010
9a799d71
AK		 4011 err = ii->get_invariants(hw);
4012 if (err)
4013 goto err_hw_init;
4014
4015 /* setup the private structure */
4016 err = ixgbe_sw_init(adapter);
4017 if (err)
4018 goto err_sw_init;
4019
c44ade9e
JB		 4020 /* reset_hw fills in the perm_addr as well */
4021 err = hw->mac.ops.reset_hw(hw);
4022 if (err) {
4023 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
4024 goto err_sw_init;
4025 }
4026
9a799d71 4027 netdev->features = NETIF_F_SG |
b4617240
PW		 4028 NETIF_F_IP_CSUM |
4029 NETIF_F_HW_VLAN_TX |
4030 NETIF_F_HW_VLAN_RX |
4031 NETIF_F_HW_VLAN_FILTER;
9a799d71 4032
e9990a9c 4033 netdev->features |= NETIF_F_IPV6_CSUM;
9a799d71 4034 netdev->features |= NETIF_F_TSO;
9a799d71 4035 netdev->features |= NETIF_F_TSO6;
e9990a9c 4036 netdev->features |= NETIF_F_LRO;
ad31c402
JK		 4037
4038 netdev->vlan_features |= NETIF_F_TSO;
4039 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 4040 netdev->vlan_features |= NETIF_F_IP_CSUM;
ad31c402
JK		 4041 netdev->vlan_features |= NETIF_F_SG;
4042
2f90b865
AD		 4043 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
4044 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4045
4046#ifdef CONFIG_IXGBE_DCBNL
4047 netdev->dcbnl_ops = &dcbnl_ops;
4048#endif
4049
9a799d71
AK		 4050 if (pci_using_dac)
4051 netdev->features |= NETIF_F_HIGHDMA;
4052
9a799d71 4053 /* make sure the EEPROM is good */
c44ade9e 4054 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
9a799d71
AK		 4055 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
4056 err = -EIO;
4057 goto err_eeprom;
4058 }
4059
4060 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
4061 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
4062
c44ade9e
JB		 4063 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
4064 dev_err(&pdev->dev, "invalid MAC address\n");
9a799d71
AK		 4065 err = -EIO;
4066 goto err_eeprom;
4067 }
4068
4069 init_timer(&adapter->watchdog_timer);
4070 adapter->watchdog_timer.function = &ixgbe_watchdog;
4071 adapter->watchdog_timer.data = (unsigned long)adapter;
4072
4073 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
cf8280ee 4074 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
9a799d71 4075
021230d4
AV		 4076 err = ixgbe_init_interrupt_scheme(adapter);
4077 if (err)
4078 goto err_sw_init;
9a799d71
AK		 4079
4080 /* print bus type/speed/width info */
4081 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
4082 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
4083 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
7c510e4b 4084 dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
b4617240
PW		 4085 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
4086 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
4087 "Unknown"),
4088 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
4089 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
4090 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
4091 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
4092 "Unknown"),
7c510e4b 4093 netdev->dev_addr);
c44ade9e 4094 ixgbe_read_pba_num_generic(hw, &part_num);
9a799d71 4095 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
b4617240
PW		 4096 hw->mac.type, hw->phy.type,
4097 (part_num >> 8), (part_num & 0xff));
9a799d71 4098
0c254d86
AK		 4099 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
4100 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
b4617240
PW		 4101 "this card is not sufficient for optimal "
4102 "performance.\n");
0c254d86 4103 dev_warn(&pdev->dev, "For optimal performance a x8 "
b4617240 4104 "PCI-Express slot is required.\n");
0c254d86
AK		 4105 }
4106
9a799d71 4107 /* reset the hardware with the new settings */
c44ade9e
JB		 4108 hw->mac.ops.start_hw(hw);
4109
4110 /* link_config depends on start_hw being called at least once */
4111 err = ixgbe_link_config(hw);
4112 if (err) {
4113 dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err);
4114 goto err_register;
4115 }
9a799d71
AK		 4116
4117 netif_carrier_off(netdev);
2f90b865 4118 netif_tx_stop_all_queues(netdev);
9a799d71 4119
021230d4
AV		 4120 ixgbe_napi_add_all(adapter);
4121
9a799d71
AK		 4122 strcpy(netdev->name, "eth%d");
4123 err = register_netdev(netdev);
4124 if (err)
4125 goto err_register;
4126
5dd2d332 4127#ifdef CONFIG_IXGBE_DCA
652f093f 4128 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd
JC		 4129 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
4130 /* always use CB2 mode, difference is masked
4131 * in the CB driver */
4132 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
4133 ixgbe_setup_dca(adapter);
4134 }
4135#endif
9a799d71
AK		 4136
4137 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
4138 cards_found++;
4139 return 0;
4140
4141err_register:
5eba3699 4142 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4143err_hw_init:
4144err_sw_init:
021230d4 4145 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4146err_eeprom:
4147 iounmap(hw->hw_addr);
4148err_ioremap:
4149 free_netdev(netdev);
4150err_alloc_etherdev:
4151 pci_release_regions(pdev);
4152err_pci_reg:
4153err_dma:
4154 pci_disable_device(pdev);
4155 return err;
4156}
4157
4158/**
4159 * ixgbe_remove - Device Removal Routine
4160 * @pdev: PCI device information struct
4161 *
4162 * ixgbe_remove is called by the PCI subsystem to alert the driver
4163 * that it should release a PCI device. The could be caused by a
4164 * Hot-Plug event, or because the driver is going to be removed from
4165 * memory.
4166 **/
4167static void __devexit ixgbe_remove(struct pci_dev *pdev)
4168{
4169 struct net_device *netdev = pci_get_drvdata(pdev);
4170 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4171
4172 set_bit(__IXGBE_DOWN, &adapter->state);
4173 del_timer_sync(&adapter->watchdog_timer);
4174
4175 flush_scheduled_work();
4176
5dd2d332 4177#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4178 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
4179 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
4180 dca_remove_requester(&pdev->dev);
4181 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
4182 }
4183
4184#endif
9a799d71
AK		 4185 unregister_netdev(netdev);
4186
021230d4 4187 ixgbe_reset_interrupt_capability(adapter);
5eba3699 4188
021230d4 4189 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4190
4191 iounmap(adapter->hw.hw_addr);
4192 pci_release_regions(pdev);
4193
021230d4 4194 DPRINTK(PROBE, INFO, "complete\n");
b3c8b4ba 4195 ixgbe_napi_del_all(adapter);
021230d4
AV		 4196 kfree(adapter->tx_ring);
4197 kfree(adapter->rx_ring);
4198
9a799d71
AK		 4199 free_netdev(netdev);
4200
4201 pci_disable_device(pdev);
4202}
4203
4204/**
4205 * ixgbe_io_error_detected - called when PCI error is detected
4206 * @pdev: Pointer to PCI device
4207 * @state: The current pci connection state
4208 *
4209 * This function is called after a PCI bus error affecting
4210 * this device has been detected.
4211 */
4212static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
b4617240 4213 pci_channel_state_t state)
9a799d71
AK		 4214{
4215 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4217
4218 netif_device_detach(netdev);
4219
4220 if (netif_running(netdev))
4221 ixgbe_down(adapter);
4222 pci_disable_device(pdev);
4223
b4617240 4224 /* Request a slot reset. */
9a799d71
AK		 4225 return PCI_ERS_RESULT_NEED_RESET;
4226}
4227
4228/**
4229 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4230 * @pdev: Pointer to PCI device
4231 *
4232 * Restart the card from scratch, as if from a cold-boot.
4233 */
4234static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4235{
4236 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4237 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4238
4239 if (pci_enable_device(pdev)) {
4240 DPRINTK(PROBE, ERR,
b4617240 4241 "Cannot re-enable PCI device after reset.\n");
9a799d71
AK		 4242 return PCI_ERS_RESULT_DISCONNECT;
4243 }
4244 pci_set_master(pdev);
fb3b27bc 4245 pci_restore_state(pdev);
9a799d71
AK		 4246
4247 pci_enable_wake(pdev, PCI_D3hot, 0);
4248 pci_enable_wake(pdev, PCI_D3cold, 0);
4249
4250 ixgbe_reset(adapter);
4251
4252 return PCI_ERS_RESULT_RECOVERED;
4253}
4254
4255/**
4256 * ixgbe_io_resume - called when traffic can start flowing again.
4257 * @pdev: Pointer to PCI device
4258 *
4259 * This callback is called when the error recovery driver tells us that
4260 * its OK to resume normal operation.
4261 */
4262static void ixgbe_io_resume(struct pci_dev *pdev)
4263{
4264 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 4265 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4266
4267 if (netif_running(netdev)) {
4268 if (ixgbe_up(adapter)) {
4269 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4270 return;
4271 }
4272 }
4273
4274 netif_device_attach(netdev);
9a799d71
AK		 4275}
4276
4277static struct pci_error_handlers ixgbe_err_handler = {
4278 .error_detected = ixgbe_io_error_detected,
4279 .slot_reset = ixgbe_io_slot_reset,
4280 .resume = ixgbe_io_resume,
4281};
4282
4283static struct pci_driver ixgbe_driver = {
4284 .name = ixgbe_driver_name,
4285 .id_table = ixgbe_pci_tbl,
4286 .probe = ixgbe_probe,
4287 .remove = __devexit_p(ixgbe_remove),
4288#ifdef CONFIG_PM
4289 .suspend = ixgbe_suspend,
4290 .resume = ixgbe_resume,
4291#endif
4292 .shutdown = ixgbe_shutdown,
4293 .err_handler = &ixgbe_err_handler
4294};
4295
4296/**
4297 * ixgbe_init_module - Driver Registration Routine
4298 *
4299 * ixgbe_init_module is the first routine called when the driver is
4300 * loaded. All it does is register with the PCI subsystem.
4301 **/
4302static int __init ixgbe_init_module(void)
4303{
4304 int ret;
4305 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4306 ixgbe_driver_string, ixgbe_driver_version);
4307
4308 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4309
5dd2d332 4310#ifdef CONFIG_IXGBE_DCA
bd0362dd 4311 dca_register_notify(&dca_notifier);
bd0362dd 4312#endif
5dd2d332 4313
9a799d71
AK		 4314 ret = pci_register_driver(&ixgbe_driver);
4315 return ret;
4316}
b4617240 4317
9a799d71
AK		 4318module_init(ixgbe_init_module);
4319
4320/**
4321 * ixgbe_exit_module - Driver Exit Cleanup Routine
4322 *
4323 * ixgbe_exit_module is called just before the driver is removed
4324 * from memory.
4325 **/
4326static void __exit ixgbe_exit_module(void)
4327{
5dd2d332 4328#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 4329 dca_unregister_notify(&dca_notifier);
4330#endif
9a799d71
AK		 4331 pci_unregister_driver(&ixgbe_driver);
4332}
bd0362dd 4333
5dd2d332 4334#ifdef CONFIG_IXGBE_DCA
bd0362dd 4335static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
b4617240 4336 void *p)
bd0362dd
JC		 4337{
4338 int ret_val;
4339
4340 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
b4617240 4341 __ixgbe_notify_dca);
bd0362dd
JC		 4342
4343 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4344}
5dd2d332 4345#endif /* CONFIG_IXGBE_DCA */
bd0362dd 4346
9a799d71
AK		 4347module_exit(ixgbe_exit_module);
4348
4349/* ixgbe_main.c */
Linux kernel - Deliverables
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