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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
3efac5a0 | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/tcp.h> | |
37 | #include <linux/ipv6.h> | |
38 | #include <net/checksum.h> | |
39 | #include <net/ip6_checksum.h> | |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/if_vlan.h> | |
eacd73f7 | 42 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
43 | |
44 | #include "ixgbe.h" | |
45 | #include "ixgbe_common.h" | |
46 | ||
47 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 48 | static const char ixgbe_driver_string[] = |
b4617240 | 49 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
9a799d71 | 50 | |
a1c1db39 | 51 | #define DRV_VERSION "2.0.34-k2" |
9c8eb720 | 52 | const char ixgbe_driver_version[] = DRV_VERSION; |
3efac5a0 | 53 | static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation."; |
9a799d71 AK |
54 | |
55 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 56 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 57 | [board_82599] = &ixgbe_82599_info, |
9a799d71 AK |
58 | }; |
59 | ||
60 | /* ixgbe_pci_tbl - PCI Device ID Table | |
61 | * | |
62 | * Wildcard entries (PCI_ANY_ID) should come last | |
63 | * Last entry must be all 0s | |
64 | * | |
65 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
66 | * Class, Class Mask, private data (not used) } | |
67 | */ | |
68 | static struct pci_device_id ixgbe_pci_tbl[] = { | |
1e336d0f DS |
69 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), |
70 | board_82598 }, | |
9a799d71 | 71 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), |
3957d63d | 72 | board_82598 }, |
9a799d71 | 73 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), |
3957d63d | 74 | board_82598 }, |
0befdb3e JB |
75 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), |
76 | board_82598 }, | |
9a799d71 | 77 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), |
3957d63d | 78 | board_82598 }, |
8d792cd9 JB |
79 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), |
80 | board_82598 }, | |
c4900be0 DS |
81 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), |
82 | board_82598 }, | |
83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), | |
84 | board_82598 }, | |
b95f5fcb JB |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), |
86 | board_82598 }, | |
c4900be0 DS |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), |
88 | board_82598 }, | |
2f21bdd3 DS |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), |
90 | board_82598 }, | |
e8e26350 PW |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), |
92 | board_82599 }, | |
1fcf03e6 PWJ |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), |
94 | board_82599 }, | |
e8e26350 PW |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), |
96 | board_82599 }, | |
9a799d71 AK |
97 | |
98 | /* required last entry */ | |
99 | {0, } | |
100 | }; | |
101 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
102 | ||
5dd2d332 | 103 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 104 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
b4617240 | 105 | void *p); |
bd0362dd JC |
106 | static struct notifier_block dca_notifier = { |
107 | .notifier_call = ixgbe_notify_dca, | |
108 | .next = NULL, | |
109 | .priority = 0 | |
110 | }; | |
111 | #endif | |
112 | ||
9a799d71 AK |
113 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
114 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
115 | MODULE_LICENSE("GPL"); | |
116 | MODULE_VERSION(DRV_VERSION); | |
117 | ||
118 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
119 | ||
5eba3699 AV |
120 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
121 | { | |
122 | u32 ctrl_ext; | |
123 | ||
124 | /* Let firmware take over control of h/w */ | |
125 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
126 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 127 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
128 | } |
129 | ||
130 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
131 | { | |
132 | u32 ctrl_ext; | |
133 | ||
134 | /* Let firmware know the driver has taken over */ | |
135 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
136 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
b4617240 | 137 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 138 | } |
9a799d71 | 139 | |
e8e26350 PW |
140 | /* |
141 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
142 | * @adapter: pointer to adapter struct | |
143 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
144 | * @queue: queue to map the corresponding interrupt to | |
145 | * @msix_vector: the vector to map to the corresponding queue | |
146 | * | |
147 | */ | |
148 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
149 | u8 queue, u8 msix_vector) | |
9a799d71 AK |
150 | { |
151 | u32 ivar, index; | |
e8e26350 PW |
152 | struct ixgbe_hw *hw = &adapter->hw; |
153 | switch (hw->mac.type) { | |
154 | case ixgbe_mac_82598EB: | |
155 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
156 | if (direction == -1) | |
157 | direction = 0; | |
158 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
159 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
160 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
161 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
162 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
163 | break; | |
164 | case ixgbe_mac_82599EB: | |
165 | if (direction == -1) { | |
166 | /* other causes */ | |
167 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
168 | index = ((queue & 1) * 8); | |
169 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
170 | ivar &= ~(0xFF << index); | |
171 | ivar |= (msix_vector << index); | |
172 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
173 | break; | |
174 | } else { | |
175 | /* tx or rx causes */ | |
176 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
177 | index = ((16 * (queue & 1)) + (8 * direction)); | |
178 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
179 | ivar &= ~(0xFF << index); | |
180 | ivar |= (msix_vector << index); | |
181 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
182 | break; | |
183 | } | |
184 | default: | |
185 | break; | |
186 | } | |
9a799d71 AK |
187 | } |
188 | ||
fe49f04a AD |
189 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
190 | u64 qmask) | |
191 | { | |
192 | u32 mask; | |
193 | ||
194 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
195 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
196 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
197 | } else { | |
198 | mask = (qmask & 0xFFFFFFFF); | |
199 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
200 | mask = (qmask >> 32); | |
201 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
202 | } | |
203 | } | |
204 | ||
9a799d71 | 205 | static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter, |
b4617240 PW |
206 | struct ixgbe_tx_buffer |
207 | *tx_buffer_info) | |
9a799d71 | 208 | { |
44df32c5 | 209 | tx_buffer_info->dma = 0; |
9a799d71 | 210 | if (tx_buffer_info->skb) { |
44df32c5 AD |
211 | skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb, |
212 | DMA_TO_DEVICE); | |
9a799d71 AK |
213 | dev_kfree_skb_any(tx_buffer_info->skb); |
214 | tx_buffer_info->skb = NULL; | |
215 | } | |
44df32c5 | 216 | tx_buffer_info->time_stamp = 0; |
9a799d71 AK |
217 | /* tx_buffer_info must be completely set up in the transmit path */ |
218 | } | |
219 | ||
220 | static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter, | |
b4617240 PW |
221 | struct ixgbe_ring *tx_ring, |
222 | unsigned int eop) | |
9a799d71 | 223 | { |
e01c31a5 | 224 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 225 | |
9a799d71 | 226 | /* Detect a transmit hang in hardware, this serializes the |
e01c31a5 | 227 | * check with the clearing of time_stamp and movement of eop */ |
9a799d71 | 228 | adapter->detect_tx_hung = false; |
44df32c5 | 229 | if (tx_ring->tx_buffer_info[eop].time_stamp && |
9a799d71 AK |
230 | time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) && |
231 | !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) { | |
232 | /* detected Tx unit hang */ | |
e01c31a5 JB |
233 | union ixgbe_adv_tx_desc *tx_desc; |
234 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
9a799d71 | 235 | DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n" |
e01c31a5 JB |
236 | " Tx Queue <%d>\n" |
237 | " TDH, TDT <%x>, <%x>\n" | |
9a799d71 AK |
238 | " next_to_use <%x>\n" |
239 | " next_to_clean <%x>\n" | |
240 | "tx_buffer_info[next_to_clean]\n" | |
241 | " time_stamp <%lx>\n" | |
e01c31a5 JB |
242 | " jiffies <%lx>\n", |
243 | tx_ring->queue_index, | |
44df32c5 AD |
244 | IXGBE_READ_REG(hw, tx_ring->head), |
245 | IXGBE_READ_REG(hw, tx_ring->tail), | |
e01c31a5 JB |
246 | tx_ring->next_to_use, eop, |
247 | tx_ring->tx_buffer_info[eop].time_stamp, jiffies); | |
9a799d71 AK |
248 | return true; |
249 | } | |
250 | ||
251 | return false; | |
252 | } | |
253 | ||
b4617240 PW |
254 | #define IXGBE_MAX_TXD_PWR 14 |
255 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
e092be60 AV |
256 | |
257 | /* Tx Descriptors needed, worst case */ | |
258 | #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \ | |
259 | (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0)) | |
260 | #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \ | |
b4617240 | 261 | MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */ |
e092be60 | 262 | |
e01c31a5 JB |
263 | static void ixgbe_tx_timeout(struct net_device *netdev); |
264 | ||
9a799d71 AK |
265 | /** |
266 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 267 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 268 | * @tx_ring: tx ring to clean |
9a799d71 | 269 | **/ |
fe49f04a | 270 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e01c31a5 | 271 | struct ixgbe_ring *tx_ring) |
9a799d71 | 272 | { |
fe49f04a | 273 | struct ixgbe_adapter *adapter = q_vector->adapter; |
e01c31a5 | 274 | struct net_device *netdev = adapter->netdev; |
12207e49 PWJ |
275 | union ixgbe_adv_tx_desc *tx_desc, *eop_desc; |
276 | struct ixgbe_tx_buffer *tx_buffer_info; | |
277 | unsigned int i, eop, count = 0; | |
e01c31a5 | 278 | unsigned int total_bytes = 0, total_packets = 0; |
9a799d71 AK |
279 | |
280 | i = tx_ring->next_to_clean; | |
12207e49 PWJ |
281 | eop = tx_ring->tx_buffer_info[i].next_to_watch; |
282 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
283 | ||
284 | while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) && | |
9a1a69ad | 285 | (count < tx_ring->work_limit)) { |
12207e49 PWJ |
286 | bool cleaned = false; |
287 | for ( ; !cleaned; count++) { | |
288 | struct sk_buff *skb; | |
9a799d71 AK |
289 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); |
290 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
12207e49 | 291 | cleaned = (i == eop); |
e01c31a5 | 292 | skb = tx_buffer_info->skb; |
9a799d71 | 293 | |
12207e49 | 294 | if (cleaned && skb) { |
e092be60 | 295 | unsigned int segs, bytecount; |
3d8fd385 | 296 | unsigned int hlen = skb_headlen(skb); |
e01c31a5 JB |
297 | |
298 | /* gso_segs is currently only valid for tcp */ | |
e092be60 | 299 | segs = skb_shinfo(skb)->gso_segs ?: 1; |
3d8fd385 YZ |
300 | #ifdef IXGBE_FCOE |
301 | /* adjust for FCoE Sequence Offload */ | |
302 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
303 | && (skb->protocol == htons(ETH_P_FCOE)) && | |
304 | skb_is_gso(skb)) { | |
305 | hlen = skb_transport_offset(skb) + | |
306 | sizeof(struct fc_frame_header) + | |
307 | sizeof(struct fcoe_crc_eof); | |
308 | segs = DIV_ROUND_UP(skb->len - hlen, | |
309 | skb_shinfo(skb)->gso_size); | |
310 | } | |
311 | #endif /* IXGBE_FCOE */ | |
e092be60 | 312 | /* multiply data chunks by size of headers */ |
3d8fd385 | 313 | bytecount = ((segs - 1) * hlen) + skb->len; |
e01c31a5 JB |
314 | total_packets += segs; |
315 | total_bytes += bytecount; | |
e092be60 | 316 | } |
e01c31a5 | 317 | |
9a799d71 | 318 | ixgbe_unmap_and_free_tx_resource(adapter, |
e01c31a5 | 319 | tx_buffer_info); |
9a799d71 | 320 | |
12207e49 PWJ |
321 | tx_desc->wb.status = 0; |
322 | ||
9a799d71 AK |
323 | i++; |
324 | if (i == tx_ring->count) | |
325 | i = 0; | |
e01c31a5 | 326 | } |
12207e49 PWJ |
327 | |
328 | eop = tx_ring->tx_buffer_info[i].next_to_watch; | |
329 | eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop); | |
330 | } | |
331 | ||
9a799d71 AK |
332 | tx_ring->next_to_clean = i; |
333 | ||
e092be60 | 334 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
e01c31a5 JB |
335 | if (unlikely(count && netif_carrier_ok(netdev) && |
336 | (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
e092be60 AV |
337 | /* Make sure that anybody stopping the queue after this |
338 | * sees the new next_to_clean. | |
339 | */ | |
340 | smp_mb(); | |
30eba97a AV |
341 | if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) && |
342 | !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
343 | netif_wake_subqueue(netdev, tx_ring->queue_index); | |
e01c31a5 | 344 | ++adapter->restart_queue; |
30eba97a | 345 | } |
e092be60 | 346 | } |
9a799d71 | 347 | |
e01c31a5 JB |
348 | if (adapter->detect_tx_hung) { |
349 | if (ixgbe_check_tx_hang(adapter, tx_ring, i)) { | |
350 | /* schedule immediate reset if we believe we hung */ | |
351 | DPRINTK(PROBE, INFO, | |
352 | "tx hang %d detected, resetting adapter\n", | |
353 | adapter->tx_timeout_count + 1); | |
354 | ixgbe_tx_timeout(adapter->netdev); | |
355 | } | |
356 | } | |
9a799d71 | 357 | |
e01c31a5 | 358 | /* re-arm the interrupt */ |
fe49f04a AD |
359 | if (count >= tx_ring->work_limit) |
360 | ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
9a799d71 | 361 | |
e01c31a5 JB |
362 | tx_ring->total_bytes += total_bytes; |
363 | tx_ring->total_packets += total_packets; | |
e01c31a5 | 364 | tx_ring->stats.packets += total_packets; |
12207e49 | 365 | tx_ring->stats.bytes += total_bytes; |
e01c31a5 JB |
366 | adapter->net_stats.tx_bytes += total_bytes; |
367 | adapter->net_stats.tx_packets += total_packets; | |
9a1a69ad | 368 | return (count < tx_ring->work_limit); |
9a799d71 AK |
369 | } |
370 | ||
5dd2d332 | 371 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 372 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
b4617240 | 373 | struct ixgbe_ring *rx_ring) |
bd0362dd JC |
374 | { |
375 | u32 rxctrl; | |
376 | int cpu = get_cpu(); | |
3a581073 | 377 | int q = rx_ring - adapter->rx_ring; |
bd0362dd | 378 | |
3a581073 | 379 | if (rx_ring->cpu != cpu) { |
bd0362dd | 380 | rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q)); |
e8e26350 PW |
381 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
382 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
383 | rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
384 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
385 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; | |
386 | rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
387 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); | |
388 | } | |
bd0362dd JC |
389 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
390 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
15005a32 DS |
391 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); |
392 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN | | |
e8e26350 | 393 | IXGBE_DCA_RXCTRL_DESC_HSRO_EN); |
bd0362dd | 394 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl); |
3a581073 | 395 | rx_ring->cpu = cpu; |
bd0362dd JC |
396 | } |
397 | put_cpu(); | |
398 | } | |
399 | ||
400 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
b4617240 | 401 | struct ixgbe_ring *tx_ring) |
bd0362dd JC |
402 | { |
403 | u32 txctrl; | |
404 | int cpu = get_cpu(); | |
3a581073 | 405 | int q = tx_ring - adapter->tx_ring; |
bd0362dd | 406 | |
3a581073 | 407 | if (tx_ring->cpu != cpu) { |
bd0362dd | 408 | txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q)); |
e8e26350 PW |
409 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
410 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
411 | txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
412 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
413 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; | |
414 | txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) << | |
415 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); | |
416 | } | |
bd0362dd JC |
417 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
418 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl); | |
3a581073 | 419 | tx_ring->cpu = cpu; |
bd0362dd JC |
420 | } |
421 | put_cpu(); | |
422 | } | |
423 | ||
424 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
425 | { | |
426 | int i; | |
427 | ||
428 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
429 | return; | |
430 | ||
e35ec126 AD |
431 | /* always use CB2 mode, difference is masked in the CB driver */ |
432 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
433 | ||
bd0362dd JC |
434 | for (i = 0; i < adapter->num_tx_queues; i++) { |
435 | adapter->tx_ring[i].cpu = -1; | |
436 | ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]); | |
437 | } | |
438 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
439 | adapter->rx_ring[i].cpu = -1; | |
440 | ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]); | |
441 | } | |
442 | } | |
443 | ||
444 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
445 | { | |
446 | struct net_device *netdev = dev_get_drvdata(dev); | |
447 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
448 | unsigned long event = *(unsigned long *)data; | |
449 | ||
450 | switch (event) { | |
451 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
452 | /* if we're already enabled, don't do it again */ |
453 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
454 | break; | |
652f093f | 455 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 456 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
457 | ixgbe_setup_dca(adapter); |
458 | break; | |
459 | } | |
460 | /* Fall Through since DCA is disabled. */ | |
461 | case DCA_PROVIDER_REMOVE: | |
462 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
463 | dca_remove_requester(dev); | |
464 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
465 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
466 | } | |
467 | break; | |
468 | } | |
469 | ||
652f093f | 470 | return 0; |
bd0362dd JC |
471 | } |
472 | ||
5dd2d332 | 473 | #endif /* CONFIG_IXGBE_DCA */ |
9a799d71 AK |
474 | /** |
475 | * ixgbe_receive_skb - Send a completed packet up the stack | |
476 | * @adapter: board private structure | |
477 | * @skb: packet to send up | |
177db6ff MC |
478 | * @status: hardware indication of status of receive |
479 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
480 | * @rx_desc: rx descriptor | |
9a799d71 | 481 | **/ |
78b6f4ce | 482 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
b4617240 | 483 | struct sk_buff *skb, u8 status, |
fdaff1ce | 484 | struct ixgbe_ring *ring, |
177db6ff | 485 | union ixgbe_adv_rx_desc *rx_desc) |
9a799d71 | 486 | { |
78b6f4ce HX |
487 | struct ixgbe_adapter *adapter = q_vector->adapter; |
488 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
489 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
490 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 491 | |
fdaff1ce | 492 | skb_record_rx_queue(skb, ring->queue_index); |
182ff8df | 493 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) { |
2f90b865 | 494 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
78b6f4ce | 495 | vlan_gro_receive(napi, adapter->vlgrp, tag, skb); |
9a799d71 | 496 | else |
78b6f4ce | 497 | napi_gro_receive(napi, skb); |
177db6ff | 498 | } else { |
182ff8df AD |
499 | if (adapter->vlgrp && is_vlan && (tag != 0)) |
500 | vlan_hwaccel_rx(skb, adapter->vlgrp, tag); | |
501 | else | |
502 | netif_rx(skb); | |
9a799d71 AK |
503 | } |
504 | } | |
505 | ||
e59bd25d AV |
506 | /** |
507 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
508 | * @adapter: address of board private structure | |
509 | * @status_err: hardware indication of status of receive | |
510 | * @skb: skb currently being received and modified | |
511 | **/ | |
9a799d71 | 512 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
712744be | 513 | u32 status_err, struct sk_buff *skb) |
9a799d71 AK |
514 | { |
515 | skb->ip_summed = CHECKSUM_NONE; | |
516 | ||
712744be JB |
517 | /* Rx csum disabled */ |
518 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 519 | return; |
e59bd25d AV |
520 | |
521 | /* if IP and error */ | |
522 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
523 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
524 | adapter->hw_csum_rx_error++; |
525 | return; | |
526 | } | |
e59bd25d AV |
527 | |
528 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
529 | return; | |
530 | ||
531 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
532 | adapter->hw_csum_rx_error++; | |
533 | return; | |
534 | } | |
535 | ||
9a799d71 | 536 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 537 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
538 | adapter->hw_csum_rx_good++; |
539 | } | |
540 | ||
e8e26350 PW |
541 | static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw, |
542 | struct ixgbe_ring *rx_ring, u32 val) | |
543 | { | |
544 | /* | |
545 | * Force memory writes to complete before letting h/w | |
546 | * know there are new descriptors to fetch. (Only | |
547 | * applicable for weak-ordered memory model archs, | |
548 | * such as IA-64). | |
549 | */ | |
550 | wmb(); | |
551 | IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val); | |
552 | } | |
553 | ||
9a799d71 AK |
554 | /** |
555 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
556 | * @adapter: address of board private structure | |
557 | **/ | |
558 | static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter, | |
7c6e0a43 JB |
559 | struct ixgbe_ring *rx_ring, |
560 | int cleaned_count) | |
9a799d71 | 561 | { |
9a799d71 AK |
562 | struct pci_dev *pdev = adapter->pdev; |
563 | union ixgbe_adv_rx_desc *rx_desc; | |
3a581073 | 564 | struct ixgbe_rx_buffer *bi; |
9a799d71 | 565 | unsigned int i; |
e8e26350 | 566 | unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN; |
9a799d71 AK |
567 | |
568 | i = rx_ring->next_to_use; | |
3a581073 | 569 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
570 | |
571 | while (cleaned_count--) { | |
572 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
573 | ||
762f4c57 | 574 | if (!bi->page_dma && |
3a581073 | 575 | (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) { |
3a581073 | 576 | if (!bi->page) { |
762f4c57 JB |
577 | bi->page = alloc_page(GFP_ATOMIC); |
578 | if (!bi->page) { | |
579 | adapter->alloc_rx_page_failed++; | |
580 | goto no_buffers; | |
581 | } | |
582 | bi->page_offset = 0; | |
583 | } else { | |
584 | /* use a half page if we're re-using */ | |
585 | bi->page_offset ^= (PAGE_SIZE / 2); | |
9a799d71 | 586 | } |
762f4c57 JB |
587 | |
588 | bi->page_dma = pci_map_page(pdev, bi->page, | |
589 | bi->page_offset, | |
590 | (PAGE_SIZE / 2), | |
591 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
592 | } |
593 | ||
3a581073 | 594 | if (!bi->skb) { |
5ecc3614 | 595 | struct sk_buff *skb; |
e8e26350 | 596 | skb = netdev_alloc_skb(adapter->netdev, bufsz); |
9a799d71 AK |
597 | |
598 | if (!skb) { | |
599 | adapter->alloc_rx_buff_failed++; | |
600 | goto no_buffers; | |
601 | } | |
602 | ||
603 | /* | |
604 | * Make buffer alignment 2 beyond a 16 byte boundary | |
605 | * this will result in a 16 byte aligned IP header after | |
606 | * the 14 byte MAC header is removed | |
607 | */ | |
608 | skb_reserve(skb, NET_IP_ALIGN); | |
609 | ||
3a581073 | 610 | bi->skb = skb; |
e8e26350 | 611 | bi->dma = pci_map_single(pdev, skb->data, bufsz, |
3a581073 | 612 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
613 | } |
614 | /* Refresh the desc even if buffer_addrs didn't change because | |
615 | * each write-back erases this info. */ | |
616 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
3a581073 JB |
617 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
618 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 619 | } else { |
3a581073 | 620 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
9a799d71 AK |
621 | } |
622 | ||
623 | i++; | |
624 | if (i == rx_ring->count) | |
625 | i = 0; | |
3a581073 | 626 | bi = &rx_ring->rx_buffer_info[i]; |
9a799d71 | 627 | } |
7c6e0a43 | 628 | |
9a799d71 AK |
629 | no_buffers: |
630 | if (rx_ring->next_to_use != i) { | |
631 | rx_ring->next_to_use = i; | |
632 | if (i-- == 0) | |
633 | i = (rx_ring->count - 1); | |
634 | ||
e8e26350 | 635 | ixgbe_release_rx_desc(&adapter->hw, rx_ring, i); |
9a799d71 AK |
636 | } |
637 | } | |
638 | ||
7c6e0a43 JB |
639 | static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc) |
640 | { | |
641 | return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
642 | } | |
643 | ||
644 | static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc) | |
645 | { | |
646 | return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
647 | } | |
648 | ||
f8212f97 AD |
649 | static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc) |
650 | { | |
651 | return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
652 | IXGBE_RXDADV_RSCCNT_MASK) >> | |
653 | IXGBE_RXDADV_RSCCNT_SHIFT; | |
654 | } | |
655 | ||
656 | /** | |
657 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
658 | * @skb: pointer to the last skb in the rsc queue | |
659 | * | |
660 | * This function changes a queue full of hw rsc buffers into a completed | |
661 | * packet. It uses the ->prev pointers to find the first packet and then | |
662 | * turns it into the frag list owner. | |
663 | **/ | |
664 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb) | |
665 | { | |
666 | unsigned int frag_list_size = 0; | |
667 | ||
668 | while (skb->prev) { | |
669 | struct sk_buff *prev = skb->prev; | |
670 | frag_list_size += skb->len; | |
671 | skb->prev = NULL; | |
672 | skb = prev; | |
673 | } | |
674 | ||
675 | skb_shinfo(skb)->frag_list = skb->next; | |
676 | skb->next = NULL; | |
677 | skb->len += frag_list_size; | |
678 | skb->data_len += frag_list_size; | |
679 | skb->truesize += frag_list_size; | |
680 | return skb; | |
681 | } | |
682 | ||
78b6f4ce | 683 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
b4617240 PW |
684 | struct ixgbe_ring *rx_ring, |
685 | int *work_done, int work_to_do) | |
9a799d71 | 686 | { |
78b6f4ce | 687 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
688 | struct pci_dev *pdev = adapter->pdev; |
689 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; | |
690 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
691 | struct sk_buff *skb; | |
f8212f97 | 692 | unsigned int i, rsc_count = 0; |
7c6e0a43 | 693 | u32 len, staterr; |
177db6ff MC |
694 | u16 hdr_info; |
695 | bool cleaned = false; | |
9a799d71 | 696 | int cleaned_count = 0; |
d2f4fbe2 | 697 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3d8fd385 YZ |
698 | #ifdef IXGBE_FCOE |
699 | int ddp_bytes = 0; | |
700 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
701 | |
702 | i = rx_ring->next_to_clean; | |
9a799d71 AK |
703 | rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i); |
704 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
705 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
9a799d71 AK |
706 | |
707 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 708 | u32 upper_len = 0; |
9a799d71 AK |
709 | if (*work_done >= work_to_do) |
710 | break; | |
711 | (*work_done)++; | |
712 | ||
713 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 JB |
714 | hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc)); |
715 | len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
762f4c57 | 716 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; |
9a799d71 AK |
717 | if (hdr_info & IXGBE_RXDADV_SPH) |
718 | adapter->rx_hdr_split++; | |
719 | if (len > IXGBE_RX_HDR_SIZE) | |
720 | len = IXGBE_RX_HDR_SIZE; | |
721 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
7c6e0a43 | 722 | } else { |
9a799d71 | 723 | len = le16_to_cpu(rx_desc->wb.upper.length); |
7c6e0a43 | 724 | } |
9a799d71 AK |
725 | |
726 | cleaned = true; | |
727 | skb = rx_buffer_info->skb; | |
728 | prefetch(skb->data - NET_IP_ALIGN); | |
729 | rx_buffer_info->skb = NULL; | |
730 | ||
21fa4e66 | 731 | if (rx_buffer_info->dma) { |
9a799d71 | 732 | pci_unmap_single(pdev, rx_buffer_info->dma, |
5ecc3614 | 733 | rx_ring->rx_buf_len, |
b4617240 | 734 | PCI_DMA_FROMDEVICE); |
9a799d71 AK |
735 | skb_put(skb, len); |
736 | } | |
737 | ||
738 | if (upper_len) { | |
739 | pci_unmap_page(pdev, rx_buffer_info->page_dma, | |
762f4c57 | 740 | PAGE_SIZE / 2, PCI_DMA_FROMDEVICE); |
9a799d71 AK |
741 | rx_buffer_info->page_dma = 0; |
742 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
762f4c57 JB |
743 | rx_buffer_info->page, |
744 | rx_buffer_info->page_offset, | |
745 | upper_len); | |
746 | ||
747 | if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) || | |
748 | (page_count(rx_buffer_info->page) != 1)) | |
749 | rx_buffer_info->page = NULL; | |
750 | else | |
751 | get_page(rx_buffer_info->page); | |
9a799d71 AK |
752 | |
753 | skb->len += upper_len; | |
754 | skb->data_len += upper_len; | |
755 | skb->truesize += upper_len; | |
756 | } | |
757 | ||
758 | i++; | |
759 | if (i == rx_ring->count) | |
760 | i = 0; | |
9a799d71 AK |
761 | |
762 | next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i); | |
763 | prefetch(next_rxd); | |
9a799d71 | 764 | cleaned_count++; |
f8212f97 | 765 | |
df647b5c | 766 | if (adapter->flags & IXGBE_FLAG2_RSC_CAPABLE) |
f8212f97 AD |
767 | rsc_count = ixgbe_get_rsc_count(rx_desc); |
768 | ||
769 | if (rsc_count) { | |
770 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> | |
771 | IXGBE_RXDADV_NEXTP_SHIFT; | |
772 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
773 | rx_ring->rsc_count += (rsc_count - 1); | |
774 | } else { | |
775 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
776 | } | |
777 | ||
9a799d71 | 778 | if (staterr & IXGBE_RXD_STAT_EOP) { |
f8212f97 AD |
779 | if (skb->prev) |
780 | skb = ixgbe_transform_rsc_queue(skb); | |
9a799d71 AK |
781 | rx_ring->stats.packets++; |
782 | rx_ring->stats.bytes += skb->len; | |
783 | } else { | |
f8212f97 AD |
784 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
785 | rx_buffer_info->skb = next_buffer->skb; | |
786 | rx_buffer_info->dma = next_buffer->dma; | |
787 | next_buffer->skb = skb; | |
788 | next_buffer->dma = 0; | |
789 | } else { | |
790 | skb->next = next_buffer->skb; | |
791 | skb->next->prev = skb; | |
792 | } | |
9a799d71 AK |
793 | adapter->non_eop_descs++; |
794 | goto next_desc; | |
795 | } | |
796 | ||
797 | if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) { | |
798 | dev_kfree_skb_irq(skb); | |
799 | goto next_desc; | |
800 | } | |
801 | ||
802 | ixgbe_rx_checksum(adapter, staterr, skb); | |
d2f4fbe2 AV |
803 | |
804 | /* probably a little skewed due to removing CRC */ | |
805 | total_rx_bytes += skb->len; | |
806 | total_rx_packets++; | |
807 | ||
74ce8dd2 | 808 | skb->protocol = eth_type_trans(skb, adapter->netdev); |
332d4a7d YZ |
809 | #ifdef IXGBE_FCOE |
810 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
3d8fd385 YZ |
811 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
812 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); | |
813 | if (!ddp_bytes) | |
332d4a7d | 814 | goto next_desc; |
3d8fd385 | 815 | } |
332d4a7d | 816 | #endif /* IXGBE_FCOE */ |
fdaff1ce | 817 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 AK |
818 | |
819 | next_desc: | |
820 | rx_desc->wb.upper.status_error = 0; | |
821 | ||
822 | /* return some buffers to hardware, one at a time is too slow */ | |
823 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
824 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
825 | cleaned_count = 0; | |
826 | } | |
827 | ||
828 | /* use prefetched values */ | |
829 | rx_desc = next_rxd; | |
f8212f97 | 830 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
9a799d71 AK |
831 | |
832 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
177db6ff MC |
833 | } |
834 | ||
9a799d71 AK |
835 | rx_ring->next_to_clean = i; |
836 | cleaned_count = IXGBE_DESC_UNUSED(rx_ring); | |
837 | ||
838 | if (cleaned_count) | |
839 | ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); | |
840 | ||
3d8fd385 YZ |
841 | #ifdef IXGBE_FCOE |
842 | /* include DDPed FCoE data */ | |
843 | if (ddp_bytes > 0) { | |
844 | unsigned int mss; | |
845 | ||
846 | mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) - | |
847 | sizeof(struct fc_frame_header) - | |
848 | sizeof(struct fcoe_crc_eof); | |
849 | if (mss > 512) | |
850 | mss &= ~511; | |
851 | total_rx_bytes += ddp_bytes; | |
852 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
853 | } | |
854 | #endif /* IXGBE_FCOE */ | |
855 | ||
f494e8fa AV |
856 | rx_ring->total_packets += total_rx_packets; |
857 | rx_ring->total_bytes += total_rx_bytes; | |
858 | adapter->net_stats.rx_bytes += total_rx_bytes; | |
859 | adapter->net_stats.rx_packets += total_rx_packets; | |
860 | ||
9a799d71 AK |
861 | return cleaned; |
862 | } | |
863 | ||
021230d4 | 864 | static int ixgbe_clean_rxonly(struct napi_struct *, int); |
9a799d71 AK |
865 | /** |
866 | * ixgbe_configure_msix - Configure MSI-X hardware | |
867 | * @adapter: board private structure | |
868 | * | |
869 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
870 | * interrupts. | |
871 | **/ | |
872 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
873 | { | |
021230d4 AV |
874 | struct ixgbe_q_vector *q_vector; |
875 | int i, j, q_vectors, v_idx, r_idx; | |
876 | u32 mask; | |
9a799d71 | 877 | |
021230d4 | 878 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 879 | |
4df10466 JB |
880 | /* |
881 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
882 | * corresponding register. |
883 | */ | |
884 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
7a921c93 | 885 | q_vector = adapter->q_vector[v_idx]; |
021230d4 AV |
886 | /* XXX for_each_bit(...) */ |
887 | r_idx = find_first_bit(q_vector->rxr_idx, | |
b4617240 | 888 | adapter->num_rx_queues); |
021230d4 AV |
889 | |
890 | for (i = 0; i < q_vector->rxr_count; i++) { | |
891 | j = adapter->rx_ring[r_idx].reg_idx; | |
e8e26350 | 892 | ixgbe_set_ivar(adapter, 0, j, v_idx); |
021230d4 | 893 | r_idx = find_next_bit(q_vector->rxr_idx, |
b4617240 PW |
894 | adapter->num_rx_queues, |
895 | r_idx + 1); | |
021230d4 AV |
896 | } |
897 | r_idx = find_first_bit(q_vector->txr_idx, | |
b4617240 | 898 | adapter->num_tx_queues); |
021230d4 AV |
899 | |
900 | for (i = 0; i < q_vector->txr_count; i++) { | |
901 | j = adapter->tx_ring[r_idx].reg_idx; | |
e8e26350 | 902 | ixgbe_set_ivar(adapter, 1, j, v_idx); |
021230d4 | 903 | r_idx = find_next_bit(q_vector->txr_idx, |
b4617240 PW |
904 | adapter->num_tx_queues, |
905 | r_idx + 1); | |
021230d4 AV |
906 | } |
907 | ||
30efa5a3 | 908 | /* if this is a tx only vector halve the interrupt rate */ |
021230d4 | 909 | if (q_vector->txr_count && !q_vector->rxr_count) |
30efa5a3 | 910 | q_vector->eitr = (adapter->eitr_param >> 1); |
509ee935 | 911 | else if (q_vector->rxr_count) |
30efa5a3 JB |
912 | /* rx only */ |
913 | q_vector->eitr = adapter->eitr_param; | |
021230d4 | 914 | |
fe49f04a | 915 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
916 | } |
917 | ||
e8e26350 PW |
918 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
919 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, | |
920 | v_idx); | |
921 | else if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
922 | ixgbe_set_ivar(adapter, -1, 1, v_idx); | |
021230d4 AV |
923 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
924 | ||
41fb9248 | 925 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 926 | mask = IXGBE_EIMS_ENABLE_MASK; |
41fb9248 | 927 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); |
021230d4 | 928 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
929 | } |
930 | ||
f494e8fa AV |
931 | enum latency_range { |
932 | lowest_latency = 0, | |
933 | low_latency = 1, | |
934 | bulk_latency = 2, | |
935 | latency_invalid = 255 | |
936 | }; | |
937 | ||
938 | /** | |
939 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
940 | * @adapter: pointer to adapter | |
941 | * @eitr: eitr setting (ints per sec) to give last timeslice | |
942 | * @itr_setting: current throttle rate in ints/second | |
943 | * @packets: the number of packets during this measurement interval | |
944 | * @bytes: the number of bytes during this measurement interval | |
945 | * | |
946 | * Stores a new ITR value based on packets and byte | |
947 | * counts during the last interrupt. The advantage of per interrupt | |
948 | * computation is faster updates and more accurate ITR for the current | |
949 | * traffic pattern. Constants in this function were computed | |
950 | * based on theoretical maximum wire speed and thresholds were set based | |
951 | * on testing data as well as attempting to minimize response time | |
952 | * while increasing bulk throughput. | |
953 | * this functionality is controlled by the InterruptThrottleRate module | |
954 | * parameter (see ixgbe_param.c) | |
955 | **/ | |
956 | static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter, | |
b4617240 PW |
957 | u32 eitr, u8 itr_setting, |
958 | int packets, int bytes) | |
f494e8fa AV |
959 | { |
960 | unsigned int retval = itr_setting; | |
961 | u32 timepassed_us; | |
962 | u64 bytes_perint; | |
963 | ||
964 | if (packets == 0) | |
965 | goto update_itr_done; | |
966 | ||
967 | ||
968 | /* simple throttlerate management | |
969 | * 0-20MB/s lowest (100000 ints/s) | |
970 | * 20-100MB/s low (20000 ints/s) | |
971 | * 100-1249MB/s bulk (8000 ints/s) | |
972 | */ | |
973 | /* what was last interrupt timeslice? */ | |
974 | timepassed_us = 1000000/eitr; | |
975 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ | |
976 | ||
977 | switch (itr_setting) { | |
978 | case lowest_latency: | |
979 | if (bytes_perint > adapter->eitr_low) | |
980 | retval = low_latency; | |
981 | break; | |
982 | case low_latency: | |
983 | if (bytes_perint > adapter->eitr_high) | |
984 | retval = bulk_latency; | |
985 | else if (bytes_perint <= adapter->eitr_low) | |
986 | retval = lowest_latency; | |
987 | break; | |
988 | case bulk_latency: | |
989 | if (bytes_perint <= adapter->eitr_high) | |
990 | retval = low_latency; | |
991 | break; | |
992 | } | |
993 | ||
994 | update_itr_done: | |
995 | return retval; | |
996 | } | |
997 | ||
509ee935 JB |
998 | /** |
999 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1000 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1001 | * |
1002 | * This function is made to be called by ethtool and by the driver | |
1003 | * when it needs to update EITR registers at runtime. Hardware | |
1004 | * specific quirks/differences are taken care of here. | |
1005 | */ | |
fe49f04a | 1006 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1007 | { |
fe49f04a | 1008 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1009 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
1010 | int v_idx = q_vector->v_idx; |
1011 | u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); | |
1012 | ||
509ee935 JB |
1013 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1014 | /* must write high and low 16 bits to reset counter */ | |
1015 | itr_reg |= (itr_reg << 16); | |
1016 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
1017 | /* | |
1018 | * set the WDIS bit to not clear the timer bits and cause an | |
1019 | * immediate assertion of the interrupt | |
1020 | */ | |
1021 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
1022 | } | |
1023 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1024 | } | |
1025 | ||
f494e8fa AV |
1026 | static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector) |
1027 | { | |
1028 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
f494e8fa AV |
1029 | u32 new_itr; |
1030 | u8 current_itr, ret_itr; | |
fe49f04a | 1031 | int i, r_idx; |
f494e8fa AV |
1032 | struct ixgbe_ring *rx_ring, *tx_ring; |
1033 | ||
1034 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1035 | for (i = 0; i < q_vector->txr_count; i++) { | |
1036 | tx_ring = &(adapter->tx_ring[r_idx]); | |
1037 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1038 | q_vector->tx_itr, |
1039 | tx_ring->total_packets, | |
1040 | tx_ring->total_bytes); | |
f494e8fa AV |
1041 | /* if the result for this queue would decrease interrupt |
1042 | * rate for this vector then use that result */ | |
30efa5a3 | 1043 | q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ? |
b4617240 | 1044 | q_vector->tx_itr - 1 : ret_itr); |
f494e8fa | 1045 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1046 | r_idx + 1); |
f494e8fa AV |
1047 | } |
1048 | ||
1049 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1050 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1051 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1052 | ret_itr = ixgbe_update_itr(adapter, q_vector->eitr, | |
b4617240 PW |
1053 | q_vector->rx_itr, |
1054 | rx_ring->total_packets, | |
1055 | rx_ring->total_bytes); | |
f494e8fa AV |
1056 | /* if the result for this queue would decrease interrupt |
1057 | * rate for this vector then use that result */ | |
30efa5a3 | 1058 | q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ? |
b4617240 | 1059 | q_vector->rx_itr - 1 : ret_itr); |
f494e8fa | 1060 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
b4617240 | 1061 | r_idx + 1); |
f494e8fa AV |
1062 | } |
1063 | ||
30efa5a3 | 1064 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1065 | |
1066 | switch (current_itr) { | |
1067 | /* counts and packets in update_itr are dependent on these numbers */ | |
1068 | case lowest_latency: | |
1069 | new_itr = 100000; | |
1070 | break; | |
1071 | case low_latency: | |
1072 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1073 | break; | |
1074 | case bulk_latency: | |
1075 | default: | |
1076 | new_itr = 8000; | |
1077 | break; | |
1078 | } | |
1079 | ||
1080 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1081 | /* do an exponential smoothing */ |
1082 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1083 | |
1084 | /* save the algorithm value here, not the smoothed one */ | |
1085 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1086 | |
1087 | ixgbe_write_eitr(q_vector); | |
f494e8fa AV |
1088 | } |
1089 | ||
1090 | return; | |
1091 | } | |
1092 | ||
0befdb3e JB |
1093 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1094 | { | |
1095 | struct ixgbe_hw *hw = &adapter->hw; | |
1096 | ||
1097 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1098 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
1099 | DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n"); | |
1100 | /* write to clear the interrupt */ | |
1101 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1102 | } | |
1103 | } | |
cf8280ee | 1104 | |
e8e26350 PW |
1105 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1106 | { | |
1107 | struct ixgbe_hw *hw = &adapter->hw; | |
1108 | ||
1109 | if (eicr & IXGBE_EICR_GPI_SDP1) { | |
1110 | /* Clear the interrupt */ | |
1111 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1112 | schedule_work(&adapter->multispeed_fiber_task); | |
1113 | } else if (eicr & IXGBE_EICR_GPI_SDP2) { | |
1114 | /* Clear the interrupt */ | |
1115 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
1116 | schedule_work(&adapter->sfp_config_module_task); | |
1117 | } else { | |
1118 | /* Interrupt isn't for us... */ | |
1119 | return; | |
1120 | } | |
1121 | } | |
1122 | ||
cf8280ee JB |
1123 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1124 | { | |
1125 | struct ixgbe_hw *hw = &adapter->hw; | |
1126 | ||
1127 | adapter->lsc_int++; | |
1128 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1129 | adapter->link_check_timeout = jiffies; | |
1130 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1131 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
1132 | schedule_work(&adapter->watchdog_task); | |
1133 | } | |
1134 | } | |
1135 | ||
9a799d71 AK |
1136 | static irqreturn_t ixgbe_msix_lsc(int irq, void *data) |
1137 | { | |
1138 | struct net_device *netdev = data; | |
1139 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1140 | struct ixgbe_hw *hw = &adapter->hw; | |
54037505 DS |
1141 | u32 eicr; |
1142 | ||
1143 | /* | |
1144 | * Workaround for Silicon errata. Use clear-by-write instead | |
1145 | * of clear-by-read. Reading with EICS will return the | |
1146 | * interrupt causes without clearing, which later be done | |
1147 | * with the write to EICR. | |
1148 | */ | |
1149 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1150 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
9a799d71 | 1151 | |
cf8280ee JB |
1152 | if (eicr & IXGBE_EICR_LSC) |
1153 | ixgbe_check_lsc(adapter); | |
d4f80882 | 1154 | |
e8e26350 PW |
1155 | if (hw->mac.type == ixgbe_mac_82598EB) |
1156 | ixgbe_check_fan_failure(adapter, eicr); | |
0befdb3e | 1157 | |
c4cf55e5 | 1158 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 1159 | ixgbe_check_sfp_event(adapter, eicr); |
c4cf55e5 PWJ |
1160 | |
1161 | /* Handle Flow Director Full threshold interrupt */ | |
1162 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
1163 | int i; | |
1164 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR); | |
1165 | /* Disable transmits before FDIR Re-initialization */ | |
1166 | netif_tx_stop_all_queues(netdev); | |
1167 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1168 | struct ixgbe_ring *tx_ring = | |
1169 | &adapter->tx_ring[i]; | |
1170 | if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE, | |
1171 | &tx_ring->reinit_state)) | |
1172 | schedule_work(&adapter->fdir_reinit_task); | |
1173 | } | |
1174 | } | |
1175 | } | |
d4f80882 AV |
1176 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
1177 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER); | |
9a799d71 AK |
1178 | |
1179 | return IRQ_HANDLED; | |
1180 | } | |
1181 | ||
fe49f04a AD |
1182 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1183 | u64 qmask) | |
1184 | { | |
1185 | u32 mask; | |
1186 | ||
1187 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1188 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1189 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); | |
1190 | } else { | |
1191 | mask = (qmask & 0xFFFFFFFF); | |
1192 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask); | |
1193 | mask = (qmask >> 32); | |
1194 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask); | |
1195 | } | |
1196 | /* skip the flush */ | |
1197 | } | |
1198 | ||
1199 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
1200 | u64 qmask) | |
1201 | { | |
1202 | u32 mask; | |
1203 | ||
1204 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
1205 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); | |
1206 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); | |
1207 | } else { | |
1208 | mask = (qmask & 0xFFFFFFFF); | |
1209 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask); | |
1210 | mask = (qmask >> 32); | |
1211 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask); | |
1212 | } | |
1213 | /* skip the flush */ | |
1214 | } | |
1215 | ||
9a799d71 AK |
1216 | static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data) |
1217 | { | |
021230d4 AV |
1218 | struct ixgbe_q_vector *q_vector = data; |
1219 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1220 | struct ixgbe_ring *tx_ring; |
021230d4 AV |
1221 | int i, r_idx; |
1222 | ||
1223 | if (!q_vector->txr_count) | |
1224 | return IRQ_HANDLED; | |
1225 | ||
1226 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1227 | for (i = 0; i < q_vector->txr_count; i++) { | |
3a581073 | 1228 | tx_ring = &(adapter->tx_ring[r_idx]); |
3a581073 JB |
1229 | tx_ring->total_bytes = 0; |
1230 | tx_ring->total_packets = 0; | |
021230d4 | 1231 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, |
b4617240 | 1232 | r_idx + 1); |
021230d4 | 1233 | } |
9a799d71 | 1234 | |
91281fd3 AD |
1235 | /* disable interrupts on this vector only */ |
1236 | ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
1237 | napi_schedule(&q_vector->napi); | |
1238 | ||
9a799d71 AK |
1239 | return IRQ_HANDLED; |
1240 | } | |
1241 | ||
021230d4 AV |
1242 | /** |
1243 | * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues) | |
1244 | * @irq: unused | |
1245 | * @data: pointer to our q_vector struct for this interrupt vector | |
1246 | **/ | |
9a799d71 AK |
1247 | static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data) |
1248 | { | |
021230d4 AV |
1249 | struct ixgbe_q_vector *q_vector = data; |
1250 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
3a581073 | 1251 | struct ixgbe_ring *rx_ring; |
021230d4 | 1252 | int r_idx; |
30efa5a3 | 1253 | int i; |
021230d4 AV |
1254 | |
1255 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
30efa5a3 JB |
1256 | for (i = 0; i < q_vector->rxr_count; i++) { |
1257 | rx_ring = &(adapter->rx_ring[r_idx]); | |
1258 | rx_ring->total_bytes = 0; | |
1259 | rx_ring->total_packets = 0; | |
1260 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1261 | r_idx + 1); | |
1262 | } | |
1263 | ||
021230d4 AV |
1264 | if (!q_vector->rxr_count) |
1265 | return IRQ_HANDLED; | |
1266 | ||
30efa5a3 | 1267 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1268 | rx_ring = &(adapter->rx_ring[r_idx]); |
021230d4 | 1269 | /* disable interrupts on this vector only */ |
fe49f04a | 1270 | ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx)); |
288379f0 | 1271 | napi_schedule(&q_vector->napi); |
021230d4 AV |
1272 | |
1273 | return IRQ_HANDLED; | |
1274 | } | |
1275 | ||
1276 | static irqreturn_t ixgbe_msix_clean_many(int irq, void *data) | |
1277 | { | |
91281fd3 AD |
1278 | struct ixgbe_q_vector *q_vector = data; |
1279 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1280 | struct ixgbe_ring *ring; | |
1281 | int r_idx; | |
1282 | int i; | |
1283 | ||
1284 | if (!q_vector->txr_count && !q_vector->rxr_count) | |
1285 | return IRQ_HANDLED; | |
1286 | ||
1287 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1288 | for (i = 0; i < q_vector->txr_count; i++) { | |
1289 | ring = &(adapter->tx_ring[r_idx]); | |
1290 | ring->total_bytes = 0; | |
1291 | ring->total_packets = 0; | |
1292 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1293 | r_idx + 1); | |
1294 | } | |
1295 | ||
1296 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1297 | for (i = 0; i < q_vector->rxr_count; i++) { | |
1298 | ring = &(adapter->rx_ring[r_idx]); | |
1299 | ring->total_bytes = 0; | |
1300 | ring->total_packets = 0; | |
1301 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, | |
1302 | r_idx + 1); | |
1303 | } | |
1304 | ||
1305 | /* disable interrupts on this vector only */ | |
1306 | ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
1307 | napi_schedule(&q_vector->napi); | |
9a799d71 | 1308 | |
9a799d71 AK |
1309 | return IRQ_HANDLED; |
1310 | } | |
1311 | ||
021230d4 AV |
1312 | /** |
1313 | * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine | |
1314 | * @napi: napi struct with our devices info in it | |
1315 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1316 | * | |
f0848276 JB |
1317 | * This function is optimized for cleaning one queue only on a single |
1318 | * q_vector!!! | |
021230d4 | 1319 | **/ |
9a799d71 AK |
1320 | static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget) |
1321 | { | |
021230d4 | 1322 | struct ixgbe_q_vector *q_vector = |
b4617240 | 1323 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 1324 | struct ixgbe_adapter *adapter = q_vector->adapter; |
f0848276 | 1325 | struct ixgbe_ring *rx_ring = NULL; |
9a799d71 | 1326 | int work_done = 0; |
021230d4 | 1327 | long r_idx; |
9a799d71 | 1328 | |
021230d4 | 1329 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); |
3a581073 | 1330 | rx_ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1331 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 1332 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3a581073 | 1333 | ixgbe_update_rx_dca(adapter, rx_ring); |
bd0362dd | 1334 | #endif |
9a799d71 | 1335 | |
78b6f4ce | 1336 | ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget); |
9a799d71 | 1337 | |
021230d4 AV |
1338 | /* If all Rx work done, exit the polling mode */ |
1339 | if (work_done < budget) { | |
288379f0 | 1340 | napi_complete(napi); |
509ee935 | 1341 | if (adapter->itr_setting & 1) |
f494e8fa | 1342 | ixgbe_set_itr_msix(q_vector); |
9a799d71 | 1343 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
fe49f04a AD |
1344 | ixgbe_irq_enable_queues(adapter, |
1345 | ((u64)1 << q_vector->v_idx)); | |
9a799d71 AK |
1346 | } |
1347 | ||
1348 | return work_done; | |
1349 | } | |
1350 | ||
f0848276 | 1351 | /** |
91281fd3 | 1352 | * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine |
f0848276 JB |
1353 | * @napi: napi struct with our devices info in it |
1354 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1355 | * | |
1356 | * This function will clean more than one rx queue associated with a | |
1357 | * q_vector. | |
1358 | **/ | |
91281fd3 | 1359 | static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget) |
f0848276 JB |
1360 | { |
1361 | struct ixgbe_q_vector *q_vector = | |
1362 | container_of(napi, struct ixgbe_q_vector, napi); | |
1363 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
91281fd3 | 1364 | struct ixgbe_ring *ring = NULL; |
f0848276 JB |
1365 | int work_done = 0, i; |
1366 | long r_idx; | |
91281fd3 AD |
1367 | bool tx_clean_complete = true; |
1368 | ||
1369 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1370 | for (i = 0; i < q_vector->txr_count; i++) { | |
1371 | ring = &(adapter->tx_ring[r_idx]); | |
1372 | #ifdef CONFIG_IXGBE_DCA | |
1373 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1374 | ixgbe_update_tx_dca(adapter, ring); | |
1375 | #endif | |
1376 | tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring); | |
1377 | r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues, | |
1378 | r_idx + 1); | |
1379 | } | |
f0848276 JB |
1380 | |
1381 | /* attempt to distribute budget to each queue fairly, but don't allow | |
1382 | * the budget to go below 1 because we'll exit polling */ | |
1383 | budget /= (q_vector->rxr_count ?: 1); | |
1384 | budget = max(budget, 1); | |
1385 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
1386 | for (i = 0; i < q_vector->rxr_count; i++) { | |
91281fd3 | 1387 | ring = &(adapter->rx_ring[r_idx]); |
5dd2d332 | 1388 | #ifdef CONFIG_IXGBE_DCA |
f0848276 | 1389 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
91281fd3 | 1390 | ixgbe_update_rx_dca(adapter, ring); |
f0848276 | 1391 | #endif |
91281fd3 | 1392 | ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget); |
f0848276 JB |
1393 | r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues, |
1394 | r_idx + 1); | |
1395 | } | |
1396 | ||
1397 | r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues); | |
91281fd3 | 1398 | ring = &(adapter->rx_ring[r_idx]); |
f0848276 | 1399 | /* If all Rx work done, exit the polling mode */ |
7f821875 | 1400 | if (work_done < budget) { |
288379f0 | 1401 | napi_complete(napi); |
509ee935 | 1402 | if (adapter->itr_setting & 1) |
f0848276 JB |
1403 | ixgbe_set_itr_msix(q_vector); |
1404 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
fe49f04a AD |
1405 | ixgbe_irq_enable_queues(adapter, |
1406 | ((u64)1 << q_vector->v_idx)); | |
f0848276 JB |
1407 | return 0; |
1408 | } | |
1409 | ||
1410 | return work_done; | |
1411 | } | |
91281fd3 AD |
1412 | |
1413 | /** | |
1414 | * ixgbe_clean_txonly - msix (aka one shot) tx clean routine | |
1415 | * @napi: napi struct with our devices info in it | |
1416 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1417 | * | |
1418 | * This function is optimized for cleaning one queue only on a single | |
1419 | * q_vector!!! | |
1420 | **/ | |
1421 | static int ixgbe_clean_txonly(struct napi_struct *napi, int budget) | |
1422 | { | |
1423 | struct ixgbe_q_vector *q_vector = | |
1424 | container_of(napi, struct ixgbe_q_vector, napi); | |
1425 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
1426 | struct ixgbe_ring *tx_ring = NULL; | |
1427 | int work_done = 0; | |
1428 | long r_idx; | |
1429 | ||
1430 | r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues); | |
1431 | tx_ring = &(adapter->tx_ring[r_idx]); | |
1432 | #ifdef CONFIG_IXGBE_DCA | |
1433 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1434 | ixgbe_update_tx_dca(adapter, tx_ring); | |
1435 | #endif | |
1436 | ||
1437 | if (!ixgbe_clean_tx_irq(q_vector, tx_ring)) | |
1438 | work_done = budget; | |
1439 | ||
1440 | /* If all Rx work done, exit the polling mode */ | |
1441 | if (work_done < budget) { | |
1442 | napi_complete(napi); | |
1443 | if (adapter->itr_setting & 1) | |
1444 | ixgbe_set_itr_msix(q_vector); | |
1445 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
1446 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
1447 | } | |
1448 | ||
1449 | return work_done; | |
1450 | } | |
1451 | ||
021230d4 | 1452 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
b4617240 | 1453 | int r_idx) |
021230d4 | 1454 | { |
7a921c93 AD |
1455 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1456 | ||
1457 | set_bit(r_idx, q_vector->rxr_idx); | |
1458 | q_vector->rxr_count++; | |
021230d4 AV |
1459 | } |
1460 | ||
1461 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
7a921c93 | 1462 | int t_idx) |
021230d4 | 1463 | { |
7a921c93 AD |
1464 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
1465 | ||
1466 | set_bit(t_idx, q_vector->txr_idx); | |
1467 | q_vector->txr_count++; | |
021230d4 AV |
1468 | } |
1469 | ||
9a799d71 | 1470 | /** |
021230d4 AV |
1471 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
1472 | * @adapter: board private structure to initialize | |
1473 | * @vectors: allotted vector count for descriptor rings | |
9a799d71 | 1474 | * |
021230d4 AV |
1475 | * This function maps descriptor rings to the queue-specific vectors |
1476 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
1477 | * one vector per ring/queue, but on a constrained vector budget, we | |
1478 | * group the rings as "efficiently" as possible. You would add new | |
1479 | * mapping configurations in here. | |
9a799d71 | 1480 | **/ |
021230d4 | 1481 | static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 1482 | int vectors) |
021230d4 AV |
1483 | { |
1484 | int v_start = 0; | |
1485 | int rxr_idx = 0, txr_idx = 0; | |
1486 | int rxr_remaining = adapter->num_rx_queues; | |
1487 | int txr_remaining = adapter->num_tx_queues; | |
1488 | int i, j; | |
1489 | int rqpv, tqpv; | |
1490 | int err = 0; | |
1491 | ||
1492 | /* No mapping required if MSI-X is disabled. */ | |
1493 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
1494 | goto out; | |
9a799d71 | 1495 | |
021230d4 AV |
1496 | /* |
1497 | * The ideal configuration... | |
1498 | * We have enough vectors to map one per queue. | |
1499 | */ | |
1500 | if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) { | |
1501 | for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++) | |
1502 | map_vector_to_rxq(adapter, v_start, rxr_idx); | |
9a799d71 | 1503 | |
021230d4 AV |
1504 | for (; txr_idx < txr_remaining; v_start++, txr_idx++) |
1505 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 1506 | |
9a799d71 | 1507 | goto out; |
021230d4 | 1508 | } |
9a799d71 | 1509 | |
021230d4 AV |
1510 | /* |
1511 | * If we don't have enough vectors for a 1-to-1 | |
1512 | * mapping, we'll have to group them so there are | |
1513 | * multiple queues per vector. | |
1514 | */ | |
1515 | /* Re-adjusting *qpv takes care of the remainder. */ | |
1516 | for (i = v_start; i < vectors; i++) { | |
1517 | rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i); | |
1518 | for (j = 0; j < rqpv; j++) { | |
1519 | map_vector_to_rxq(adapter, i, rxr_idx); | |
1520 | rxr_idx++; | |
1521 | rxr_remaining--; | |
1522 | } | |
1523 | } | |
1524 | for (i = v_start; i < vectors; i++) { | |
1525 | tqpv = DIV_ROUND_UP(txr_remaining, vectors - i); | |
1526 | for (j = 0; j < tqpv; j++) { | |
1527 | map_vector_to_txq(adapter, i, txr_idx); | |
1528 | txr_idx++; | |
1529 | txr_remaining--; | |
9a799d71 | 1530 | } |
9a799d71 AK |
1531 | } |
1532 | ||
021230d4 AV |
1533 | out: |
1534 | return err; | |
1535 | } | |
1536 | ||
1537 | /** | |
1538 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
1539 | * @adapter: board private structure | |
1540 | * | |
1541 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
1542 | * interrupts from the kernel. | |
1543 | **/ | |
1544 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
1545 | { | |
1546 | struct net_device *netdev = adapter->netdev; | |
1547 | irqreturn_t (*handler)(int, void *); | |
1548 | int i, vector, q_vectors, err; | |
cb13fc20 | 1549 | int ri=0, ti=0; |
021230d4 AV |
1550 | |
1551 | /* Decrement for Other and TCP Timer vectors */ | |
1552 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1553 | ||
1554 | /* Map the Tx/Rx rings to the vectors we were allotted. */ | |
1555 | err = ixgbe_map_rings_to_vectors(adapter, q_vectors); | |
1556 | if (err) | |
1557 | goto out; | |
1558 | ||
1559 | #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \ | |
b4617240 PW |
1560 | (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \ |
1561 | &ixgbe_msix_clean_many) | |
021230d4 | 1562 | for (vector = 0; vector < q_vectors; vector++) { |
7a921c93 | 1563 | handler = SET_HANDLER(adapter->q_vector[vector]); |
cb13fc20 RO |
1564 | |
1565 | if(handler == &ixgbe_msix_clean_rx) { | |
1566 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1567 | netdev->name, "rx", ri++); | |
1568 | } | |
1569 | else if(handler == &ixgbe_msix_clean_tx) { | |
1570 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1571 | netdev->name, "tx", ti++); | |
1572 | } | |
1573 | else | |
1574 | sprintf(adapter->name[vector], "%s-%s-%d", | |
1575 | netdev->name, "TxRx", vector); | |
1576 | ||
021230d4 | 1577 | err = request_irq(adapter->msix_entries[vector].vector, |
b4617240 | 1578 | handler, 0, adapter->name[vector], |
7a921c93 | 1579 | adapter->q_vector[vector]); |
9a799d71 AK |
1580 | if (err) { |
1581 | DPRINTK(PROBE, ERR, | |
b4617240 PW |
1582 | "request_irq failed for MSIX interrupt " |
1583 | "Error: %d\n", err); | |
021230d4 | 1584 | goto free_queue_irqs; |
9a799d71 | 1585 | } |
9a799d71 AK |
1586 | } |
1587 | ||
021230d4 AV |
1588 | sprintf(adapter->name[vector], "%s:lsc", netdev->name); |
1589 | err = request_irq(adapter->msix_entries[vector].vector, | |
b4617240 | 1590 | &ixgbe_msix_lsc, 0, adapter->name[vector], netdev); |
9a799d71 AK |
1591 | if (err) { |
1592 | DPRINTK(PROBE, ERR, | |
1593 | "request_irq for msix_lsc failed: %d\n", err); | |
021230d4 | 1594 | goto free_queue_irqs; |
9a799d71 AK |
1595 | } |
1596 | ||
9a799d71 AK |
1597 | return 0; |
1598 | ||
021230d4 AV |
1599 | free_queue_irqs: |
1600 | for (i = vector - 1; i >= 0; i--) | |
1601 | free_irq(adapter->msix_entries[--vector].vector, | |
7a921c93 | 1602 | adapter->q_vector[i]); |
021230d4 AV |
1603 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
1604 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
1605 | kfree(adapter->msix_entries); |
1606 | adapter->msix_entries = NULL; | |
021230d4 | 1607 | out: |
9a799d71 AK |
1608 | return err; |
1609 | } | |
1610 | ||
f494e8fa AV |
1611 | static void ixgbe_set_itr(struct ixgbe_adapter *adapter) |
1612 | { | |
7a921c93 | 1613 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
f494e8fa AV |
1614 | u8 current_itr; |
1615 | u32 new_itr = q_vector->eitr; | |
1616 | struct ixgbe_ring *rx_ring = &adapter->rx_ring[0]; | |
1617 | struct ixgbe_ring *tx_ring = &adapter->tx_ring[0]; | |
1618 | ||
30efa5a3 | 1619 | q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1620 | q_vector->tx_itr, |
1621 | tx_ring->total_packets, | |
1622 | tx_ring->total_bytes); | |
30efa5a3 | 1623 | q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr, |
b4617240 PW |
1624 | q_vector->rx_itr, |
1625 | rx_ring->total_packets, | |
1626 | rx_ring->total_bytes); | |
f494e8fa | 1627 | |
30efa5a3 | 1628 | current_itr = max(q_vector->rx_itr, q_vector->tx_itr); |
f494e8fa AV |
1629 | |
1630 | switch (current_itr) { | |
1631 | /* counts and packets in update_itr are dependent on these numbers */ | |
1632 | case lowest_latency: | |
1633 | new_itr = 100000; | |
1634 | break; | |
1635 | case low_latency: | |
1636 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1637 | break; | |
1638 | case bulk_latency: | |
1639 | new_itr = 8000; | |
1640 | break; | |
1641 | default: | |
1642 | break; | |
1643 | } | |
1644 | ||
1645 | if (new_itr != q_vector->eitr) { | |
fe49f04a AD |
1646 | /* do an exponential smoothing */ |
1647 | new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100); | |
509ee935 JB |
1648 | |
1649 | /* save the algorithm value here, not the smoothed one */ | |
1650 | q_vector->eitr = new_itr; | |
fe49f04a AD |
1651 | |
1652 | ixgbe_write_eitr(q_vector); | |
f494e8fa AV |
1653 | } |
1654 | ||
1655 | return; | |
1656 | } | |
1657 | ||
79aefa45 AD |
1658 | /** |
1659 | * ixgbe_irq_enable - Enable default interrupt generation settings | |
1660 | * @adapter: board private structure | |
1661 | **/ | |
1662 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter) | |
1663 | { | |
1664 | u32 mask; | |
835462fc NS |
1665 | |
1666 | mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); | |
6ab33d51 DM |
1667 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
1668 | mask |= IXGBE_EIMS_GPI_SDP1; | |
e8e26350 | 1669 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
2a41ff81 | 1670 | mask |= IXGBE_EIMS_ECC; |
e8e26350 PW |
1671 | mask |= IXGBE_EIMS_GPI_SDP1; |
1672 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1673 | } | |
c4cf55e5 PWJ |
1674 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
1675 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
1676 | mask |= IXGBE_EIMS_FLOW_DIR; | |
e8e26350 | 1677 | |
79aefa45 | 1678 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
835462fc | 1679 | ixgbe_irq_enable_queues(adapter, ~0); |
79aefa45 AD |
1680 | IXGBE_WRITE_FLUSH(&adapter->hw); |
1681 | } | |
021230d4 | 1682 | |
9a799d71 | 1683 | /** |
021230d4 | 1684 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
1685 | * @irq: interrupt number |
1686 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
1687 | **/ |
1688 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
1689 | { | |
1690 | struct net_device *netdev = data; | |
1691 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1692 | struct ixgbe_hw *hw = &adapter->hw; | |
7a921c93 | 1693 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
1694 | u32 eicr; |
1695 | ||
54037505 DS |
1696 | /* |
1697 | * Workaround for silicon errata. Mask the interrupts | |
1698 | * before the read of EICR. | |
1699 | */ | |
1700 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
1701 | ||
021230d4 AV |
1702 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
1703 | * therefore no explict interrupt disable is necessary */ | |
1704 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e JB |
1705 | if (!eicr) { |
1706 | /* shared interrupt alert! | |
1707 | * make sure interrupts are enabled because the read will | |
1708 | * have disabled interrupts due to EIAM */ | |
1709 | ixgbe_irq_enable(adapter); | |
9a799d71 | 1710 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 1711 | } |
9a799d71 | 1712 | |
cf8280ee JB |
1713 | if (eicr & IXGBE_EICR_LSC) |
1714 | ixgbe_check_lsc(adapter); | |
021230d4 | 1715 | |
e8e26350 PW |
1716 | if (hw->mac.type == ixgbe_mac_82599EB) |
1717 | ixgbe_check_sfp_event(adapter, eicr); | |
1718 | ||
0befdb3e JB |
1719 | ixgbe_check_fan_failure(adapter, eicr); |
1720 | ||
7a921c93 | 1721 | if (napi_schedule_prep(&(q_vector->napi))) { |
f494e8fa AV |
1722 | adapter->tx_ring[0].total_packets = 0; |
1723 | adapter->tx_ring[0].total_bytes = 0; | |
1724 | adapter->rx_ring[0].total_packets = 0; | |
1725 | adapter->rx_ring[0].total_bytes = 0; | |
021230d4 | 1726 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 1727 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
1728 | } |
1729 | ||
1730 | return IRQ_HANDLED; | |
1731 | } | |
1732 | ||
021230d4 AV |
1733 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
1734 | { | |
1735 | int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
1736 | ||
1737 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 1738 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
021230d4 AV |
1739 | bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES); |
1740 | bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES); | |
1741 | q_vector->rxr_count = 0; | |
1742 | q_vector->txr_count = 0; | |
1743 | } | |
1744 | } | |
1745 | ||
9a799d71 AK |
1746 | /** |
1747 | * ixgbe_request_irq - initialize interrupts | |
1748 | * @adapter: board private structure | |
1749 | * | |
1750 | * Attempts to configure interrupts using the best available | |
1751 | * capabilities of the hardware and kernel. | |
1752 | **/ | |
021230d4 | 1753 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
1754 | { |
1755 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 1756 | int err; |
9a799d71 | 1757 | |
021230d4 AV |
1758 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
1759 | err = ixgbe_request_msix_irqs(adapter); | |
1760 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
1761 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0, | |
b4617240 | 1762 | netdev->name, netdev); |
021230d4 AV |
1763 | } else { |
1764 | err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED, | |
b4617240 | 1765 | netdev->name, netdev); |
9a799d71 AK |
1766 | } |
1767 | ||
9a799d71 AK |
1768 | if (err) |
1769 | DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err); | |
1770 | ||
9a799d71 AK |
1771 | return err; |
1772 | } | |
1773 | ||
1774 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
1775 | { | |
1776 | struct net_device *netdev = adapter->netdev; | |
1777 | ||
1778 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
021230d4 | 1779 | int i, q_vectors; |
9a799d71 | 1780 | |
021230d4 AV |
1781 | q_vectors = adapter->num_msix_vectors; |
1782 | ||
1783 | i = q_vectors - 1; | |
9a799d71 | 1784 | free_irq(adapter->msix_entries[i].vector, netdev); |
9a799d71 | 1785 | |
021230d4 AV |
1786 | i--; |
1787 | for (; i >= 0; i--) { | |
1788 | free_irq(adapter->msix_entries[i].vector, | |
7a921c93 | 1789 | adapter->q_vector[i]); |
021230d4 AV |
1790 | } |
1791 | ||
1792 | ixgbe_reset_q_vectors(adapter); | |
1793 | } else { | |
1794 | free_irq(adapter->pdev->irq, netdev); | |
9a799d71 AK |
1795 | } |
1796 | } | |
1797 | ||
22d5a71b JB |
1798 | /** |
1799 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
1800 | * @adapter: board private structure | |
1801 | **/ | |
1802 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
1803 | { | |
835462fc NS |
1804 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
1805 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); | |
1806 | } else { | |
1807 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); | |
1808 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 1809 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
22d5a71b JB |
1810 | } |
1811 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
1812 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
1813 | int i; | |
1814 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
1815 | synchronize_irq(adapter->msix_entries[i].vector); | |
1816 | } else { | |
1817 | synchronize_irq(adapter->pdev->irq); | |
1818 | } | |
1819 | } | |
1820 | ||
9a799d71 AK |
1821 | /** |
1822 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
1823 | * | |
1824 | **/ | |
1825 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
1826 | { | |
9a799d71 AK |
1827 | struct ixgbe_hw *hw = &adapter->hw; |
1828 | ||
021230d4 | 1829 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
30efa5a3 | 1830 | EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param)); |
9a799d71 | 1831 | |
e8e26350 PW |
1832 | ixgbe_set_ivar(adapter, 0, 0, 0); |
1833 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 AV |
1834 | |
1835 | map_vector_to_rxq(adapter, 0, 0); | |
1836 | map_vector_to_txq(adapter, 0, 0); | |
1837 | ||
1838 | DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n"); | |
9a799d71 AK |
1839 | } |
1840 | ||
1841 | /** | |
3a581073 | 1842 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
1843 | * @adapter: board private structure |
1844 | * | |
1845 | * Configure the Tx unit of the MAC after a reset. | |
1846 | **/ | |
1847 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
1848 | { | |
12207e49 | 1849 | u64 tdba; |
9a799d71 | 1850 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 1851 | u32 i, j, tdlen, txctrl; |
9a799d71 AK |
1852 | |
1853 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
1854 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
e01c31a5 JB |
1855 | struct ixgbe_ring *ring = &adapter->tx_ring[i]; |
1856 | j = ring->reg_idx; | |
1857 | tdba = ring->dma; | |
1858 | tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc); | |
021230d4 | 1859 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j), |
284901a9 | 1860 | (tdba & DMA_BIT_MASK(32))); |
021230d4 AV |
1861 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32)); |
1862 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen); | |
1863 | IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0); | |
1864 | IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0); | |
1865 | adapter->tx_ring[i].head = IXGBE_TDH(j); | |
1866 | adapter->tx_ring[i].tail = IXGBE_TDT(j); | |
1867 | /* Disable Tx Head Writeback RO bit, since this hoses | |
1868 | * bookkeeping if things aren't delivered in order. | |
1869 | */ | |
e01c31a5 | 1870 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j)); |
021230d4 | 1871 | txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN; |
e01c31a5 | 1872 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl); |
9a799d71 | 1873 | } |
e8e26350 PW |
1874 | if (hw->mac.type == ixgbe_mac_82599EB) { |
1875 | /* We enable 8 traffic classes, DCB only */ | |
1876 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
1877 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA | | |
1878 | IXGBE_MTQC_8TC_8TQ)); | |
1879 | } | |
9a799d71 AK |
1880 | } |
1881 | ||
e8e26350 | 1882 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c JB |
1883 | |
1884 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index) | |
1885 | { | |
1886 | struct ixgbe_ring *rx_ring; | |
1887 | u32 srrctl; | |
e8e26350 | 1888 | int queue0 = 0; |
3be1adfb | 1889 | unsigned long mask; |
0cefafad | 1890 | struct ixgbe_ring_feature *feature = adapter->ring_feature; |
3be1adfb | 1891 | |
e8e26350 | 1892 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
163de42e | 1893 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
0cefafad | 1894 | int dcb_i = feature[RING_F_DCB].indices; |
163de42e AD |
1895 | if (dcb_i == 8) |
1896 | queue0 = index >> 4; | |
1897 | else if (dcb_i == 4) | |
1898 | queue0 = index >> 5; | |
1899 | else | |
1900 | dev_err(&adapter->pdev->dev, "Invalid DCB " | |
1901 | "configuration\n"); | |
0331a832 YZ |
1902 | #ifdef IXGBE_FCOE |
1903 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
1904 | struct ixgbe_ring_feature *f; | |
1905 | ||
1906 | rx_ring = &adapter->rx_ring[queue0]; | |
1907 | f = &adapter->ring_feature[RING_F_FCOE]; | |
1908 | if ((queue0 == 0) && (index > rx_ring->reg_idx)) | |
1909 | queue0 = f->mask + index - | |
1910 | rx_ring->reg_idx - 1; | |
1911 | } | |
1912 | #endif /* IXGBE_FCOE */ | |
163de42e AD |
1913 | } else { |
1914 | queue0 = index; | |
1915 | } | |
cc41ac7c | 1916 | } else { |
0cefafad | 1917 | mask = (unsigned long) feature[RING_F_RSS].mask; |
3be1adfb AD |
1918 | queue0 = index & mask; |
1919 | index = index & mask; | |
cc41ac7c | 1920 | } |
3be1adfb | 1921 | |
cc41ac7c JB |
1922 | rx_ring = &adapter->rx_ring[queue0]; |
1923 | ||
1924 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index)); | |
1925 | ||
1926 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1927 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
1928 | ||
afafd5b0 AD |
1929 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
1930 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
1931 | ||
cc41ac7c | 1932 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
afafd5b0 AD |
1933 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
1934 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1935 | #else | |
1936 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
1937 | #endif | |
cc41ac7c | 1938 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 1939 | } else { |
afafd5b0 AD |
1940 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
1941 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 1942 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 1943 | } |
e8e26350 | 1944 | |
cc41ac7c JB |
1945 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl); |
1946 | } | |
9a799d71 | 1947 | |
0cefafad JB |
1948 | static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
1949 | { | |
1950 | u32 mrqc = 0; | |
1951 | int mask; | |
1952 | ||
1953 | if (!(adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
1954 | return mrqc; | |
1955 | ||
1956 | mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
1957 | #ifdef CONFIG_IXGBE_DCB | |
1958 | | IXGBE_FLAG_DCB_ENABLED | |
1959 | #endif | |
1960 | ); | |
1961 | ||
1962 | switch (mask) { | |
1963 | case (IXGBE_FLAG_RSS_ENABLED): | |
1964 | mrqc = IXGBE_MRQC_RSSEN; | |
1965 | break; | |
1966 | #ifdef CONFIG_IXGBE_DCB | |
1967 | case (IXGBE_FLAG_DCB_ENABLED): | |
1968 | mrqc = IXGBE_MRQC_RT8TCEN; | |
1969 | break; | |
1970 | #endif /* CONFIG_IXGBE_DCB */ | |
1971 | default: | |
1972 | break; | |
1973 | } | |
1974 | ||
1975 | return mrqc; | |
1976 | } | |
1977 | ||
9a799d71 | 1978 | /** |
3a581073 | 1979 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset |
9a799d71 AK |
1980 | * @adapter: board private structure |
1981 | * | |
1982 | * Configure the Rx unit of the MAC after a reset. | |
1983 | **/ | |
1984 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
1985 | { | |
1986 | u64 rdba; | |
1987 | struct ixgbe_hw *hw = &adapter->hw; | |
1988 | struct net_device *netdev = adapter->netdev; | |
1989 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
021230d4 | 1990 | int i, j; |
9a799d71 | 1991 | u32 rdlen, rxctrl, rxcsum; |
7c6e0a43 JB |
1992 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, |
1993 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, | |
1994 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
9a799d71 | 1995 | u32 fctrl, hlreg0; |
509ee935 | 1996 | u32 reta = 0, mrqc = 0; |
cc41ac7c | 1997 | u32 rdrxctl; |
f8212f97 | 1998 | u32 rscctrl; |
7c6e0a43 | 1999 | int rx_buf_len; |
9a799d71 AK |
2000 | |
2001 | /* Decide whether to use packet split mode or not */ | |
762f4c57 | 2002 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; |
9a799d71 | 2003 | |
eacd73f7 YZ |
2004 | #ifdef IXGBE_FCOE |
2005 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
2006 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
2007 | #endif /* IXGBE_FCOE */ | |
2008 | ||
9a799d71 AK |
2009 | /* Set the RX buffer length according to the mode */ |
2010 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
7c6e0a43 | 2011 | rx_buf_len = IXGBE_RX_HDR_SIZE; |
e8e26350 PW |
2012 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2013 | /* PSRTYPE must be initialized in 82599 */ | |
2014 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
2015 | IXGBE_PSRTYPE_UDPHDR | | |
2016 | IXGBE_PSRTYPE_IPV4HDR | | |
dfa12f05 YZ |
2017 | IXGBE_PSRTYPE_IPV6HDR | |
2018 | IXGBE_PSRTYPE_L2HDR; | |
e8e26350 PW |
2019 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype); |
2020 | } | |
9a799d71 | 2021 | } else { |
df647b5c | 2022 | if (!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED) && |
f8212f97 | 2023 | (netdev->mtu <= ETH_DATA_LEN)) |
7c6e0a43 | 2024 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; |
9a799d71 | 2025 | else |
7c6e0a43 | 2026 | rx_buf_len = ALIGN(max_frame, 1024); |
9a799d71 AK |
2027 | } |
2028 | ||
2029 | fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL); | |
2030 | fctrl |= IXGBE_FCTRL_BAM; | |
021230d4 | 2031 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ |
e8e26350 | 2032 | fctrl |= IXGBE_FCTRL_PMCF; |
9a799d71 AK |
2033 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl); |
2034 | ||
2035 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
2036 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
2037 | hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; | |
2038 | else | |
2039 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
63f39bd1 YZ |
2040 | #ifdef IXGBE_FCOE |
2041 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
2042 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
2043 | #endif | |
9a799d71 AK |
2044 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); |
2045 | ||
9a799d71 AK |
2046 | rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc); |
2047 | /* disable receives while setting up the descriptors */ | |
2048 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
2049 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
2050 | ||
0cefafad JB |
2051 | /* |
2052 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
2053 | * the Base and Length of the Rx Descriptor Ring | |
2054 | */ | |
9a799d71 AK |
2055 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2056 | rdba = adapter->rx_ring[i].dma; | |
7c6e0a43 | 2057 | j = adapter->rx_ring[i].reg_idx; |
284901a9 | 2058 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32))); |
7c6e0a43 JB |
2059 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32)); |
2060 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen); | |
2061 | IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0); | |
2062 | IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0); | |
2063 | adapter->rx_ring[i].head = IXGBE_RDH(j); | |
2064 | adapter->rx_ring[i].tail = IXGBE_RDT(j); | |
2065 | adapter->rx_ring[i].rx_buf_len = rx_buf_len; | |
cc41ac7c | 2066 | |
63f39bd1 YZ |
2067 | #ifdef IXGBE_FCOE |
2068 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
2069 | struct ixgbe_ring_feature *f; | |
2070 | f = &adapter->ring_feature[RING_F_FCOE]; | |
2071 | if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
2072 | (i >= f->mask) && (i < f->mask + f->indices)) | |
2073 | adapter->rx_ring[i].rx_buf_len = | |
2074 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2075 | } | |
2076 | ||
2077 | #endif /* IXGBE_FCOE */ | |
cc41ac7c | 2078 | ixgbe_configure_srrctl(adapter, j); |
9a799d71 AK |
2079 | } |
2080 | ||
e8e26350 PW |
2081 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2082 | /* | |
2083 | * For VMDq support of different descriptor types or | |
2084 | * buffer sizes through the use of multiple SRRCTL | |
2085 | * registers, RDRXCTL.MVMEN must be set to 1 | |
2086 | * | |
2087 | * also, the manual doesn't mention it clearly but DCA hints | |
2088 | * will only use queue 0's tags unless this bit is set. Side | |
2089 | * effects of setting this bit are only that SRRCTL must be | |
2090 | * fully programmed [0..15] | |
2091 | */ | |
2a41ff81 JB |
2092 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); |
2093 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
2094 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2f90b865 | 2095 | } |
177db6ff | 2096 | |
e8e26350 | 2097 | /* Program MRQC for the distribution of queues */ |
0cefafad | 2098 | mrqc = ixgbe_setup_mrqc(adapter); |
e8e26350 | 2099 | |
021230d4 | 2100 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
9a799d71 | 2101 | /* Fill out redirection table */ |
021230d4 AV |
2102 | for (i = 0, j = 0; i < 128; i++, j++) { |
2103 | if (j == adapter->ring_feature[RING_F_RSS].indices) | |
2104 | j = 0; | |
2105 | /* reta = 4-byte sliding window of | |
2106 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2107 | reta = (reta << 8) | (j * 0x11); | |
2108 | if ((i & 3) == 3) | |
2109 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
9a799d71 AK |
2110 | } |
2111 | ||
2112 | /* Fill out hash function seeds */ | |
2113 | for (i = 0; i < 10; i++) | |
7c6e0a43 | 2114 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); |
9a799d71 | 2115 | |
2a41ff81 JB |
2116 | if (hw->mac.type == ixgbe_mac_82598EB) |
2117 | mrqc |= IXGBE_MRQC_RSSEN; | |
9a799d71 | 2118 | /* Perform hash on these packet types */ |
2a41ff81 JB |
2119 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
2120 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2121 | | IXGBE_MRQC_RSS_FIELD_IPV4_UDP | |
2122 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2123 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP | |
2124 | | IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
021230d4 | 2125 | } |
2a41ff81 | 2126 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
9a799d71 | 2127 | |
021230d4 AV |
2128 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); |
2129 | ||
2130 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED || | |
2131 | adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) { | |
2132 | /* Disable indicating checksum in descriptor, enables | |
2133 | * RSS hash */ | |
9a799d71 | 2134 | rxcsum |= IXGBE_RXCSUM_PCSD; |
9a799d71 | 2135 | } |
021230d4 AV |
2136 | if (!(rxcsum & IXGBE_RXCSUM_PCSD)) { |
2137 | /* Enable IPv4 payload checksum for UDP fragments | |
2138 | * if PCSD is not set */ | |
2139 | rxcsum |= IXGBE_RXCSUM_IPPCSE; | |
2140 | } | |
2141 | ||
2142 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
e8e26350 PW |
2143 | |
2144 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2145 | rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
2146 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
f8212f97 | 2147 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; |
e8e26350 PW |
2148 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); |
2149 | } | |
f8212f97 | 2150 | |
df647b5c | 2151 | if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 AD |
2152 | /* Enable 82599 HW-RSC */ |
2153 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2154 | j = adapter->rx_ring[i].reg_idx; | |
2155 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j)); | |
2156 | rscctrl |= IXGBE_RSCCTL_RSCEN; | |
2157 | /* | |
e76678dd AD |
2158 | * we must limit the number of descriptors so that the |
2159 | * total size of max desc * buf_len is not greater | |
2160 | * than 65535 | |
f8212f97 | 2161 | */ |
e76678dd AD |
2162 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { |
2163 | #if (MAX_SKB_FRAGS > 16) | |
2164 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2165 | #elif (MAX_SKB_FRAGS > 8) | |
f8212f97 | 2166 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; |
e76678dd AD |
2167 | #elif (MAX_SKB_FRAGS > 4) |
2168 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
f8212f97 | 2169 | #else |
e76678dd | 2170 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; |
f8212f97 | 2171 | #endif |
e76678dd AD |
2172 | } else { |
2173 | if (rx_buf_len < IXGBE_RXBUFFER_4096) | |
2174 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2175 | else if (rx_buf_len < IXGBE_RXBUFFER_8192) | |
2176 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2177 | else | |
2178 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2179 | } | |
f8212f97 AD |
2180 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl); |
2181 | } | |
2182 | /* Disable RSC for ACK packets */ | |
2183 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
2184 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
2185 | } | |
9a799d71 AK |
2186 | } |
2187 | ||
068c89b0 DS |
2188 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
2189 | { | |
2190 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2191 | struct ixgbe_hw *hw = &adapter->hw; | |
2192 | ||
2193 | /* add VID to filter table */ | |
2194 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true); | |
2195 | } | |
2196 | ||
2197 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
2198 | { | |
2199 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2200 | struct ixgbe_hw *hw = &adapter->hw; | |
2201 | ||
2202 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2203 | ixgbe_irq_disable(adapter); | |
2204 | ||
2205 | vlan_group_set_device(adapter->vlgrp, vid, NULL); | |
2206 | ||
2207 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2208 | ixgbe_irq_enable(adapter); | |
2209 | ||
2210 | /* remove VID from filter table */ | |
2211 | hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false); | |
2212 | } | |
2213 | ||
9a799d71 | 2214 | static void ixgbe_vlan_rx_register(struct net_device *netdev, |
b4617240 | 2215 | struct vlan_group *grp) |
9a799d71 AK |
2216 | { |
2217 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2218 | u32 ctrl; | |
e8e26350 | 2219 | int i, j; |
9a799d71 | 2220 | |
d4f80882 AV |
2221 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2222 | ixgbe_irq_disable(adapter); | |
9a799d71 AK |
2223 | adapter->vlgrp = grp; |
2224 | ||
2f90b865 AD |
2225 | /* |
2226 | * For a DCB driver, always enable VLAN tag stripping so we can | |
2227 | * still receive traffic from a DCB-enabled host even if we're | |
2228 | * not in DCB mode. | |
2229 | */ | |
2230 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2231 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
2232 | ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2233 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2234 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
2235 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { | |
2236 | ctrl |= IXGBE_VLNCTRL_VFE; | |
9a799d71 AK |
2237 | /* enable VLAN tag insert/strip */ |
2238 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL); | |
9a799d71 AK |
2239 | ctrl &= ~IXGBE_VLNCTRL_CFIEN; |
2240 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl); | |
e8e26350 PW |
2241 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2242 | j = adapter->rx_ring[i].reg_idx; | |
2243 | ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j)); | |
2244 | ctrl |= IXGBE_RXDCTL_VME; | |
2245 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl); | |
2246 | } | |
9a799d71 | 2247 | } |
e8e26350 | 2248 | ixgbe_vlan_rx_add_vid(netdev, 0); |
9a799d71 | 2249 | |
d4f80882 AV |
2250 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2251 | ixgbe_irq_enable(adapter); | |
9a799d71 AK |
2252 | } |
2253 | ||
9a799d71 AK |
2254 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
2255 | { | |
2256 | ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp); | |
2257 | ||
2258 | if (adapter->vlgrp) { | |
2259 | u16 vid; | |
2260 | for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) { | |
2261 | if (!vlan_group_get_device(adapter->vlgrp, vid)) | |
2262 | continue; | |
2263 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
2264 | } | |
2265 | } | |
2266 | } | |
2267 | ||
2c5645cf CL |
2268 | static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq) |
2269 | { | |
2270 | struct dev_mc_list *mc_ptr; | |
2271 | u8 *addr = *mc_addr_ptr; | |
2272 | *vmdq = 0; | |
2273 | ||
2274 | mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]); | |
2275 | if (mc_ptr->next) | |
2276 | *mc_addr_ptr = mc_ptr->next->dmi_addr; | |
2277 | else | |
2278 | *mc_addr_ptr = NULL; | |
2279 | ||
2280 | return addr; | |
2281 | } | |
2282 | ||
9a799d71 | 2283 | /** |
2c5645cf | 2284 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
2285 | * @netdev: network interface device structure |
2286 | * | |
2c5645cf CL |
2287 | * The set_rx_method entry point is called whenever the unicast/multicast |
2288 | * address list or the network interface flags are updated. This routine is | |
2289 | * responsible for configuring the hardware for proper unicast, multicast and | |
2290 | * promiscuous mode. | |
9a799d71 | 2291 | **/ |
2c5645cf | 2292 | static void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
2293 | { |
2294 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2295 | struct ixgbe_hw *hw = &adapter->hw; | |
3d01625a | 2296 | u32 fctrl, vlnctrl; |
2c5645cf CL |
2297 | u8 *addr_list = NULL; |
2298 | int addr_count = 0; | |
9a799d71 AK |
2299 | |
2300 | /* Check for Promiscuous and All Multicast modes */ | |
2301 | ||
2302 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3d01625a | 2303 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
9a799d71 AK |
2304 | |
2305 | if (netdev->flags & IFF_PROMISC) { | |
2c5645cf | 2306 | hw->addr_ctrl.user_set_promisc = 1; |
9a799d71 | 2307 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
3d01625a | 2308 | vlnctrl &= ~IXGBE_VLNCTRL_VFE; |
9a799d71 | 2309 | } else { |
746b9f02 PM |
2310 | if (netdev->flags & IFF_ALLMULTI) { |
2311 | fctrl |= IXGBE_FCTRL_MPE; | |
2312 | fctrl &= ~IXGBE_FCTRL_UPE; | |
2313 | } else { | |
2314 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
2315 | } | |
3d01625a | 2316 | vlnctrl |= IXGBE_VLNCTRL_VFE; |
2c5645cf | 2317 | hw->addr_ctrl.user_set_promisc = 0; |
9a799d71 AK |
2318 | } |
2319 | ||
2320 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
3d01625a | 2321 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
9a799d71 | 2322 | |
2c5645cf | 2323 | /* reprogram secondary unicast list */ |
31278e71 | 2324 | hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list); |
9a799d71 | 2325 | |
2c5645cf CL |
2326 | /* reprogram multicast list */ |
2327 | addr_count = netdev->mc_count; | |
2328 | if (addr_count) | |
2329 | addr_list = netdev->mc_list->dmi_addr; | |
c44ade9e JB |
2330 | hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count, |
2331 | ixgbe_addr_list_itr); | |
9a799d71 AK |
2332 | } |
2333 | ||
021230d4 AV |
2334 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
2335 | { | |
2336 | int q_idx; | |
2337 | struct ixgbe_q_vector *q_vector; | |
2338 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2339 | ||
2340 | /* legacy and MSI only use one vector */ | |
2341 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2342 | q_vectors = 1; | |
2343 | ||
2344 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
f0848276 | 2345 | struct napi_struct *napi; |
7a921c93 | 2346 | q_vector = adapter->q_vector[q_idx]; |
f0848276 | 2347 | napi = &q_vector->napi; |
91281fd3 AD |
2348 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2349 | if (!q_vector->rxr_count || !q_vector->txr_count) { | |
2350 | if (q_vector->txr_count == 1) | |
2351 | napi->poll = &ixgbe_clean_txonly; | |
2352 | else if (q_vector->rxr_count == 1) | |
2353 | napi->poll = &ixgbe_clean_rxonly; | |
2354 | } | |
2355 | } | |
f0848276 JB |
2356 | |
2357 | napi_enable(napi); | |
021230d4 AV |
2358 | } |
2359 | } | |
2360 | ||
2361 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
2362 | { | |
2363 | int q_idx; | |
2364 | struct ixgbe_q_vector *q_vector; | |
2365 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
2366 | ||
2367 | /* legacy and MSI only use one vector */ | |
2368 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2369 | q_vectors = 1; | |
2370 | ||
2371 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 2372 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
2373 | napi_disable(&q_vector->napi); |
2374 | } | |
2375 | } | |
2376 | ||
7a6b6f51 | 2377 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2378 | /* |
2379 | * ixgbe_configure_dcb - Configure DCB hardware | |
2380 | * @adapter: ixgbe adapter struct | |
2381 | * | |
2382 | * This is called by the driver on open to configure the DCB hardware. | |
2383 | * This is also called by the gennetlink interface when reconfiguring | |
2384 | * the DCB state. | |
2385 | */ | |
2386 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
2387 | { | |
2388 | struct ixgbe_hw *hw = &adapter->hw; | |
2389 | u32 txdctl, vlnctrl; | |
2390 | int i, j; | |
2391 | ||
2392 | ixgbe_dcb_check_config(&adapter->dcb_cfg); | |
2393 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG); | |
2394 | ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG); | |
2395 | ||
2396 | /* reconfigure the hardware */ | |
2397 | ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg); | |
2398 | ||
2399 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2400 | j = adapter->tx_ring[i].reg_idx; | |
2401 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2402 | /* PThresh workaround for Tx hang with DFP enabled. */ | |
2403 | txdctl |= 32; | |
2404 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); | |
2405 | } | |
2406 | /* Enable VLAN tag insert/strip */ | |
2407 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
e8e26350 PW |
2408 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2409 | vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE; | |
2410 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2411 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2412 | } else if (hw->mac.type == ixgbe_mac_82599EB) { | |
2413 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
2414 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
2415 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
2416 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2417 | j = adapter->rx_ring[i].reg_idx; | |
2418 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2419 | vlnctrl |= IXGBE_RXDCTL_VME; | |
2420 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
2421 | } | |
2422 | } | |
2f90b865 AD |
2423 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
2424 | } | |
2425 | ||
2426 | #endif | |
9a799d71 AK |
2427 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
2428 | { | |
2429 | struct net_device *netdev = adapter->netdev; | |
c4cf55e5 | 2430 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
2431 | int i; |
2432 | ||
2c5645cf | 2433 | ixgbe_set_rx_mode(netdev); |
9a799d71 AK |
2434 | |
2435 | ixgbe_restore_vlan(adapter); | |
7a6b6f51 | 2436 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
2437 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
2438 | netif_set_gso_max_size(netdev, 32768); | |
2439 | ixgbe_configure_dcb(adapter); | |
2440 | } else { | |
2441 | netif_set_gso_max_size(netdev, 65536); | |
2442 | } | |
2443 | #else | |
2444 | netif_set_gso_max_size(netdev, 65536); | |
2445 | #endif | |
9a799d71 | 2446 | |
eacd73f7 YZ |
2447 | #ifdef IXGBE_FCOE |
2448 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
2449 | ixgbe_configure_fcoe(adapter); | |
2450 | ||
2451 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
2452 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
2453 | for (i = 0; i < adapter->num_tx_queues; i++) | |
2454 | adapter->tx_ring[i].atr_sample_rate = | |
2455 | adapter->atr_sample_rate; | |
2456 | ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc); | |
2457 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
2458 | ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc); | |
2459 | } | |
2460 | ||
9a799d71 AK |
2461 | ixgbe_configure_tx(adapter); |
2462 | ixgbe_configure_rx(adapter); | |
2463 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2464 | ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i], | |
b4617240 | 2465 | (adapter->rx_ring[i].count - 1)); |
9a799d71 AK |
2466 | } |
2467 | ||
e8e26350 PW |
2468 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2469 | { | |
2470 | switch (hw->phy.type) { | |
2471 | case ixgbe_phy_sfp_avago: | |
2472 | case ixgbe_phy_sfp_ftl: | |
2473 | case ixgbe_phy_sfp_intel: | |
2474 | case ixgbe_phy_sfp_unknown: | |
2475 | case ixgbe_phy_tw_tyco: | |
2476 | case ixgbe_phy_tw_unknown: | |
2477 | return true; | |
2478 | default: | |
2479 | return false; | |
2480 | } | |
2481 | } | |
2482 | ||
0ecc061d | 2483 | /** |
e8e26350 PW |
2484 | * ixgbe_sfp_link_config - set up SFP+ link |
2485 | * @adapter: pointer to private adapter struct | |
2486 | **/ | |
2487 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
2488 | { | |
2489 | struct ixgbe_hw *hw = &adapter->hw; | |
2490 | ||
2491 | if (hw->phy.multispeed_fiber) { | |
2492 | /* | |
2493 | * In multispeed fiber setups, the device may not have | |
2494 | * had a physical connection when the driver loaded. | |
2495 | * If that's the case, the initial link configuration | |
2496 | * couldn't get the MAC into 10G or 1G mode, so we'll | |
2497 | * never have a link status change interrupt fire. | |
2498 | * We need to try and force an autonegotiation | |
2499 | * session, then bring up link. | |
2500 | */ | |
2501 | hw->mac.ops.setup_sfp(hw); | |
2502 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) | |
2503 | schedule_work(&adapter->multispeed_fiber_task); | |
2504 | } else { | |
2505 | /* | |
2506 | * Direct Attach Cu and non-multispeed fiber modules | |
2507 | * still need to be configured properly prior to | |
2508 | * attempting link. | |
2509 | */ | |
2510 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK)) | |
2511 | schedule_work(&adapter->sfp_config_module_task); | |
2512 | } | |
2513 | } | |
2514 | ||
2515 | /** | |
2516 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
2517 | * @hw: pointer to private hardware struct |
2518 | * | |
2519 | * Returns 0 on success, negative on failure | |
2520 | **/ | |
e8e26350 | 2521 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
2522 | { |
2523 | u32 autoneg; | |
2524 | bool link_up = false; | |
2525 | u32 ret = IXGBE_ERR_LINK_SETUP; | |
2526 | ||
2527 | if (hw->mac.ops.check_link) | |
2528 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
2529 | ||
2530 | if (ret) | |
2531 | goto link_cfg_out; | |
2532 | ||
2533 | if (hw->mac.ops.get_link_capabilities) | |
2534 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, | |
2535 | &hw->mac.autoneg); | |
2536 | if (ret) | |
2537 | goto link_cfg_out; | |
2538 | ||
2539 | if (hw->mac.ops.setup_link_speed) | |
2540 | ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up); | |
0ecc061d PWJ |
2541 | link_cfg_out: |
2542 | return ret; | |
2543 | } | |
2544 | ||
e8e26350 PW |
2545 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2546 | static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2547 | int rxr) | |
2548 | { | |
2549 | int j = adapter->rx_ring[rxr].reg_idx; | |
2550 | int k; | |
2551 | ||
2552 | for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) { | |
2553 | if (IXGBE_READ_REG(&adapter->hw, | |
2554 | IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE) | |
2555 | break; | |
2556 | else | |
2557 | msleep(1); | |
2558 | } | |
2559 | if (k >= IXGBE_MAX_RX_DESC_POLL) { | |
2560 | DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d " | |
2561 | "not set within the polling period\n", rxr); | |
2562 | } | |
2563 | ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr], | |
2564 | (adapter->rx_ring[rxr].count - 1)); | |
2565 | } | |
2566 | ||
9a799d71 AK |
2567 | static int ixgbe_up_complete(struct ixgbe_adapter *adapter) |
2568 | { | |
2569 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 2570 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 | 2571 | int i, j = 0; |
e8e26350 | 2572 | int num_rx_rings = adapter->num_rx_queues; |
0ecc061d | 2573 | int err; |
9a799d71 | 2574 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 2575 | u32 txdctl, rxdctl, mhadd; |
e8e26350 | 2576 | u32 dmatxctl; |
021230d4 | 2577 | u32 gpie; |
9a799d71 | 2578 | |
5eba3699 AV |
2579 | ixgbe_get_hw_control(adapter); |
2580 | ||
021230d4 AV |
2581 | if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) || |
2582 | (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) { | |
9a799d71 AK |
2583 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
2584 | gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME | | |
b4617240 | 2585 | IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD); |
9a799d71 AK |
2586 | } else { |
2587 | /* MSI only */ | |
021230d4 | 2588 | gpie = 0; |
9a799d71 | 2589 | } |
021230d4 AV |
2590 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
2591 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
2592 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
9a799d71 AK |
2593 | } |
2594 | ||
021230d4 AV |
2595 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2596 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, | |
2597 | * specifically only auto mask tx and rx interrupts */ | |
2598 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
2599 | } | |
9a799d71 | 2600 | |
0befdb3e JB |
2601 | /* Enable fan failure interrupt if media type is copper */ |
2602 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2603 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2604 | gpie |= IXGBE_SDP1_GPIEN; | |
2605 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2606 | } | |
2607 | ||
e8e26350 PW |
2608 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2609 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
2610 | gpie |= IXGBE_SDP1_GPIEN; | |
2611 | gpie |= IXGBE_SDP2_GPIEN; | |
2612 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
2613 | } | |
2614 | ||
63f39bd1 YZ |
2615 | #ifdef IXGBE_FCOE |
2616 | /* adjust max frame to be able to do baby jumbo for FCoE */ | |
2617 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
2618 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
2619 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
2620 | ||
2621 | #endif /* IXGBE_FCOE */ | |
021230d4 | 2622 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
9a799d71 AK |
2623 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { |
2624 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2625 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2626 | ||
2627 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2628 | } | |
2629 | ||
2630 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
021230d4 AV |
2631 | j = adapter->tx_ring[i].reg_idx; |
2632 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
e01c31a5 JB |
2633 | /* enable WTHRESH=8 descriptors, to encourage burst writeback */ |
2634 | txdctl |= (8 << 16); | |
e8e26350 PW |
2635 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
2636 | } | |
2637 | ||
2638 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
2639 | /* DMATXCTL.EN must be set after all Tx queue config is done */ | |
2640 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2641 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2642 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2643 | } | |
2644 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2645 | j = adapter->tx_ring[i].reg_idx; | |
2646 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
9a799d71 | 2647 | txdctl |= IXGBE_TXDCTL_ENABLE; |
021230d4 | 2648 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl); |
9a799d71 AK |
2649 | } |
2650 | ||
e8e26350 | 2651 | for (i = 0; i < num_rx_rings; i++) { |
021230d4 AV |
2652 | j = adapter->rx_ring[i].reg_idx; |
2653 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
2654 | /* enable PTHRESH=32 descriptors (half the internal cache) | |
2655 | * and HTHRESH=0 descriptors (to minimize latency on fetch), | |
2656 | * this also removes a pesky rx_no_buffer_count increment */ | |
2657 | rxdctl |= 0x0020; | |
9a799d71 | 2658 | rxdctl |= IXGBE_RXDCTL_ENABLE; |
021230d4 | 2659 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl); |
e8e26350 PW |
2660 | if (hw->mac.type == ixgbe_mac_82599EB) |
2661 | ixgbe_rx_desc_queue_enable(adapter, i); | |
9a799d71 AK |
2662 | } |
2663 | /* enable all receives */ | |
2664 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
e8e26350 PW |
2665 | if (hw->mac.type == ixgbe_mac_82598EB) |
2666 | rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN); | |
2667 | else | |
2668 | rxdctl |= IXGBE_RXCTRL_RXEN; | |
2669 | hw->mac.ops.enable_rx_dma(hw, rxdctl); | |
9a799d71 AK |
2670 | |
2671 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
2672 | ixgbe_configure_msix(adapter); | |
2673 | else | |
2674 | ixgbe_configure_msi_and_legacy(adapter); | |
2675 | ||
2676 | clear_bit(__IXGBE_DOWN, &adapter->state); | |
021230d4 AV |
2677 | ixgbe_napi_enable_all(adapter); |
2678 | ||
2679 | /* clear any pending interrupts, may auto mask */ | |
2680 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
2681 | ||
9a799d71 AK |
2682 | ixgbe_irq_enable(adapter); |
2683 | ||
bf069c97 DS |
2684 | /* |
2685 | * If this adapter has a fan, check to see if we had a failure | |
2686 | * before we enabled the interrupt. | |
2687 | */ | |
2688 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
2689 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
2690 | if (esdp & IXGBE_ESDP_SDP1) | |
2691 | DPRINTK(DRV, CRIT, | |
2692 | "Fan has stopped, replace the adapter\n"); | |
2693 | } | |
2694 | ||
e8e26350 PW |
2695 | /* |
2696 | * For hot-pluggable SFP+ devices, a new SFP+ module may have | |
2697 | * arrived before interrupts were enabled. We need to kick off | |
2698 | * the SFP+ module setup first, then try to bring up link. | |
2699 | * If we're not hot-pluggable SFP+, we just need to configure link | |
2700 | * and bring it up. | |
2701 | */ | |
2702 | err = hw->phy.ops.identify(hw); | |
2703 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
2704 | dev_err(&adapter->pdev->dev, "failed to initialize because " |
2705 | "an unsupported SFP+ module type was detected.\n" | |
2706 | "Reload the driver after installing a supported " | |
2707 | "module.\n"); | |
e8e26350 PW |
2708 | ixgbe_down(adapter); |
2709 | return err; | |
2710 | } | |
2711 | ||
2712 | if (ixgbe_is_sfp(hw)) { | |
2713 | ixgbe_sfp_link_config(adapter); | |
2714 | } else { | |
2715 | err = ixgbe_non_sfp_link_config(hw); | |
2716 | if (err) | |
2717 | DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err); | |
2718 | } | |
0ecc061d | 2719 | |
c4cf55e5 PWJ |
2720 | for (i = 0; i < adapter->num_tx_queues; i++) |
2721 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
2722 | &(adapter->tx_ring[i].reinit_state)); | |
2723 | ||
1da100bb PWJ |
2724 | /* enable transmits */ |
2725 | netif_tx_start_all_queues(netdev); | |
2726 | ||
9a799d71 AK |
2727 | /* bring the link up in the watchdog, this could race with our first |
2728 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
2729 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
2730 | adapter->link_check_timeout = jiffies; | |
9a799d71 AK |
2731 | mod_timer(&adapter->watchdog_timer, jiffies); |
2732 | return 0; | |
2733 | } | |
2734 | ||
d4f80882 AV |
2735 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
2736 | { | |
2737 | WARN_ON(in_interrupt()); | |
2738 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) | |
2739 | msleep(1); | |
2740 | ixgbe_down(adapter); | |
2741 | ixgbe_up(adapter); | |
2742 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
2743 | } | |
2744 | ||
9a799d71 AK |
2745 | int ixgbe_up(struct ixgbe_adapter *adapter) |
2746 | { | |
2747 | /* hardware has been reset, we need to reload some things */ | |
2748 | ixgbe_configure(adapter); | |
2749 | ||
2750 | return ixgbe_up_complete(adapter); | |
2751 | } | |
2752 | ||
2753 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
2754 | { | |
c44ade9e | 2755 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
2756 | int err; |
2757 | ||
2758 | err = hw->mac.ops.init_hw(hw); | |
da4dd0f7 PWJ |
2759 | switch (err) { |
2760 | case 0: | |
2761 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
2762 | break; | |
2763 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
2764 | dev_err(&adapter->pdev->dev, "master disable timed out\n"); | |
2765 | break; | |
794caeb2 PWJ |
2766 | case IXGBE_ERR_EEPROM_VERSION: |
2767 | /* We are running on a pre-production device, log a warning */ | |
2768 | dev_warn(&adapter->pdev->dev, "This device is a pre-production " | |
2769 | "adapter/LOM. Please be aware there may be issues " | |
2770 | "associated with your hardware. If you are " | |
2771 | "experiencing problems please contact your Intel or " | |
2772 | "hardware representative who provided you with this " | |
2773 | "hardware.\n"); | |
2774 | break; | |
da4dd0f7 PWJ |
2775 | default: |
2776 | dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err); | |
2777 | } | |
9a799d71 AK |
2778 | |
2779 | /* reprogram the RAR[0] in case user changed it. */ | |
c44ade9e | 2780 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
2781 | } |
2782 | ||
9a799d71 AK |
2783 | /** |
2784 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
2785 | * @adapter: board private structure | |
2786 | * @rx_ring: ring to free buffers from | |
2787 | **/ | |
2788 | static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2789 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
2790 | { |
2791 | struct pci_dev *pdev = adapter->pdev; | |
2792 | unsigned long size; | |
2793 | unsigned int i; | |
2794 | ||
2795 | /* Free all the Rx ring sk_buffs */ | |
2796 | ||
2797 | for (i = 0; i < rx_ring->count; i++) { | |
2798 | struct ixgbe_rx_buffer *rx_buffer_info; | |
2799 | ||
2800 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
2801 | if (rx_buffer_info->dma) { | |
2802 | pci_unmap_single(pdev, rx_buffer_info->dma, | |
b4617240 PW |
2803 | rx_ring->rx_buf_len, |
2804 | PCI_DMA_FROMDEVICE); | |
9a799d71 AK |
2805 | rx_buffer_info->dma = 0; |
2806 | } | |
2807 | if (rx_buffer_info->skb) { | |
f8212f97 | 2808 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 2809 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
2810 | do { |
2811 | struct sk_buff *this = skb; | |
2812 | skb = skb->prev; | |
2813 | dev_kfree_skb(this); | |
2814 | } while (skb); | |
9a799d71 AK |
2815 | } |
2816 | if (!rx_buffer_info->page) | |
2817 | continue; | |
762f4c57 JB |
2818 | pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2, |
2819 | PCI_DMA_FROMDEVICE); | |
9a799d71 | 2820 | rx_buffer_info->page_dma = 0; |
9a799d71 AK |
2821 | put_page(rx_buffer_info->page); |
2822 | rx_buffer_info->page = NULL; | |
762f4c57 | 2823 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
2824 | } |
2825 | ||
2826 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
2827 | memset(rx_ring->rx_buffer_info, 0, size); | |
2828 | ||
2829 | /* Zero out the descriptor ring */ | |
2830 | memset(rx_ring->desc, 0, rx_ring->size); | |
2831 | ||
2832 | rx_ring->next_to_clean = 0; | |
2833 | rx_ring->next_to_use = 0; | |
2834 | ||
9891ca7c JB |
2835 | if (rx_ring->head) |
2836 | writel(0, adapter->hw.hw_addr + rx_ring->head); | |
2837 | if (rx_ring->tail) | |
2838 | writel(0, adapter->hw.hw_addr + rx_ring->tail); | |
9a799d71 AK |
2839 | } |
2840 | ||
2841 | /** | |
2842 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
2843 | * @adapter: board private structure | |
2844 | * @tx_ring: ring to be cleaned | |
2845 | **/ | |
2846 | static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter, | |
b4617240 | 2847 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
2848 | { |
2849 | struct ixgbe_tx_buffer *tx_buffer_info; | |
2850 | unsigned long size; | |
2851 | unsigned int i; | |
2852 | ||
2853 | /* Free all the Tx ring sk_buffs */ | |
2854 | ||
2855 | for (i = 0; i < tx_ring->count; i++) { | |
2856 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
2857 | ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); | |
2858 | } | |
2859 | ||
2860 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
2861 | memset(tx_ring->tx_buffer_info, 0, size); | |
2862 | ||
2863 | /* Zero out the descriptor ring */ | |
2864 | memset(tx_ring->desc, 0, tx_ring->size); | |
2865 | ||
2866 | tx_ring->next_to_use = 0; | |
2867 | tx_ring->next_to_clean = 0; | |
2868 | ||
9891ca7c JB |
2869 | if (tx_ring->head) |
2870 | writel(0, adapter->hw.hw_addr + tx_ring->head); | |
2871 | if (tx_ring->tail) | |
2872 | writel(0, adapter->hw.hw_addr + tx_ring->tail); | |
9a799d71 AK |
2873 | } |
2874 | ||
2875 | /** | |
021230d4 | 2876 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
2877 | * @adapter: board private structure |
2878 | **/ | |
021230d4 | 2879 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2880 | { |
2881 | int i; | |
2882 | ||
021230d4 AV |
2883 | for (i = 0; i < adapter->num_rx_queues; i++) |
2884 | ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
2885 | } |
2886 | ||
2887 | /** | |
021230d4 | 2888 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
2889 | * @adapter: board private structure |
2890 | **/ | |
021230d4 | 2891 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2892 | { |
2893 | int i; | |
2894 | ||
021230d4 AV |
2895 | for (i = 0; i < adapter->num_tx_queues; i++) |
2896 | ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
2897 | } |
2898 | ||
2899 | void ixgbe_down(struct ixgbe_adapter *adapter) | |
2900 | { | |
2901 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 2902 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 2903 | u32 rxctrl; |
7f821875 JB |
2904 | u32 txdctl; |
2905 | int i, j; | |
9a799d71 AK |
2906 | |
2907 | /* signal that we are down to the interrupt handler */ | |
2908 | set_bit(__IXGBE_DOWN, &adapter->state); | |
2909 | ||
2910 | /* disable receives */ | |
7f821875 JB |
2911 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
2912 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 AK |
2913 | |
2914 | netif_tx_disable(netdev); | |
2915 | ||
7f821875 | 2916 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
2917 | msleep(10); |
2918 | ||
7f821875 JB |
2919 | netif_tx_stop_all_queues(netdev); |
2920 | ||
9a799d71 AK |
2921 | ixgbe_irq_disable(adapter); |
2922 | ||
021230d4 | 2923 | ixgbe_napi_disable_all(adapter); |
7f821875 | 2924 | |
9a799d71 | 2925 | del_timer_sync(&adapter->watchdog_timer); |
cf8280ee | 2926 | cancel_work_sync(&adapter->watchdog_task); |
9a799d71 | 2927 | |
c4cf55e5 PWJ |
2928 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
2929 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
2930 | cancel_work_sync(&adapter->fdir_reinit_task); | |
2931 | ||
7f821875 JB |
2932 | /* disable transmits in the hardware now that interrupts are off */ |
2933 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2934 | j = adapter->tx_ring[i].reg_idx; | |
2935 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j)); | |
2936 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), | |
2937 | (txdctl & ~IXGBE_TXDCTL_ENABLE)); | |
2938 | } | |
88512539 PW |
2939 | /* Disable the Tx DMA engine on 82599 */ |
2940 | if (hw->mac.type == ixgbe_mac_82599EB) | |
2941 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, | |
2942 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & | |
2943 | ~IXGBE_DMATXCTL_TE)); | |
7f821875 | 2944 | |
9a799d71 | 2945 | netif_carrier_off(netdev); |
9a799d71 | 2946 | |
6f4a0e45 PL |
2947 | if (!pci_channel_offline(adapter->pdev)) |
2948 | ixgbe_reset(adapter); | |
9a799d71 AK |
2949 | ixgbe_clean_all_tx_rings(adapter); |
2950 | ixgbe_clean_all_rx_rings(adapter); | |
2951 | ||
5dd2d332 | 2952 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 2953 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 2954 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 2955 | #endif |
9a799d71 AK |
2956 | } |
2957 | ||
9a799d71 | 2958 | /** |
021230d4 AV |
2959 | * ixgbe_poll - NAPI Rx polling callback |
2960 | * @napi: structure for representing this polling device | |
2961 | * @budget: how many packets driver is allowed to clean | |
2962 | * | |
2963 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 2964 | **/ |
021230d4 | 2965 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 2966 | { |
9a1a69ad JB |
2967 | struct ixgbe_q_vector *q_vector = |
2968 | container_of(napi, struct ixgbe_q_vector, napi); | |
021230d4 | 2969 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a1a69ad | 2970 | int tx_clean_complete, work_done = 0; |
9a799d71 | 2971 | |
5dd2d332 | 2972 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
2973 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
2974 | ixgbe_update_tx_dca(adapter, adapter->tx_ring); | |
2975 | ixgbe_update_rx_dca(adapter, adapter->rx_ring); | |
2976 | } | |
2977 | #endif | |
2978 | ||
fe49f04a | 2979 | tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring); |
78b6f4ce | 2980 | ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget); |
9a799d71 | 2981 | |
9a1a69ad | 2982 | if (!tx_clean_complete) |
d2c7ddd6 DM |
2983 | work_done = budget; |
2984 | ||
53e52c72 DM |
2985 | /* If budget not fully consumed, exit the polling mode */ |
2986 | if (work_done < budget) { | |
288379f0 | 2987 | napi_complete(napi); |
509ee935 | 2988 | if (adapter->itr_setting & 1) |
f494e8fa | 2989 | ixgbe_set_itr(adapter); |
d4f80882 | 2990 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
835462fc | 2991 | ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2992 | } |
9a799d71 AK |
2993 | return work_done; |
2994 | } | |
2995 | ||
2996 | /** | |
2997 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
2998 | * @netdev: network interface device structure | |
2999 | **/ | |
3000 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
3001 | { | |
3002 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3003 | ||
3004 | /* Do the reset outside of interrupt context */ | |
3005 | schedule_work(&adapter->reset_task); | |
3006 | } | |
3007 | ||
3008 | static void ixgbe_reset_task(struct work_struct *work) | |
3009 | { | |
3010 | struct ixgbe_adapter *adapter; | |
3011 | adapter = container_of(work, struct ixgbe_adapter, reset_task); | |
3012 | ||
2f90b865 AD |
3013 | /* If we're already down or resetting, just bail */ |
3014 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
3015 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
3016 | return; | |
3017 | ||
9a799d71 AK |
3018 | adapter->tx_timeout_count++; |
3019 | ||
d4f80882 | 3020 | ixgbe_reinit_locked(adapter); |
9a799d71 AK |
3021 | } |
3022 | ||
bc97114d PWJ |
3023 | #ifdef CONFIG_IXGBE_DCB |
3024 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
b9804972 | 3025 | { |
bc97114d | 3026 | bool ret = false; |
0cefafad | 3027 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB]; |
b9804972 | 3028 | |
0cefafad JB |
3029 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) |
3030 | return ret; | |
3031 | ||
3032 | f->mask = 0x7 << 3; | |
3033 | adapter->num_rx_queues = f->indices; | |
3034 | adapter->num_tx_queues = f->indices; | |
3035 | ret = true; | |
2f90b865 | 3036 | |
bc97114d PWJ |
3037 | return ret; |
3038 | } | |
3039 | #endif | |
3040 | ||
4df10466 JB |
3041 | /** |
3042 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
3043 | * @adapter: board private structure to initialize | |
3044 | * | |
3045 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
3046 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
3047 | * | |
3048 | **/ | |
bc97114d PWJ |
3049 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
3050 | { | |
3051 | bool ret = false; | |
0cefafad | 3052 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
3053 | |
3054 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
3055 | f->mask = 0xF; |
3056 | adapter->num_rx_queues = f->indices; | |
3057 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
3058 | ret = true; |
3059 | } else { | |
bc97114d | 3060 | ret = false; |
b9804972 JB |
3061 | } |
3062 | ||
bc97114d PWJ |
3063 | return ret; |
3064 | } | |
3065 | ||
c4cf55e5 PWJ |
3066 | /** |
3067 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
3068 | * @adapter: board private structure to initialize | |
3069 | * | |
3070 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
3071 | * to the original CPU that initiated the Tx session. This runs in addition | |
3072 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
3073 | * Rx load across CPUs using RSS. | |
3074 | * | |
3075 | **/ | |
3076 | static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) | |
3077 | { | |
3078 | bool ret = false; | |
3079 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
3080 | ||
3081 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
3082 | f_fdir->mask = 0; | |
3083 | ||
3084 | /* Flow Director must have RSS enabled */ | |
3085 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
3086 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3087 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) { | |
3088 | adapter->num_tx_queues = f_fdir->indices; | |
3089 | adapter->num_rx_queues = f_fdir->indices; | |
3090 | ret = true; | |
3091 | } else { | |
3092 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
3093 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
3094 | } | |
3095 | return ret; | |
3096 | } | |
3097 | ||
0331a832 YZ |
3098 | #ifdef IXGBE_FCOE |
3099 | /** | |
3100 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
3101 | * @adapter: board private structure to initialize | |
3102 | * | |
3103 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
3104 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
3105 | * rx queues out of the max number of rx queues, instead, it is used as the | |
3106 | * index of the first rx queue used by FCoE. | |
3107 | * | |
3108 | **/ | |
3109 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
3110 | { | |
3111 | bool ret = false; | |
3112 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3113 | ||
3114 | f->indices = min((int)num_online_cpus(), f->indices); | |
3115 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
3116 | #ifdef CONFIG_IXGBE_DCB | |
3117 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3118 | DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n"); | |
3119 | ixgbe_set_dcb_queues(adapter); | |
3120 | } | |
3121 | #endif | |
3122 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3123 | DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n"); | |
3124 | ixgbe_set_rss_queues(adapter); | |
3125 | } | |
3126 | /* adding FCoE rx rings to the end */ | |
3127 | f->mask = adapter->num_rx_queues; | |
3128 | adapter->num_rx_queues += f->indices; | |
3129 | if (adapter->num_tx_queues == 0) | |
3130 | adapter->num_tx_queues = f->indices; | |
3131 | ||
3132 | ret = true; | |
3133 | } | |
3134 | ||
3135 | return ret; | |
3136 | } | |
3137 | ||
3138 | #endif /* IXGBE_FCOE */ | |
4df10466 JB |
3139 | /* |
3140 | * ixgbe_set_num_queues: Allocate queues for device, feature dependant | |
3141 | * @adapter: board private structure to initialize | |
3142 | * | |
3143 | * This is the top level queue allocation routine. The order here is very | |
3144 | * important, starting with the "most" number of features turned on at once, | |
3145 | * and ending with the smallest set of features. This way large combinations | |
3146 | * can be allocated if they're turned on, and smaller combinations are the | |
3147 | * fallthrough conditions. | |
3148 | * | |
3149 | **/ | |
bc97114d PWJ |
3150 | static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
3151 | { | |
0331a832 YZ |
3152 | #ifdef IXGBE_FCOE |
3153 | if (ixgbe_set_fcoe_queues(adapter)) | |
3154 | goto done; | |
3155 | ||
3156 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3157 | #ifdef CONFIG_IXGBE_DCB |
3158 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 3159 | goto done; |
bc97114d PWJ |
3160 | |
3161 | #endif | |
c4cf55e5 PWJ |
3162 | if (ixgbe_set_fdir_queues(adapter)) |
3163 | goto done; | |
3164 | ||
bc97114d | 3165 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
3166 | goto done; |
3167 | ||
3168 | /* fallback to base case */ | |
3169 | adapter->num_rx_queues = 1; | |
3170 | adapter->num_tx_queues = 1; | |
3171 | ||
3172 | done: | |
3173 | /* Notify the stack of the (possibly) reduced Tx Queue count. */ | |
3174 | adapter->netdev->real_num_tx_queues = adapter->num_tx_queues; | |
b9804972 JB |
3175 | } |
3176 | ||
021230d4 | 3177 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
b4617240 | 3178 | int vectors) |
021230d4 AV |
3179 | { |
3180 | int err, vector_threshold; | |
3181 | ||
3182 | /* We'll want at least 3 (vector_threshold): | |
3183 | * 1) TxQ[0] Cleanup | |
3184 | * 2) RxQ[0] Cleanup | |
3185 | * 3) Other (Link Status Change, etc.) | |
3186 | * 4) TCP Timer (optional) | |
3187 | */ | |
3188 | vector_threshold = MIN_MSIX_COUNT; | |
3189 | ||
3190 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
3191 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
3192 | * Right now, we simply care about how many we'll get; we'll | |
3193 | * set them up later while requesting irq's. | |
3194 | */ | |
3195 | while (vectors >= vector_threshold) { | |
3196 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
b4617240 | 3197 | vectors); |
021230d4 AV |
3198 | if (!err) /* Success in acquiring all requested vectors. */ |
3199 | break; | |
3200 | else if (err < 0) | |
3201 | vectors = 0; /* Nasty failure, quit now */ | |
3202 | else /* err == number of vectors we should try again with */ | |
3203 | vectors = err; | |
3204 | } | |
3205 | ||
3206 | if (vectors < vector_threshold) { | |
3207 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
3208 | * This just means we'll go with either a single MSI | |
3209 | * vector or fall back to legacy interrupts. | |
3210 | */ | |
3211 | DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n"); | |
3212 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3213 | kfree(adapter->msix_entries); | |
3214 | adapter->msix_entries = NULL; | |
021230d4 AV |
3215 | } else { |
3216 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
3217 | /* |
3218 | * Adjust for only the vectors we'll use, which is minimum | |
3219 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
3220 | * vectors we were allocated. | |
3221 | */ | |
3222 | adapter->num_msix_vectors = min(vectors, | |
3223 | adapter->max_msix_q_vectors + NON_Q_VECTORS); | |
021230d4 AV |
3224 | } |
3225 | } | |
3226 | ||
021230d4 | 3227 | /** |
bc97114d | 3228 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
3229 | * @adapter: board private structure to initialize |
3230 | * | |
bc97114d PWJ |
3231 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
3232 | * | |
021230d4 | 3233 | **/ |
bc97114d | 3234 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 3235 | { |
bc97114d PWJ |
3236 | int i; |
3237 | bool ret = false; | |
3238 | ||
3239 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3240 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3241 | adapter->rx_ring[i].reg_idx = i; | |
3242 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3243 | adapter->tx_ring[i].reg_idx = i; | |
3244 | ret = true; | |
3245 | } else { | |
3246 | ret = false; | |
3247 | } | |
3248 | ||
3249 | return ret; | |
3250 | } | |
3251 | ||
3252 | #ifdef CONFIG_IXGBE_DCB | |
3253 | /** | |
3254 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
3255 | * @adapter: board private structure to initialize | |
3256 | * | |
3257 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
3258 | * | |
3259 | **/ | |
3260 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
3261 | { | |
3262 | int i; | |
3263 | bool ret = false; | |
3264 | int dcb_i = adapter->ring_feature[RING_F_DCB].indices; | |
3265 | ||
3266 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3267 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { | |
2f90b865 AD |
3268 | /* the number of queues is assumed to be symmetric */ |
3269 | for (i = 0; i < dcb_i; i++) { | |
3270 | adapter->rx_ring[i].reg_idx = i << 3; | |
3271 | adapter->tx_ring[i].reg_idx = i << 2; | |
3272 | } | |
bc97114d | 3273 | ret = true; |
e8e26350 | 3274 | } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) { |
f92ef202 PW |
3275 | if (dcb_i == 8) { |
3276 | /* | |
3277 | * Tx TC0 starts at: descriptor queue 0 | |
3278 | * Tx TC1 starts at: descriptor queue 32 | |
3279 | * Tx TC2 starts at: descriptor queue 64 | |
3280 | * Tx TC3 starts at: descriptor queue 80 | |
3281 | * Tx TC4 starts at: descriptor queue 96 | |
3282 | * Tx TC5 starts at: descriptor queue 104 | |
3283 | * Tx TC6 starts at: descriptor queue 112 | |
3284 | * Tx TC7 starts at: descriptor queue 120 | |
3285 | * | |
3286 | * Rx TC0-TC7 are offset by 16 queues each | |
3287 | */ | |
3288 | for (i = 0; i < 3; i++) { | |
3289 | adapter->tx_ring[i].reg_idx = i << 5; | |
3290 | adapter->rx_ring[i].reg_idx = i << 4; | |
3291 | } | |
3292 | for ( ; i < 5; i++) { | |
3293 | adapter->tx_ring[i].reg_idx = | |
3294 | ((i + 2) << 4); | |
3295 | adapter->rx_ring[i].reg_idx = i << 4; | |
3296 | } | |
3297 | for ( ; i < dcb_i; i++) { | |
3298 | adapter->tx_ring[i].reg_idx = | |
3299 | ((i + 8) << 3); | |
3300 | adapter->rx_ring[i].reg_idx = i << 4; | |
3301 | } | |
3302 | ||
3303 | ret = true; | |
3304 | } else if (dcb_i == 4) { | |
3305 | /* | |
3306 | * Tx TC0 starts at: descriptor queue 0 | |
3307 | * Tx TC1 starts at: descriptor queue 64 | |
3308 | * Tx TC2 starts at: descriptor queue 96 | |
3309 | * Tx TC3 starts at: descriptor queue 112 | |
3310 | * | |
3311 | * Rx TC0-TC3 are offset by 32 queues each | |
3312 | */ | |
3313 | adapter->tx_ring[0].reg_idx = 0; | |
3314 | adapter->tx_ring[1].reg_idx = 64; | |
3315 | adapter->tx_ring[2].reg_idx = 96; | |
3316 | adapter->tx_ring[3].reg_idx = 112; | |
3317 | for (i = 0 ; i < dcb_i; i++) | |
3318 | adapter->rx_ring[i].reg_idx = i << 5; | |
3319 | ||
3320 | ret = true; | |
3321 | } else { | |
3322 | ret = false; | |
e8e26350 | 3323 | } |
bc97114d PWJ |
3324 | } else { |
3325 | ret = false; | |
021230d4 | 3326 | } |
bc97114d PWJ |
3327 | } else { |
3328 | ret = false; | |
021230d4 | 3329 | } |
bc97114d PWJ |
3330 | |
3331 | return ret; | |
3332 | } | |
3333 | #endif | |
3334 | ||
c4cf55e5 PWJ |
3335 | /** |
3336 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
3337 | * @adapter: board private structure to initialize | |
3338 | * | |
3339 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
3340 | * | |
3341 | **/ | |
3342 | static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) | |
3343 | { | |
3344 | int i; | |
3345 | bool ret = false; | |
3346 | ||
3347 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED && | |
3348 | ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) || | |
3349 | (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) { | |
3350 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3351 | adapter->rx_ring[i].reg_idx = i; | |
3352 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3353 | adapter->tx_ring[i].reg_idx = i; | |
3354 | ret = true; | |
3355 | } | |
3356 | ||
3357 | return ret; | |
3358 | } | |
3359 | ||
0331a832 YZ |
3360 | #ifdef IXGBE_FCOE |
3361 | /** | |
3362 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
3363 | * @adapter: board private structure to initialize | |
3364 | * | |
3365 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
3366 | * | |
3367 | */ | |
3368 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
3369 | { | |
3370 | int i, fcoe_i = 0; | |
3371 | bool ret = false; | |
3372 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; | |
3373 | ||
3374 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
3375 | #ifdef CONFIG_IXGBE_DCB | |
3376 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
3377 | ixgbe_cache_ring_dcb(adapter); | |
3378 | fcoe_i = adapter->rx_ring[0].reg_idx + 1; | |
3379 | } | |
3380 | #endif /* CONFIG_IXGBE_DCB */ | |
3381 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
3382 | ixgbe_cache_ring_rss(adapter); | |
3383 | fcoe_i = f->mask; | |
3384 | } | |
3385 | for (i = 0; i < f->indices; i++, fcoe_i++) | |
3386 | adapter->rx_ring[f->mask + i].reg_idx = fcoe_i; | |
3387 | ret = true; | |
3388 | } | |
3389 | return ret; | |
3390 | } | |
3391 | ||
3392 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3393 | /** |
3394 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
3395 | * @adapter: board private structure to initialize | |
3396 | * | |
3397 | * Once we know the feature-set enabled for the device, we'll cache | |
3398 | * the register offset the descriptor ring is assigned to. | |
3399 | * | |
3400 | * Note, the order the various feature calls is important. It must start with | |
3401 | * the "most" features enabled at the same time, then trickle down to the | |
3402 | * least amount of features turned on at once. | |
3403 | **/ | |
3404 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
3405 | { | |
3406 | /* start with default case */ | |
3407 | adapter->rx_ring[0].reg_idx = 0; | |
3408 | adapter->tx_ring[0].reg_idx = 0; | |
3409 | ||
0331a832 YZ |
3410 | #ifdef IXGBE_FCOE |
3411 | if (ixgbe_cache_ring_fcoe(adapter)) | |
3412 | return; | |
3413 | ||
3414 | #endif /* IXGBE_FCOE */ | |
bc97114d PWJ |
3415 | #ifdef CONFIG_IXGBE_DCB |
3416 | if (ixgbe_cache_ring_dcb(adapter)) | |
3417 | return; | |
3418 | ||
3419 | #endif | |
c4cf55e5 PWJ |
3420 | if (ixgbe_cache_ring_fdir(adapter)) |
3421 | return; | |
3422 | ||
bc97114d PWJ |
3423 | if (ixgbe_cache_ring_rss(adapter)) |
3424 | return; | |
021230d4 AV |
3425 | } |
3426 | ||
9a799d71 AK |
3427 | /** |
3428 | * ixgbe_alloc_queues - Allocate memory for all rings | |
3429 | * @adapter: board private structure to initialize | |
3430 | * | |
3431 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
3432 | * number of queues at compile-time. The polling_netdev array is |
3433 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 3434 | **/ |
2f90b865 | 3435 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3436 | { |
3437 | int i; | |
3438 | ||
3439 | adapter->tx_ring = kcalloc(adapter->num_tx_queues, | |
b4617240 | 3440 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
9a799d71 | 3441 | if (!adapter->tx_ring) |
021230d4 | 3442 | goto err_tx_ring_allocation; |
9a799d71 AK |
3443 | |
3444 | adapter->rx_ring = kcalloc(adapter->num_rx_queues, | |
b4617240 | 3445 | sizeof(struct ixgbe_ring), GFP_KERNEL); |
021230d4 AV |
3446 | if (!adapter->rx_ring) |
3447 | goto err_rx_ring_allocation; | |
9a799d71 | 3448 | |
021230d4 | 3449 | for (i = 0; i < adapter->num_tx_queues; i++) { |
b9804972 | 3450 | adapter->tx_ring[i].count = adapter->tx_ring_count; |
021230d4 AV |
3451 | adapter->tx_ring[i].queue_index = i; |
3452 | } | |
b9804972 | 3453 | |
9a799d71 | 3454 | for (i = 0; i < adapter->num_rx_queues; i++) { |
b9804972 | 3455 | adapter->rx_ring[i].count = adapter->rx_ring_count; |
021230d4 AV |
3456 | adapter->rx_ring[i].queue_index = i; |
3457 | } | |
3458 | ||
3459 | ixgbe_cache_ring_register(adapter); | |
3460 | ||
3461 | return 0; | |
3462 | ||
3463 | err_rx_ring_allocation: | |
3464 | kfree(adapter->tx_ring); | |
3465 | err_tx_ring_allocation: | |
3466 | return -ENOMEM; | |
3467 | } | |
3468 | ||
3469 | /** | |
3470 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
3471 | * @adapter: board private structure to initialize | |
3472 | * | |
3473 | * Attempt to configure the interrupts using the best available | |
3474 | * capabilities of the hardware and the kernel. | |
3475 | **/ | |
feea6a57 | 3476 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 3477 | { |
8be0e467 | 3478 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
3479 | int err = 0; |
3480 | int vector, v_budget; | |
3481 | ||
3482 | /* | |
3483 | * It's easy to be greedy for MSI-X vectors, but it really | |
3484 | * doesn't do us much good if we have a lot more vectors | |
3485 | * than CPU's. So let's be conservative and only ask for | |
3486 | * (roughly) twice the number of vectors as there are CPU's. | |
3487 | */ | |
3488 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
b4617240 | 3489 | (int)(num_online_cpus() * 2)) + NON_Q_VECTORS; |
021230d4 AV |
3490 | |
3491 | /* | |
3492 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
3493 | * hw.mac->max_msix_vectors vectors. With features |
3494 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
3495 | * descriptor queues supported by our device. Thus, we cap it off in | |
3496 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 3497 | */ |
8be0e467 | 3498 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
3499 | |
3500 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
3501 | * mean we disable MSI-X capabilities of the adapter. */ | |
3502 | adapter->msix_entries = kcalloc(v_budget, | |
b4617240 | 3503 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
3504 | if (adapter->msix_entries) { |
3505 | for (vector = 0; vector < v_budget; vector++) | |
3506 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 3507 | |
7a921c93 | 3508 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 3509 | |
7a921c93 AD |
3510 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3511 | goto out; | |
3512 | } | |
021230d4 | 3513 | |
7a921c93 AD |
3514 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
3515 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
c4cf55e5 PWJ |
3516 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
3517 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
3518 | adapter->atr_sample_rate = 0; | |
7a921c93 | 3519 | ixgbe_set_num_queues(adapter); |
021230d4 | 3520 | |
021230d4 AV |
3521 | err = pci_enable_msi(adapter->pdev); |
3522 | if (!err) { | |
3523 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
3524 | } else { | |
3525 | DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, " | |
b4617240 | 3526 | "falling back to legacy. Error: %d\n", err); |
021230d4 AV |
3527 | /* reset err */ |
3528 | err = 0; | |
3529 | } | |
3530 | ||
3531 | out: | |
021230d4 AV |
3532 | return err; |
3533 | } | |
3534 | ||
7a921c93 AD |
3535 | /** |
3536 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
3537 | * @adapter: board private structure to initialize | |
3538 | * | |
3539 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
3540 | * return -ENOMEM. | |
3541 | **/ | |
3542 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
3543 | { | |
3544 | int q_idx, num_q_vectors; | |
3545 | struct ixgbe_q_vector *q_vector; | |
3546 | int napi_vectors; | |
3547 | int (*poll)(struct napi_struct *, int); | |
3548 | ||
3549 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3550 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3551 | napi_vectors = adapter->num_rx_queues; | |
91281fd3 | 3552 | poll = &ixgbe_clean_rxtx_many; |
7a921c93 AD |
3553 | } else { |
3554 | num_q_vectors = 1; | |
3555 | napi_vectors = 1; | |
3556 | poll = &ixgbe_poll; | |
3557 | } | |
3558 | ||
3559 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3560 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL); | |
3561 | if (!q_vector) | |
3562 | goto err_out; | |
3563 | q_vector->adapter = adapter; | |
7a921c93 | 3564 | q_vector->eitr = adapter->eitr_param; |
fe49f04a | 3565 | q_vector->v_idx = q_idx; |
91281fd3 | 3566 | netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64); |
7a921c93 AD |
3567 | adapter->q_vector[q_idx] = q_vector; |
3568 | } | |
3569 | ||
3570 | return 0; | |
3571 | ||
3572 | err_out: | |
3573 | while (q_idx) { | |
3574 | q_idx--; | |
3575 | q_vector = adapter->q_vector[q_idx]; | |
3576 | netif_napi_del(&q_vector->napi); | |
3577 | kfree(q_vector); | |
3578 | adapter->q_vector[q_idx] = NULL; | |
3579 | } | |
3580 | return -ENOMEM; | |
3581 | } | |
3582 | ||
3583 | /** | |
3584 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
3585 | * @adapter: board private structure to initialize | |
3586 | * | |
3587 | * This function frees the memory allocated to the q_vectors. In addition if | |
3588 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
3589 | * to freeing the q_vector. | |
3590 | **/ | |
3591 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
3592 | { | |
3593 | int q_idx, num_q_vectors; | |
7a921c93 | 3594 | |
91281fd3 | 3595 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 3596 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 3597 | else |
7a921c93 | 3598 | num_q_vectors = 1; |
7a921c93 AD |
3599 | |
3600 | for (q_idx = 0; q_idx < num_q_vectors; q_idx++) { | |
3601 | struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx]; | |
7a921c93 | 3602 | adapter->q_vector[q_idx] = NULL; |
91281fd3 | 3603 | netif_napi_del(&q_vector->napi); |
7a921c93 AD |
3604 | kfree(q_vector); |
3605 | } | |
3606 | } | |
3607 | ||
2f90b865 | 3608 | void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
3609 | { |
3610 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
3611 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
3612 | pci_disable_msix(adapter->pdev); | |
3613 | kfree(adapter->msix_entries); | |
3614 | adapter->msix_entries = NULL; | |
3615 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
3616 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
3617 | pci_disable_msi(adapter->pdev); | |
3618 | } | |
3619 | return; | |
3620 | } | |
3621 | ||
3622 | /** | |
3623 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
3624 | * @adapter: board private structure to initialize | |
3625 | * | |
3626 | * We determine which interrupt scheme to use based on... | |
3627 | * - Kernel support (MSI, MSI-X) | |
3628 | * - which can be user-defined (via MODULE_PARAM) | |
3629 | * - Hardware queue count (num_*_queues) | |
3630 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
3631 | **/ | |
2f90b865 | 3632 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
3633 | { |
3634 | int err; | |
3635 | ||
3636 | /* Number of supported queues */ | |
3637 | ixgbe_set_num_queues(adapter); | |
3638 | ||
021230d4 AV |
3639 | err = ixgbe_set_interrupt_capability(adapter); |
3640 | if (err) { | |
3641 | DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n"); | |
3642 | goto err_set_interrupt; | |
9a799d71 AK |
3643 | } |
3644 | ||
7a921c93 AD |
3645 | err = ixgbe_alloc_q_vectors(adapter); |
3646 | if (err) { | |
3647 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queue " | |
3648 | "vectors\n"); | |
3649 | goto err_alloc_q_vectors; | |
3650 | } | |
3651 | ||
3652 | err = ixgbe_alloc_queues(adapter); | |
3653 | if (err) { | |
3654 | DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n"); | |
3655 | goto err_alloc_queues; | |
3656 | } | |
3657 | ||
021230d4 | 3658 | DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, " |
b4617240 PW |
3659 | "Tx Queue count = %u\n", |
3660 | (adapter->num_rx_queues > 1) ? "Enabled" : | |
3661 | "Disabled", adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
3662 | |
3663 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3664 | ||
9a799d71 | 3665 | return 0; |
021230d4 | 3666 | |
7a921c93 AD |
3667 | err_alloc_queues: |
3668 | ixgbe_free_q_vectors(adapter); | |
3669 | err_alloc_q_vectors: | |
3670 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 3671 | err_set_interrupt: |
7a921c93 AD |
3672 | return err; |
3673 | } | |
3674 | ||
3675 | /** | |
3676 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
3677 | * @adapter: board private structure to clear interrupt scheme on | |
3678 | * | |
3679 | * We go through and clear interrupt specific resources and reset the structure | |
3680 | * to pre-load conditions | |
3681 | **/ | |
3682 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
3683 | { | |
021230d4 AV |
3684 | kfree(adapter->tx_ring); |
3685 | kfree(adapter->rx_ring); | |
7a921c93 AD |
3686 | adapter->tx_ring = NULL; |
3687 | adapter->rx_ring = NULL; | |
3688 | ||
3689 | ixgbe_free_q_vectors(adapter); | |
3690 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
3691 | } |
3692 | ||
c4900be0 DS |
3693 | /** |
3694 | * ixgbe_sfp_timer - worker thread to find a missing module | |
3695 | * @data: pointer to our adapter struct | |
3696 | **/ | |
3697 | static void ixgbe_sfp_timer(unsigned long data) | |
3698 | { | |
3699 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
3700 | ||
4df10466 JB |
3701 | /* |
3702 | * Do the sfp_timer outside of interrupt context due to the | |
c4900be0 DS |
3703 | * delays that sfp+ detection requires |
3704 | */ | |
3705 | schedule_work(&adapter->sfp_task); | |
3706 | } | |
3707 | ||
3708 | /** | |
3709 | * ixgbe_sfp_task - worker thread to find a missing module | |
3710 | * @work: pointer to work_struct containing our data | |
3711 | **/ | |
3712 | static void ixgbe_sfp_task(struct work_struct *work) | |
3713 | { | |
3714 | struct ixgbe_adapter *adapter = container_of(work, | |
3715 | struct ixgbe_adapter, | |
3716 | sfp_task); | |
3717 | struct ixgbe_hw *hw = &adapter->hw; | |
3718 | ||
3719 | if ((hw->phy.type == ixgbe_phy_nl) && | |
3720 | (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) { | |
3721 | s32 ret = hw->phy.ops.identify_sfp(hw); | |
3722 | if (ret) | |
3723 | goto reschedule; | |
3724 | ret = hw->phy.ops.reset(hw); | |
3725 | if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
3726 | dev_err(&adapter->pdev->dev, "failed to initialize " |
3727 | "because an unsupported SFP+ module type " | |
3728 | "was detected.\n" | |
3729 | "Reload the driver after installing a " | |
3730 | "supported module.\n"); | |
c4900be0 DS |
3731 | unregister_netdev(adapter->netdev); |
3732 | } else { | |
3733 | DPRINTK(PROBE, INFO, "detected SFP+: %d\n", | |
3734 | hw->phy.sfp_type); | |
3735 | } | |
3736 | /* don't need this routine any more */ | |
3737 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
3738 | } | |
3739 | return; | |
3740 | reschedule: | |
3741 | if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state)) | |
3742 | mod_timer(&adapter->sfp_timer, | |
3743 | round_jiffies(jiffies + (2 * HZ))); | |
3744 | } | |
3745 | ||
9a799d71 AK |
3746 | /** |
3747 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
3748 | * @adapter: board private structure to initialize | |
3749 | * | |
3750 | * ixgbe_sw_init initializes the Adapter private data structure. | |
3751 | * Fields are initialized based on PCI device information and | |
3752 | * OS network device settings (MTU size). | |
3753 | **/ | |
3754 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
3755 | { | |
3756 | struct ixgbe_hw *hw = &adapter->hw; | |
3757 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3758 | unsigned int rss; |
7a6b6f51 | 3759 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3760 | int j; |
3761 | struct tc_configuration *tc; | |
3762 | #endif | |
021230d4 | 3763 | |
c44ade9e JB |
3764 | /* PCI config space info */ |
3765 | ||
3766 | hw->vendor_id = pdev->vendor; | |
3767 | hw->device_id = pdev->device; | |
3768 | hw->revision_id = pdev->revision; | |
3769 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
3770 | hw->subsystem_device_id = pdev->subsystem_device; | |
3771 | ||
021230d4 AV |
3772 | /* Set capability flags */ |
3773 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
3774 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
3775 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
2f90b865 | 3776 | adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES; |
bf069c97 DS |
3777 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3778 | if (hw->device_id == IXGBE_DEV_ID_82598AT) | |
3779 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 3780 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bf069c97 | 3781 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 | 3782 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
df647b5c PWJ |
3783 | adapter->flags |= IXGBE_FLAG2_RSC_CAPABLE; |
3784 | adapter->flags |= IXGBE_FLAG2_RSC_ENABLED; | |
c4cf55e5 PWJ |
3785 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; |
3786 | adapter->ring_feature[RING_F_FDIR].indices = | |
3787 | IXGBE_MAX_FDIR_INDICES; | |
3788 | adapter->atr_sample_rate = 20; | |
3789 | adapter->fdir_pballoc = 0; | |
eacd73f7 YZ |
3790 | #ifdef IXGBE_FCOE |
3791 | adapter->flags |= IXGBE_FLAG_FCOE_ENABLED; | |
0331a832 | 3792 | adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE; |
eacd73f7 | 3793 | #endif /* IXGBE_FCOE */ |
f8212f97 | 3794 | } |
2f90b865 | 3795 | |
7a6b6f51 | 3796 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3797 | /* Configure DCB traffic classes */ |
3798 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
3799 | tc = &adapter->dcb_cfg.tc_config[j]; | |
3800 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
3801 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
3802 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
3803 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
3804 | tc->dcb_pfc = pfc_disabled; | |
3805 | } | |
3806 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
3807 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
3808 | adapter->dcb_cfg.rx_pba_cfg = pba_equal; | |
264857b8 | 3809 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 AD |
3810 | adapter->dcb_cfg.round_robin_enable = false; |
3811 | adapter->dcb_set_bitmap = 0x00; | |
3812 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, | |
3813 | adapter->ring_feature[RING_F_DCB].indices); | |
3814 | ||
3815 | #endif | |
9a799d71 AK |
3816 | |
3817 | /* default flow control settings */ | |
cd7664f6 | 3818 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 3819 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
3820 | #ifdef CONFIG_DCB |
3821 | adapter->last_lfc_mode = hw->fc.current_mode; | |
3822 | #endif | |
2b9ade93 JB |
3823 | hw->fc.high_water = IXGBE_DEFAULT_FCRTH; |
3824 | hw->fc.low_water = IXGBE_DEFAULT_FCRTL; | |
3825 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; | |
3826 | hw->fc.send_xon = true; | |
71fd570b | 3827 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 3828 | |
30efa5a3 JB |
3829 | /* enable itr by default in dynamic mode */ |
3830 | adapter->itr_setting = 1; | |
3831 | adapter->eitr_param = 20000; | |
3832 | ||
3833 | /* set defaults for eitr in MegaBytes */ | |
3834 | adapter->eitr_low = 10; | |
3835 | adapter->eitr_high = 20; | |
3836 | ||
3837 | /* set default ring sizes */ | |
3838 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
3839 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
3840 | ||
9a799d71 | 3841 | /* initialize eeprom parameters */ |
c44ade9e | 3842 | if (ixgbe_init_eeprom_params_generic(hw)) { |
9a799d71 AK |
3843 | dev_err(&pdev->dev, "EEPROM initialization failed\n"); |
3844 | return -EIO; | |
3845 | } | |
3846 | ||
021230d4 | 3847 | /* enable rx csum by default */ |
9a799d71 AK |
3848 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
3849 | ||
9a799d71 AK |
3850 | set_bit(__IXGBE_DOWN, &adapter->state); |
3851 | ||
3852 | return 0; | |
3853 | } | |
3854 | ||
3855 | /** | |
3856 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3857 | * @adapter: board private structure | |
3a581073 | 3858 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3859 | * |
3860 | * Return 0 on success, negative on failure | |
3861 | **/ | |
3862 | int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter, | |
e01c31a5 | 3863 | struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3864 | { |
3865 | struct pci_dev *pdev = adapter->pdev; | |
3866 | int size; | |
3867 | ||
3a581073 JB |
3868 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
3869 | tx_ring->tx_buffer_info = vmalloc(size); | |
e01c31a5 JB |
3870 | if (!tx_ring->tx_buffer_info) |
3871 | goto err; | |
3a581073 | 3872 | memset(tx_ring->tx_buffer_info, 0, size); |
9a799d71 AK |
3873 | |
3874 | /* round up to nearest 4K */ | |
12207e49 | 3875 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 3876 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 3877 | |
3a581073 JB |
3878 | tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size, |
3879 | &tx_ring->dma); | |
e01c31a5 JB |
3880 | if (!tx_ring->desc) |
3881 | goto err; | |
9a799d71 | 3882 | |
3a581073 JB |
3883 | tx_ring->next_to_use = 0; |
3884 | tx_ring->next_to_clean = 0; | |
3885 | tx_ring->work_limit = tx_ring->count; | |
9a799d71 | 3886 | return 0; |
e01c31a5 JB |
3887 | |
3888 | err: | |
3889 | vfree(tx_ring->tx_buffer_info); | |
3890 | tx_ring->tx_buffer_info = NULL; | |
3891 | DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit " | |
3892 | "descriptor ring\n"); | |
3893 | return -ENOMEM; | |
9a799d71 AK |
3894 | } |
3895 | ||
69888674 AD |
3896 | /** |
3897 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
3898 | * @adapter: board private structure | |
3899 | * | |
3900 | * If this function returns with an error, then it's possible one or | |
3901 | * more of the rings is populated (while the rest are not). It is the | |
3902 | * callers duty to clean those orphaned rings. | |
3903 | * | |
3904 | * Return 0 on success, negative on failure | |
3905 | **/ | |
3906 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
3907 | { | |
3908 | int i, err = 0; | |
3909 | ||
3910 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3911 | err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]); | |
3912 | if (!err) | |
3913 | continue; | |
3914 | DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i); | |
3915 | break; | |
3916 | } | |
3917 | ||
3918 | return err; | |
3919 | } | |
3920 | ||
9a799d71 AK |
3921 | /** |
3922 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3923 | * @adapter: board private structure | |
3a581073 | 3924 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
3925 | * |
3926 | * Returns 0 on success, negative on failure | |
3927 | **/ | |
3928 | int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, | |
b4617240 | 3929 | struct ixgbe_ring *rx_ring) |
9a799d71 AK |
3930 | { |
3931 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 3932 | int size; |
9a799d71 | 3933 | |
3a581073 JB |
3934 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
3935 | rx_ring->rx_buffer_info = vmalloc(size); | |
3936 | if (!rx_ring->rx_buffer_info) { | |
9a799d71 | 3937 | DPRINTK(PROBE, ERR, |
b4617240 | 3938 | "vmalloc allocation failed for the rx desc ring\n"); |
177db6ff | 3939 | goto alloc_failed; |
9a799d71 | 3940 | } |
3a581073 | 3941 | memset(rx_ring->rx_buffer_info, 0, size); |
9a799d71 | 3942 | |
9a799d71 | 3943 | /* Round up to nearest 4K */ |
3a581073 JB |
3944 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
3945 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 3946 | |
3a581073 | 3947 | rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma); |
9a799d71 | 3948 | |
3a581073 | 3949 | if (!rx_ring->desc) { |
9a799d71 | 3950 | DPRINTK(PROBE, ERR, |
b4617240 | 3951 | "Memory allocation failed for the rx desc ring\n"); |
3a581073 | 3952 | vfree(rx_ring->rx_buffer_info); |
177db6ff | 3953 | goto alloc_failed; |
9a799d71 AK |
3954 | } |
3955 | ||
3a581073 JB |
3956 | rx_ring->next_to_clean = 0; |
3957 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
3958 | |
3959 | return 0; | |
177db6ff MC |
3960 | |
3961 | alloc_failed: | |
177db6ff | 3962 | return -ENOMEM; |
9a799d71 AK |
3963 | } |
3964 | ||
69888674 AD |
3965 | /** |
3966 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
3967 | * @adapter: board private structure | |
3968 | * | |
3969 | * If this function returns with an error, then it's possible one or | |
3970 | * more of the rings is populated (while the rest are not). It is the | |
3971 | * callers duty to clean those orphaned rings. | |
3972 | * | |
3973 | * Return 0 on success, negative on failure | |
3974 | **/ | |
3975 | ||
3976 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) | |
3977 | { | |
3978 | int i, err = 0; | |
3979 | ||
3980 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3981 | err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]); | |
3982 | if (!err) | |
3983 | continue; | |
3984 | DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i); | |
3985 | break; | |
3986 | } | |
3987 | ||
3988 | return err; | |
3989 | } | |
3990 | ||
9a799d71 AK |
3991 | /** |
3992 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
3993 | * @adapter: board private structure | |
3994 | * @tx_ring: Tx descriptor ring for a specific queue | |
3995 | * | |
3996 | * Free all transmit software resources | |
3997 | **/ | |
c431f97e JB |
3998 | void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter, |
3999 | struct ixgbe_ring *tx_ring) | |
9a799d71 AK |
4000 | { |
4001 | struct pci_dev *pdev = adapter->pdev; | |
4002 | ||
4003 | ixgbe_clean_tx_ring(adapter, tx_ring); | |
4004 | ||
4005 | vfree(tx_ring->tx_buffer_info); | |
4006 | tx_ring->tx_buffer_info = NULL; | |
4007 | ||
4008 | pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma); | |
4009 | ||
4010 | tx_ring->desc = NULL; | |
4011 | } | |
4012 | ||
4013 | /** | |
4014 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
4015 | * @adapter: board private structure | |
4016 | * | |
4017 | * Free all transmit software resources | |
4018 | **/ | |
4019 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
4020 | { | |
4021 | int i; | |
4022 | ||
4023 | for (i = 0; i < adapter->num_tx_queues; i++) | |
9891ca7c JB |
4024 | if (adapter->tx_ring[i].desc) |
4025 | ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]); | |
9a799d71 AK |
4026 | } |
4027 | ||
4028 | /** | |
b4617240 | 4029 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
4030 | * @adapter: board private structure |
4031 | * @rx_ring: ring to clean the resources from | |
4032 | * | |
4033 | * Free all receive software resources | |
4034 | **/ | |
c431f97e JB |
4035 | void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter, |
4036 | struct ixgbe_ring *rx_ring) | |
9a799d71 AK |
4037 | { |
4038 | struct pci_dev *pdev = adapter->pdev; | |
4039 | ||
4040 | ixgbe_clean_rx_ring(adapter, rx_ring); | |
4041 | ||
4042 | vfree(rx_ring->rx_buffer_info); | |
4043 | rx_ring->rx_buffer_info = NULL; | |
4044 | ||
4045 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | |
4046 | ||
4047 | rx_ring->desc = NULL; | |
4048 | } | |
4049 | ||
4050 | /** | |
4051 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
4052 | * @adapter: board private structure | |
4053 | * | |
4054 | * Free all receive software resources | |
4055 | **/ | |
4056 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
4057 | { | |
4058 | int i; | |
4059 | ||
4060 | for (i = 0; i < adapter->num_rx_queues; i++) | |
9891ca7c JB |
4061 | if (adapter->rx_ring[i].desc) |
4062 | ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]); | |
9a799d71 AK |
4063 | } |
4064 | ||
9a799d71 AK |
4065 | /** |
4066 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
4067 | * @netdev: network interface device structure | |
4068 | * @new_mtu: new value for maximum frame size | |
4069 | * | |
4070 | * Returns 0 on success, negative on failure | |
4071 | **/ | |
4072 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
4073 | { | |
4074 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4075 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
4076 | ||
42c783c5 JB |
4077 | /* MTU < 68 is an error and causes problems on some kernels */ |
4078 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
9a799d71 AK |
4079 | return -EINVAL; |
4080 | ||
021230d4 | 4081 | DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n", |
b4617240 | 4082 | netdev->mtu, new_mtu); |
021230d4 | 4083 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
4084 | netdev->mtu = new_mtu; |
4085 | ||
d4f80882 AV |
4086 | if (netif_running(netdev)) |
4087 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
4088 | |
4089 | return 0; | |
4090 | } | |
4091 | ||
4092 | /** | |
4093 | * ixgbe_open - Called when a network interface is made active | |
4094 | * @netdev: network interface device structure | |
4095 | * | |
4096 | * Returns 0 on success, negative value on failure | |
4097 | * | |
4098 | * The open entry point is called when a network interface is made | |
4099 | * active by the system (IFF_UP). At this point all resources needed | |
4100 | * for transmit and receive operations are allocated, the interrupt | |
4101 | * handler is registered with the OS, the watchdog timer is started, | |
4102 | * and the stack is notified that the interface is ready. | |
4103 | **/ | |
4104 | static int ixgbe_open(struct net_device *netdev) | |
4105 | { | |
4106 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4107 | int err; | |
4bebfaa5 AK |
4108 | |
4109 | /* disallow open during test */ | |
4110 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
4111 | return -EBUSY; | |
9a799d71 | 4112 | |
54386467 JB |
4113 | netif_carrier_off(netdev); |
4114 | ||
9a799d71 AK |
4115 | /* allocate transmit descriptors */ |
4116 | err = ixgbe_setup_all_tx_resources(adapter); | |
4117 | if (err) | |
4118 | goto err_setup_tx; | |
4119 | ||
9a799d71 AK |
4120 | /* allocate receive descriptors */ |
4121 | err = ixgbe_setup_all_rx_resources(adapter); | |
4122 | if (err) | |
4123 | goto err_setup_rx; | |
4124 | ||
4125 | ixgbe_configure(adapter); | |
4126 | ||
021230d4 | 4127 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
4128 | if (err) |
4129 | goto err_req_irq; | |
4130 | ||
9a799d71 AK |
4131 | err = ixgbe_up_complete(adapter); |
4132 | if (err) | |
4133 | goto err_up; | |
4134 | ||
d55b53ff JK |
4135 | netif_tx_start_all_queues(netdev); |
4136 | ||
9a799d71 AK |
4137 | return 0; |
4138 | ||
4139 | err_up: | |
5eba3699 | 4140 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4141 | ixgbe_free_irq(adapter); |
4142 | err_req_irq: | |
9a799d71 | 4143 | err_setup_rx: |
a20a1199 | 4144 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 4145 | err_setup_tx: |
a20a1199 | 4146 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
4147 | ixgbe_reset(adapter); |
4148 | ||
4149 | return err; | |
4150 | } | |
4151 | ||
4152 | /** | |
4153 | * ixgbe_close - Disables a network interface | |
4154 | * @netdev: network interface device structure | |
4155 | * | |
4156 | * Returns 0, this is not allowed to fail | |
4157 | * | |
4158 | * The close entry point is called when an interface is de-activated | |
4159 | * by the OS. The hardware is still under the drivers control, but | |
4160 | * needs to be disabled. A global MAC reset is issued to stop the | |
4161 | * hardware, and all transmit and receive resources are freed. | |
4162 | **/ | |
4163 | static int ixgbe_close(struct net_device *netdev) | |
4164 | { | |
4165 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
4166 | |
4167 | ixgbe_down(adapter); | |
4168 | ixgbe_free_irq(adapter); | |
4169 | ||
4170 | ixgbe_free_all_tx_resources(adapter); | |
4171 | ixgbe_free_all_rx_resources(adapter); | |
4172 | ||
5eba3699 | 4173 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4174 | |
4175 | return 0; | |
4176 | } | |
4177 | ||
b3c8b4ba AD |
4178 | #ifdef CONFIG_PM |
4179 | static int ixgbe_resume(struct pci_dev *pdev) | |
4180 | { | |
4181 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4182 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4183 | u32 err; | |
4184 | ||
4185 | pci_set_power_state(pdev, PCI_D0); | |
4186 | pci_restore_state(pdev); | |
9ce77666 | 4187 | |
4188 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 4189 | if (err) { |
69888674 | 4190 | printk(KERN_ERR "ixgbe: Cannot enable PCI device from " |
b3c8b4ba AD |
4191 | "suspend\n"); |
4192 | return err; | |
4193 | } | |
4194 | pci_set_master(pdev); | |
4195 | ||
dd4d8ca6 | 4196 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
4197 | |
4198 | err = ixgbe_init_interrupt_scheme(adapter); | |
4199 | if (err) { | |
4200 | printk(KERN_ERR "ixgbe: Cannot initialize interrupts for " | |
4201 | "device\n"); | |
4202 | return err; | |
4203 | } | |
4204 | ||
b3c8b4ba AD |
4205 | ixgbe_reset(adapter); |
4206 | ||
495dce12 WJP |
4207 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
4208 | ||
b3c8b4ba AD |
4209 | if (netif_running(netdev)) { |
4210 | err = ixgbe_open(adapter->netdev); | |
4211 | if (err) | |
4212 | return err; | |
4213 | } | |
4214 | ||
4215 | netif_device_attach(netdev); | |
4216 | ||
4217 | return 0; | |
4218 | } | |
b3c8b4ba | 4219 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
4220 | |
4221 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba AD |
4222 | { |
4223 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4224 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
e8e26350 PW |
4225 | struct ixgbe_hw *hw = &adapter->hw; |
4226 | u32 ctrl, fctrl; | |
4227 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
4228 | #ifdef CONFIG_PM |
4229 | int retval = 0; | |
4230 | #endif | |
4231 | ||
4232 | netif_device_detach(netdev); | |
4233 | ||
4234 | if (netif_running(netdev)) { | |
4235 | ixgbe_down(adapter); | |
4236 | ixgbe_free_irq(adapter); | |
4237 | ixgbe_free_all_tx_resources(adapter); | |
4238 | ixgbe_free_all_rx_resources(adapter); | |
4239 | } | |
7a921c93 | 4240 | ixgbe_clear_interrupt_scheme(adapter); |
b3c8b4ba AD |
4241 | |
4242 | #ifdef CONFIG_PM | |
4243 | retval = pci_save_state(pdev); | |
4244 | if (retval) | |
4245 | return retval; | |
4df10466 | 4246 | |
b3c8b4ba | 4247 | #endif |
e8e26350 PW |
4248 | if (wufc) { |
4249 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 4250 | |
e8e26350 PW |
4251 | /* turn on all-multi mode if wake on multicast is enabled */ |
4252 | if (wufc & IXGBE_WUFC_MC) { | |
4253 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4254 | fctrl |= IXGBE_FCTRL_MPE; | |
4255 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4256 | } | |
4257 | ||
4258 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
4259 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
4260 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
4261 | ||
4262 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
4263 | } else { | |
4264 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
4265 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
4266 | } | |
4267 | ||
dd4d8ca6 DS |
4268 | if (wufc && hw->mac.type == ixgbe_mac_82599EB) |
4269 | pci_wake_from_d3(pdev, true); | |
4270 | else | |
4271 | pci_wake_from_d3(pdev, false); | |
b3c8b4ba | 4272 | |
9d8d05ae RW |
4273 | *enable_wake = !!wufc; |
4274 | ||
b3c8b4ba AD |
4275 | ixgbe_release_hw_control(adapter); |
4276 | ||
4277 | pci_disable_device(pdev); | |
4278 | ||
9d8d05ae RW |
4279 | return 0; |
4280 | } | |
4281 | ||
4282 | #ifdef CONFIG_PM | |
4283 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
4284 | { | |
4285 | int retval; | |
4286 | bool wake; | |
4287 | ||
4288 | retval = __ixgbe_shutdown(pdev, &wake); | |
4289 | if (retval) | |
4290 | return retval; | |
4291 | ||
4292 | if (wake) { | |
4293 | pci_prepare_to_sleep(pdev); | |
4294 | } else { | |
4295 | pci_wake_from_d3(pdev, false); | |
4296 | pci_set_power_state(pdev, PCI_D3hot); | |
4297 | } | |
b3c8b4ba AD |
4298 | |
4299 | return 0; | |
4300 | } | |
9d8d05ae | 4301 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
4302 | |
4303 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
4304 | { | |
9d8d05ae RW |
4305 | bool wake; |
4306 | ||
4307 | __ixgbe_shutdown(pdev, &wake); | |
4308 | ||
4309 | if (system_state == SYSTEM_POWER_OFF) { | |
4310 | pci_wake_from_d3(pdev, wake); | |
4311 | pci_set_power_state(pdev, PCI_D3hot); | |
4312 | } | |
b3c8b4ba AD |
4313 | } |
4314 | ||
9a799d71 AK |
4315 | /** |
4316 | * ixgbe_update_stats - Update the board statistics counters. | |
4317 | * @adapter: board private structure | |
4318 | **/ | |
4319 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
4320 | { | |
4321 | struct ixgbe_hw *hw = &adapter->hw; | |
6f11eef7 AV |
4322 | u64 total_mpc = 0; |
4323 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
9a799d71 | 4324 | |
d51019a4 | 4325 | if (hw->mac.type == ixgbe_mac_82599EB) { |
f8212f97 | 4326 | u64 rsc_count = 0; |
d51019a4 PW |
4327 | for (i = 0; i < 16; i++) |
4328 | adapter->hw_rx_no_dma_resources += | |
4329 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
f8212f97 AD |
4330 | for (i = 0; i < adapter->num_rx_queues; i++) |
4331 | rsc_count += adapter->rx_ring[i].rsc_count; | |
4332 | adapter->rsc_count = rsc_count; | |
d51019a4 PW |
4333 | } |
4334 | ||
9a799d71 | 4335 | adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
6f11eef7 AV |
4336 | for (i = 0; i < 8; i++) { |
4337 | /* for packet buffers not used, the register should read 0 */ | |
4338 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
4339 | missed_rx += mpc; | |
4340 | adapter->stats.mpc[i] += mpc; | |
4341 | total_mpc += adapter->stats.mpc[i]; | |
e8e26350 PW |
4342 | if (hw->mac.type == ixgbe_mac_82598EB) |
4343 | adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
2f90b865 AD |
4344 | adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
4345 | adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
4346 | adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
4347 | adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
e8e26350 PW |
4348 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4349 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4350 | IXGBE_PXONRXCNT(i)); | |
4351 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4352 | IXGBE_PXOFFRXCNT(i)); | |
4353 | adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
e8e26350 PW |
4354 | } else { |
4355 | adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw, | |
4356 | IXGBE_PXONRXC(i)); | |
4357 | adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw, | |
4358 | IXGBE_PXOFFRXC(i)); | |
4359 | } | |
2f90b865 AD |
4360 | adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw, |
4361 | IXGBE_PXONTXC(i)); | |
2f90b865 | 4362 | adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw, |
e8e26350 | 4363 | IXGBE_PXOFFTXC(i)); |
6f11eef7 AV |
4364 | } |
4365 | adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); | |
4366 | /* work around hardware counting issue */ | |
4367 | adapter->stats.gprc -= missed_rx; | |
4368 | ||
4369 | /* 82598 hardware only has a 32 bit counter in the high register */ | |
e8e26350 PW |
4370 | if (hw->mac.type == ixgbe_mac_82599EB) { |
4371 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); | |
4372 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ | |
4373 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
4374 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ | |
4375 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL); | |
4376 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ | |
4377 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
4378 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
c4cf55e5 PWJ |
4379 | adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
4380 | adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c YZ |
4381 | #ifdef IXGBE_FCOE |
4382 | adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); | |
4383 | adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
4384 | adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
4385 | adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
4386 | adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
4387 | adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
4388 | #endif /* IXGBE_FCOE */ | |
e8e26350 PW |
4389 | } else { |
4390 | adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
4391 | adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
4392 | adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); | |
4393 | adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
4394 | adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
4395 | } | |
9a799d71 AK |
4396 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
4397 | adapter->stats.bprc += bprc; | |
4398 | adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 PW |
4399 | if (hw->mac.type == ixgbe_mac_82598EB) |
4400 | adapter->stats.mprc -= bprc; | |
9a799d71 AK |
4401 | adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC); |
4402 | adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
4403 | adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
4404 | adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
4405 | adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
4406 | adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
4407 | adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
9a799d71 | 4408 | adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); |
6f11eef7 AV |
4409 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
4410 | adapter->stats.lxontxc += lxon; | |
4411 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); | |
4412 | adapter->stats.lxofftxc += lxoff; | |
9a799d71 AK |
4413 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4414 | adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); | |
6f11eef7 AV |
4415 | adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); |
4416 | /* | |
4417 | * 82598 errata - tx of flow control packets is included in tx counters | |
4418 | */ | |
4419 | xon_off_tot = lxon + lxoff; | |
4420 | adapter->stats.gptc -= xon_off_tot; | |
4421 | adapter->stats.mptc -= xon_off_tot; | |
4422 | adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
9a799d71 AK |
4423 | adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC); |
4424 | adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
4425 | adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
9a799d71 AK |
4426 | adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR); |
4427 | adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6f11eef7 | 4428 | adapter->stats.ptc64 -= xon_off_tot; |
9a799d71 AK |
4429 | adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); |
4430 | adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
4431 | adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
4432 | adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
4433 | adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
9a799d71 AK |
4434 | adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); |
4435 | ||
4436 | /* Fill out the OS statistics structure */ | |
9a799d71 AK |
4437 | adapter->net_stats.multicast = adapter->stats.mprc; |
4438 | ||
4439 | /* Rx Errors */ | |
4440 | adapter->net_stats.rx_errors = adapter->stats.crcerrs + | |
b4617240 | 4441 | adapter->stats.rlec; |
9a799d71 AK |
4442 | adapter->net_stats.rx_dropped = 0; |
4443 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; | |
4444 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | |
6f11eef7 | 4445 | adapter->net_stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
4446 | } |
4447 | ||
4448 | /** | |
4449 | * ixgbe_watchdog - Timer Call-back | |
4450 | * @data: pointer to adapter cast into an unsigned long | |
4451 | **/ | |
4452 | static void ixgbe_watchdog(unsigned long data) | |
4453 | { | |
4454 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
cf8280ee | 4455 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
4456 | u64 eics = 0; |
4457 | int i; | |
cf8280ee | 4458 | |
fe49f04a AD |
4459 | /* |
4460 | * Do the watchdog outside of interrupt context due to the lovely | |
4461 | * delays that some of the newer hardware requires | |
4462 | */ | |
22d5a71b | 4463 | |
fe49f04a AD |
4464 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
4465 | goto watchdog_short_circuit; | |
22d5a71b | 4466 | |
fe49f04a AD |
4467 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
4468 | /* | |
4469 | * for legacy and MSI interrupts don't set any bits | |
4470 | * that are enabled for EIAM, because this operation | |
4471 | * would set *both* EIMS and EICS for any bit in EIAM | |
4472 | */ | |
4473 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
4474 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
4475 | goto watchdog_reschedule; | |
4476 | } | |
4477 | ||
4478 | /* get one bit for every active tx/rx interrupt vector */ | |
4479 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
4480 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
4481 | if (qv->rxr_count || qv->txr_count) | |
4482 | eics |= ((u64)1 << i); | |
cf8280ee | 4483 | } |
9a799d71 | 4484 | |
fe49f04a AD |
4485 | /* Cause software interrupt to ensure rx rings are cleaned */ |
4486 | ixgbe_irq_rearm_queues(adapter, eics); | |
4487 | ||
4488 | watchdog_reschedule: | |
4489 | /* Reset the timer */ | |
4490 | mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ)); | |
4491 | ||
4492 | watchdog_short_circuit: | |
cf8280ee JB |
4493 | schedule_work(&adapter->watchdog_task); |
4494 | } | |
4495 | ||
e8e26350 PW |
4496 | /** |
4497 | * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber | |
4498 | * @work: pointer to work_struct containing our data | |
4499 | **/ | |
4500 | static void ixgbe_multispeed_fiber_task(struct work_struct *work) | |
4501 | { | |
4502 | struct ixgbe_adapter *adapter = container_of(work, | |
4503 | struct ixgbe_adapter, | |
4504 | multispeed_fiber_task); | |
4505 | struct ixgbe_hw *hw = &adapter->hw; | |
4506 | u32 autoneg; | |
4507 | ||
4508 | adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK; | |
a1f25324 MC |
4509 | autoneg = hw->phy.autoneg_advertised; |
4510 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e26350 PW |
4511 | hw->mac.ops.get_link_capabilities(hw, &autoneg, |
4512 | &hw->mac.autoneg); | |
4513 | if (hw->mac.ops.setup_link_speed) | |
4514 | hw->mac.ops.setup_link_speed(hw, autoneg, true, true); | |
4515 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
4516 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK; | |
4517 | } | |
4518 | ||
4519 | /** | |
4520 | * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module | |
4521 | * @work: pointer to work_struct containing our data | |
4522 | **/ | |
4523 | static void ixgbe_sfp_config_module_task(struct work_struct *work) | |
4524 | { | |
4525 | struct ixgbe_adapter *adapter = container_of(work, | |
4526 | struct ixgbe_adapter, | |
4527 | sfp_config_module_task); | |
4528 | struct ixgbe_hw *hw = &adapter->hw; | |
4529 | u32 err; | |
4530 | ||
4531 | adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4532 | err = hw->phy.ops.identify_sfp(hw); | |
4533 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
4534 | dev_err(&adapter->pdev->dev, "failed to initialize because " |
4535 | "an unsupported SFP+ module type was detected.\n" | |
4536 | "Reload the driver after installing a supported " | |
4537 | "module.\n"); | |
e8e26350 PW |
4538 | ixgbe_down(adapter); |
4539 | return; | |
4540 | } | |
4541 | hw->mac.ops.setup_sfp(hw); | |
4542 | ||
8d1c3c07 | 4543 | if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK)) |
e8e26350 PW |
4544 | /* This will also work for DA Twinax connections */ |
4545 | schedule_work(&adapter->multispeed_fiber_task); | |
4546 | adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK; | |
4547 | } | |
4548 | ||
c4cf55e5 PWJ |
4549 | /** |
4550 | * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table | |
4551 | * @work: pointer to work_struct containing our data | |
4552 | **/ | |
4553 | static void ixgbe_fdir_reinit_task(struct work_struct *work) | |
4554 | { | |
4555 | struct ixgbe_adapter *adapter = container_of(work, | |
4556 | struct ixgbe_adapter, | |
4557 | fdir_reinit_task); | |
4558 | struct ixgbe_hw *hw = &adapter->hw; | |
4559 | int i; | |
4560 | ||
4561 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { | |
4562 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4563 | set_bit(__IXGBE_FDIR_INIT_DONE, | |
4564 | &(adapter->tx_ring[i].reinit_state)); | |
4565 | } else { | |
4566 | DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, " | |
4567 | "ignored adding FDIR ATR filters \n"); | |
4568 | } | |
4569 | /* Done FDIR Re-initialization, enable transmits */ | |
4570 | netif_tx_start_all_queues(adapter->netdev); | |
4571 | } | |
4572 | ||
cf8280ee | 4573 | /** |
69888674 AD |
4574 | * ixgbe_watchdog_task - worker thread to bring link up |
4575 | * @work: pointer to work_struct containing our data | |
cf8280ee JB |
4576 | **/ |
4577 | static void ixgbe_watchdog_task(struct work_struct *work) | |
4578 | { | |
4579 | struct ixgbe_adapter *adapter = container_of(work, | |
4580 | struct ixgbe_adapter, | |
4581 | watchdog_task); | |
4582 | struct net_device *netdev = adapter->netdev; | |
4583 | struct ixgbe_hw *hw = &adapter->hw; | |
4584 | u32 link_speed = adapter->link_speed; | |
4585 | bool link_up = adapter->link_up; | |
bc59fcda NS |
4586 | int i; |
4587 | struct ixgbe_ring *tx_ring; | |
4588 | int some_tx_pending = 0; | |
cf8280ee JB |
4589 | |
4590 | adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK; | |
4591 | ||
4592 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { | |
4593 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
264857b8 PWJ |
4594 | if (link_up) { |
4595 | #ifdef CONFIG_DCB | |
4596 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
4597 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
620fa036 | 4598 | hw->mac.ops.fc_enable(hw, i); |
264857b8 | 4599 | } else { |
620fa036 | 4600 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
4601 | } |
4602 | #else | |
620fa036 | 4603 | hw->mac.ops.fc_enable(hw, 0); |
264857b8 PWJ |
4604 | #endif |
4605 | } | |
4606 | ||
cf8280ee JB |
4607 | if (link_up || |
4608 | time_after(jiffies, (adapter->link_check_timeout + | |
4609 | IXGBE_TRY_LINK_TIMEOUT))) { | |
cf8280ee | 4610 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
264857b8 | 4611 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); |
cf8280ee JB |
4612 | } |
4613 | adapter->link_up = link_up; | |
4614 | adapter->link_speed = link_speed; | |
4615 | } | |
9a799d71 AK |
4616 | |
4617 | if (link_up) { | |
4618 | if (!netif_carrier_ok(netdev)) { | |
e8e26350 PW |
4619 | bool flow_rx, flow_tx; |
4620 | ||
4621 | if (hw->mac.type == ixgbe_mac_82599EB) { | |
4622 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
4623 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
4624 | flow_rx = (mflcn & IXGBE_MFLCN_RFCE); | |
4625 | flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
4626 | } else { | |
4627 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4628 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
4629 | flow_rx = (frctl & IXGBE_FCTRL_RFCE); | |
4630 | flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X); | |
4631 | } | |
4632 | ||
a46e534b JK |
4633 | printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, " |
4634 | "Flow Control: %s\n", | |
4635 | netdev->name, | |
4636 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
4637 | "10 Gbps" : | |
4638 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
4639 | "1 Gbps" : "unknown speed")), | |
e8e26350 PW |
4640 | ((flow_rx && flow_tx) ? "RX/TX" : |
4641 | (flow_rx ? "RX" : | |
4642 | (flow_tx ? "TX" : "None")))); | |
9a799d71 AK |
4643 | |
4644 | netif_carrier_on(netdev); | |
9a799d71 AK |
4645 | } else { |
4646 | /* Force detection of hung controller */ | |
4647 | adapter->detect_tx_hung = true; | |
4648 | } | |
4649 | } else { | |
cf8280ee JB |
4650 | adapter->link_up = false; |
4651 | adapter->link_speed = 0; | |
9a799d71 | 4652 | if (netif_carrier_ok(netdev)) { |
a46e534b JK |
4653 | printk(KERN_INFO "ixgbe: %s NIC Link is Down\n", |
4654 | netdev->name); | |
9a799d71 | 4655 | netif_carrier_off(netdev); |
9a799d71 AK |
4656 | } |
4657 | } | |
4658 | ||
bc59fcda NS |
4659 | if (!netif_carrier_ok(netdev)) { |
4660 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4661 | tx_ring = &adapter->tx_ring[i]; | |
4662 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { | |
4663 | some_tx_pending = 1; | |
4664 | break; | |
4665 | } | |
4666 | } | |
4667 | ||
4668 | if (some_tx_pending) { | |
4669 | /* We've lost link, so the controller stops DMA, | |
4670 | * but we've got queued Tx work that's never going | |
4671 | * to get done, so reset controller to flush Tx. | |
4672 | * (Do the reset outside of interrupt context). | |
4673 | */ | |
4674 | schedule_work(&adapter->reset_task); | |
4675 | } | |
4676 | } | |
4677 | ||
9a799d71 | 4678 | ixgbe_update_stats(adapter); |
cf8280ee | 4679 | adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK; |
9a799d71 AK |
4680 | } |
4681 | ||
9a799d71 | 4682 | static int ixgbe_tso(struct ixgbe_adapter *adapter, |
b4617240 PW |
4683 | struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
4684 | u32 tx_flags, u8 *hdr_len) | |
9a799d71 AK |
4685 | { |
4686 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4687 | unsigned int i; | |
4688 | int err; | |
4689 | struct ixgbe_tx_buffer *tx_buffer_info; | |
9f8cdf4f JB |
4690 | u32 vlan_macip_lens = 0, type_tucmd_mlhl; |
4691 | u32 mss_l4len_idx, l4len; | |
9a799d71 AK |
4692 | |
4693 | if (skb_is_gso(skb)) { | |
4694 | if (skb_header_cloned(skb)) { | |
4695 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
4696 | if (err) | |
4697 | return err; | |
4698 | } | |
4699 | l4len = tcp_hdrlen(skb); | |
4700 | *hdr_len += l4len; | |
4701 | ||
8327d000 | 4702 | if (skb->protocol == htons(ETH_P_IP)) { |
9a799d71 AK |
4703 | struct iphdr *iph = ip_hdr(skb); |
4704 | iph->tot_len = 0; | |
4705 | iph->check = 0; | |
4706 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
b4617240 PW |
4707 | iph->daddr, 0, |
4708 | IPPROTO_TCP, | |
4709 | 0); | |
9a799d71 AK |
4710 | adapter->hw_tso_ctxt++; |
4711 | } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) { | |
4712 | ipv6_hdr(skb)->payload_len = 0; | |
4713 | tcp_hdr(skb)->check = | |
4714 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
b4617240 PW |
4715 | &ipv6_hdr(skb)->daddr, |
4716 | 0, IPPROTO_TCP, 0); | |
9a799d71 AK |
4717 | adapter->hw_tso6_ctxt++; |
4718 | } | |
4719 | ||
4720 | i = tx_ring->next_to_use; | |
4721 | ||
4722 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4723 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4724 | ||
4725 | /* VLAN MACLEN IPLEN */ | |
4726 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4727 | vlan_macip_lens |= | |
4728 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4729 | vlan_macip_lens |= ((skb_network_offset(skb)) << | |
b4617240 | 4730 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4731 | *hdr_len += skb_network_offset(skb); |
4732 | vlan_macip_lens |= | |
4733 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4734 | *hdr_len += | |
4735 | (skb_transport_header(skb) - skb_network_header(skb)); | |
4736 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4737 | context_desc->seqnum_seed = 0; | |
4738 | ||
4739 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ | |
9f8cdf4f | 4740 | type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT | |
b4617240 | 4741 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 | 4742 | |
8327d000 | 4743 | if (skb->protocol == htons(ETH_P_IP)) |
9a799d71 AK |
4744 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
4745 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
4746 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4747 | ||
4748 | /* MSS L4LEN IDX */ | |
9f8cdf4f | 4749 | mss_l4len_idx = |
9a799d71 AK |
4750 | (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT); |
4751 | mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT); | |
4eeae6fd PW |
4752 | /* use index 1 for TSO */ |
4753 | mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4754 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); |
4755 | ||
4756 | tx_buffer_info->time_stamp = jiffies; | |
4757 | tx_buffer_info->next_to_watch = i; | |
4758 | ||
4759 | i++; | |
4760 | if (i == tx_ring->count) | |
4761 | i = 0; | |
4762 | tx_ring->next_to_use = i; | |
4763 | ||
4764 | return true; | |
4765 | } | |
4766 | return false; | |
4767 | } | |
4768 | ||
4769 | static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4770 | struct ixgbe_ring *tx_ring, |
4771 | struct sk_buff *skb, u32 tx_flags) | |
9a799d71 AK |
4772 | { |
4773 | struct ixgbe_adv_tx_context_desc *context_desc; | |
4774 | unsigned int i; | |
4775 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4776 | u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; | |
4777 | ||
4778 | if (skb->ip_summed == CHECKSUM_PARTIAL || | |
4779 | (tx_flags & IXGBE_TX_FLAGS_VLAN)) { | |
4780 | i = tx_ring->next_to_use; | |
4781 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4782 | context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i); | |
4783 | ||
4784 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4785 | vlan_macip_lens |= | |
4786 | (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK); | |
4787 | vlan_macip_lens |= (skb_network_offset(skb) << | |
b4617240 | 4788 | IXGBE_ADVTXD_MACLEN_SHIFT); |
9a799d71 AK |
4789 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
4790 | vlan_macip_lens |= (skb_transport_header(skb) - | |
b4617240 | 4791 | skb_network_header(skb)); |
9a799d71 AK |
4792 | |
4793 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4794 | context_desc->seqnum_seed = 0; | |
4795 | ||
4796 | type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT | | |
b4617240 | 4797 | IXGBE_ADVTXD_DTYP_CTXT); |
9a799d71 AK |
4798 | |
4799 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
41825d71 | 4800 | switch (skb->protocol) { |
09640e63 | 4801 | case cpu_to_be16(ETH_P_IP): |
9a799d71 | 4802 | type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4; |
41825d71 AK |
4803 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
4804 | type_tucmd_mlhl |= | |
b4617240 | 4805 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4806 | else if (ip_hdr(skb)->protocol == IPPROTO_SCTP) |
4807 | type_tucmd_mlhl |= | |
4808 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4809 | break; |
09640e63 | 4810 | case cpu_to_be16(ETH_P_IPV6): |
41825d71 AK |
4811 | /* XXX what about other V6 headers?? */ |
4812 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
4813 | type_tucmd_mlhl |= | |
b4617240 | 4814 | IXGBE_ADVTXD_TUCMD_L4T_TCP; |
45a5ead0 JB |
4815 | else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP) |
4816 | type_tucmd_mlhl |= | |
4817 | IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
41825d71 | 4818 | break; |
41825d71 AK |
4819 | default: |
4820 | if (unlikely(net_ratelimit())) { | |
4821 | DPRINTK(PROBE, WARNING, | |
4822 | "partial checksum but proto=%x!\n", | |
4823 | skb->protocol); | |
4824 | } | |
4825 | break; | |
4826 | } | |
9a799d71 AK |
4827 | } |
4828 | ||
4829 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl); | |
4eeae6fd | 4830 | /* use index zero for tx checksum offload */ |
9a799d71 AK |
4831 | context_desc->mss_l4len_idx = 0; |
4832 | ||
4833 | tx_buffer_info->time_stamp = jiffies; | |
4834 | tx_buffer_info->next_to_watch = i; | |
9f8cdf4f | 4835 | |
9a799d71 AK |
4836 | adapter->hw_csum_tx_good++; |
4837 | i++; | |
4838 | if (i == tx_ring->count) | |
4839 | i = 0; | |
4840 | tx_ring->next_to_use = i; | |
4841 | ||
4842 | return true; | |
4843 | } | |
9f8cdf4f | 4844 | |
9a799d71 AK |
4845 | return false; |
4846 | } | |
4847 | ||
4848 | static int ixgbe_tx_map(struct ixgbe_adapter *adapter, | |
b4617240 | 4849 | struct ixgbe_ring *tx_ring, |
eacd73f7 YZ |
4850 | struct sk_buff *skb, u32 tx_flags, |
4851 | unsigned int first) | |
9a799d71 AK |
4852 | { |
4853 | struct ixgbe_tx_buffer *tx_buffer_info; | |
eacd73f7 YZ |
4854 | unsigned int len; |
4855 | unsigned int total = skb->len; | |
9a799d71 AK |
4856 | unsigned int offset = 0, size, count = 0, i; |
4857 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | |
4858 | unsigned int f; | |
44df32c5 | 4859 | dma_addr_t *map; |
9a799d71 AK |
4860 | |
4861 | i = tx_ring->next_to_use; | |
4862 | ||
44df32c5 AD |
4863 | if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) { |
4864 | dev_err(&adapter->pdev->dev, "TX DMA map failed\n"); | |
4865 | return 0; | |
4866 | } | |
4867 | ||
4868 | map = skb_shinfo(skb)->dma_maps; | |
4869 | ||
eacd73f7 YZ |
4870 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) |
4871 | /* excluding fcoe_crc_eof for FCoE */ | |
4872 | total -= sizeof(struct fcoe_crc_eof); | |
4873 | ||
4874 | len = min(skb_headlen(skb), total); | |
9a799d71 AK |
4875 | while (len) { |
4876 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4877 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4878 | ||
4879 | tx_buffer_info->length = size; | |
042a53a9 | 4880 | tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset; |
9a799d71 AK |
4881 | tx_buffer_info->time_stamp = jiffies; |
4882 | tx_buffer_info->next_to_watch = i; | |
4883 | ||
4884 | len -= size; | |
eacd73f7 | 4885 | total -= size; |
9a799d71 AK |
4886 | offset += size; |
4887 | count++; | |
44df32c5 AD |
4888 | |
4889 | if (len) { | |
4890 | i++; | |
4891 | if (i == tx_ring->count) | |
4892 | i = 0; | |
4893 | } | |
9a799d71 AK |
4894 | } |
4895 | ||
4896 | for (f = 0; f < nr_frags; f++) { | |
4897 | struct skb_frag_struct *frag; | |
4898 | ||
4899 | frag = &skb_shinfo(skb)->frags[f]; | |
eacd73f7 | 4900 | len = min((unsigned int)frag->size, total); |
44df32c5 | 4901 | offset = 0; |
9a799d71 AK |
4902 | |
4903 | while (len) { | |
44df32c5 AD |
4904 | i++; |
4905 | if (i == tx_ring->count) | |
4906 | i = 0; | |
4907 | ||
9a799d71 AK |
4908 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
4909 | size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD); | |
4910 | ||
4911 | tx_buffer_info->length = size; | |
042a53a9 | 4912 | tx_buffer_info->dma = map[f] + offset; |
9a799d71 AK |
4913 | tx_buffer_info->time_stamp = jiffies; |
4914 | tx_buffer_info->next_to_watch = i; | |
4915 | ||
4916 | len -= size; | |
eacd73f7 | 4917 | total -= size; |
9a799d71 AK |
4918 | offset += size; |
4919 | count++; | |
9a799d71 | 4920 | } |
eacd73f7 YZ |
4921 | if (total == 0) |
4922 | break; | |
9a799d71 | 4923 | } |
44df32c5 | 4924 | |
9a799d71 AK |
4925 | tx_ring->tx_buffer_info[i].skb = skb; |
4926 | tx_ring->tx_buffer_info[first].next_to_watch = i; | |
4927 | ||
4928 | return count; | |
4929 | } | |
4930 | ||
4931 | static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, | |
b4617240 PW |
4932 | struct ixgbe_ring *tx_ring, |
4933 | int tx_flags, int count, u32 paylen, u8 hdr_len) | |
9a799d71 AK |
4934 | { |
4935 | union ixgbe_adv_tx_desc *tx_desc = NULL; | |
4936 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4937 | u32 olinfo_status = 0, cmd_type_len = 0; | |
4938 | unsigned int i; | |
4939 | u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS; | |
4940 | ||
4941 | cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA; | |
4942 | ||
4943 | cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT; | |
4944 | ||
4945 | if (tx_flags & IXGBE_TX_FLAGS_VLAN) | |
4946 | cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE; | |
4947 | ||
4948 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { | |
4949 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4950 | ||
4951 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4952 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4953 | |
4eeae6fd PW |
4954 | /* use index 1 context for tso */ |
4955 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
9a799d71 AK |
4956 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) |
4957 | olinfo_status |= IXGBE_TXD_POPTS_IXSM << | |
b4617240 | 4958 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 AK |
4959 | |
4960 | } else if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
4961 | olinfo_status |= IXGBE_TXD_POPTS_TXSM << | |
b4617240 | 4962 | IXGBE_ADVTXD_POPTS_SHIFT; |
9a799d71 | 4963 | |
eacd73f7 YZ |
4964 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
4965 | olinfo_status |= IXGBE_ADVTXD_CC; | |
4966 | olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT); | |
4967 | if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
4968 | cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE; | |
4969 | } | |
4970 | ||
9a799d71 AK |
4971 | olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT); |
4972 | ||
4973 | i = tx_ring->next_to_use; | |
4974 | while (count--) { | |
4975 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4976 | tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i); | |
4977 | tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma); | |
4978 | tx_desc->read.cmd_type_len = | |
b4617240 | 4979 | cpu_to_le32(cmd_type_len | tx_buffer_info->length); |
9a799d71 | 4980 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
9a799d71 AK |
4981 | i++; |
4982 | if (i == tx_ring->count) | |
4983 | i = 0; | |
4984 | } | |
4985 | ||
4986 | tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd); | |
4987 | ||
4988 | /* | |
4989 | * Force memory writes to complete before letting h/w | |
4990 | * know there are new descriptors to fetch. (Only | |
4991 | * applicable for weak-ordered memory model archs, | |
4992 | * such as IA-64). | |
4993 | */ | |
4994 | wmb(); | |
4995 | ||
4996 | tx_ring->next_to_use = i; | |
4997 | writel(i, adapter->hw.hw_addr + tx_ring->tail); | |
4998 | } | |
4999 | ||
c4cf55e5 PWJ |
5000 | static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb, |
5001 | int queue, u32 tx_flags) | |
5002 | { | |
5003 | /* Right now, we support IPv4 only */ | |
5004 | struct ixgbe_atr_input atr_input; | |
5005 | struct tcphdr *th; | |
5006 | struct udphdr *uh; | |
5007 | struct iphdr *iph = ip_hdr(skb); | |
5008 | struct ethhdr *eth = (struct ethhdr *)skb->data; | |
5009 | u16 vlan_id, src_port, dst_port, flex_bytes; | |
5010 | u32 src_ipv4_addr, dst_ipv4_addr; | |
5011 | u8 l4type = 0; | |
5012 | ||
5013 | /* check if we're UDP or TCP */ | |
5014 | if (iph->protocol == IPPROTO_TCP) { | |
5015 | th = tcp_hdr(skb); | |
5016 | src_port = th->source; | |
5017 | dst_port = th->dest; | |
5018 | l4type |= IXGBE_ATR_L4TYPE_TCP; | |
5019 | /* l4type IPv4 type is 0, no need to assign */ | |
5020 | } else if(iph->protocol == IPPROTO_UDP) { | |
5021 | uh = udp_hdr(skb); | |
5022 | src_port = uh->source; | |
5023 | dst_port = uh->dest; | |
5024 | l4type |= IXGBE_ATR_L4TYPE_UDP; | |
5025 | /* l4type IPv4 type is 0, no need to assign */ | |
5026 | } else { | |
5027 | /* Unsupported L4 header, just bail here */ | |
5028 | return; | |
5029 | } | |
5030 | ||
5031 | memset(&atr_input, 0, sizeof(struct ixgbe_atr_input)); | |
5032 | ||
5033 | vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >> | |
5034 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
5035 | src_ipv4_addr = iph->saddr; | |
5036 | dst_ipv4_addr = iph->daddr; | |
5037 | flex_bytes = eth->h_proto; | |
5038 | ||
5039 | ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id); | |
5040 | ixgbe_atr_set_src_port_82599(&atr_input, dst_port); | |
5041 | ixgbe_atr_set_dst_port_82599(&atr_input, src_port); | |
5042 | ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes); | |
5043 | ixgbe_atr_set_l4type_82599(&atr_input, l4type); | |
5044 | /* src and dst are inverted, think how the receiver sees them */ | |
5045 | ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr); | |
5046 | ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr); | |
5047 | ||
5048 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
5049 | ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue); | |
5050 | } | |
5051 | ||
e092be60 | 5052 | static int __ixgbe_maybe_stop_tx(struct net_device *netdev, |
b4617240 | 5053 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
5054 | { |
5055 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5056 | ||
30eba97a | 5057 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
5058 | /* Herbert's original patch had: |
5059 | * smp_mb__after_netif_stop_queue(); | |
5060 | * but since that doesn't exist yet, just open code it. */ | |
5061 | smp_mb(); | |
5062 | ||
5063 | /* We need to check again in a case another CPU has just | |
5064 | * made room available. */ | |
5065 | if (likely(IXGBE_DESC_UNUSED(tx_ring) < size)) | |
5066 | return -EBUSY; | |
5067 | ||
5068 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
af72166f | 5069 | netif_start_subqueue(netdev, tx_ring->queue_index); |
e092be60 AV |
5070 | ++adapter->restart_queue; |
5071 | return 0; | |
5072 | } | |
5073 | ||
5074 | static int ixgbe_maybe_stop_tx(struct net_device *netdev, | |
b4617240 | 5075 | struct ixgbe_ring *tx_ring, int size) |
e092be60 AV |
5076 | { |
5077 | if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size)) | |
5078 | return 0; | |
5079 | return __ixgbe_maybe_stop_tx(netdev, tx_ring, size); | |
5080 | } | |
5081 | ||
09a3b1f8 SH |
5082 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
5083 | { | |
5084 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5085 | ||
c4cf55e5 PWJ |
5086 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) |
5087 | return smp_processor_id(); | |
5088 | ||
09a3b1f8 SH |
5089 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
5090 | return 0; /* All traffic should default to class 0 */ | |
5091 | ||
5092 | return skb_tx_hash(dev, skb); | |
5093 | } | |
5094 | ||
9a799d71 AK |
5095 | static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
5096 | { | |
5097 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5098 | struct ixgbe_ring *tx_ring; | |
9a799d71 AK |
5099 | unsigned int first; |
5100 | unsigned int tx_flags = 0; | |
30eba97a AV |
5101 | u8 hdr_len = 0; |
5102 | int r_idx = 0, tso; | |
9a799d71 AK |
5103 | int count = 0; |
5104 | unsigned int f; | |
9f8cdf4f | 5105 | |
95615d90 | 5106 | r_idx = skb->queue_mapping; |
30eba97a | 5107 | tx_ring = &adapter->tx_ring[r_idx]; |
9a799d71 | 5108 | |
9f8cdf4f JB |
5109 | if (adapter->vlgrp && vlan_tx_tag_present(skb)) { |
5110 | tx_flags |= vlan_tx_tag_get(skb); | |
2f90b865 AD |
5111 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { |
5112 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; | |
5113 | tx_flags |= (skb->queue_mapping << 13); | |
5114 | } | |
5115 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; | |
5116 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
5117 | } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
5118 | tx_flags |= (skb->queue_mapping << 13); | |
9f8cdf4f JB |
5119 | tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT; |
5120 | tx_flags |= IXGBE_TX_FLAGS_VLAN; | |
9a799d71 | 5121 | } |
eacd73f7 YZ |
5122 | |
5123 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
5124 | (skb->protocol == htons(ETH_P_FCOE))) | |
5125 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | |
5126 | ||
5127 | /* four things can cause us to need a context descriptor */ | |
9f8cdf4f JB |
5128 | if (skb_is_gso(skb) || |
5129 | (skb->ip_summed == CHECKSUM_PARTIAL) || | |
eacd73f7 YZ |
5130 | (tx_flags & IXGBE_TX_FLAGS_VLAN) || |
5131 | (tx_flags & IXGBE_TX_FLAGS_FCOE)) | |
9a799d71 AK |
5132 | count++; |
5133 | ||
9f8cdf4f JB |
5134 | count += TXD_USE_COUNT(skb_headlen(skb)); |
5135 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
9a799d71 AK |
5136 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); |
5137 | ||
e092be60 | 5138 | if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) { |
9a799d71 | 5139 | adapter->tx_busy++; |
9a799d71 AK |
5140 | return NETDEV_TX_BUSY; |
5141 | } | |
9a799d71 | 5142 | |
9a799d71 | 5143 | first = tx_ring->next_to_use; |
eacd73f7 YZ |
5144 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { |
5145 | #ifdef IXGBE_FCOE | |
5146 | /* setup tx offload for FCoE */ | |
5147 | tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
5148 | if (tso < 0) { | |
5149 | dev_kfree_skb_any(skb); | |
5150 | return NETDEV_TX_OK; | |
5151 | } | |
5152 | if (tso) | |
5153 | tx_flags |= IXGBE_TX_FLAGS_FSO; | |
5154 | #endif /* IXGBE_FCOE */ | |
5155 | } else { | |
5156 | if (skb->protocol == htons(ETH_P_IP)) | |
5157 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
5158 | tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len); | |
5159 | if (tso < 0) { | |
5160 | dev_kfree_skb_any(skb); | |
5161 | return NETDEV_TX_OK; | |
5162 | } | |
9a799d71 | 5163 | |
eacd73f7 YZ |
5164 | if (tso) |
5165 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
5166 | else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) && | |
5167 | (skb->ip_summed == CHECKSUM_PARTIAL)) | |
5168 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
5169 | } | |
9a799d71 | 5170 | |
eacd73f7 | 5171 | count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first); |
44df32c5 | 5172 | if (count) { |
c4cf55e5 PWJ |
5173 | /* add the ATR filter if ATR is on */ |
5174 | if (tx_ring->atr_sample_rate) { | |
5175 | ++tx_ring->atr_count; | |
5176 | if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) && | |
5177 | test_bit(__IXGBE_FDIR_INIT_DONE, | |
5178 | &tx_ring->reinit_state)) { | |
5179 | ixgbe_atr(adapter, skb, tx_ring->queue_index, | |
5180 | tx_flags); | |
5181 | tx_ring->atr_count = 0; | |
5182 | } | |
5183 | } | |
44df32c5 AD |
5184 | ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len, |
5185 | hdr_len); | |
44df32c5 | 5186 | ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED); |
9a799d71 | 5187 | |
44df32c5 AD |
5188 | } else { |
5189 | dev_kfree_skb_any(skb); | |
5190 | tx_ring->tx_buffer_info[first].time_stamp = 0; | |
5191 | tx_ring->next_to_use = first; | |
5192 | } | |
9a799d71 AK |
5193 | |
5194 | return NETDEV_TX_OK; | |
5195 | } | |
5196 | ||
5197 | /** | |
5198 | * ixgbe_get_stats - Get System Network Statistics | |
5199 | * @netdev: network interface device structure | |
5200 | * | |
5201 | * Returns the address of the device statistics structure. | |
5202 | * The statistics are actually updated from the timer callback. | |
5203 | **/ | |
5204 | static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev) | |
5205 | { | |
5206 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5207 | ||
5208 | /* only return the current stats */ | |
5209 | return &adapter->net_stats; | |
5210 | } | |
5211 | ||
5212 | /** | |
5213 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
5214 | * @netdev: network interface device structure | |
5215 | * @p: pointer to an address structure | |
5216 | * | |
5217 | * Returns 0 on success, negative on failure | |
5218 | **/ | |
5219 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
5220 | { | |
5221 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 5222 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
5223 | struct sockaddr *addr = p; |
5224 | ||
5225 | if (!is_valid_ether_addr(addr->sa_data)) | |
5226 | return -EADDRNOTAVAIL; | |
5227 | ||
5228 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 5229 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 5230 | |
b4617240 | 5231 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 AK |
5232 | |
5233 | return 0; | |
5234 | } | |
5235 | ||
6b73e10d BH |
5236 | static int |
5237 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
5238 | { | |
5239 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5240 | struct ixgbe_hw *hw = &adapter->hw; | |
5241 | u16 value; | |
5242 | int rc; | |
5243 | ||
5244 | if (prtad != hw->phy.mdio.prtad) | |
5245 | return -EINVAL; | |
5246 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
5247 | if (!rc) | |
5248 | rc = value; | |
5249 | return rc; | |
5250 | } | |
5251 | ||
5252 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
5253 | u16 addr, u16 value) | |
5254 | { | |
5255 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5256 | struct ixgbe_hw *hw = &adapter->hw; | |
5257 | ||
5258 | if (prtad != hw->phy.mdio.prtad) | |
5259 | return -EINVAL; | |
5260 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
5261 | } | |
5262 | ||
5263 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
5264 | { | |
5265 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5266 | ||
5267 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
5268 | } | |
5269 | ||
0365e6e4 PW |
5270 | /** |
5271 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 5272 | * netdev->dev_addrs |
0365e6e4 PW |
5273 | * @netdev: network interface device structure |
5274 | * | |
5275 | * Returns non-zero on failure | |
5276 | **/ | |
5277 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
5278 | { | |
5279 | int err = 0; | |
5280 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5281 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
5282 | ||
5283 | if (is_valid_ether_addr(mac->san_addr)) { | |
5284 | rtnl_lock(); | |
5285 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
5286 | rtnl_unlock(); | |
5287 | } | |
5288 | return err; | |
5289 | } | |
5290 | ||
5291 | /** | |
5292 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 5293 | * netdev->dev_addrs |
0365e6e4 PW |
5294 | * @netdev: network interface device structure |
5295 | * | |
5296 | * Returns non-zero on failure | |
5297 | **/ | |
5298 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
5299 | { | |
5300 | int err = 0; | |
5301 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
5302 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
5303 | ||
5304 | if (is_valid_ether_addr(mac->san_addr)) { | |
5305 | rtnl_lock(); | |
5306 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
5307 | rtnl_unlock(); | |
5308 | } | |
5309 | return err; | |
5310 | } | |
5311 | ||
9a799d71 AK |
5312 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5313 | /* | |
5314 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
5315 | * without having to re-enable interrupts. It's not called while | |
5316 | * the interrupt routine is executing. | |
5317 | */ | |
5318 | static void ixgbe_netpoll(struct net_device *netdev) | |
5319 | { | |
5320 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5321 | ||
5322 | disable_irq(adapter->pdev->irq); | |
5323 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; | |
5324 | ixgbe_intr(adapter->pdev->irq, netdev); | |
5325 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; | |
5326 | enable_irq(adapter->pdev->irq); | |
5327 | } | |
5328 | #endif | |
5329 | ||
0edc3527 SH |
5330 | static const struct net_device_ops ixgbe_netdev_ops = { |
5331 | .ndo_open = ixgbe_open, | |
5332 | .ndo_stop = ixgbe_close, | |
00829823 | 5333 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 5334 | .ndo_select_queue = ixgbe_select_queue, |
0edc3527 | 5335 | .ndo_get_stats = ixgbe_get_stats, |
e90d400c | 5336 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
5337 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
5338 | .ndo_validate_addr = eth_validate_addr, | |
5339 | .ndo_set_mac_address = ixgbe_set_mac, | |
5340 | .ndo_change_mtu = ixgbe_change_mtu, | |
5341 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
5342 | .ndo_vlan_rx_register = ixgbe_vlan_rx_register, | |
5343 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, | |
5344 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 5345 | .ndo_do_ioctl = ixgbe_ioctl, |
0edc3527 SH |
5346 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5347 | .ndo_poll_controller = ixgbe_netpoll, | |
5348 | #endif | |
332d4a7d YZ |
5349 | #ifdef IXGBE_FCOE |
5350 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
5351 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, | |
5352 | #endif /* IXGBE_FCOE */ | |
0edc3527 SH |
5353 | }; |
5354 | ||
9a799d71 AK |
5355 | /** |
5356 | * ixgbe_probe - Device Initialization Routine | |
5357 | * @pdev: PCI device information struct | |
5358 | * @ent: entry in ixgbe_pci_tbl | |
5359 | * | |
5360 | * Returns 0 on success, negative on failure | |
5361 | * | |
5362 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
5363 | * The OS initialization, configuring of the adapter private structure, | |
5364 | * and a hardware reset occur. | |
5365 | **/ | |
5366 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
b4617240 | 5367 | const struct pci_device_id *ent) |
9a799d71 AK |
5368 | { |
5369 | struct net_device *netdev; | |
5370 | struct ixgbe_adapter *adapter = NULL; | |
5371 | struct ixgbe_hw *hw; | |
5372 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
5373 | static int cards_found; |
5374 | int i, err, pci_using_dac; | |
eacd73f7 YZ |
5375 | #ifdef IXGBE_FCOE |
5376 | u16 device_caps; | |
5377 | #endif | |
c44ade9e | 5378 | u32 part_num, eec; |
9a799d71 | 5379 | |
9ce77666 | 5380 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
5381 | if (err) |
5382 | return err; | |
5383 | ||
6a35528a YH |
5384 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && |
5385 | !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
5386 | pci_using_dac = 1; |
5387 | } else { | |
284901a9 | 5388 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 5389 | if (err) { |
284901a9 | 5390 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
9a799d71 | 5391 | if (err) { |
b4617240 PW |
5392 | dev_err(&pdev->dev, "No usable DMA " |
5393 | "configuration, aborting\n"); | |
9a799d71 AK |
5394 | goto err_dma; |
5395 | } | |
5396 | } | |
5397 | pci_using_dac = 0; | |
5398 | } | |
5399 | ||
9ce77666 | 5400 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
5401 | IORESOURCE_MEM), ixgbe_driver_name); | |
9a799d71 | 5402 | if (err) { |
9ce77666 | 5403 | dev_err(&pdev->dev, |
5404 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
5405 | goto err_pci_reg; |
5406 | } | |
5407 | ||
6fabd715 PWJ |
5408 | err = pci_enable_pcie_error_reporting(pdev); |
5409 | if (err) { | |
5410 | dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed " | |
5411 | "0x%x\n", err); | |
5412 | /* non-fatal, continue */ | |
5413 | } | |
5414 | ||
9a799d71 | 5415 | pci_set_master(pdev); |
fb3b27bc | 5416 | pci_save_state(pdev); |
9a799d71 | 5417 | |
30eba97a | 5418 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES); |
9a799d71 AK |
5419 | if (!netdev) { |
5420 | err = -ENOMEM; | |
5421 | goto err_alloc_etherdev; | |
5422 | } | |
5423 | ||
9a799d71 AK |
5424 | SET_NETDEV_DEV(netdev, &pdev->dev); |
5425 | ||
5426 | pci_set_drvdata(pdev, netdev); | |
5427 | adapter = netdev_priv(netdev); | |
5428 | ||
5429 | adapter->netdev = netdev; | |
5430 | adapter->pdev = pdev; | |
5431 | hw = &adapter->hw; | |
5432 | hw->back = adapter; | |
5433 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
5434 | ||
05857980 JK |
5435 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
5436 | pci_resource_len(pdev, 0)); | |
9a799d71 AK |
5437 | if (!hw->hw_addr) { |
5438 | err = -EIO; | |
5439 | goto err_ioremap; | |
5440 | } | |
5441 | ||
5442 | for (i = 1; i <= 5; i++) { | |
5443 | if (pci_resource_len(pdev, i) == 0) | |
5444 | continue; | |
5445 | } | |
5446 | ||
0edc3527 | 5447 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 5448 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 5449 | netdev->watchdog_timeo = 5 * HZ; |
9a799d71 AK |
5450 | strcpy(netdev->name, pci_name(pdev)); |
5451 | ||
9a799d71 AK |
5452 | adapter->bd_number = cards_found; |
5453 | ||
9a799d71 AK |
5454 | /* Setup hw api */ |
5455 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 5456 | hw->mac.type = ii->mac; |
9a799d71 | 5457 | |
c44ade9e JB |
5458 | /* EEPROM */ |
5459 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
5460 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
5461 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
5462 | if (!(eec & (1 << 8))) | |
5463 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
5464 | ||
5465 | /* PHY */ | |
5466 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 5467 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
5468 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
5469 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
5470 | hw->phy.mdio.mmds = 0; | |
5471 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
5472 | hw->phy.mdio.dev = netdev; | |
5473 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
5474 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 DS |
5475 | |
5476 | /* set up this timer and work struct before calling get_invariants | |
5477 | * which might start the timer | |
5478 | */ | |
5479 | init_timer(&adapter->sfp_timer); | |
5480 | adapter->sfp_timer.function = &ixgbe_sfp_timer; | |
5481 | adapter->sfp_timer.data = (unsigned long) adapter; | |
5482 | ||
5483 | INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task); | |
c44ade9e | 5484 | |
e8e26350 PW |
5485 | /* multispeed fiber has its own tasklet, called from GPI SDP1 context */ |
5486 | INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task); | |
5487 | ||
5488 | /* a new SFP+ module arrival, called from GPI SDP2 context */ | |
5489 | INIT_WORK(&adapter->sfp_config_module_task, | |
5490 | ixgbe_sfp_config_module_task); | |
5491 | ||
8ca783ab | 5492 | ii->get_invariants(hw); |
9a799d71 AK |
5493 | |
5494 | /* setup the private structure */ | |
5495 | err = ixgbe_sw_init(adapter); | |
5496 | if (err) | |
5497 | goto err_sw_init; | |
5498 | ||
bf069c97 DS |
5499 | /* |
5500 | * If there is a fan on this device and it has failed log the | |
5501 | * failure. | |
5502 | */ | |
5503 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
5504 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
5505 | if (esdp & IXGBE_ESDP_SDP1) | |
5506 | DPRINTK(PROBE, CRIT, | |
5507 | "Fan has stopped, replace the adapter\n"); | |
5508 | } | |
5509 | ||
c44ade9e JB |
5510 | /* reset_hw fills in the perm_addr as well */ |
5511 | err = hw->mac.ops.reset_hw(hw); | |
8ca783ab DS |
5512 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
5513 | hw->mac.type == ixgbe_mac_82598EB) { | |
5514 | /* | |
5515 | * Start a kernel thread to watch for a module to arrive. | |
5516 | * Only do this for 82598, since 82599 will generate | |
5517 | * interrupts on module arrival. | |
5518 | */ | |
5519 | set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
5520 | mod_timer(&adapter->sfp_timer, | |
5521 | round_jiffies(jiffies + (2 * HZ))); | |
5522 | err = 0; | |
5523 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
88d2b81f DS |
5524 | dev_err(&adapter->pdev->dev, "failed to initialize because " |
5525 | "an unsupported SFP+ module type was detected.\n" | |
5526 | "Reload the driver after installing a supported " | |
5527 | "module.\n"); | |
04f165ef PW |
5528 | goto err_sw_init; |
5529 | } else if (err) { | |
c44ade9e JB |
5530 | dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err); |
5531 | goto err_sw_init; | |
5532 | } | |
5533 | ||
9a799d71 | 5534 | netdev->features = NETIF_F_SG | |
b4617240 PW |
5535 | NETIF_F_IP_CSUM | |
5536 | NETIF_F_HW_VLAN_TX | | |
5537 | NETIF_F_HW_VLAN_RX | | |
5538 | NETIF_F_HW_VLAN_FILTER; | |
9a799d71 | 5539 | |
e9990a9c | 5540 | netdev->features |= NETIF_F_IPV6_CSUM; |
9a799d71 | 5541 | netdev->features |= NETIF_F_TSO; |
9a799d71 | 5542 | netdev->features |= NETIF_F_TSO6; |
78b6f4ce | 5543 | netdev->features |= NETIF_F_GRO; |
ad31c402 | 5544 | |
45a5ead0 JB |
5545 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) |
5546 | netdev->features |= NETIF_F_SCTP_CSUM; | |
5547 | ||
ad31c402 JK |
5548 | netdev->vlan_features |= NETIF_F_TSO; |
5549 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 5550 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
ad31c402 JK |
5551 | netdev->vlan_features |= NETIF_F_SG; |
5552 | ||
2f90b865 AD |
5553 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) |
5554 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
5555 | ||
7a6b6f51 | 5556 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5557 | netdev->dcbnl_ops = &dcbnl_ops; |
5558 | #endif | |
5559 | ||
eacd73f7 YZ |
5560 | #ifdef IXGBE_FCOE |
5561 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { | |
5562 | if (hw->mac.ops.get_device_caps) { | |
5563 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
5564 | if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) { | |
5565 | netdev->features |= NETIF_F_FCOE_CRC; | |
5566 | netdev->features |= NETIF_F_FSO; | |
332d4a7d | 5567 | netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1; |
c4cf55e5 PWJ |
5568 | DPRINTK(DRV, INFO, "FCoE enabled, " |
5569 | "disabling Flow Director\n"); | |
5570 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
5571 | adapter->flags &= | |
5572 | ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
5573 | adapter->atr_sample_rate = 0; | |
eacd73f7 YZ |
5574 | } else { |
5575 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5576 | } | |
5577 | } | |
5578 | } | |
5579 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
5580 | if (pci_using_dac) |
5581 | netdev->features |= NETIF_F_HIGHDMA; | |
5582 | ||
df647b5c | 5583 | if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
5584 | netdev->features |= NETIF_F_LRO; |
5585 | ||
9a799d71 | 5586 | /* make sure the EEPROM is good */ |
c44ade9e | 5587 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
9a799d71 AK |
5588 | dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); |
5589 | err = -EIO; | |
5590 | goto err_eeprom; | |
5591 | } | |
5592 | ||
5593 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
5594 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
5595 | ||
c44ade9e JB |
5596 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
5597 | dev_err(&pdev->dev, "invalid MAC address\n"); | |
9a799d71 AK |
5598 | err = -EIO; |
5599 | goto err_eeprom; | |
5600 | } | |
5601 | ||
5602 | init_timer(&adapter->watchdog_timer); | |
5603 | adapter->watchdog_timer.function = &ixgbe_watchdog; | |
5604 | adapter->watchdog_timer.data = (unsigned long)adapter; | |
5605 | ||
5606 | INIT_WORK(&adapter->reset_task, ixgbe_reset_task); | |
cf8280ee | 5607 | INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task); |
9a799d71 | 5608 | |
021230d4 AV |
5609 | err = ixgbe_init_interrupt_scheme(adapter); |
5610 | if (err) | |
5611 | goto err_sw_init; | |
9a799d71 | 5612 | |
e8e26350 PW |
5613 | switch (pdev->device) { |
5614 | case IXGBE_DEV_ID_82599_KX4: | |
495dce12 WJP |
5615 | adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX | |
5616 | IXGBE_WUFC_MC | IXGBE_WUFC_BC); | |
bdf0a550 PWJ |
5617 | /* Enable ACPI wakeup in GRC */ |
5618 | IXGBE_WRITE_REG(hw, IXGBE_GRC, | |
5619 | (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME)); | |
e8e26350 PW |
5620 | break; |
5621 | default: | |
5622 | adapter->wol = 0; | |
5623 | break; | |
5624 | } | |
5625 | device_init_wakeup(&adapter->pdev->dev, true); | |
5626 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); | |
5627 | ||
04f165ef PW |
5628 | /* pick up the PCI bus settings for reporting later */ |
5629 | hw->mac.ops.get_bus_info(hw); | |
5630 | ||
9a799d71 | 5631 | /* print bus type/speed/width info */ |
7c510e4b | 5632 | dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n", |
e8e26350 PW |
5633 | ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s": |
5634 | (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"), | |
5635 | ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" : | |
5636 | (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" : | |
5637 | (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" : | |
b4617240 | 5638 | "Unknown"), |
7c510e4b | 5639 | netdev->dev_addr); |
c44ade9e | 5640 | ixgbe_read_pba_num_generic(hw, &part_num); |
e8e26350 PW |
5641 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
5642 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n", | |
5643 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
5644 | (part_num >> 8), (part_num & 0xff)); | |
5645 | else | |
5646 | dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n", | |
5647 | hw->mac.type, hw->phy.type, | |
5648 | (part_num >> 8), (part_num & 0xff)); | |
9a799d71 | 5649 | |
e8e26350 | 5650 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
0c254d86 | 5651 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for " |
b4617240 PW |
5652 | "this card is not sufficient for optimal " |
5653 | "performance.\n"); | |
0c254d86 | 5654 | dev_warn(&pdev->dev, "For optimal performance a x8 " |
b4617240 | 5655 | "PCI-Express slot is required.\n"); |
0c254d86 AK |
5656 | } |
5657 | ||
34b0368c PWJ |
5658 | /* save off EEPROM version number */ |
5659 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
5660 | ||
9a799d71 | 5661 | /* reset the hardware with the new settings */ |
794caeb2 | 5662 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 5663 | |
794caeb2 PWJ |
5664 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
5665 | /* We are running on a pre-production device, log a warning */ | |
5666 | dev_warn(&pdev->dev, "This device is a pre-production " | |
5667 | "adapter/LOM. Please be aware there may be issues " | |
5668 | "associated with your hardware. If you are " | |
5669 | "experiencing problems please contact your Intel or " | |
5670 | "hardware representative who provided you with this " | |
5671 | "hardware.\n"); | |
5672 | } | |
9a799d71 AK |
5673 | strcpy(netdev->name, "eth%d"); |
5674 | err = register_netdev(netdev); | |
5675 | if (err) | |
5676 | goto err_register; | |
5677 | ||
54386467 JB |
5678 | /* carrier off reporting is important to ethtool even BEFORE open */ |
5679 | netif_carrier_off(netdev); | |
5680 | ||
c4cf55e5 PWJ |
5681 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
5682 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
5683 | INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task); | |
5684 | ||
5dd2d332 | 5685 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 5686 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 5687 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
5688 | ixgbe_setup_dca(adapter); |
5689 | } | |
5690 | #endif | |
0365e6e4 PW |
5691 | /* add san mac addr to netdev */ |
5692 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 AK |
5693 | |
5694 | dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n"); | |
5695 | cards_found++; | |
5696 | return 0; | |
5697 | ||
5698 | err_register: | |
5eba3699 | 5699 | ixgbe_release_hw_control(adapter); |
7a921c93 | 5700 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
5701 | err_sw_init: |
5702 | err_eeprom: | |
c4900be0 DS |
5703 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); |
5704 | del_timer_sync(&adapter->sfp_timer); | |
5705 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5706 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5707 | cancel_work_sync(&adapter->sfp_config_module_task); | |
9a799d71 AK |
5708 | iounmap(hw->hw_addr); |
5709 | err_ioremap: | |
5710 | free_netdev(netdev); | |
5711 | err_alloc_etherdev: | |
9ce77666 | 5712 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
5713 | IORESOURCE_MEM)); | |
9a799d71 AK |
5714 | err_pci_reg: |
5715 | err_dma: | |
5716 | pci_disable_device(pdev); | |
5717 | return err; | |
5718 | } | |
5719 | ||
5720 | /** | |
5721 | * ixgbe_remove - Device Removal Routine | |
5722 | * @pdev: PCI device information struct | |
5723 | * | |
5724 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
5725 | * that it should release a PCI device. The could be caused by a | |
5726 | * Hot-Plug event, or because the driver is going to be removed from | |
5727 | * memory. | |
5728 | **/ | |
5729 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
5730 | { | |
5731 | struct net_device *netdev = pci_get_drvdata(pdev); | |
5732 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6fabd715 | 5733 | int err; |
9a799d71 AK |
5734 | |
5735 | set_bit(__IXGBE_DOWN, &adapter->state); | |
c4900be0 DS |
5736 | /* clear the module not found bit to make sure the worker won't |
5737 | * reschedule | |
5738 | */ | |
5739 | clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state); | |
9a799d71 AK |
5740 | del_timer_sync(&adapter->watchdog_timer); |
5741 | ||
c4900be0 DS |
5742 | del_timer_sync(&adapter->sfp_timer); |
5743 | cancel_work_sync(&adapter->watchdog_task); | |
5744 | cancel_work_sync(&adapter->sfp_task); | |
e8e26350 PW |
5745 | cancel_work_sync(&adapter->multispeed_fiber_task); |
5746 | cancel_work_sync(&adapter->sfp_config_module_task); | |
c4cf55e5 PWJ |
5747 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || |
5748 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
5749 | cancel_work_sync(&adapter->fdir_reinit_task); | |
9a799d71 AK |
5750 | flush_scheduled_work(); |
5751 | ||
5dd2d332 | 5752 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5753 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
5754 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
5755 | dca_remove_requester(&pdev->dev); | |
5756 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
5757 | } | |
5758 | ||
5759 | #endif | |
332d4a7d YZ |
5760 | #ifdef IXGBE_FCOE |
5761 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
5762 | ixgbe_cleanup_fcoe(adapter); | |
5763 | ||
5764 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
5765 | |
5766 | /* remove the added san mac */ | |
5767 | ixgbe_del_sanmac_netdev(netdev); | |
5768 | ||
c4900be0 DS |
5769 | if (netdev->reg_state == NETREG_REGISTERED) |
5770 | unregister_netdev(netdev); | |
9a799d71 | 5771 | |
7a921c93 | 5772 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 5773 | |
021230d4 | 5774 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5775 | |
5776 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 5777 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
5778 | IORESOURCE_MEM)); | |
9a799d71 | 5779 | |
021230d4 | 5780 | DPRINTK(PROBE, INFO, "complete\n"); |
021230d4 | 5781 | |
9a799d71 AK |
5782 | free_netdev(netdev); |
5783 | ||
6fabd715 PWJ |
5784 | err = pci_disable_pcie_error_reporting(pdev); |
5785 | if (err) | |
5786 | dev_err(&pdev->dev, | |
5787 | "pci_disable_pcie_error_reporting failed 0x%x\n", err); | |
5788 | ||
9a799d71 AK |
5789 | pci_disable_device(pdev); |
5790 | } | |
5791 | ||
5792 | /** | |
5793 | * ixgbe_io_error_detected - called when PCI error is detected | |
5794 | * @pdev: Pointer to PCI device | |
5795 | * @state: The current pci connection state | |
5796 | * | |
5797 | * This function is called after a PCI bus error affecting | |
5798 | * this device has been detected. | |
5799 | */ | |
5800 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
b4617240 | 5801 | pci_channel_state_t state) |
9a799d71 AK |
5802 | { |
5803 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5804 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5805 | |
5806 | netif_device_detach(netdev); | |
5807 | ||
3044b8d1 BL |
5808 | if (state == pci_channel_io_perm_failure) |
5809 | return PCI_ERS_RESULT_DISCONNECT; | |
5810 | ||
9a799d71 AK |
5811 | if (netif_running(netdev)) |
5812 | ixgbe_down(adapter); | |
5813 | pci_disable_device(pdev); | |
5814 | ||
b4617240 | 5815 | /* Request a slot reset. */ |
9a799d71 AK |
5816 | return PCI_ERS_RESULT_NEED_RESET; |
5817 | } | |
5818 | ||
5819 | /** | |
5820 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
5821 | * @pdev: Pointer to PCI device | |
5822 | * | |
5823 | * Restart the card from scratch, as if from a cold-boot. | |
5824 | */ | |
5825 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
5826 | { | |
5827 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5828 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
6fabd715 PWJ |
5829 | pci_ers_result_t result; |
5830 | int err; | |
9a799d71 | 5831 | |
9ce77666 | 5832 | if (pci_enable_device_mem(pdev)) { |
9a799d71 | 5833 | DPRINTK(PROBE, ERR, |
b4617240 | 5834 | "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
5835 | result = PCI_ERS_RESULT_DISCONNECT; |
5836 | } else { | |
5837 | pci_set_master(pdev); | |
5838 | pci_restore_state(pdev); | |
9a799d71 | 5839 | |
dd4d8ca6 | 5840 | pci_wake_from_d3(pdev, false); |
9a799d71 | 5841 | |
6fabd715 | 5842 | ixgbe_reset(adapter); |
88512539 | 5843 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
5844 | result = PCI_ERS_RESULT_RECOVERED; |
5845 | } | |
5846 | ||
5847 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
5848 | if (err) { | |
5849 | dev_err(&pdev->dev, | |
5850 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err); | |
5851 | /* non-fatal, continue */ | |
5852 | } | |
9a799d71 | 5853 | |
6fabd715 | 5854 | return result; |
9a799d71 AK |
5855 | } |
5856 | ||
5857 | /** | |
5858 | * ixgbe_io_resume - called when traffic can start flowing again. | |
5859 | * @pdev: Pointer to PCI device | |
5860 | * | |
5861 | * This callback is called when the error recovery driver tells us that | |
5862 | * its OK to resume normal operation. | |
5863 | */ | |
5864 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
5865 | { | |
5866 | struct net_device *netdev = pci_get_drvdata(pdev); | |
454d7c9b | 5867 | struct ixgbe_adapter *adapter = netdev_priv(netdev); |
9a799d71 AK |
5868 | |
5869 | if (netif_running(netdev)) { | |
5870 | if (ixgbe_up(adapter)) { | |
5871 | DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n"); | |
5872 | return; | |
5873 | } | |
5874 | } | |
5875 | ||
5876 | netif_device_attach(netdev); | |
9a799d71 AK |
5877 | } |
5878 | ||
5879 | static struct pci_error_handlers ixgbe_err_handler = { | |
5880 | .error_detected = ixgbe_io_error_detected, | |
5881 | .slot_reset = ixgbe_io_slot_reset, | |
5882 | .resume = ixgbe_io_resume, | |
5883 | }; | |
5884 | ||
5885 | static struct pci_driver ixgbe_driver = { | |
5886 | .name = ixgbe_driver_name, | |
5887 | .id_table = ixgbe_pci_tbl, | |
5888 | .probe = ixgbe_probe, | |
5889 | .remove = __devexit_p(ixgbe_remove), | |
5890 | #ifdef CONFIG_PM | |
5891 | .suspend = ixgbe_suspend, | |
5892 | .resume = ixgbe_resume, | |
5893 | #endif | |
5894 | .shutdown = ixgbe_shutdown, | |
5895 | .err_handler = &ixgbe_err_handler | |
5896 | }; | |
5897 | ||
5898 | /** | |
5899 | * ixgbe_init_module - Driver Registration Routine | |
5900 | * | |
5901 | * ixgbe_init_module is the first routine called when the driver is | |
5902 | * loaded. All it does is register with the PCI subsystem. | |
5903 | **/ | |
5904 | static int __init ixgbe_init_module(void) | |
5905 | { | |
5906 | int ret; | |
5907 | printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name, | |
5908 | ixgbe_driver_string, ixgbe_driver_version); | |
5909 | ||
5910 | printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright); | |
5911 | ||
5dd2d332 | 5912 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5913 | dca_register_notify(&dca_notifier); |
bd0362dd | 5914 | #endif |
5dd2d332 | 5915 | |
9a799d71 AK |
5916 | ret = pci_register_driver(&ixgbe_driver); |
5917 | return ret; | |
5918 | } | |
b4617240 | 5919 | |
9a799d71 AK |
5920 | module_init(ixgbe_init_module); |
5921 | ||
5922 | /** | |
5923 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
5924 | * | |
5925 | * ixgbe_exit_module is called just before the driver is removed | |
5926 | * from memory. | |
5927 | **/ | |
5928 | static void __exit ixgbe_exit_module(void) | |
5929 | { | |
5dd2d332 | 5930 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
5931 | dca_unregister_notify(&dca_notifier); |
5932 | #endif | |
9a799d71 AK |
5933 | pci_unregister_driver(&ixgbe_driver); |
5934 | } | |
bd0362dd | 5935 | |
5dd2d332 | 5936 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 5937 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
b4617240 | 5938 | void *p) |
bd0362dd JC |
5939 | { |
5940 | int ret_val; | |
5941 | ||
5942 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
b4617240 | 5943 | __ixgbe_notify_dca); |
bd0362dd JC |
5944 | |
5945 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
5946 | } | |
b453368d | 5947 | |
5dd2d332 | 5948 | #endif /* CONFIG_IXGBE_DCA */ |
b453368d AD |
5949 | #ifdef DEBUG |
5950 | /** | |
5951 | * ixgbe_get_hw_dev_name - return device name string | |
5952 | * used by hardware layer to print debugging information | |
5953 | **/ | |
5954 | char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw) | |
5955 | { | |
5956 | struct ixgbe_adapter *adapter = hw->back; | |
5957 | return adapter->netdev->name; | |
5958 | } | |
bd0362dd | 5959 | |
b453368d | 5960 | #endif |
9a799d71 AK |
5961 | module_exit(ixgbe_exit_module); |
5962 | ||
5963 | /* ixgbe_main.c */ |