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fe15e8e1 DS |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
a52055e0 | 4 | Copyright(c) 1999 - 2011 Intel Corporation. |
fe15e8e1 DS |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/pci.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/sched.h> | |
31 | ||
32 | #include "ixgbe.h" | |
33 | #include "ixgbe_phy.h" | |
fe15e8e1 DS |
34 | |
35 | #define IXGBE_X540_MAX_TX_QUEUES 128 | |
36 | #define IXGBE_X540_MAX_RX_QUEUES 128 | |
37 | #define IXGBE_X540_RAR_ENTRIES 128 | |
38 | #define IXGBE_X540_MC_TBL_SIZE 128 | |
39 | #define IXGBE_X540_VFT_TBL_SIZE 128 | |
40 | ||
41 | static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); | |
42 | static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); | |
43 | static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); | |
44 | static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); | |
45 | static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); | |
46 | static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); | |
47 | ||
b93a2226 | 48 | static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
49 | { |
50 | return ixgbe_media_type_copper; | |
51 | } | |
52 | ||
53 | static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw) | |
54 | { | |
55 | struct ixgbe_mac_info *mac = &hw->mac; | |
56 | ||
57 | /* Call PHY identify routine to get the phy type */ | |
58 | ixgbe_identify_phy_generic(hw); | |
59 | ||
60 | mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; | |
61 | mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; | |
62 | mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; | |
63 | mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; | |
64 | mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; | |
65 | mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); | |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
70 | /** | |
71 | * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires | |
72 | * @hw: pointer to hardware structure | |
73 | * @speed: new link speed | |
74 | * @autoneg: true if autonegotiation enabled | |
75 | * @autoneg_wait_to_complete: true when waiting for completion is needed | |
76 | **/ | |
b93a2226 DS |
77 | static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, |
78 | ixgbe_link_speed speed, bool autoneg, | |
79 | bool autoneg_wait_to_complete) | |
fe15e8e1 DS |
80 | { |
81 | return hw->phy.ops.setup_link_speed(hw, speed, autoneg, | |
82 | autoneg_wait_to_complete); | |
83 | } | |
84 | ||
85 | /** | |
86 | * ixgbe_reset_hw_X540 - Perform hardware reset | |
87 | * @hw: pointer to hardware structure | |
88 | * | |
89 | * Resets the hardware by resetting the transmit and receive units, masks | |
90 | * and clears all interrupts, perform a PHY reset, and perform a link (MAC) | |
91 | * reset. | |
92 | **/ | |
b93a2226 | 93 | static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
94 | { |
95 | ixgbe_link_speed link_speed; | |
96 | s32 status = 0; | |
97 | u32 ctrl; | |
98 | u32 ctrl_ext; | |
99 | u32 reset_bit; | |
100 | u32 i; | |
101 | u32 autoc; | |
102 | u32 autoc2; | |
103 | bool link_up = false; | |
104 | ||
105 | /* Call adapter stop to disable tx/rx and clear interrupts */ | |
106 | hw->mac.ops.stop_adapter(hw); | |
107 | ||
108 | /* | |
109 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | |
110 | * access and verify no pending requests before reset | |
111 | */ | |
a4297dc2 | 112 | ixgbe_disable_pcie_master(hw); |
fe15e8e1 | 113 | |
a4297dc2 | 114 | mac_reset_top: |
fe15e8e1 DS |
115 | /* |
116 | * Issue global reset to the MAC. Needs to be SW reset if link is up. | |
117 | * If link reset is used when link is up, it might reset the PHY when | |
118 | * mng is using it. If link is down or the flag to force full link | |
119 | * reset is set, then perform link reset. | |
120 | */ | |
121 | if (hw->force_full_reset) { | |
122 | reset_bit = IXGBE_CTRL_LNK_RST; | |
123 | } else { | |
124 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
125 | if (!link_up) | |
126 | reset_bit = IXGBE_CTRL_LNK_RST; | |
127 | else | |
128 | reset_bit = IXGBE_CTRL_RST; | |
129 | } | |
130 | ||
131 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
2c4db944 | 132 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | reset_bit)); |
fe15e8e1 DS |
133 | IXGBE_WRITE_FLUSH(hw); |
134 | ||
135 | /* Poll for reset bit to self-clear indicating reset is complete */ | |
136 | for (i = 0; i < 10; i++) { | |
137 | udelay(1); | |
138 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
2c4db944 | 139 | if (!(ctrl & reset_bit)) |
fe15e8e1 DS |
140 | break; |
141 | } | |
2c4db944 | 142 | if (ctrl & reset_bit) { |
fe15e8e1 DS |
143 | status = IXGBE_ERR_RESET_FAILED; |
144 | hw_dbg(hw, "Reset polling failed to complete.\n"); | |
145 | } | |
146 | ||
a4297dc2 ET |
147 | /* |
148 | * Double resets are required for recovery from certain error | |
149 | * conditions. Between resets, it is necessary to stall to allow time | |
150 | * for any pending HW events to complete. We use 1usec since that is | |
151 | * what is needed for ixgbe_disable_pcie_master(). The second reset | |
152 | * then clears out any effects of those events. | |
153 | */ | |
154 | if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { | |
155 | hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; | |
156 | udelay(1); | |
157 | goto mac_reset_top; | |
158 | } | |
159 | ||
fe15e8e1 DS |
160 | /* Clear PF Reset Done bit so PF/VF Mail Ops can work */ |
161 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
162 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
163 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
164 | ||
165 | msleep(50); | |
166 | ||
167 | /* Set the Rx packet buffer size. */ | |
168 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); | |
169 | ||
170 | /* Store the permanent mac address */ | |
171 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); | |
172 | ||
173 | /* | |
174 | * Store the original AUTOC/AUTOC2 values if they have not been | |
175 | * stored off yet. Otherwise restore the stored original | |
176 | * values since the reset operation sets back to defaults. | |
177 | */ | |
178 | autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
179 | autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); | |
180 | if (hw->mac.orig_link_settings_stored == false) { | |
181 | hw->mac.orig_autoc = autoc; | |
182 | hw->mac.orig_autoc2 = autoc2; | |
183 | hw->mac.orig_link_settings_stored = true; | |
184 | } else { | |
185 | if (autoc != hw->mac.orig_autoc) | |
186 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc | | |
187 | IXGBE_AUTOC_AN_RESTART)); | |
188 | ||
189 | if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != | |
190 | (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { | |
191 | autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; | |
192 | autoc2 |= (hw->mac.orig_autoc2 & | |
193 | IXGBE_AUTOC2_UPPER_MASK); | |
194 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); | |
195 | } | |
196 | } | |
197 | ||
198 | /* | |
199 | * Store MAC address from RAR0, clear receive address registers, and | |
200 | * clear the multicast table. Also reset num_rar_entries to 128, | |
201 | * since we modify this value when programming the SAN MAC address. | |
202 | */ | |
93cb38dc | 203 | hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES; |
fe15e8e1 DS |
204 | hw->mac.ops.init_rx_addrs(hw); |
205 | ||
206 | /* Store the permanent mac address */ | |
207 | hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); | |
208 | ||
209 | /* Store the permanent SAN mac address */ | |
210 | hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); | |
211 | ||
212 | /* Add the SAN MAC address to the RAR only if it's a valid address */ | |
213 | if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { | |
214 | hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, | |
215 | hw->mac.san_addr, 0, IXGBE_RAH_AV); | |
216 | ||
217 | /* Reserve the last RAR for the SAN MAC address */ | |
218 | hw->mac.num_rar_entries--; | |
219 | } | |
220 | ||
221 | /* Store the alternative WWNN/WWPN prefix */ | |
222 | hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, | |
223 | &hw->mac.wwpn_prefix); | |
224 | ||
225 | return status; | |
226 | } | |
227 | ||
7184b7cf ET |
228 | /** |
229 | * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx | |
230 | * @hw: pointer to hardware structure | |
231 | * | |
232 | * Starts the hardware using the generic start_hw function | |
233 | * and the generation start_hw function. | |
234 | * Then performs revision-specific operations, if any. | |
235 | **/ | |
236 | static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) | |
237 | { | |
238 | s32 ret_val = 0; | |
239 | ||
240 | ret_val = ixgbe_start_hw_generic(hw); | |
241 | if (ret_val != 0) | |
242 | goto out; | |
243 | ||
244 | ret_val = ixgbe_start_hw_gen2(hw); | |
245 | ||
246 | out: | |
247 | return ret_val; | |
248 | } | |
249 | ||
fe15e8e1 DS |
250 | /** |
251 | * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type | |
252 | * @hw: pointer to hardware structure | |
253 | * | |
254 | * Determines physical layer capabilities of the current configuration. | |
255 | **/ | |
b93a2226 | 256 | static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
257 | { |
258 | u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; | |
259 | u16 ext_ability = 0; | |
260 | ||
261 | hw->phy.ops.identify(hw); | |
262 | ||
263 | hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD, | |
264 | &ext_ability); | |
265 | if (ext_ability & MDIO_PMA_EXTABLE_10GBT) | |
266 | physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; | |
267 | if (ext_ability & MDIO_PMA_EXTABLE_1000BT) | |
268 | physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; | |
269 | if (ext_ability & MDIO_PMA_EXTABLE_100BTX) | |
270 | physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; | |
271 | ||
272 | return physical_layer; | |
273 | } | |
274 | ||
275 | /** | |
77ed18f3 ET |
276 | * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params |
277 | * @hw: pointer to hardware structure | |
278 | * | |
279 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the | |
280 | * ixgbe_hw struct in order to set up EEPROM access. | |
fe15e8e1 | 281 | **/ |
b93a2226 | 282 | static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
283 | { |
284 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; | |
285 | u32 eec; | |
286 | u16 eeprom_size; | |
287 | ||
288 | if (eeprom->type == ixgbe_eeprom_uninitialized) { | |
289 | eeprom->semaphore_delay = 10; | |
290 | eeprom->type = ixgbe_flash; | |
291 | ||
292 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
293 | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> | |
294 | IXGBE_EEC_SIZE_SHIFT); | |
295 | eeprom->word_size = 1 << (eeprom_size + | |
296 | IXGBE_EEPROM_WORD_SIZE_SHIFT); | |
297 | ||
298 | hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", | |
77ed18f3 | 299 | eeprom->type, eeprom->word_size); |
fe15e8e1 DS |
300 | } |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
305 | /** | |
306 | * ixgbe_read_eerd_X540 - Read EEPROM word using EERD | |
307 | * @hw: pointer to hardware structure | |
308 | * @offset: offset of word in the EEPROM to read | |
309 | * @data: word read from the EERPOM | |
310 | **/ | |
b93a2226 | 311 | static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) |
fe15e8e1 DS |
312 | { |
313 | s32 status; | |
314 | ||
5e655105 | 315 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) |
fe15e8e1 DS |
316 | status = ixgbe_read_eerd_generic(hw, offset, data); |
317 | else | |
318 | status = IXGBE_ERR_SWFW_SYNC; | |
319 | ||
320 | ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM); | |
321 | return status; | |
322 | } | |
323 | ||
324 | /** | |
eb9c3e3e ET |
325 | * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR |
326 | * @hw: pointer to hardware structure | |
327 | * @offset: offset of word in the EEPROM to write | |
328 | * @data: word write to the EEPROM | |
fe15e8e1 | 329 | * |
eb9c3e3e | 330 | * Write a 16 bit word to the EEPROM using the EEWR register. |
fe15e8e1 | 331 | **/ |
b93a2226 | 332 | static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) |
fe15e8e1 | 333 | { |
eb9c3e3e | 334 | s32 status = 0; |
fe15e8e1 | 335 | |
eb9c3e3e ET |
336 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) |
337 | status = ixgbe_write_eewr_generic(hw, offset, data); | |
338 | else | |
fe15e8e1 | 339 | status = IXGBE_ERR_SWFW_SYNC; |
fe15e8e1 | 340 | |
eb9c3e3e | 341 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
fe15e8e1 DS |
342 | return status; |
343 | } | |
344 | ||
345 | /** | |
eb9c3e3e ET |
346 | * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum |
347 | * | |
348 | * This function does not use synchronization for EERD and EEWR. It can | |
349 | * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. | |
350 | * | |
351 | * @hw: pointer to hardware structure | |
fe15e8e1 DS |
352 | **/ |
353 | static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) | |
354 | { | |
355 | u16 i; | |
356 | u16 j; | |
357 | u16 checksum = 0; | |
358 | u16 length = 0; | |
359 | u16 pointer = 0; | |
360 | u16 word = 0; | |
361 | ||
eb9c3e3e ET |
362 | /* |
363 | * Do not use hw->eeprom.ops.read because we do not want to take | |
364 | * the synchronization semaphores here. Instead use | |
365 | * ixgbe_read_eerd_generic | |
366 | */ | |
367 | ||
fe15e8e1 DS |
368 | /* Include 0x0-0x3F in the checksum */ |
369 | for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { | |
eb9c3e3e | 370 | if (ixgbe_read_eerd_generic(hw, i, &word) != 0) { |
fe15e8e1 DS |
371 | hw_dbg(hw, "EEPROM read failed\n"); |
372 | break; | |
373 | } | |
374 | checksum += word; | |
375 | } | |
376 | ||
377 | /* | |
378 | * Include all data from pointers 0x3, 0x6-0xE. This excludes the | |
379 | * FW, PHY module, and PCIe Expansion/Option ROM pointers. | |
380 | */ | |
381 | for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { | |
382 | if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) | |
383 | continue; | |
384 | ||
eb9c3e3e | 385 | if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) { |
fe15e8e1 DS |
386 | hw_dbg(hw, "EEPROM read failed\n"); |
387 | break; | |
388 | } | |
389 | ||
390 | /* Skip pointer section if the pointer is invalid. */ | |
391 | if (pointer == 0xFFFF || pointer == 0 || | |
392 | pointer >= hw->eeprom.word_size) | |
393 | continue; | |
394 | ||
eb9c3e3e | 395 | if (ixgbe_read_eerd_generic(hw, pointer, &length) != 0) { |
fe15e8e1 DS |
396 | hw_dbg(hw, "EEPROM read failed\n"); |
397 | break; | |
398 | } | |
399 | ||
400 | /* Skip pointer section if length is invalid. */ | |
401 | if (length == 0xFFFF || length == 0 || | |
402 | (pointer + length) >= hw->eeprom.word_size) | |
403 | continue; | |
404 | ||
405 | for (j = pointer+1; j <= pointer+length; j++) { | |
eb9c3e3e | 406 | if (ixgbe_read_eerd_generic(hw, j, &word) != 0) { |
fe15e8e1 DS |
407 | hw_dbg(hw, "EEPROM read failed\n"); |
408 | break; | |
409 | } | |
410 | checksum += word; | |
411 | } | |
412 | } | |
413 | ||
414 | checksum = (u16)IXGBE_EEPROM_SUM - checksum; | |
415 | ||
416 | return checksum; | |
417 | } | |
418 | ||
eb9c3e3e ET |
419 | /** |
420 | * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum | |
421 | * @hw: pointer to hardware structure | |
422 | * @checksum_val: calculated checksum | |
423 | * | |
424 | * Performs checksum calculation and validates the EEPROM checksum. If the | |
425 | * caller does not need checksum_val, the value can be NULL. | |
426 | **/ | |
427 | static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, | |
428 | u16 *checksum_val) | |
429 | { | |
430 | s32 status; | |
431 | u16 checksum; | |
432 | u16 read_checksum = 0; | |
433 | ||
434 | /* | |
435 | * Read the first word from the EEPROM. If this times out or fails, do | |
436 | * not continue or we could be in for a very long wait while every | |
437 | * EEPROM read fails | |
438 | */ | |
439 | status = hw->eeprom.ops.read(hw, 0, &checksum); | |
440 | ||
441 | if (status != 0) { | |
442 | hw_dbg(hw, "EEPROM read failed\n"); | |
443 | goto out; | |
444 | } | |
445 | ||
446 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { | |
447 | checksum = hw->eeprom.ops.calc_checksum(hw); | |
448 | ||
449 | /* | |
450 | * Do not use hw->eeprom.ops.read because we do not want to take | |
451 | * the synchronization semaphores twice here. | |
452 | */ | |
453 | ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, | |
454 | &read_checksum); | |
455 | ||
456 | /* | |
457 | * Verify read checksum from EEPROM is the same as | |
458 | * calculated checksum | |
459 | */ | |
460 | if (read_checksum != checksum) | |
461 | status = IXGBE_ERR_EEPROM_CHECKSUM; | |
462 | ||
463 | /* If the user cares, return the calculated checksum */ | |
464 | if (checksum_val) | |
465 | *checksum_val = checksum; | |
466 | } else { | |
467 | status = IXGBE_ERR_SWFW_SYNC; | |
468 | } | |
469 | ||
470 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
471 | out: | |
472 | return status; | |
473 | } | |
474 | ||
fe15e8e1 DS |
475 | /** |
476 | * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash | |
477 | * @hw: pointer to hardware structure | |
478 | * | |
479 | * After writing EEPROM to shadow RAM using EEWR register, software calculates | |
480 | * checksum and updates the EEPROM and instructs the hardware to update | |
481 | * the flash. | |
482 | **/ | |
b93a2226 | 483 | static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) |
fe15e8e1 DS |
484 | { |
485 | s32 status; | |
eb9c3e3e | 486 | u16 checksum; |
fe15e8e1 | 487 | |
eb9c3e3e ET |
488 | /* |
489 | * Read the first word from the EEPROM. If this times out or fails, do | |
490 | * not continue or we could be in for a very long wait while every | |
491 | * EEPROM read fails | |
492 | */ | |
493 | status = hw->eeprom.ops.read(hw, 0, &checksum); | |
494 | ||
495 | if (status != 0) | |
496 | hw_dbg(hw, "EEPROM read failed\n"); | |
497 | ||
498 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { | |
499 | checksum = hw->eeprom.ops.calc_checksum(hw); | |
fe15e8e1 | 500 | |
eb9c3e3e ET |
501 | /* |
502 | * Do not use hw->eeprom.ops.write because we do not want to | |
503 | * take the synchronization semaphores twice here. | |
504 | */ | |
505 | status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, | |
506 | checksum); | |
507 | ||
508 | if (status == 0) | |
fe15e8e1 | 509 | status = ixgbe_update_flash_X540(hw); |
eb9c3e3e ET |
510 | else |
511 | status = IXGBE_ERR_SWFW_SYNC; | |
512 | } | |
513 | ||
514 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); | |
fe15e8e1 DS |
515 | |
516 | return status; | |
517 | } | |
518 | ||
519 | /** | |
520 | * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device | |
521 | * @hw: pointer to hardware structure | |
522 | * | |
523 | * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy | |
524 | * EEPROM from shadow RAM to the flash device. | |
525 | **/ | |
526 | static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) | |
527 | { | |
528 | u32 flup; | |
529 | s32 status = IXGBE_ERR_EEPROM; | |
530 | ||
531 | status = ixgbe_poll_flash_update_done_X540(hw); | |
532 | if (status == IXGBE_ERR_EEPROM) { | |
533 | hw_dbg(hw, "Flash update time out\n"); | |
534 | goto out; | |
535 | } | |
536 | ||
537 | flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP; | |
538 | IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); | |
539 | ||
540 | status = ixgbe_poll_flash_update_done_X540(hw); | |
2ea5ea5f | 541 | if (status == 0) |
fe15e8e1 DS |
542 | hw_dbg(hw, "Flash update complete\n"); |
543 | else | |
544 | hw_dbg(hw, "Flash update time out\n"); | |
545 | ||
546 | if (hw->revision_id == 0) { | |
547 | flup = IXGBE_READ_REG(hw, IXGBE_EEC); | |
548 | ||
549 | if (flup & IXGBE_EEC_SEC1VAL) { | |
550 | flup |= IXGBE_EEC_FLUP; | |
551 | IXGBE_WRITE_REG(hw, IXGBE_EEC, flup); | |
552 | } | |
553 | ||
554 | status = ixgbe_poll_flash_update_done_X540(hw); | |
2ea5ea5f | 555 | if (status == 0) |
fe15e8e1 DS |
556 | hw_dbg(hw, "Flash update complete\n"); |
557 | else | |
558 | hw_dbg(hw, "Flash update time out\n"); | |
fe15e8e1 DS |
559 | } |
560 | out: | |
561 | return status; | |
562 | } | |
563 | ||
564 | /** | |
565 | * ixgbe_poll_flash_update_done_X540 - Poll flash update status | |
566 | * @hw: pointer to hardware structure | |
567 | * | |
568 | * Polls the FLUDONE (bit 26) of the EEC Register to determine when the | |
569 | * flash update is done. | |
570 | **/ | |
571 | static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) | |
572 | { | |
573 | u32 i; | |
574 | u32 reg; | |
575 | s32 status = IXGBE_ERR_EEPROM; | |
576 | ||
577 | for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { | |
578 | reg = IXGBE_READ_REG(hw, IXGBE_EEC); | |
579 | if (reg & IXGBE_EEC_FLUDONE) { | |
580 | status = 0; | |
581 | break; | |
582 | } | |
583 | udelay(5); | |
584 | } | |
585 | return status; | |
586 | } | |
587 | ||
588 | /** | |
589 | * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore | |
590 | * @hw: pointer to hardware structure | |
591 | * @mask: Mask to specify which semaphore to acquire | |
592 | * | |
593 | * Acquires the SWFW semaphore thought the SW_FW_SYNC register for | |
594 | * the specified function (CSR, PHY0, PHY1, NVM, Flash) | |
595 | **/ | |
596 | static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) | |
597 | { | |
598 | u32 swfw_sync; | |
599 | u32 swmask = mask; | |
600 | u32 fwmask = mask << 5; | |
601 | u32 hwmask = 0; | |
602 | u32 timeout = 200; | |
603 | u32 i; | |
604 | ||
605 | if (swmask == IXGBE_GSSR_EEP_SM) | |
606 | hwmask = IXGBE_GSSR_FLASH_SM; | |
607 | ||
608 | for (i = 0; i < timeout; i++) { | |
609 | /* | |
610 | * SW NVM semaphore bit is used for access to all | |
611 | * SW_FW_SYNC bits (not just NVM) | |
612 | */ | |
613 | if (ixgbe_get_swfw_sync_semaphore(hw)) | |
614 | return IXGBE_ERR_SWFW_SYNC; | |
615 | ||
616 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | |
617 | if (!(swfw_sync & (fwmask | swmask | hwmask))) { | |
618 | swfw_sync |= swmask; | |
619 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); | |
620 | ixgbe_release_swfw_sync_semaphore(hw); | |
621 | break; | |
622 | } else { | |
623 | /* | |
624 | * Firmware currently using resource (fwmask), | |
625 | * hardware currently using resource (hwmask), | |
626 | * or other software thread currently using | |
627 | * resource (swmask) | |
628 | */ | |
629 | ixgbe_release_swfw_sync_semaphore(hw); | |
032b4325 | 630 | usleep_range(5000, 10000); |
fe15e8e1 DS |
631 | } |
632 | } | |
633 | ||
634 | /* | |
635 | * If the resource is not released by the FW/HW the SW can assume that | |
636 | * the FW/HW malfunctions. In that case the SW should sets the | |
637 | * SW bit(s) of the requested resource(s) while ignoring the | |
638 | * corresponding FW/HW bits in the SW_FW_SYNC register. | |
639 | */ | |
640 | if (i >= timeout) { | |
641 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | |
642 | if (swfw_sync & (fwmask | hwmask)) { | |
643 | if (ixgbe_get_swfw_sync_semaphore(hw)) | |
644 | return IXGBE_ERR_SWFW_SYNC; | |
645 | ||
646 | swfw_sync |= swmask; | |
647 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); | |
648 | ixgbe_release_swfw_sync_semaphore(hw); | |
649 | } | |
650 | } | |
651 | ||
032b4325 | 652 | usleep_range(5000, 10000); |
fe15e8e1 DS |
653 | return 0; |
654 | } | |
655 | ||
656 | /** | |
657 | * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore | |
658 | * @hw: pointer to hardware structure | |
659 | * @mask: Mask to specify which semaphore to release | |
660 | * | |
25985edc | 661 | * Releases the SWFW semaphore through the SW_FW_SYNC register |
fe15e8e1 DS |
662 | * for the specified function (CSR, PHY0, PHY1, EVM, Flash) |
663 | **/ | |
664 | static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) | |
665 | { | |
666 | u32 swfw_sync; | |
667 | u32 swmask = mask; | |
668 | ||
669 | ixgbe_get_swfw_sync_semaphore(hw); | |
670 | ||
671 | swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | |
672 | swfw_sync &= ~swmask; | |
673 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync); | |
674 | ||
675 | ixgbe_release_swfw_sync_semaphore(hw); | |
032b4325 | 676 | usleep_range(5000, 10000); |
fe15e8e1 DS |
677 | } |
678 | ||
679 | /** | |
680 | * ixgbe_get_nvm_semaphore - Get hardware semaphore | |
681 | * @hw: pointer to hardware structure | |
682 | * | |
683 | * Sets the hardware semaphores so SW/FW can gain control of shared resources | |
684 | **/ | |
685 | static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) | |
686 | { | |
687 | s32 status = IXGBE_ERR_EEPROM; | |
688 | u32 timeout = 2000; | |
689 | u32 i; | |
690 | u32 swsm; | |
691 | ||
692 | /* Get SMBI software semaphore between device drivers first */ | |
693 | for (i = 0; i < timeout; i++) { | |
694 | /* | |
695 | * If the SMBI bit is 0 when we read it, then the bit will be | |
696 | * set and we have the semaphore | |
697 | */ | |
698 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
699 | if (!(swsm & IXGBE_SWSM_SMBI)) { | |
700 | status = 0; | |
701 | break; | |
702 | } | |
703 | udelay(50); | |
704 | } | |
705 | ||
706 | /* Now get the semaphore between SW/FW through the REGSMP bit */ | |
707 | if (status) { | |
708 | for (i = 0; i < timeout; i++) { | |
709 | swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | |
710 | if (!(swsm & IXGBE_SWFW_REGSMP)) | |
711 | break; | |
712 | ||
713 | udelay(50); | |
714 | } | |
715 | } else { | |
716 | hw_dbg(hw, "Software semaphore SMBI between device drivers " | |
717 | "not granted.\n"); | |
718 | } | |
719 | ||
720 | return status; | |
721 | } | |
722 | ||
723 | /** | |
724 | * ixgbe_release_nvm_semaphore - Release hardware semaphore | |
725 | * @hw: pointer to hardware structure | |
726 | * | |
727 | * This function clears hardware semaphore bits. | |
728 | **/ | |
729 | static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) | |
730 | { | |
731 | u32 swsm; | |
732 | ||
733 | /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ | |
734 | ||
735 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); | |
736 | swsm &= ~IXGBE_SWSM_SMBI; | |
737 | IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); | |
738 | ||
739 | swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); | |
740 | swsm &= ~IXGBE_SWFW_REGSMP; | |
741 | IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm); | |
742 | ||
743 | IXGBE_WRITE_FLUSH(hw); | |
744 | } | |
745 | ||
746 | static struct ixgbe_mac_operations mac_ops_X540 = { | |
747 | .init_hw = &ixgbe_init_hw_generic, | |
748 | .reset_hw = &ixgbe_reset_hw_X540, | |
7184b7cf | 749 | .start_hw = &ixgbe_start_hw_X540, |
fe15e8e1 DS |
750 | .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, |
751 | .get_media_type = &ixgbe_get_media_type_X540, | |
752 | .get_supported_physical_layer = | |
753 | &ixgbe_get_supported_physical_layer_X540, | |
754 | .enable_rx_dma = &ixgbe_enable_rx_dma_generic, | |
755 | .get_mac_addr = &ixgbe_get_mac_addr_generic, | |
756 | .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, | |
b776d104 | 757 | .get_device_caps = &ixgbe_get_device_caps_generic, |
fe15e8e1 DS |
758 | .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, |
759 | .stop_adapter = &ixgbe_stop_adapter_generic, | |
760 | .get_bus_info = &ixgbe_get_bus_info_generic, | |
761 | .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, | |
762 | .read_analog_reg8 = NULL, | |
763 | .write_analog_reg8 = NULL, | |
764 | .setup_link = &ixgbe_setup_mac_link_X540, | |
765 | .check_link = &ixgbe_check_mac_link_generic, | |
766 | .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, | |
767 | .led_on = &ixgbe_led_on_generic, | |
768 | .led_off = &ixgbe_led_off_generic, | |
769 | .blink_led_start = &ixgbe_blink_led_start_generic, | |
770 | .blink_led_stop = &ixgbe_blink_led_stop_generic, | |
771 | .set_rar = &ixgbe_set_rar_generic, | |
772 | .clear_rar = &ixgbe_clear_rar_generic, | |
773 | .set_vmdq = &ixgbe_set_vmdq_generic, | |
774 | .clear_vmdq = &ixgbe_clear_vmdq_generic, | |
775 | .init_rx_addrs = &ixgbe_init_rx_addrs_generic, | |
fe15e8e1 DS |
776 | .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, |
777 | .enable_mc = &ixgbe_enable_mc_generic, | |
778 | .disable_mc = &ixgbe_disable_mc_generic, | |
779 | .clear_vfta = &ixgbe_clear_vfta_generic, | |
780 | .set_vfta = &ixgbe_set_vfta_generic, | |
781 | .fc_enable = &ixgbe_fc_enable_generic, | |
782 | .init_uta_tables = &ixgbe_init_uta_tables_generic, | |
783 | .setup_sfp = NULL, | |
3377eba7 GR |
784 | .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, |
785 | .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, | |
5e655105 DS |
786 | .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, |
787 | .release_swfw_sync = &ixgbe_release_swfw_sync_X540, | |
fe15e8e1 DS |
788 | }; |
789 | ||
790 | static struct ixgbe_eeprom_operations eeprom_ops_X540 = { | |
791 | .init_params = &ixgbe_init_eeprom_params_X540, | |
792 | .read = &ixgbe_read_eerd_X540, | |
793 | .write = &ixgbe_write_eewr_X540, | |
794 | .calc_checksum = &ixgbe_calc_eeprom_checksum_X540, | |
eb9c3e3e | 795 | .validate_checksum = &ixgbe_validate_eeprom_checksum_X540, |
fe15e8e1 DS |
796 | .update_checksum = &ixgbe_update_eeprom_checksum_X540, |
797 | }; | |
798 | ||
799 | static struct ixgbe_phy_operations phy_ops_X540 = { | |
800 | .identify = &ixgbe_identify_phy_generic, | |
801 | .identify_sfp = &ixgbe_identify_sfp_module_generic, | |
802 | .init = NULL, | |
b60c5dd3 | 803 | .reset = NULL, |
fe15e8e1 DS |
804 | .read_reg = &ixgbe_read_phy_reg_generic, |
805 | .write_reg = &ixgbe_write_phy_reg_generic, | |
806 | .setup_link = &ixgbe_setup_phy_link_generic, | |
807 | .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, | |
808 | .read_i2c_byte = &ixgbe_read_i2c_byte_generic, | |
809 | .write_i2c_byte = &ixgbe_write_i2c_byte_generic, | |
810 | .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, | |
811 | .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, | |
812 | .check_overtemp = &ixgbe_tn_check_overtemp, | |
813 | }; | |
814 | ||
815 | struct ixgbe_info ixgbe_X540_info = { | |
816 | .mac = ixgbe_mac_X540, | |
817 | .get_invariants = &ixgbe_get_invariants_X540, | |
818 | .mac_ops = &mac_ops_X540, | |
819 | .eeprom_ops = &eeprom_ops_X540, | |
820 | .phy_ops = &phy_ops_X540, | |
821 | .mbx_ops = &mbx_ops_generic, | |
822 | }; |