Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Network device driver for the MACE ethernet controller on | |
3 | * Apple Powermacs. Assumes it's under a DBDMA controller. | |
4 | * | |
5 | * Copyright (C) 1996 Paul Mackerras. | |
6 | */ | |
7 | ||
1da177e4 LT |
8 | #include <linux/module.h> |
9 | #include <linux/kernel.h> | |
10 | #include <linux/netdevice.h> | |
11 | #include <linux/etherdevice.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/string.h> | |
14 | #include <linux/timer.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/crc32.h> | |
17 | #include <linux/spinlock.h> | |
bc63eb9c | 18 | #include <linux/bitrev.h> |
1da177e4 LT |
19 | #include <asm/prom.h> |
20 | #include <asm/dbdma.h> | |
21 | #include <asm/io.h> | |
22 | #include <asm/pgtable.h> | |
23 | #include <asm/macio.h> | |
24 | ||
25 | #include "mace.h" | |
26 | ||
27 | static int port_aaui = -1; | |
28 | ||
29 | #define N_RX_RING 8 | |
30 | #define N_TX_RING 6 | |
31 | #define MAX_TX_ACTIVE 1 | |
32 | #define NCMDS_TX 1 /* dma commands per element in tx ring */ | |
33 | #define RX_BUFLEN (ETH_FRAME_LEN + 8) | |
34 | #define TX_TIMEOUT HZ /* 1 second */ | |
35 | ||
36 | /* Chip rev needs workaround on HW & multicast addr change */ | |
37 | #define BROKEN_ADDRCHG_REV 0x0941 | |
38 | ||
39 | /* Bits in transmit DMA status */ | |
40 | #define TX_DMA_ERR 0x80 | |
41 | ||
42 | struct mace_data { | |
43 | volatile struct mace __iomem *mace; | |
44 | volatile struct dbdma_regs __iomem *tx_dma; | |
45 | int tx_dma_intr; | |
46 | volatile struct dbdma_regs __iomem *rx_dma; | |
47 | int rx_dma_intr; | |
48 | volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */ | |
49 | volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */ | |
50 | struct sk_buff *rx_bufs[N_RX_RING]; | |
51 | int rx_fill; | |
52 | int rx_empty; | |
53 | struct sk_buff *tx_bufs[N_TX_RING]; | |
54 | int tx_fill; | |
55 | int tx_empty; | |
56 | unsigned char maccc; | |
57 | unsigned char tx_fullup; | |
58 | unsigned char tx_active; | |
59 | unsigned char tx_bad_runt; | |
1da177e4 LT |
60 | struct timer_list tx_timeout; |
61 | int timeout_active; | |
62 | int port_aaui; | |
63 | int chipid; | |
64 | struct macio_dev *mdev; | |
65 | spinlock_t lock; | |
66 | }; | |
67 | ||
68 | /* | |
69 | * Number of bytes of private data per MACE: allow enough for | |
70 | * the rx and tx dma commands plus a branch dma command each, | |
71 | * and another 16 bytes to allow us to align the dma command | |
72 | * buffers on a 16 byte boundary. | |
73 | */ | |
74 | #define PRIV_BYTES (sizeof(struct mace_data) \ | |
75 | + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd)) | |
76 | ||
1da177e4 LT |
77 | static int mace_open(struct net_device *dev); |
78 | static int mace_close(struct net_device *dev); | |
79 | static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); | |
1da177e4 LT |
80 | static void mace_set_multicast(struct net_device *dev); |
81 | static void mace_reset(struct net_device *dev); | |
82 | static int mace_set_address(struct net_device *dev, void *addr); | |
7d12e780 DH |
83 | static irqreturn_t mace_interrupt(int irq, void *dev_id); |
84 | static irqreturn_t mace_txdma_intr(int irq, void *dev_id); | |
85 | static irqreturn_t mace_rxdma_intr(int irq, void *dev_id); | |
1da177e4 LT |
86 | static void mace_set_timeout(struct net_device *dev); |
87 | static void mace_tx_timeout(unsigned long data); | |
88 | static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma); | |
89 | static inline void mace_clean_rings(struct mace_data *mp); | |
90 | static void __mace_set_address(struct net_device *dev, void *addr); | |
91 | ||
92 | /* | |
93 | * If we can't get a skbuff when we need it, we use this area for DMA. | |
94 | */ | |
95 | static unsigned char *dummy_buf; | |
96 | ||
5e655772 | 97 | static int __devinit mace_probe(struct macio_dev *mdev, const struct of_device_id *match) |
1da177e4 LT |
98 | { |
99 | struct device_node *mace = macio_get_of_node(mdev); | |
100 | struct net_device *dev; | |
101 | struct mace_data *mp; | |
1a2509c9 | 102 | const unsigned char *addr; |
1da177e4 | 103 | int j, rev, rc = -EBUSY; |
0795af57 | 104 | DECLARE_MAC_BUF(mac); |
1da177e4 LT |
105 | |
106 | if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) { | |
107 | printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n", | |
108 | mace->full_name); | |
109 | return -ENODEV; | |
110 | } | |
111 | ||
40cd3a45 | 112 | addr = of_get_property(mace, "mac-address", NULL); |
1da177e4 | 113 | if (addr == NULL) { |
40cd3a45 | 114 | addr = of_get_property(mace, "local-mac-address", NULL); |
1da177e4 LT |
115 | if (addr == NULL) { |
116 | printk(KERN_ERR "Can't get mac-address for MACE %s\n", | |
117 | mace->full_name); | |
118 | return -ENODEV; | |
119 | } | |
120 | } | |
121 | ||
122 | /* | |
123 | * lazy allocate the driver-wide dummy buffer. (Note that we | |
124 | * never have more than one MACE in the system anyway) | |
125 | */ | |
126 | if (dummy_buf == NULL) { | |
127 | dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL); | |
128 | if (dummy_buf == NULL) { | |
129 | printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n"); | |
130 | return -ENOMEM; | |
131 | } | |
132 | } | |
133 | ||
134 | if (macio_request_resources(mdev, "mace")) { | |
135 | printk(KERN_ERR "MACE: can't request IO resources !\n"); | |
136 | return -EBUSY; | |
137 | } | |
138 | ||
139 | dev = alloc_etherdev(PRIV_BYTES); | |
140 | if (!dev) { | |
141 | printk(KERN_ERR "MACE: can't allocate ethernet device !\n"); | |
142 | rc = -ENOMEM; | |
143 | goto err_release; | |
144 | } | |
1da177e4 LT |
145 | SET_NETDEV_DEV(dev, &mdev->ofdev.dev); |
146 | ||
147 | mp = dev->priv; | |
148 | mp->mdev = mdev; | |
149 | macio_set_drvdata(mdev, dev); | |
150 | ||
151 | dev->base_addr = macio_resource_start(mdev, 0); | |
152 | mp->mace = ioremap(dev->base_addr, 0x1000); | |
153 | if (mp->mace == NULL) { | |
154 | printk(KERN_ERR "MACE: can't map IO resources !\n"); | |
155 | rc = -ENOMEM; | |
156 | goto err_free; | |
157 | } | |
158 | dev->irq = macio_irq(mdev, 0); | |
159 | ||
160 | rev = addr[0] == 0 && addr[1] == 0xA0; | |
161 | for (j = 0; j < 6; ++j) { | |
bc63eb9c | 162 | dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j]; |
1da177e4 LT |
163 | } |
164 | mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) | | |
165 | in_8(&mp->mace->chipid_lo); | |
6aa20a22 | 166 | |
1da177e4 LT |
167 | |
168 | mp = (struct mace_data *) dev->priv; | |
169 | mp->maccc = ENXMT | ENRCV; | |
170 | ||
171 | mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000); | |
172 | if (mp->tx_dma == NULL) { | |
173 | printk(KERN_ERR "MACE: can't map TX DMA resources !\n"); | |
174 | rc = -ENOMEM; | |
175 | goto err_unmap_io; | |
176 | } | |
177 | mp->tx_dma_intr = macio_irq(mdev, 1); | |
178 | ||
179 | mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000); | |
180 | if (mp->rx_dma == NULL) { | |
181 | printk(KERN_ERR "MACE: can't map RX DMA resources !\n"); | |
182 | rc = -ENOMEM; | |
183 | goto err_unmap_tx_dma; | |
184 | } | |
185 | mp->rx_dma_intr = macio_irq(mdev, 2); | |
186 | ||
187 | mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1); | |
188 | mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1; | |
189 | ||
1da177e4 LT |
190 | memset((char *) mp->tx_cmds, 0, |
191 | (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd)); | |
192 | init_timer(&mp->tx_timeout); | |
193 | spin_lock_init(&mp->lock); | |
194 | mp->timeout_active = 0; | |
195 | ||
196 | if (port_aaui >= 0) | |
197 | mp->port_aaui = port_aaui; | |
198 | else { | |
199 | /* Apple Network Server uses the AAUI port */ | |
200 | if (machine_is_compatible("AAPL,ShinerESB")) | |
201 | mp->port_aaui = 1; | |
202 | else { | |
203 | #ifdef CONFIG_MACE_AAUI_PORT | |
204 | mp->port_aaui = 1; | |
205 | #else | |
206 | mp->port_aaui = 0; | |
6aa20a22 | 207 | #endif |
1da177e4 LT |
208 | } |
209 | } | |
210 | ||
211 | dev->open = mace_open; | |
212 | dev->stop = mace_close; | |
213 | dev->hard_start_xmit = mace_xmit_start; | |
1da177e4 LT |
214 | dev->set_multicast_list = mace_set_multicast; |
215 | dev->set_mac_address = mace_set_address; | |
216 | ||
217 | /* | |
218 | * Most of what is below could be moved to mace_open() | |
219 | */ | |
220 | mace_reset(dev); | |
221 | ||
222 | rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev); | |
223 | if (rc) { | |
224 | printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq); | |
225 | goto err_unmap_rx_dma; | |
226 | } | |
227 | rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev); | |
228 | if (rc) { | |
0ebfff14 | 229 | printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr); |
1da177e4 LT |
230 | goto err_free_irq; |
231 | } | |
232 | rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev); | |
233 | if (rc) { | |
0ebfff14 | 234 | printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr); |
1da177e4 LT |
235 | goto err_free_tx_irq; |
236 | } | |
237 | ||
238 | rc = register_netdev(dev); | |
239 | if (rc) { | |
240 | printk(KERN_ERR "MACE: Cannot register net device, aborting.\n"); | |
241 | goto err_free_rx_irq; | |
242 | } | |
243 | ||
0795af57 JP |
244 | printk(KERN_INFO "%s: MACE at %s, chip revision %d.%d\n", |
245 | dev->name, print_mac(mac, dev->dev_addr), | |
246 | mp->chipid >> 8, mp->chipid & 0xff); | |
1da177e4 LT |
247 | |
248 | return 0; | |
6aa20a22 | 249 | |
1da177e4 LT |
250 | err_free_rx_irq: |
251 | free_irq(macio_irq(mdev, 2), dev); | |
252 | err_free_tx_irq: | |
253 | free_irq(macio_irq(mdev, 1), dev); | |
254 | err_free_irq: | |
255 | free_irq(macio_irq(mdev, 0), dev); | |
256 | err_unmap_rx_dma: | |
257 | iounmap(mp->rx_dma); | |
258 | err_unmap_tx_dma: | |
259 | iounmap(mp->tx_dma); | |
260 | err_unmap_io: | |
261 | iounmap(mp->mace); | |
262 | err_free: | |
263 | free_netdev(dev); | |
264 | err_release: | |
265 | macio_release_resources(mdev); | |
266 | ||
267 | return rc; | |
268 | } | |
269 | ||
270 | static int __devexit mace_remove(struct macio_dev *mdev) | |
271 | { | |
272 | struct net_device *dev = macio_get_drvdata(mdev); | |
273 | struct mace_data *mp; | |
274 | ||
275 | BUG_ON(dev == NULL); | |
276 | ||
277 | macio_set_drvdata(mdev, NULL); | |
278 | ||
279 | mp = dev->priv; | |
280 | ||
281 | unregister_netdev(dev); | |
282 | ||
283 | free_irq(dev->irq, dev); | |
284 | free_irq(mp->tx_dma_intr, dev); | |
285 | free_irq(mp->rx_dma_intr, dev); | |
286 | ||
287 | iounmap(mp->rx_dma); | |
288 | iounmap(mp->tx_dma); | |
289 | iounmap(mp->mace); | |
290 | ||
291 | free_netdev(dev); | |
292 | ||
293 | macio_release_resources(mdev); | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | static void dbdma_reset(volatile struct dbdma_regs __iomem *dma) | |
299 | { | |
300 | int i; | |
301 | ||
302 | out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16); | |
303 | ||
304 | /* | |
305 | * Yes this looks peculiar, but apparently it needs to be this | |
306 | * way on some machines. | |
307 | */ | |
308 | for (i = 200; i > 0; --i) | |
309 | if (ld_le32(&dma->control) & RUN) | |
310 | udelay(1); | |
311 | } | |
312 | ||
313 | static void mace_reset(struct net_device *dev) | |
314 | { | |
315 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
316 | volatile struct mace __iomem *mb = mp->mace; | |
317 | int i; | |
318 | ||
319 | /* soft-reset the chip */ | |
320 | i = 200; | |
321 | while (--i) { | |
322 | out_8(&mb->biucc, SWRST); | |
323 | if (in_8(&mb->biucc) & SWRST) { | |
324 | udelay(10); | |
325 | continue; | |
326 | } | |
327 | break; | |
328 | } | |
329 | if (!i) { | |
330 | printk(KERN_ERR "mace: cannot reset chip!\n"); | |
331 | return; | |
332 | } | |
333 | ||
334 | out_8(&mb->imr, 0xff); /* disable all intrs for now */ | |
335 | i = in_8(&mb->ir); | |
336 | out_8(&mb->maccc, 0); /* turn off tx, rx */ | |
337 | ||
338 | out_8(&mb->biucc, XMTSP_64); | |
339 | out_8(&mb->utr, RTRD); | |
340 | out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST); | |
341 | out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */ | |
342 | out_8(&mb->rcvfc, 0); | |
343 | ||
344 | /* load up the hardware address */ | |
345 | __mace_set_address(dev, dev->dev_addr); | |
346 | ||
347 | /* clear the multicast filter */ | |
348 | if (mp->chipid == BROKEN_ADDRCHG_REV) | |
349 | out_8(&mb->iac, LOGADDR); | |
350 | else { | |
351 | out_8(&mb->iac, ADDRCHG | LOGADDR); | |
352 | while ((in_8(&mb->iac) & ADDRCHG) != 0) | |
353 | ; | |
354 | } | |
355 | for (i = 0; i < 8; ++i) | |
356 | out_8(&mb->ladrf, 0); | |
357 | ||
358 | /* done changing address */ | |
359 | if (mp->chipid != BROKEN_ADDRCHG_REV) | |
360 | out_8(&mb->iac, 0); | |
361 | ||
362 | if (mp->port_aaui) | |
363 | out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO); | |
364 | else | |
365 | out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO); | |
366 | } | |
367 | ||
368 | static void __mace_set_address(struct net_device *dev, void *addr) | |
369 | { | |
370 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
371 | volatile struct mace __iomem *mb = mp->mace; | |
372 | unsigned char *p = addr; | |
373 | int i; | |
374 | ||
375 | /* load up the hardware address */ | |
376 | if (mp->chipid == BROKEN_ADDRCHG_REV) | |
377 | out_8(&mb->iac, PHYADDR); | |
378 | else { | |
379 | out_8(&mb->iac, ADDRCHG | PHYADDR); | |
380 | while ((in_8(&mb->iac) & ADDRCHG) != 0) | |
381 | ; | |
382 | } | |
383 | for (i = 0; i < 6; ++i) | |
384 | out_8(&mb->padr, dev->dev_addr[i] = p[i]); | |
385 | if (mp->chipid != BROKEN_ADDRCHG_REV) | |
386 | out_8(&mb->iac, 0); | |
387 | } | |
388 | ||
389 | static int mace_set_address(struct net_device *dev, void *addr) | |
390 | { | |
391 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
392 | volatile struct mace __iomem *mb = mp->mace; | |
393 | unsigned long flags; | |
394 | ||
395 | spin_lock_irqsave(&mp->lock, flags); | |
396 | ||
397 | __mace_set_address(dev, addr); | |
398 | ||
399 | /* note: setting ADDRCHG clears ENRCV */ | |
400 | out_8(&mb->maccc, mp->maccc); | |
401 | ||
402 | spin_unlock_irqrestore(&mp->lock, flags); | |
403 | return 0; | |
404 | } | |
405 | ||
406 | static inline void mace_clean_rings(struct mace_data *mp) | |
407 | { | |
408 | int i; | |
409 | ||
410 | /* free some skb's */ | |
411 | for (i = 0; i < N_RX_RING; ++i) { | |
412 | if (mp->rx_bufs[i] != 0) { | |
413 | dev_kfree_skb(mp->rx_bufs[i]); | |
414 | mp->rx_bufs[i] = NULL; | |
415 | } | |
416 | } | |
417 | for (i = mp->tx_empty; i != mp->tx_fill; ) { | |
418 | dev_kfree_skb(mp->tx_bufs[i]); | |
419 | if (++i >= N_TX_RING) | |
420 | i = 0; | |
421 | } | |
422 | } | |
423 | ||
424 | static int mace_open(struct net_device *dev) | |
425 | { | |
426 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
427 | volatile struct mace __iomem *mb = mp->mace; | |
428 | volatile struct dbdma_regs __iomem *rd = mp->rx_dma; | |
429 | volatile struct dbdma_regs __iomem *td = mp->tx_dma; | |
430 | volatile struct dbdma_cmd *cp; | |
431 | int i; | |
432 | struct sk_buff *skb; | |
433 | unsigned char *data; | |
434 | ||
435 | /* reset the chip */ | |
436 | mace_reset(dev); | |
437 | ||
438 | /* initialize list of sk_buffs for receiving and set up recv dma */ | |
439 | mace_clean_rings(mp); | |
440 | memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd)); | |
441 | cp = mp->rx_cmds; | |
442 | for (i = 0; i < N_RX_RING - 1; ++i) { | |
443 | skb = dev_alloc_skb(RX_BUFLEN + 2); | |
444 | if (skb == 0) { | |
445 | data = dummy_buf; | |
446 | } else { | |
447 | skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */ | |
448 | data = skb->data; | |
449 | } | |
450 | mp->rx_bufs[i] = skb; | |
451 | st_le16(&cp->req_count, RX_BUFLEN); | |
452 | st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS); | |
453 | st_le32(&cp->phy_addr, virt_to_bus(data)); | |
454 | cp->xfer_status = 0; | |
455 | ++cp; | |
456 | } | |
457 | mp->rx_bufs[i] = NULL; | |
458 | st_le16(&cp->command, DBDMA_STOP); | |
459 | mp->rx_fill = i; | |
460 | mp->rx_empty = 0; | |
461 | ||
462 | /* Put a branch back to the beginning of the receive command list */ | |
463 | ++cp; | |
464 | st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS); | |
465 | st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds)); | |
466 | ||
467 | /* start rx dma */ | |
468 | out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ | |
469 | out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds)); | |
470 | out_le32(&rd->control, (RUN << 16) | RUN); | |
471 | ||
472 | /* put a branch at the end of the tx command list */ | |
473 | cp = mp->tx_cmds + NCMDS_TX * N_TX_RING; | |
474 | st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS); | |
475 | st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds)); | |
476 | ||
477 | /* reset tx dma */ | |
478 | out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); | |
479 | out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds)); | |
480 | mp->tx_fill = 0; | |
481 | mp->tx_empty = 0; | |
482 | mp->tx_fullup = 0; | |
483 | mp->tx_active = 0; | |
484 | mp->tx_bad_runt = 0; | |
485 | ||
486 | /* turn it on! */ | |
487 | out_8(&mb->maccc, mp->maccc); | |
488 | /* enable all interrupts except receive interrupts */ | |
489 | out_8(&mb->imr, RCVINT); | |
490 | ||
491 | return 0; | |
492 | } | |
493 | ||
494 | static int mace_close(struct net_device *dev) | |
495 | { | |
496 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
497 | volatile struct mace __iomem *mb = mp->mace; | |
498 | volatile struct dbdma_regs __iomem *rd = mp->rx_dma; | |
499 | volatile struct dbdma_regs __iomem *td = mp->tx_dma; | |
500 | ||
501 | /* disable rx and tx */ | |
502 | out_8(&mb->maccc, 0); | |
503 | out_8(&mb->imr, 0xff); /* disable all intrs */ | |
504 | ||
505 | /* disable rx and tx dma */ | |
506 | st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ | |
507 | st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ | |
508 | ||
509 | mace_clean_rings(mp); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
514 | static inline void mace_set_timeout(struct net_device *dev) | |
515 | { | |
516 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
517 | ||
518 | if (mp->timeout_active) | |
519 | del_timer(&mp->tx_timeout); | |
520 | mp->tx_timeout.expires = jiffies + TX_TIMEOUT; | |
521 | mp->tx_timeout.function = mace_tx_timeout; | |
522 | mp->tx_timeout.data = (unsigned long) dev; | |
523 | add_timer(&mp->tx_timeout); | |
524 | mp->timeout_active = 1; | |
525 | } | |
526 | ||
527 | static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) | |
528 | { | |
529 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
530 | volatile struct dbdma_regs __iomem *td = mp->tx_dma; | |
531 | volatile struct dbdma_cmd *cp, *np; | |
532 | unsigned long flags; | |
533 | int fill, next, len; | |
534 | ||
535 | /* see if there's a free slot in the tx ring */ | |
536 | spin_lock_irqsave(&mp->lock, flags); | |
537 | fill = mp->tx_fill; | |
538 | next = fill + 1; | |
539 | if (next >= N_TX_RING) | |
540 | next = 0; | |
541 | if (next == mp->tx_empty) { | |
542 | netif_stop_queue(dev); | |
543 | mp->tx_fullup = 1; | |
544 | spin_unlock_irqrestore(&mp->lock, flags); | |
545 | return 1; /* can't take it at the moment */ | |
546 | } | |
547 | spin_unlock_irqrestore(&mp->lock, flags); | |
548 | ||
549 | /* partially fill in the dma command block */ | |
550 | len = skb->len; | |
551 | if (len > ETH_FRAME_LEN) { | |
552 | printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len); | |
553 | len = ETH_FRAME_LEN; | |
554 | } | |
555 | mp->tx_bufs[fill] = skb; | |
556 | cp = mp->tx_cmds + NCMDS_TX * fill; | |
557 | st_le16(&cp->req_count, len); | |
558 | st_le32(&cp->phy_addr, virt_to_bus(skb->data)); | |
559 | ||
560 | np = mp->tx_cmds + NCMDS_TX * next; | |
561 | out_le16(&np->command, DBDMA_STOP); | |
562 | ||
563 | /* poke the tx dma channel */ | |
564 | spin_lock_irqsave(&mp->lock, flags); | |
565 | mp->tx_fill = next; | |
566 | if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) { | |
567 | out_le16(&cp->xfer_status, 0); | |
568 | out_le16(&cp->command, OUTPUT_LAST); | |
569 | out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); | |
570 | ++mp->tx_active; | |
571 | mace_set_timeout(dev); | |
572 | } | |
573 | if (++next >= N_TX_RING) | |
574 | next = 0; | |
575 | if (next == mp->tx_empty) | |
576 | netif_stop_queue(dev); | |
577 | spin_unlock_irqrestore(&mp->lock, flags); | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
1da177e4 LT |
582 | static void mace_set_multicast(struct net_device *dev) |
583 | { | |
584 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
585 | volatile struct mace __iomem *mb = mp->mace; | |
586 | int i, j; | |
587 | u32 crc; | |
588 | unsigned long flags; | |
589 | ||
590 | spin_lock_irqsave(&mp->lock, flags); | |
591 | mp->maccc &= ~PROM; | |
592 | if (dev->flags & IFF_PROMISC) { | |
593 | mp->maccc |= PROM; | |
594 | } else { | |
595 | unsigned char multicast_filter[8]; | |
596 | struct dev_mc_list *dmi = dev->mc_list; | |
597 | ||
598 | if (dev->flags & IFF_ALLMULTI) { | |
599 | for (i = 0; i < 8; i++) | |
600 | multicast_filter[i] = 0xff; | |
601 | } else { | |
602 | for (i = 0; i < 8; i++) | |
603 | multicast_filter[i] = 0; | |
604 | for (i = 0; i < dev->mc_count; i++) { | |
605 | crc = ether_crc_le(6, dmi->dmi_addr); | |
606 | j = crc >> 26; /* bit number in multicast_filter */ | |
607 | multicast_filter[j >> 3] |= 1 << (j & 7); | |
608 | dmi = dmi->next; | |
609 | } | |
610 | } | |
611 | #if 0 | |
612 | printk("Multicast filter :"); | |
613 | for (i = 0; i < 8; i++) | |
614 | printk("%02x ", multicast_filter[i]); | |
615 | printk("\n"); | |
616 | #endif | |
617 | ||
618 | if (mp->chipid == BROKEN_ADDRCHG_REV) | |
619 | out_8(&mb->iac, LOGADDR); | |
620 | else { | |
621 | out_8(&mb->iac, ADDRCHG | LOGADDR); | |
622 | while ((in_8(&mb->iac) & ADDRCHG) != 0) | |
623 | ; | |
624 | } | |
625 | for (i = 0; i < 8; ++i) | |
626 | out_8(&mb->ladrf, multicast_filter[i]); | |
627 | if (mp->chipid != BROKEN_ADDRCHG_REV) | |
628 | out_8(&mb->iac, 0); | |
629 | } | |
630 | /* reset maccc */ | |
631 | out_8(&mb->maccc, mp->maccc); | |
632 | spin_unlock_irqrestore(&mp->lock, flags); | |
633 | } | |
634 | ||
09f75cd7 | 635 | static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev) |
1da177e4 LT |
636 | { |
637 | volatile struct mace __iomem *mb = mp->mace; | |
638 | static int mace_babbles, mace_jabbers; | |
639 | ||
640 | if (intr & MPCO) | |
09f75cd7 JG |
641 | dev->stats.rx_missed_errors += 256; |
642 | dev->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */ | |
1da177e4 | 643 | if (intr & RNTPCO) |
09f75cd7 JG |
644 | dev->stats.rx_length_errors += 256; |
645 | dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */ | |
1da177e4 | 646 | if (intr & CERR) |
09f75cd7 | 647 | ++dev->stats.tx_heartbeat_errors; |
1da177e4 LT |
648 | if (intr & BABBLE) |
649 | if (mace_babbles++ < 4) | |
650 | printk(KERN_DEBUG "mace: babbling transmitter\n"); | |
651 | if (intr & JABBER) | |
652 | if (mace_jabbers++ < 4) | |
653 | printk(KERN_DEBUG "mace: jabbering transceiver\n"); | |
654 | } | |
655 | ||
7d12e780 | 656 | static irqreturn_t mace_interrupt(int irq, void *dev_id) |
1da177e4 LT |
657 | { |
658 | struct net_device *dev = (struct net_device *) dev_id; | |
659 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
660 | volatile struct mace __iomem *mb = mp->mace; | |
661 | volatile struct dbdma_regs __iomem *td = mp->tx_dma; | |
662 | volatile struct dbdma_cmd *cp; | |
663 | int intr, fs, i, stat, x; | |
664 | int xcount, dstat; | |
665 | unsigned long flags; | |
666 | /* static int mace_last_fs, mace_last_xcount; */ | |
667 | ||
668 | spin_lock_irqsave(&mp->lock, flags); | |
669 | intr = in_8(&mb->ir); /* read interrupt register */ | |
670 | in_8(&mb->xmtrc); /* get retries */ | |
09f75cd7 | 671 | mace_handle_misc_intrs(mp, intr, dev); |
1da177e4 LT |
672 | |
673 | i = mp->tx_empty; | |
674 | while (in_8(&mb->pr) & XMTSV) { | |
675 | del_timer(&mp->tx_timeout); | |
676 | mp->timeout_active = 0; | |
677 | /* | |
678 | * Clear any interrupt indication associated with this status | |
679 | * word. This appears to unlatch any error indication from | |
680 | * the DMA controller. | |
681 | */ | |
682 | intr = in_8(&mb->ir); | |
683 | if (intr != 0) | |
09f75cd7 | 684 | mace_handle_misc_intrs(mp, intr, dev); |
1da177e4 LT |
685 | if (mp->tx_bad_runt) { |
686 | fs = in_8(&mb->xmtfs); | |
687 | mp->tx_bad_runt = 0; | |
688 | out_8(&mb->xmtfc, AUTO_PAD_XMIT); | |
689 | continue; | |
690 | } | |
691 | dstat = ld_le32(&td->status); | |
692 | /* stop DMA controller */ | |
693 | out_le32(&td->control, RUN << 16); | |
694 | /* | |
695 | * xcount is the number of complete frames which have been | |
696 | * written to the fifo but for which status has not been read. | |
697 | */ | |
698 | xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; | |
699 | if (xcount == 0 || (dstat & DEAD)) { | |
700 | /* | |
701 | * If a packet was aborted before the DMA controller has | |
702 | * finished transferring it, it seems that there are 2 bytes | |
703 | * which are stuck in some buffer somewhere. These will get | |
704 | * transmitted as soon as we read the frame status (which | |
705 | * reenables the transmit data transfer request). Turning | |
706 | * off the DMA controller and/or resetting the MACE doesn't | |
707 | * help. So we disable auto-padding and FCS transmission | |
708 | * so the two bytes will only be a runt packet which should | |
709 | * be ignored by other stations. | |
710 | */ | |
711 | out_8(&mb->xmtfc, DXMTFCS); | |
712 | } | |
713 | fs = in_8(&mb->xmtfs); | |
714 | if ((fs & XMTSV) == 0) { | |
715 | printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n", | |
716 | fs, xcount, dstat); | |
717 | mace_reset(dev); | |
718 | /* | |
719 | * XXX mace likes to hang the machine after a xmtfs error. | |
720 | * This is hard to reproduce, reseting *may* help | |
721 | */ | |
722 | } | |
723 | cp = mp->tx_cmds + NCMDS_TX * i; | |
724 | stat = ld_le16(&cp->xfer_status); | |
725 | if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) { | |
726 | /* | |
727 | * Check whether there were in fact 2 bytes written to | |
728 | * the transmit FIFO. | |
729 | */ | |
730 | udelay(1); | |
731 | x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; | |
732 | if (x != 0) { | |
733 | /* there were two bytes with an end-of-packet indication */ | |
734 | mp->tx_bad_runt = 1; | |
735 | mace_set_timeout(dev); | |
736 | } else { | |
737 | /* | |
738 | * Either there weren't the two bytes buffered up, or they | |
739 | * didn't have an end-of-packet indication. | |
740 | * We flush the transmit FIFO just in case (by setting the | |
741 | * XMTFWU bit with the transmitter disabled). | |
742 | */ | |
743 | out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT); | |
744 | out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU); | |
745 | udelay(1); | |
746 | out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT); | |
747 | out_8(&mb->xmtfc, AUTO_PAD_XMIT); | |
748 | } | |
749 | } | |
750 | /* dma should have finished */ | |
751 | if (i == mp->tx_fill) { | |
752 | printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n", | |
753 | fs, xcount, dstat); | |
754 | continue; | |
755 | } | |
756 | /* Update stats */ | |
757 | if (fs & (UFLO|LCOL|LCAR|RTRY)) { | |
09f75cd7 | 758 | ++dev->stats.tx_errors; |
1da177e4 | 759 | if (fs & LCAR) |
09f75cd7 | 760 | ++dev->stats.tx_carrier_errors; |
1da177e4 | 761 | if (fs & (UFLO|LCOL|RTRY)) |
09f75cd7 | 762 | ++dev->stats.tx_aborted_errors; |
1da177e4 | 763 | } else { |
09f75cd7 JG |
764 | dev->stats.tx_bytes += mp->tx_bufs[i]->len; |
765 | ++dev->stats.tx_packets; | |
1da177e4 LT |
766 | } |
767 | dev_kfree_skb_irq(mp->tx_bufs[i]); | |
768 | --mp->tx_active; | |
769 | if (++i >= N_TX_RING) | |
770 | i = 0; | |
771 | #if 0 | |
772 | mace_last_fs = fs; | |
773 | mace_last_xcount = xcount; | |
774 | #endif | |
775 | } | |
776 | ||
777 | if (i != mp->tx_empty) { | |
778 | mp->tx_fullup = 0; | |
779 | netif_wake_queue(dev); | |
780 | } | |
781 | mp->tx_empty = i; | |
782 | i += mp->tx_active; | |
783 | if (i >= N_TX_RING) | |
784 | i -= N_TX_RING; | |
785 | if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) { | |
786 | do { | |
787 | /* set up the next one */ | |
788 | cp = mp->tx_cmds + NCMDS_TX * i; | |
789 | out_le16(&cp->xfer_status, 0); | |
790 | out_le16(&cp->command, OUTPUT_LAST); | |
791 | ++mp->tx_active; | |
792 | if (++i >= N_TX_RING) | |
793 | i = 0; | |
794 | } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE); | |
795 | out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); | |
796 | mace_set_timeout(dev); | |
797 | } | |
798 | spin_unlock_irqrestore(&mp->lock, flags); | |
799 | return IRQ_HANDLED; | |
800 | } | |
801 | ||
802 | static void mace_tx_timeout(unsigned long data) | |
803 | { | |
804 | struct net_device *dev = (struct net_device *) data; | |
805 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
806 | volatile struct mace __iomem *mb = mp->mace; | |
807 | volatile struct dbdma_regs __iomem *td = mp->tx_dma; | |
808 | volatile struct dbdma_regs __iomem *rd = mp->rx_dma; | |
809 | volatile struct dbdma_cmd *cp; | |
810 | unsigned long flags; | |
811 | int i; | |
812 | ||
813 | spin_lock_irqsave(&mp->lock, flags); | |
814 | mp->timeout_active = 0; | |
815 | if (mp->tx_active == 0 && !mp->tx_bad_runt) | |
816 | goto out; | |
817 | ||
818 | /* update various counters */ | |
09f75cd7 | 819 | mace_handle_misc_intrs(mp, in_8(&mb->ir), dev); |
1da177e4 LT |
820 | |
821 | cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty; | |
822 | ||
823 | /* turn off both tx and rx and reset the chip */ | |
824 | out_8(&mb->maccc, 0); | |
825 | printk(KERN_ERR "mace: transmit timeout - resetting\n"); | |
826 | dbdma_reset(td); | |
827 | mace_reset(dev); | |
828 | ||
829 | /* restart rx dma */ | |
830 | cp = bus_to_virt(ld_le32(&rd->cmdptr)); | |
831 | dbdma_reset(rd); | |
832 | out_le16(&cp->xfer_status, 0); | |
833 | out_le32(&rd->cmdptr, virt_to_bus(cp)); | |
834 | out_le32(&rd->control, (RUN << 16) | RUN); | |
835 | ||
836 | /* fix up the transmit side */ | |
837 | i = mp->tx_empty; | |
838 | mp->tx_active = 0; | |
09f75cd7 | 839 | ++dev->stats.tx_errors; |
1da177e4 LT |
840 | if (mp->tx_bad_runt) { |
841 | mp->tx_bad_runt = 0; | |
842 | } else if (i != mp->tx_fill) { | |
843 | dev_kfree_skb(mp->tx_bufs[i]); | |
844 | if (++i >= N_TX_RING) | |
845 | i = 0; | |
846 | mp->tx_empty = i; | |
847 | } | |
848 | mp->tx_fullup = 0; | |
849 | netif_wake_queue(dev); | |
850 | if (i != mp->tx_fill) { | |
851 | cp = mp->tx_cmds + NCMDS_TX * i; | |
852 | out_le16(&cp->xfer_status, 0); | |
853 | out_le16(&cp->command, OUTPUT_LAST); | |
854 | out_le32(&td->cmdptr, virt_to_bus(cp)); | |
855 | out_le32(&td->control, (RUN << 16) | RUN); | |
856 | ++mp->tx_active; | |
857 | mace_set_timeout(dev); | |
858 | } | |
859 | ||
860 | /* turn it back on */ | |
861 | out_8(&mb->imr, RCVINT); | |
862 | out_8(&mb->maccc, mp->maccc); | |
863 | ||
864 | out: | |
865 | spin_unlock_irqrestore(&mp->lock, flags); | |
866 | } | |
867 | ||
7d12e780 | 868 | static irqreturn_t mace_txdma_intr(int irq, void *dev_id) |
1da177e4 LT |
869 | { |
870 | return IRQ_HANDLED; | |
871 | } | |
872 | ||
7d12e780 | 873 | static irqreturn_t mace_rxdma_intr(int irq, void *dev_id) |
1da177e4 LT |
874 | { |
875 | struct net_device *dev = (struct net_device *) dev_id; | |
876 | struct mace_data *mp = (struct mace_data *) dev->priv; | |
877 | volatile struct dbdma_regs __iomem *rd = mp->rx_dma; | |
878 | volatile struct dbdma_cmd *cp, *np; | |
879 | int i, nb, stat, next; | |
880 | struct sk_buff *skb; | |
881 | unsigned frame_status; | |
882 | static int mace_lost_status; | |
883 | unsigned char *data; | |
884 | unsigned long flags; | |
885 | ||
886 | spin_lock_irqsave(&mp->lock, flags); | |
887 | for (i = mp->rx_empty; i != mp->rx_fill; ) { | |
888 | cp = mp->rx_cmds + i; | |
889 | stat = ld_le16(&cp->xfer_status); | |
890 | if ((stat & ACTIVE) == 0) { | |
891 | next = i + 1; | |
892 | if (next >= N_RX_RING) | |
893 | next = 0; | |
894 | np = mp->rx_cmds + next; | |
895 | if (next != mp->rx_fill | |
896 | && (ld_le16(&np->xfer_status) & ACTIVE) != 0) { | |
897 | printk(KERN_DEBUG "mace: lost a status word\n"); | |
898 | ++mace_lost_status; | |
899 | } else | |
900 | break; | |
901 | } | |
902 | nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count); | |
903 | out_le16(&cp->command, DBDMA_STOP); | |
904 | /* got a packet, have a look at it */ | |
905 | skb = mp->rx_bufs[i]; | |
906 | if (skb == 0) { | |
09f75cd7 | 907 | ++dev->stats.rx_dropped; |
1da177e4 LT |
908 | } else if (nb > 8) { |
909 | data = skb->data; | |
910 | frame_status = (data[nb-3] << 8) + data[nb-4]; | |
911 | if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) { | |
09f75cd7 | 912 | ++dev->stats.rx_errors; |
1da177e4 | 913 | if (frame_status & RS_OFLO) |
09f75cd7 | 914 | ++dev->stats.rx_over_errors; |
1da177e4 | 915 | if (frame_status & RS_FRAMERR) |
09f75cd7 | 916 | ++dev->stats.rx_frame_errors; |
1da177e4 | 917 | if (frame_status & RS_FCSERR) |
09f75cd7 | 918 | ++dev->stats.rx_crc_errors; |
1da177e4 LT |
919 | } else { |
920 | /* Mace feature AUTO_STRIP_RCV is on by default, dropping the | |
921 | * FCS on frames with 802.3 headers. This means that Ethernet | |
922 | * frames have 8 extra octets at the end, while 802.3 frames | |
923 | * have only 4. We need to correctly account for this. */ | |
924 | if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */ | |
925 | nb -= 4; | |
926 | else /* Ethernet header; mace includes FCS */ | |
927 | nb -= 8; | |
928 | skb_put(skb, nb); | |
1da177e4 | 929 | skb->protocol = eth_type_trans(skb, dev); |
09f75cd7 | 930 | dev->stats.rx_bytes += skb->len; |
1da177e4 LT |
931 | netif_rx(skb); |
932 | dev->last_rx = jiffies; | |
933 | mp->rx_bufs[i] = NULL; | |
09f75cd7 | 934 | ++dev->stats.rx_packets; |
1da177e4 LT |
935 | } |
936 | } else { | |
09f75cd7 JG |
937 | ++dev->stats.rx_errors; |
938 | ++dev->stats.rx_length_errors; | |
1da177e4 LT |
939 | } |
940 | ||
941 | /* advance to next */ | |
942 | if (++i >= N_RX_RING) | |
943 | i = 0; | |
944 | } | |
945 | mp->rx_empty = i; | |
946 | ||
947 | i = mp->rx_fill; | |
948 | for (;;) { | |
949 | next = i + 1; | |
950 | if (next >= N_RX_RING) | |
951 | next = 0; | |
952 | if (next == mp->rx_empty) | |
953 | break; | |
954 | cp = mp->rx_cmds + i; | |
955 | skb = mp->rx_bufs[i]; | |
956 | if (skb == 0) { | |
957 | skb = dev_alloc_skb(RX_BUFLEN + 2); | |
958 | if (skb != 0) { | |
959 | skb_reserve(skb, 2); | |
960 | mp->rx_bufs[i] = skb; | |
961 | } | |
962 | } | |
963 | st_le16(&cp->req_count, RX_BUFLEN); | |
964 | data = skb? skb->data: dummy_buf; | |
965 | st_le32(&cp->phy_addr, virt_to_bus(data)); | |
966 | out_le16(&cp->xfer_status, 0); | |
967 | out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS); | |
968 | #if 0 | |
969 | if ((ld_le32(&rd->status) & ACTIVE) != 0) { | |
970 | out_le32(&rd->control, (PAUSE << 16) | PAUSE); | |
971 | while ((in_le32(&rd->status) & ACTIVE) != 0) | |
972 | ; | |
973 | } | |
974 | #endif | |
975 | i = next; | |
976 | } | |
977 | if (i != mp->rx_fill) { | |
978 | out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE)); | |
979 | mp->rx_fill = i; | |
980 | } | |
981 | spin_unlock_irqrestore(&mp->lock, flags); | |
982 | return IRQ_HANDLED; | |
983 | } | |
984 | ||
6aa20a22 | 985 | static struct of_device_id mace_match[] = |
1da177e4 LT |
986 | { |
987 | { | |
988 | .name = "mace", | |
1da177e4 LT |
989 | }, |
990 | {}, | |
991 | }; | |
8c9795ba | 992 | MODULE_DEVICE_TABLE (of, mace_match); |
1da177e4 | 993 | |
6aa20a22 | 994 | static struct macio_driver mace_driver = |
1da177e4 LT |
995 | { |
996 | .name = "mace", | |
997 | .match_table = mace_match, | |
998 | .probe = mace_probe, | |
999 | .remove = mace_remove, | |
1000 | }; | |
1001 | ||
1002 | ||
1003 | static int __init mace_init(void) | |
1004 | { | |
1005 | return macio_register_driver(&mace_driver); | |
1006 | } | |
1007 | ||
1008 | static void __exit mace_cleanup(void) | |
1009 | { | |
1010 | macio_unregister_driver(&mace_driver); | |
1011 | ||
b4558ea9 JJ |
1012 | kfree(dummy_buf); |
1013 | dummy_buf = NULL; | |
1da177e4 LT |
1014 | } |
1015 | ||
1016 | MODULE_AUTHOR("Paul Mackerras"); | |
1017 | MODULE_DESCRIPTION("PowerMac MACE driver."); | |
8d3b33f6 | 1018 | module_param(port_aaui, int, 0); |
1da177e4 LT |
1019 | MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)"); |
1020 | MODULE_LICENSE("GPL"); | |
1021 | ||
1022 | module_init(mace_init); | |
1023 | module_exit(mace_cleanup); |