[deliverable/linux.git] / drivers / net / mlx4 / mlx4_en.h

/*
 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

#ifndef _MLX4_EN_H_
#define _MLX4_EN_H_

#include <linux/compiler.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>

#include <linux/mlx4/device.h>
#include <linux/mlx4/qp.h>
#include <linux/mlx4/cq.h>
#include <linux/mlx4/srq.h>
#include <linux/mlx4/doorbell.h>
#include <linux/mlx4/cmd.h>

#include "en_port.h"

#define DRV_NAME	"mlx4_en"
#define DRV_VERSION	"1.5.1.6"
#define DRV_RELDATE	"August 2010"

#define MLX4_EN_MSG_LEVEL	(NETIF_MSG_LINK | NETIF_MSG_IFDOWN)

/*
 * Device constants
 */


#define MLX4_EN_PAGE_SHIFT	12
#define MLX4_EN_PAGE_SIZE	(1 << MLX4_EN_PAGE_SHIFT)
#define MAX_RX_RINGS		16
#define MIN_RX_RINGS		4
#define TXBB_SIZE		64
#define HEADROOM		(2048 / TXBB_SIZE + 1)
#define STAMP_STRIDE		64
#define STAMP_DWORDS		(STAMP_STRIDE / 4)
#define STAMP_SHIFT		31
#define STAMP_VAL		0x7fffffff
#define STATS_DELAY		(HZ / 4)

/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
#define MAX_DESC_SIZE		512
#define MAX_DESC_TXBBS		(MAX_DESC_SIZE / TXBB_SIZE)

/*
 * OS related constants and tunables
 */

#define MLX4_EN_WATCHDOG_TIMEOUT	(15 * HZ)

#define MLX4_EN_ALLOC_ORDER	2
#define MLX4_EN_ALLOC_SIZE	(PAGE_SIZE << MLX4_EN_ALLOC_ORDER)

#define MLX4_EN_MAX_LRO_DESCRIPTORS	32

/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
 * and 4K allocations) */
enum {
	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	FRAG_SZ1 = 1024,
	FRAG_SZ2 = 4096,
	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
};
#define MLX4_EN_MAX_RX_FRAGS	4

/* Maximum ring sizes */
#define MLX4_EN_MAX_TX_SIZE	8192
#define MLX4_EN_MAX_RX_SIZE	8192

/* Minimum ring size for our page-allocation sceme to work */
#define MLX4_EN_MIN_RX_SIZE	(MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
#define MLX4_EN_MIN_TX_SIZE	(4096 / TXBB_SIZE)

#define MLX4_EN_SMALL_PKT_SIZE		64
#define MLX4_EN_NUM_TX_RINGS		8
#define MLX4_EN_NUM_PPP_RINGS		8
#define MAX_TX_RINGS			(MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
#define MLX4_EN_DEF_TX_RING_SIZE	512
#define MLX4_EN_DEF_RX_RING_SIZE  	1024

/* Target number of packets to coalesce with interrupt moderation */
#define MLX4_EN_RX_COAL_TARGET	44
#define MLX4_EN_RX_COAL_TIME	0x10

#define MLX4_EN_TX_COAL_PKTS	5
#define MLX4_EN_TX_COAL_TIME	0x80

#define MLX4_EN_RX_RATE_LOW		400000
#define MLX4_EN_RX_COAL_TIME_LOW	0
#define MLX4_EN_RX_RATE_HIGH		450000
#define MLX4_EN_RX_COAL_TIME_HIGH	128
#define MLX4_EN_RX_SIZE_THRESH		1024
#define MLX4_EN_RX_RATE_THRESH		(1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
#define MLX4_EN_SAMPLE_INTERVAL		0
#define MLX4_EN_AVG_PKT_SMALL		256

#define MLX4_EN_AUTO_CONF	0xffff

#define MLX4_EN_DEF_RX_PAUSE	1
#define MLX4_EN_DEF_TX_PAUSE	1

/* Interval between successive polls in the Tx routine when polling is used
   instead of interrupts (in per-core Tx rings) - should be power of 2 */
#define MLX4_EN_TX_POLL_MODER	16
#define MLX4_EN_TX_POLL_TIMEOUT	(HZ / 4)

#define ETH_LLC_SNAP_SIZE	8

#define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
#define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)

#define MLX4_EN_MIN_MTU		46
#define ETH_BCAST		0xffffffffffffULL

#define MLX4_EN_LOOPBACK_RETRIES	5
#define MLX4_EN_LOOPBACK_TIMEOUT	100

#ifdef MLX4_EN_PERF_STAT
/* Number of samples to 'average' */
#define AVG_SIZE			128
#define AVG_FACTOR			1024
#define NUM_PERF_STATS			NUM_PERF_COUNTERS

#define INC_PERF_COUNTER(cnt)		(++(cnt))
#define ADD_PERF_COUNTER(cnt, add)	((cnt) += (add))
#define AVG_PERF_COUNTER(cnt, sample) \
	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
#define GET_PERF_COUNTER(cnt)		(cnt)
#define GET_AVG_PERF_COUNTER(cnt)	((cnt) / AVG_FACTOR)

#else

#define NUM_PERF_STATS			0
#define INC_PERF_COUNTER(cnt)		do {} while (0)
#define ADD_PERF_COUNTER(cnt, add)	do {} while (0)
#define AVG_PERF_COUNTER(cnt, sample)	do {} while (0)
#define GET_PERF_COUNTER(cnt)		(0)
#define GET_AVG_PERF_COUNTER(cnt)	(0)
#endif /* MLX4_EN_PERF_STAT */

/*
 * Configurables
 */

enum cq_type {
	RX = 0,
	TX = 1,
};


/*
 * Useful macros
 */
#define ROUNDUP_LOG2(x)		ilog2(roundup_pow_of_two(x))
#define XNOR(x, y)		(!(x) == !(y))
#define ILLEGAL_MAC(addr)	(addr == 0xffffffffffffULL || addr == 0x0)


struct mlx4_en_tx_info {
	struct sk_buff *skb;
	u32 nr_txbb;
	u8 linear;
	u8 data_offset;
	u8 inl;
};


#define MLX4_EN_BIT_DESC_OWN	0x80000000
#define CTRL_SIZE	sizeof(struct mlx4_wqe_ctrl_seg)
#define MLX4_EN_MEMTYPE_PAD	0x100
#define DS_SIZE		sizeof(struct mlx4_wqe_data_seg)


struct mlx4_en_tx_desc {
	struct mlx4_wqe_ctrl_seg ctrl;
	union {
		struct mlx4_wqe_data_seg data; /* at least one data segment */
		struct mlx4_wqe_lso_seg lso;
		struct mlx4_wqe_inline_seg inl;
	};
};

#define MLX4_EN_USE_SRQ		0x01000000

#define MLX4_EN_CX3_LOW_ID	0x1000
#define MLX4_EN_CX3_HIGH_ID	0x1005

struct mlx4_en_rx_alloc {
	struct page *page;
	u16 offset;
};

struct mlx4_en_tx_ring {
	struct mlx4_hwq_resources wqres;
	u32 size ; /* number of TXBBs */
	u32 size_mask;
	u16 stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	u32 doorbell_qpn;
	void *buf;
	u16 poll_cnt;
	int blocked;
	struct mlx4_en_tx_info *tx_info;
	u8 *bounce_buf;
	u32 last_nr_txbb;
	struct mlx4_qp qp;
	struct mlx4_qp_context context;
	int qpn;
	enum mlx4_qp_state qp_state;
	struct mlx4_srq dummy;
	unsigned long bytes;
	unsigned long packets;
	spinlock_t comp_lock;
};

struct mlx4_en_rx_desc {
	/* actual number of entries depends on rx ring stride */
	struct mlx4_wqe_data_seg data[0];
};

struct mlx4_en_rx_ring {
	struct mlx4_hwq_resources wqres;
	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
	u32 size ;	/* number of Rx descs*/
	u32 actual_size;
	u32 size_mask;
	u16 stride;
	u16 log_stride;
	u16 cqn;	/* index of port CQ associated with this ring */
	u32 prod;
	u32 cons;
	u32 buf_size;
	void *buf;
	void *rx_info;
	unsigned long bytes;
	unsigned long packets;
};


static inline int mlx4_en_can_lro(__be16 status)
{
	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4	|
				     MLX4_CQE_STATUS_IPV4F	|
				     MLX4_CQE_STATUS_IPV6	|
				     MLX4_CQE_STATUS_IPV4OPT	|
				     MLX4_CQE_STATUS_TCP	|
				     MLX4_CQE_STATUS_UDP	|
				     MLX4_CQE_STATUS_IPOK)) ==
		cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
			    MLX4_CQE_STATUS_IPOK |
			    MLX4_CQE_STATUS_TCP);
}

struct mlx4_en_cq {
	struct mlx4_cq          mcq;
	struct mlx4_hwq_resources wqres;
	int                     ring;
	spinlock_t              lock;
	struct net_device      *dev;
	struct napi_struct	napi;
	/* Per-core Tx cq processing support */
	struct timer_list timer;
	int size;
	int buf_size;
	unsigned vector;
	enum cq_type is_tx;
	u16 moder_time;
	u16 moder_cnt;
	struct mlx4_cqe *buf;
#define MLX4_EN_OPCODE_ERROR	0x1e
};

struct mlx4_en_port_profile {
	u32 flags;
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 tx_ring_size;
	u32 rx_ring_size;
	u8 rx_pause;
	u8 rx_ppp;
	u8 tx_pause;
	u8 tx_ppp;
};

struct mlx4_en_profile {
	int rss_xor;
	int tcp_rss;
	int udp_rss;
	u8 rss_mask;
	u32 active_ports;
	u32 small_pkt_int;
	u8 no_reset;
	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
};

struct mlx4_en_dev {
	struct mlx4_dev         *dev;
	struct pci_dev		*pdev;
	struct mutex		state_lock;
	struct net_device       *pndev[MLX4_MAX_PORTS + 1];
	u32                     port_cnt;
	bool			device_up;
	struct mlx4_en_profile  profile;
	u32			LSO_support;
	struct workqueue_struct *workqueue;
	struct device           *dma_device;
	void __iomem            *uar_map;
	struct mlx4_uar         priv_uar;
	struct mlx4_mr		mr;
	u32                     priv_pdn;
	spinlock_t              uar_lock;
	u8			mac_removed[MLX4_MAX_PORTS + 1];
};


struct mlx4_en_rss_map {
	int base_qpn;
	struct mlx4_qp qps[MAX_RX_RINGS];
	enum mlx4_qp_state state[MAX_RX_RINGS];
	struct mlx4_qp indir_qp;
	enum mlx4_qp_state indir_state;
};

struct mlx4_en_rss_context {
	__be32 base_qpn;
	__be32 default_qpn;
	u16 reserved;
	u8 hash_fn;
	u8 flags;
	__be32 rss_key[10];
	__be32 base_qpn_udp;
};

struct mlx4_en_port_state {
	int link_state;
	int link_speed;
	int transciver;
};

struct mlx4_en_pkt_stats {
	unsigned long broadcast;
	unsigned long rx_prio[8];
	unsigned long tx_prio[8];
#define NUM_PKT_STATS		17
};

struct mlx4_en_port_stats {
	unsigned long tso_packets;
	unsigned long queue_stopped;
	unsigned long wake_queue;
	unsigned long tx_timeout;
	unsigned long rx_alloc_failed;
	unsigned long rx_chksum_good;
	unsigned long rx_chksum_none;
	unsigned long tx_chksum_offload;
#define NUM_PORT_STATS		8
};

struct mlx4_en_perf_stats {
	u32 tx_poll;
	u64 tx_pktsz_avg;
	u32 inflight_avg;
	u16 tx_coal_avg;
	u16 rx_coal_avg;
	u32 napi_quota;
#define NUM_PERF_COUNTERS		6
};

struct mlx4_en_frag_info {
	u16 frag_size;
	u16 frag_prefix_size;
	u16 frag_stride;
	u16 frag_align;
	u16 last_offset;

};

struct mlx4_en_priv {
	struct mlx4_en_dev *mdev;
	struct mlx4_en_port_profile *prof;
	struct net_device *dev;
	struct vlan_group *vlgrp;
	struct net_device_stats stats;
	struct net_device_stats ret_stats;
	struct mlx4_en_port_state port_state;
	spinlock_t stats_lock;

	unsigned long last_moder_packets;
	unsigned long last_moder_tx_packets;
	unsigned long last_moder_bytes;
	unsigned long last_moder_jiffies;
	int last_moder_time;
	u16 rx_usecs;
	u16 rx_frames;
	u16 tx_usecs;
	u16 tx_frames;
	u32 pkt_rate_low;
	u16 rx_usecs_low;
	u32 pkt_rate_high;
	u16 rx_usecs_high;
	u16 sample_interval;
	u16 adaptive_rx_coal;
	u32 msg_enable;
	u32 loopback_ok;
	u32 validate_loopback;

	struct mlx4_hwq_resources res;
	int link_state;
	int last_link_state;
	bool port_up;
	int port;
	int registered;
	int allocated;
	int stride;
	int rx_csum;
	u64 mac;
	int mac_index;
	unsigned max_mtu;
	int base_qpn;

	struct mlx4_en_rss_map rss_map;
	u32 flags;
#define MLX4_EN_FLAG_PROMISC	0x1
#define MLX4_EN_FLAG_MC_PROMISC	0x2
	u32 tx_ring_num;
	u32 rx_ring_num;
	u32 rx_skb_size;
	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
	u16 num_frags;
	u16 log_rx_info;

	struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
	int tx_vector;
	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
	struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
	struct work_struct mcast_task;
	struct work_struct mac_task;
	struct work_struct watchdog_task;
	struct work_struct linkstate_task;
	struct delayed_work stats_task;
	struct mlx4_en_perf_stats pstats;
	struct mlx4_en_pkt_stats pkstats;
	struct mlx4_en_port_stats port_stats;
	char *mc_addrs;
	int mc_addrs_cnt;
	struct mlx4_en_stat_out_mbox hw_stats;
	int vids[128];
	bool wol;
};

enum mlx4_en_wol {
	MLX4_EN_WOL_MAGIC = (1ULL << 61),
	MLX4_EN_WOL_ENABLED = (1ULL << 62),
	MLX4_EN_WOL_DO_MODIFY = (1ULL << 63),
};


void mlx4_en_destroy_netdev(struct net_device *dev);
int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
			struct mlx4_en_port_profile *prof);

int mlx4_en_start_port(struct net_device *dev);
void mlx4_en_stop_port(struct net_device *dev);

void mlx4_en_free_resources(struct mlx4_en_priv *priv, bool reserve_vectors);
int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);

int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
		      int entries, int ring, enum cq_type mode);
void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
			bool reserve_vectors);
int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);

void mlx4_en_poll_tx_cq(unsigned long data);
void mlx4_en_tx_irq(struct mlx4_cq *mcq);
u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);

int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
			   u32 size, u16 stride);
void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_tx_ring *ring,
			     int cq);
void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_tx_ring *ring);

int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
			   struct mlx4_en_rx_ring *ring,
			   u32 size, u16 stride);
void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
			     struct mlx4_en_rx_ring *ring);
int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
				struct mlx4_en_rx_ring *ring);
int mlx4_en_process_rx_cq(struct net_device *dev,
			  struct mlx4_en_cq *cq,
			  int budget);
int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
			     int is_tx, int rss, int qpn, int cqn,
			     struct mlx4_qp_context *context);
void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
int mlx4_en_map_buffer(struct mlx4_buf *buf);
void mlx4_en_unmap_buffer(struct mlx4_buf *buf);

void mlx4_en_calc_rx_buf(struct net_device *dev);
int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
void mlx4_en_rx_irq(struct mlx4_cq *mcq);

int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
			  u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
			   u8 promisc);

int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);

#define MLX4_EN_NUM_SELF_TEST	5
void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
u64 mlx4_en_mac_to_u64(u8 *addr);

/*
 * Globals
 */
extern const struct ethtool_ops mlx4_en_ethtool_ops;


/*
 * printk / logging functions
 */

int en_print(const char *level, const struct mlx4_en_priv *priv,
	     const char *format, ...) __attribute__ ((format (printf, 3, 4)));

#define en_dbg(mlevel, priv, format, arg...)			\
do {								\
	if (NETIF_MSG_##mlevel & priv->msg_enable)		\
		en_print(KERN_DEBUG, priv, format, ##arg);	\
} while (0)
#define en_warn(priv, format, arg...)			\
	en_print(KERN_WARNING, priv, format, ##arg)
#define en_err(priv, format, arg...)			\
	en_print(KERN_ERR, priv, format, ##arg)
#define en_info(priv, format, arg...)			\
	en_print(KERN_INFO, priv, format, ## arg)

#define mlx4_err(mdev, format, arg...)			\
	pr_err("%s %s: " format, DRV_NAME,		\
	       dev_name(&mdev->pdev->dev), ##arg)
#define mlx4_info(mdev, format, arg...)			\
	pr_info("%s %s: " format, DRV_NAME,		\
		dev_name(&mdev->pdev->dev), ##arg)
#define mlx4_warn(mdev, format, arg...)			\
	pr_warning("%s %s: " format, DRV_NAME,		\
		   dev_name(&mdev->pdev->dev), ##arg)

#endif
Commit	Line	Data
c27a02cd YP	1	/*
	2	* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*
	32	*/
	33
	34	#ifndef _MLX4_EN_H_
	35	#define _MLX4_EN_H_
	36
	37	#include <linux/compiler.h>
	38	#include <linux/list.h>
	39	#include <linux/mutex.h>
	40	#include <linux/netdevice.h>
c27a02cd YP	41
	42	#include <linux/mlx4/device.h>
	43	#include <linux/mlx4/qp.h>
	44	#include <linux/mlx4/cq.h>
	45	#include <linux/mlx4/srq.h>
	46	#include <linux/mlx4/doorbell.h>
e7c1c2c4	47	#include <linux/mlx4/cmd.h>
c27a02cd YP	48
	49	#include "en_port.h"
	50
	51	#define DRV_NAME "mlx4_en"
04714a16 YP	52	#define DRV_VERSION "1.5.1.6"
04714a16 YP	53	#define DRV_RELDATE "August 2010"
c27a02cd	54
c27a02cd YP	55	#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK \| NETIF_MSG_IFDOWN)
c27a02cd YP	56
c27a02cd YP	57	/*
	58	* Device constants
	59	*/
	60
	61
	62	#define MLX4_EN_PAGE_SHIFT 12
	63	#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
c27a02cd	64	#define MAX_RX_RINGS 16
1fb9876e	65	#define MIN_RX_RINGS 4
c27a02cd YP	66	#define TXBB_SIZE 64
c27a02cd YP	67	#define HEADROOM (2048 / TXBB_SIZE + 1)
c27a02cd YP	68	#define STAMP_STRIDE 64
	69	#define STAMP_DWORDS (STAMP_STRIDE / 4)
	70	#define STAMP_SHIFT 31
	71	#define STAMP_VAL 0x7fffffff
	72	#define STATS_DELAY (HZ / 4)
	73
	74	/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
	75	#define MAX_DESC_SIZE 512
	76	#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
	77
	78	/*
	79	* OS related constants and tunables
	80	*/
	81
	82	#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
	83
	84	#define MLX4_EN_ALLOC_ORDER 2
	85	#define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
	86
	87	#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
	88
	89	/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
	90	* and 4K allocations) */
	91	enum {
	92	FRAG_SZ0 = 512 - NET_IP_ALIGN,
	93	FRAG_SZ1 = 1024,
	94	FRAG_SZ2 = 4096,
	95	FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
	96	};
	97	#define MLX4_EN_MAX_RX_FRAGS 4
	98
bd531e36 YP	99	/* Maximum ring sizes */
	100	#define MLX4_EN_MAX_TX_SIZE 8192
	101	#define MLX4_EN_MAX_RX_SIZE 8192
	102
c27a02cd YP	103	/* Minimum ring size for our page-allocation sceme to work */
	104	#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
	105	#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
	106
f813cad8 YP	107	#define MLX4_EN_SMALL_PKT_SIZE 64
	108	#define MLX4_EN_NUM_TX_RINGS 8
	109	#define MLX4_EN_NUM_PPP_RINGS 8
a0b4e6e0	110	#define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
f813cad8	111	#define MLX4_EN_DEF_TX_RING_SIZE 512
c27a02cd YP	112	#define MLX4_EN_DEF_RX_RING_SIZE 1024
c27a02cd YP	113
3db36fb2 YP	114	/* Target number of packets to coalesce with interrupt moderation */
3db36fb2 YP	115	#define MLX4_EN_RX_COAL_TARGET 44
c27a02cd YP	116	#define MLX4_EN_RX_COAL_TIME 0x10
	117
	118	#define MLX4_EN_TX_COAL_PKTS 5
	119	#define MLX4_EN_TX_COAL_TIME 0x80
	120
	121	#define MLX4_EN_RX_RATE_LOW 400000
	122	#define MLX4_EN_RX_COAL_TIME_LOW 0
	123	#define MLX4_EN_RX_RATE_HIGH 450000
	124	#define MLX4_EN_RX_COAL_TIME_HIGH 128
	125	#define MLX4_EN_RX_SIZE_THRESH 1024
	126	#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
	127	#define MLX4_EN_SAMPLE_INTERVAL 0
46afd0fb	128	#define MLX4_EN_AVG_PKT_SMALL 256
c27a02cd YP	129
	130	#define MLX4_EN_AUTO_CONF 0xffff
	131
	132	#define MLX4_EN_DEF_RX_PAUSE 1
	133	#define MLX4_EN_DEF_TX_PAUSE 1
	134
af901ca1	135	/* Interval between successive polls in the Tx routine when polling is used
c27a02cd YP	136	instead of interrupts (in per-core Tx rings) - should be power of 2 */
	137	#define MLX4_EN_TX_POLL_MODER 16
	138	#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
	139
	140	#define ETH_LLC_SNAP_SIZE 8
	141
	142	#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
	143	#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
e7c1c2c4	144	#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
c27a02cd YP	145
	146	#define MLX4_EN_MIN_MTU 46
	147	#define ETH_BCAST 0xffffffffffffULL
	148
e7c1c2c4 YP	149	#define MLX4_EN_LOOPBACK_RETRIES 5
	150	#define MLX4_EN_LOOPBACK_TIMEOUT 100
	151
c27a02cd YP	152	#ifdef MLX4_EN_PERF_STAT
	153	/* Number of samples to 'average' */
	154	#define AVG_SIZE 128
	155	#define AVG_FACTOR 1024
	156	#define NUM_PERF_STATS NUM_PERF_COUNTERS
	157
	158	#define INC_PERF_COUNTER(cnt) (++(cnt))
	159	#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
	160	#define AVG_PERF_COUNTER(cnt, sample) \
	161	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
	162	#define GET_PERF_COUNTER(cnt) (cnt)
	163	#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
	164
	165	#else
	166
	167	#define NUM_PERF_STATS 0
	168	#define INC_PERF_COUNTER(cnt) do {} while (0)
	169	#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
	170	#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
	171	#define GET_PERF_COUNTER(cnt) (0)
	172	#define GET_AVG_PERF_COUNTER(cnt) (0)
	173	#endif /* MLX4_EN_PERF_STAT */
	174
	175	/*
	176	* Configurables
	177	*/
	178
	179	enum cq_type {
	180	RX = 0,
	181	TX = 1,
	182	};
	183
	184
	185	/*
	186	* Useful macros
	187	*/
	188	#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
	189	#define XNOR(x, y) (!(x) == !(y))
	190	#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL \|\| addr == 0x0)
	191
	192
	193	struct mlx4_en_tx_info {
	194	struct sk_buff *skb;
	195	u32 nr_txbb;
	196	u8 linear;
	197	u8 data_offset;
41efea5a	198	u8 inl;
c27a02cd YP	199	};
	200
	201
	202	#define MLX4_EN_BIT_DESC_OWN 0x80000000
	203	#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
	204	#define MLX4_EN_MEMTYPE_PAD 0x100
	205	#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
	206
	207
	208	struct mlx4_en_tx_desc {
	209	struct mlx4_wqe_ctrl_seg ctrl;
	210	union {
	211	struct mlx4_wqe_data_seg data; /* at least one data segment */
	212	struct mlx4_wqe_lso_seg lso;
	213	struct mlx4_wqe_inline_seg inl;
	214	};
	215	};
	216
	217	#define MLX4_EN_USE_SRQ 0x01000000
	218
725c8999 YP	219	#define MLX4_EN_CX3_LOW_ID 0x1000
	220	#define MLX4_EN_CX3_HIGH_ID 0x1005
	221
c27a02cd YP	222	struct mlx4_en_rx_alloc {
	223	struct page *page;
	224	u16 offset;
	225	};
	226
	227	struct mlx4_en_tx_ring {
	228	struct mlx4_hwq_resources wqres;
	229	u32 size ; /* number of TXBBs */
	230	u32 size_mask;
	231	u16 stride;
	232	u16 cqn; /* index of port CQ associated with this ring */
	233	u32 prod;
	234	u32 cons;
	235	u32 buf_size;
	236	u32 doorbell_qpn;
	237	void *buf;
	238	u16 poll_cnt;
	239	int blocked;
	240	struct mlx4_en_tx_info *tx_info;
	241	u8 *bounce_buf;
	242	u32 last_nr_txbb;
	243	struct mlx4_qp qp;
	244	struct mlx4_qp_context context;
	245	int qpn;
	246	enum mlx4_qp_state qp_state;
	247	struct mlx4_srq dummy;
	248	unsigned long bytes;
	249	unsigned long packets;
	250	spinlock_t comp_lock;
	251	};
	252
	253	struct mlx4_en_rx_desc {
c27a02cd YP	254	/* actual number of entries depends on rx ring stride */
	255	struct mlx4_wqe_data_seg data[0];
	256	};
	257
	258	struct mlx4_en_rx_ring {
c27a02cd YP	259	struct mlx4_hwq_resources wqres;
c27a02cd YP	260	struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
c27a02cd YP	261	u32 size ; /* number of Rx descs*/
	262	u32 actual_size;
	263	u32 size_mask;
	264	u16 stride;
	265	u16 log_stride;
	266	u16 cqn; /* index of port CQ associated with this ring */
	267	u32 prod;
	268	u32 cons;
	269	u32 buf_size;
c27a02cd YP	270	void *buf;
	271	void *rx_info;
	272	unsigned long bytes;
	273	unsigned long packets;
	274	};
	275
	276
	277	static inline int mlx4_en_can_lro(__be16 status)
	278	{
	279	return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
	280	MLX4_CQE_STATUS_IPV4F \|
	281	MLX4_CQE_STATUS_IPV6 \|
	282	MLX4_CQE_STATUS_IPV4OPT \|
	283	MLX4_CQE_STATUS_TCP \|
	284	MLX4_CQE_STATUS_UDP \|
	285	MLX4_CQE_STATUS_IPOK)) ==
	286	cpu_to_be16(MLX4_CQE_STATUS_IPV4 \|
	287	MLX4_CQE_STATUS_IPOK \|
	288	MLX4_CQE_STATUS_TCP);
	289	}
	290
	291	struct mlx4_en_cq {
	292	struct mlx4_cq mcq;
	293	struct mlx4_hwq_resources wqres;
	294	int ring;
	295	spinlock_t lock;
	296	struct net_device *dev;
	297	struct napi_struct napi;
	298	/* Per-core Tx cq processing support */
	299	struct timer_list timer;
	300	int size;
	301	int buf_size;
	302	unsigned vector;
	303	enum cq_type is_tx;
	304	u16 moder_time;
	305	u16 moder_cnt;
c27a02cd YP	306	struct mlx4_cqe *buf;
	307	#define MLX4_EN_OPCODE_ERROR 0x1e
	308	};
	309
	310	struct mlx4_en_port_profile {
	311	u32 flags;
	312	u32 tx_ring_num;
	313	u32 rx_ring_num;
	314	u32 tx_ring_size;
	315	u32 rx_ring_size;
d53b93f2 YP	316	u8 rx_pause;
	317	u8 rx_ppp;
	318	u8 tx_pause;
	319	u8 tx_ppp;
c27a02cd YP	320	};
	321
	322	struct mlx4_en_profile {
	323	int rss_xor;
0533943c YP	324	int tcp_rss;
0533943c YP	325	int udp_rss;
c27a02cd YP	326	u8 rss_mask;
	327	u32 active_ports;
	328	u32 small_pkt_int;
c27a02cd YP	329	u8 no_reset;
	330	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
	331	};
	332
	333	struct mlx4_en_dev {
	334	struct mlx4_dev *dev;
	335	struct pci_dev *pdev;
	336	struct mutex state_lock;
	337	struct net_device *pndev[MLX4_MAX_PORTS + 1];
	338	u32 port_cnt;
	339	bool device_up;
	340	struct mlx4_en_profile profile;
	341	u32 LSO_support;
	342	struct workqueue_struct *workqueue;
	343	struct device *dma_device;
	344	void __iomem *uar_map;
	345	struct mlx4_uar priv_uar;
	346	struct mlx4_mr mr;
	347	u32 priv_pdn;
	348	spinlock_t uar_lock;
d7e1a487	349	u8 mac_removed[MLX4_MAX_PORTS + 1];
c27a02cd YP	350	};
	351
	352
	353	struct mlx4_en_rss_map {
c27a02cd	354	int base_qpn;
b6b912e0 YP	355	struct mlx4_qp qps[MAX_RX_RINGS];
b6b912e0 YP	356	enum mlx4_qp_state state[MAX_RX_RINGS];
c27a02cd YP	357	struct mlx4_qp indir_qp;
	358	enum mlx4_qp_state indir_state;
	359	};
	360
	361	struct mlx4_en_rss_context {
	362	__be32 base_qpn;
	363	__be32 default_qpn;
	364	u16 reserved;
	365	u8 hash_fn;
	366	u8 flags;
	367	__be32 rss_key[10];
0533943c	368	__be32 base_qpn_udp;
c27a02cd YP	369	};
c27a02cd YP	370
e7c1c2c4 YP	371	struct mlx4_en_port_state {
	372	int link_state;
	373	int link_speed;
	374	int transciver;
	375	};
	376
c27a02cd YP	377	struct mlx4_en_pkt_stats {
	378	unsigned long broadcast;
	379	unsigned long rx_prio[8];
	380	unsigned long tx_prio[8];
	381	#define NUM_PKT_STATS 17
	382	};
	383
	384	struct mlx4_en_port_stats {
c27a02cd YP	385	unsigned long tso_packets;
	386	unsigned long queue_stopped;
	387	unsigned long wake_queue;
	388	unsigned long tx_timeout;
	389	unsigned long rx_alloc_failed;
	390	unsigned long rx_chksum_good;
	391	unsigned long rx_chksum_none;
	392	unsigned long tx_chksum_offload;
d61702f1	393	#define NUM_PORT_STATS 8
c27a02cd YP	394	};
	395
	396	struct mlx4_en_perf_stats {
	397	u32 tx_poll;
	398	u64 tx_pktsz_avg;
	399	u32 inflight_avg;
	400	u16 tx_coal_avg;
	401	u16 rx_coal_avg;
	402	u32 napi_quota;
	403	#define NUM_PERF_COUNTERS 6
	404	};
	405
	406	struct mlx4_en_frag_info {
	407	u16 frag_size;
	408	u16 frag_prefix_size;
	409	u16 frag_stride;
	410	u16 frag_align;
	411	u16 last_offset;
	412
	413	};
	414
	415	struct mlx4_en_priv {
	416	struct mlx4_en_dev *mdev;
	417	struct mlx4_en_port_profile *prof;
	418	struct net_device *dev;
	419	struct vlan_group *vlgrp;
	420	struct net_device_stats stats;
	421	struct net_device_stats ret_stats;
e7c1c2c4	422	struct mlx4_en_port_state port_state;
c27a02cd YP	423	spinlock_t stats_lock;
	424
	425	unsigned long last_moder_packets;
	426	unsigned long last_moder_tx_packets;
	427	unsigned long last_moder_bytes;
	428	unsigned long last_moder_jiffies;
	429	int last_moder_time;
	430	u16 rx_usecs;
	431	u16 rx_frames;
	432	u16 tx_usecs;
	433	u16 tx_frames;
	434	u32 pkt_rate_low;
	435	u16 rx_usecs_low;
	436	u32 pkt_rate_high;
	437	u16 rx_usecs_high;
	438	u16 sample_interval;
	439	u16 adaptive_rx_coal;
	440	u32 msg_enable;
e7c1c2c4 YP	441	u32 loopback_ok;
e7c1c2c4 YP	442	u32 validate_loopback;
c27a02cd YP	443
	444	struct mlx4_hwq_resources res;
	445	int link_state;
	446	int last_link_state;
	447	bool port_up;
	448	int port;
	449	int registered;
	450	int allocated;
	451	int stride;
	452	int rx_csum;
	453	u64 mac;
	454	int mac_index;
	455	unsigned max_mtu;
	456	int base_qpn;
	457
	458	struct mlx4_en_rss_map rss_map;
c27a02cd YP	459	u32 flags;
c27a02cd YP	460	#define MLX4_EN_FLAG_PROMISC 0x1
1679200f	461	#define MLX4_EN_FLAG_MC_PROMISC 0x2
c27a02cd YP	462	u32 tx_ring_num;
	463	u32 rx_ring_num;
	464	u32 rx_skb_size;
	465	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
	466	u16 num_frags;
	467	u16 log_rx_info;
	468
	469	struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
1fb9876e	470	int tx_vector;
c27a02cd YP	471	struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
	472	struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
	473	struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
	474	struct work_struct mcast_task;
	475	struct work_struct mac_task;
c27a02cd YP	476	struct work_struct watchdog_task;
	477	struct work_struct linkstate_task;
	478	struct delayed_work stats_task;
	479	struct mlx4_en_perf_stats pstats;
	480	struct mlx4_en_pkt_stats pkstats;
	481	struct mlx4_en_port_stats port_stats;
ff6e2163 JP	482	char *mc_addrs;
ff6e2163 JP	483	int mc_addrs_cnt;
c27a02cd	484	struct mlx4_en_stat_out_mbox hw_stats;
4c3eb3ca	485	int vids[128];
14c07b13 YP	486	bool wol;
	487	};
	488
	489	enum mlx4_en_wol {
	490	MLX4_EN_WOL_MAGIC = (1ULL << 61),
	491	MLX4_EN_WOL_ENABLED = (1ULL << 62),
	492	MLX4_EN_WOL_DO_MODIFY = (1ULL << 63),
c27a02cd YP	493	};
	494
	495
	496	void mlx4_en_destroy_netdev(struct net_device *dev);
	497	int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
	498	struct mlx4_en_port_profile *prof);
	499
18cc42a3 YP	500	int mlx4_en_start_port(struct net_device *dev);
	501	void mlx4_en_stop_port(struct net_device *dev);
	502
1fb9876e	503	void mlx4_en_free_resources(struct mlx4_en_priv *priv, bool reserve_vectors);
18cc42a3 YP	504	int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
18cc42a3 YP	505
c27a02cd YP	506	int mlx4_en_create_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq,
c27a02cd YP	507	int entries, int ring, enum cq_type mode);
1fb9876e YP	508	void mlx4_en_destroy_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq,
1fb9876e YP	509	bool reserve_vectors);
c27a02cd YP	510	int mlx4_en_activate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	511	void mlx4_en_deactivate_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	512	int mlx4_en_set_cq_moder(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	513	int mlx4_en_arm_cq(struct mlx4_en_priv priv, struct mlx4_en_cq cq);
	514
	515	void mlx4_en_poll_tx_cq(unsigned long data);
	516	void mlx4_en_tx_irq(struct mlx4_cq *mcq);
f813cad8	517	u16 mlx4_en_select_queue(struct net_device dev, struct sk_buff skb);
61357325	518	netdev_tx_t mlx4_en_xmit(struct sk_buff skb, struct net_device dev);
c27a02cd YP	519
	520	int mlx4_en_create_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring,
	521	u32 size, u16 stride);
	522	void mlx4_en_destroy_tx_ring(struct mlx4_en_priv priv, struct mlx4_en_tx_ring ring);
	523	int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
	524	struct mlx4_en_tx_ring *ring,
9f519f68	525	int cq);
c27a02cd YP	526	void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
	527	struct mlx4_en_tx_ring *ring);
	528
	529	int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
	530	struct mlx4_en_rx_ring *ring,
	531	u32 size, u16 stride);
	532	void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
	533	struct mlx4_en_rx_ring *ring);
	534	int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
	535	void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
	536	struct mlx4_en_rx_ring *ring);
	537	int mlx4_en_process_rx_cq(struct net_device *dev,
	538	struct mlx4_en_cq *cq,
	539	int budget);
	540	int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
	541	void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
9f519f68	542	int is_tx, int rss, int qpn, int cqn,
c27a02cd	543	struct mlx4_qp_context *context);
966508f7	544	void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
c27a02cd YP	545	int mlx4_en_map_buffer(struct mlx4_buf *buf);
	546	void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
	547
	548	void mlx4_en_calc_rx_buf(struct net_device *dev);
c27a02cd YP	549	int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
	550	void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
	551	int mlx4_en_free_tx_buf(struct net_device dev, struct mlx4_en_tx_ring ring);
c27a02cd YP	552	void mlx4_en_rx_irq(struct mlx4_cq *mcq);
	553
	554	int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
	555	int mlx4_SET_VLAN_FLTR(struct mlx4_dev dev, u8 port, struct vlan_group grp);
	556	int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
	557	u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
	558	int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
	559	u8 promisc);
	560
	561	int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
e7c1c2c4 YP	562	int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
	563
	564	#define MLX4_EN_NUM_SELF_TEST 5
	565	void mlx4_en_ex_selftest(struct net_device dev, u32 flags, u64 *buf);
	566	u64 mlx4_en_mac_to_u64(u8 *addr);
c27a02cd YP	567
	568	/*
	569	* Globals
	570	*/
	571	extern const struct ethtool_ops mlx4_en_ethtool_ops;
0a645e80 JP	572
	573
	574
	575	/*
	576	* printk / logging functions
	577	*/
	578
	579	int en_print(const char level, const struct mlx4_en_priv priv,
	580	const char *format, ...) __attribute__ ((format (printf, 3, 4)));
	581
	582	#define en_dbg(mlevel, priv, format, arg...) \
	583	do { \
	584	if (NETIF_MSG_##mlevel & priv->msg_enable) \
	585	en_print(KERN_DEBUG, priv, format, ##arg); \
	586	} while (0)
	587	#define en_warn(priv, format, arg...) \
	588	en_print(KERN_WARNING, priv, format, ##arg)
	589	#define en_err(priv, format, arg...) \
	590	en_print(KERN_ERR, priv, format, ##arg)
e5cc44b2 YP	591	#define en_info(priv, format, arg...) \
e5cc44b2 YP	592	en_print(KERN_INFO, priv, format, ## arg)
0a645e80 JP	593
	594	#define mlx4_err(mdev, format, arg...) \
	595	pr_err("%s %s: " format, DRV_NAME, \
	596	dev_name(&mdev->pdev->dev), ##arg)
	597	#define mlx4_info(mdev, format, arg...) \
	598	pr_info("%s %s: " format, DRV_NAME, \
	599	dev_name(&mdev->pdev->dev), ##arg)
	600	#define mlx4_warn(mdev, format, arg...) \
	601	pr_warning("%s %s: " format, DRV_NAME, \
	602	dev_name(&mdev->pdev->dev), ##arg)
	603
c27a02cd	604	#endif