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sfc: Use generic XENPAK register definitions
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
c3efab8e 41#include <linux/ip.h>
1da177e4
LT		 42#include <linux/tcp.h>
43#include <linux/udp.h>
44#include <linux/etherdevice.h>
1da177e4
LT		 45#include <linux/delay.h>
46#include <linux/ethtool.h>
d052d1be 47#include <linux/platform_device.h>
fbd6a754
LB		 48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/spinlock.h>
51#include <linux/workqueue.h>
ed94493f 52#include <linux/phy.h>
fbd6a754 53#include <linux/mv643xx_eth.h>
10a9948d
LB		 54#include <linux/io.h>
55#include <linux/types.h>
eaf5d590 56#include <linux/inet_lro.h>
1da177e4 57#include <asm/system.h>
fbd6a754 58
e5371493 59static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 60static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 61
fbd6a754 62
fbd6a754
LB		 63/*
64 * Registers shared between all ports.
65 */
3cb4667c
LB		 66#define PHY_ADDR 0x0000
67#define SMI_REG 0x0004
45c5d3bc
LB		 68#define SMI_BUSY 0x10000000
69#define SMI_READ_VALID 0x08000000
70#define SMI_OPCODE_READ 0x04000000
71#define SMI_OPCODE_WRITE 0x00000000
72#define ERR_INT_CAUSE 0x0080
73#define ERR_INT_SMI_DONE 0x00000010
74#define ERR_INT_MASK 0x0084
3cb4667c
LB		 75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
37a6084f
LB		 82 * Main per-port registers. These live at offset 0x0400 for
83 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 84 */
37a6084f 85#define PORT_CONFIG 0x0000
d9a073ea 86#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 87#define PORT_CONFIG_EXT 0x0004
88#define MAC_ADDR_LOW 0x0014
89#define MAC_ADDR_HIGH 0x0018
90#define SDMA_CONFIG 0x001c
becfad97
LB		 91#define TX_BURST_SIZE_16_64BIT 0x01000000
92#define TX_BURST_SIZE_4_64BIT 0x00800000
93#define BLM_TX_NO_SWAP 0x00000020
94#define BLM_RX_NO_SWAP 0x00000010
95#define RX_BURST_SIZE_16_64BIT 0x00000008
96#define RX_BURST_SIZE_4_64BIT 0x00000004
37a6084f 97#define PORT_SERIAL_CONTROL 0x003c
becfad97
LB		 98#define SET_MII_SPEED_TO_100 0x01000000
99#define SET_GMII_SPEED_TO_1000 0x00800000
100#define SET_FULL_DUPLEX_MODE 0x00200000
101#define MAX_RX_PACKET_9700BYTE 0x000a0000
102#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
103#define DO_NOT_FORCE_LINK_FAIL 0x00000400
104#define SERIAL_PORT_CONTROL_RESERVED 0x00000200
105#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
106#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
107#define FORCE_LINK_PASS 0x00000002
108#define SERIAL_PORT_ENABLE 0x00000001
37a6084f 109#define PORT_STATUS 0x0044
a2a41689 110#define TX_FIFO_EMPTY 0x00000400
ae9ae064 111#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 112#define PORT_SPEED_MASK 0x00000030
113#define PORT_SPEED_1000 0x00000010
114#define PORT_SPEED_100 0x00000020
115#define PORT_SPEED_10 0x00000000
116#define FLOW_CONTROL_ENABLED 0x00000008
117#define FULL_DUPLEX 0x00000004
81600eea 118#define LINK_UP 0x00000002
37a6084f
LB		 119#define TXQ_COMMAND 0x0048
120#define TXQ_FIX_PRIO_CONF 0x004c
121#define TX_BW_RATE 0x0050
122#define TX_BW_MTU 0x0058
123#define TX_BW_BURST 0x005c
124#define INT_CAUSE 0x0060
226bb6b7 125#define INT_TX_END 0x07f80000
e0ca8410 126#define INT_TX_END_0 0x00080000
befefe21 127#define INT_RX 0x000003fc
e0ca8410 128#define INT_RX_0 0x00000004
073a345c 129#define INT_EXT 0x00000002
37a6084f 130#define INT_CAUSE_EXT 0x0064
befefe21
LB		 131#define INT_EXT_LINK_PHY 0x00110000
132#define INT_EXT_TX 0x000000ff
37a6084f
LB		 133#define INT_MASK 0x0068
134#define INT_MASK_EXT 0x006c
135#define TX_FIFO_URGENT_THRESHOLD 0x0074
136#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
137#define TX_BW_RATE_MOVED 0x00e0
138#define TX_BW_MTU_MOVED 0x00e8
139#define TX_BW_BURST_MOVED 0x00ec
140#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
141#define RXQ_COMMAND 0x0280
142#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
143#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
144#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
145#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
146
147/*
148 * Misc per-port registers.
149 */
3cb4667c
LB		 150#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
151#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
152#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
153#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 154
2679a550
LB		 155
156/*
becfad97 157 * SDMA configuration register default value.
2679a550 158 */
fbd6a754
LB		 159#if defined(__BIG_ENDIAN)
160#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 161 (RX_BURST_SIZE_4_64BIT | \
162 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 163#elif defined(__LITTLE_ENDIAN)
164#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 165 (RX_BURST_SIZE_4_64BIT | \
166 BLM_RX_NO_SWAP | \
167 BLM_TX_NO_SWAP | \
168 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 169#else
170#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
171#endif
172
2beff77b
LB		 173
174/*
becfad97 175 * Misc definitions.
2beff77b 176 */
becfad97
LB		 177#define DEFAULT_RX_QUEUE_SIZE 128
178#define DEFAULT_TX_QUEUE_SIZE 256
7fd96ce4 179#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
fbd6a754 180
fbd6a754 181
7ca72a3b
LB		 182/*
183 * RX/TX descriptors.
fbd6a754
LB		 184 */
185#if defined(__BIG_ENDIAN)
cc9754b3 186struct rx_desc {
fbd6a754
LB		 187 u16 byte_cnt; /* Descriptor buffer byte count */
188 u16 buf_size; /* Buffer size */
189 u32 cmd_sts; /* Descriptor command status */
190 u32 next_desc_ptr; /* Next descriptor pointer */
191 u32 buf_ptr; /* Descriptor buffer pointer */
192};
193
cc9754b3 194struct tx_desc {
fbd6a754
LB		 195 u16 byte_cnt; /* buffer byte count */
196 u16 l4i_chk; /* CPU provided TCP checksum */
197 u32 cmd_sts; /* Command/status field */
198 u32 next_desc_ptr; /* Pointer to next descriptor */
199 u32 buf_ptr; /* pointer to buffer for this descriptor*/
200};
201#elif defined(__LITTLE_ENDIAN)
cc9754b3 202struct rx_desc {
fbd6a754
LB		 203 u32 cmd_sts; /* Descriptor command status */
204 u16 buf_size; /* Buffer size */
205 u16 byte_cnt; /* Descriptor buffer byte count */
206 u32 buf_ptr; /* Descriptor buffer pointer */
207 u32 next_desc_ptr; /* Next descriptor pointer */
208};
209
cc9754b3 210struct tx_desc {
fbd6a754
LB		 211 u32 cmd_sts; /* Command/status field */
212 u16 l4i_chk; /* CPU provided TCP checksum */
213 u16 byte_cnt; /* buffer byte count */
214 u32 buf_ptr; /* pointer to buffer for this descriptor*/
215 u32 next_desc_ptr; /* Pointer to next descriptor */
216};
217#else
218#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
219#endif
220
7ca72a3b 221/* RX & TX descriptor command */
cc9754b3 222#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 223
224/* RX & TX descriptor status */
cc9754b3 225#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 226
227/* RX descriptor status */
cc9754b3
LB		 228#define LAYER_4_CHECKSUM_OK 0x40000000
229#define RX_ENABLE_INTERRUPT 0x20000000
230#define RX_FIRST_DESC 0x08000000
231#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 232#define RX_IP_HDR_OK 0x02000000
233#define RX_PKT_IS_IPV4 0x01000000
234#define RX_PKT_IS_ETHERNETV2 0x00800000
235#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
236#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
237#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 238
239/* TX descriptor command */
cc9754b3
LB		 240#define TX_ENABLE_INTERRUPT 0x00800000
241#define GEN_CRC 0x00400000
242#define TX_FIRST_DESC 0x00200000
243#define TX_LAST_DESC 0x00100000
244#define ZERO_PADDING 0x00080000
245#define GEN_IP_V4_CHECKSUM 0x00040000
246#define GEN_TCP_UDP_CHECKSUM 0x00020000
247#define UDP_FRAME 0x00010000
e32b6617
LB		 248#define MAC_HDR_EXTRA_4_BYTES 0x00008000
249#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 250
cc9754b3 251#define TX_IHL_SHIFT 11
7ca72a3b
LB		 252
253
c9df406f 254/* global *******************************************************************/
e5371493 255struct mv643xx_eth_shared_private {
fc32b0e2
LB		 256 /*
257 * Ethernet controller base address.
258 */
cc9754b3 259 void __iomem *base;
c9df406f 260
fc0eb9f2
LB		 261 /*
262 * Points at the right SMI instance to use.
263 */
264 struct mv643xx_eth_shared_private *smi;
265
fc32b0e2 266 /*
ed94493f 267 * Provides access to local SMI interface.
fc32b0e2 268 */
298cf9be 269 struct mii_bus *smi_bus;
c9df406f 270
45c5d3bc
LB		 271 /*
272 * If we have access to the error interrupt pin (which is
273 * somewhat misnamed as it not only reflects internal errors
274 * but also reflects SMI completion), use that to wait for
275 * SMI access completion instead of polling the SMI busy bit.
276 */
277 int err_interrupt;
278 wait_queue_head_t smi_busy_wait;
279
fc32b0e2
LB		 280 /*
281 * Per-port MBUS window access register value.
282 */
c9df406f
LB		 283 u32 win_protect;
284
fc32b0e2
LB		 285 /*
286 * Hardware-specific parameters.
287 */
c9df406f 288 unsigned int t_clk;
773fc3ee 289 int extended_rx_coal_limit;
457b1d5a 290 int tx_bw_control;
c9df406f
LB		 291};
292
457b1d5a
LB		 293#define TX_BW_CONTROL_ABSENT 0
294#define TX_BW_CONTROL_OLD_LAYOUT 1
295#define TX_BW_CONTROL_NEW_LAYOUT 2
296
e7d2f4db
LB		 297static int mv643xx_eth_open(struct net_device *dev);
298static int mv643xx_eth_stop(struct net_device *dev);
299
c9df406f
LB		 300
301/* per-port *****************************************************************/
e5371493 302struct mib_counters {
fbd6a754
LB		 303 u64 good_octets_received;
304 u32 bad_octets_received;
305 u32 internal_mac_transmit_err;
306 u32 good_frames_received;
307 u32 bad_frames_received;
308 u32 broadcast_frames_received;
309 u32 multicast_frames_received;
310 u32 frames_64_octets;
311 u32 frames_65_to_127_octets;
312 u32 frames_128_to_255_octets;
313 u32 frames_256_to_511_octets;
314 u32 frames_512_to_1023_octets;
315 u32 frames_1024_to_max_octets;
316 u64 good_octets_sent;
317 u32 good_frames_sent;
318 u32 excessive_collision;
319 u32 multicast_frames_sent;
320 u32 broadcast_frames_sent;
321 u32 unrec_mac_control_received;
322 u32 fc_sent;
323 u32 good_fc_received;
324 u32 bad_fc_received;
325 u32 undersize_received;
326 u32 fragments_received;
327 u32 oversize_received;
328 u32 jabber_received;
329 u32 mac_receive_error;
330 u32 bad_crc_event;
331 u32 collision;
332 u32 late_collision;
333};
334
eaf5d590
LB		 335struct lro_counters {
336 u32 lro_aggregated;
337 u32 lro_flushed;
338 u32 lro_no_desc;
339};
340
8a578111 341struct rx_queue {
64da80a2
LB		 342 int index;
343
8a578111
LB		 344 int rx_ring_size;
345
346 int rx_desc_count;
347 int rx_curr_desc;
348 int rx_used_desc;
349
350 struct rx_desc *rx_desc_area;
351 dma_addr_t rx_desc_dma;
352 int rx_desc_area_size;
353 struct sk_buff **rx_skb;
eaf5d590 354
eaf5d590
LB		 355 struct net_lro_mgr lro_mgr;
356 struct net_lro_desc lro_arr[8];
8a578111
LB		 357};
358
13d64285 359struct tx_queue {
3d6b35bc
LB		 360 int index;
361
13d64285 362 int tx_ring_size;
fbd6a754 363
13d64285
LB		 364 int tx_desc_count;
365 int tx_curr_desc;
366 int tx_used_desc;
fbd6a754 367
5daffe94 368 struct tx_desc *tx_desc_area;
fbd6a754
LB		 369 dma_addr_t tx_desc_dma;
370 int tx_desc_area_size;
99ab08e0
LB		 371
372 struct sk_buff_head tx_skb;
8fd89211
LB		 373
374 unsigned long tx_packets;
375 unsigned long tx_bytes;
376 unsigned long tx_dropped;
13d64285
LB		 377};
378
379struct mv643xx_eth_private {
380 struct mv643xx_eth_shared_private *shared;
37a6084f 381 void __iomem *base;
fc32b0e2 382 int port_num;
13d64285 383
fc32b0e2 384 struct net_device *dev;
fbd6a754 385
ed94493f 386 struct phy_device *phy;
fbd6a754 387
4ff3495a
LB		 388 struct timer_list mib_counters_timer;
389 spinlock_t mib_counters_lock;
fc32b0e2 390 struct mib_counters mib_counters;
4ff3495a 391
eaf5d590
LB		 392 struct lro_counters lro_counters;
393
fc32b0e2 394 struct work_struct tx_timeout_task;
8a578111 395
1fa38c58 396 struct napi_struct napi;
e0ca8410 397 u32 int_mask;
1319ebad 398 u8 oom;
1fa38c58
LB		 399 u8 work_link;
400 u8 work_tx;
401 u8 work_tx_end;
402 u8 work_rx;
403 u8 work_rx_refill;
1fa38c58 404
2bcb4b0f
LB		 405 int skb_size;
406 struct sk_buff_head rx_recycle;
407
8a578111
LB		 408 /*
409 * RX state.
410 */
e7d2f4db 411 int rx_ring_size;
8a578111
LB		 412 unsigned long rx_desc_sram_addr;
413 int rx_desc_sram_size;
f7981c1c 414 int rxq_count;
2257e05c 415 struct timer_list rx_oom;
64da80a2 416 struct rx_queue rxq[8];
13d64285
LB		 417
418 /*
419 * TX state.
420 */
e7d2f4db 421 int tx_ring_size;
13d64285
LB		 422 unsigned long tx_desc_sram_addr;
423 int tx_desc_sram_size;
f7981c1c 424 int txq_count;
3d6b35bc 425 struct tx_queue txq[8];
fbd6a754 426};
1da177e4 427
fbd6a754 428
c9df406f 429/* port register accessors **************************************************/
e5371493 430static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 431{
cc9754b3 432 return readl(mp->shared->base + offset);
c9df406f 433}
fbd6a754 434
37a6084f
LB		 435static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
436{
437 return readl(mp->base + offset);
438}
439
e5371493 440static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 441{
cc9754b3 442 writel(data, mp->shared->base + offset);
c9df406f 443}
fbd6a754 444
37a6084f
LB		 445static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
446{
447 writel(data, mp->base + offset);
448}
449
fbd6a754 450
c9df406f 451/* rxq/txq helper functions *************************************************/
8a578111 452static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 453{
64da80a2 454 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 455}
fbd6a754 456
13d64285
LB		 457static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
458{
3d6b35bc 459 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 460}
461
8a578111 462static void rxq_enable(struct rx_queue *rxq)
c9df406f 463{
8a578111 464 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 465 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 466}
1da177e4 467
8a578111
LB		 468static void rxq_disable(struct rx_queue *rxq)
469{
470 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 471 u8 mask = 1 << rxq->index;
1da177e4 472
37a6084f
LB		 473 wrlp(mp, RXQ_COMMAND, mask << 8);
474 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 475 udelay(10);
c9df406f
LB		 476}
477
6b368f68
LB		 478static void txq_reset_hw_ptr(struct tx_queue *txq)
479{
480 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 481 u32 addr;
482
483 addr = (u32)txq->tx_desc_dma;
484 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 485 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 486}
487
13d64285 488static void txq_enable(struct tx_queue *txq)
1da177e4 489{
13d64285 490 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 491 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 492}
493
13d64285 494static void txq_disable(struct tx_queue *txq)
1da177e4 495{
13d64285 496 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 497 u8 mask = 1 << txq->index;
c9df406f 498
37a6084f
LB		 499 wrlp(mp, TXQ_COMMAND, mask << 8);
500 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 501 udelay(10);
502}
503
1fa38c58 504static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 505{
506 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 507 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 508
8fd89211
LB		 509 if (netif_tx_queue_stopped(nq)) {
510 __netif_tx_lock(nq, smp_processor_id());
511 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
512 netif_tx_wake_queue(nq);
513 __netif_tx_unlock(nq);
514 }
1da177e4
LT		 515}
516
c9df406f 517
1fa38c58 518/* rx napi ******************************************************************/
eaf5d590
LB		 519static int
520mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
521 u64 *hdr_flags, void *priv)
522{
523 unsigned long cmd_sts = (unsigned long)priv;
524
525 /*
526 * Make sure that this packet is Ethernet II, is not VLAN
527 * tagged, is IPv4, has a valid IP header, and is TCP.
528 */
529 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
530 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
531 RX_PKT_IS_VLAN_TAGGED)) !=
532 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
533 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
534 return -1;
535
536 skb_reset_network_header(skb);
537 skb_set_transport_header(skb, ip_hdrlen(skb));
538 *iphdr = ip_hdr(skb);
539 *tcph = tcp_hdr(skb);
540 *hdr_flags = LRO_IPV4 | LRO_TCP;
541
542 return 0;
543}
eaf5d590 544
8a578111 545static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 546{
8a578111
LB		 547 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
548 struct net_device_stats *stats = &mp->dev->stats;
eaf5d590 549 int lro_flush_needed;
8a578111 550 int rx;
1da177e4 551
eaf5d590 552 lro_flush_needed = 0;
8a578111 553 rx = 0;
9e1f3772 554 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 555 struct rx_desc *rx_desc;
96587661 556 unsigned int cmd_sts;
fc32b0e2 557 struct sk_buff *skb;
6b8f90c2 558 u16 byte_cnt;
ff561eef 559
8a578111 560 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 561
96587661 562 cmd_sts = rx_desc->cmd_sts;
2257e05c 563 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 564 break;
96587661 565 rmb();
1da177e4 566
8a578111
LB		 567 skb = rxq->rx_skb[rxq->rx_curr_desc];
568 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 569
9da78745
LB		 570 rxq->rx_curr_desc++;
571 if (rxq->rx_curr_desc == rxq->rx_ring_size)
572 rxq->rx_curr_desc = 0;
ff561eef 573
3a499481 574 dma_unmap_single(NULL, rx_desc->buf_ptr,
abe78717 575 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 576 rxq->rx_desc_count--;
577 rx++;
b1dd9ca1 578
1fa38c58
LB		 579 mp->work_rx_refill |= 1 << rxq->index;
580
6b8f90c2
LB		 581 byte_cnt = rx_desc->byte_cnt;
582
468d09f8
DF		 583 /*
584 * Update statistics.
fc32b0e2
LB		 585 *
586 * Note that the descriptor byte count includes 2 dummy
587 * bytes automatically inserted by the hardware at the
588 * start of the packet (which we don't count), and a 4
589 * byte CRC at the end of the packet (which we do count).
468d09f8 590 */
1da177e4 591 stats->rx_packets++;
6b8f90c2 592 stats->rx_bytes += byte_cnt - 2;
96587661 593
1da177e4 594 /*
fc32b0e2
LB		 595 * In case we received a packet without first / last bits
596 * on, or the error summary bit is set, the packet needs
597 * to be dropped.
1da177e4 598 */
f61e5547
LB		 599 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
600 != (RX_FIRST_DESC | RX_LAST_DESC))
601 goto err;
602
603 /*
604 * The -4 is for the CRC in the trailer of the
605 * received packet
606 */
607 skb_put(skb, byte_cnt - 2 - 4);
608
609 if (cmd_sts & LAYER_4_CHECKSUM_OK)
610 skb->ip_summed = CHECKSUM_UNNECESSARY;
611 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 612
eaf5d590
LB		 613 if (skb->dev->features & NETIF_F_LRO &&
614 skb->ip_summed == CHECKSUM_UNNECESSARY) {
615 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
616 lro_flush_needed = 1;
617 } else
eaf5d590 618 netif_receive_skb(skb);
f61e5547
LB		 619
620 continue;
621
622err:
623 stats->rx_dropped++;
624
625 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
626 (RX_FIRST_DESC | RX_LAST_DESC)) {
627 if (net_ratelimit())
628 dev_printk(KERN_ERR, &mp->dev->dev,
629 "received packet spanning "
630 "multiple descriptors\n");
1da177e4 631 }
f61e5547
LB		 632
633 if (cmd_sts & ERROR_SUMMARY)
634 stats->rx_errors++;
635
636 dev_kfree_skb(skb);
1da177e4 637 }
fc32b0e2 638
eaf5d590
LB		 639 if (lro_flush_needed)
640 lro_flush_all(&rxq->lro_mgr);
eaf5d590 641
1fa38c58
LB		 642 if (rx < budget)
643 mp->work_rx &= ~(1 << rxq->index);
644
8a578111 645 return rx;
1da177e4
LT		 646}
647
1fa38c58 648static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 649{
1fa38c58 650 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 651 int refilled;
8a578111 652
1fa38c58
LB		 653 refilled = 0;
654 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
655 struct sk_buff *skb;
1fa38c58 656 int rx;
53771522 657 struct rx_desc *rx_desc;
d0412d96 658
2bcb4b0f
LB		 659 skb = __skb_dequeue(&mp->rx_recycle);
660 if (skb == NULL)
7fd96ce4 661 skb = dev_alloc_skb(mp->skb_size);
2bcb4b0f 662
1fa38c58 663 if (skb == NULL) {
1319ebad 664 mp->oom = 1;
1fa38c58
LB		 665 goto oom;
666 }
d0412d96 667
7fd96ce4
LB		 668 if (SKB_DMA_REALIGN)
669 skb_reserve(skb, SKB_DMA_REALIGN);
2257e05c 670
1fa38c58
LB		 671 refilled++;
672 rxq->rx_desc_count++;
c9df406f 673
1fa38c58
LB		 674 rx = rxq->rx_used_desc++;
675 if (rxq->rx_used_desc == rxq->rx_ring_size)
676 rxq->rx_used_desc = 0;
2257e05c 677
53771522
LB		 678 rx_desc = rxq->rx_desc_area + rx;
679
680 rx_desc->buf_ptr = dma_map_single(NULL, skb->data,
681 mp->skb_size, DMA_FROM_DEVICE);
682 rx_desc->buf_size = mp->skb_size;
1fa38c58
LB		 683 rxq->rx_skb[rx] = skb;
684 wmb();
53771522 685 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 686 wmb();
2257e05c 687
1fa38c58
LB		 688 /*
689 * The hardware automatically prepends 2 bytes of
690 * dummy data to each received packet, so that the
691 * IP header ends up 16-byte aligned.
692 */
693 skb_reserve(skb, 2);
694 }
695
696 if (refilled < budget)
697 mp->work_rx_refill &= ~(1 << rxq->index);
698
699oom:
700 return refilled;
d0412d96
JC		 701}
702
c9df406f
LB		 703
704/* tx ***********************************************************************/
c9df406f 705static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 706{
13d64285 707 int frag;
1da177e4 708
c9df406f 709 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 710 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
711 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 712 return 1;
1da177e4 713 }
13d64285 714
c9df406f
LB		 715 return 0;
716}
7303fde8 717
13d64285 718static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 719{
13d64285 720 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 721 int frag;
1da177e4 722
13d64285
LB		 723 for (frag = 0; frag < nr_frags; frag++) {
724 skb_frag_t *this_frag;
725 int tx_index;
726 struct tx_desc *desc;
727
728 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 729 tx_index = txq->tx_curr_desc++;
730 if (txq->tx_curr_desc == txq->tx_ring_size)
731 txq->tx_curr_desc = 0;
13d64285
LB		 732 desc = &txq->tx_desc_area[tx_index];
733
734 /*
735 * The last fragment will generate an interrupt
736 * which will free the skb on TX completion.
737 */
738 if (frag == nr_frags - 1) {
739 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
740 ZERO_PADDING | TX_LAST_DESC |
741 TX_ENABLE_INTERRUPT;
13d64285
LB		 742 } else {
743 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 744 }
745
c9df406f
LB		 746 desc->l4i_chk = 0;
747 desc->byte_cnt = this_frag->size;
748 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
749 this_frag->page_offset,
750 this_frag->size,
751 DMA_TO_DEVICE);
752 }
1da177e4
LT		 753}
754
c9df406f
LB		 755static inline __be16 sum16_as_be(__sum16 sum)
756{
757 return (__force __be16)sum;
758}
1da177e4 759
4df89bd5 760static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 761{
8fa89bf5 762 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 763 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 764 int tx_index;
cc9754b3 765 struct tx_desc *desc;
c9df406f 766 u32 cmd_sts;
4df89bd5 767 u16 l4i_chk;
c9df406f 768 int length;
1da177e4 769
cc9754b3 770 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 771 l4i_chk = 0;
c9df406f
LB		 772
773 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4df89bd5 774 int tag_bytes;
e32b6617
LB		 775
776 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
777 skb->protocol != htons(ETH_P_8021Q));
c9df406f 778
4df89bd5
LB		 779 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
780 if (unlikely(tag_bytes & ~12)) {
781 if (skb_checksum_help(skb) == 0)
782 goto no_csum;
783 kfree_skb(skb);
784 return 1;
785 }
c9df406f 786
4df89bd5 787 if (tag_bytes & 4)
e32b6617 788 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 789 if (tag_bytes & 8)
e32b6617 790 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 791
792 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
793 GEN_IP_V4_CHECKSUM |
794 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 795
c9df406f
LB		 796 switch (ip_hdr(skb)->protocol) {
797 case IPPROTO_UDP:
cc9754b3 798 cmd_sts |= UDP_FRAME;
4df89bd5 799 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 800 break;
801 case IPPROTO_TCP:
4df89bd5 802 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 803 break;
804 default:
805 BUG();
806 }
807 } else {
4df89bd5 808no_csum:
c9df406f 809 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 810 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 811 }
812
66823b92
LB		 813 tx_index = txq->tx_curr_desc++;
814 if (txq->tx_curr_desc == txq->tx_ring_size)
815 txq->tx_curr_desc = 0;
4df89bd5
LB		 816 desc = &txq->tx_desc_area[tx_index];
817
818 if (nr_frags) {
819 txq_submit_frag_skb(txq, skb);
820 length = skb_headlen(skb);
821 } else {
822 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
823 length = skb->len;
824 }
825
826 desc->l4i_chk = l4i_chk;
827 desc->byte_cnt = length;
828 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
829
99ab08e0
LB		 830 __skb_queue_tail(&txq->tx_skb, skb);
831
c9df406f
LB		 832 /* ensure all other descriptors are written before first cmd_sts */
833 wmb();
834 desc->cmd_sts = cmd_sts;
835
1fa38c58
LB		 836 /* clear TX_END status */
837 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 838
c9df406f
LB		 839 /* ensure all descriptors are written before poking hardware */
840 wmb();
13d64285 841 txq_enable(txq);
c9df406f 842
13d64285 843 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 844
845 return 0;
1da177e4 846}
1da177e4 847
fc32b0e2 848static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 849{
e5371493 850 struct mv643xx_eth_private *mp = netdev_priv(dev);
e5ef1de1 851 int queue;
13d64285 852 struct tx_queue *txq;
e5ef1de1 853 struct netdev_queue *nq;
afdb57a2 854
8fd89211
LB		 855 queue = skb_get_queue_mapping(skb);
856 txq = mp->txq + queue;
857 nq = netdev_get_tx_queue(dev, queue);
858
c9df406f 859 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 860 txq->tx_dropped++;
fc32b0e2
LB		 861 dev_printk(KERN_DEBUG, &dev->dev,
862 "failed to linearize skb with tiny "
863 "unaligned fragment\n");
c9df406f
LB		 864 return NETDEV_TX_BUSY;
865 }
866
17cd0a59 867 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1
LB		 868 if (net_ratelimit())
869 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
3d6b35bc
LB		 870 kfree_skb(skb);
871 return NETDEV_TX_OK;
c9df406f
LB		 872 }
873
4df89bd5
LB		 874 if (!txq_submit_skb(txq, skb)) {
875 int entries_left;
876
877 txq->tx_bytes += skb->len;
878 txq->tx_packets++;
879 dev->trans_start = jiffies;
c9df406f 880
4df89bd5
LB		 881 entries_left = txq->tx_ring_size - txq->tx_desc_count;
882 if (entries_left < MAX_SKB_FRAGS + 1)
883 netif_tx_stop_queue(nq);
884 }
c9df406f 885
c9df406f 886 return NETDEV_TX_OK;
1da177e4
LT		 887}
888
c9df406f 889
1fa38c58
LB		 890/* tx napi ******************************************************************/
891static void txq_kick(struct tx_queue *txq)
892{
893 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 894 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 895 u32 hw_desc_ptr;
896 u32 expected_ptr;
897
8fd89211 898 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 899
37a6084f 900 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 901 goto out;
902
37a6084f 903 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 904 expected_ptr = (u32)txq->tx_desc_dma +
905 txq->tx_curr_desc * sizeof(struct tx_desc);
906
907 if (hw_desc_ptr != expected_ptr)
908 txq_enable(txq);
909
910out:
8fd89211 911 __netif_tx_unlock(nq);
1fa38c58
LB		 912
913 mp->work_tx_end &= ~(1 << txq->index);
914}
915
916static int txq_reclaim(struct tx_queue *txq, int budget, int force)
917{
918 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 919 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 920 int reclaimed;
921
8fd89211 922 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 923
924 reclaimed = 0;
925 while (reclaimed < budget && txq->tx_desc_count > 0) {
926 int tx_index;
927 struct tx_desc *desc;
928 u32 cmd_sts;
929 struct sk_buff *skb;
1fa38c58
LB		 930
931 tx_index = txq->tx_used_desc;
932 desc = &txq->tx_desc_area[tx_index];
933 cmd_sts = desc->cmd_sts;
934
935 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
936 if (!force)
937 break;
938 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
939 }
940
941 txq->tx_used_desc = tx_index + 1;
942 if (txq->tx_used_desc == txq->tx_ring_size)
943 txq->tx_used_desc = 0;
944
945 reclaimed++;
946 txq->tx_desc_count--;
947
99ab08e0
LB		 948 skb = NULL;
949 if (cmd_sts & TX_LAST_DESC)
950 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 951
952 if (cmd_sts & ERROR_SUMMARY) {
953 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
954 mp->dev->stats.tx_errors++;
955 }
956
a418950c
LB		 957 if (cmd_sts & TX_FIRST_DESC) {
958 dma_unmap_single(NULL, desc->buf_ptr,
959 desc->byte_cnt, DMA_TO_DEVICE);
960 } else {
961 dma_unmap_page(NULL, desc->buf_ptr,
962 desc->byte_cnt, DMA_TO_DEVICE);
963 }
1fa38c58 964
2bcb4b0f
LB		 965 if (skb != NULL) {
966 if (skb_queue_len(&mp->rx_recycle) <
e7d2f4db 967 mp->rx_ring_size &&
7fd96ce4 968 skb_recycle_check(skb, mp->skb_size))
2bcb4b0f
LB		 969 __skb_queue_head(&mp->rx_recycle, skb);
970 else
971 dev_kfree_skb(skb);
972 }
1fa38c58
LB		 973 }
974
8fd89211
LB		 975 __netif_tx_unlock(nq);
976
1fa38c58
LB		 977 if (reclaimed < budget)
978 mp->work_tx &= ~(1 << txq->index);
979
1fa38c58
LB		 980 return reclaimed;
981}
982
983
89df5fdc
LB		 984/* tx rate control **********************************************************/
985/*
986 * Set total maximum TX rate (shared by all TX queues for this port)
987 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
988 */
989static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
990{
991 int token_rate;
992 int mtu;
993 int bucket_size;
994
995 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
996 if (token_rate > 1023)
997 token_rate = 1023;
998
999 mtu = (mp->dev->mtu + 255) >> 8;
1000 if (mtu > 63)
1001 mtu = 63;
1002
1003 bucket_size = (burst + 255) >> 8;
1004 if (bucket_size > 65535)
1005 bucket_size = 65535;
1006
457b1d5a
LB		 1007 switch (mp->shared->tx_bw_control) {
1008 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 1009 wrlp(mp, TX_BW_RATE, token_rate);
1010 wrlp(mp, TX_BW_MTU, mtu);
1011 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 1012 break;
1013 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 1014 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1015 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1016 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 1017 break;
1e881592 1018 }
89df5fdc
LB		 1019}
1020
1021static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1022{
1023 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1024 int token_rate;
1025 int bucket_size;
1026
1027 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1028 if (token_rate > 1023)
1029 token_rate = 1023;
1030
1031 bucket_size = (burst + 255) >> 8;
1032 if (bucket_size > 65535)
1033 bucket_size = 65535;
1034
37a6084f
LB		 1035 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1036 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 1037}
1038
1039static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1040{
1041 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1042 int off;
1043 u32 val;
1044
1045 /*
1046 * Turn on fixed priority mode.
1047 */
457b1d5a
LB		 1048 off = 0;
1049 switch (mp->shared->tx_bw_control) {
1050 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1051 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1052 break;
1053 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1054 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1055 break;
1056 }
89df5fdc 1057
457b1d5a 1058 if (off) {
37a6084f 1059 val = rdlp(mp, off);
457b1d5a 1060 val |= 1 << txq->index;
37a6084f 1061 wrlp(mp, off, val);
457b1d5a 1062 }
89df5fdc
LB		 1063}
1064
1065static void txq_set_wrr(struct tx_queue *txq, int weight)
1066{
1067 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1068 int off;
1069 u32 val;
1070
1071 /*
1072 * Turn off fixed priority mode.
1073 */
457b1d5a
LB		 1074 off = 0;
1075 switch (mp->shared->tx_bw_control) {
1076 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1077 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1078 break;
1079 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1080 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1081 break;
1082 }
89df5fdc 1083
457b1d5a 1084 if (off) {
37a6084f 1085 val = rdlp(mp, off);
457b1d5a 1086 val &= ~(1 << txq->index);
37a6084f 1087 wrlp(mp, off, val);
89df5fdc 1088
457b1d5a
LB		 1089 /*
1090 * Configure WRR weight for this queue.
1091 */
89df5fdc 1092
37a6084f 1093 val = rdlp(mp, off);
457b1d5a 1094 val = (val & ~0xff) | (weight & 0xff);
37a6084f 1095 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
457b1d5a 1096 }
89df5fdc
LB		 1097}
1098
1099
c9df406f 1100/* mii management interface *************************************************/
45c5d3bc
LB		 1101static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1102{
1103 struct mv643xx_eth_shared_private *msp = dev_id;
1104
1105 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1106 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1107 wake_up(&msp->smi_busy_wait);
1108 return IRQ_HANDLED;
1109 }
1110
1111 return IRQ_NONE;
1112}
c9df406f 1113
45c5d3bc 1114static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1115{
45c5d3bc
LB		 1116 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1117}
1da177e4 1118
45c5d3bc
LB		 1119static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1120{
1121 if (msp->err_interrupt == NO_IRQ) {
1122 int i;
c9df406f 1123
45c5d3bc
LB		 1124 for (i = 0; !smi_is_done(msp); i++) {
1125 if (i == 10)
1126 return -ETIMEDOUT;
1127 msleep(10);
c9df406f 1128 }
45c5d3bc
LB		 1129
1130 return 0;
1131 }
1132
ee04448d
LB		 1133 if (!smi_is_done(msp)) {
1134 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1135 msecs_to_jiffies(100));
1136 if (!smi_is_done(msp))
1137 return -ETIMEDOUT;
1138 }
45c5d3bc
LB		 1139
1140 return 0;
1141}
1142
ed94493f 1143static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1144{
ed94493f 1145 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1146 void __iomem *smi_reg = msp->base + SMI_REG;
1147 int ret;
1148
45c5d3bc 1149 if (smi_wait_ready(msp)) {
10a9948d 1150 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1151 return -ETIMEDOUT;
1da177e4
LT		 1152 }
1153
fc32b0e2 1154 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1155
45c5d3bc 1156 if (smi_wait_ready(msp)) {
10a9948d 1157 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f 1158 return -ETIMEDOUT;
45c5d3bc
LB		 1159 }
1160
1161 ret = readl(smi_reg);
1162 if (!(ret & SMI_READ_VALID)) {
10a9948d 1163 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
ed94493f 1164 return -ENODEV;
c9df406f
LB		 1165 }
1166
ed94493f 1167 return ret & 0xffff;
1da177e4
LT		 1168}
1169
ed94493f 1170static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1171{
ed94493f 1172 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1173 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1174
45c5d3bc 1175 if (smi_wait_ready(msp)) {
10a9948d 1176 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
45c5d3bc 1177 return -ETIMEDOUT;
1da177e4
LT		 1178 }
1179
fc32b0e2 1180 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1181 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1182
ed94493f 1183 if (smi_wait_ready(msp)) {
10a9948d 1184 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
ed94493f
LB		 1185 return -ETIMEDOUT;
1186 }
45c5d3bc
LB		 1187
1188 return 0;
c9df406f 1189}
1da177e4 1190
c9df406f 1191
8fd89211
LB		 1192/* statistics ***************************************************************/
1193static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1194{
1195 struct mv643xx_eth_private *mp = netdev_priv(dev);
1196 struct net_device_stats *stats = &dev->stats;
1197 unsigned long tx_packets = 0;
1198 unsigned long tx_bytes = 0;
1199 unsigned long tx_dropped = 0;
1200 int i;
1201
1202 for (i = 0; i < mp->txq_count; i++) {
1203 struct tx_queue *txq = mp->txq + i;
1204
1205 tx_packets += txq->tx_packets;
1206 tx_bytes += txq->tx_bytes;
1207 tx_dropped += txq->tx_dropped;
1208 }
1209
1210 stats->tx_packets = tx_packets;
1211 stats->tx_bytes = tx_bytes;
1212 stats->tx_dropped = tx_dropped;
1213
1214 return stats;
1215}
1216
eaf5d590
LB		 1217static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1218{
1219 u32 lro_aggregated = 0;
1220 u32 lro_flushed = 0;
1221 u32 lro_no_desc = 0;
1222 int i;
1223
eaf5d590
LB		 1224 for (i = 0; i < mp->rxq_count; i++) {
1225 struct rx_queue *rxq = mp->rxq + i;
1226
1227 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1228 lro_flushed += rxq->lro_mgr.stats.flushed;
1229 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1230 }
eaf5d590
LB		 1231
1232 mp->lro_counters.lro_aggregated = lro_aggregated;
1233 mp->lro_counters.lro_flushed = lro_flushed;
1234 mp->lro_counters.lro_no_desc = lro_no_desc;
1235}
1236
fc32b0e2 1237static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1238{
fc32b0e2 1239 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1240}
1241
fc32b0e2 1242static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1243{
fc32b0e2
LB		 1244 int i;
1245
1246 for (i = 0; i < 0x80; i += 4)
1247 mib_read(mp, i);
c9df406f 1248}
d0412d96 1249
fc32b0e2 1250static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1251{
e5371493 1252 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1253
57e8f26a 1254 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1255 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1256 p->bad_octets_received += mib_read(mp, 0x08);
1257 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1258 p->good_frames_received += mib_read(mp, 0x10);
1259 p->bad_frames_received += mib_read(mp, 0x14);
1260 p->broadcast_frames_received += mib_read(mp, 0x18);
1261 p->multicast_frames_received += mib_read(mp, 0x1c);
1262 p->frames_64_octets += mib_read(mp, 0x20);
1263 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1264 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1265 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1266 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1267 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1268 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1269 p->good_frames_sent += mib_read(mp, 0x40);
1270 p->excessive_collision += mib_read(mp, 0x44);
1271 p->multicast_frames_sent += mib_read(mp, 0x48);
1272 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1273 p->unrec_mac_control_received += mib_read(mp, 0x50);
1274 p->fc_sent += mib_read(mp, 0x54);
1275 p->good_fc_received += mib_read(mp, 0x58);
1276 p->bad_fc_received += mib_read(mp, 0x5c);
1277 p->undersize_received += mib_read(mp, 0x60);
1278 p->fragments_received += mib_read(mp, 0x64);
1279 p->oversize_received += mib_read(mp, 0x68);
1280 p->jabber_received += mib_read(mp, 0x6c);
1281 p->mac_receive_error += mib_read(mp, 0x70);
1282 p->bad_crc_event += mib_read(mp, 0x74);
1283 p->collision += mib_read(mp, 0x78);
1284 p->late_collision += mib_read(mp, 0x7c);
57e8f26a 1285 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1286
1287 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1288}
1289
1290static void mib_counters_timer_wrapper(unsigned long _mp)
1291{
1292 struct mv643xx_eth_private *mp = (void *)_mp;
1293
1294 mib_counters_update(mp);
d0412d96
JC		 1295}
1296
c9df406f 1297
3e508034
LB		 1298/* interrupt coalescing *****************************************************/
1299/*
1300 * Hardware coalescing parameters are set in units of 64 t_clk
1301 * cycles. I.e.:
1302 *
1303 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1304 *
1305 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1306 *
1307 * In the ->set*() methods, we round the computed register value
1308 * to the nearest integer.
1309 */
1310static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1311{
1312 u32 val = rdlp(mp, SDMA_CONFIG);
1313 u64 temp;
1314
1315 if (mp->shared->extended_rx_coal_limit)
1316 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1317 else
1318 temp = (val & 0x003fff00) >> 8;
1319
1320 temp *= 64000000;
1321 do_div(temp, mp->shared->t_clk);
1322
1323 return (unsigned int)temp;
1324}
1325
1326static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1327{
1328 u64 temp;
1329 u32 val;
1330
1331 temp = (u64)usec * mp->shared->t_clk;
1332 temp += 31999999;
1333 do_div(temp, 64000000);
1334
1335 val = rdlp(mp, SDMA_CONFIG);
1336 if (mp->shared->extended_rx_coal_limit) {
1337 if (temp > 0xffff)
1338 temp = 0xffff;
1339 val &= ~0x023fff80;
1340 val |= (temp & 0x8000) << 10;
1341 val |= (temp & 0x7fff) << 7;
1342 } else {
1343 if (temp > 0x3fff)
1344 temp = 0x3fff;
1345 val &= ~0x003fff00;
1346 val |= (temp & 0x3fff) << 8;
1347 }
1348 wrlp(mp, SDMA_CONFIG, val);
1349}
1350
1351static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1352{
1353 u64 temp;
1354
1355 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1356 temp *= 64000000;
1357 do_div(temp, mp->shared->t_clk);
1358
1359 return (unsigned int)temp;
1360}
1361
1362static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1363{
1364 u64 temp;
1365
1366 temp = (u64)usec * mp->shared->t_clk;
1367 temp += 31999999;
1368 do_div(temp, 64000000);
1369
1370 if (temp > 0x3fff)
1371 temp = 0x3fff;
1372
1373 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1374}
1375
1376
c9df406f 1377/* ethtool ******************************************************************/
e5371493 1378struct mv643xx_eth_stats {
c9df406f
LB		 1379 char stat_string[ETH_GSTRING_LEN];
1380 int sizeof_stat;
16820054
LB		 1381 int netdev_off;
1382 int mp_off;
c9df406f
LB		 1383};
1384
16820054
LB		 1385#define SSTAT(m) \
1386 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1387 offsetof(struct net_device, stats.m), -1 }
1388
1389#define MIBSTAT(m) \
1390 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1391 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1392
eaf5d590
LB		 1393#define LROSTAT(m) \
1394 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1395 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1396
16820054
LB		 1397static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1398 SSTAT(rx_packets),
1399 SSTAT(tx_packets),
1400 SSTAT(rx_bytes),
1401 SSTAT(tx_bytes),
1402 SSTAT(rx_errors),
1403 SSTAT(tx_errors),
1404 SSTAT(rx_dropped),
1405 SSTAT(tx_dropped),
1406 MIBSTAT(good_octets_received),
1407 MIBSTAT(bad_octets_received),
1408 MIBSTAT(internal_mac_transmit_err),
1409 MIBSTAT(good_frames_received),
1410 MIBSTAT(bad_frames_received),
1411 MIBSTAT(broadcast_frames_received),
1412 MIBSTAT(multicast_frames_received),
1413 MIBSTAT(frames_64_octets),
1414 MIBSTAT(frames_65_to_127_octets),
1415 MIBSTAT(frames_128_to_255_octets),
1416 MIBSTAT(frames_256_to_511_octets),
1417 MIBSTAT(frames_512_to_1023_octets),
1418 MIBSTAT(frames_1024_to_max_octets),
1419 MIBSTAT(good_octets_sent),
1420 MIBSTAT(good_frames_sent),
1421 MIBSTAT(excessive_collision),
1422 MIBSTAT(multicast_frames_sent),
1423 MIBSTAT(broadcast_frames_sent),
1424 MIBSTAT(unrec_mac_control_received),
1425 MIBSTAT(fc_sent),
1426 MIBSTAT(good_fc_received),
1427 MIBSTAT(bad_fc_received),
1428 MIBSTAT(undersize_received),
1429 MIBSTAT(fragments_received),
1430 MIBSTAT(oversize_received),
1431 MIBSTAT(jabber_received),
1432 MIBSTAT(mac_receive_error),
1433 MIBSTAT(bad_crc_event),
1434 MIBSTAT(collision),
1435 MIBSTAT(late_collision),
eaf5d590
LB		 1436 LROSTAT(lro_aggregated),
1437 LROSTAT(lro_flushed),
1438 LROSTAT(lro_no_desc),
c9df406f
LB		 1439};
1440
10a9948d 1441static int
6bdf576e
LB		 1442mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1443 struct ethtool_cmd *cmd)
d0412d96 1444{
d0412d96
JC		 1445 int err;
1446
ed94493f
LB		 1447 err = phy_read_status(mp->phy);
1448 if (err == 0)
1449 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1450
fc32b0e2
LB		 1451 /*
1452 * The MAC does not support 1000baseT_Half.
1453 */
d0412d96
JC		 1454 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1455 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1456
1457 return err;
1458}
1459
10a9948d 1460static int
6bdf576e 1461mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1462 struct ethtool_cmd *cmd)
bedfe324 1463{
81600eea
LB		 1464 u32 port_status;
1465
37a6084f 1466 port_status = rdlp(mp, PORT_STATUS);
81600eea 1467
bedfe324
LB		 1468 cmd->supported = SUPPORTED_MII;
1469 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1470 switch (port_status & PORT_SPEED_MASK) {
1471 case PORT_SPEED_10:
1472 cmd->speed = SPEED_10;
1473 break;
1474 case PORT_SPEED_100:
1475 cmd->speed = SPEED_100;
1476 break;
1477 case PORT_SPEED_1000:
1478 cmd->speed = SPEED_1000;
1479 break;
1480 default:
1481 cmd->speed = -1;
1482 break;
1483 }
1484 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1485 cmd->port = PORT_MII;
1486 cmd->phy_address = 0;
1487 cmd->transceiver = XCVR_INTERNAL;
1488 cmd->autoneg = AUTONEG_DISABLE;
1489 cmd->maxtxpkt = 1;
1490 cmd->maxrxpkt = 1;
1491
1492 return 0;
1493}
1494
6bdf576e
LB		 1495static int
1496mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1497{
1498 struct mv643xx_eth_private *mp = netdev_priv(dev);
1499
1500 if (mp->phy != NULL)
1501 return mv643xx_eth_get_settings_phy(mp, cmd);
1502 else
1503 return mv643xx_eth_get_settings_phyless(mp, cmd);
1504}
1505
10a9948d
LB		 1506static int
1507mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1508{
e5371493 1509 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1510
6bdf576e
LB		 1511 if (mp->phy == NULL)
1512 return -EINVAL;
1513
fc32b0e2
LB		 1514 /*
1515 * The MAC does not support 1000baseT_Half.
1516 */
1517 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1518
ed94493f 1519 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1520}
1da177e4 1521
fc32b0e2
LB		 1522static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1523 struct ethtool_drvinfo *drvinfo)
c9df406f 1524{
e5371493
LB		 1525 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1526 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1527 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1528 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1529 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1530}
1da177e4 1531
fc32b0e2 1532static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1533{
e5371493 1534 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1535
6bdf576e
LB		 1536 if (mp->phy == NULL)
1537 return -EINVAL;
1da177e4 1538
6bdf576e 1539 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1540}
1541
c9df406f
LB		 1542static u32 mv643xx_eth_get_link(struct net_device *dev)
1543{
ed94493f 1544 return !!netif_carrier_ok(dev);
bedfe324
LB		 1545}
1546
3e508034
LB		 1547static int
1548mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1549{
1550 struct mv643xx_eth_private *mp = netdev_priv(dev);
1551
1552 ec->rx_coalesce_usecs = get_rx_coal(mp);
1553 ec->tx_coalesce_usecs = get_tx_coal(mp);
1554
1555 return 0;
1556}
1557
1558static int
1559mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1560{
1561 struct mv643xx_eth_private *mp = netdev_priv(dev);
1562
1563 set_rx_coal(mp, ec->rx_coalesce_usecs);
1564 set_tx_coal(mp, ec->tx_coalesce_usecs);
1565
1566 return 0;
1567}
1568
e7d2f4db
LB		 1569static void
1570mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1571{
1572 struct mv643xx_eth_private *mp = netdev_priv(dev);
1573
1574 er->rx_max_pending = 4096;
1575 er->tx_max_pending = 4096;
1576 er->rx_mini_max_pending = 0;
1577 er->rx_jumbo_max_pending = 0;
1578
1579 er->rx_pending = mp->rx_ring_size;
1580 er->tx_pending = mp->tx_ring_size;
1581 er->rx_mini_pending = 0;
1582 er->rx_jumbo_pending = 0;
1583}
1584
1585static int
1586mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1587{
1588 struct mv643xx_eth_private *mp = netdev_priv(dev);
1589
1590 if (er->rx_mini_pending || er->rx_jumbo_pending)
1591 return -EINVAL;
1592
1593 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1594 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1595
1596 if (netif_running(dev)) {
1597 mv643xx_eth_stop(dev);
1598 if (mv643xx_eth_open(dev)) {
1599 dev_printk(KERN_ERR, &dev->dev,
1600 "fatal error on re-opening device after "
1601 "ring param change\n");
1602 return -ENOMEM;
1603 }
1604 }
1605
1606 return 0;
1607}
1608
d888b373
LB		 1609static u32
1610mv643xx_eth_get_rx_csum(struct net_device *dev)
1611{
1612 struct mv643xx_eth_private *mp = netdev_priv(dev);
1613
1614 return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
1615}
1616
1617static int
1618mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
1619{
1620 struct mv643xx_eth_private *mp = netdev_priv(dev);
1621
1622 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1623
1624 return 0;
1625}
1626
fc32b0e2
LB		 1627static void mv643xx_eth_get_strings(struct net_device *dev,
1628 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1629{
1630 int i;
1da177e4 1631
fc32b0e2
LB		 1632 if (stringset == ETH_SS_STATS) {
1633 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1634 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1635 mv643xx_eth_stats[i].stat_string,
e5371493 1636 ETH_GSTRING_LEN);
c9df406f 1637 }
c9df406f
LB		 1638 }
1639}
1da177e4 1640
fc32b0e2
LB		 1641static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1642 struct ethtool_stats *stats,
1643 uint64_t *data)
c9df406f 1644{
b9873841 1645 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1646 int i;
1da177e4 1647
8fd89211 1648 mv643xx_eth_get_stats(dev);
fc32b0e2 1649 mib_counters_update(mp);
eaf5d590 1650 mv643xx_eth_grab_lro_stats(mp);
1da177e4 1651
16820054
LB		 1652 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1653 const struct mv643xx_eth_stats *stat;
1654 void *p;
1655
1656 stat = mv643xx_eth_stats + i;
1657
1658 if (stat->netdev_off >= 0)
1659 p = ((void *)mp->dev) + stat->netdev_off;
1660 else
1661 p = ((void *)mp) + stat->mp_off;
1662
1663 data[i] = (stat->sizeof_stat == 8) ?
1664 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1665 }
c9df406f 1666}
1da177e4 1667
fc32b0e2 1668static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1669{
fc32b0e2 1670 if (sset == ETH_SS_STATS)
16820054 1671 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1672
1673 return -EOPNOTSUPP;
c9df406f 1674}
1da177e4 1675
e5371493 1676static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1677 .get_settings = mv643xx_eth_get_settings,
1678 .set_settings = mv643xx_eth_set_settings,
1679 .get_drvinfo = mv643xx_eth_get_drvinfo,
1680 .nway_reset = mv643xx_eth_nway_reset,
1681 .get_link = mv643xx_eth_get_link,
3e508034
LB		 1682 .get_coalesce = mv643xx_eth_get_coalesce,
1683 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1684 .get_ringparam = mv643xx_eth_get_ringparam,
1685 .set_ringparam = mv643xx_eth_set_ringparam,
d888b373
LB		 1686 .get_rx_csum = mv643xx_eth_get_rx_csum,
1687 .set_rx_csum = mv643xx_eth_set_rx_csum,
b8df184f 1688 .set_tx_csum = ethtool_op_set_tx_csum,
c9df406f 1689 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1690 .get_strings = mv643xx_eth_get_strings,
1691 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
eaf5d590
LB		 1692 .get_flags = ethtool_op_get_flags,
1693 .set_flags = ethtool_op_set_flags,
e5371493 1694 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1695};
1da177e4 1696
bea3348e 1697
c9df406f 1698/* address handling *********************************************************/
5daffe94 1699static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1700{
66e63ffb
LB		 1701 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1702 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1703
5daffe94
LB		 1704 addr[0] = (mac_h >> 24) & 0xff;
1705 addr[1] = (mac_h >> 16) & 0xff;
1706 addr[2] = (mac_h >> 8) & 0xff;
1707 addr[3] = mac_h & 0xff;
1708 addr[4] = (mac_l >> 8) & 0xff;
1709 addr[5] = mac_l & 0xff;
c9df406f 1710}
1da177e4 1711
66e63ffb 1712static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1713{
66e63ffb
LB		 1714 wrlp(mp, MAC_ADDR_HIGH,
1715 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1716 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1717}
d0412d96 1718
66e63ffb 1719static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1720{
66e63ffb
LB		 1721 struct dev_addr_list *uc_ptr;
1722 u32 nibbles;
1da177e4 1723
66e63ffb
LB		 1724 if (dev->flags & IFF_PROMISC)
1725 return 0;
1da177e4 1726
66e63ffb
LB		 1727 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1728 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1729 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1730 return 0;
1731 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1732 return 0;
ff561eef 1733
66e63ffb
LB		 1734 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1735 }
1da177e4 1736
66e63ffb 1737 return nibbles;
1da177e4
LT		 1738}
1739
66e63ffb 1740static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1741{
e5371493 1742 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1743 u32 port_config;
1744 u32 nibbles;
1745 int i;
1da177e4 1746
cc9754b3 1747 uc_addr_set(mp, dev->dev_addr);
1da177e4 1748
66e63ffb
LB		 1749 port_config = rdlp(mp, PORT_CONFIG);
1750 nibbles = uc_addr_filter_mask(dev);
1751 if (!nibbles) {
1752 port_config |= UNICAST_PROMISCUOUS_MODE;
1753 wrlp(mp, PORT_CONFIG, port_config);
1754 return;
1755 }
1756
1757 for (i = 0; i < 16; i += 4) {
1758 int off = UNICAST_TABLE(mp->port_num) + i;
1759 u32 v;
1760
1761 v = 0;
1762 if (nibbles & 1)
1763 v |= 0x00000001;
1764 if (nibbles & 2)
1765 v |= 0x00000100;
1766 if (nibbles & 4)
1767 v |= 0x00010000;
1768 if (nibbles & 8)
1769 v |= 0x01000000;
1770 nibbles >>= 4;
1771
1772 wrl(mp, off, v);
1773 }
1774
1775 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1776 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1777}
1778
69876569
LB		 1779static int addr_crc(unsigned char *addr)
1780{
1781 int crc = 0;
1782 int i;
1783
1784 for (i = 0; i < 6; i++) {
1785 int j;
1786
1787 crc = (crc ^ addr[i]) << 8;
1788 for (j = 7; j >= 0; j--) {
1789 if (crc & (0x100 << j))
1790 crc ^= 0x107 << j;
1791 }
1792 }
1793
1794 return crc;
1795}
1796
66e63ffb 1797static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1798{
fc32b0e2 1799 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1800 u32 *mc_spec;
1801 u32 *mc_other;
fc32b0e2
LB		 1802 struct dev_addr_list *addr;
1803 int i;
c8aaea25 1804
fc32b0e2 1805 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1806 int port_num;
1807 u32 accept;
c8aaea25 1808
66e63ffb
LB		 1809oom:
1810 port_num = mp->port_num;
1811 accept = 0x01010101;
fc32b0e2
LB		 1812 for (i = 0; i < 0x100; i += 4) {
1813 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1814 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1815 }
1816 return;
1817 }
c8aaea25 1818
82a5bd6a 1819 mc_spec = kmalloc(0x200, GFP_ATOMIC);
66e63ffb
LB		 1820 if (mc_spec == NULL)
1821 goto oom;
1822 mc_other = mc_spec + (0x100 >> 2);
1823
1824 memset(mc_spec, 0, 0x100);
1825 memset(mc_other, 0, 0x100);
1da177e4 1826
fc32b0e2
LB		 1827 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1828 u8 *a = addr->da_addr;
66e63ffb
LB		 1829 u32 *table;
1830 int entry;
1da177e4 1831
fc32b0e2 1832 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1833 table = mc_spec;
1834 entry = a[5];
fc32b0e2 1835 } else {
66e63ffb
LB		 1836 table = mc_other;
1837 entry = addr_crc(a);
fc32b0e2 1838 }
66e63ffb 1839
2b448334 1840 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1841 }
66e63ffb
LB		 1842
1843 for (i = 0; i < 0x100; i += 4) {
1844 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1845 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1846 }
1847
1848 kfree(mc_spec);
1849}
1850
1851static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1852{
1853 mv643xx_eth_program_unicast_filter(dev);
1854 mv643xx_eth_program_multicast_filter(dev);
1855}
1856
1857static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1858{
1859 struct sockaddr *sa = addr;
1860
1861 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1862
1863 netif_addr_lock_bh(dev);
1864 mv643xx_eth_program_unicast_filter(dev);
1865 netif_addr_unlock_bh(dev);
1866
1867 return 0;
c9df406f 1868}
c8aaea25 1869
c8aaea25 1870
c9df406f 1871/* rx/tx queue initialisation ***********************************************/
64da80a2 1872static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1873{
64da80a2 1874 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1875 struct rx_desc *rx_desc;
1876 int size;
c9df406f
LB		 1877 int i;
1878
64da80a2
LB		 1879 rxq->index = index;
1880
e7d2f4db 1881 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1882
1883 rxq->rx_desc_count = 0;
1884 rxq->rx_curr_desc = 0;
1885 rxq->rx_used_desc = 0;
1886
1887 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1888
f7981c1c 1889 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1890 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1891 mp->rx_desc_sram_size);
1892 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1893 } else {
1894 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1895 &rxq->rx_desc_dma,
1896 GFP_KERNEL);
f7ea3337
PJ		 1897 }
1898
8a578111
LB		 1899 if (rxq->rx_desc_area == NULL) {
1900 dev_printk(KERN_ERR, &mp->dev->dev,
1901 "can't allocate rx ring (%d bytes)\n", size);
1902 goto out;
1903 }
1904 memset(rxq->rx_desc_area, 0, size);
1da177e4 1905
8a578111
LB		 1906 rxq->rx_desc_area_size = size;
1907 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1908 GFP_KERNEL);
1909 if (rxq->rx_skb == NULL) {
1910 dev_printk(KERN_ERR, &mp->dev->dev,
1911 "can't allocate rx skb ring\n");
1912 goto out_free;
1913 }
1914
1915 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1916 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1917 int nexti;
1918
1919 nexti = i + 1;
1920 if (nexti == rxq->rx_ring_size)
1921 nexti = 0;
1922
8a578111
LB		 1923 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1924 nexti * sizeof(struct rx_desc);
1925 }
1926
eaf5d590
LB		 1927 rxq->lro_mgr.dev = mp->dev;
1928 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1929 rxq->lro_mgr.features = LRO_F_NAPI;
1930 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1931 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1932 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1933 rxq->lro_mgr.max_aggr = 32;
1934 rxq->lro_mgr.frag_align_pad = 0;
1935 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1936 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1937
1938 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
eaf5d590 1939
8a578111
LB		 1940 return 0;
1941
1942
1943out_free:
f7981c1c 1944 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1945 iounmap(rxq->rx_desc_area);
1946 else
1947 dma_free_coherent(NULL, size,
1948 rxq->rx_desc_area,
1949 rxq->rx_desc_dma);
1950
1951out:
1952 return -ENOMEM;
c9df406f 1953}
c8aaea25 1954
8a578111 1955static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1956{
8a578111
LB		 1957 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1958 int i;
1959
1960 rxq_disable(rxq);
c8aaea25 1961
8a578111
LB		 1962 for (i = 0; i < rxq->rx_ring_size; i++) {
1963 if (rxq->rx_skb[i]) {
1964 dev_kfree_skb(rxq->rx_skb[i]);
1965 rxq->rx_desc_count--;
1da177e4 1966 }
c8aaea25 1967 }
1da177e4 1968
8a578111
LB		 1969 if (rxq->rx_desc_count) {
1970 dev_printk(KERN_ERR, &mp->dev->dev,
1971 "error freeing rx ring -- %d skbs stuck\n",
1972 rxq->rx_desc_count);
1973 }
1974
f7981c1c 1975 if (rxq->index == 0 &&
64da80a2 1976 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1977 iounmap(rxq->rx_desc_area);
c9df406f 1978 else
8a578111
LB		 1979 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1980 rxq->rx_desc_area, rxq->rx_desc_dma);
1981
1982 kfree(rxq->rx_skb);
c9df406f 1983}
1da177e4 1984
3d6b35bc 1985static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1986{
3d6b35bc 1987 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1988 struct tx_desc *tx_desc;
1989 int size;
c9df406f 1990 int i;
1da177e4 1991
3d6b35bc
LB		 1992 txq->index = index;
1993
e7d2f4db 1994 txq->tx_ring_size = mp->tx_ring_size;
13d64285
LB		 1995
1996 txq->tx_desc_count = 0;
1997 txq->tx_curr_desc = 0;
1998 txq->tx_used_desc = 0;
1999
2000 size = txq->tx_ring_size * sizeof(struct tx_desc);
2001
f7981c1c 2002 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 2003 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2004 mp->tx_desc_sram_size);
2005 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2006 } else {
2007 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
2008 &txq->tx_desc_dma,
2009 GFP_KERNEL);
2010 }
2011
2012 if (txq->tx_desc_area == NULL) {
2013 dev_printk(KERN_ERR, &mp->dev->dev,
2014 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 2015 return -ENOMEM;
c9df406f 2016 }
13d64285
LB		 2017 memset(txq->tx_desc_area, 0, size);
2018
2019 txq->tx_desc_area_size = size;
13d64285
LB		 2020
2021 tx_desc = (struct tx_desc *)txq->tx_desc_area;
2022 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 2023 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 2024 int nexti;
2025
2026 nexti = i + 1;
2027 if (nexti == txq->tx_ring_size)
2028 nexti = 0;
6b368f68
LB		 2029
2030 txd->cmd_sts = 0;
2031 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 2032 nexti * sizeof(struct tx_desc);
2033 }
2034
99ab08e0 2035 skb_queue_head_init(&txq->tx_skb);
c9df406f 2036
99ab08e0 2037 return 0;
c8aaea25 2038}
1da177e4 2039
13d64285 2040static void txq_deinit(struct tx_queue *txq)
c9df406f 2041{
13d64285 2042 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 2043
13d64285 2044 txq_disable(txq);
1fa38c58 2045 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 2046
13d64285 2047 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 2048
f7981c1c 2049 if (txq->index == 0 &&
3d6b35bc 2050 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 2051 iounmap(txq->tx_desc_area);
c9df406f 2052 else
13d64285
LB		 2053 dma_free_coherent(NULL, txq->tx_desc_area_size,
2054 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 2055}
1da177e4 2056
1da177e4 2057
c9df406f 2058/* netdev ops and related ***************************************************/
1fa38c58
LB		 2059static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2060{
2061 u32 int_cause;
2062 u32 int_cause_ext;
2063
e0ca8410 2064 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1fa38c58
LB		 2065 if (int_cause == 0)
2066 return 0;
2067
2068 int_cause_ext = 0;
e0ca8410
SB		 2069 if (int_cause & INT_EXT) {
2070 int_cause &= ~INT_EXT;
37a6084f 2071 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
e0ca8410 2072 }
1fa38c58 2073
1fa38c58 2074 if (int_cause) {
37a6084f 2075 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 2076 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 2077 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 2078 mp->work_rx |= (int_cause & INT_RX) >> 2;
2079 }
2080
2081 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2082 if (int_cause_ext) {
37a6084f 2083 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 2084 if (int_cause_ext & INT_EXT_LINK_PHY)
2085 mp->work_link = 1;
2086 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2087 }
2088
2089 return 1;
2090}
2091
2092static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2093{
2094 struct net_device *dev = (struct net_device *)dev_id;
2095 struct mv643xx_eth_private *mp = netdev_priv(dev);
2096
2097 if (unlikely(!mv643xx_eth_collect_events(mp)))
2098 return IRQ_NONE;
2099
37a6084f 2100 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 2101 napi_schedule(&mp->napi);
2102
2103 return IRQ_HANDLED;
2104}
2105
2f7eb47a
LB		 2106static void handle_link_event(struct mv643xx_eth_private *mp)
2107{
2108 struct net_device *dev = mp->dev;
2109 u32 port_status;
2110 int speed;
2111 int duplex;
2112 int fc;
2113
37a6084f 2114 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 2115 if (!(port_status & LINK_UP)) {
2116 if (netif_carrier_ok(dev)) {
2117 int i;
2118
2119 printk(KERN_INFO "%s: link down\n", dev->name);
2120
2121 netif_carrier_off(dev);
2f7eb47a 2122
f7981c1c 2123 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 2124 struct tx_queue *txq = mp->txq + i;
2125
1fa38c58 2126 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 2127 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 2128 }
2129 }
2130 return;
2131 }
2132
2133 switch (port_status & PORT_SPEED_MASK) {
2134 case PORT_SPEED_10:
2135 speed = 10;
2136 break;
2137 case PORT_SPEED_100:
2138 speed = 100;
2139 break;
2140 case PORT_SPEED_1000:
2141 speed = 1000;
2142 break;
2143 default:
2144 speed = -1;
2145 break;
2146 }
2147 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2148 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2149
2150 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
2151 "flow control %sabled\n", dev->name,
2152 speed, duplex ? "full" : "half",
2153 fc ? "en" : "dis");
2154
4fdeca3f 2155 if (!netif_carrier_ok(dev))
2f7eb47a 2156 netif_carrier_on(dev);
2f7eb47a
LB		 2157}
2158
1fa38c58 2159static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 2160{
1fa38c58
LB		 2161 struct mv643xx_eth_private *mp;
2162 int work_done;
ce4e2e45 2163
1fa38c58 2164 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 2165
1319ebad
LB		 2166 if (unlikely(mp->oom)) {
2167 mp->oom = 0;
2168 del_timer(&mp->rx_oom);
2169 }
1da177e4 2170
1fa38c58
LB		 2171 work_done = 0;
2172 while (work_done < budget) {
2173 u8 queue_mask;
2174 int queue;
2175 int work_tbd;
2176
2177 if (mp->work_link) {
2178 mp->work_link = 0;
2179 handle_link_event(mp);
26ef1f17 2180 work_done++;
1fa38c58
LB		 2181 continue;
2182 }
1da177e4 2183
1319ebad
LB		 2184 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2185 if (likely(!mp->oom))
2186 queue_mask |= mp->work_rx_refill;
2187
1fa38c58
LB		 2188 if (!queue_mask) {
2189 if (mv643xx_eth_collect_events(mp))
2190 continue;
2191 break;
2192 }
1da177e4 2193
1fa38c58
LB		 2194 queue = fls(queue_mask) - 1;
2195 queue_mask = 1 << queue;
2196
2197 work_tbd = budget - work_done;
2198 if (work_tbd > 16)
2199 work_tbd = 16;
2200
2201 if (mp->work_tx_end & queue_mask) {
2202 txq_kick(mp->txq + queue);
2203 } else if (mp->work_tx & queue_mask) {
2204 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2205 txq_maybe_wake(mp->txq + queue);
2206 } else if (mp->work_rx & queue_mask) {
2207 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2208 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2209 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2210 } else {
2211 BUG();
2212 }
84dd619e 2213 }
fc32b0e2 2214
1fa38c58 2215 if (work_done < budget) {
1319ebad 2216 if (mp->oom)
1fa38c58
LB		 2217 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2218 napi_complete(napi);
e0ca8410 2219 wrlp(mp, INT_MASK, mp->int_mask);
226bb6b7 2220 }
3d6b35bc 2221
1fa38c58
LB		 2222 return work_done;
2223}
8fa89bf5 2224
1fa38c58
LB		 2225static inline void oom_timer_wrapper(unsigned long data)
2226{
2227 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2228
1fa38c58 2229 napi_schedule(&mp->napi);
1da177e4
LT		 2230}
2231
e5371493 2232static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 2233{
45c5d3bc
LB		 2234 int data;
2235
ed94493f 2236 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 2237 if (data < 0)
2238 return;
1da177e4 2239
7f106c1d 2240 data |= BMCR_RESET;
ed94493f 2241 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 2242 return;
1da177e4 2243
c9df406f 2244 do {
ed94493f 2245 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 2246 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 2247}
2248
fc32b0e2 2249static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2250{
d0412d96 2251 u32 pscr;
8a578111 2252 int i;
1da177e4 2253
bedfe324
LB		 2254 /*
2255 * Perform PHY reset, if there is a PHY.
2256 */
ed94493f 2257 if (mp->phy != NULL) {
bedfe324
LB		 2258 struct ethtool_cmd cmd;
2259
2260 mv643xx_eth_get_settings(mp->dev, &cmd);
2261 phy_reset(mp);
2262 mv643xx_eth_set_settings(mp->dev, &cmd);
2263 }
1da177e4 2264
81600eea
LB		 2265 /*
2266 * Configure basic link parameters.
2267 */
37a6084f 2268 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2269
2270 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2271 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2272
2273 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2274 if (mp->phy == NULL)
81600eea 2275 pscr |= FORCE_LINK_PASS;
37a6084f 2276 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2277
13d64285
LB		 2278 /*
2279 * Configure TX path and queues.
2280 */
89df5fdc 2281 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2282 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2283 struct tx_queue *txq = mp->txq + i;
13d64285 2284
6b368f68 2285 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2286 txq_set_rate(txq, 1000000000, 16777216);
2287 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2288 }
2289
d9a073ea
LB		 2290 /*
2291 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2292 * frames to RX queue #0, and include the pseudo-header when
2293 * calculating receive checksums.
d9a073ea 2294 */
37a6084f 2295 wrlp(mp, PORT_CONFIG, 0x02000000);
01999873 2296
376489a2
LB		 2297 /*
2298 * Treat BPDUs as normal multicasts, and disable partition mode.
2299 */
37a6084f 2300 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2301
5a893922
LB		 2302 /*
2303 * Add configured unicast addresses to address filter table.
2304 */
2305 mv643xx_eth_program_unicast_filter(mp->dev);
2306
8a578111 2307 /*
64da80a2 2308 * Enable the receive queues.
8a578111 2309 */
f7981c1c 2310 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2311 struct rx_queue *rxq = mp->rxq + i;
8a578111 2312 u32 addr;
1da177e4 2313
8a578111
LB		 2314 addr = (u32)rxq->rx_desc_dma;
2315 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2316 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2317
8a578111
LB		 2318 rxq_enable(rxq);
2319 }
1da177e4
LT		 2320}
2321
2bcb4b0f
LB		 2322static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2323{
2324 int skb_size;
2325
2326 /*
2327 * Reserve 2+14 bytes for an ethernet header (the hardware
2328 * automatically prepends 2 bytes of dummy data to each
2329 * received packet), 16 bytes for up to four VLAN tags, and
2330 * 4 bytes for the trailing FCS -- 36 bytes total.
2331 */
2332 skb_size = mp->dev->mtu + 36;
2333
2334 /*
2335 * Make sure that the skb size is a multiple of 8 bytes, as
2336 * the lower three bits of the receive descriptor's buffer
2337 * size field are ignored by the hardware.
2338 */
2339 mp->skb_size = (skb_size + 7) & ~7;
7fd96ce4
LB		 2340
2341 /*
2342 * If NET_SKB_PAD is smaller than a cache line,
2343 * netdev_alloc_skb() will cause skb->data to be misaligned
2344 * to a cache line boundary. If this is the case, include
2345 * some extra space to allow re-aligning the data area.
2346 */
2347 mp->skb_size += SKB_DMA_REALIGN;
2bcb4b0f
LB		 2348}
2349
c9df406f 2350static int mv643xx_eth_open(struct net_device *dev)
16e03018 2351{
e5371493 2352 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2353 int err;
64da80a2 2354 int i;
16e03018 2355
37a6084f
LB		 2356 wrlp(mp, INT_CAUSE, 0);
2357 wrlp(mp, INT_CAUSE_EXT, 0);
2358 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2359
fc32b0e2 2360 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2361 IRQF_SHARED, dev->name, dev);
c9df406f 2362 if (err) {
fc32b0e2 2363 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 2364 return -EAGAIN;
16e03018
DF		 2365 }
2366
2bcb4b0f
LB		 2367 mv643xx_eth_recalc_skb_size(mp);
2368
2257e05c
LB		 2369 napi_enable(&mp->napi);
2370
2bcb4b0f
LB		 2371 skb_queue_head_init(&mp->rx_recycle);
2372
e0ca8410
SB		 2373 mp->int_mask = INT_EXT;
2374
f7981c1c 2375 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2376 err = rxq_init(mp, i);
2377 if (err) {
2378 while (--i >= 0)
f7981c1c 2379 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2380 goto out;
2381 }
2382
1fa38c58 2383 rxq_refill(mp->rxq + i, INT_MAX);
e0ca8410 2384 mp->int_mask |= INT_RX_0 << i;
2257e05c
LB		 2385 }
2386
1319ebad 2387 if (mp->oom) {
2257e05c
LB		 2388 mp->rx_oom.expires = jiffies + (HZ / 10);
2389 add_timer(&mp->rx_oom);
64da80a2 2390 }
8a578111 2391
f7981c1c 2392 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2393 err = txq_init(mp, i);
2394 if (err) {
2395 while (--i >= 0)
f7981c1c 2396 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2397 goto out_free;
2398 }
e0ca8410 2399 mp->int_mask |= INT_TX_END_0 << i;
3d6b35bc 2400 }
16e03018 2401
fc32b0e2 2402 port_start(mp);
16e03018 2403
37a6084f 2404 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
e0ca8410 2405 wrlp(mp, INT_MASK, mp->int_mask);
16e03018 2406
c9df406f
LB		 2407 return 0;
2408
13d64285 2409
fc32b0e2 2410out_free:
f7981c1c
LB		 2411 for (i = 0; i < mp->rxq_count; i++)
2412 rxq_deinit(mp->rxq + i);
fc32b0e2 2413out:
c9df406f
LB		 2414 free_irq(dev->irq, dev);
2415
2416 return err;
16e03018
DF		 2417}
2418
e5371493 2419static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2420{
fc32b0e2 2421 unsigned int data;
64da80a2 2422 int i;
1da177e4 2423
f7981c1c
LB		 2424 for (i = 0; i < mp->rxq_count; i++)
2425 rxq_disable(mp->rxq + i);
2426 for (i = 0; i < mp->txq_count; i++)
2427 txq_disable(mp->txq + i);
ae9ae064
LB		 2428
2429 while (1) {
37a6084f 2430 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2431
2432 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2433 break;
13d64285 2434 udelay(10);
ae9ae064 2435 }
1da177e4 2436
c9df406f 2437 /* Reset the Enable bit in the Configuration Register */
37a6084f 2438 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2439 data &= ~(SERIAL_PORT_ENABLE |
2440 DO_NOT_FORCE_LINK_FAIL |
2441 FORCE_LINK_PASS);
37a6084f 2442 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2443}
2444
c9df406f 2445static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2446{
e5371493 2447 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2448 int i;
1da177e4 2449
fe65e704 2450 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2451 wrlp(mp, INT_MASK, 0x00000000);
2452 rdlp(mp, INT_MASK);
1da177e4 2453
c9df406f 2454 napi_disable(&mp->napi);
78fff83b 2455
2257e05c
LB		 2456 del_timer_sync(&mp->rx_oom);
2457
c9df406f 2458 netif_carrier_off(dev);
1da177e4 2459
fc32b0e2
LB		 2460 free_irq(dev->irq, dev);
2461
cc9754b3 2462 port_reset(mp);
8fd89211 2463 mv643xx_eth_get_stats(dev);
fc32b0e2 2464 mib_counters_update(mp);
57e8f26a 2465 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2466
2bcb4b0f
LB		 2467 skb_queue_purge(&mp->rx_recycle);
2468
f7981c1c
LB		 2469 for (i = 0; i < mp->rxq_count; i++)
2470 rxq_deinit(mp->rxq + i);
2471 for (i = 0; i < mp->txq_count; i++)
2472 txq_deinit(mp->txq + i);
1da177e4 2473
c9df406f 2474 return 0;
1da177e4
LT		 2475}
2476
fc32b0e2 2477static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2478{
e5371493 2479 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2480
ed94493f
LB		 2481 if (mp->phy != NULL)
2482 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
bedfe324
LB		 2483
2484 return -EOPNOTSUPP;
1da177e4
LT		 2485}
2486
c9df406f 2487static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2488{
89df5fdc
LB		 2489 struct mv643xx_eth_private *mp = netdev_priv(dev);
2490
fc32b0e2 2491 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2492 return -EINVAL;
1da177e4 2493
c9df406f 2494 dev->mtu = new_mtu;
2bcb4b0f 2495 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2496 tx_set_rate(mp, 1000000000, 16777216);
2497
c9df406f
LB		 2498 if (!netif_running(dev))
2499 return 0;
1da177e4 2500
c9df406f
LB		 2501 /*
2502 * Stop and then re-open the interface. This will allocate RX
2503 * skbs of the new MTU.
2504 * There is a possible danger that the open will not succeed,
fc32b0e2 2505 * due to memory being full.
c9df406f
LB		 2506 */
2507 mv643xx_eth_stop(dev);
2508 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2509 dev_printk(KERN_ERR, &dev->dev,
2510 "fatal error on re-opening device after "
2511 "MTU change\n");
c9df406f
LB		 2512 }
2513
2514 return 0;
1da177e4
LT		 2515}
2516
fc32b0e2 2517static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2518{
fc32b0e2 2519 struct mv643xx_eth_private *mp;
1da177e4 2520
fc32b0e2
LB		 2521 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2522 if (netif_running(mp->dev)) {
e5ef1de1 2523 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2524 port_reset(mp);
2525 port_start(mp);
e5ef1de1 2526 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2527 }
c9df406f
LB		 2528}
2529
c9df406f 2530static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2531{
e5371493 2532 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2533
fc32b0e2 2534 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2535
c9df406f 2536 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2537}
2538
c9df406f 2539#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2540static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2541{
fc32b0e2 2542 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2543
37a6084f
LB		 2544 wrlp(mp, INT_MASK, 0x00000000);
2545 rdlp(mp, INT_MASK);
c9df406f 2546
fc32b0e2 2547 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2548
e0ca8410 2549 wrlp(mp, INT_MASK, mp->int_mask);
9f8dd319 2550}
c9df406f 2551#endif
9f8dd319 2552
9f8dd319 2553
c9df406f 2554/* platform glue ************************************************************/
e5371493
LB		 2555static void
2556mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2557 struct mbus_dram_target_info *dram)
c9df406f 2558{
cc9754b3 2559 void __iomem *base = msp->base;
c9df406f
LB		 2560 u32 win_enable;
2561 u32 win_protect;
2562 int i;
9f8dd319 2563
c9df406f
LB		 2564 for (i = 0; i < 6; i++) {
2565 writel(0, base + WINDOW_BASE(i));
2566 writel(0, base + WINDOW_SIZE(i));
2567 if (i < 4)
2568 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2569 }
2570
c9df406f
LB		 2571 win_enable = 0x3f;
2572 win_protect = 0;
2573
2574 for (i = 0; i < dram->num_cs; i++) {
2575 struct mbus_dram_window *cs = dram->cs + i;
2576
2577 writel((cs->base & 0xffff0000) |
2578 (cs->mbus_attr << 8) |
2579 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2580 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2581
2582 win_enable &= ~(1 << i);
2583 win_protect |= 3 << (2 * i);
2584 }
2585
2586 writel(win_enable, base + WINDOW_BAR_ENABLE);
2587 msp->win_protect = win_protect;
9f8dd319
DF		 2588}
2589
773fc3ee
LB		 2590static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2591{
2592 /*
2593 * Check whether we have a 14-bit coal limit field in bits
2594 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2595 * SDMA config register.
2596 */
37a6084f
LB		 2597 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2598 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2599 msp->extended_rx_coal_limit = 1;
2600 else
2601 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2602
2603 /*
457b1d5a
LB		 2604 * Check whether the MAC supports TX rate control, and if
2605 * yes, whether its associated registers are in the old or
2606 * the new place.
1e881592 2607 */
37a6084f
LB		 2608 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2609 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2610 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2611 } else {
37a6084f
LB		 2612 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2613 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2614 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2615 else
2616 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2617 }
773fc3ee
LB		 2618}
2619
c9df406f 2620static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2621{
10a9948d 2622 static int mv643xx_eth_version_printed;
c9df406f 2623 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2624 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2625 struct resource *res;
2626 int ret;
9f8dd319 2627
e5371493 2628 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2629 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2630 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2631
c9df406f
LB		 2632 ret = -EINVAL;
2633 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2634 if (res == NULL)
2635 goto out;
9f8dd319 2636
c9df406f
LB		 2637 ret = -ENOMEM;
2638 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2639 if (msp == NULL)
2640 goto out;
2641 memset(msp, 0, sizeof(*msp));
2642
cc9754b3
LB		 2643 msp->base = ioremap(res->start, res->end - res->start + 1);
2644 if (msp->base == NULL)
c9df406f
LB		 2645 goto out_free;
2646
ed94493f
LB		 2647 /*
2648 * Set up and register SMI bus.
2649 */
2650 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2651 msp->smi_bus = mdiobus_alloc();
2652 if (msp->smi_bus == NULL)
ed94493f 2653 goto out_unmap;
298cf9be
LB		 2654
2655 msp->smi_bus->priv = msp;
2656 msp->smi_bus->name = "mv643xx_eth smi";
2657 msp->smi_bus->read = smi_bus_read;
2658 msp->smi_bus->write = smi_bus_write,
2659 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2660 msp->smi_bus->parent = &pdev->dev;
2661 msp->smi_bus->phy_mask = 0xffffffff;
2662 if (mdiobus_register(msp->smi_bus) < 0)
2663 goto out_free_mii_bus;
ed94493f
LB		 2664 msp->smi = msp;
2665 } else {
fc0eb9f2 2666 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2667 }
c9df406f 2668
45c5d3bc
LB		 2669 msp->err_interrupt = NO_IRQ;
2670 init_waitqueue_head(&msp->smi_busy_wait);
2671
2672 /*
2673 * Check whether the error interrupt is hooked up.
2674 */
2675 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2676 if (res != NULL) {
2677 int err;
2678
2679 err = request_irq(res->start, mv643xx_eth_err_irq,
2680 IRQF_SHARED, "mv643xx_eth", msp);
2681 if (!err) {
2682 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2683 msp->err_interrupt = res->start;
2684 }
2685 }
2686
c9df406f
LB		 2687 /*
2688 * (Re-)program MBUS remapping windows if we are asked to.
2689 */
2690 if (pd != NULL && pd->dram != NULL)
2691 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2692
fc32b0e2
LB		 2693 /*
2694 * Detect hardware parameters.
2695 */
2696 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2697 infer_hw_params(msp);
fc32b0e2
LB		 2698
2699 platform_set_drvdata(pdev, msp);
2700
c9df406f
LB		 2701 return 0;
2702
298cf9be
LB		 2703out_free_mii_bus:
2704 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2705out_unmap:
2706 iounmap(msp->base);
c9df406f
LB		 2707out_free:
2708 kfree(msp);
2709out:
2710 return ret;
2711}
2712
2713static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2714{
e5371493 2715 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2716 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2717
298cf9be 2718 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2719 mdiobus_unregister(msp->smi_bus);
bcb3336c 2720 mdiobus_free(msp->smi_bus);
298cf9be 2721 }
45c5d3bc
LB		 2722 if (msp->err_interrupt != NO_IRQ)
2723 free_irq(msp->err_interrupt, msp);
cc9754b3 2724 iounmap(msp->base);
c9df406f
LB		 2725 kfree(msp);
2726
2727 return 0;
9f8dd319
DF		 2728}
2729
c9df406f 2730static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2731 .probe = mv643xx_eth_shared_probe,
2732 .remove = mv643xx_eth_shared_remove,
c9df406f 2733 .driver = {
fc32b0e2 2734 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2735 .owner = THIS_MODULE,
2736 },
2737};
2738
e5371493 2739static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2740{
c9df406f 2741 int addr_shift = 5 * mp->port_num;
fc32b0e2 2742 u32 data;
1da177e4 2743
fc32b0e2
LB		 2744 data = rdl(mp, PHY_ADDR);
2745 data &= ~(0x1f << addr_shift);
2746 data |= (phy_addr & 0x1f) << addr_shift;
2747 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2748}
2749
e5371493 2750static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2751{
fc32b0e2
LB		 2752 unsigned int data;
2753
2754 data = rdl(mp, PHY_ADDR);
2755
2756 return (data >> (5 * mp->port_num)) & 0x1f;
2757}
2758
2759static void set_params(struct mv643xx_eth_private *mp,
2760 struct mv643xx_eth_platform_data *pd)
2761{
2762 struct net_device *dev = mp->dev;
2763
2764 if (is_valid_ether_addr(pd->mac_addr))
2765 memcpy(dev->dev_addr, pd->mac_addr, 6);
2766 else
2767 uc_addr_get(mp, dev->dev_addr);
2768
e7d2f4db 2769 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2770 if (pd->rx_queue_size)
e7d2f4db 2771 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2772 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2773 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2774
f7981c1c 2775 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2776
e7d2f4db 2777 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2778 if (pd->tx_queue_size)
e7d2f4db 2779 mp->tx_ring_size = pd->tx_queue_size;
fc32b0e2
LB		 2780 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2781 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2782
f7981c1c 2783 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2784}
2785
ed94493f
LB		 2786static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2787 int phy_addr)
1da177e4 2788{
298cf9be 2789 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2790 struct phy_device *phydev;
2791 int start;
2792 int num;
2793 int i;
45c5d3bc 2794
ed94493f
LB		 2795 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2796 start = phy_addr_get(mp) & 0x1f;
2797 num = 32;
2798 } else {
2799 start = phy_addr & 0x1f;
2800 num = 1;
2801 }
45c5d3bc 2802
ed94493f
LB		 2803 phydev = NULL;
2804 for (i = 0; i < num; i++) {
2805 int addr = (start + i) & 0x1f;
fc32b0e2 2806
ed94493f
LB		 2807 if (bus->phy_map[addr] == NULL)
2808 mdiobus_scan(bus, addr);
1da177e4 2809
ed94493f
LB		 2810 if (phydev == NULL) {
2811 phydev = bus->phy_map[addr];
2812 if (phydev != NULL)
2813 phy_addr_set(mp, addr);
2814 }
2815 }
1da177e4 2816
ed94493f 2817 return phydev;
1da177e4
LT		 2818}
2819
ed94493f 2820static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2821{
ed94493f 2822 struct phy_device *phy = mp->phy;
c28a4f89 2823
fc32b0e2
LB		 2824 phy_reset(mp);
2825
db1d7bf7 2826 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
ed94493f
LB		 2827
2828 if (speed == 0) {
2829 phy->autoneg = AUTONEG_ENABLE;
2830 phy->speed = 0;
2831 phy->duplex = 0;
2832 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2833 } else {
ed94493f
LB		 2834 phy->autoneg = AUTONEG_DISABLE;
2835 phy->advertising = 0;
2836 phy->speed = speed;
2837 phy->duplex = duplex;
c9df406f 2838 }
ed94493f 2839 phy_start_aneg(phy);
c28a4f89
JC		 2840}
2841
81600eea
LB		 2842static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2843{
2844 u32 pscr;
2845
37a6084f 2846 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2847 if (pscr & SERIAL_PORT_ENABLE) {
2848 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2849 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2850 }
2851
2852 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2853 if (mp->phy == NULL) {
81600eea
LB		 2854 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2855 if (speed == SPEED_1000)
2856 pscr |= SET_GMII_SPEED_TO_1000;
2857 else if (speed == SPEED_100)
2858 pscr |= SET_MII_SPEED_TO_100;
2859
2860 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2861
2862 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2863 if (duplex == DUPLEX_FULL)
2864 pscr |= SET_FULL_DUPLEX_MODE;
2865 }
2866
37a6084f 2867 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2868}
2869
ea8a8642
LB		 2870static const struct net_device_ops mv643xx_eth_netdev_ops = {
2871 .ndo_open = mv643xx_eth_open,
2872 .ndo_stop = mv643xx_eth_stop,
2873 .ndo_start_xmit = mv643xx_eth_xmit,
2874 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2875 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2876 .ndo_do_ioctl = mv643xx_eth_ioctl,
2877 .ndo_change_mtu = mv643xx_eth_change_mtu,
2878 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2879 .ndo_get_stats = mv643xx_eth_get_stats,
2880#ifdef CONFIG_NET_POLL_CONTROLLER
2881 .ndo_poll_controller = mv643xx_eth_netpoll,
2882#endif
2883};
2884
c9df406f 2885static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2886{
c9df406f 2887 struct mv643xx_eth_platform_data *pd;
e5371493 2888 struct mv643xx_eth_private *mp;
c9df406f 2889 struct net_device *dev;
c9df406f 2890 struct resource *res;
fc32b0e2 2891 int err;
1da177e4 2892
c9df406f
LB		 2893 pd = pdev->dev.platform_data;
2894 if (pd == NULL) {
fc32b0e2
LB		 2895 dev_printk(KERN_ERR, &pdev->dev,
2896 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2897 return -ENODEV;
2898 }
1da177e4 2899
c9df406f 2900 if (pd->shared == NULL) {
fc32b0e2
LB		 2901 dev_printk(KERN_ERR, &pdev->dev,
2902 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2903 return -ENODEV;
2904 }
8f518703 2905
e5ef1de1 2906 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2907 if (!dev)
2908 return -ENOMEM;
1da177e4 2909
c9df406f 2910 mp = netdev_priv(dev);
fc32b0e2
LB		 2911 platform_set_drvdata(pdev, mp);
2912
2913 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2914 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2915 mp->port_num = pd->port_number;
2916
c9df406f 2917 mp->dev = dev;
78fff83b 2918
fc32b0e2 2919 set_params(mp, pd);
e5ef1de1 2920 dev->real_num_tx_queues = mp->txq_count;
fc32b0e2 2921
ed94493f
LB		 2922 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2923 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2924
6bdf576e 2925 if (mp->phy != NULL)
ed94493f 2926 phy_init(mp, pd->speed, pd->duplex);
6bdf576e
LB		 2927
2928 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2929
81600eea 2930 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2931
4ff3495a
LB		 2932
2933 mib_counters_clear(mp);
2934
2935 init_timer(&mp->mib_counters_timer);
2936 mp->mib_counters_timer.data = (unsigned long)mp;
2937 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2938 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2939 add_timer(&mp->mib_counters_timer);
2940
2941 spin_lock_init(&mp->mib_counters_lock);
2942
2943 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2944
2257e05c
LB		 2945 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2946
2947 init_timer(&mp->rx_oom);
2948 mp->rx_oom.data = (unsigned long)mp;
2949 mp->rx_oom.function = oom_timer_wrapper;
2950
fc32b0e2 2951
c9df406f
LB		 2952 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2953 BUG_ON(!res);
2954 dev->irq = res->start;
1da177e4 2955
ea8a8642
LB		 2956 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2957
c9df406f
LB		 2958 dev->watchdog_timeo = 2 * HZ;
2959 dev->base_addr = 0;
1da177e4 2960
c9df406f 2961 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
e32b6617 2962 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2963
fc32b0e2 2964 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2965
c9df406f 2966 if (mp->shared->win_protect)
fc32b0e2 2967 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2968
a5fe3616
LB		 2969 netif_carrier_off(dev);
2970
b5e86db4
LB		 2971 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2972
4fb0a54a 2973 set_rx_coal(mp, 250);
a5fe3616
LB		 2974 set_tx_coal(mp, 0);
2975
c9df406f
LB		 2976 err = register_netdev(dev);
2977 if (err)
2978 goto out;
1da177e4 2979
e174961c
JB		 2980 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2981 mp->port_num, dev->dev_addr);
1da177e4 2982
13d64285 2983 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2984 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2985
c9df406f 2986 return 0;
1da177e4 2987
c9df406f
LB		 2988out:
2989 free_netdev(dev);
1da177e4 2990
c9df406f 2991 return err;
1da177e4
LT		 2992}
2993
c9df406f 2994static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2995{
fc32b0e2 2996 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2997
fc32b0e2 2998 unregister_netdev(mp->dev);
ed94493f
LB		 2999 if (mp->phy != NULL)
3000 phy_detach(mp->phy);
c9df406f 3001 flush_scheduled_work();
fc32b0e2 3002 free_netdev(mp->dev);
c9df406f 3003
c9df406f 3004 platform_set_drvdata(pdev, NULL);
fc32b0e2 3005
c9df406f 3006 return 0;
1da177e4
LT		 3007}
3008
c9df406f 3009static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 3010{
fc32b0e2 3011 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 3012
c9df406f 3013 /* Mask all interrupts on ethernet port */
37a6084f
LB		 3014 wrlp(mp, INT_MASK, 0);
3015 rdlp(mp, INT_MASK);
c9df406f 3016
fc32b0e2
LB		 3017 if (netif_running(mp->dev))
3018 port_reset(mp);
d0412d96
JC		 3019}
3020
c9df406f 3021static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 3022 .probe = mv643xx_eth_probe,
3023 .remove = mv643xx_eth_remove,
3024 .shutdown = mv643xx_eth_shutdown,
c9df406f 3025 .driver = {
fc32b0e2 3026 .name = MV643XX_ETH_NAME,
c9df406f
LB		 3027 .owner = THIS_MODULE,
3028 },
3029};
3030
e5371493 3031static int __init mv643xx_eth_init_module(void)
d0412d96 3032{
c9df406f 3033 int rc;
d0412d96 3034
c9df406f
LB		 3035 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3036 if (!rc) {
3037 rc = platform_driver_register(&mv643xx_eth_driver);
3038 if (rc)
3039 platform_driver_unregister(&mv643xx_eth_shared_driver);
3040 }
fc32b0e2 3041
c9df406f 3042 return rc;
d0412d96 3043}
fc32b0e2 3044module_init(mv643xx_eth_init_module);
d0412d96 3045
e5371493 3046static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 3047{
c9df406f
LB		 3048 platform_driver_unregister(&mv643xx_eth_driver);
3049 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 3050}
e5371493 3051module_exit(mv643xx_eth_cleanup_module);
1da177e4 3052
45675bc6
LB		 3053MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3054 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 3055MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 3056MODULE_LICENSE("GPL");
c9df406f 3057MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 3058MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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