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[PATCH] vmsplice: restrict stealing a little more
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 9 * written by Manish Lachwani
1da177e4
LT		 10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
c8aaea25 13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
b6298c22
AV		 35#include <linux/in.h>
36#include <linux/ip.h>
1da177e4
LT		 37#include <linux/tcp.h>
38#include <linux/udp.h>
39#include <linux/etherdevice.h>
40
41#include <linux/bitops.h>
42#include <linux/delay.h>
43#include <linux/ethtool.h>
d052d1be
RK		 44#include <linux/platform_device.h>
45
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/types.h>
48#include <asm/pgtable.h>
49#include <asm/system.h>
50#include <asm/delay.h>
51#include "mv643xx_eth.h"
52
1da177e4 53/* Static function declarations */
1da177e4
LT		 54static void eth_port_uc_addr_get(struct net_device *dev,
55 unsigned char *MacAddr);
16e03018 56static void eth_port_set_multicast_list(struct net_device *);
9f8dd319 57static void mv643xx_eth_port_enable_tx(unsigned int port_num,
12a87c64 58 unsigned int queues);
9f8dd319 59static void mv643xx_eth_port_enable_rx(unsigned int port_num,
12a87c64 60 unsigned int queues);
9f8dd319
DF		 61static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
62static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
ab4384a6
DF		 63static int mv643xx_eth_open(struct net_device *);
64static int mv643xx_eth_stop(struct net_device *);
1da177e4
LT		 65static int mv643xx_eth_change_mtu(struct net_device *, int);
66static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
67static void eth_port_init_mac_tables(unsigned int eth_port_num);
68#ifdef MV643XX_NAPI
69static int mv643xx_poll(struct net_device *dev, int *budget);
70#endif
c28a4f89 71static int ethernet_phy_get(unsigned int eth_port_num);
1da177e4
LT		 72static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
73static int ethernet_phy_detect(unsigned int eth_port_num);
c28a4f89
JC		 74static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
75static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
d0412d96 76static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
1da177e4
LT		 77static struct ethtool_ops mv643xx_ethtool_ops;
78
79static char mv643xx_driver_name[] = "mv643xx_eth";
80static char mv643xx_driver_version[] = "1.0";
81
82static void __iomem *mv643xx_eth_shared_base;
83
84/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
a9f6a0dd 85static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
1da177e4
LT		 86
87static inline u32 mv_read(int offset)
88{
dc074a8a 89 void __iomem *reg_base;
1da177e4
LT		 90
91 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
92
93 return readl(reg_base + offset);
94}
95
96static inline void mv_write(int offset, u32 data)
97{
dc074a8a 98 void __iomem *reg_base;
1da177e4
LT		 99
100 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
101 writel(data, reg_base + offset);
102}
103
104/*
105 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
106 *
107 * Input : pointer to ethernet interface network device structure
108 * new mtu size
109 * Output : 0 upon success, -EINVAL upon failure
110 */
111static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
112{
8f518703 113 if ((new_mtu > 9500) || (new_mtu < 64))
1da177e4 114 return -EINVAL;
1da177e4
LT		 115
116 dev->mtu = new_mtu;
117 /*
118 * Stop then re-open the interface. This will allocate RX skb's with
119 * the new MTU.
120 * There is a possible danger that the open will not successed, due
121 * to memory is full, which might fail the open function.
122 */
123 if (netif_running(dev)) {
ab4384a6
DF		 124 mv643xx_eth_stop(dev);
125 if (mv643xx_eth_open(dev))
1da177e4
LT		 126 printk(KERN_ERR
127 "%s: Fatal error on opening device\n",
128 dev->name);
129 }
130
1da177e4
LT		 131 return 0;
132}
133
134/*
f78fb474 135 * mv643xx_eth_rx_refill_descs
1da177e4
LT		 136 *
137 * Fills / refills RX queue on a certain gigabit ethernet port
138 *
139 * Input : pointer to ethernet interface network device structure
140 * Output : N/A
141 */
f78fb474 142static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
1da177e4 143{
1da177e4
LT		 144 struct mv643xx_private *mp = netdev_priv(dev);
145 struct pkt_info pkt_info;
146 struct sk_buff *skb;
b44cd572 147 int unaligned;
1da177e4 148
f78fb474 149 while (mp->rx_desc_count < mp->rx_ring_size) {
7303fde8 150 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + ETH_DMA_ALIGN);
1da177e4
LT		 151 if (!skb)
152 break;
f98e36f1 153 mp->rx_desc_count++;
7303fde8 154 unaligned = (u32)skb->data & (ETH_DMA_ALIGN - 1);
b44cd572 155 if (unaligned)
7303fde8 156 skb_reserve(skb, ETH_DMA_ALIGN - unaligned);
1da177e4 157 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
7303fde8
DF		 158 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
159 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
160 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
1da177e4
LT		 161 pkt_info.return_info = skb;
162 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
163 printk(KERN_ERR
164 "%s: Error allocating RX Ring\n", dev->name);
165 break;
166 }
7303fde8 167 skb_reserve(skb, ETH_HW_IP_ALIGN);
1da177e4 168 }
1da177e4
LT		 169 /*
170 * If RX ring is empty of SKB, set a timer to try allocating
f78fb474 171 * again at a later time.
1da177e4 172 */
f78fb474 173 if (mp->rx_desc_count == 0) {
1da177e4 174 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
f78fb474 175 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
1da177e4 176 add_timer(&mp->timeout);
1da177e4 177 }
1da177e4
LT		 178}
179
180/*
f78fb474 181 * mv643xx_eth_rx_refill_descs_timer_wrapper
1da177e4
LT		 182 *
183 * Timer routine to wake up RX queue filling task. This function is
184 * used only in case the RX queue is empty, and all alloc_skb has
185 * failed (due to out of memory event).
186 *
187 * Input : pointer to ethernet interface network device structure
188 * Output : N/A
189 */
f78fb474 190static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
1da177e4 191{
f78fb474 192 mv643xx_eth_rx_refill_descs((struct net_device *)data);
1da177e4
LT		 193}
194
195/*
196 * mv643xx_eth_update_mac_address
197 *
198 * Update the MAC address of the port in the address table
199 *
200 * Input : pointer to ethernet interface network device structure
201 * Output : N/A
202 */
203static void mv643xx_eth_update_mac_address(struct net_device *dev)
204{
205 struct mv643xx_private *mp = netdev_priv(dev);
206 unsigned int port_num = mp->port_num;
207
208 eth_port_init_mac_tables(port_num);
ed9b5d45 209 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 210}
211
212/*
213 * mv643xx_eth_set_rx_mode
214 *
215 * Change from promiscuos to regular rx mode
216 *
217 * Input : pointer to ethernet interface network device structure
218 * Output : N/A
219 */
220static void mv643xx_eth_set_rx_mode(struct net_device *dev)
221{
222 struct mv643xx_private *mp = netdev_priv(dev);
01999873 223 u32 config_reg;
1da177e4 224
01999873 225 config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num));
1da177e4 226 if (dev->flags & IFF_PROMISC)
01999873 227 config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
1da177e4 228 else
01999873
DF		 229 config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
230 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg);
16e03018
DF		 231
232 eth_port_set_multicast_list(dev);
1da177e4
LT		 233}
234
235/*
236 * mv643xx_eth_set_mac_address
237 *
238 * Change the interface's mac address.
239 * No special hardware thing should be done because interface is always
240 * put in promiscuous mode.
241 *
242 * Input : pointer to ethernet interface network device structure and
243 * a pointer to the designated entry to be added to the cache.
244 * Output : zero upon success, negative upon failure
245 */
246static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
247{
248 int i;
249
250 for (i = 0; i < 6; i++)
251 /* +2 is for the offset of the HW addr type */
252 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
253 mv643xx_eth_update_mac_address(dev);
254 return 0;
255}
256
257/*
258 * mv643xx_eth_tx_timeout
259 *
260 * Called upon a timeout on transmitting a packet
261 *
262 * Input : pointer to ethernet interface network device structure.
263 * Output : N/A
264 */
265static void mv643xx_eth_tx_timeout(struct net_device *dev)
266{
267 struct mv643xx_private *mp = netdev_priv(dev);
268
269 printk(KERN_INFO "%s: TX timeout ", dev->name);
270
271 /* Do the reset outside of interrupt context */
272 schedule_work(&mp->tx_timeout_task);
273}
274
275/*
276 * mv643xx_eth_tx_timeout_task
277 *
278 * Actual routine to reset the adapter when a timeout on Tx has occurred
279 */
280static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
281{
282 struct mv643xx_private *mp = netdev_priv(dev);
283
94843566
DF		 284 if (!netif_running(dev))
285 return;
286
287 netif_stop_queue(dev);
288
1da177e4 289 eth_port_reset(mp->port_num);
ed9b5d45 290 eth_port_start(dev);
94843566
DF		 291
292 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
293 netif_wake_queue(dev);
1da177e4
LT		 294}
295
ff561eef
DF		 296/**
297 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
1da177e4 298 *
ff561eef 299 * If force is non-zero, frees uncompleted descriptors as well
1da177e4 300 */
ff561eef 301int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1da177e4
LT		 302{
303 struct mv643xx_private *mp = netdev_priv(dev);
ff561eef
DF		 304 struct eth_tx_desc *desc;
305 u32 cmd_sts;
306 struct sk_buff *skb;
307 unsigned long flags;
308 int tx_index;
309 dma_addr_t addr;
310 int count;
311 int released = 0;
1da177e4 312
ff561eef
DF		 313 while (mp->tx_desc_count > 0) {
314 spin_lock_irqsave(&mp->lock, flags);
315 tx_index = mp->tx_used_desc_q;
316 desc = &mp->p_tx_desc_area[tx_index];
317 cmd_sts = desc->cmd_sts;
318
319 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
320 spin_unlock_irqrestore(&mp->lock, flags);
321 return released;
322 }
323
324 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
325 mp->tx_desc_count--;
326
327 addr = desc->buf_ptr;
328 count = desc->byte_cnt;
329 skb = mp->tx_skb[tx_index];
330 if (skb)
331 mp->tx_skb[tx_index] = NULL;
332
333 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 334
7303fde8 335 if (cmd_sts & ETH_ERROR_SUMMARY) {
1da177e4 336 printk("%s: Error in TX\n", dev->name);
ff561eef 337 mp->stats.tx_errors++;
1da177e4
LT		 338 }
339
ff561eef
DF		 340 if (cmd_sts & ETH_TX_FIRST_DESC)
341 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
cb415d30 342 else
ff561eef 343 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1da177e4 344
ff561eef
DF		 345 if (skb)
346 dev_kfree_skb_irq(skb);
347
348 released = 1;
1da177e4
LT		 349 }
350
1da177e4
LT		 351 return released;
352}
353
ff561eef
DF		 354static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
355{
356 struct mv643xx_private *mp = netdev_priv(dev);
357
358 if (mv643xx_eth_free_tx_descs(dev, 0) &&
359 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
360 netif_wake_queue(dev);
361}
362
363static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
364{
365 mv643xx_eth_free_tx_descs(dev, 1);
366}
367
1da177e4
LT		 368/*
369 * mv643xx_eth_receive
370 *
371 * This function is forward packets that are received from the port's
372 * queues toward kernel core or FastRoute them to another interface.
373 *
374 * Input : dev - a pointer to the required interface
375 * max - maximum number to receive (0 means unlimted)
376 *
377 * Output : number of served packets
378 */
1da177e4 379static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
1da177e4
LT		 380{
381 struct mv643xx_private *mp = netdev_priv(dev);
382 struct net_device_stats *stats = &mp->stats;
383 unsigned int received_packets = 0;
384 struct sk_buff *skb;
385 struct pkt_info pkt_info;
386
b1dd9ca1 387 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
f98e36f1 388 mp->rx_desc_count--;
1da177e4 389 received_packets++;
b1dd9ca1 390
468d09f8
DF		 391 /*
392 * Update statistics.
393 * Note byte count includes 4 byte CRC count
394 */
1da177e4
LT		 395 stats->rx_packets++;
396 stats->rx_bytes += pkt_info.byte_cnt;
397 skb = pkt_info.return_info;
398 /*
399 * In case received a packet without first / last bits on OR
400 * the error summary bit is on, the packets needs to be dropeed.
401 */
402 if (((pkt_info.cmd_sts
403 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
404 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
405 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
406 stats->rx_dropped++;
407 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
408 ETH_RX_LAST_DESC)) !=
409 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
410 if (net_ratelimit())
411 printk(KERN_ERR
412 "%s: Received packet spread "
413 "on multiple descriptors\n",
414 dev->name);
415 }
416 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
417 stats->rx_errors++;
418
419 dev_kfree_skb_irq(skb);
420 } else {
421 /*
422 * The -4 is for the CRC in the trailer of the
423 * received packet
424 */
425 skb_put(skb, pkt_info.byte_cnt - 4);
426 skb->dev = dev;
427
428 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
429 skb->ip_summed = CHECKSUM_UNNECESSARY;
430 skb->csum = htons(
431 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
432 }
433 skb->protocol = eth_type_trans(skb, dev);
434#ifdef MV643XX_NAPI
435 netif_receive_skb(skb);
436#else
437 netif_rx(skb);
438#endif
439 }
12ad74f8 440 dev->last_rx = jiffies;
1da177e4 441 }
f78fb474 442 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1da177e4
LT		 443
444 return received_packets;
445}
446
d0412d96
JC		 447/* Set the mv643xx port configuration register for the speed/duplex mode. */
448static void mv643xx_eth_update_pscr(struct net_device *dev,
449 struct ethtool_cmd *ecmd)
450{
451 struct mv643xx_private *mp = netdev_priv(dev);
452 int port_num = mp->port_num;
453 u32 o_pscr, n_pscr;
12a87c64 454 unsigned int queues;
d0412d96
JC		 455
456 o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
457 n_pscr = o_pscr;
458
459 /* clear speed, duplex and rx buffer size fields */
460 n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 |
461 MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
462 MV643XX_ETH_SET_FULL_DUPLEX_MODE |
463 MV643XX_ETH_MAX_RX_PACKET_MASK);
464
465 if (ecmd->duplex == DUPLEX_FULL)
466 n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE;
467
468 if (ecmd->speed == SPEED_1000)
469 n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
470 MV643XX_ETH_MAX_RX_PACKET_9700BYTE;
471 else {
472 if (ecmd->speed == SPEED_100)
473 n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100;
474 n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE;
475 }
476
477 if (n_pscr != o_pscr) {
478 if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0)
479 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
480 n_pscr);
481 else {
12a87c64 482 queues = mv643xx_eth_port_disable_tx(port_num);
d0412d96
JC		 483
484 o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
485 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
486 o_pscr);
487 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
488 n_pscr);
489 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
490 n_pscr);
12a87c64
DF		 491 if (queues)
492 mv643xx_eth_port_enable_tx(port_num, queues);
d0412d96
JC		 493 }
494 }
495}
496
1da177e4
LT		 497/*
498 * mv643xx_eth_int_handler
499 *
500 * Main interrupt handler for the gigbit ethernet ports
501 *
502 * Input : irq - irq number (not used)
503 * dev_id - a pointer to the required interface's data structure
504 * regs - not used
505 * Output : N/A
506 */
507
508static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
b4de9051 509 struct pt_regs *regs)
1da177e4
LT		 510{
511 struct net_device *dev = (struct net_device *)dev_id;
512 struct mv643xx_private *mp = netdev_priv(dev);
513 u32 eth_int_cause, eth_int_cause_ext = 0;
514 unsigned int port_num = mp->port_num;
515
516 /* Read interrupt cause registers */
517 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
7303fde8 518 ETH_INT_UNMASK_ALL;
468d09f8 519 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1da177e4
LT		 520 eth_int_cause_ext = mv_read(
521 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
7303fde8 522 ETH_INT_UNMASK_ALL_EXT;
468d09f8
DF		 523 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),
524 ~eth_int_cause_ext);
1da177e4 525 }
7303fde8 526
1da177e4 527 /* PHY status changed */
468d09f8 528 if (eth_int_cause_ext & ETH_INT_CAUSE_PHY) {
d0412d96
JC		 529 struct ethtool_cmd cmd;
530
c28a4f89 531 if (mii_link_ok(&mp->mii)) {
d0412d96
JC		 532 mii_ethtool_gset(&mp->mii, &cmd);
533 mv643xx_eth_update_pscr(dev, &cmd);
ff561eef
DF		 534 mv643xx_eth_port_enable_tx(port_num,
535 ETH_TX_QUEUES_ENABLED);
c28a4f89
JC		 536 if (!netif_carrier_ok(dev)) {
537 netif_carrier_on(dev);
ff561eef
DF		 538 if (mp->tx_ring_size - mp->tx_desc_count >=
539 MAX_DESCS_PER_SKB)
d0412d96 540 netif_wake_queue(dev);
c28a4f89
JC		 541 }
542 } else if (netif_carrier_ok(dev)) {
1da177e4 543 netif_stop_queue(dev);
c28a4f89 544 netif_carrier_off(dev);
1da177e4
LT		 545 }
546 }
547
468d09f8
DF		 548#ifdef MV643XX_NAPI
549 if (eth_int_cause & ETH_INT_CAUSE_RX) {
550 /* schedule the NAPI poll routine to maintain port */
551 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
552 ETH_INT_MASK_ALL);
553 /* wait for previous write to complete */
554 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
555
556 netif_rx_schedule(dev);
557 }
558#else
559 if (eth_int_cause & ETH_INT_CAUSE_RX)
560 mv643xx_eth_receive_queue(dev, INT_MAX);
5c537408 561#endif
468d09f8
DF		 562 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
563 mv643xx_eth_free_completed_tx_descs(dev);
468d09f8 564
1da177e4
LT		 565 /*
566 * If no real interrupt occured, exit.
567 * This can happen when using gigE interrupt coalescing mechanism.
568 */
569 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
570 return IRQ_NONE;
571
572 return IRQ_HANDLED;
573}
574
575#ifdef MV643XX_COAL
576
577/*
578 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
579 *
580 * DESCRIPTION:
581 * This routine sets the RX coalescing interrupt mechanism parameter.
582 * This parameter is a timeout counter, that counts in 64 t_clk
583 * chunks ; that when timeout event occurs a maskable interrupt
584 * occurs.
585 * The parameter is calculated using the tClk of the MV-643xx chip
586 * , and the required delay of the interrupt in usec.
587 *
588 * INPUT:
589 * unsigned int eth_port_num Ethernet port number
590 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
591 * unsigned int delay Delay in usec
592 *
593 * OUTPUT:
594 * Interrupt coalescing mechanism value is set in MV-643xx chip.
595 *
596 * RETURN:
597 * The interrupt coalescing value set in the gigE port.
598 *
599 */
600static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
601 unsigned int t_clk, unsigned int delay)
602{
603 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
604
605 /* Set RX Coalescing mechanism */
606 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
607 ((coal & 0x3fff) << 8) |
608 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
609 & 0xffc000ff));
610
611 return coal;
612}
613#endif
614
615/*
616 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
617 *
618 * DESCRIPTION:
619 * This routine sets the TX coalescing interrupt mechanism parameter.
620 * This parameter is a timeout counter, that counts in 64 t_clk
621 * chunks ; that when timeout event occurs a maskable interrupt
622 * occurs.
623 * The parameter is calculated using the t_cLK frequency of the
624 * MV-643xx chip and the required delay in the interrupt in uSec
625 *
626 * INPUT:
627 * unsigned int eth_port_num Ethernet port number
628 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
629 * unsigned int delay Delay in uSeconds
630 *
631 * OUTPUT:
632 * Interrupt coalescing mechanism value is set in MV-643xx chip.
633 *
634 * RETURN:
635 * The interrupt coalescing value set in the gigE port.
636 *
637 */
638static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
639 unsigned int t_clk, unsigned int delay)
640{
641 unsigned int coal;
642 coal = ((t_clk / 1000000) * delay) / 64;
643 /* Set TX Coalescing mechanism */
644 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
645 coal << 4);
646 return coal;
647}
648
1da177e4
LT		 649/*
650 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
651 *
652 * DESCRIPTION:
653 * This function prepares a Rx chained list of descriptors and packet
654 * buffers in a form of a ring. The routine must be called after port
655 * initialization routine and before port start routine.
656 * The Ethernet SDMA engine uses CPU bus addresses to access the various
657 * devices in the system (i.e. DRAM). This function uses the ethernet
658 * struct 'virtual to physical' routine (set by the user) to set the ring
659 * with physical addresses.
660 *
661 * INPUT:
662 * struct mv643xx_private *mp Ethernet Port Control srtuct.
663 *
664 * OUTPUT:
665 * The routine updates the Ethernet port control struct with information
666 * regarding the Rx descriptors and buffers.
667 *
668 * RETURN:
669 * None.
670 */
671static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
672{
673 volatile struct eth_rx_desc *p_rx_desc;
674 int rx_desc_num = mp->rx_ring_size;
675 int i;
676
677 /* initialize the next_desc_ptr links in the Rx descriptors ring */
678 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
679 for (i = 0; i < rx_desc_num; i++) {
680 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
681 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
682 }
683
684 /* Save Rx desc pointer to driver struct. */
685 mp->rx_curr_desc_q = 0;
686 mp->rx_used_desc_q = 0;
687
688 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
1da177e4
LT		 689}
690
691/*
692 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
693 *
694 * DESCRIPTION:
695 * This function prepares a Tx chained list of descriptors and packet
696 * buffers in a form of a ring. The routine must be called after port
697 * initialization routine and before port start routine.
698 * The Ethernet SDMA engine uses CPU bus addresses to access the various
699 * devices in the system (i.e. DRAM). This function uses the ethernet
700 * struct 'virtual to physical' routine (set by the user) to set the ring
701 * with physical addresses.
702 *
703 * INPUT:
704 * struct mv643xx_private *mp Ethernet Port Control srtuct.
705 *
706 * OUTPUT:
707 * The routine updates the Ethernet port control struct with information
708 * regarding the Tx descriptors and buffers.
709 *
710 * RETURN:
711 * None.
712 */
713static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
714{
715 int tx_desc_num = mp->tx_ring_size;
716 struct eth_tx_desc *p_tx_desc;
717 int i;
718
719 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
720 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
721 for (i = 0; i < tx_desc_num; i++) {
722 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
723 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
724 }
725
726 mp->tx_curr_desc_q = 0;
727 mp->tx_used_desc_q = 0;
1da177e4
LT		 728
729 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
1da177e4
LT		 730}
731
d0412d96
JC		 732static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
733{
734 struct mv643xx_private *mp = netdev_priv(dev);
735 int err;
736
737 spin_lock_irq(&mp->lock);
738 err = mii_ethtool_sset(&mp->mii, cmd);
739 spin_unlock_irq(&mp->lock);
740
741 return err;
742}
743
744static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
745{
746 struct mv643xx_private *mp = netdev_priv(dev);
747 int err;
748
749 spin_lock_irq(&mp->lock);
750 err = mii_ethtool_gset(&mp->mii, cmd);
751 spin_unlock_irq(&mp->lock);
752
753 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
754 cmd->supported &= ~SUPPORTED_1000baseT_Half;
755 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
756
757 return err;
758}
759
ab4384a6
DF		 760/*
761 * mv643xx_eth_open
762 *
763 * This function is called when openning the network device. The function
764 * should initialize all the hardware, initialize cyclic Rx/Tx
765 * descriptors chain and buffers and allocate an IRQ to the network
766 * device.
767 *
768 * Input : a pointer to the network device structure
769 *
770 * Output : zero of success , nonzero if fails.
771 */
772
773static int mv643xx_eth_open(struct net_device *dev)
1da177e4
LT		 774{
775 struct mv643xx_private *mp = netdev_priv(dev);
776 unsigned int port_num = mp->port_num;
777 unsigned int size;
ab4384a6
DF		 778 int err;
779
780 err = request_irq(dev->irq, mv643xx_eth_int_handler,
781 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
782 if (err) {
783 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
784 port_num);
785 return -EAGAIN;
786 }
1da177e4 787
1da177e4
LT		 788 eth_port_init(mp);
789
1da177e4 790 memset(&mp->timeout, 0, sizeof(struct timer_list));
f78fb474 791 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
1da177e4
LT		 792 mp->timeout.data = (unsigned long)dev;
793
1da177e4
LT		 794 /* Allocate RX and TX skb rings */
795 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
796 GFP_KERNEL);
797 if (!mp->rx_skb) {
798 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
ab4384a6
DF		 799 err = -ENOMEM;
800 goto out_free_irq;
1da177e4
LT		 801 }
802 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
803 GFP_KERNEL);
804 if (!mp->tx_skb) {
805 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
ab4384a6
DF		 806 err = -ENOMEM;
807 goto out_free_rx_skb;
1da177e4
LT		 808 }
809
810 /* Allocate TX ring */
f98e36f1 811 mp->tx_desc_count = 0;
1da177e4
LT		 812 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
813 mp->tx_desc_area_size = size;
814
815 if (mp->tx_sram_size) {
816 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
817 mp->tx_sram_size);
818 mp->tx_desc_dma = mp->tx_sram_addr;
819 } else
820 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
821 &mp->tx_desc_dma,
822 GFP_KERNEL);
823
824 if (!mp->p_tx_desc_area) {
825 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
826 dev->name, size);
ab4384a6
DF		 827 err = -ENOMEM;
828 goto out_free_tx_skb;
1da177e4
LT		 829 }
830 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
831 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
832
833 ether_init_tx_desc_ring(mp);
834
835 /* Allocate RX ring */
f98e36f1 836 mp->rx_desc_count = 0;
1da177e4
LT		 837 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
838 mp->rx_desc_area_size = size;
839
840 if (mp->rx_sram_size) {
841 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
842 mp->rx_sram_size);
843 mp->rx_desc_dma = mp->rx_sram_addr;
844 } else
845 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
846 &mp->rx_desc_dma,
847 GFP_KERNEL);
848
849 if (!mp->p_rx_desc_area) {
850 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
851 dev->name, size);
852 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
853 dev->name);
854 if (mp->rx_sram_size)
dd09b1de 855 iounmap(mp->p_tx_desc_area);
1da177e4
LT		 856 else
857 dma_free_coherent(NULL, mp->tx_desc_area_size,
858 mp->p_tx_desc_area, mp->tx_desc_dma);
ab4384a6
DF		 859 err = -ENOMEM;
860 goto out_free_tx_skb;
1da177e4
LT		 861 }
862 memset((void *)mp->p_rx_desc_area, 0, size);
863
864 ether_init_rx_desc_ring(mp);
865
f78fb474 866 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1da177e4 867
d0412d96
JC		 868 /* Clear any pending ethernet port interrupts */
869 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
870 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
871
ed9b5d45 872 eth_port_start(dev);
1da177e4
LT		 873
874 /* Interrupt Coalescing */
875
876#ifdef MV643XX_COAL
877 mp->rx_int_coal =
878 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
879#endif
880
881 mp->tx_int_coal =
882 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
883
8f518703
DF		 884 /* Unmask phy and link status changes interrupts */
885 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
7303fde8 886 ETH_INT_UNMASK_ALL_EXT);
1da177e4 887
8f518703 888 /* Unmask RX buffer and TX end interrupt */
7303fde8 889 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
d0412d96 890
1da177e4 891 return 0;
ab4384a6
DF		 892
893out_free_tx_skb:
894 kfree(mp->tx_skb);
895out_free_rx_skb:
896 kfree(mp->rx_skb);
897out_free_irq:
898 free_irq(dev->irq, dev);
899
900 return err;
1da177e4
LT		 901}
902
903static void mv643xx_eth_free_tx_rings(struct net_device *dev)
904{
905 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4
LT		 906
907 /* Stop Tx Queues */
ff561eef 908 mv643xx_eth_port_disable_tx(mp->port_num);
1da177e4 909
ff561eef
DF		 910 /* Free outstanding skb's on TX ring */
911 mv643xx_eth_free_all_tx_descs(dev);
912
913 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1da177e4
LT		 914
915 /* Free TX ring */
916 if (mp->tx_sram_size)
917 iounmap(mp->p_tx_desc_area);
918 else
919 dma_free_coherent(NULL, mp->tx_desc_area_size,
920 mp->p_tx_desc_area, mp->tx_desc_dma);
921}
922
923static void mv643xx_eth_free_rx_rings(struct net_device *dev)
924{
925 struct mv643xx_private *mp = netdev_priv(dev);
926 unsigned int port_num = mp->port_num;
927 int curr;
928
929 /* Stop RX Queues */
9f8dd319 930 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 931
932 /* Free preallocated skb's on RX rings */
f98e36f1 933 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1da177e4
LT		 934 if (mp->rx_skb[curr]) {
935 dev_kfree_skb(mp->rx_skb[curr]);
f98e36f1 936 mp->rx_desc_count--;
1da177e4
LT		 937 }
938 }
939
f98e36f1 940 if (mp->rx_desc_count)
1da177e4
LT		 941 printk(KERN_ERR
942 "%s: Error in freeing Rx Ring. %d skb's still"
943 " stuck in RX Ring - ignoring them\n", dev->name,
f98e36f1 944 mp->rx_desc_count);
1da177e4
LT		 945 /* Free RX ring */
946 if (mp->rx_sram_size)
947 iounmap(mp->p_rx_desc_area);
948 else
949 dma_free_coherent(NULL, mp->rx_desc_area_size,
950 mp->p_rx_desc_area, mp->rx_desc_dma);
951}
952
953/*
954 * mv643xx_eth_stop
955 *
956 * This function is used when closing the network device.
957 * It updates the hardware,
958 * release all memory that holds buffers and descriptors and release the IRQ.
959 * Input : a pointer to the device structure
960 * Output : zero if success , nonzero if fails
961 */
962
ab4384a6 963static int mv643xx_eth_stop(struct net_device *dev)
1da177e4
LT		 964{
965 struct mv643xx_private *mp = netdev_priv(dev);
966 unsigned int port_num = mp->port_num;
967
c2e5b352 968 /* Mask all interrupts on ethernet port */
7303fde8 969 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
c2e5b352 970 /* wait for previous write to complete */
8f518703
DF		 971 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
972
973#ifdef MV643XX_NAPI
974 netif_poll_disable(dev);
975#endif
1da177e4
LT		 976 netif_carrier_off(dev);
977 netif_stop_queue(dev);
978
1da177e4
LT		 979 eth_port_reset(mp->port_num);
980
8f518703
DF		 981 mv643xx_eth_free_tx_rings(dev);
982 mv643xx_eth_free_rx_rings(dev);
1da177e4 983
8f518703
DF		 984#ifdef MV643XX_NAPI
985 netif_poll_enable(dev);
986#endif
1da177e4 987
1da177e4 988 free_irq(dev->irq, dev);
1da177e4
LT		 989
990 return 0;
991}
992
993#ifdef MV643XX_NAPI
1da177e4
LT		 994/*
995 * mv643xx_poll
996 *
997 * This function is used in case of NAPI
998 */
999static int mv643xx_poll(struct net_device *dev, int *budget)
1000{
1001 struct mv643xx_private *mp = netdev_priv(dev);
1002 int done = 1, orig_budget, work_done;
1003 unsigned int port_num = mp->port_num;
1da177e4
LT		 1004
1005#ifdef MV643XX_TX_FAST_REFILL
1006 if (++mp->tx_clean_threshold > 5) {
ff561eef 1007 mv643xx_eth_free_completed_tx_descs(dev);
1da177e4 1008 mp->tx_clean_threshold = 0;
1da177e4
LT		 1009 }
1010#endif
1011
1012 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1013 != (u32) mp->rx_used_desc_q) {
1014 orig_budget = *budget;
1015 if (orig_budget > dev->quota)
1016 orig_budget = dev->quota;
1017 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1da177e4
LT		 1018 *budget -= work_done;
1019 dev->quota -= work_done;
1020 if (work_done >= orig_budget)
1021 done = 0;
1022 }
1023
1024 if (done) {
8f518703 1025 netif_rx_complete(dev);
1da177e4
LT		 1026 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1027 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1028 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
7303fde8 1029 ETH_INT_UNMASK_ALL);
1da177e4
LT		 1030 }
1031
1032 return done ? 0 : 1;
1033}
1034#endif
1035
c8aaea25
DF		 1036/**
1037 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1038 *
1039 * Hardware can't handle unaligned fragments smaller than 9 bytes.
f7ea3337
PJ		 1040 * This helper function detects that case.
1041 */
1042
1043static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1044{
b4de9051
DF		 1045 unsigned int frag;
1046 skb_frag_t *fragp;
f7ea3337 1047
b4de9051
DF		 1048 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1049 fragp = &skb_shinfo(skb)->frags[frag];
1050 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1051 return 1;
1052 }
1053 return 0;
f7ea3337
PJ		 1054}
1055
c8aaea25
DF		 1056/**
1057 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1058 */
1059static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1060{
1061 int tx_desc_curr;
1062
c8aaea25 1063 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
c8aaea25 1064
ff561eef 1065 tx_desc_curr = mp->tx_curr_desc_q;
c8aaea25
DF		 1066 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
1067
1068 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
1069
1070 return tx_desc_curr;
1071}
1072
1073/**
1074 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1da177e4 1075 *
c8aaea25
DF		 1076 * Ensure the data for each fragment to be transmitted is mapped properly,
1077 * then fill in descriptors in the tx hw queue.
1da177e4 1078 */
c8aaea25
DF		 1079static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1080 struct sk_buff *skb)
1da177e4 1081{
c8aaea25
DF		 1082 int frag;
1083 int tx_index;
1084 struct eth_tx_desc *desc;
1da177e4 1085
c8aaea25
DF		 1086 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1087 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1088
1089 tx_index = eth_alloc_tx_desc_index(mp);
1090 desc = &mp->p_tx_desc_area[tx_index];
1091
1092 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1093 /* Last Frag enables interrupt and frees the skb */
1094 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1095 desc->cmd_sts |= ETH_ZERO_PADDING |
1096 ETH_TX_LAST_DESC |
1097 ETH_TX_ENABLE_INTERRUPT;
1098 mp->tx_skb[tx_index] = skb;
1099 } else
1100 mp->tx_skb[tx_index] = 0;
1101
1102 desc = &mp->p_tx_desc_area[tx_index];
1103 desc->l4i_chk = 0;
1104 desc->byte_cnt = this_frag->size;
1105 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1106 this_frag->page_offset,
1107 this_frag->size,
1108 DMA_TO_DEVICE);
1da177e4 1109 }
c8aaea25 1110}
1da177e4 1111
c8aaea25
DF		 1112/**
1113 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1114 *
1115 * Ensure the data for an skb to be transmitted is mapped properly,
1116 * then fill in descriptors in the tx hw queue and start the hardware.
1117 */
ff561eef
DF		 1118static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1119 struct sk_buff *skb)
c8aaea25
DF		 1120{
1121 int tx_index;
1122 struct eth_tx_desc *desc;
1123 u32 cmd_sts;
1124 int length;
ff561eef 1125 int nr_frags = skb_shinfo(skb)->nr_frags;
1da177e4 1126
c8aaea25 1127 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1da177e4 1128
c8aaea25
DF		 1129 tx_index = eth_alloc_tx_desc_index(mp);
1130 desc = &mp->p_tx_desc_area[tx_index];
1131
ff561eef 1132 if (nr_frags) {
c8aaea25
DF		 1133 eth_tx_fill_frag_descs(mp, skb);
1134
1135 length = skb_headlen(skb);
1136 mp->tx_skb[tx_index] = 0;
1137 } else {
1138 cmd_sts |= ETH_ZERO_PADDING |
1139 ETH_TX_LAST_DESC |
1140 ETH_TX_ENABLE_INTERRUPT;
1141 length = skb->len;
1142 mp->tx_skb[tx_index] = skb;
f7ea3337
PJ		 1143 }
1144
c8aaea25
DF		 1145 desc->byte_cnt = length;
1146 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1da177e4 1147
c8aaea25
DF		 1148 if (skb->ip_summed == CHECKSUM_HW) {
1149 BUG_ON(skb->protocol != ETH_P_IP);
1150
1151 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1152 ETH_GEN_IP_V_4_CHECKSUM |
1153 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1154
1155 switch (skb->nh.iph->protocol) {
1156 case IPPROTO_UDP:
1157 cmd_sts |= ETH_UDP_FRAME;
1158 desc->l4i_chk = skb->h.uh->check;
1159 break;
1160 case IPPROTO_TCP:
1161 desc->l4i_chk = skb->h.th->check;
1162 break;
1163 default:
1164 BUG();
1da177e4 1165 }
1da177e4 1166 } else {
c8aaea25
DF		 1167 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1168 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1169 desc->l4i_chk = 0;
1170 }
1da177e4 1171
c8aaea25
DF		 1172 /* ensure all other descriptors are written before first cmd_sts */
1173 wmb();
1174 desc->cmd_sts = cmd_sts;
1da177e4 1175
c8aaea25
DF		 1176 /* ensure all descriptors are written before poking hardware */
1177 wmb();
ff561eef 1178 mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED);
1da177e4 1179
ff561eef 1180 mp->tx_desc_count += nr_frags + 1;
c8aaea25 1181}
1da177e4 1182
c8aaea25
DF		 1183/**
1184 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1185 *
1186 */
1187static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1188{
1189 struct mv643xx_private *mp = netdev_priv(dev);
1190 struct net_device_stats *stats = &mp->stats;
1191 unsigned long flags;
1da177e4 1192
c8aaea25
DF		 1193 BUG_ON(netif_queue_stopped(dev));
1194 BUG_ON(skb == NULL);
94843566
DF		 1195
1196 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1197 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1198 netif_stop_queue(dev);
1199 return 1;
1200 }
1da177e4 1201
c8aaea25
DF		 1202 if (has_tiny_unaligned_frags(skb)) {
1203 if ((skb_linearize(skb, GFP_ATOMIC) != 0)) {
1204 stats->tx_dropped++;
1205 printk(KERN_DEBUG "%s: failed to linearize tiny "
1206 "unaligned fragment\n", dev->name);
1207 return 1;
1da177e4
LT		 1208 }
1209 }
f7ea3337 1210
c8aaea25 1211 spin_lock_irqsave(&mp->lock, flags);
1da177e4 1212
ff561eef
DF		 1213 eth_tx_submit_descs_for_skb(mp, skb);
1214 stats->tx_bytes = skb->len;
1da177e4
LT		 1215 stats->tx_packets++;
1216 dev->trans_start = jiffies;
1217
c8aaea25
DF		 1218 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1219 netif_stop_queue(dev);
1220
1da177e4
LT		 1221 spin_unlock_irqrestore(&mp->lock, flags);
1222
1223 return 0; /* success */
1224}
1225
1226/*
1227 * mv643xx_eth_get_stats
1228 *
1229 * Returns a pointer to the interface statistics.
1230 *
1231 * Input : dev - a pointer to the required interface
1232 *
1233 * Output : a pointer to the interface's statistics
1234 */
1235
1236static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1237{
1238 struct mv643xx_private *mp = netdev_priv(dev);
1239
1240 return &mp->stats;
1241}
1242
63c9e549 1243#ifdef CONFIG_NET_POLL_CONTROLLER
63c9e549
DF		 1244static void mv643xx_netpoll(struct net_device *netdev)
1245{
1246 struct mv643xx_private *mp = netdev_priv(netdev);
c2e5b352
DF		 1247 int port_num = mp->port_num;
1248
7303fde8 1249 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
c2e5b352
DF		 1250 /* wait for previous write to complete */
1251 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
63c9e549 1252
63c9e549 1253 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
c2e5b352 1254
7303fde8 1255 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
63c9e549
DF		 1256}
1257#endif
1258
d0412d96
JC		 1259static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
1260 int speed, int duplex,
1261 struct ethtool_cmd *cmd)
1262{
1263 struct mv643xx_private *mp = netdev_priv(dev);
1264
1265 memset(cmd, 0, sizeof(*cmd));
1266
1267 cmd->port = PORT_MII;
1268 cmd->transceiver = XCVR_INTERNAL;
1269 cmd->phy_address = phy_address;
1270
1271 if (speed == 0) {
1272 cmd->autoneg = AUTONEG_ENABLE;
1273 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1274 cmd->speed = SPEED_100;
1275 cmd->advertising = ADVERTISED_10baseT_Half |
1276 ADVERTISED_10baseT_Full |
1277 ADVERTISED_100baseT_Half |
1278 ADVERTISED_100baseT_Full;
1279 if (mp->mii.supports_gmii)
1280 cmd->advertising |= ADVERTISED_1000baseT_Full;
1281 } else {
1282 cmd->autoneg = AUTONEG_DISABLE;
1283 cmd->speed = speed;
1284 cmd->duplex = duplex;
1285 }
1286}
1287
1da177e4
LT		 1288/*/
1289 * mv643xx_eth_probe
1290 *
1291 * First function called after registering the network device.
1292 * It's purpose is to initialize the device as an ethernet device,
1293 * fill the ethernet device structure with pointers * to functions,
1294 * and set the MAC address of the interface
1295 *
1296 * Input : struct device *
1297 * Output : -ENOMEM if failed , 0 if success
1298 */
3ae5eaec 1299static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 1300{
1da177e4
LT		 1301 struct mv643xx_eth_platform_data *pd;
1302 int port_num = pdev->id;
1303 struct mv643xx_private *mp;
1304 struct net_device *dev;
1305 u8 *p;
1306 struct resource *res;
1307 int err;
d0412d96 1308 struct ethtool_cmd cmd;
01999873
DF		 1309 int duplex = DUPLEX_HALF;
1310 int speed = 0; /* default to auto-negotiation */
1da177e4
LT		 1311
1312 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1313 if (!dev)
1314 return -ENOMEM;
1315
3ae5eaec 1316 platform_set_drvdata(pdev, dev);
1da177e4
LT		 1317
1318 mp = netdev_priv(dev);
1319
1320 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1321 BUG_ON(!res);
1322 dev->irq = res->start;
1323
1324 mp->port_num = port_num;
1325
1326 dev->open = mv643xx_eth_open;
1327 dev->stop = mv643xx_eth_stop;
1328 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1329 dev->get_stats = mv643xx_eth_get_stats;
1330 dev->set_mac_address = mv643xx_eth_set_mac_address;
1331 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1332
1333 /* No need to Tx Timeout */
1334 dev->tx_timeout = mv643xx_eth_tx_timeout;
1335#ifdef MV643XX_NAPI
1336 dev->poll = mv643xx_poll;
1337 dev->weight = 64;
1338#endif
1339
63c9e549
DF		 1340#ifdef CONFIG_NET_POLL_CONTROLLER
1341 dev->poll_controller = mv643xx_netpoll;
1342#endif
1343
1da177e4
LT		 1344 dev->watchdog_timeo = 2 * HZ;
1345 dev->tx_queue_len = mp->tx_ring_size;
1346 dev->base_addr = 0;
1347 dev->change_mtu = mv643xx_eth_change_mtu;
d0412d96 1348 dev->do_ioctl = mv643xx_eth_do_ioctl;
1da177e4
LT		 1349 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1350
1351#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1352#ifdef MAX_SKB_FRAGS
1353 /*
1354 * Zero copy can only work if we use Discovery II memory. Else, we will
1355 * have to map the buffers to ISA memory which is only 16 MB
1356 */
63890576 1357 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4
LT		 1358#endif
1359#endif
1360
1361 /* Configure the timeout task */
1362 INIT_WORK(&mp->tx_timeout_task,
1363 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1364
1365 spin_lock_init(&mp->lock);
1366
1367 /* set default config values */
1368 eth_port_uc_addr_get(dev, dev->dev_addr);
1da177e4
LT		 1369 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1370 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1371
1372 pd = pdev->dev.platform_data;
1373 if (pd) {
01999873 1374 if (pd->mac_addr)
1da177e4
LT		 1375 memcpy(dev->dev_addr, pd->mac_addr, 6);
1376
1377 if (pd->phy_addr || pd->force_phy_addr)
1378 ethernet_phy_set(port_num, pd->phy_addr);
1379
1da177e4
LT		 1380 if (pd->rx_queue_size)
1381 mp->rx_ring_size = pd->rx_queue_size;
1382
1383 if (pd->tx_queue_size)
1384 mp->tx_ring_size = pd->tx_queue_size;
1385
1386 if (pd->tx_sram_size) {
1387 mp->tx_sram_size = pd->tx_sram_size;
1388 mp->tx_sram_addr = pd->tx_sram_addr;
1389 }
1390
1391 if (pd->rx_sram_size) {
1392 mp->rx_sram_size = pd->rx_sram_size;
1393 mp->rx_sram_addr = pd->rx_sram_addr;
1394 }
01999873
DF		 1395
1396 duplex = pd->duplex;
1397 speed = pd->speed;
1da177e4
LT		 1398 }
1399
c28a4f89
JC		 1400 /* Hook up MII support for ethtool */
1401 mp->mii.dev = dev;
1402 mp->mii.mdio_read = mv643xx_mdio_read;
1403 mp->mii.mdio_write = mv643xx_mdio_write;
1404 mp->mii.phy_id = ethernet_phy_get(port_num);
1405 mp->mii.phy_id_mask = 0x3f;
1406 mp->mii.reg_num_mask = 0x1f;
1407
1da177e4
LT		 1408 err = ethernet_phy_detect(port_num);
1409 if (err) {
1410 pr_debug("MV643xx ethernet port %d: "
1411 "No PHY detected at addr %d\n",
1412 port_num, ethernet_phy_get(port_num));
d0412d96 1413 goto out;
1da177e4
LT		 1414 }
1415
01999873 1416 ethernet_phy_reset(port_num);
c28a4f89 1417 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
d0412d96
JC		 1418 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
1419 mv643xx_eth_update_pscr(dev, &cmd);
1420 mv643xx_set_settings(dev, &cmd);
c28a4f89 1421
1da177e4
LT		 1422 err = register_netdev(dev);
1423 if (err)
1424 goto out;
1425
1426 p = dev->dev_addr;
1427 printk(KERN_NOTICE
1428 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1429 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1430
1431 if (dev->features & NETIF_F_SG)
1432 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1433
1434 if (dev->features & NETIF_F_IP_CSUM)
1435 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1436 dev->name);
1437
1438#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1439 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1440#endif
1441
1442#ifdef MV643XX_COAL
1443 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1444 dev->name);
1445#endif
1446
1447#ifdef MV643XX_NAPI
1448 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1449#endif
1450
b1529871
ND		 1451 if (mp->tx_sram_size > 0)
1452 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1453
1da177e4
LT		 1454 return 0;
1455
1456out:
1457 free_netdev(dev);
1458
1459 return err;
1460}
1461
3ae5eaec 1462static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 1463{
3ae5eaec 1464 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 1465
1466 unregister_netdev(dev);
1467 flush_scheduled_work();
1468
1469 free_netdev(dev);
3ae5eaec 1470 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1471 return 0;
1472}
1473
3ae5eaec 1474static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1da177e4 1475{
1da177e4
LT		 1476 struct resource *res;
1477
1478 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1479
1480 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1481 if (res == NULL)
1482 return -ENODEV;
1483
1484 mv643xx_eth_shared_base = ioremap(res->start,
1485 MV643XX_ETH_SHARED_REGS_SIZE);
1486 if (mv643xx_eth_shared_base == NULL)
1487 return -ENOMEM;
1488
1489 return 0;
1490
1491}
1492
3ae5eaec 1493static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1da177e4
LT		 1494{
1495 iounmap(mv643xx_eth_shared_base);
1496 mv643xx_eth_shared_base = NULL;
1497
1498 return 0;
1499}
1500
3ae5eaec 1501static struct platform_driver mv643xx_eth_driver = {
1da177e4
LT		 1502 .probe = mv643xx_eth_probe,
1503 .remove = mv643xx_eth_remove,
3ae5eaec
RK		 1504 .driver = {
1505 .name = MV643XX_ETH_NAME,
1506 },
1da177e4
LT		 1507};
1508
3ae5eaec 1509static struct platform_driver mv643xx_eth_shared_driver = {
1da177e4
LT		 1510 .probe = mv643xx_eth_shared_probe,
1511 .remove = mv643xx_eth_shared_remove,
3ae5eaec
RK		 1512 .driver = {
1513 .name = MV643XX_ETH_SHARED_NAME,
1514 },
1da177e4
LT		 1515};
1516
1517/*
1518 * mv643xx_init_module
1519 *
1520 * Registers the network drivers into the Linux kernel
1521 *
1522 * Input : N/A
1523 *
1524 * Output : N/A
1525 */
1526static int __init mv643xx_init_module(void)
1527{
1528 int rc;
1529
3ae5eaec 1530 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1da177e4 1531 if (!rc) {
3ae5eaec 1532 rc = platform_driver_register(&mv643xx_eth_driver);
1da177e4 1533 if (rc)
3ae5eaec 1534 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1535 }
1536 return rc;
1537}
1538
1539/*
1540 * mv643xx_cleanup_module
1541 *
1542 * Registers the network drivers into the Linux kernel
1543 *
1544 * Input : N/A
1545 *
1546 * Output : N/A
1547 */
1548static void __exit mv643xx_cleanup_module(void)
1549{
3ae5eaec
RK		 1550 platform_driver_unregister(&mv643xx_eth_driver);
1551 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1552}
1553
1554module_init(mv643xx_init_module);
1555module_exit(mv643xx_cleanup_module);
1556
1557MODULE_LICENSE("GPL");
1558MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1559 " and Dale Farnsworth");
1560MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1561
1562/*
1563 * The second part is the low level driver of the gigE ethernet ports.
1564 */
1565
1566/*
1567 * Marvell's Gigabit Ethernet controller low level driver
1568 *
1569 * DESCRIPTION:
1570 * This file introduce low level API to Marvell's Gigabit Ethernet
1571 * controller. This Gigabit Ethernet Controller driver API controls
1572 * 1) Operations (i.e. port init, start, reset etc').
1573 * 2) Data flow (i.e. port send, receive etc').
1574 * Each Gigabit Ethernet port is controlled via
1575 * struct mv643xx_private.
1576 * This struct includes user configuration information as well as
1577 * driver internal data needed for its operations.
1578 *
1579 * Supported Features:
1580 * - This low level driver is OS independent. Allocating memory for
1581 * the descriptor rings and buffers are not within the scope of
1582 * this driver.
1583 * - The user is free from Rx/Tx queue managing.
1584 * - This low level driver introduce functionality API that enable
1585 * the to operate Marvell's Gigabit Ethernet Controller in a
1586 * convenient way.
1587 * - Simple Gigabit Ethernet port operation API.
1588 * - Simple Gigabit Ethernet port data flow API.
1589 * - Data flow and operation API support per queue functionality.
1590 * - Support cached descriptors for better performance.
1591 * - Enable access to all four DRAM banks and internal SRAM memory
1592 * spaces.
1593 * - PHY access and control API.
1594 * - Port control register configuration API.
1595 * - Full control over Unicast and Multicast MAC configurations.
1596 *
1597 * Operation flow:
1598 *
1599 * Initialization phase
1600 * This phase complete the initialization of the the
1601 * mv643xx_private struct.
1602 * User information regarding port configuration has to be set
1603 * prior to calling the port initialization routine.
1604 *
1605 * In this phase any port Tx/Rx activity is halted, MIB counters
1606 * are cleared, PHY address is set according to user parameter and
1607 * access to DRAM and internal SRAM memory spaces.
1608 *
1609 * Driver ring initialization
1610 * Allocating memory for the descriptor rings and buffers is not
1611 * within the scope of this driver. Thus, the user is required to
1612 * allocate memory for the descriptors ring and buffers. Those
1613 * memory parameters are used by the Rx and Tx ring initialization
1614 * routines in order to curve the descriptor linked list in a form
1615 * of a ring.
1616 * Note: Pay special attention to alignment issues when using
1617 * cached descriptors/buffers. In this phase the driver store
1618 * information in the mv643xx_private struct regarding each queue
1619 * ring.
1620 *
1621 * Driver start
1622 * This phase prepares the Ethernet port for Rx and Tx activity.
1623 * It uses the information stored in the mv643xx_private struct to
1624 * initialize the various port registers.
1625 *
1626 * Data flow:
1627 * All packet references to/from the driver are done using
1628 * struct pkt_info.
1629 * This struct is a unified struct used with Rx and Tx operations.
1630 * This way the user is not required to be familiar with neither
1631 * Tx nor Rx descriptors structures.
1632 * The driver's descriptors rings are management by indexes.
1633 * Those indexes controls the ring resources and used to indicate
1634 * a SW resource error:
1635 * 'current'
1636 * This index points to the current available resource for use. For
1637 * example in Rx process this index will point to the descriptor
1638 * that will be passed to the user upon calling the receive
1639 * routine. In Tx process, this index will point to the descriptor
1640 * that will be assigned with the user packet info and transmitted.
1641 * 'used'
1642 * This index points to the descriptor that need to restore its
1643 * resources. For example in Rx process, using the Rx buffer return
1644 * API will attach the buffer returned in packet info to the
1645 * descriptor pointed by 'used'. In Tx process, using the Tx
1646 * descriptor return will merely return the user packet info with
1647 * the command status of the transmitted buffer pointed by the
1648 * 'used' index. Nevertheless, it is essential to use this routine
1649 * to update the 'used' index.
1650 * 'first'
1651 * This index supports Tx Scatter-Gather. It points to the first
1652 * descriptor of a packet assembled of multiple buffers. For
1653 * example when in middle of Such packet we have a Tx resource
1654 * error the 'curr' index get the value of 'first' to indicate
1655 * that the ring returned to its state before trying to transmit
1656 * this packet.
1657 *
1658 * Receive operation:
1659 * The eth_port_receive API set the packet information struct,
1660 * passed by the caller, with received information from the
1661 * 'current' SDMA descriptor.
1662 * It is the user responsibility to return this resource back
1663 * to the Rx descriptor ring to enable the reuse of this source.
1664 * Return Rx resource is done using the eth_rx_return_buff API.
1665 *
1da177e4
LT		 1666 * Prior to calling the initialization routine eth_port_init() the user
1667 * must set the following fields under mv643xx_private struct:
1668 * port_num User Ethernet port number.
1da177e4
LT		 1669 * port_config User port configuration value.
1670 * port_config_extend User port config extend value.
1671 * port_sdma_config User port SDMA config value.
1672 * port_serial_control User port serial control value.
1673 *
1674 * This driver data flow is done using the struct pkt_info which
1675 * is a unified struct for Rx and Tx operations:
1676 *
1677 * byte_cnt Tx/Rx descriptor buffer byte count.
1678 * l4i_chk CPU provided TCP Checksum. For Tx operation
1679 * only.
1680 * cmd_sts Tx/Rx descriptor command status.
1681 * buf_ptr Tx/Rx descriptor buffer pointer.
1682 * return_info Tx/Rx user resource return information.
1683 */
1684
1da177e4
LT		 1685/* PHY routines */
1686static int ethernet_phy_get(unsigned int eth_port_num);
1687static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1688
1689/* Ethernet Port routines */
cf4086c7 1690static void eth_port_set_filter_table_entry(int table, unsigned char entry);
1da177e4
LT		 1691
1692/*
1693 * eth_port_init - Initialize the Ethernet port driver
1694 *
1695 * DESCRIPTION:
1696 * This function prepares the ethernet port to start its activity:
1697 * 1) Completes the ethernet port driver struct initialization toward port
1698 * start routine.
1699 * 2) Resets the device to a quiescent state in case of warm reboot.
1700 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1701 * 4) Clean MAC tables. The reset status of those tables is unknown.
1702 * 5) Set PHY address.
1703 * Note: Call this routine prior to eth_port_start routine and after
1704 * setting user values in the user fields of Ethernet port control
1705 * struct.
1706 *
1707 * INPUT:
1708 * struct mv643xx_private *mp Ethernet port control struct
1709 *
1710 * OUTPUT:
1711 * See description.
1712 *
1713 * RETURN:
1714 * None.
1715 */
1716static void eth_port_init(struct mv643xx_private *mp)
1717{
1da177e4 1718 mp->rx_resource_err = 0;
1da177e4
LT		 1719
1720 eth_port_reset(mp->port_num);
1721
1722 eth_port_init_mac_tables(mp->port_num);
1da177e4
LT		 1723}
1724
1725/*
1726 * eth_port_start - Start the Ethernet port activity.
1727 *
1728 * DESCRIPTION:
1729 * This routine prepares the Ethernet port for Rx and Tx activity:
1730 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1731 * has been initialized a descriptor's ring (using
1732 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1733 * 2. Initialize and enable the Ethernet configuration port by writing to
1734 * the port's configuration and command registers.
1735 * 3. Initialize and enable the SDMA by writing to the SDMA's
1736 * configuration and command registers. After completing these steps,
1737 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1738 *
1739 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1740 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1741 * and ether_init_rx_desc_ring for Rx queues).
1742 *
1743 * INPUT:
ed9b5d45 1744 * dev - a pointer to the required interface
1da177e4
LT		 1745 *
1746 * OUTPUT:
1747 * Ethernet port is ready to receive and transmit.
1748 *
1749 * RETURN:
1750 * None.
1751 */
ed9b5d45 1752static void eth_port_start(struct net_device *dev)
1da177e4 1753{
ed9b5d45 1754 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4
LT		 1755 unsigned int port_num = mp->port_num;
1756 int tx_curr_desc, rx_curr_desc;
d0412d96
JC		 1757 u32 pscr;
1758 struct ethtool_cmd ethtool_cmd;
1da177e4
LT		 1759
1760 /* Assignment of Tx CTRP of given queue */
1761 tx_curr_desc = mp->tx_curr_desc_q;
1762 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1763 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1764
1765 /* Assignment of Rx CRDP of given queue */
1766 rx_curr_desc = mp->rx_curr_desc_q;
1767 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1768 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1769
1770 /* Add the assigned Ethernet address to the port's address table */
ed9b5d45 1771 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 1772
1773 /* Assign port configuration and command. */
01999873
DF		 1774 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num),
1775 MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE);
1776
1777 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1778 MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE);
1da177e4 1779
d0412d96 1780 pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
01999873
DF		 1781
1782 pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS);
d0412d96 1783 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4 1784
d0412d96
JC		 1785 pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1786 MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII |
1787 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX |
1788 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
1789 MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED;
1da177e4 1790
d0412d96 1791 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4 1792
d0412d96
JC		 1793 pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE;
1794 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4
LT		 1795
1796 /* Assign port SDMA configuration */
01999873
DF		 1797 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1798 MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE);
1da177e4
LT		 1799
1800 /* Enable port Rx. */
ff561eef 1801 mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
8f543718
DF		 1802
1803 /* Disable port bandwidth limits by clearing MTU register */
1804 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
d0412d96
JC		 1805
1806 /* save phy settings across reset */
1807 mv643xx_get_settings(dev, &ethtool_cmd);
1808 ethernet_phy_reset(mp->port_num);
1809 mv643xx_set_settings(dev, &ethtool_cmd);
1da177e4
LT		 1810}
1811
1812/*
1813 * eth_port_uc_addr_set - This function Set the port Unicast address.
1814 *
1815 * DESCRIPTION:
1816 * This function Set the port Ethernet MAC address.
1817 *
1818 * INPUT:
1819 * unsigned int eth_port_num Port number.
1820 * char * p_addr Address to be set
1821 *
1822 * OUTPUT:
cf4086c7
DF		 1823 * Set MAC address low and high registers. also calls
1824 * eth_port_set_filter_table_entry() to set the unicast
1825 * table with the proper information.
1da177e4
LT		 1826 *
1827 * RETURN:
1828 * N/A.
1829 *
1830 */
1831static void eth_port_uc_addr_set(unsigned int eth_port_num,
1832 unsigned char *p_addr)
1833{
1834 unsigned int mac_h;
1835 unsigned int mac_l;
cf4086c7 1836 int table;
1da177e4
LT		 1837
1838 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1839 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1840 (p_addr[3] << 0);
1841
1842 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1843 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1844
1845 /* Accept frames of this address */
cf4086c7
DF		 1846 table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(eth_port_num);
1847 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
1da177e4
LT		 1848}
1849
1850/*
1851 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1852 * (MAC address) from the ethernet hw registers.
1853 *
1854 * DESCRIPTION:
1855 * This function retrieves the port Ethernet MAC address.
1856 *
1857 * INPUT:
1858 * unsigned int eth_port_num Port number.
1859 * char *MacAddr pointer where the MAC address is stored
1860 *
1861 * OUTPUT:
1862 * Copy the MAC address to the location pointed to by MacAddr
1863 *
1864 * RETURN:
1865 * N/A.
1866 *
1867 */
1868static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1869{
1870 struct mv643xx_private *mp = netdev_priv(dev);
1871 unsigned int mac_h;
1872 unsigned int mac_l;
1873
1874 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1875 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1876
1877 p_addr[0] = (mac_h >> 24) & 0xff;
1878 p_addr[1] = (mac_h >> 16) & 0xff;
1879 p_addr[2] = (mac_h >> 8) & 0xff;
1880 p_addr[3] = mac_h & 0xff;
1881 p_addr[4] = (mac_l >> 8) & 0xff;
1882 p_addr[5] = mac_l & 0xff;
1883}
1884
16e03018
DF		 1885/*
1886 * The entries in each table are indexed by a hash of a packet's MAC
1887 * address. One bit in each entry determines whether the packet is
1888 * accepted. There are 4 entries (each 8 bits wide) in each register
1889 * of the table. The bits in each entry are defined as follows:
1890 * 0 Accept=1, Drop=0
1891 * 3-1 Queue (ETH_Q0=0)
1892 * 7-4 Reserved = 0;
1893 */
1894static void eth_port_set_filter_table_entry(int table, unsigned char entry)
1895{
1896 unsigned int table_reg;
1897 unsigned int tbl_offset;
1898 unsigned int reg_offset;
1899
1900 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1901 reg_offset = entry % 4; /* Entry offset within the register */
1902
1903 /* Set "accepts frame bit" at specified table entry */
1904 table_reg = mv_read(table + tbl_offset);
1905 table_reg |= 0x01 << (8 * reg_offset);
1906 mv_write(table + tbl_offset, table_reg);
1907}
1908
1909/*
1910 * eth_port_mc_addr - Multicast address settings.
1911 *
1912 * The MV device supports multicast using two tables:
1913 * 1) Special Multicast Table for MAC addresses of the form
1914 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1915 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1916 * Table entries in the DA-Filter table.
1917 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1918 * is used as an index to the Other Multicast Table entries in the
1919 * DA-Filter table. This function calculates the CRC-8bit value.
1920 * In either case, eth_port_set_filter_table_entry() is then called
1921 * to set to set the actual table entry.
1922 */
1923static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
1924{
1925 unsigned int mac_h;
1926 unsigned int mac_l;
1927 unsigned char crc_result = 0;
1928 int table;
1929 int mac_array[48];
1930 int crc[8];
1931 int i;
1932
1933 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1934 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
1935 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
1936 (eth_port_num);
1937 eth_port_set_filter_table_entry(table, p_addr[5]);
1938 return;
1939 }
1940
1941 /* Calculate CRC-8 out of the given address */
1942 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1943 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1944 (p_addr[4] << 8) | (p_addr[5] << 0);
1945
1946 for (i = 0; i < 32; i++)
1947 mac_array[i] = (mac_l >> i) & 0x1;
1948 for (i = 32; i < 48; i++)
1949 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1950
1951 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1952 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1953 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1954 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1955 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1956
1957 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1958 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1959 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1960 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1961 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1962 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1963 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1964
1965 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1966 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1967 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1968 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1969 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1970 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
1971
1972 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1973 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1974 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1975 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1976 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
1977 mac_array[3] ^ mac_array[2] ^ mac_array[1];
1978
1979 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
1980 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
1981 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1982 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
1983 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
1984 mac_array[3] ^ mac_array[2];
1985
1986 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
1987 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
1988 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1989 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
1990 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
1991 mac_array[4] ^ mac_array[3];
1992
1993 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
1994 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
1995 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1996 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
1997 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
1998 mac_array[4];
1999
2000 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2001 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2002 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2003 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2004 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2005
2006 for (i = 0; i < 8; i++)
2007 crc_result = crc_result | (crc[i] << i);
2008
2009 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2010 eth_port_set_filter_table_entry(table, crc_result);
2011}
2012
2013/*
2014 * Set the entire multicast list based on dev->mc_list.
2015 */
2016static void eth_port_set_multicast_list(struct net_device *dev)
2017{
2018
2019 struct dev_mc_list *mc_list;
2020 int i;
2021 int table_index;
2022 struct mv643xx_private *mp = netdev_priv(dev);
2023 unsigned int eth_port_num = mp->port_num;
2024
2025 /* If the device is in promiscuous mode or in all multicast mode,
2026 * we will fully populate both multicast tables with accept.
2027 * This is guaranteed to yield a match on all multicast addresses...
2028 */
2029 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2030 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
b4de9051
DF		 2031 /* Set all entries in DA filter special multicast
2032 * table (Ex_dFSMT)
2033 * Set for ETH_Q0 for now
2034 * Bits
2035 * 0 Accept=1, Drop=0
2036 * 3-1 Queue ETH_Q0=0
2037 * 7-4 Reserved = 0;
2038 */
2039 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2040
2041 /* Set all entries in DA filter other multicast
2042 * table (Ex_dFOMT)
2043 * Set for ETH_Q0 for now
2044 * Bits
2045 * 0 Accept=1, Drop=0
2046 * 3-1 Queue ETH_Q0=0
2047 * 7-4 Reserved = 0;
2048 */
2049 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2050 }
16e03018
DF		 2051 return;
2052 }
2053
2054 /* We will clear out multicast tables every time we get the list.
2055 * Then add the entire new list...
2056 */
2057 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2058 /* Clear DA filter special multicast table (Ex_dFSMT) */
2059 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2060 (eth_port_num) + table_index, 0);
2061
2062 /* Clear DA filter other multicast table (Ex_dFOMT) */
2063 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2064 (eth_port_num) + table_index, 0);
2065 }
2066
2067 /* Get pointer to net_device multicast list and add each one... */
2068 for (i = 0, mc_list = dev->mc_list;
2069 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2070 i++, mc_list = mc_list->next)
2071 if (mc_list->dmi_addrlen == 6)
2072 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2073}
2074
1da177e4
LT		 2075/*
2076 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2077 *
2078 * DESCRIPTION:
2079 * Go through all the DA filter tables (Unicast, Special Multicast &
2080 * Other Multicast) and set each entry to 0.
2081 *
2082 * INPUT:
2083 * unsigned int eth_port_num Ethernet Port number.
2084 *
2085 * OUTPUT:
2086 * Multicast and Unicast packets are rejected.
2087 *
2088 * RETURN:
2089 * None.
2090 */
2091static void eth_port_init_mac_tables(unsigned int eth_port_num)
2092{
2093 int table_index;
2094
2095 /* Clear DA filter unicast table (Ex_dFUT) */
2096 for (table_index = 0; table_index <= 0xC; table_index += 4)
cf4086c7
DF		 2097 mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2098 (eth_port_num) + table_index, 0);
1da177e4
LT		 2099
2100 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2101 /* Clear DA filter special multicast table (Ex_dFSMT) */
16e03018
DF		 2102 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2103 (eth_port_num) + table_index, 0);
1da177e4 2104 /* Clear DA filter other multicast table (Ex_dFOMT) */
16e03018
DF		 2105 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2106 (eth_port_num) + table_index, 0);
1da177e4
LT		 2107 }
2108}
2109
2110/*
2111 * eth_clear_mib_counters - Clear all MIB counters
2112 *
2113 * DESCRIPTION:
2114 * This function clears all MIB counters of a specific ethernet port.
2115 * A read from the MIB counter will reset the counter.
2116 *
2117 * INPUT:
2118 * unsigned int eth_port_num Ethernet Port number.
2119 *
2120 * OUTPUT:
2121 * After reading all MIB counters, the counters resets.
2122 *
2123 * RETURN:
2124 * MIB counter value.
2125 *
2126 */
2127static void eth_clear_mib_counters(unsigned int eth_port_num)
2128{
2129 int i;
2130
2131 /* Perform dummy reads from MIB counters */
2132 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2133 i += 4)
2134 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2135}
2136
2137static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2138{
2139 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2140}
2141
2142static void eth_update_mib_counters(struct mv643xx_private *mp)
2143{
2144 struct mv643xx_mib_counters *p = &mp->mib_counters;
2145 int offset;
2146
2147 p->good_octets_received +=
2148 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2149 p->good_octets_received +=
2150 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2151
2152 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2153 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2154 offset += 4)
2155 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2156
2157 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2158 p->good_octets_sent +=
2159 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2160
2161 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2162 offset <= ETH_MIB_LATE_COLLISION;
2163 offset += 4)
2164 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2165}
2166
2167/*
2168 * ethernet_phy_detect - Detect whether a phy is present
2169 *
2170 * DESCRIPTION:
2171 * This function tests whether there is a PHY present on
2172 * the specified port.
2173 *
2174 * INPUT:
2175 * unsigned int eth_port_num Ethernet Port number.
2176 *
2177 * OUTPUT:
2178 * None
2179 *
2180 * RETURN:
2181 * 0 on success
2182 * -ENODEV on failure
2183 *
2184 */
2185static int ethernet_phy_detect(unsigned int port_num)
2186{
2187 unsigned int phy_reg_data0;
2188 int auto_neg;
2189
2190 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2191 auto_neg = phy_reg_data0 & 0x1000;
2192 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2193 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2194
2195 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2196 if ((phy_reg_data0 & 0x1000) == auto_neg)
2197 return -ENODEV; /* change didn't take */
2198
2199 phy_reg_data0 ^= 0x1000;
2200 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2201 return 0;
2202}
2203
2204/*
2205 * ethernet_phy_get - Get the ethernet port PHY address.
2206 *
2207 * DESCRIPTION:
2208 * This routine returns the given ethernet port PHY address.
2209 *
2210 * INPUT:
2211 * unsigned int eth_port_num Ethernet Port number.
2212 *
2213 * OUTPUT:
2214 * None.
2215 *
2216 * RETURN:
2217 * PHY address.
2218 *
2219 */
2220static int ethernet_phy_get(unsigned int eth_port_num)
2221{
2222 unsigned int reg_data;
2223
2224 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2225
2226 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2227}
2228
2229/*
2230 * ethernet_phy_set - Set the ethernet port PHY address.
2231 *
2232 * DESCRIPTION:
2233 * This routine sets the given ethernet port PHY address.
2234 *
2235 * INPUT:
2236 * unsigned int eth_port_num Ethernet Port number.
2237 * int phy_addr PHY address.
2238 *
2239 * OUTPUT:
2240 * None.
2241 *
2242 * RETURN:
2243 * None.
2244 *
2245 */
2246static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2247{
2248 u32 reg_data;
2249 int addr_shift = 5 * eth_port_num;
2250
2251 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2252 reg_data &= ~(0x1f << addr_shift);
2253 reg_data |= (phy_addr & 0x1f) << addr_shift;
2254 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2255}
2256
2257/*
2258 * ethernet_phy_reset - Reset Ethernet port PHY.
2259 *
2260 * DESCRIPTION:
2261 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2262 *
2263 * INPUT:
2264 * unsigned int eth_port_num Ethernet Port number.
2265 *
2266 * OUTPUT:
2267 * The PHY is reset.
2268 *
2269 * RETURN:
2270 * None.
2271 *
2272 */
2273static void ethernet_phy_reset(unsigned int eth_port_num)
2274{
2275 unsigned int phy_reg_data;
2276
2277 /* Reset the PHY */
2278 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2279 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2280 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
d0412d96
JC		 2281
2282 /* wait for PHY to come out of reset */
2283 do {
2284 udelay(1);
2285 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2286 } while (phy_reg_data & 0x8000);
1da177e4
LT		 2287}
2288
9f8dd319 2289static void mv643xx_eth_port_enable_tx(unsigned int port_num,
12a87c64 2290 unsigned int queues)
9f8dd319 2291{
12a87c64 2292 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
9f8dd319
DF		 2293}
2294
2295static void mv643xx_eth_port_enable_rx(unsigned int port_num,
12a87c64 2296 unsigned int queues)
9f8dd319 2297{
12a87c64 2298 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
9f8dd319
DF		 2299}
2300
2301static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2302{
12a87c64 2303 u32 queues;
9f8dd319
DF		 2304
2305 /* Stop Tx port activity. Check port Tx activity. */
12a87c64 2306 queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
9f8dd319 2307 & 0xFF;
12a87c64
DF		 2308 if (queues) {
2309 /* Issue stop command for active queues only */
9f8dd319 2310 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
12a87c64 2311 (queues << 8));
9f8dd319
DF		 2312
2313 /* Wait for all Tx activity to terminate. */
2314 /* Check port cause register that all Tx queues are stopped */
2315 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2316 & 0xFF)
2317 udelay(PHY_WAIT_MICRO_SECONDS);
2318
2319 /* Wait for Tx FIFO to empty */
2320 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) &
2321 ETH_PORT_TX_FIFO_EMPTY)
2322 udelay(PHY_WAIT_MICRO_SECONDS);
2323 }
2324
12a87c64 2325 return queues;
9f8dd319
DF		 2326}
2327
2328static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2329{
12a87c64 2330 u32 queues;
9f8dd319
DF		 2331
2332 /* Stop Rx port activity. Check port Rx activity. */
12a87c64 2333 queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
e38fd1a0 2334 & 0xFF;
12a87c64
DF		 2335 if (queues) {
2336 /* Issue stop command for active queues only */
9f8dd319 2337 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
12a87c64 2338 (queues << 8));
9f8dd319
DF		 2339
2340 /* Wait for all Rx activity to terminate. */
2341 /* Check port cause register that all Rx queues are stopped */
2342 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2343 & 0xFF)
2344 udelay(PHY_WAIT_MICRO_SECONDS);
2345 }
2346
12a87c64 2347 return queues;
9f8dd319
DF		 2348}
2349
1da177e4
LT		 2350/*
2351 * eth_port_reset - Reset Ethernet port
2352 *
2353 * DESCRIPTION:
2354 * This routine resets the chip by aborting any SDMA engine activity and
2355 * clearing the MIB counters. The Receiver and the Transmit unit are in
2356 * idle state after this command is performed and the port is disabled.
2357 *
2358 * INPUT:
2359 * unsigned int eth_port_num Ethernet Port number.
2360 *
2361 * OUTPUT:
2362 * Channel activity is halted.
2363 *
2364 * RETURN:
2365 * None.
2366 *
2367 */
2368static void eth_port_reset(unsigned int port_num)
2369{
2370 unsigned int reg_data;
2371
9f8dd319
DF		 2372 mv643xx_eth_port_disable_tx(port_num);
2373 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 2374
2375 /* Clear all MIB counters */
2376 eth_clear_mib_counters(port_num);
2377
2378 /* Reset the Enable bit in the Configuration Register */
2379 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
d0412d96
JC		 2380 reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE |
2381 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
2382 MV643XX_ETH_FORCE_LINK_PASS);
1da177e4
LT		 2383 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2384}
2385
1da177e4 2386
1da177e4
LT		 2387/*
2388 * eth_port_read_smi_reg - Read PHY registers
2389 *
2390 * DESCRIPTION:
2391 * This routine utilize the SMI interface to interact with the PHY in
2392 * order to perform PHY register read.
2393 *
2394 * INPUT:
2395 * unsigned int port_num Ethernet Port number.
2396 * unsigned int phy_reg PHY register address offset.
2397 * unsigned int *value Register value buffer.
2398 *
2399 * OUTPUT:
2400 * Write the value of a specified PHY register into given buffer.
2401 *
2402 * RETURN:
2403 * false if the PHY is busy or read data is not in valid state.
2404 * true otherwise.
2405 *
2406 */
2407static void eth_port_read_smi_reg(unsigned int port_num,
2408 unsigned int phy_reg, unsigned int *value)
2409{
2410 int phy_addr = ethernet_phy_get(port_num);
2411 unsigned long flags;
2412 int i;
2413
2414 /* the SMI register is a shared resource */
2415 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2416
2417 /* wait for the SMI register to become available */
2418 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2419 if (i == PHY_WAIT_ITERATIONS) {
2420 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2421 goto out;
2422 }
2423 udelay(PHY_WAIT_MICRO_SECONDS);
2424 }
2425
2426 mv_write(MV643XX_ETH_SMI_REG,
2427 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2428
2429 /* now wait for the data to be valid */
2430 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2431 if (i == PHY_WAIT_ITERATIONS) {
2432 printk("mv643xx PHY read timeout, port %d\n", port_num);
2433 goto out;
2434 }
2435 udelay(PHY_WAIT_MICRO_SECONDS);
2436 }
2437
2438 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2439out:
2440 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2441}
2442
2443/*
2444 * eth_port_write_smi_reg - Write to PHY registers
2445 *
2446 * DESCRIPTION:
2447 * This routine utilize the SMI interface to interact with the PHY in
2448 * order to perform writes to PHY registers.
2449 *
2450 * INPUT:
2451 * unsigned int eth_port_num Ethernet Port number.
2452 * unsigned int phy_reg PHY register address offset.
2453 * unsigned int value Register value.
2454 *
2455 * OUTPUT:
2456 * Write the given value to the specified PHY register.
2457 *
2458 * RETURN:
2459 * false if the PHY is busy.
2460 * true otherwise.
2461 *
2462 */
2463static void eth_port_write_smi_reg(unsigned int eth_port_num,
2464 unsigned int phy_reg, unsigned int value)
2465{
2466 int phy_addr;
2467 int i;
2468 unsigned long flags;
2469
2470 phy_addr = ethernet_phy_get(eth_port_num);
2471
2472 /* the SMI register is a shared resource */
2473 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2474
2475 /* wait for the SMI register to become available */
2476 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2477 if (i == PHY_WAIT_ITERATIONS) {
2478 printk("mv643xx PHY busy timeout, port %d\n",
2479 eth_port_num);
2480 goto out;
2481 }
2482 udelay(PHY_WAIT_MICRO_SECONDS);
2483 }
2484
2485 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2486 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2487out:
2488 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2489}
2490
c28a4f89
JC		 2491/*
2492 * Wrappers for MII support library.
2493 */
2494static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2495{
2496 int val;
2497 struct mv643xx_private *mp = netdev_priv(dev);
2498
2499 eth_port_read_smi_reg(mp->port_num, location, &val);
2500 return val;
2501}
2502
2503static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2504{
2505 struct mv643xx_private *mp = netdev_priv(dev);
2506 eth_port_write_smi_reg(mp->port_num, location, val);
2507}
2508
1da177e4
LT		 2509/*
2510 * eth_port_receive - Get received information from Rx ring.
2511 *
2512 * DESCRIPTION:
2513 * This routine returns the received data to the caller. There is no
2514 * data copying during routine operation. All information is returned
2515 * using pointer to packet information struct passed from the caller.
2516 * If the routine exhausts Rx ring resources then the resource error flag
2517 * is set.
2518 *
2519 * INPUT:
2520 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2521 * struct pkt_info *p_pkt_info User packet buffer.
2522 *
2523 * OUTPUT:
2524 * Rx ring current and used indexes are updated.
2525 *
2526 * RETURN:
2527 * ETH_ERROR in case the routine can not access Rx desc ring.
2528 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2529 * ETH_END_OF_JOB if there is no received data.
2530 * ETH_OK otherwise.
2531 */
2532static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2533 struct pkt_info *p_pkt_info)
2534{
2535 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2536 volatile struct eth_rx_desc *p_rx_desc;
2537 unsigned int command_status;
8f518703 2538 unsigned long flags;
1da177e4
LT		 2539
2540 /* Do not process Rx ring in case of Rx ring resource error */
2541 if (mp->rx_resource_err)
2542 return ETH_QUEUE_FULL;
2543
8f518703
DF		 2544 spin_lock_irqsave(&mp->lock, flags);
2545
1da177e4
LT		 2546 /* Get the Rx Desc ring 'curr and 'used' indexes */
2547 rx_curr_desc = mp->rx_curr_desc_q;
2548 rx_used_desc = mp->rx_used_desc_q;
2549
2550 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2551
2552 /* The following parameters are used to save readings from memory */
2553 command_status = p_rx_desc->cmd_sts;
2554 rmb();
2555
2556 /* Nothing to receive... */
8f518703
DF		 2557 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2558 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 2559 return ETH_END_OF_JOB;
8f518703 2560 }
1da177e4
LT		 2561
2562 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2563 p_pkt_info->cmd_sts = command_status;
2564 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2565 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2566 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2567
b4de9051
DF		 2568 /*
2569 * Clean the return info field to indicate that the
2570 * packet has been moved to the upper layers
2571 */
1da177e4
LT		 2572 mp->rx_skb[rx_curr_desc] = NULL;
2573
2574 /* Update current index in data structure */
2575 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2576 mp->rx_curr_desc_q = rx_next_curr_desc;
2577
2578 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2579 if (rx_next_curr_desc == rx_used_desc)
2580 mp->rx_resource_err = 1;
2581
8f518703
DF		 2582 spin_unlock_irqrestore(&mp->lock, flags);
2583
1da177e4
LT		 2584 return ETH_OK;
2585}
2586
2587/*
2588 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2589 *
2590 * DESCRIPTION:
2591 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2592 * next 'used' descriptor and attached the returned buffer to it.
2593 * In case the Rx ring was in "resource error" condition, where there are
2594 * no available Rx resources, the function resets the resource error flag.
2595 *
2596 * INPUT:
2597 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2598 * struct pkt_info *p_pkt_info Information on returned buffer.
2599 *
2600 * OUTPUT:
2601 * New available Rx resource in Rx descriptor ring.
2602 *
2603 * RETURN:
2604 * ETH_ERROR in case the routine can not access Rx desc ring.
2605 * ETH_OK otherwise.
2606 */
2607static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2608 struct pkt_info *p_pkt_info)
2609{
2610 int used_rx_desc; /* Where to return Rx resource */
2611 volatile struct eth_rx_desc *p_used_rx_desc;
8f518703
DF		 2612 unsigned long flags;
2613
2614 spin_lock_irqsave(&mp->lock, flags);
1da177e4
LT		 2615
2616 /* Get 'used' Rx descriptor */
2617 used_rx_desc = mp->rx_used_desc_q;
2618 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2619
2620 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2621 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2622 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2623
2624 /* Flush the write pipe */
2625
2626 /* Return the descriptor to DMA ownership */
2627 wmb();
2628 p_used_rx_desc->cmd_sts =
2629 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2630 wmb();
2631
2632 /* Move the used descriptor pointer to the next descriptor */
2633 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2634
2635 /* Any Rx return cancels the Rx resource error status */
2636 mp->rx_resource_err = 0;
2637
8f518703
DF		 2638 spin_unlock_irqrestore(&mp->lock, flags);
2639
1da177e4
LT		 2640 return ETH_OK;
2641}
2642
2643/************* Begin ethtool support *************************/
2644
2645struct mv643xx_stats {
2646 char stat_string[ETH_GSTRING_LEN];
2647 int sizeof_stat;
2648 int stat_offset;
2649};
2650
2651#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
b4de9051 2652 offsetof(struct mv643xx_private, m)
1da177e4
LT		 2653
2654static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2655 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2656 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2657 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2658 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2659 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2660 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2661 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2662 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2663 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2664 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2665 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2666 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2667 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2668 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2669 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2670 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2671 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2672 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2673 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2674 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2675 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2676 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2677 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2678 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2679 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2680 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2681 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2682 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2683 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2684 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2685 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2686 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2687 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2688 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2689 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2690 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2691 { "collision", MV643XX_STAT(mib_counters.collision) },
2692 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2693};
2694
2695#define MV643XX_STATS_LEN \
2696 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2697
b4de9051
DF		 2698static void mv643xx_get_drvinfo(struct net_device *netdev,
2699 struct ethtool_drvinfo *drvinfo)
1da177e4
LT		 2700{
2701 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2702 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2703 strncpy(drvinfo->fw_version, "N/A", 32);
2704 strncpy(drvinfo->bus_info, "mv643xx", 32);
2705 drvinfo->n_stats = MV643XX_STATS_LEN;
2706}
2707
b4de9051 2708static int mv643xx_get_stats_count(struct net_device *netdev)
1da177e4
LT		 2709{
2710 return MV643XX_STATS_LEN;
2711}
2712
b4de9051
DF		 2713static void mv643xx_get_ethtool_stats(struct net_device *netdev,
2714 struct ethtool_stats *stats, uint64_t *data)
1da177e4
LT		 2715{
2716 struct mv643xx_private *mp = netdev->priv;
2717 int i;
2718
2719 eth_update_mib_counters(mp);
2720
b4de9051 2721 for (i = 0; i < MV643XX_STATS_LEN; i++) {
1da177e4 2722 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
b4de9051 2723 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
1da177e4
LT		 2724 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
2725 }
2726}
2727
b4de9051
DF		 2728static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
2729 uint8_t *data)
1da177e4
LT		 2730{
2731 int i;
2732
2733 switch(stringset) {
2734 case ETH_SS_STATS:
2735 for (i=0; i < MV643XX_STATS_LEN; i++) {
b4de9051
DF		 2736 memcpy(data + i * ETH_GSTRING_LEN,
2737 mv643xx_gstrings_stats[i].stat_string,
2738 ETH_GSTRING_LEN);
1da177e4
LT		 2739 }
2740 break;
2741 }
2742}
2743
d0412d96
JC		 2744static u32 mv643xx_eth_get_link(struct net_device *dev)
2745{
2746 struct mv643xx_private *mp = netdev_priv(dev);
2747
2748 return mii_link_ok(&mp->mii);
2749}
2750
2751static int mv643xx_eth_nway_restart(struct net_device *dev)
2752{
2753 struct mv643xx_private *mp = netdev_priv(dev);
2754
2755 return mii_nway_restart(&mp->mii);
2756}
2757
2758static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2759{
2760 struct mv643xx_private *mp = netdev_priv(dev);
2761
2762 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2763}
2764
1da177e4
LT		 2765static struct ethtool_ops mv643xx_ethtool_ops = {
2766 .get_settings = mv643xx_get_settings,
d0412d96 2767 .set_settings = mv643xx_set_settings,
1da177e4 2768 .get_drvinfo = mv643xx_get_drvinfo,
d0412d96 2769 .get_link = mv643xx_eth_get_link,
1da177e4
LT		 2770 .get_sg = ethtool_op_get_sg,
2771 .set_sg = ethtool_op_set_sg,
2772 .get_strings = mv643xx_get_strings,
2773 .get_stats_count = mv643xx_get_stats_count,
2774 .get_ethtool_stats = mv643xx_get_ethtool_stats,
d0412d96
JC		 2775 .get_strings = mv643xx_get_strings,
2776 .get_stats_count = mv643xx_get_stats_count,
2777 .get_ethtool_stats = mv643xx_get_ethtool_stats,
2778 .nway_reset = mv643xx_eth_nway_restart,
1da177e4
LT		 2779};
2780
2781/************* End ethtool support *************************/
Linux kernel - Deliverables
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