Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
1da177e4 LT |
41 | #include <linux/tcp.h> |
42 | #include <linux/udp.h> | |
43 | #include <linux/etherdevice.h> | |
1da177e4 LT |
44 | #include <linux/delay.h> |
45 | #include <linux/ethtool.h> | |
d052d1be | 46 | #include <linux/platform_device.h> |
fbd6a754 LB |
47 | #include <linux/module.h> |
48 | #include <linux/kernel.h> | |
49 | #include <linux/spinlock.h> | |
50 | #include <linux/workqueue.h> | |
51 | #include <linux/mii.h> | |
fbd6a754 | 52 | #include <linux/mv643xx_eth.h> |
1da177e4 LT |
53 | #include <asm/io.h> |
54 | #include <asm/types.h> | |
1da177e4 | 55 | #include <asm/system.h> |
fbd6a754 | 56 | |
e5371493 | 57 | static char mv643xx_eth_driver_name[] = "mv643xx_eth"; |
c4560318 | 58 | static char mv643xx_eth_driver_version[] = "1.3"; |
c9df406f | 59 | |
fbd6a754 | 60 | |
fbd6a754 LB |
61 | /* |
62 | * Registers shared between all ports. | |
63 | */ | |
3cb4667c LB |
64 | #define PHY_ADDR 0x0000 |
65 | #define SMI_REG 0x0004 | |
45c5d3bc LB |
66 | #define SMI_BUSY 0x10000000 |
67 | #define SMI_READ_VALID 0x08000000 | |
68 | #define SMI_OPCODE_READ 0x04000000 | |
69 | #define SMI_OPCODE_WRITE 0x00000000 | |
70 | #define ERR_INT_CAUSE 0x0080 | |
71 | #define ERR_INT_SMI_DONE 0x00000010 | |
72 | #define ERR_INT_MASK 0x0084 | |
3cb4667c LB |
73 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) |
74 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
75 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
76 | #define WINDOW_BAR_ENABLE 0x0290 | |
77 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
78 | |
79 | /* | |
80 | * Per-port registers. | |
81 | */ | |
3cb4667c | 82 | #define PORT_CONFIG(p) (0x0400 + ((p) << 10)) |
d9a073ea | 83 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
3cb4667c LB |
84 | #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10)) |
85 | #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) | |
86 | #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) | |
87 | #define SDMA_CONFIG(p) (0x041c + ((p) << 10)) | |
88 | #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) | |
89 | #define PORT_STATUS(p) (0x0444 + ((p) << 10)) | |
a2a41689 | 90 | #define TX_FIFO_EMPTY 0x00000400 |
ae9ae064 | 91 | #define TX_IN_PROGRESS 0x00000080 |
2f7eb47a LB |
92 | #define PORT_SPEED_MASK 0x00000030 |
93 | #define PORT_SPEED_1000 0x00000010 | |
94 | #define PORT_SPEED_100 0x00000020 | |
95 | #define PORT_SPEED_10 0x00000000 | |
96 | #define FLOW_CONTROL_ENABLED 0x00000008 | |
97 | #define FULL_DUPLEX 0x00000004 | |
81600eea | 98 | #define LINK_UP 0x00000002 |
3cb4667c | 99 | #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) |
89df5fdc LB |
100 | #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10)) |
101 | #define TX_BW_RATE(p) (0x0450 + ((p) << 10)) | |
3cb4667c | 102 | #define TX_BW_MTU(p) (0x0458 + ((p) << 10)) |
89df5fdc | 103 | #define TX_BW_BURST(p) (0x045c + ((p) << 10)) |
3cb4667c | 104 | #define INT_CAUSE(p) (0x0460 + ((p) << 10)) |
226bb6b7 | 105 | #define INT_TX_END 0x07f80000 |
befefe21 | 106 | #define INT_RX 0x000003fc |
073a345c | 107 | #define INT_EXT 0x00000002 |
3cb4667c | 108 | #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10)) |
befefe21 LB |
109 | #define INT_EXT_LINK_PHY 0x00110000 |
110 | #define INT_EXT_TX 0x000000ff | |
3cb4667c LB |
111 | #define INT_MASK(p) (0x0468 + ((p) << 10)) |
112 | #define INT_MASK_EXT(p) (0x046c + ((p) << 10)) | |
113 | #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10)) | |
1e881592 LB |
114 | #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10)) |
115 | #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10)) | |
116 | #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10)) | |
117 | #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10)) | |
64da80a2 | 118 | #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4)) |
3cb4667c | 119 | #define RXQ_COMMAND(p) (0x0680 + ((p) << 10)) |
3d6b35bc LB |
120 | #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2)) |
121 | #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4)) | |
122 | #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4)) | |
123 | #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4)) | |
3cb4667c LB |
124 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) |
125 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
126 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
127 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 128 | |
2679a550 LB |
129 | |
130 | /* | |
131 | * SDMA configuration register. | |
132 | */ | |
cd4ccf76 | 133 | #define RX_BURST_SIZE_16_64BIT (4 << 1) |
fbd6a754 | 134 | #define BLM_RX_NO_SWAP (1 << 4) |
fbd6a754 | 135 | #define BLM_TX_NO_SWAP (1 << 5) |
cd4ccf76 | 136 | #define TX_BURST_SIZE_16_64BIT (4 << 22) |
fbd6a754 LB |
137 | |
138 | #if defined(__BIG_ENDIAN) | |
139 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
cd4ccf76 LB |
140 | RX_BURST_SIZE_16_64BIT | \ |
141 | TX_BURST_SIZE_16_64BIT | |
fbd6a754 LB |
142 | #elif defined(__LITTLE_ENDIAN) |
143 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
cd4ccf76 | 144 | RX_BURST_SIZE_16_64BIT | \ |
fbd6a754 LB |
145 | BLM_RX_NO_SWAP | \ |
146 | BLM_TX_NO_SWAP | \ | |
cd4ccf76 | 147 | TX_BURST_SIZE_16_64BIT |
fbd6a754 LB |
148 | #else |
149 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
150 | #endif | |
151 | ||
2beff77b LB |
152 | |
153 | /* | |
154 | * Port serial control register. | |
155 | */ | |
156 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
157 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | |
158 | #define SET_FULL_DUPLEX_MODE (1 << 21) | |
fbd6a754 | 159 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
2beff77b LB |
160 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
161 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | |
162 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | |
163 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | |
164 | #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) | |
165 | #define FORCE_LINK_PASS (1 << 1) | |
166 | #define SERIAL_PORT_ENABLE (1 << 0) | |
fbd6a754 | 167 | |
2b4a624d LB |
168 | #define DEFAULT_RX_QUEUE_SIZE 128 |
169 | #define DEFAULT_TX_QUEUE_SIZE 256 | |
fbd6a754 | 170 | |
fbd6a754 | 171 | |
7ca72a3b LB |
172 | /* |
173 | * RX/TX descriptors. | |
fbd6a754 LB |
174 | */ |
175 | #if defined(__BIG_ENDIAN) | |
cc9754b3 | 176 | struct rx_desc { |
fbd6a754 LB |
177 | u16 byte_cnt; /* Descriptor buffer byte count */ |
178 | u16 buf_size; /* Buffer size */ | |
179 | u32 cmd_sts; /* Descriptor command status */ | |
180 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
181 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
182 | }; | |
183 | ||
cc9754b3 | 184 | struct tx_desc { |
fbd6a754 LB |
185 | u16 byte_cnt; /* buffer byte count */ |
186 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
187 | u32 cmd_sts; /* Command/status field */ | |
188 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
189 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
190 | }; | |
191 | #elif defined(__LITTLE_ENDIAN) | |
cc9754b3 | 192 | struct rx_desc { |
fbd6a754 LB |
193 | u32 cmd_sts; /* Descriptor command status */ |
194 | u16 buf_size; /* Buffer size */ | |
195 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
196 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
197 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
198 | }; | |
199 | ||
cc9754b3 | 200 | struct tx_desc { |
fbd6a754 LB |
201 | u32 cmd_sts; /* Command/status field */ |
202 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
203 | u16 byte_cnt; /* buffer byte count */ | |
204 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
205 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
206 | }; | |
207 | #else | |
208 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
209 | #endif | |
210 | ||
7ca72a3b | 211 | /* RX & TX descriptor command */ |
cc9754b3 | 212 | #define BUFFER_OWNED_BY_DMA 0x80000000 |
7ca72a3b LB |
213 | |
214 | /* RX & TX descriptor status */ | |
cc9754b3 | 215 | #define ERROR_SUMMARY 0x00000001 |
7ca72a3b LB |
216 | |
217 | /* RX descriptor status */ | |
cc9754b3 LB |
218 | #define LAYER_4_CHECKSUM_OK 0x40000000 |
219 | #define RX_ENABLE_INTERRUPT 0x20000000 | |
220 | #define RX_FIRST_DESC 0x08000000 | |
221 | #define RX_LAST_DESC 0x04000000 | |
7ca72a3b LB |
222 | |
223 | /* TX descriptor command */ | |
cc9754b3 LB |
224 | #define TX_ENABLE_INTERRUPT 0x00800000 |
225 | #define GEN_CRC 0x00400000 | |
226 | #define TX_FIRST_DESC 0x00200000 | |
227 | #define TX_LAST_DESC 0x00100000 | |
228 | #define ZERO_PADDING 0x00080000 | |
229 | #define GEN_IP_V4_CHECKSUM 0x00040000 | |
230 | #define GEN_TCP_UDP_CHECKSUM 0x00020000 | |
231 | #define UDP_FRAME 0x00010000 | |
e32b6617 LB |
232 | #define MAC_HDR_EXTRA_4_BYTES 0x00008000 |
233 | #define MAC_HDR_EXTRA_8_BYTES 0x00000200 | |
7ca72a3b | 234 | |
cc9754b3 | 235 | #define TX_IHL_SHIFT 11 |
7ca72a3b LB |
236 | |
237 | ||
c9df406f | 238 | /* global *******************************************************************/ |
e5371493 | 239 | struct mv643xx_eth_shared_private { |
fc32b0e2 LB |
240 | /* |
241 | * Ethernet controller base address. | |
242 | */ | |
cc9754b3 | 243 | void __iomem *base; |
c9df406f | 244 | |
fc0eb9f2 LB |
245 | /* |
246 | * Points at the right SMI instance to use. | |
247 | */ | |
248 | struct mv643xx_eth_shared_private *smi; | |
249 | ||
fc32b0e2 LB |
250 | /* |
251 | * Protects access to SMI_REG, which is shared between ports. | |
252 | */ | |
2b3ba0e3 | 253 | struct mutex phy_lock; |
c9df406f | 254 | |
45c5d3bc LB |
255 | /* |
256 | * If we have access to the error interrupt pin (which is | |
257 | * somewhat misnamed as it not only reflects internal errors | |
258 | * but also reflects SMI completion), use that to wait for | |
259 | * SMI access completion instead of polling the SMI busy bit. | |
260 | */ | |
261 | int err_interrupt; | |
262 | wait_queue_head_t smi_busy_wait; | |
263 | ||
fc32b0e2 LB |
264 | /* |
265 | * Per-port MBUS window access register value. | |
266 | */ | |
c9df406f LB |
267 | u32 win_protect; |
268 | ||
fc32b0e2 LB |
269 | /* |
270 | * Hardware-specific parameters. | |
271 | */ | |
c9df406f | 272 | unsigned int t_clk; |
773fc3ee | 273 | int extended_rx_coal_limit; |
457b1d5a | 274 | int tx_bw_control; |
c9df406f LB |
275 | }; |
276 | ||
457b1d5a LB |
277 | #define TX_BW_CONTROL_ABSENT 0 |
278 | #define TX_BW_CONTROL_OLD_LAYOUT 1 | |
279 | #define TX_BW_CONTROL_NEW_LAYOUT 2 | |
280 | ||
c9df406f LB |
281 | |
282 | /* per-port *****************************************************************/ | |
e5371493 | 283 | struct mib_counters { |
fbd6a754 LB |
284 | u64 good_octets_received; |
285 | u32 bad_octets_received; | |
286 | u32 internal_mac_transmit_err; | |
287 | u32 good_frames_received; | |
288 | u32 bad_frames_received; | |
289 | u32 broadcast_frames_received; | |
290 | u32 multicast_frames_received; | |
291 | u32 frames_64_octets; | |
292 | u32 frames_65_to_127_octets; | |
293 | u32 frames_128_to_255_octets; | |
294 | u32 frames_256_to_511_octets; | |
295 | u32 frames_512_to_1023_octets; | |
296 | u32 frames_1024_to_max_octets; | |
297 | u64 good_octets_sent; | |
298 | u32 good_frames_sent; | |
299 | u32 excessive_collision; | |
300 | u32 multicast_frames_sent; | |
301 | u32 broadcast_frames_sent; | |
302 | u32 unrec_mac_control_received; | |
303 | u32 fc_sent; | |
304 | u32 good_fc_received; | |
305 | u32 bad_fc_received; | |
306 | u32 undersize_received; | |
307 | u32 fragments_received; | |
308 | u32 oversize_received; | |
309 | u32 jabber_received; | |
310 | u32 mac_receive_error; | |
311 | u32 bad_crc_event; | |
312 | u32 collision; | |
313 | u32 late_collision; | |
314 | }; | |
315 | ||
8a578111 | 316 | struct rx_queue { |
64da80a2 LB |
317 | int index; |
318 | ||
8a578111 LB |
319 | int rx_ring_size; |
320 | ||
321 | int rx_desc_count; | |
322 | int rx_curr_desc; | |
323 | int rx_used_desc; | |
324 | ||
325 | struct rx_desc *rx_desc_area; | |
326 | dma_addr_t rx_desc_dma; | |
327 | int rx_desc_area_size; | |
328 | struct sk_buff **rx_skb; | |
8a578111 LB |
329 | }; |
330 | ||
13d64285 | 331 | struct tx_queue { |
3d6b35bc LB |
332 | int index; |
333 | ||
13d64285 | 334 | int tx_ring_size; |
fbd6a754 | 335 | |
13d64285 LB |
336 | int tx_desc_count; |
337 | int tx_curr_desc; | |
338 | int tx_used_desc; | |
fbd6a754 | 339 | |
5daffe94 | 340 | struct tx_desc *tx_desc_area; |
fbd6a754 LB |
341 | dma_addr_t tx_desc_dma; |
342 | int tx_desc_area_size; | |
99ab08e0 LB |
343 | |
344 | struct sk_buff_head tx_skb; | |
8fd89211 LB |
345 | |
346 | unsigned long tx_packets; | |
347 | unsigned long tx_bytes; | |
348 | unsigned long tx_dropped; | |
13d64285 LB |
349 | }; |
350 | ||
351 | struct mv643xx_eth_private { | |
352 | struct mv643xx_eth_shared_private *shared; | |
fc32b0e2 | 353 | int port_num; |
13d64285 | 354 | |
fc32b0e2 | 355 | struct net_device *dev; |
fbd6a754 | 356 | |
fc32b0e2 | 357 | int phy_addr; |
fbd6a754 | 358 | |
fc32b0e2 LB |
359 | struct mib_counters mib_counters; |
360 | struct work_struct tx_timeout_task; | |
fbd6a754 | 361 | struct mii_if_info mii; |
8a578111 | 362 | |
1fa38c58 LB |
363 | struct napi_struct napi; |
364 | u8 work_link; | |
365 | u8 work_tx; | |
366 | u8 work_tx_end; | |
367 | u8 work_rx; | |
368 | u8 work_rx_refill; | |
369 | u8 work_rx_oom; | |
370 | ||
8a578111 LB |
371 | /* |
372 | * RX state. | |
373 | */ | |
374 | int default_rx_ring_size; | |
375 | unsigned long rx_desc_sram_addr; | |
376 | int rx_desc_sram_size; | |
f7981c1c | 377 | int rxq_count; |
2257e05c | 378 | struct timer_list rx_oom; |
64da80a2 | 379 | struct rx_queue rxq[8]; |
13d64285 LB |
380 | |
381 | /* | |
382 | * TX state. | |
383 | */ | |
384 | int default_tx_ring_size; | |
385 | unsigned long tx_desc_sram_addr; | |
386 | int tx_desc_sram_size; | |
f7981c1c | 387 | int txq_count; |
3d6b35bc | 388 | struct tx_queue txq[8]; |
fbd6a754 | 389 | }; |
1da177e4 | 390 | |
fbd6a754 | 391 | |
c9df406f | 392 | /* port register accessors **************************************************/ |
e5371493 | 393 | static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 394 | { |
cc9754b3 | 395 | return readl(mp->shared->base + offset); |
c9df406f | 396 | } |
fbd6a754 | 397 | |
e5371493 | 398 | static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) |
c9df406f | 399 | { |
cc9754b3 | 400 | writel(data, mp->shared->base + offset); |
c9df406f | 401 | } |
fbd6a754 | 402 | |
fbd6a754 | 403 | |
c9df406f | 404 | /* rxq/txq helper functions *************************************************/ |
8a578111 | 405 | static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) |
c9df406f | 406 | { |
64da80a2 | 407 | return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); |
c9df406f | 408 | } |
fbd6a754 | 409 | |
13d64285 LB |
410 | static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) |
411 | { | |
3d6b35bc | 412 | return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); |
13d64285 LB |
413 | } |
414 | ||
8a578111 | 415 | static void rxq_enable(struct rx_queue *rxq) |
c9df406f | 416 | { |
8a578111 | 417 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
64da80a2 | 418 | wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index); |
8a578111 | 419 | } |
1da177e4 | 420 | |
8a578111 LB |
421 | static void rxq_disable(struct rx_queue *rxq) |
422 | { | |
423 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); | |
64da80a2 | 424 | u8 mask = 1 << rxq->index; |
1da177e4 | 425 | |
8a578111 LB |
426 | wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8); |
427 | while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask) | |
428 | udelay(10); | |
c9df406f LB |
429 | } |
430 | ||
6b368f68 LB |
431 | static void txq_reset_hw_ptr(struct tx_queue *txq) |
432 | { | |
433 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
434 | int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index); | |
435 | u32 addr; | |
436 | ||
437 | addr = (u32)txq->tx_desc_dma; | |
438 | addr += txq->tx_curr_desc * sizeof(struct tx_desc); | |
439 | wrl(mp, off, addr); | |
440 | } | |
441 | ||
13d64285 | 442 | static void txq_enable(struct tx_queue *txq) |
1da177e4 | 443 | { |
13d64285 | 444 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 445 | wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index); |
1da177e4 LT |
446 | } |
447 | ||
13d64285 | 448 | static void txq_disable(struct tx_queue *txq) |
1da177e4 | 449 | { |
13d64285 | 450 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 451 | u8 mask = 1 << txq->index; |
c9df406f | 452 | |
13d64285 LB |
453 | wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8); |
454 | while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask) | |
455 | udelay(10); | |
456 | } | |
457 | ||
1fa38c58 | 458 | static void txq_maybe_wake(struct tx_queue *txq) |
13d64285 LB |
459 | { |
460 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
e5ef1de1 | 461 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
3d6b35bc | 462 | |
8fd89211 LB |
463 | if (netif_tx_queue_stopped(nq)) { |
464 | __netif_tx_lock(nq, smp_processor_id()); | |
465 | if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1) | |
466 | netif_tx_wake_queue(nq); | |
467 | __netif_tx_unlock(nq); | |
468 | } | |
1da177e4 LT |
469 | } |
470 | ||
c9df406f | 471 | |
1fa38c58 | 472 | /* rx napi ******************************************************************/ |
8a578111 | 473 | static int rxq_process(struct rx_queue *rxq, int budget) |
1da177e4 | 474 | { |
8a578111 LB |
475 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
476 | struct net_device_stats *stats = &mp->dev->stats; | |
477 | int rx; | |
1da177e4 | 478 | |
8a578111 | 479 | rx = 0; |
9e1f3772 | 480 | while (rx < budget && rxq->rx_desc_count) { |
fc32b0e2 | 481 | struct rx_desc *rx_desc; |
96587661 | 482 | unsigned int cmd_sts; |
fc32b0e2 | 483 | struct sk_buff *skb; |
6b8f90c2 | 484 | u16 byte_cnt; |
ff561eef | 485 | |
8a578111 | 486 | rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; |
1da177e4 | 487 | |
96587661 | 488 | cmd_sts = rx_desc->cmd_sts; |
2257e05c | 489 | if (cmd_sts & BUFFER_OWNED_BY_DMA) |
96587661 | 490 | break; |
96587661 | 491 | rmb(); |
1da177e4 | 492 | |
8a578111 LB |
493 | skb = rxq->rx_skb[rxq->rx_curr_desc]; |
494 | rxq->rx_skb[rxq->rx_curr_desc] = NULL; | |
ff561eef | 495 | |
9da78745 LB |
496 | rxq->rx_curr_desc++; |
497 | if (rxq->rx_curr_desc == rxq->rx_ring_size) | |
498 | rxq->rx_curr_desc = 0; | |
ff561eef | 499 | |
3a499481 | 500 | dma_unmap_single(NULL, rx_desc->buf_ptr, |
abe78717 | 501 | rx_desc->buf_size, DMA_FROM_DEVICE); |
8a578111 LB |
502 | rxq->rx_desc_count--; |
503 | rx++; | |
b1dd9ca1 | 504 | |
1fa38c58 LB |
505 | mp->work_rx_refill |= 1 << rxq->index; |
506 | ||
6b8f90c2 LB |
507 | byte_cnt = rx_desc->byte_cnt; |
508 | ||
468d09f8 DF |
509 | /* |
510 | * Update statistics. | |
fc32b0e2 LB |
511 | * |
512 | * Note that the descriptor byte count includes 2 dummy | |
513 | * bytes automatically inserted by the hardware at the | |
514 | * start of the packet (which we don't count), and a 4 | |
515 | * byte CRC at the end of the packet (which we do count). | |
468d09f8 | 516 | */ |
1da177e4 | 517 | stats->rx_packets++; |
6b8f90c2 | 518 | stats->rx_bytes += byte_cnt - 2; |
96587661 | 519 | |
1da177e4 | 520 | /* |
fc32b0e2 LB |
521 | * In case we received a packet without first / last bits |
522 | * on, or the error summary bit is set, the packet needs | |
523 | * to be dropped. | |
1da177e4 | 524 | */ |
96587661 | 525 | if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != |
cc9754b3 | 526 | (RX_FIRST_DESC | RX_LAST_DESC)) |
96587661 | 527 | || (cmd_sts & ERROR_SUMMARY)) { |
1da177e4 | 528 | stats->rx_dropped++; |
fc32b0e2 | 529 | |
96587661 | 530 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != |
cc9754b3 | 531 | (RX_FIRST_DESC | RX_LAST_DESC)) { |
1da177e4 | 532 | if (net_ratelimit()) |
fc32b0e2 LB |
533 | dev_printk(KERN_ERR, &mp->dev->dev, |
534 | "received packet spanning " | |
535 | "multiple descriptors\n"); | |
1da177e4 | 536 | } |
fc32b0e2 | 537 | |
96587661 | 538 | if (cmd_sts & ERROR_SUMMARY) |
1da177e4 LT |
539 | stats->rx_errors++; |
540 | ||
78fff83b | 541 | dev_kfree_skb(skb); |
1da177e4 LT |
542 | } else { |
543 | /* | |
544 | * The -4 is for the CRC in the trailer of the | |
545 | * received packet | |
546 | */ | |
6b8f90c2 | 547 | skb_put(skb, byte_cnt - 2 - 4); |
1da177e4 | 548 | |
96587661 | 549 | if (cmd_sts & LAYER_4_CHECKSUM_OK) { |
1da177e4 LT |
550 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
551 | skb->csum = htons( | |
96587661 | 552 | (cmd_sts & 0x0007fff8) >> 3); |
1da177e4 | 553 | } |
8a578111 | 554 | skb->protocol = eth_type_trans(skb, mp->dev); |
1da177e4 | 555 | netif_receive_skb(skb); |
1da177e4 | 556 | } |
fc32b0e2 | 557 | |
8a578111 | 558 | mp->dev->last_rx = jiffies; |
1da177e4 | 559 | } |
fc32b0e2 | 560 | |
1fa38c58 LB |
561 | if (rx < budget) |
562 | mp->work_rx &= ~(1 << rxq->index); | |
563 | ||
8a578111 | 564 | return rx; |
1da177e4 LT |
565 | } |
566 | ||
1fa38c58 | 567 | static int rxq_refill(struct rx_queue *rxq, int budget) |
d0412d96 | 568 | { |
1fa38c58 LB |
569 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
570 | int skb_size; | |
571 | int refilled; | |
8a578111 | 572 | |
1fa38c58 LB |
573 | /* |
574 | * Reserve 2+14 bytes for an ethernet header (the hardware | |
575 | * automatically prepends 2 bytes of dummy data to each | |
576 | * received packet), 16 bytes for up to four VLAN tags, and | |
577 | * 4 bytes for the trailing FCS -- 36 bytes total. | |
578 | */ | |
579 | skb_size = rxq_to_mp(rxq)->dev->mtu + 36; | |
d0412d96 | 580 | |
1fa38c58 LB |
581 | /* |
582 | * Make sure that the skb size is a multiple of 8 bytes, as | |
583 | * the lower three bits of the receive descriptor's buffer | |
584 | * size field are ignored by the hardware. | |
585 | */ | |
586 | skb_size = (skb_size + 7) & ~7; | |
4dfc1c87 | 587 | |
1fa38c58 LB |
588 | refilled = 0; |
589 | while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { | |
590 | struct sk_buff *skb; | |
591 | int unaligned; | |
592 | int rx; | |
d0412d96 | 593 | |
1fa38c58 LB |
594 | skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1); |
595 | if (skb == NULL) { | |
596 | mp->work_rx_oom |= 1 << rxq->index; | |
597 | goto oom; | |
598 | } | |
d0412d96 | 599 | |
1fa38c58 LB |
600 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
601 | if (unaligned) | |
602 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); | |
2257e05c | 603 | |
1fa38c58 LB |
604 | refilled++; |
605 | rxq->rx_desc_count++; | |
c9df406f | 606 | |
1fa38c58 LB |
607 | rx = rxq->rx_used_desc++; |
608 | if (rxq->rx_used_desc == rxq->rx_ring_size) | |
609 | rxq->rx_used_desc = 0; | |
2257e05c | 610 | |
1fa38c58 LB |
611 | rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data, |
612 | skb_size, DMA_FROM_DEVICE); | |
613 | rxq->rx_desc_area[rx].buf_size = skb_size; | |
614 | rxq->rx_skb[rx] = skb; | |
615 | wmb(); | |
616 | rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA | | |
617 | RX_ENABLE_INTERRUPT; | |
618 | wmb(); | |
2257e05c | 619 | |
1fa38c58 LB |
620 | /* |
621 | * The hardware automatically prepends 2 bytes of | |
622 | * dummy data to each received packet, so that the | |
623 | * IP header ends up 16-byte aligned. | |
624 | */ | |
625 | skb_reserve(skb, 2); | |
626 | } | |
627 | ||
628 | if (refilled < budget) | |
629 | mp->work_rx_refill &= ~(1 << rxq->index); | |
630 | ||
631 | oom: | |
632 | return refilled; | |
d0412d96 JC |
633 | } |
634 | ||
c9df406f LB |
635 | |
636 | /* tx ***********************************************************************/ | |
c9df406f | 637 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 638 | { |
13d64285 | 639 | int frag; |
1da177e4 | 640 | |
c9df406f | 641 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
13d64285 LB |
642 | skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; |
643 | if (fragp->size <= 8 && fragp->page_offset & 7) | |
c9df406f | 644 | return 1; |
1da177e4 | 645 | } |
13d64285 | 646 | |
c9df406f LB |
647 | return 0; |
648 | } | |
7303fde8 | 649 | |
13d64285 | 650 | static int txq_alloc_desc_index(struct tx_queue *txq) |
c9df406f LB |
651 | { |
652 | int tx_desc_curr; | |
d0412d96 | 653 | |
13d64285 | 654 | BUG_ON(txq->tx_desc_count >= txq->tx_ring_size); |
1da177e4 | 655 | |
9da78745 LB |
656 | tx_desc_curr = txq->tx_curr_desc++; |
657 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
658 | txq->tx_curr_desc = 0; | |
e4d00fa9 | 659 | |
13d64285 | 660 | BUG_ON(txq->tx_curr_desc == txq->tx_used_desc); |
468d09f8 | 661 | |
c9df406f LB |
662 | return tx_desc_curr; |
663 | } | |
468d09f8 | 664 | |
13d64285 | 665 | static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) |
c9df406f | 666 | { |
13d64285 | 667 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 668 | int frag; |
1da177e4 | 669 | |
13d64285 LB |
670 | for (frag = 0; frag < nr_frags; frag++) { |
671 | skb_frag_t *this_frag; | |
672 | int tx_index; | |
673 | struct tx_desc *desc; | |
674 | ||
675 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
676 | tx_index = txq_alloc_desc_index(txq); | |
677 | desc = &txq->tx_desc_area[tx_index]; | |
678 | ||
679 | /* | |
680 | * The last fragment will generate an interrupt | |
681 | * which will free the skb on TX completion. | |
682 | */ | |
683 | if (frag == nr_frags - 1) { | |
684 | desc->cmd_sts = BUFFER_OWNED_BY_DMA | | |
685 | ZERO_PADDING | TX_LAST_DESC | | |
686 | TX_ENABLE_INTERRUPT; | |
13d64285 LB |
687 | } else { |
688 | desc->cmd_sts = BUFFER_OWNED_BY_DMA; | |
13d64285 LB |
689 | } |
690 | ||
c9df406f LB |
691 | desc->l4i_chk = 0; |
692 | desc->byte_cnt = this_frag->size; | |
693 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
694 | this_frag->page_offset, | |
695 | this_frag->size, | |
696 | DMA_TO_DEVICE); | |
697 | } | |
1da177e4 LT |
698 | } |
699 | ||
c9df406f LB |
700 | static inline __be16 sum16_as_be(__sum16 sum) |
701 | { | |
702 | return (__force __be16)sum; | |
703 | } | |
1da177e4 | 704 | |
13d64285 | 705 | static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) |
1da177e4 | 706 | { |
8fa89bf5 | 707 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
13d64285 | 708 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 709 | int tx_index; |
cc9754b3 | 710 | struct tx_desc *desc; |
c9df406f LB |
711 | u32 cmd_sts; |
712 | int length; | |
1da177e4 | 713 | |
cc9754b3 | 714 | cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; |
1da177e4 | 715 | |
13d64285 LB |
716 | tx_index = txq_alloc_desc_index(txq); |
717 | desc = &txq->tx_desc_area[tx_index]; | |
c9df406f LB |
718 | |
719 | if (nr_frags) { | |
13d64285 | 720 | txq_submit_frag_skb(txq, skb); |
c9df406f | 721 | length = skb_headlen(skb); |
c9df406f | 722 | } else { |
cc9754b3 | 723 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; |
c9df406f | 724 | length = skb->len; |
c9df406f LB |
725 | } |
726 | ||
727 | desc->byte_cnt = length; | |
728 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
729 | ||
730 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
e32b6617 LB |
731 | int mac_hdr_len; |
732 | ||
733 | BUG_ON(skb->protocol != htons(ETH_P_IP) && | |
734 | skb->protocol != htons(ETH_P_8021Q)); | |
c9df406f | 735 | |
cc9754b3 LB |
736 | cmd_sts |= GEN_TCP_UDP_CHECKSUM | |
737 | GEN_IP_V4_CHECKSUM | | |
738 | ip_hdr(skb)->ihl << TX_IHL_SHIFT; | |
c9df406f | 739 | |
e32b6617 LB |
740 | mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data; |
741 | switch (mac_hdr_len - ETH_HLEN) { | |
742 | case 0: | |
743 | break; | |
744 | case 4: | |
745 | cmd_sts |= MAC_HDR_EXTRA_4_BYTES; | |
746 | break; | |
747 | case 8: | |
748 | cmd_sts |= MAC_HDR_EXTRA_8_BYTES; | |
749 | break; | |
750 | case 12: | |
751 | cmd_sts |= MAC_HDR_EXTRA_4_BYTES; | |
752 | cmd_sts |= MAC_HDR_EXTRA_8_BYTES; | |
753 | break; | |
754 | default: | |
755 | if (net_ratelimit()) | |
756 | dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev, | |
757 | "mac header length is %d?!\n", mac_hdr_len); | |
758 | break; | |
759 | } | |
760 | ||
c9df406f LB |
761 | switch (ip_hdr(skb)->protocol) { |
762 | case IPPROTO_UDP: | |
cc9754b3 | 763 | cmd_sts |= UDP_FRAME; |
c9df406f LB |
764 | desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); |
765 | break; | |
766 | case IPPROTO_TCP: | |
767 | desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); | |
768 | break; | |
769 | default: | |
770 | BUG(); | |
771 | } | |
772 | } else { | |
773 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ | |
cc9754b3 | 774 | cmd_sts |= 5 << TX_IHL_SHIFT; |
c9df406f LB |
775 | desc->l4i_chk = 0; |
776 | } | |
777 | ||
99ab08e0 LB |
778 | __skb_queue_tail(&txq->tx_skb, skb); |
779 | ||
c9df406f LB |
780 | /* ensure all other descriptors are written before first cmd_sts */ |
781 | wmb(); | |
782 | desc->cmd_sts = cmd_sts; | |
783 | ||
1fa38c58 LB |
784 | /* clear TX_END status */ |
785 | mp->work_tx_end &= ~(1 << txq->index); | |
8fa89bf5 | 786 | |
c9df406f LB |
787 | /* ensure all descriptors are written before poking hardware */ |
788 | wmb(); | |
13d64285 | 789 | txq_enable(txq); |
c9df406f | 790 | |
13d64285 | 791 | txq->tx_desc_count += nr_frags + 1; |
1da177e4 | 792 | } |
1da177e4 | 793 | |
fc32b0e2 | 794 | static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 795 | { |
e5371493 | 796 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
e5ef1de1 | 797 | int queue; |
13d64285 | 798 | struct tx_queue *txq; |
e5ef1de1 | 799 | struct netdev_queue *nq; |
e5ef1de1 | 800 | int entries_left; |
afdb57a2 | 801 | |
8fd89211 LB |
802 | queue = skb_get_queue_mapping(skb); |
803 | txq = mp->txq + queue; | |
804 | nq = netdev_get_tx_queue(dev, queue); | |
805 | ||
c9df406f | 806 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
8fd89211 | 807 | txq->tx_dropped++; |
fc32b0e2 LB |
808 | dev_printk(KERN_DEBUG, &dev->dev, |
809 | "failed to linearize skb with tiny " | |
810 | "unaligned fragment\n"); | |
c9df406f LB |
811 | return NETDEV_TX_BUSY; |
812 | } | |
813 | ||
17cd0a59 | 814 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { |
e5ef1de1 LB |
815 | if (net_ratelimit()) |
816 | dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n"); | |
3d6b35bc LB |
817 | kfree_skb(skb); |
818 | return NETDEV_TX_OK; | |
c9df406f LB |
819 | } |
820 | ||
13d64285 | 821 | txq_submit_skb(txq, skb); |
8fd89211 LB |
822 | txq->tx_bytes += skb->len; |
823 | txq->tx_packets++; | |
c9df406f LB |
824 | dev->trans_start = jiffies; |
825 | ||
e5ef1de1 LB |
826 | entries_left = txq->tx_ring_size - txq->tx_desc_count; |
827 | if (entries_left < MAX_SKB_FRAGS + 1) | |
828 | netif_tx_stop_queue(nq); | |
c9df406f | 829 | |
c9df406f | 830 | return NETDEV_TX_OK; |
1da177e4 LT |
831 | } |
832 | ||
c9df406f | 833 | |
1fa38c58 LB |
834 | /* tx napi ******************************************************************/ |
835 | static void txq_kick(struct tx_queue *txq) | |
836 | { | |
837 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 838 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
839 | u32 hw_desc_ptr; |
840 | u32 expected_ptr; | |
841 | ||
8fd89211 | 842 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 LB |
843 | |
844 | if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index)) | |
845 | goto out; | |
846 | ||
847 | hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index)); | |
848 | expected_ptr = (u32)txq->tx_desc_dma + | |
849 | txq->tx_curr_desc * sizeof(struct tx_desc); | |
850 | ||
851 | if (hw_desc_ptr != expected_ptr) | |
852 | txq_enable(txq); | |
853 | ||
854 | out: | |
8fd89211 | 855 | __netif_tx_unlock(nq); |
1fa38c58 LB |
856 | |
857 | mp->work_tx_end &= ~(1 << txq->index); | |
858 | } | |
859 | ||
860 | static int txq_reclaim(struct tx_queue *txq, int budget, int force) | |
861 | { | |
862 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 863 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
864 | int reclaimed; |
865 | ||
8fd89211 | 866 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 LB |
867 | |
868 | reclaimed = 0; | |
869 | while (reclaimed < budget && txq->tx_desc_count > 0) { | |
870 | int tx_index; | |
871 | struct tx_desc *desc; | |
872 | u32 cmd_sts; | |
873 | struct sk_buff *skb; | |
1fa38c58 LB |
874 | |
875 | tx_index = txq->tx_used_desc; | |
876 | desc = &txq->tx_desc_area[tx_index]; | |
877 | cmd_sts = desc->cmd_sts; | |
878 | ||
879 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { | |
880 | if (!force) | |
881 | break; | |
882 | desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; | |
883 | } | |
884 | ||
885 | txq->tx_used_desc = tx_index + 1; | |
886 | if (txq->tx_used_desc == txq->tx_ring_size) | |
887 | txq->tx_used_desc = 0; | |
888 | ||
889 | reclaimed++; | |
890 | txq->tx_desc_count--; | |
891 | ||
99ab08e0 LB |
892 | skb = NULL; |
893 | if (cmd_sts & TX_LAST_DESC) | |
894 | skb = __skb_dequeue(&txq->tx_skb); | |
1fa38c58 LB |
895 | |
896 | if (cmd_sts & ERROR_SUMMARY) { | |
897 | dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n"); | |
898 | mp->dev->stats.tx_errors++; | |
899 | } | |
900 | ||
a418950c LB |
901 | if (cmd_sts & TX_FIRST_DESC) { |
902 | dma_unmap_single(NULL, desc->buf_ptr, | |
903 | desc->byte_cnt, DMA_TO_DEVICE); | |
904 | } else { | |
905 | dma_unmap_page(NULL, desc->buf_ptr, | |
906 | desc->byte_cnt, DMA_TO_DEVICE); | |
907 | } | |
1fa38c58 LB |
908 | |
909 | if (skb) | |
910 | dev_kfree_skb(skb); | |
1fa38c58 LB |
911 | } |
912 | ||
8fd89211 LB |
913 | __netif_tx_unlock(nq); |
914 | ||
1fa38c58 LB |
915 | if (reclaimed < budget) |
916 | mp->work_tx &= ~(1 << txq->index); | |
917 | ||
1fa38c58 LB |
918 | return reclaimed; |
919 | } | |
920 | ||
921 | ||
89df5fdc LB |
922 | /* tx rate control **********************************************************/ |
923 | /* | |
924 | * Set total maximum TX rate (shared by all TX queues for this port) | |
925 | * to 'rate' bits per second, with a maximum burst of 'burst' bytes. | |
926 | */ | |
927 | static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) | |
928 | { | |
929 | int token_rate; | |
930 | int mtu; | |
931 | int bucket_size; | |
932 | ||
933 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
934 | if (token_rate > 1023) | |
935 | token_rate = 1023; | |
936 | ||
937 | mtu = (mp->dev->mtu + 255) >> 8; | |
938 | if (mtu > 63) | |
939 | mtu = 63; | |
940 | ||
941 | bucket_size = (burst + 255) >> 8; | |
942 | if (bucket_size > 65535) | |
943 | bucket_size = 65535; | |
944 | ||
457b1d5a LB |
945 | switch (mp->shared->tx_bw_control) { |
946 | case TX_BW_CONTROL_OLD_LAYOUT: | |
1e881592 LB |
947 | wrl(mp, TX_BW_RATE(mp->port_num), token_rate); |
948 | wrl(mp, TX_BW_MTU(mp->port_num), mtu); | |
949 | wrl(mp, TX_BW_BURST(mp->port_num), bucket_size); | |
457b1d5a LB |
950 | break; |
951 | case TX_BW_CONTROL_NEW_LAYOUT: | |
952 | wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate); | |
953 | wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu); | |
954 | wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size); | |
955 | break; | |
1e881592 | 956 | } |
89df5fdc LB |
957 | } |
958 | ||
959 | static void txq_set_rate(struct tx_queue *txq, int rate, int burst) | |
960 | { | |
961 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
962 | int token_rate; | |
963 | int bucket_size; | |
964 | ||
965 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
966 | if (token_rate > 1023) | |
967 | token_rate = 1023; | |
968 | ||
969 | bucket_size = (burst + 255) >> 8; | |
970 | if (bucket_size > 65535) | |
971 | bucket_size = 65535; | |
972 | ||
3d6b35bc LB |
973 | wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14); |
974 | wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index), | |
89df5fdc LB |
975 | (bucket_size << 10) | token_rate); |
976 | } | |
977 | ||
978 | static void txq_set_fixed_prio_mode(struct tx_queue *txq) | |
979 | { | |
980 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
981 | int off; | |
982 | u32 val; | |
983 | ||
984 | /* | |
985 | * Turn on fixed priority mode. | |
986 | */ | |
457b1d5a LB |
987 | off = 0; |
988 | switch (mp->shared->tx_bw_control) { | |
989 | case TX_BW_CONTROL_OLD_LAYOUT: | |
1e881592 | 990 | off = TXQ_FIX_PRIO_CONF(mp->port_num); |
457b1d5a LB |
991 | break; |
992 | case TX_BW_CONTROL_NEW_LAYOUT: | |
993 | off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num); | |
994 | break; | |
995 | } | |
89df5fdc | 996 | |
457b1d5a LB |
997 | if (off) { |
998 | val = rdl(mp, off); | |
999 | val |= 1 << txq->index; | |
1000 | wrl(mp, off, val); | |
1001 | } | |
89df5fdc LB |
1002 | } |
1003 | ||
1004 | static void txq_set_wrr(struct tx_queue *txq, int weight) | |
1005 | { | |
1006 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1007 | int off; | |
1008 | u32 val; | |
1009 | ||
1010 | /* | |
1011 | * Turn off fixed priority mode. | |
1012 | */ | |
457b1d5a LB |
1013 | off = 0; |
1014 | switch (mp->shared->tx_bw_control) { | |
1015 | case TX_BW_CONTROL_OLD_LAYOUT: | |
1e881592 | 1016 | off = TXQ_FIX_PRIO_CONF(mp->port_num); |
457b1d5a LB |
1017 | break; |
1018 | case TX_BW_CONTROL_NEW_LAYOUT: | |
1019 | off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num); | |
1020 | break; | |
1021 | } | |
89df5fdc | 1022 | |
457b1d5a LB |
1023 | if (off) { |
1024 | val = rdl(mp, off); | |
1025 | val &= ~(1 << txq->index); | |
1026 | wrl(mp, off, val); | |
89df5fdc | 1027 | |
457b1d5a LB |
1028 | /* |
1029 | * Configure WRR weight for this queue. | |
1030 | */ | |
1031 | off = TXQ_BW_WRR_CONF(mp->port_num, txq->index); | |
89df5fdc | 1032 | |
457b1d5a LB |
1033 | val = rdl(mp, off); |
1034 | val = (val & ~0xff) | (weight & 0xff); | |
1035 | wrl(mp, off, val); | |
1036 | } | |
89df5fdc LB |
1037 | } |
1038 | ||
1039 | ||
c9df406f | 1040 | /* mii management interface *************************************************/ |
45c5d3bc LB |
1041 | static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id) |
1042 | { | |
1043 | struct mv643xx_eth_shared_private *msp = dev_id; | |
1044 | ||
1045 | if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) { | |
1046 | writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE); | |
1047 | wake_up(&msp->smi_busy_wait); | |
1048 | return IRQ_HANDLED; | |
1049 | } | |
1050 | ||
1051 | return IRQ_NONE; | |
1052 | } | |
c9df406f | 1053 | |
45c5d3bc | 1054 | static int smi_is_done(struct mv643xx_eth_shared_private *msp) |
1da177e4 | 1055 | { |
45c5d3bc LB |
1056 | return !(readl(msp->base + SMI_REG) & SMI_BUSY); |
1057 | } | |
1da177e4 | 1058 | |
45c5d3bc LB |
1059 | static int smi_wait_ready(struct mv643xx_eth_shared_private *msp) |
1060 | { | |
1061 | if (msp->err_interrupt == NO_IRQ) { | |
1062 | int i; | |
c9df406f | 1063 | |
45c5d3bc LB |
1064 | for (i = 0; !smi_is_done(msp); i++) { |
1065 | if (i == 10) | |
1066 | return -ETIMEDOUT; | |
1067 | msleep(10); | |
c9df406f | 1068 | } |
45c5d3bc LB |
1069 | |
1070 | return 0; | |
1071 | } | |
1072 | ||
1073 | if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp), | |
1074 | msecs_to_jiffies(100))) | |
1075 | return -ETIMEDOUT; | |
1076 | ||
1077 | return 0; | |
1078 | } | |
1079 | ||
1080 | static int smi_reg_read(struct mv643xx_eth_private *mp, | |
1081 | unsigned int addr, unsigned int reg) | |
1082 | { | |
fc0eb9f2 | 1083 | struct mv643xx_eth_shared_private *msp = mp->shared->smi; |
45c5d3bc LB |
1084 | void __iomem *smi_reg = msp->base + SMI_REG; |
1085 | int ret; | |
1086 | ||
1087 | mutex_lock(&msp->phy_lock); | |
1088 | ||
1089 | if (smi_wait_ready(msp)) { | |
1090 | printk("%s: SMI bus busy timeout\n", mp->dev->name); | |
1091 | ret = -ETIMEDOUT; | |
1092 | goto out; | |
1da177e4 LT |
1093 | } |
1094 | ||
fc32b0e2 | 1095 | writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); |
1da177e4 | 1096 | |
45c5d3bc LB |
1097 | if (smi_wait_ready(msp)) { |
1098 | printk("%s: SMI bus busy timeout\n", mp->dev->name); | |
1099 | ret = -ETIMEDOUT; | |
1100 | goto out; | |
1101 | } | |
1102 | ||
1103 | ret = readl(smi_reg); | |
1104 | if (!(ret & SMI_READ_VALID)) { | |
1105 | printk("%s: SMI bus read not valid\n", mp->dev->name); | |
1106 | ret = -ENODEV; | |
1107 | goto out; | |
c9df406f LB |
1108 | } |
1109 | ||
45c5d3bc LB |
1110 | ret &= 0xffff; |
1111 | ||
c9df406f | 1112 | out: |
45c5d3bc LB |
1113 | mutex_unlock(&msp->phy_lock); |
1114 | ||
1115 | return ret; | |
1da177e4 LT |
1116 | } |
1117 | ||
45c5d3bc LB |
1118 | static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr, |
1119 | unsigned int reg, unsigned int value) | |
1da177e4 | 1120 | { |
fc0eb9f2 | 1121 | struct mv643xx_eth_shared_private *msp = mp->shared->smi; |
45c5d3bc | 1122 | void __iomem *smi_reg = msp->base + SMI_REG; |
1da177e4 | 1123 | |
45c5d3bc | 1124 | mutex_lock(&msp->phy_lock); |
c9df406f | 1125 | |
45c5d3bc LB |
1126 | if (smi_wait_ready(msp)) { |
1127 | printk("%s: SMI bus busy timeout\n", mp->dev->name); | |
1128 | mutex_unlock(&msp->phy_lock); | |
1129 | return -ETIMEDOUT; | |
1da177e4 LT |
1130 | } |
1131 | ||
fc32b0e2 LB |
1132 | writel(SMI_OPCODE_WRITE | (reg << 21) | |
1133 | (addr << 16) | (value & 0xffff), smi_reg); | |
45c5d3bc LB |
1134 | |
1135 | mutex_unlock(&msp->phy_lock); | |
1136 | ||
1137 | return 0; | |
c9df406f | 1138 | } |
1da177e4 | 1139 | |
c9df406f | 1140 | |
8fd89211 LB |
1141 | /* statistics ***************************************************************/ |
1142 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) | |
1143 | { | |
1144 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1145 | struct net_device_stats *stats = &dev->stats; | |
1146 | unsigned long tx_packets = 0; | |
1147 | unsigned long tx_bytes = 0; | |
1148 | unsigned long tx_dropped = 0; | |
1149 | int i; | |
1150 | ||
1151 | for (i = 0; i < mp->txq_count; i++) { | |
1152 | struct tx_queue *txq = mp->txq + i; | |
1153 | ||
1154 | tx_packets += txq->tx_packets; | |
1155 | tx_bytes += txq->tx_bytes; | |
1156 | tx_dropped += txq->tx_dropped; | |
1157 | } | |
1158 | ||
1159 | stats->tx_packets = tx_packets; | |
1160 | stats->tx_bytes = tx_bytes; | |
1161 | stats->tx_dropped = tx_dropped; | |
1162 | ||
1163 | return stats; | |
1164 | } | |
1165 | ||
fc32b0e2 | 1166 | static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 1167 | { |
fc32b0e2 | 1168 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
1da177e4 LT |
1169 | } |
1170 | ||
fc32b0e2 | 1171 | static void mib_counters_clear(struct mv643xx_eth_private *mp) |
d0412d96 | 1172 | { |
fc32b0e2 LB |
1173 | int i; |
1174 | ||
1175 | for (i = 0; i < 0x80; i += 4) | |
1176 | mib_read(mp, i); | |
c9df406f | 1177 | } |
d0412d96 | 1178 | |
fc32b0e2 | 1179 | static void mib_counters_update(struct mv643xx_eth_private *mp) |
c9df406f | 1180 | { |
e5371493 | 1181 | struct mib_counters *p = &mp->mib_counters; |
4b8e3655 | 1182 | |
fc32b0e2 LB |
1183 | p->good_octets_received += mib_read(mp, 0x00); |
1184 | p->good_octets_received += (u64)mib_read(mp, 0x04) << 32; | |
1185 | p->bad_octets_received += mib_read(mp, 0x08); | |
1186 | p->internal_mac_transmit_err += mib_read(mp, 0x0c); | |
1187 | p->good_frames_received += mib_read(mp, 0x10); | |
1188 | p->bad_frames_received += mib_read(mp, 0x14); | |
1189 | p->broadcast_frames_received += mib_read(mp, 0x18); | |
1190 | p->multicast_frames_received += mib_read(mp, 0x1c); | |
1191 | p->frames_64_octets += mib_read(mp, 0x20); | |
1192 | p->frames_65_to_127_octets += mib_read(mp, 0x24); | |
1193 | p->frames_128_to_255_octets += mib_read(mp, 0x28); | |
1194 | p->frames_256_to_511_octets += mib_read(mp, 0x2c); | |
1195 | p->frames_512_to_1023_octets += mib_read(mp, 0x30); | |
1196 | p->frames_1024_to_max_octets += mib_read(mp, 0x34); | |
1197 | p->good_octets_sent += mib_read(mp, 0x38); | |
1198 | p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32; | |
1199 | p->good_frames_sent += mib_read(mp, 0x40); | |
1200 | p->excessive_collision += mib_read(mp, 0x44); | |
1201 | p->multicast_frames_sent += mib_read(mp, 0x48); | |
1202 | p->broadcast_frames_sent += mib_read(mp, 0x4c); | |
1203 | p->unrec_mac_control_received += mib_read(mp, 0x50); | |
1204 | p->fc_sent += mib_read(mp, 0x54); | |
1205 | p->good_fc_received += mib_read(mp, 0x58); | |
1206 | p->bad_fc_received += mib_read(mp, 0x5c); | |
1207 | p->undersize_received += mib_read(mp, 0x60); | |
1208 | p->fragments_received += mib_read(mp, 0x64); | |
1209 | p->oversize_received += mib_read(mp, 0x68); | |
1210 | p->jabber_received += mib_read(mp, 0x6c); | |
1211 | p->mac_receive_error += mib_read(mp, 0x70); | |
1212 | p->bad_crc_event += mib_read(mp, 0x74); | |
1213 | p->collision += mib_read(mp, 0x78); | |
1214 | p->late_collision += mib_read(mp, 0x7c); | |
d0412d96 JC |
1215 | } |
1216 | ||
c9df406f LB |
1217 | |
1218 | /* ethtool ******************************************************************/ | |
e5371493 | 1219 | struct mv643xx_eth_stats { |
c9df406f LB |
1220 | char stat_string[ETH_GSTRING_LEN]; |
1221 | int sizeof_stat; | |
16820054 LB |
1222 | int netdev_off; |
1223 | int mp_off; | |
c9df406f LB |
1224 | }; |
1225 | ||
16820054 LB |
1226 | #define SSTAT(m) \ |
1227 | { #m, FIELD_SIZEOF(struct net_device_stats, m), \ | |
1228 | offsetof(struct net_device, stats.m), -1 } | |
1229 | ||
1230 | #define MIBSTAT(m) \ | |
1231 | { #m, FIELD_SIZEOF(struct mib_counters, m), \ | |
1232 | -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } | |
1233 | ||
1234 | static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { | |
1235 | SSTAT(rx_packets), | |
1236 | SSTAT(tx_packets), | |
1237 | SSTAT(rx_bytes), | |
1238 | SSTAT(tx_bytes), | |
1239 | SSTAT(rx_errors), | |
1240 | SSTAT(tx_errors), | |
1241 | SSTAT(rx_dropped), | |
1242 | SSTAT(tx_dropped), | |
1243 | MIBSTAT(good_octets_received), | |
1244 | MIBSTAT(bad_octets_received), | |
1245 | MIBSTAT(internal_mac_transmit_err), | |
1246 | MIBSTAT(good_frames_received), | |
1247 | MIBSTAT(bad_frames_received), | |
1248 | MIBSTAT(broadcast_frames_received), | |
1249 | MIBSTAT(multicast_frames_received), | |
1250 | MIBSTAT(frames_64_octets), | |
1251 | MIBSTAT(frames_65_to_127_octets), | |
1252 | MIBSTAT(frames_128_to_255_octets), | |
1253 | MIBSTAT(frames_256_to_511_octets), | |
1254 | MIBSTAT(frames_512_to_1023_octets), | |
1255 | MIBSTAT(frames_1024_to_max_octets), | |
1256 | MIBSTAT(good_octets_sent), | |
1257 | MIBSTAT(good_frames_sent), | |
1258 | MIBSTAT(excessive_collision), | |
1259 | MIBSTAT(multicast_frames_sent), | |
1260 | MIBSTAT(broadcast_frames_sent), | |
1261 | MIBSTAT(unrec_mac_control_received), | |
1262 | MIBSTAT(fc_sent), | |
1263 | MIBSTAT(good_fc_received), | |
1264 | MIBSTAT(bad_fc_received), | |
1265 | MIBSTAT(undersize_received), | |
1266 | MIBSTAT(fragments_received), | |
1267 | MIBSTAT(oversize_received), | |
1268 | MIBSTAT(jabber_received), | |
1269 | MIBSTAT(mac_receive_error), | |
1270 | MIBSTAT(bad_crc_event), | |
1271 | MIBSTAT(collision), | |
1272 | MIBSTAT(late_collision), | |
c9df406f LB |
1273 | }; |
1274 | ||
e5371493 | 1275 | static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
d0412d96 | 1276 | { |
e5371493 | 1277 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
d0412d96 JC |
1278 | int err; |
1279 | ||
d0412d96 | 1280 | err = mii_ethtool_gset(&mp->mii, cmd); |
d0412d96 | 1281 | |
fc32b0e2 LB |
1282 | /* |
1283 | * The MAC does not support 1000baseT_Half. | |
1284 | */ | |
d0412d96 JC |
1285 | cmd->supported &= ~SUPPORTED_1000baseT_Half; |
1286 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1287 | ||
1288 | return err; | |
1289 | } | |
1290 | ||
bedfe324 LB |
1291 | static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) |
1292 | { | |
81600eea LB |
1293 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1294 | u32 port_status; | |
1295 | ||
1296 | port_status = rdl(mp, PORT_STATUS(mp->port_num)); | |
1297 | ||
bedfe324 LB |
1298 | cmd->supported = SUPPORTED_MII; |
1299 | cmd->advertising = ADVERTISED_MII; | |
81600eea LB |
1300 | switch (port_status & PORT_SPEED_MASK) { |
1301 | case PORT_SPEED_10: | |
1302 | cmd->speed = SPEED_10; | |
1303 | break; | |
1304 | case PORT_SPEED_100: | |
1305 | cmd->speed = SPEED_100; | |
1306 | break; | |
1307 | case PORT_SPEED_1000: | |
1308 | cmd->speed = SPEED_1000; | |
1309 | break; | |
1310 | default: | |
1311 | cmd->speed = -1; | |
1312 | break; | |
1313 | } | |
1314 | cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; | |
bedfe324 LB |
1315 | cmd->port = PORT_MII; |
1316 | cmd->phy_address = 0; | |
1317 | cmd->transceiver = XCVR_INTERNAL; | |
1318 | cmd->autoneg = AUTONEG_DISABLE; | |
1319 | cmd->maxtxpkt = 1; | |
1320 | cmd->maxrxpkt = 1; | |
1321 | ||
1322 | return 0; | |
1323 | } | |
1324 | ||
e5371493 | 1325 | static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 1326 | { |
e5371493 | 1327 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
ab4384a6 | 1328 | |
fc32b0e2 LB |
1329 | /* |
1330 | * The MAC does not support 1000baseT_Half. | |
1331 | */ | |
1332 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1333 | ||
2b3ba0e3 | 1334 | return mii_ethtool_sset(&mp->mii, cmd); |
c9df406f | 1335 | } |
1da177e4 | 1336 | |
bedfe324 LB |
1337 | static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) |
1338 | { | |
1339 | return -EINVAL; | |
1340 | } | |
1341 | ||
fc32b0e2 LB |
1342 | static void mv643xx_eth_get_drvinfo(struct net_device *dev, |
1343 | struct ethtool_drvinfo *drvinfo) | |
c9df406f | 1344 | { |
e5371493 LB |
1345 | strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); |
1346 | strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); | |
c9df406f | 1347 | strncpy(drvinfo->fw_version, "N/A", 32); |
fc32b0e2 | 1348 | strncpy(drvinfo->bus_info, "platform", 32); |
16820054 | 1349 | drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); |
c9df406f | 1350 | } |
1da177e4 | 1351 | |
fc32b0e2 | 1352 | static int mv643xx_eth_nway_reset(struct net_device *dev) |
c9df406f | 1353 | { |
e5371493 | 1354 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1355 | |
c9df406f LB |
1356 | return mii_nway_restart(&mp->mii); |
1357 | } | |
1da177e4 | 1358 | |
bedfe324 LB |
1359 | static int mv643xx_eth_nway_reset_phyless(struct net_device *dev) |
1360 | { | |
1361 | return -EINVAL; | |
1362 | } | |
1363 | ||
c9df406f LB |
1364 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
1365 | { | |
e5371493 | 1366 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1367 | |
c9df406f LB |
1368 | return mii_link_ok(&mp->mii); |
1369 | } | |
1da177e4 | 1370 | |
bedfe324 LB |
1371 | static u32 mv643xx_eth_get_link_phyless(struct net_device *dev) |
1372 | { | |
1373 | return 1; | |
1374 | } | |
1375 | ||
fc32b0e2 LB |
1376 | static void mv643xx_eth_get_strings(struct net_device *dev, |
1377 | uint32_t stringset, uint8_t *data) | |
c9df406f LB |
1378 | { |
1379 | int i; | |
1da177e4 | 1380 | |
fc32b0e2 LB |
1381 | if (stringset == ETH_SS_STATS) { |
1382 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { | |
c9df406f | 1383 | memcpy(data + i * ETH_GSTRING_LEN, |
16820054 | 1384 | mv643xx_eth_stats[i].stat_string, |
e5371493 | 1385 | ETH_GSTRING_LEN); |
c9df406f | 1386 | } |
c9df406f LB |
1387 | } |
1388 | } | |
1da177e4 | 1389 | |
fc32b0e2 LB |
1390 | static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, |
1391 | struct ethtool_stats *stats, | |
1392 | uint64_t *data) | |
c9df406f | 1393 | { |
b9873841 | 1394 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 1395 | int i; |
1da177e4 | 1396 | |
8fd89211 | 1397 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 1398 | mib_counters_update(mp); |
1da177e4 | 1399 | |
16820054 LB |
1400 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
1401 | const struct mv643xx_eth_stats *stat; | |
1402 | void *p; | |
1403 | ||
1404 | stat = mv643xx_eth_stats + i; | |
1405 | ||
1406 | if (stat->netdev_off >= 0) | |
1407 | p = ((void *)mp->dev) + stat->netdev_off; | |
1408 | else | |
1409 | p = ((void *)mp) + stat->mp_off; | |
1410 | ||
1411 | data[i] = (stat->sizeof_stat == 8) ? | |
1412 | *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1413 | } |
c9df406f | 1414 | } |
1da177e4 | 1415 | |
fc32b0e2 | 1416 | static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) |
c9df406f | 1417 | { |
fc32b0e2 | 1418 | if (sset == ETH_SS_STATS) |
16820054 | 1419 | return ARRAY_SIZE(mv643xx_eth_stats); |
fc32b0e2 LB |
1420 | |
1421 | return -EOPNOTSUPP; | |
c9df406f | 1422 | } |
1da177e4 | 1423 | |
e5371493 | 1424 | static const struct ethtool_ops mv643xx_eth_ethtool_ops = { |
fc32b0e2 LB |
1425 | .get_settings = mv643xx_eth_get_settings, |
1426 | .set_settings = mv643xx_eth_set_settings, | |
1427 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1428 | .nway_reset = mv643xx_eth_nway_reset, | |
1429 | .get_link = mv643xx_eth_get_link, | |
c9df406f | 1430 | .set_sg = ethtool_op_set_sg, |
fc32b0e2 LB |
1431 | .get_strings = mv643xx_eth_get_strings, |
1432 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
e5371493 | 1433 | .get_sset_count = mv643xx_eth_get_sset_count, |
c9df406f | 1434 | }; |
1da177e4 | 1435 | |
bedfe324 LB |
1436 | static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = { |
1437 | .get_settings = mv643xx_eth_get_settings_phyless, | |
1438 | .set_settings = mv643xx_eth_set_settings_phyless, | |
1439 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1440 | .nway_reset = mv643xx_eth_nway_reset_phyless, | |
1441 | .get_link = mv643xx_eth_get_link_phyless, | |
1442 | .set_sg = ethtool_op_set_sg, | |
1443 | .get_strings = mv643xx_eth_get_strings, | |
1444 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
1445 | .get_sset_count = mv643xx_eth_get_sset_count, | |
1446 | }; | |
1447 | ||
bea3348e | 1448 | |
c9df406f | 1449 | /* address handling *********************************************************/ |
5daffe94 | 1450 | static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1451 | { |
c9df406f LB |
1452 | unsigned int mac_h; |
1453 | unsigned int mac_l; | |
1da177e4 | 1454 | |
fc32b0e2 LB |
1455 | mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num)); |
1456 | mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num)); | |
1da177e4 | 1457 | |
5daffe94 LB |
1458 | addr[0] = (mac_h >> 24) & 0xff; |
1459 | addr[1] = (mac_h >> 16) & 0xff; | |
1460 | addr[2] = (mac_h >> 8) & 0xff; | |
1461 | addr[3] = mac_h & 0xff; | |
1462 | addr[4] = (mac_l >> 8) & 0xff; | |
1463 | addr[5] = mac_l & 0xff; | |
c9df406f | 1464 | } |
1da177e4 | 1465 | |
e5371493 | 1466 | static void init_mac_tables(struct mv643xx_eth_private *mp) |
c9df406f | 1467 | { |
fc32b0e2 | 1468 | int i; |
1da177e4 | 1469 | |
fc32b0e2 LB |
1470 | for (i = 0; i < 0x100; i += 4) { |
1471 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0); | |
1472 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0); | |
c9df406f | 1473 | } |
fc32b0e2 LB |
1474 | |
1475 | for (i = 0; i < 0x10; i += 4) | |
1476 | wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0); | |
c9df406f | 1477 | } |
d0412d96 | 1478 | |
e5371493 | 1479 | static void set_filter_table_entry(struct mv643xx_eth_private *mp, |
fc32b0e2 | 1480 | int table, unsigned char entry) |
c9df406f LB |
1481 | { |
1482 | unsigned int table_reg; | |
ab4384a6 | 1483 | |
c9df406f | 1484 | /* Set "accepts frame bit" at specified table entry */ |
fc32b0e2 LB |
1485 | table_reg = rdl(mp, table + (entry & 0xfc)); |
1486 | table_reg |= 0x01 << (8 * (entry & 3)); | |
1487 | wrl(mp, table + (entry & 0xfc), table_reg); | |
1da177e4 LT |
1488 | } |
1489 | ||
5daffe94 | 1490 | static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) |
1da177e4 | 1491 | { |
c9df406f LB |
1492 | unsigned int mac_h; |
1493 | unsigned int mac_l; | |
1494 | int table; | |
1da177e4 | 1495 | |
fc32b0e2 LB |
1496 | mac_l = (addr[4] << 8) | addr[5]; |
1497 | mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; | |
ff561eef | 1498 | |
fc32b0e2 LB |
1499 | wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l); |
1500 | wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h); | |
1da177e4 | 1501 | |
fc32b0e2 | 1502 | table = UNICAST_TABLE(mp->port_num); |
5daffe94 | 1503 | set_filter_table_entry(mp, table, addr[5] & 0x0f); |
1da177e4 LT |
1504 | } |
1505 | ||
fc32b0e2 | 1506 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) |
1da177e4 | 1507 | { |
e5371493 | 1508 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1509 | |
fc32b0e2 LB |
1510 | /* +2 is for the offset of the HW addr type */ |
1511 | memcpy(dev->dev_addr, addr + 2, 6); | |
1512 | ||
cc9754b3 LB |
1513 | init_mac_tables(mp); |
1514 | uc_addr_set(mp, dev->dev_addr); | |
1da177e4 LT |
1515 | |
1516 | return 0; | |
1517 | } | |
1518 | ||
69876569 LB |
1519 | static int addr_crc(unsigned char *addr) |
1520 | { | |
1521 | int crc = 0; | |
1522 | int i; | |
1523 | ||
1524 | for (i = 0; i < 6; i++) { | |
1525 | int j; | |
1526 | ||
1527 | crc = (crc ^ addr[i]) << 8; | |
1528 | for (j = 7; j >= 0; j--) { | |
1529 | if (crc & (0x100 << j)) | |
1530 | crc ^= 0x107 << j; | |
1531 | } | |
1532 | } | |
1533 | ||
1534 | return crc; | |
1535 | } | |
1536 | ||
fc32b0e2 | 1537 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) |
1da177e4 | 1538 | { |
fc32b0e2 LB |
1539 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1540 | u32 port_config; | |
1541 | struct dev_addr_list *addr; | |
1542 | int i; | |
c8aaea25 | 1543 | |
fc32b0e2 LB |
1544 | port_config = rdl(mp, PORT_CONFIG(mp->port_num)); |
1545 | if (dev->flags & IFF_PROMISC) | |
1546 | port_config |= UNICAST_PROMISCUOUS_MODE; | |
1547 | else | |
1548 | port_config &= ~UNICAST_PROMISCUOUS_MODE; | |
1549 | wrl(mp, PORT_CONFIG(mp->port_num), port_config); | |
1da177e4 | 1550 | |
fc32b0e2 LB |
1551 | if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { |
1552 | int port_num = mp->port_num; | |
1553 | u32 accept = 0x01010101; | |
c8aaea25 | 1554 | |
fc32b0e2 LB |
1555 | for (i = 0; i < 0x100; i += 4) { |
1556 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); | |
1557 | wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); | |
c9df406f LB |
1558 | } |
1559 | return; | |
1560 | } | |
c8aaea25 | 1561 | |
fc32b0e2 LB |
1562 | for (i = 0; i < 0x100; i += 4) { |
1563 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0); | |
1564 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0); | |
1da177e4 LT |
1565 | } |
1566 | ||
fc32b0e2 LB |
1567 | for (addr = dev->mc_list; addr != NULL; addr = addr->next) { |
1568 | u8 *a = addr->da_addr; | |
1569 | int table; | |
324ff2c1 | 1570 | |
fc32b0e2 LB |
1571 | if (addr->da_addrlen != 6) |
1572 | continue; | |
1da177e4 | 1573 | |
fc32b0e2 LB |
1574 | if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { |
1575 | table = SPECIAL_MCAST_TABLE(mp->port_num); | |
1576 | set_filter_table_entry(mp, table, a[5]); | |
1577 | } else { | |
1578 | int crc = addr_crc(a); | |
1da177e4 | 1579 | |
fc32b0e2 LB |
1580 | table = OTHER_MCAST_TABLE(mp->port_num); |
1581 | set_filter_table_entry(mp, table, crc); | |
1582 | } | |
1583 | } | |
c9df406f | 1584 | } |
c8aaea25 | 1585 | |
c8aaea25 | 1586 | |
c9df406f | 1587 | /* rx/tx queue initialisation ***********************************************/ |
64da80a2 | 1588 | static int rxq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1589 | { |
64da80a2 | 1590 | struct rx_queue *rxq = mp->rxq + index; |
8a578111 LB |
1591 | struct rx_desc *rx_desc; |
1592 | int size; | |
c9df406f LB |
1593 | int i; |
1594 | ||
64da80a2 LB |
1595 | rxq->index = index; |
1596 | ||
8a578111 LB |
1597 | rxq->rx_ring_size = mp->default_rx_ring_size; |
1598 | ||
1599 | rxq->rx_desc_count = 0; | |
1600 | rxq->rx_curr_desc = 0; | |
1601 | rxq->rx_used_desc = 0; | |
1602 | ||
1603 | size = rxq->rx_ring_size * sizeof(struct rx_desc); | |
1604 | ||
f7981c1c | 1605 | if (index == 0 && size <= mp->rx_desc_sram_size) { |
8a578111 LB |
1606 | rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, |
1607 | mp->rx_desc_sram_size); | |
1608 | rxq->rx_desc_dma = mp->rx_desc_sram_addr; | |
1609 | } else { | |
1610 | rxq->rx_desc_area = dma_alloc_coherent(NULL, size, | |
1611 | &rxq->rx_desc_dma, | |
1612 | GFP_KERNEL); | |
f7ea3337 PJ |
1613 | } |
1614 | ||
8a578111 LB |
1615 | if (rxq->rx_desc_area == NULL) { |
1616 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1617 | "can't allocate rx ring (%d bytes)\n", size); | |
1618 | goto out; | |
1619 | } | |
1620 | memset(rxq->rx_desc_area, 0, size); | |
1da177e4 | 1621 | |
8a578111 LB |
1622 | rxq->rx_desc_area_size = size; |
1623 | rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), | |
1624 | GFP_KERNEL); | |
1625 | if (rxq->rx_skb == NULL) { | |
1626 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1627 | "can't allocate rx skb ring\n"); | |
1628 | goto out_free; | |
1629 | } | |
1630 | ||
1631 | rx_desc = (struct rx_desc *)rxq->rx_desc_area; | |
1632 | for (i = 0; i < rxq->rx_ring_size; i++) { | |
9da78745 LB |
1633 | int nexti; |
1634 | ||
1635 | nexti = i + 1; | |
1636 | if (nexti == rxq->rx_ring_size) | |
1637 | nexti = 0; | |
1638 | ||
8a578111 LB |
1639 | rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + |
1640 | nexti * sizeof(struct rx_desc); | |
1641 | } | |
1642 | ||
8a578111 LB |
1643 | return 0; |
1644 | ||
1645 | ||
1646 | out_free: | |
f7981c1c | 1647 | if (index == 0 && size <= mp->rx_desc_sram_size) |
8a578111 LB |
1648 | iounmap(rxq->rx_desc_area); |
1649 | else | |
1650 | dma_free_coherent(NULL, size, | |
1651 | rxq->rx_desc_area, | |
1652 | rxq->rx_desc_dma); | |
1653 | ||
1654 | out: | |
1655 | return -ENOMEM; | |
c9df406f | 1656 | } |
c8aaea25 | 1657 | |
8a578111 | 1658 | static void rxq_deinit(struct rx_queue *rxq) |
c9df406f | 1659 | { |
8a578111 LB |
1660 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1661 | int i; | |
1662 | ||
1663 | rxq_disable(rxq); | |
c8aaea25 | 1664 | |
8a578111 LB |
1665 | for (i = 0; i < rxq->rx_ring_size; i++) { |
1666 | if (rxq->rx_skb[i]) { | |
1667 | dev_kfree_skb(rxq->rx_skb[i]); | |
1668 | rxq->rx_desc_count--; | |
1da177e4 | 1669 | } |
c8aaea25 | 1670 | } |
1da177e4 | 1671 | |
8a578111 LB |
1672 | if (rxq->rx_desc_count) { |
1673 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1674 | "error freeing rx ring -- %d skbs stuck\n", | |
1675 | rxq->rx_desc_count); | |
1676 | } | |
1677 | ||
f7981c1c | 1678 | if (rxq->index == 0 && |
64da80a2 | 1679 | rxq->rx_desc_area_size <= mp->rx_desc_sram_size) |
8a578111 | 1680 | iounmap(rxq->rx_desc_area); |
c9df406f | 1681 | else |
8a578111 LB |
1682 | dma_free_coherent(NULL, rxq->rx_desc_area_size, |
1683 | rxq->rx_desc_area, rxq->rx_desc_dma); | |
1684 | ||
1685 | kfree(rxq->rx_skb); | |
c9df406f | 1686 | } |
1da177e4 | 1687 | |
3d6b35bc | 1688 | static int txq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1689 | { |
3d6b35bc | 1690 | struct tx_queue *txq = mp->txq + index; |
13d64285 LB |
1691 | struct tx_desc *tx_desc; |
1692 | int size; | |
c9df406f | 1693 | int i; |
1da177e4 | 1694 | |
3d6b35bc LB |
1695 | txq->index = index; |
1696 | ||
13d64285 LB |
1697 | txq->tx_ring_size = mp->default_tx_ring_size; |
1698 | ||
1699 | txq->tx_desc_count = 0; | |
1700 | txq->tx_curr_desc = 0; | |
1701 | txq->tx_used_desc = 0; | |
1702 | ||
1703 | size = txq->tx_ring_size * sizeof(struct tx_desc); | |
1704 | ||
f7981c1c | 1705 | if (index == 0 && size <= mp->tx_desc_sram_size) { |
13d64285 LB |
1706 | txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, |
1707 | mp->tx_desc_sram_size); | |
1708 | txq->tx_desc_dma = mp->tx_desc_sram_addr; | |
1709 | } else { | |
1710 | txq->tx_desc_area = dma_alloc_coherent(NULL, size, | |
1711 | &txq->tx_desc_dma, | |
1712 | GFP_KERNEL); | |
1713 | } | |
1714 | ||
1715 | if (txq->tx_desc_area == NULL) { | |
1716 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1717 | "can't allocate tx ring (%d bytes)\n", size); | |
99ab08e0 | 1718 | return -ENOMEM; |
c9df406f | 1719 | } |
13d64285 LB |
1720 | memset(txq->tx_desc_area, 0, size); |
1721 | ||
1722 | txq->tx_desc_area_size = size; | |
13d64285 LB |
1723 | |
1724 | tx_desc = (struct tx_desc *)txq->tx_desc_area; | |
1725 | for (i = 0; i < txq->tx_ring_size; i++) { | |
6b368f68 | 1726 | struct tx_desc *txd = tx_desc + i; |
9da78745 LB |
1727 | int nexti; |
1728 | ||
1729 | nexti = i + 1; | |
1730 | if (nexti == txq->tx_ring_size) | |
1731 | nexti = 0; | |
6b368f68 LB |
1732 | |
1733 | txd->cmd_sts = 0; | |
1734 | txd->next_desc_ptr = txq->tx_desc_dma + | |
13d64285 LB |
1735 | nexti * sizeof(struct tx_desc); |
1736 | } | |
1737 | ||
99ab08e0 | 1738 | skb_queue_head_init(&txq->tx_skb); |
c9df406f | 1739 | |
99ab08e0 | 1740 | return 0; |
c8aaea25 | 1741 | } |
1da177e4 | 1742 | |
13d64285 | 1743 | static void txq_deinit(struct tx_queue *txq) |
c9df406f | 1744 | { |
13d64285 | 1745 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
fa3959f4 | 1746 | |
13d64285 | 1747 | txq_disable(txq); |
1fa38c58 | 1748 | txq_reclaim(txq, txq->tx_ring_size, 1); |
1da177e4 | 1749 | |
13d64285 | 1750 | BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); |
1da177e4 | 1751 | |
f7981c1c | 1752 | if (txq->index == 0 && |
3d6b35bc | 1753 | txq->tx_desc_area_size <= mp->tx_desc_sram_size) |
13d64285 | 1754 | iounmap(txq->tx_desc_area); |
c9df406f | 1755 | else |
13d64285 LB |
1756 | dma_free_coherent(NULL, txq->tx_desc_area_size, |
1757 | txq->tx_desc_area, txq->tx_desc_dma); | |
c9df406f | 1758 | } |
1da177e4 | 1759 | |
1da177e4 | 1760 | |
c9df406f | 1761 | /* netdev ops and related ***************************************************/ |
1fa38c58 LB |
1762 | static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) |
1763 | { | |
1764 | u32 int_cause; | |
1765 | u32 int_cause_ext; | |
1766 | ||
1767 | int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & | |
1768 | (INT_TX_END | INT_RX | INT_EXT); | |
1769 | if (int_cause == 0) | |
1770 | return 0; | |
1771 | ||
1772 | int_cause_ext = 0; | |
1773 | if (int_cause & INT_EXT) | |
1774 | int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num)); | |
1775 | ||
1776 | int_cause &= INT_TX_END | INT_RX; | |
1777 | if (int_cause) { | |
1778 | wrl(mp, INT_CAUSE(mp->port_num), ~int_cause); | |
1779 | mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & | |
1780 | ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff); | |
1781 | mp->work_rx |= (int_cause & INT_RX) >> 2; | |
1782 | } | |
1783 | ||
1784 | int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; | |
1785 | if (int_cause_ext) { | |
1786 | wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext); | |
1787 | if (int_cause_ext & INT_EXT_LINK_PHY) | |
1788 | mp->work_link = 1; | |
1789 | mp->work_tx |= int_cause_ext & INT_EXT_TX; | |
1790 | } | |
1791 | ||
1792 | return 1; | |
1793 | } | |
1794 | ||
1795 | static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) | |
1796 | { | |
1797 | struct net_device *dev = (struct net_device *)dev_id; | |
1798 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1799 | ||
1800 | if (unlikely(!mv643xx_eth_collect_events(mp))) | |
1801 | return IRQ_NONE; | |
1802 | ||
1803 | wrl(mp, INT_MASK(mp->port_num), 0); | |
1804 | napi_schedule(&mp->napi); | |
1805 | ||
1806 | return IRQ_HANDLED; | |
1807 | } | |
1808 | ||
2f7eb47a LB |
1809 | static void handle_link_event(struct mv643xx_eth_private *mp) |
1810 | { | |
1811 | struct net_device *dev = mp->dev; | |
1812 | u32 port_status; | |
1813 | int speed; | |
1814 | int duplex; | |
1815 | int fc; | |
1816 | ||
1817 | port_status = rdl(mp, PORT_STATUS(mp->port_num)); | |
1818 | if (!(port_status & LINK_UP)) { | |
1819 | if (netif_carrier_ok(dev)) { | |
1820 | int i; | |
1821 | ||
1822 | printk(KERN_INFO "%s: link down\n", dev->name); | |
1823 | ||
1824 | netif_carrier_off(dev); | |
2f7eb47a | 1825 | |
f7981c1c | 1826 | for (i = 0; i < mp->txq_count; i++) { |
2f7eb47a LB |
1827 | struct tx_queue *txq = mp->txq + i; |
1828 | ||
1fa38c58 | 1829 | txq_reclaim(txq, txq->tx_ring_size, 1); |
f7981c1c | 1830 | txq_reset_hw_ptr(txq); |
2f7eb47a LB |
1831 | } |
1832 | } | |
1833 | return; | |
1834 | } | |
1835 | ||
1836 | switch (port_status & PORT_SPEED_MASK) { | |
1837 | case PORT_SPEED_10: | |
1838 | speed = 10; | |
1839 | break; | |
1840 | case PORT_SPEED_100: | |
1841 | speed = 100; | |
1842 | break; | |
1843 | case PORT_SPEED_1000: | |
1844 | speed = 1000; | |
1845 | break; | |
1846 | default: | |
1847 | speed = -1; | |
1848 | break; | |
1849 | } | |
1850 | duplex = (port_status & FULL_DUPLEX) ? 1 : 0; | |
1851 | fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; | |
1852 | ||
1853 | printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " | |
1854 | "flow control %sabled\n", dev->name, | |
1855 | speed, duplex ? "full" : "half", | |
1856 | fc ? "en" : "dis"); | |
1857 | ||
4fdeca3f | 1858 | if (!netif_carrier_ok(dev)) |
2f7eb47a | 1859 | netif_carrier_on(dev); |
2f7eb47a LB |
1860 | } |
1861 | ||
1fa38c58 | 1862 | static int mv643xx_eth_poll(struct napi_struct *napi, int budget) |
c9df406f | 1863 | { |
1fa38c58 LB |
1864 | struct mv643xx_eth_private *mp; |
1865 | int work_done; | |
ce4e2e45 | 1866 | |
1fa38c58 | 1867 | mp = container_of(napi, struct mv643xx_eth_private, napi); |
fc32b0e2 | 1868 | |
1fa38c58 LB |
1869 | mp->work_rx_refill |= mp->work_rx_oom; |
1870 | mp->work_rx_oom = 0; | |
1da177e4 | 1871 | |
1fa38c58 LB |
1872 | work_done = 0; |
1873 | while (work_done < budget) { | |
1874 | u8 queue_mask; | |
1875 | int queue; | |
1876 | int work_tbd; | |
1877 | ||
1878 | if (mp->work_link) { | |
1879 | mp->work_link = 0; | |
1880 | handle_link_event(mp); | |
1881 | continue; | |
1882 | } | |
1da177e4 | 1883 | |
1fa38c58 LB |
1884 | queue_mask = mp->work_tx | mp->work_tx_end | |
1885 | mp->work_rx | mp->work_rx_refill; | |
1886 | if (!queue_mask) { | |
1887 | if (mv643xx_eth_collect_events(mp)) | |
1888 | continue; | |
1889 | break; | |
1890 | } | |
1da177e4 | 1891 | |
1fa38c58 LB |
1892 | queue = fls(queue_mask) - 1; |
1893 | queue_mask = 1 << queue; | |
1894 | ||
1895 | work_tbd = budget - work_done; | |
1896 | if (work_tbd > 16) | |
1897 | work_tbd = 16; | |
1898 | ||
1899 | if (mp->work_tx_end & queue_mask) { | |
1900 | txq_kick(mp->txq + queue); | |
1901 | } else if (mp->work_tx & queue_mask) { | |
1902 | work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); | |
1903 | txq_maybe_wake(mp->txq + queue); | |
1904 | } else if (mp->work_rx & queue_mask) { | |
1905 | work_done += rxq_process(mp->rxq + queue, work_tbd); | |
1906 | } else if (mp->work_rx_refill & queue_mask) { | |
1907 | work_done += rxq_refill(mp->rxq + queue, work_tbd); | |
1908 | } else { | |
1909 | BUG(); | |
1910 | } | |
84dd619e | 1911 | } |
fc32b0e2 | 1912 | |
1fa38c58 LB |
1913 | if (work_done < budget) { |
1914 | if (mp->work_rx_oom) | |
1915 | mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); | |
1916 | napi_complete(napi); | |
1917 | wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); | |
226bb6b7 | 1918 | } |
3d6b35bc | 1919 | |
1fa38c58 LB |
1920 | return work_done; |
1921 | } | |
8fa89bf5 | 1922 | |
1fa38c58 LB |
1923 | static inline void oom_timer_wrapper(unsigned long data) |
1924 | { | |
1925 | struct mv643xx_eth_private *mp = (void *)data; | |
1da177e4 | 1926 | |
1fa38c58 | 1927 | napi_schedule(&mp->napi); |
1da177e4 LT |
1928 | } |
1929 | ||
e5371493 | 1930 | static void phy_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 1931 | { |
45c5d3bc LB |
1932 | int data; |
1933 | ||
1934 | data = smi_reg_read(mp, mp->phy_addr, MII_BMCR); | |
1935 | if (data < 0) | |
1936 | return; | |
1da177e4 | 1937 | |
7f106c1d | 1938 | data |= BMCR_RESET; |
45c5d3bc LB |
1939 | if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0) |
1940 | return; | |
1da177e4 | 1941 | |
c9df406f | 1942 | do { |
45c5d3bc LB |
1943 | data = smi_reg_read(mp, mp->phy_addr, MII_BMCR); |
1944 | } while (data >= 0 && data & BMCR_RESET); | |
1da177e4 LT |
1945 | } |
1946 | ||
fc32b0e2 | 1947 | static void port_start(struct mv643xx_eth_private *mp) |
1da177e4 | 1948 | { |
d0412d96 | 1949 | u32 pscr; |
8a578111 | 1950 | int i; |
1da177e4 | 1951 | |
bedfe324 LB |
1952 | /* |
1953 | * Perform PHY reset, if there is a PHY. | |
1954 | */ | |
1955 | if (mp->phy_addr != -1) { | |
1956 | struct ethtool_cmd cmd; | |
1957 | ||
1958 | mv643xx_eth_get_settings(mp->dev, &cmd); | |
1959 | phy_reset(mp); | |
1960 | mv643xx_eth_set_settings(mp->dev, &cmd); | |
1961 | } | |
1da177e4 | 1962 | |
81600eea LB |
1963 | /* |
1964 | * Configure basic link parameters. | |
1965 | */ | |
1966 | pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); | |
1967 | ||
1968 | pscr |= SERIAL_PORT_ENABLE; | |
1969 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
1970 | ||
1971 | pscr |= DO_NOT_FORCE_LINK_FAIL; | |
1972 | if (mp->phy_addr == -1) | |
1973 | pscr |= FORCE_LINK_PASS; | |
1974 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
1975 | ||
1976 | wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE); | |
1977 | ||
13d64285 LB |
1978 | /* |
1979 | * Configure TX path and queues. | |
1980 | */ | |
89df5fdc | 1981 | tx_set_rate(mp, 1000000000, 16777216); |
f7981c1c | 1982 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc | 1983 | struct tx_queue *txq = mp->txq + i; |
13d64285 | 1984 | |
6b368f68 | 1985 | txq_reset_hw_ptr(txq); |
89df5fdc LB |
1986 | txq_set_rate(txq, 1000000000, 16777216); |
1987 | txq_set_fixed_prio_mode(txq); | |
13d64285 LB |
1988 | } |
1989 | ||
fc32b0e2 LB |
1990 | /* |
1991 | * Add configured unicast address to address filter table. | |
1992 | */ | |
1993 | uc_addr_set(mp, mp->dev->dev_addr); | |
1da177e4 | 1994 | |
d9a073ea LB |
1995 | /* |
1996 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
1997 | * frames to RX queue #0. | |
1998 | */ | |
8a578111 | 1999 | wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000); |
01999873 | 2000 | |
376489a2 LB |
2001 | /* |
2002 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
2003 | */ | |
8a578111 | 2004 | wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000); |
01999873 | 2005 | |
8a578111 | 2006 | /* |
64da80a2 | 2007 | * Enable the receive queues. |
8a578111 | 2008 | */ |
f7981c1c | 2009 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 LB |
2010 | struct rx_queue *rxq = mp->rxq + i; |
2011 | int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i); | |
8a578111 | 2012 | u32 addr; |
1da177e4 | 2013 | |
8a578111 LB |
2014 | addr = (u32)rxq->rx_desc_dma; |
2015 | addr += rxq->rx_curr_desc * sizeof(struct rx_desc); | |
2016 | wrl(mp, off, addr); | |
1da177e4 | 2017 | |
8a578111 LB |
2018 | rxq_enable(rxq); |
2019 | } | |
1da177e4 LT |
2020 | } |
2021 | ||
ffd86bbe | 2022 | static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay) |
1da177e4 | 2023 | { |
c9df406f | 2024 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
773fc3ee | 2025 | u32 val; |
1da177e4 | 2026 | |
773fc3ee LB |
2027 | val = rdl(mp, SDMA_CONFIG(mp->port_num)); |
2028 | if (mp->shared->extended_rx_coal_limit) { | |
2029 | if (coal > 0xffff) | |
2030 | coal = 0xffff; | |
2031 | val &= ~0x023fff80; | |
2032 | val |= (coal & 0x8000) << 10; | |
2033 | val |= (coal & 0x7fff) << 7; | |
2034 | } else { | |
2035 | if (coal > 0x3fff) | |
2036 | coal = 0x3fff; | |
2037 | val &= ~0x003fff00; | |
2038 | val |= (coal & 0x3fff) << 8; | |
2039 | } | |
2040 | wrl(mp, SDMA_CONFIG(mp->port_num), val); | |
1da177e4 LT |
2041 | } |
2042 | ||
ffd86bbe | 2043 | static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay) |
1da177e4 | 2044 | { |
c9df406f | 2045 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 2046 | |
fc32b0e2 LB |
2047 | if (coal > 0x3fff) |
2048 | coal = 0x3fff; | |
2049 | wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4); | |
16e03018 DF |
2050 | } |
2051 | ||
c9df406f | 2052 | static int mv643xx_eth_open(struct net_device *dev) |
16e03018 | 2053 | { |
e5371493 | 2054 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2055 | int err; |
64da80a2 | 2056 | int i; |
16e03018 | 2057 | |
fc32b0e2 LB |
2058 | wrl(mp, INT_CAUSE(mp->port_num), 0); |
2059 | wrl(mp, INT_CAUSE_EXT(mp->port_num), 0); | |
2060 | rdl(mp, INT_CAUSE_EXT(mp->port_num)); | |
c9df406f | 2061 | |
fc32b0e2 | 2062 | err = request_irq(dev->irq, mv643xx_eth_irq, |
2a1867a7 | 2063 | IRQF_SHARED, dev->name, dev); |
c9df406f | 2064 | if (err) { |
fc32b0e2 | 2065 | dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); |
c9df406f | 2066 | return -EAGAIN; |
16e03018 DF |
2067 | } |
2068 | ||
fc32b0e2 | 2069 | init_mac_tables(mp); |
16e03018 | 2070 | |
2257e05c LB |
2071 | napi_enable(&mp->napi); |
2072 | ||
f7981c1c | 2073 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 LB |
2074 | err = rxq_init(mp, i); |
2075 | if (err) { | |
2076 | while (--i >= 0) | |
f7981c1c | 2077 | rxq_deinit(mp->rxq + i); |
64da80a2 LB |
2078 | goto out; |
2079 | } | |
2080 | ||
1fa38c58 | 2081 | rxq_refill(mp->rxq + i, INT_MAX); |
2257e05c LB |
2082 | } |
2083 | ||
1fa38c58 | 2084 | if (mp->work_rx_oom) { |
2257e05c LB |
2085 | mp->rx_oom.expires = jiffies + (HZ / 10); |
2086 | add_timer(&mp->rx_oom); | |
64da80a2 | 2087 | } |
8a578111 | 2088 | |
f7981c1c | 2089 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc LB |
2090 | err = txq_init(mp, i); |
2091 | if (err) { | |
2092 | while (--i >= 0) | |
f7981c1c | 2093 | txq_deinit(mp->txq + i); |
3d6b35bc LB |
2094 | goto out_free; |
2095 | } | |
2096 | } | |
16e03018 | 2097 | |
2f7eb47a | 2098 | netif_carrier_off(dev); |
2f7eb47a | 2099 | |
fc32b0e2 | 2100 | port_start(mp); |
16e03018 | 2101 | |
ffd86bbe LB |
2102 | set_rx_coal(mp, 0); |
2103 | set_tx_coal(mp, 0); | |
16e03018 | 2104 | |
befefe21 | 2105 | wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX); |
226bb6b7 | 2106 | wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); |
16e03018 | 2107 | |
c9df406f LB |
2108 | return 0; |
2109 | ||
13d64285 | 2110 | |
fc32b0e2 | 2111 | out_free: |
f7981c1c LB |
2112 | for (i = 0; i < mp->rxq_count; i++) |
2113 | rxq_deinit(mp->rxq + i); | |
fc32b0e2 | 2114 | out: |
c9df406f LB |
2115 | free_irq(dev->irq, dev); |
2116 | ||
2117 | return err; | |
16e03018 DF |
2118 | } |
2119 | ||
e5371493 | 2120 | static void port_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2121 | { |
fc32b0e2 | 2122 | unsigned int data; |
64da80a2 | 2123 | int i; |
1da177e4 | 2124 | |
f7981c1c LB |
2125 | for (i = 0; i < mp->rxq_count; i++) |
2126 | rxq_disable(mp->rxq + i); | |
2127 | for (i = 0; i < mp->txq_count; i++) | |
2128 | txq_disable(mp->txq + i); | |
ae9ae064 LB |
2129 | |
2130 | while (1) { | |
2131 | u32 ps = rdl(mp, PORT_STATUS(mp->port_num)); | |
2132 | ||
2133 | if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) | |
2134 | break; | |
13d64285 | 2135 | udelay(10); |
ae9ae064 | 2136 | } |
1da177e4 | 2137 | |
c9df406f | 2138 | /* Reset the Enable bit in the Configuration Register */ |
fc32b0e2 LB |
2139 | data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); |
2140 | data &= ~(SERIAL_PORT_ENABLE | | |
2141 | DO_NOT_FORCE_LINK_FAIL | | |
2142 | FORCE_LINK_PASS); | |
2143 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data); | |
1da177e4 LT |
2144 | } |
2145 | ||
c9df406f | 2146 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 | 2147 | { |
e5371493 | 2148 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
64da80a2 | 2149 | int i; |
1da177e4 | 2150 | |
fc32b0e2 LB |
2151 | wrl(mp, INT_MASK(mp->port_num), 0x00000000); |
2152 | rdl(mp, INT_MASK(mp->port_num)); | |
1da177e4 | 2153 | |
c9df406f | 2154 | napi_disable(&mp->napi); |
78fff83b | 2155 | |
2257e05c LB |
2156 | del_timer_sync(&mp->rx_oom); |
2157 | ||
c9df406f | 2158 | netif_carrier_off(dev); |
1da177e4 | 2159 | |
fc32b0e2 LB |
2160 | free_irq(dev->irq, dev); |
2161 | ||
cc9754b3 | 2162 | port_reset(mp); |
8fd89211 | 2163 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 2164 | mib_counters_update(mp); |
1da177e4 | 2165 | |
f7981c1c LB |
2166 | for (i = 0; i < mp->rxq_count; i++) |
2167 | rxq_deinit(mp->rxq + i); | |
2168 | for (i = 0; i < mp->txq_count; i++) | |
2169 | txq_deinit(mp->txq + i); | |
1da177e4 | 2170 | |
c9df406f | 2171 | return 0; |
1da177e4 LT |
2172 | } |
2173 | ||
fc32b0e2 | 2174 | static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2175 | { |
e5371493 | 2176 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2177 | |
bedfe324 LB |
2178 | if (mp->phy_addr != -1) |
2179 | return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); | |
2180 | ||
2181 | return -EOPNOTSUPP; | |
1da177e4 LT |
2182 | } |
2183 | ||
c9df406f | 2184 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2185 | { |
89df5fdc LB |
2186 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
2187 | ||
fc32b0e2 | 2188 | if (new_mtu < 64 || new_mtu > 9500) |
c9df406f | 2189 | return -EINVAL; |
1da177e4 | 2190 | |
c9df406f | 2191 | dev->mtu = new_mtu; |
89df5fdc LB |
2192 | tx_set_rate(mp, 1000000000, 16777216); |
2193 | ||
c9df406f LB |
2194 | if (!netif_running(dev)) |
2195 | return 0; | |
1da177e4 | 2196 | |
c9df406f LB |
2197 | /* |
2198 | * Stop and then re-open the interface. This will allocate RX | |
2199 | * skbs of the new MTU. | |
2200 | * There is a possible danger that the open will not succeed, | |
fc32b0e2 | 2201 | * due to memory being full. |
c9df406f LB |
2202 | */ |
2203 | mv643xx_eth_stop(dev); | |
2204 | if (mv643xx_eth_open(dev)) { | |
fc32b0e2 LB |
2205 | dev_printk(KERN_ERR, &dev->dev, |
2206 | "fatal error on re-opening device after " | |
2207 | "MTU change\n"); | |
c9df406f LB |
2208 | } |
2209 | ||
2210 | return 0; | |
1da177e4 LT |
2211 | } |
2212 | ||
fc32b0e2 | 2213 | static void tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2214 | { |
fc32b0e2 | 2215 | struct mv643xx_eth_private *mp; |
1da177e4 | 2216 | |
fc32b0e2 LB |
2217 | mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); |
2218 | if (netif_running(mp->dev)) { | |
e5ef1de1 | 2219 | netif_tx_stop_all_queues(mp->dev); |
fc32b0e2 LB |
2220 | port_reset(mp); |
2221 | port_start(mp); | |
e5ef1de1 | 2222 | netif_tx_wake_all_queues(mp->dev); |
fc32b0e2 | 2223 | } |
c9df406f LB |
2224 | } |
2225 | ||
c9df406f | 2226 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2227 | { |
e5371493 | 2228 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2229 | |
fc32b0e2 | 2230 | dev_printk(KERN_INFO, &dev->dev, "tx timeout\n"); |
d0412d96 | 2231 | |
c9df406f | 2232 | schedule_work(&mp->tx_timeout_task); |
1da177e4 LT |
2233 | } |
2234 | ||
c9df406f | 2235 | #ifdef CONFIG_NET_POLL_CONTROLLER |
fc32b0e2 | 2236 | static void mv643xx_eth_netpoll(struct net_device *dev) |
9f8dd319 | 2237 | { |
fc32b0e2 | 2238 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2239 | |
fc32b0e2 LB |
2240 | wrl(mp, INT_MASK(mp->port_num), 0x00000000); |
2241 | rdl(mp, INT_MASK(mp->port_num)); | |
c9df406f | 2242 | |
fc32b0e2 | 2243 | mv643xx_eth_irq(dev->irq, dev); |
c9df406f | 2244 | |
f2ca60f2 | 2245 | wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT); |
9f8dd319 | 2246 | } |
c9df406f | 2247 | #endif |
9f8dd319 | 2248 | |
fc32b0e2 | 2249 | static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg) |
9f8dd319 | 2250 | { |
e5371493 | 2251 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
45c5d3bc | 2252 | return smi_reg_read(mp, addr, reg); |
9f8dd319 DF |
2253 | } |
2254 | ||
fc32b0e2 | 2255 | static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val) |
9f8dd319 | 2256 | { |
e5371493 | 2257 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
fc32b0e2 | 2258 | smi_reg_write(mp, addr, reg, val); |
c9df406f | 2259 | } |
9f8dd319 | 2260 | |
9f8dd319 | 2261 | |
c9df406f | 2262 | /* platform glue ************************************************************/ |
e5371493 LB |
2263 | static void |
2264 | mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, | |
2265 | struct mbus_dram_target_info *dram) | |
c9df406f | 2266 | { |
cc9754b3 | 2267 | void __iomem *base = msp->base; |
c9df406f LB |
2268 | u32 win_enable; |
2269 | u32 win_protect; | |
2270 | int i; | |
9f8dd319 | 2271 | |
c9df406f LB |
2272 | for (i = 0; i < 6; i++) { |
2273 | writel(0, base + WINDOW_BASE(i)); | |
2274 | writel(0, base + WINDOW_SIZE(i)); | |
2275 | if (i < 4) | |
2276 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2277 | } |
2278 | ||
c9df406f LB |
2279 | win_enable = 0x3f; |
2280 | win_protect = 0; | |
2281 | ||
2282 | for (i = 0; i < dram->num_cs; i++) { | |
2283 | struct mbus_dram_window *cs = dram->cs + i; | |
2284 | ||
2285 | writel((cs->base & 0xffff0000) | | |
2286 | (cs->mbus_attr << 8) | | |
2287 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2288 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2289 | ||
2290 | win_enable &= ~(1 << i); | |
2291 | win_protect |= 3 << (2 * i); | |
2292 | } | |
2293 | ||
2294 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2295 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2296 | } |
2297 | ||
773fc3ee LB |
2298 | static void infer_hw_params(struct mv643xx_eth_shared_private *msp) |
2299 | { | |
2300 | /* | |
2301 | * Check whether we have a 14-bit coal limit field in bits | |
2302 | * [21:8], or a 16-bit coal limit in bits [25,21:7] of the | |
2303 | * SDMA config register. | |
2304 | */ | |
2305 | writel(0x02000000, msp->base + SDMA_CONFIG(0)); | |
2306 | if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000) | |
2307 | msp->extended_rx_coal_limit = 1; | |
2308 | else | |
2309 | msp->extended_rx_coal_limit = 0; | |
1e881592 LB |
2310 | |
2311 | /* | |
457b1d5a LB |
2312 | * Check whether the MAC supports TX rate control, and if |
2313 | * yes, whether its associated registers are in the old or | |
2314 | * the new place. | |
1e881592 LB |
2315 | */ |
2316 | writel(1, msp->base + TX_BW_MTU_MOVED(0)); | |
457b1d5a LB |
2317 | if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1) { |
2318 | msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; | |
2319 | } else { | |
2320 | writel(7, msp->base + TX_BW_RATE(0)); | |
2321 | if (readl(msp->base + TX_BW_RATE(0)) & 7) | |
2322 | msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; | |
2323 | else | |
2324 | msp->tx_bw_control = TX_BW_CONTROL_ABSENT; | |
2325 | } | |
773fc3ee LB |
2326 | } |
2327 | ||
c9df406f | 2328 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2329 | { |
e5371493 | 2330 | static int mv643xx_eth_version_printed = 0; |
c9df406f | 2331 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
e5371493 | 2332 | struct mv643xx_eth_shared_private *msp; |
c9df406f LB |
2333 | struct resource *res; |
2334 | int ret; | |
9f8dd319 | 2335 | |
e5371493 | 2336 | if (!mv643xx_eth_version_printed++) |
7dde154d LB |
2337 | printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet " |
2338 | "driver version %s\n", mv643xx_eth_driver_version); | |
9f8dd319 | 2339 | |
c9df406f LB |
2340 | ret = -EINVAL; |
2341 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2342 | if (res == NULL) | |
2343 | goto out; | |
9f8dd319 | 2344 | |
c9df406f LB |
2345 | ret = -ENOMEM; |
2346 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2347 | if (msp == NULL) | |
2348 | goto out; | |
2349 | memset(msp, 0, sizeof(*msp)); | |
2350 | ||
cc9754b3 LB |
2351 | msp->base = ioremap(res->start, res->end - res->start + 1); |
2352 | if (msp->base == NULL) | |
c9df406f LB |
2353 | goto out_free; |
2354 | ||
fc0eb9f2 LB |
2355 | msp->smi = msp; |
2356 | if (pd != NULL && pd->shared_smi != NULL) | |
2357 | msp->smi = platform_get_drvdata(pd->shared_smi); | |
2358 | ||
2b3ba0e3 | 2359 | mutex_init(&msp->phy_lock); |
c9df406f | 2360 | |
45c5d3bc LB |
2361 | msp->err_interrupt = NO_IRQ; |
2362 | init_waitqueue_head(&msp->smi_busy_wait); | |
2363 | ||
2364 | /* | |
2365 | * Check whether the error interrupt is hooked up. | |
2366 | */ | |
2367 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
2368 | if (res != NULL) { | |
2369 | int err; | |
2370 | ||
2371 | err = request_irq(res->start, mv643xx_eth_err_irq, | |
2372 | IRQF_SHARED, "mv643xx_eth", msp); | |
2373 | if (!err) { | |
2374 | writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK); | |
2375 | msp->err_interrupt = res->start; | |
2376 | } | |
2377 | } | |
2378 | ||
c9df406f LB |
2379 | /* |
2380 | * (Re-)program MBUS remapping windows if we are asked to. | |
2381 | */ | |
2382 | if (pd != NULL && pd->dram != NULL) | |
2383 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2384 | ||
fc32b0e2 LB |
2385 | /* |
2386 | * Detect hardware parameters. | |
2387 | */ | |
2388 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
773fc3ee | 2389 | infer_hw_params(msp); |
fc32b0e2 LB |
2390 | |
2391 | platform_set_drvdata(pdev, msp); | |
2392 | ||
c9df406f LB |
2393 | return 0; |
2394 | ||
2395 | out_free: | |
2396 | kfree(msp); | |
2397 | out: | |
2398 | return ret; | |
2399 | } | |
2400 | ||
2401 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2402 | { | |
e5371493 | 2403 | struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); |
c9df406f | 2404 | |
45c5d3bc LB |
2405 | if (msp->err_interrupt != NO_IRQ) |
2406 | free_irq(msp->err_interrupt, msp); | |
cc9754b3 | 2407 | iounmap(msp->base); |
c9df406f LB |
2408 | kfree(msp); |
2409 | ||
2410 | return 0; | |
9f8dd319 DF |
2411 | } |
2412 | ||
c9df406f | 2413 | static struct platform_driver mv643xx_eth_shared_driver = { |
fc32b0e2 LB |
2414 | .probe = mv643xx_eth_shared_probe, |
2415 | .remove = mv643xx_eth_shared_remove, | |
c9df406f | 2416 | .driver = { |
fc32b0e2 | 2417 | .name = MV643XX_ETH_SHARED_NAME, |
c9df406f LB |
2418 | .owner = THIS_MODULE, |
2419 | }, | |
2420 | }; | |
2421 | ||
e5371493 | 2422 | static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) |
1da177e4 | 2423 | { |
c9df406f | 2424 | int addr_shift = 5 * mp->port_num; |
fc32b0e2 | 2425 | u32 data; |
1da177e4 | 2426 | |
fc32b0e2 LB |
2427 | data = rdl(mp, PHY_ADDR); |
2428 | data &= ~(0x1f << addr_shift); | |
2429 | data |= (phy_addr & 0x1f) << addr_shift; | |
2430 | wrl(mp, PHY_ADDR, data); | |
1da177e4 LT |
2431 | } |
2432 | ||
e5371493 | 2433 | static int phy_addr_get(struct mv643xx_eth_private *mp) |
1da177e4 | 2434 | { |
fc32b0e2 LB |
2435 | unsigned int data; |
2436 | ||
2437 | data = rdl(mp, PHY_ADDR); | |
2438 | ||
2439 | return (data >> (5 * mp->port_num)) & 0x1f; | |
2440 | } | |
2441 | ||
2442 | static void set_params(struct mv643xx_eth_private *mp, | |
2443 | struct mv643xx_eth_platform_data *pd) | |
2444 | { | |
2445 | struct net_device *dev = mp->dev; | |
2446 | ||
2447 | if (is_valid_ether_addr(pd->mac_addr)) | |
2448 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2449 | else | |
2450 | uc_addr_get(mp, dev->dev_addr); | |
2451 | ||
ac840605 | 2452 | if (pd->phy_addr == MV643XX_ETH_PHY_NONE) { |
fc32b0e2 LB |
2453 | mp->phy_addr = -1; |
2454 | } else { | |
ac840605 | 2455 | if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) { |
fc32b0e2 LB |
2456 | mp->phy_addr = pd->phy_addr & 0x3f; |
2457 | phy_addr_set(mp, mp->phy_addr); | |
2458 | } else { | |
2459 | mp->phy_addr = phy_addr_get(mp); | |
2460 | } | |
2461 | } | |
1da177e4 | 2462 | |
fc32b0e2 LB |
2463 | mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE; |
2464 | if (pd->rx_queue_size) | |
2465 | mp->default_rx_ring_size = pd->rx_queue_size; | |
2466 | mp->rx_desc_sram_addr = pd->rx_sram_addr; | |
2467 | mp->rx_desc_sram_size = pd->rx_sram_size; | |
1da177e4 | 2468 | |
f7981c1c | 2469 | mp->rxq_count = pd->rx_queue_count ? : 1; |
64da80a2 | 2470 | |
fc32b0e2 LB |
2471 | mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE; |
2472 | if (pd->tx_queue_size) | |
2473 | mp->default_tx_ring_size = pd->tx_queue_size; | |
2474 | mp->tx_desc_sram_addr = pd->tx_sram_addr; | |
2475 | mp->tx_desc_sram_size = pd->tx_sram_size; | |
3d6b35bc | 2476 | |
f7981c1c | 2477 | mp->txq_count = pd->tx_queue_count ? : 1; |
1da177e4 LT |
2478 | } |
2479 | ||
e5371493 | 2480 | static int phy_detect(struct mv643xx_eth_private *mp) |
1da177e4 | 2481 | { |
45c5d3bc LB |
2482 | int data; |
2483 | int data2; | |
2484 | ||
2485 | data = smi_reg_read(mp, mp->phy_addr, MII_BMCR); | |
2486 | if (data < 0) | |
2487 | return -ENODEV; | |
2488 | ||
2489 | if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0) | |
2490 | return -ENODEV; | |
fc32b0e2 | 2491 | |
45c5d3bc LB |
2492 | data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR); |
2493 | if (data2 < 0) | |
2494 | return -ENODEV; | |
1da177e4 | 2495 | |
7f106c1d | 2496 | if (((data ^ data2) & BMCR_ANENABLE) == 0) |
fc32b0e2 | 2497 | return -ENODEV; |
1da177e4 | 2498 | |
7f106c1d | 2499 | smi_reg_write(mp, mp->phy_addr, MII_BMCR, data); |
1da177e4 | 2500 | |
c9df406f | 2501 | return 0; |
1da177e4 LT |
2502 | } |
2503 | ||
fc32b0e2 LB |
2504 | static int phy_init(struct mv643xx_eth_private *mp, |
2505 | struct mv643xx_eth_platform_data *pd) | |
c28a4f89 | 2506 | { |
fc32b0e2 LB |
2507 | struct ethtool_cmd cmd; |
2508 | int err; | |
c28a4f89 | 2509 | |
fc32b0e2 LB |
2510 | err = phy_detect(mp); |
2511 | if (err) { | |
2512 | dev_printk(KERN_INFO, &mp->dev->dev, | |
2513 | "no PHY detected at addr %d\n", mp->phy_addr); | |
2514 | return err; | |
2515 | } | |
2516 | phy_reset(mp); | |
2517 | ||
2518 | mp->mii.phy_id = mp->phy_addr; | |
2519 | mp->mii.phy_id_mask = 0x3f; | |
2520 | mp->mii.reg_num_mask = 0x1f; | |
2521 | mp->mii.dev = mp->dev; | |
2522 | mp->mii.mdio_read = mv643xx_eth_mdio_read; | |
2523 | mp->mii.mdio_write = mv643xx_eth_mdio_write; | |
c28a4f89 | 2524 | |
fc32b0e2 | 2525 | mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); |
c9df406f | 2526 | |
fc32b0e2 LB |
2527 | memset(&cmd, 0, sizeof(cmd)); |
2528 | ||
2529 | cmd.port = PORT_MII; | |
2530 | cmd.transceiver = XCVR_INTERNAL; | |
2531 | cmd.phy_address = mp->phy_addr; | |
2532 | if (pd->speed == 0) { | |
2533 | cmd.autoneg = AUTONEG_ENABLE; | |
2534 | cmd.speed = SPEED_100; | |
2535 | cmd.advertising = ADVERTISED_10baseT_Half | | |
2536 | ADVERTISED_10baseT_Full | | |
2537 | ADVERTISED_100baseT_Half | | |
2538 | ADVERTISED_100baseT_Full; | |
c9df406f | 2539 | if (mp->mii.supports_gmii) |
fc32b0e2 | 2540 | cmd.advertising |= ADVERTISED_1000baseT_Full; |
c9df406f | 2541 | } else { |
fc32b0e2 LB |
2542 | cmd.autoneg = AUTONEG_DISABLE; |
2543 | cmd.speed = pd->speed; | |
2544 | cmd.duplex = pd->duplex; | |
c9df406f | 2545 | } |
fc32b0e2 | 2546 | |
fc32b0e2 LB |
2547 | mv643xx_eth_set_settings(mp->dev, &cmd); |
2548 | ||
2549 | return 0; | |
c28a4f89 JC |
2550 | } |
2551 | ||
81600eea LB |
2552 | static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) |
2553 | { | |
2554 | u32 pscr; | |
2555 | ||
2556 | pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); | |
2557 | if (pscr & SERIAL_PORT_ENABLE) { | |
2558 | pscr &= ~SERIAL_PORT_ENABLE; | |
2559 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
2560 | } | |
2561 | ||
2562 | pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; | |
2563 | if (mp->phy_addr == -1) { | |
2564 | pscr |= DISABLE_AUTO_NEG_SPEED_GMII; | |
2565 | if (speed == SPEED_1000) | |
2566 | pscr |= SET_GMII_SPEED_TO_1000; | |
2567 | else if (speed == SPEED_100) | |
2568 | pscr |= SET_MII_SPEED_TO_100; | |
2569 | ||
2570 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; | |
2571 | ||
2572 | pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; | |
2573 | if (duplex == DUPLEX_FULL) | |
2574 | pscr |= SET_FULL_DUPLEX_MODE; | |
2575 | } | |
2576 | ||
2577 | wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr); | |
2578 | } | |
2579 | ||
c9df406f | 2580 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2581 | { |
c9df406f | 2582 | struct mv643xx_eth_platform_data *pd; |
e5371493 | 2583 | struct mv643xx_eth_private *mp; |
c9df406f | 2584 | struct net_device *dev; |
c9df406f | 2585 | struct resource *res; |
c9df406f | 2586 | DECLARE_MAC_BUF(mac); |
fc32b0e2 | 2587 | int err; |
1da177e4 | 2588 | |
c9df406f LB |
2589 | pd = pdev->dev.platform_data; |
2590 | if (pd == NULL) { | |
fc32b0e2 LB |
2591 | dev_printk(KERN_ERR, &pdev->dev, |
2592 | "no mv643xx_eth_platform_data\n"); | |
c9df406f LB |
2593 | return -ENODEV; |
2594 | } | |
1da177e4 | 2595 | |
c9df406f | 2596 | if (pd->shared == NULL) { |
fc32b0e2 LB |
2597 | dev_printk(KERN_ERR, &pdev->dev, |
2598 | "no mv643xx_eth_platform_data->shared\n"); | |
c9df406f LB |
2599 | return -ENODEV; |
2600 | } | |
8f518703 | 2601 | |
e5ef1de1 | 2602 | dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); |
c9df406f LB |
2603 | if (!dev) |
2604 | return -ENOMEM; | |
1da177e4 | 2605 | |
c9df406f | 2606 | mp = netdev_priv(dev); |
fc32b0e2 LB |
2607 | platform_set_drvdata(pdev, mp); |
2608 | ||
2609 | mp->shared = platform_get_drvdata(pd->shared); | |
2610 | mp->port_num = pd->port_number; | |
2611 | ||
c9df406f | 2612 | mp->dev = dev; |
78fff83b | 2613 | |
fc32b0e2 | 2614 | set_params(mp, pd); |
e5ef1de1 | 2615 | dev->real_num_tx_queues = mp->txq_count; |
fc32b0e2 | 2616 | |
fc32b0e2 LB |
2617 | mib_counters_clear(mp); |
2618 | INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); | |
2619 | ||
bedfe324 LB |
2620 | if (mp->phy_addr != -1) { |
2621 | err = phy_init(mp, pd); | |
2622 | if (err) | |
2623 | goto out; | |
2624 | ||
2625 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); | |
2626 | } else { | |
2627 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless); | |
2628 | } | |
81600eea | 2629 | init_pscr(mp, pd->speed, pd->duplex); |
fc32b0e2 | 2630 | |
2257e05c LB |
2631 | netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128); |
2632 | ||
2633 | init_timer(&mp->rx_oom); | |
2634 | mp->rx_oom.data = (unsigned long)mp; | |
2635 | mp->rx_oom.function = oom_timer_wrapper; | |
2636 | ||
fc32b0e2 | 2637 | |
c9df406f LB |
2638 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2639 | BUG_ON(!res); | |
2640 | dev->irq = res->start; | |
1da177e4 | 2641 | |
8fd89211 | 2642 | dev->get_stats = mv643xx_eth_get_stats; |
fc32b0e2 | 2643 | dev->hard_start_xmit = mv643xx_eth_xmit; |
c9df406f LB |
2644 | dev->open = mv643xx_eth_open; |
2645 | dev->stop = mv643xx_eth_stop; | |
c9df406f | 2646 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; |
fc32b0e2 LB |
2647 | dev->set_mac_address = mv643xx_eth_set_mac_address; |
2648 | dev->do_ioctl = mv643xx_eth_ioctl; | |
2649 | dev->change_mtu = mv643xx_eth_change_mtu; | |
c9df406f | 2650 | dev->tx_timeout = mv643xx_eth_tx_timeout; |
c9df406f | 2651 | #ifdef CONFIG_NET_POLL_CONTROLLER |
e5371493 | 2652 | dev->poll_controller = mv643xx_eth_netpoll; |
c9df406f | 2653 | #endif |
c9df406f LB |
2654 | dev->watchdog_timeo = 2 * HZ; |
2655 | dev->base_addr = 0; | |
1da177e4 | 2656 | |
c9df406f | 2657 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
e32b6617 | 2658 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM; |
1da177e4 | 2659 | |
fc32b0e2 | 2660 | SET_NETDEV_DEV(dev, &pdev->dev); |
8f518703 | 2661 | |
c9df406f | 2662 | if (mp->shared->win_protect) |
fc32b0e2 | 2663 | wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); |
1da177e4 | 2664 | |
c9df406f LB |
2665 | err = register_netdev(dev); |
2666 | if (err) | |
2667 | goto out; | |
1da177e4 | 2668 | |
fc32b0e2 LB |
2669 | dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n", |
2670 | mp->port_num, print_mac(mac, dev->dev_addr)); | |
1da177e4 | 2671 | |
13d64285 | 2672 | if (mp->tx_desc_sram_size > 0) |
fc32b0e2 | 2673 | dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n"); |
1da177e4 | 2674 | |
c9df406f | 2675 | return 0; |
1da177e4 | 2676 | |
c9df406f LB |
2677 | out: |
2678 | free_netdev(dev); | |
1da177e4 | 2679 | |
c9df406f | 2680 | return err; |
1da177e4 LT |
2681 | } |
2682 | ||
c9df406f | 2683 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2684 | { |
fc32b0e2 | 2685 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
1da177e4 | 2686 | |
fc32b0e2 | 2687 | unregister_netdev(mp->dev); |
c9df406f | 2688 | flush_scheduled_work(); |
fc32b0e2 | 2689 | free_netdev(mp->dev); |
c9df406f | 2690 | |
c9df406f | 2691 | platform_set_drvdata(pdev, NULL); |
fc32b0e2 | 2692 | |
c9df406f | 2693 | return 0; |
1da177e4 LT |
2694 | } |
2695 | ||
c9df406f | 2696 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 2697 | { |
fc32b0e2 | 2698 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
d0412d96 | 2699 | |
c9df406f | 2700 | /* Mask all interrupts on ethernet port */ |
fc32b0e2 LB |
2701 | wrl(mp, INT_MASK(mp->port_num), 0); |
2702 | rdl(mp, INT_MASK(mp->port_num)); | |
c9df406f | 2703 | |
fc32b0e2 LB |
2704 | if (netif_running(mp->dev)) |
2705 | port_reset(mp); | |
d0412d96 JC |
2706 | } |
2707 | ||
c9df406f | 2708 | static struct platform_driver mv643xx_eth_driver = { |
fc32b0e2 LB |
2709 | .probe = mv643xx_eth_probe, |
2710 | .remove = mv643xx_eth_remove, | |
2711 | .shutdown = mv643xx_eth_shutdown, | |
c9df406f | 2712 | .driver = { |
fc32b0e2 | 2713 | .name = MV643XX_ETH_NAME, |
c9df406f LB |
2714 | .owner = THIS_MODULE, |
2715 | }, | |
2716 | }; | |
2717 | ||
e5371493 | 2718 | static int __init mv643xx_eth_init_module(void) |
d0412d96 | 2719 | { |
c9df406f | 2720 | int rc; |
d0412d96 | 2721 | |
c9df406f LB |
2722 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
2723 | if (!rc) { | |
2724 | rc = platform_driver_register(&mv643xx_eth_driver); | |
2725 | if (rc) | |
2726 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
2727 | } | |
fc32b0e2 | 2728 | |
c9df406f | 2729 | return rc; |
d0412d96 | 2730 | } |
fc32b0e2 | 2731 | module_init(mv643xx_eth_init_module); |
d0412d96 | 2732 | |
e5371493 | 2733 | static void __exit mv643xx_eth_cleanup_module(void) |
d0412d96 | 2734 | { |
c9df406f LB |
2735 | platform_driver_unregister(&mv643xx_eth_driver); |
2736 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 | 2737 | } |
e5371493 | 2738 | module_exit(mv643xx_eth_cleanup_module); |
1da177e4 | 2739 | |
45675bc6 LB |
2740 | MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " |
2741 | "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); | |
c9df406f | 2742 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); |
fc32b0e2 | 2743 | MODULE_LICENSE("GPL"); |
c9df406f | 2744 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |
fc32b0e2 | 2745 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); |