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[PATCH] mv643xx_eth: Clean up interrupt handling
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 9 * written by Manish Lachwani
1da177e4
LT		 10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
c8aaea25 13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
b6298c22
AV		 35#include <linux/in.h>
36#include <linux/ip.h>
1da177e4
LT		 37#include <linux/tcp.h>
38#include <linux/udp.h>
39#include <linux/etherdevice.h>
40
41#include <linux/bitops.h>
42#include <linux/delay.h>
43#include <linux/ethtool.h>
d052d1be
RK		 44#include <linux/platform_device.h>
45
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/types.h>
48#include <asm/pgtable.h>
49#include <asm/system.h>
50#include <asm/delay.h>
51#include "mv643xx_eth.h"
52
1da177e4 53/* Static function declarations */
1da177e4
LT		 54static void eth_port_uc_addr_get(struct net_device *dev,
55 unsigned char *MacAddr);
16e03018 56static void eth_port_set_multicast_list(struct net_device *);
9f8dd319 57static void mv643xx_eth_port_enable_tx(unsigned int port_num,
12a87c64 58 unsigned int queues);
9f8dd319 59static void mv643xx_eth_port_enable_rx(unsigned int port_num,
12a87c64 60 unsigned int queues);
9f8dd319
DF		 61static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
62static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
ab4384a6
DF		 63static int mv643xx_eth_open(struct net_device *);
64static int mv643xx_eth_stop(struct net_device *);
1da177e4
LT		 65static int mv643xx_eth_change_mtu(struct net_device *, int);
66static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
67static void eth_port_init_mac_tables(unsigned int eth_port_num);
68#ifdef MV643XX_NAPI
69static int mv643xx_poll(struct net_device *dev, int *budget);
70#endif
c28a4f89 71static int ethernet_phy_get(unsigned int eth_port_num);
1da177e4
LT		 72static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
73static int ethernet_phy_detect(unsigned int eth_port_num);
c28a4f89
JC		 74static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
75static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
d0412d96 76static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
1da177e4
LT		 77static struct ethtool_ops mv643xx_ethtool_ops;
78
79static char mv643xx_driver_name[] = "mv643xx_eth";
80static char mv643xx_driver_version[] = "1.0";
81
82static void __iomem *mv643xx_eth_shared_base;
83
84/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
a9f6a0dd 85static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
1da177e4
LT		 86
87static inline u32 mv_read(int offset)
88{
dc074a8a 89 void __iomem *reg_base;
1da177e4
LT		 90
91 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
92
93 return readl(reg_base + offset);
94}
95
96static inline void mv_write(int offset, u32 data)
97{
dc074a8a 98 void __iomem *reg_base;
1da177e4
LT		 99
100 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
101 writel(data, reg_base + offset);
102}
103
104/*
105 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
106 *
107 * Input : pointer to ethernet interface network device structure
108 * new mtu size
109 * Output : 0 upon success, -EINVAL upon failure
110 */
111static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
112{
8f518703 113 if ((new_mtu > 9500) || (new_mtu < 64))
1da177e4 114 return -EINVAL;
1da177e4
LT		 115
116 dev->mtu = new_mtu;
117 /*
118 * Stop then re-open the interface. This will allocate RX skb's with
119 * the new MTU.
120 * There is a possible danger that the open will not successed, due
121 * to memory is full, which might fail the open function.
122 */
123 if (netif_running(dev)) {
ab4384a6
DF		 124 mv643xx_eth_stop(dev);
125 if (mv643xx_eth_open(dev))
1da177e4
LT		 126 printk(KERN_ERR
127 "%s: Fatal error on opening device\n",
128 dev->name);
129 }
130
1da177e4
LT		 131 return 0;
132}
133
134/*
135 * mv643xx_eth_rx_task
136 *
137 * Fills / refills RX queue on a certain gigabit ethernet port
138 *
139 * Input : pointer to ethernet interface network device structure
140 * Output : N/A
141 */
142static void mv643xx_eth_rx_task(void *data)
143{
144 struct net_device *dev = (struct net_device *)data;
145 struct mv643xx_private *mp = netdev_priv(dev);
146 struct pkt_info pkt_info;
147 struct sk_buff *skb;
b44cd572 148 int unaligned;
1da177e4
LT		 149
150 if (test_and_set_bit(0, &mp->rx_task_busy))
151 panic("%s: Error in test_set_bit / clear_bit", dev->name);
152
f98e36f1 153 while (mp->rx_desc_count < (mp->rx_ring_size - 5)) {
7303fde8 154 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + ETH_DMA_ALIGN);
1da177e4
LT		 155 if (!skb)
156 break;
f98e36f1 157 mp->rx_desc_count++;
7303fde8 158 unaligned = (u32)skb->data & (ETH_DMA_ALIGN - 1);
b44cd572 159 if (unaligned)
7303fde8 160 skb_reserve(skb, ETH_DMA_ALIGN - unaligned);
1da177e4 161 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
7303fde8
DF		 162 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
163 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
164 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
1da177e4
LT		 165 pkt_info.return_info = skb;
166 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
167 printk(KERN_ERR
168 "%s: Error allocating RX Ring\n", dev->name);
169 break;
170 }
7303fde8 171 skb_reserve(skb, ETH_HW_IP_ALIGN);
1da177e4
LT		 172 }
173 clear_bit(0, &mp->rx_task_busy);
174 /*
175 * If RX ring is empty of SKB, set a timer to try allocating
176 * again in a later time .
177 */
f98e36f1 178 if ((mp->rx_desc_count == 0) && (mp->rx_timer_flag == 0)) {
1da177e4
LT		 179 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
180 /* After 100mSec */
181 mp->timeout.expires = jiffies + (HZ / 10);
182 add_timer(&mp->timeout);
183 mp->rx_timer_flag = 1;
184 }
185#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
186 else {
187 /* Return interrupts */
188 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
c2e5b352 189 INT_UNMASK_ALL);
1da177e4
LT		 190 }
191#endif
192}
193
194/*
195 * mv643xx_eth_rx_task_timer_wrapper
196 *
197 * Timer routine to wake up RX queue filling task. This function is
198 * used only in case the RX queue is empty, and all alloc_skb has
199 * failed (due to out of memory event).
200 *
201 * Input : pointer to ethernet interface network device structure
202 * Output : N/A
203 */
204static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
205{
206 struct net_device *dev = (struct net_device *)data;
207 struct mv643xx_private *mp = netdev_priv(dev);
208
209 mp->rx_timer_flag = 0;
210 mv643xx_eth_rx_task((void *)data);
211}
212
213/*
214 * mv643xx_eth_update_mac_address
215 *
216 * Update the MAC address of the port in the address table
217 *
218 * Input : pointer to ethernet interface network device structure
219 * Output : N/A
220 */
221static void mv643xx_eth_update_mac_address(struct net_device *dev)
222{
223 struct mv643xx_private *mp = netdev_priv(dev);
224 unsigned int port_num = mp->port_num;
225
226 eth_port_init_mac_tables(port_num);
ed9b5d45 227 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 228}
229
230/*
231 * mv643xx_eth_set_rx_mode
232 *
233 * Change from promiscuos to regular rx mode
234 *
235 * Input : pointer to ethernet interface network device structure
236 * Output : N/A
237 */
238static void mv643xx_eth_set_rx_mode(struct net_device *dev)
239{
240 struct mv643xx_private *mp = netdev_priv(dev);
01999873 241 u32 config_reg;
1da177e4 242
01999873 243 config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num));
1da177e4 244 if (dev->flags & IFF_PROMISC)
01999873 245 config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
1da177e4 246 else
01999873
DF		 247 config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
248 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg);
16e03018
DF		 249
250 eth_port_set_multicast_list(dev);
1da177e4
LT		 251}
252
253/*
254 * mv643xx_eth_set_mac_address
255 *
256 * Change the interface's mac address.
257 * No special hardware thing should be done because interface is always
258 * put in promiscuous mode.
259 *
260 * Input : pointer to ethernet interface network device structure and
261 * a pointer to the designated entry to be added to the cache.
262 * Output : zero upon success, negative upon failure
263 */
264static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
265{
266 int i;
267
268 for (i = 0; i < 6; i++)
269 /* +2 is for the offset of the HW addr type */
270 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
271 mv643xx_eth_update_mac_address(dev);
272 return 0;
273}
274
275/*
276 * mv643xx_eth_tx_timeout
277 *
278 * Called upon a timeout on transmitting a packet
279 *
280 * Input : pointer to ethernet interface network device structure.
281 * Output : N/A
282 */
283static void mv643xx_eth_tx_timeout(struct net_device *dev)
284{
285 struct mv643xx_private *mp = netdev_priv(dev);
286
287 printk(KERN_INFO "%s: TX timeout ", dev->name);
288
289 /* Do the reset outside of interrupt context */
290 schedule_work(&mp->tx_timeout_task);
291}
292
293/*
294 * mv643xx_eth_tx_timeout_task
295 *
296 * Actual routine to reset the adapter when a timeout on Tx has occurred
297 */
298static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
299{
300 struct mv643xx_private *mp = netdev_priv(dev);
301
302 netif_device_detach(dev);
303 eth_port_reset(mp->port_num);
ed9b5d45 304 eth_port_start(dev);
1da177e4
LT		 305 netif_device_attach(dev);
306}
307
ff561eef
DF		 308/**
309 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
1da177e4 310 *
ff561eef 311 * If force is non-zero, frees uncompleted descriptors as well
1da177e4 312 */
ff561eef 313int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1da177e4
LT		 314{
315 struct mv643xx_private *mp = netdev_priv(dev);
ff561eef
DF		 316 struct eth_tx_desc *desc;
317 u32 cmd_sts;
318 struct sk_buff *skb;
319 unsigned long flags;
320 int tx_index;
321 dma_addr_t addr;
322 int count;
323 int released = 0;
1da177e4 324
ff561eef
DF		 325 while (mp->tx_desc_count > 0) {
326 spin_lock_irqsave(&mp->lock, flags);
327 tx_index = mp->tx_used_desc_q;
328 desc = &mp->p_tx_desc_area[tx_index];
329 cmd_sts = desc->cmd_sts;
330
331 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
332 spin_unlock_irqrestore(&mp->lock, flags);
333 return released;
334 }
335
336 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
337 mp->tx_desc_count--;
338
339 addr = desc->buf_ptr;
340 count = desc->byte_cnt;
341 skb = mp->tx_skb[tx_index];
342 if (skb)
343 mp->tx_skb[tx_index] = NULL;
344
345 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 346
7303fde8 347 if (cmd_sts & ETH_ERROR_SUMMARY) {
1da177e4 348 printk("%s: Error in TX\n", dev->name);
ff561eef 349 mp->stats.tx_errors++;
1da177e4
LT		 350 }
351
ff561eef
DF		 352 if (cmd_sts & ETH_TX_FIRST_DESC)
353 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
cb415d30 354 else
ff561eef 355 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1da177e4 356
ff561eef
DF		 357 if (skb)
358 dev_kfree_skb_irq(skb);
359
360 released = 1;
1da177e4
LT		 361 }
362
1da177e4
LT		 363 return released;
364}
365
ff561eef
DF		 366static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
367{
368 struct mv643xx_private *mp = netdev_priv(dev);
369
370 if (mv643xx_eth_free_tx_descs(dev, 0) &&
371 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
372 netif_wake_queue(dev);
373}
374
375static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
376{
377 mv643xx_eth_free_tx_descs(dev, 1);
378}
379
1da177e4
LT		 380/*
381 * mv643xx_eth_receive
382 *
383 * This function is forward packets that are received from the port's
384 * queues toward kernel core or FastRoute them to another interface.
385 *
386 * Input : dev - a pointer to the required interface
387 * max - maximum number to receive (0 means unlimted)
388 *
389 * Output : number of served packets
390 */
1da177e4 391static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
1da177e4
LT		 392{
393 struct mv643xx_private *mp = netdev_priv(dev);
394 struct net_device_stats *stats = &mp->stats;
395 unsigned int received_packets = 0;
396 struct sk_buff *skb;
397 struct pkt_info pkt_info;
398
b1dd9ca1 399 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
f98e36f1 400 mp->rx_desc_count--;
1da177e4 401 received_packets++;
b1dd9ca1 402
468d09f8
DF		 403 /*
404 * Update statistics.
405 * Note byte count includes 4 byte CRC count
406 */
1da177e4
LT		 407 stats->rx_packets++;
408 stats->rx_bytes += pkt_info.byte_cnt;
409 skb = pkt_info.return_info;
410 /*
411 * In case received a packet without first / last bits on OR
412 * the error summary bit is on, the packets needs to be dropeed.
413 */
414 if (((pkt_info.cmd_sts
415 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
416 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
417 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
418 stats->rx_dropped++;
419 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
420 ETH_RX_LAST_DESC)) !=
421 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
422 if (net_ratelimit())
423 printk(KERN_ERR
424 "%s: Received packet spread "
425 "on multiple descriptors\n",
426 dev->name);
427 }
428 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
429 stats->rx_errors++;
430
431 dev_kfree_skb_irq(skb);
432 } else {
433 /*
434 * The -4 is for the CRC in the trailer of the
435 * received packet
436 */
437 skb_put(skb, pkt_info.byte_cnt - 4);
438 skb->dev = dev;
439
440 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
441 skb->ip_summed = CHECKSUM_UNNECESSARY;
442 skb->csum = htons(
443 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
444 }
445 skb->protocol = eth_type_trans(skb, dev);
446#ifdef MV643XX_NAPI
447 netif_receive_skb(skb);
448#else
449 netif_rx(skb);
450#endif
451 }
12ad74f8 452 dev->last_rx = jiffies;
1da177e4
LT		 453 }
454
455 return received_packets;
456}
457
d0412d96
JC		 458/* Set the mv643xx port configuration register for the speed/duplex mode. */
459static void mv643xx_eth_update_pscr(struct net_device *dev,
460 struct ethtool_cmd *ecmd)
461{
462 struct mv643xx_private *mp = netdev_priv(dev);
463 int port_num = mp->port_num;
464 u32 o_pscr, n_pscr;
12a87c64 465 unsigned int queues;
d0412d96
JC		 466
467 o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
468 n_pscr = o_pscr;
469
470 /* clear speed, duplex and rx buffer size fields */
471 n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 |
472 MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
473 MV643XX_ETH_SET_FULL_DUPLEX_MODE |
474 MV643XX_ETH_MAX_RX_PACKET_MASK);
475
476 if (ecmd->duplex == DUPLEX_FULL)
477 n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE;
478
479 if (ecmd->speed == SPEED_1000)
480 n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
481 MV643XX_ETH_MAX_RX_PACKET_9700BYTE;
482 else {
483 if (ecmd->speed == SPEED_100)
484 n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100;
485 n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE;
486 }
487
488 if (n_pscr != o_pscr) {
489 if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0)
490 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
491 n_pscr);
492 else {
12a87c64 493 queues = mv643xx_eth_port_disable_tx(port_num);
d0412d96
JC		 494
495 o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
496 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
497 o_pscr);
498 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
499 n_pscr);
500 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
501 n_pscr);
12a87c64
DF		 502 if (queues)
503 mv643xx_eth_port_enable_tx(port_num, queues);
d0412d96
JC		 504 }
505 }
506}
507
1da177e4
LT		 508/*
509 * mv643xx_eth_int_handler
510 *
511 * Main interrupt handler for the gigbit ethernet ports
512 *
513 * Input : irq - irq number (not used)
514 * dev_id - a pointer to the required interface's data structure
515 * regs - not used
516 * Output : N/A
517 */
518
519static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
b4de9051 520 struct pt_regs *regs)
1da177e4
LT		 521{
522 struct net_device *dev = (struct net_device *)dev_id;
523 struct mv643xx_private *mp = netdev_priv(dev);
524 u32 eth_int_cause, eth_int_cause_ext = 0;
525 unsigned int port_num = mp->port_num;
526
527 /* Read interrupt cause registers */
528 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
7303fde8 529 ETH_INT_UNMASK_ALL;
468d09f8 530 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1da177e4
LT		 531 eth_int_cause_ext = mv_read(
532 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
7303fde8 533 ETH_INT_UNMASK_ALL_EXT;
1da177e4 534#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
c2e5b352 535 /* Mask all interrupts on ethernet port */
1da177e4 536 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
c2e5b352 537 INT_MASK_ALL);
8f518703
DF		 538 /* wait for previous write to take effect */
539 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
540
1da177e4
LT		 541 queue_task(&mp->rx_task, &tq_immediate);
542 mark_bh(IMMEDIATE_BH);
543#else
544 mp->rx_task.func(dev);
545#endif
468d09f8
DF		 546 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),
547 ~eth_int_cause_ext);
1da177e4 548 }
7303fde8 549
1da177e4 550 /* PHY status changed */
468d09f8 551 if (eth_int_cause_ext & ETH_INT_CAUSE_PHY) {
d0412d96
JC		 552 struct ethtool_cmd cmd;
553
c28a4f89 554 if (mii_link_ok(&mp->mii)) {
d0412d96
JC		 555 mii_ethtool_gset(&mp->mii, &cmd);
556 mv643xx_eth_update_pscr(dev, &cmd);
ff561eef
DF		 557 mv643xx_eth_port_enable_tx(port_num,
558 ETH_TX_QUEUES_ENABLED);
c28a4f89
JC		 559 if (!netif_carrier_ok(dev)) {
560 netif_carrier_on(dev);
ff561eef
DF		 561 if (mp->tx_ring_size - mp->tx_desc_count >=
562 MAX_DESCS_PER_SKB)
d0412d96 563 netif_wake_queue(dev);
c28a4f89
JC		 564 }
565 } else if (netif_carrier_ok(dev)) {
1da177e4 566 netif_stop_queue(dev);
c28a4f89 567 netif_carrier_off(dev);
1da177e4
LT		 568 }
569 }
570
468d09f8
DF		 571#ifdef MV643XX_NAPI
572 if (eth_int_cause & ETH_INT_CAUSE_RX) {
573 /* schedule the NAPI poll routine to maintain port */
574 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
575 ETH_INT_MASK_ALL);
576 /* wait for previous write to complete */
577 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
578
579 netif_rx_schedule(dev);
580 }
581#else
582 if (eth_int_cause & ETH_INT_CAUSE_RX)
583 mv643xx_eth_receive_queue(dev, INT_MAX);
584 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
585 mv643xx_eth_free_completed_tx_descs(dev);
586#endif
587
1da177e4
LT		 588 /*
589 * If no real interrupt occured, exit.
590 * This can happen when using gigE interrupt coalescing mechanism.
591 */
592 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
593 return IRQ_NONE;
594
595 return IRQ_HANDLED;
596}
597
598#ifdef MV643XX_COAL
599
600/*
601 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
602 *
603 * DESCRIPTION:
604 * This routine sets the RX coalescing interrupt mechanism parameter.
605 * This parameter is a timeout counter, that counts in 64 t_clk
606 * chunks ; that when timeout event occurs a maskable interrupt
607 * occurs.
608 * The parameter is calculated using the tClk of the MV-643xx chip
609 * , and the required delay of the interrupt in usec.
610 *
611 * INPUT:
612 * unsigned int eth_port_num Ethernet port number
613 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
614 * unsigned int delay Delay in usec
615 *
616 * OUTPUT:
617 * Interrupt coalescing mechanism value is set in MV-643xx chip.
618 *
619 * RETURN:
620 * The interrupt coalescing value set in the gigE port.
621 *
622 */
623static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
624 unsigned int t_clk, unsigned int delay)
625{
626 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
627
628 /* Set RX Coalescing mechanism */
629 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
630 ((coal & 0x3fff) << 8) |
631 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
632 & 0xffc000ff));
633
634 return coal;
635}
636#endif
637
638/*
639 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
640 *
641 * DESCRIPTION:
642 * This routine sets the TX coalescing interrupt mechanism parameter.
643 * This parameter is a timeout counter, that counts in 64 t_clk
644 * chunks ; that when timeout event occurs a maskable interrupt
645 * occurs.
646 * The parameter is calculated using the t_cLK frequency of the
647 * MV-643xx chip and the required delay in the interrupt in uSec
648 *
649 * INPUT:
650 * unsigned int eth_port_num Ethernet port number
651 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
652 * unsigned int delay Delay in uSeconds
653 *
654 * OUTPUT:
655 * Interrupt coalescing mechanism value is set in MV-643xx chip.
656 *
657 * RETURN:
658 * The interrupt coalescing value set in the gigE port.
659 *
660 */
661static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
662 unsigned int t_clk, unsigned int delay)
663{
664 unsigned int coal;
665 coal = ((t_clk / 1000000) * delay) / 64;
666 /* Set TX Coalescing mechanism */
667 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
668 coal << 4);
669 return coal;
670}
671
1da177e4
LT		 672/*
673 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
674 *
675 * DESCRIPTION:
676 * This function prepares a Rx chained list of descriptors and packet
677 * buffers in a form of a ring. The routine must be called after port
678 * initialization routine and before port start routine.
679 * The Ethernet SDMA engine uses CPU bus addresses to access the various
680 * devices in the system (i.e. DRAM). This function uses the ethernet
681 * struct 'virtual to physical' routine (set by the user) to set the ring
682 * with physical addresses.
683 *
684 * INPUT:
685 * struct mv643xx_private *mp Ethernet Port Control srtuct.
686 *
687 * OUTPUT:
688 * The routine updates the Ethernet port control struct with information
689 * regarding the Rx descriptors and buffers.
690 *
691 * RETURN:
692 * None.
693 */
694static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
695{
696 volatile struct eth_rx_desc *p_rx_desc;
697 int rx_desc_num = mp->rx_ring_size;
698 int i;
699
700 /* initialize the next_desc_ptr links in the Rx descriptors ring */
701 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
702 for (i = 0; i < rx_desc_num; i++) {
703 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
704 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
705 }
706
707 /* Save Rx desc pointer to driver struct. */
708 mp->rx_curr_desc_q = 0;
709 mp->rx_used_desc_q = 0;
710
711 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
1da177e4
LT		 712}
713
714/*
715 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
716 *
717 * DESCRIPTION:
718 * This function prepares a Tx chained list of descriptors and packet
719 * buffers in a form of a ring. The routine must be called after port
720 * initialization routine and before port start routine.
721 * The Ethernet SDMA engine uses CPU bus addresses to access the various
722 * devices in the system (i.e. DRAM). This function uses the ethernet
723 * struct 'virtual to physical' routine (set by the user) to set the ring
724 * with physical addresses.
725 *
726 * INPUT:
727 * struct mv643xx_private *mp Ethernet Port Control srtuct.
728 *
729 * OUTPUT:
730 * The routine updates the Ethernet port control struct with information
731 * regarding the Tx descriptors and buffers.
732 *
733 * RETURN:
734 * None.
735 */
736static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
737{
738 int tx_desc_num = mp->tx_ring_size;
739 struct eth_tx_desc *p_tx_desc;
740 int i;
741
742 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
743 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
744 for (i = 0; i < tx_desc_num; i++) {
745 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
746 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
747 }
748
749 mp->tx_curr_desc_q = 0;
750 mp->tx_used_desc_q = 0;
1da177e4
LT		 751
752 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
1da177e4
LT		 753}
754
d0412d96
JC		 755static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
756{
757 struct mv643xx_private *mp = netdev_priv(dev);
758 int err;
759
760 spin_lock_irq(&mp->lock);
761 err = mii_ethtool_sset(&mp->mii, cmd);
762 spin_unlock_irq(&mp->lock);
763
764 return err;
765}
766
767static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
768{
769 struct mv643xx_private *mp = netdev_priv(dev);
770 int err;
771
772 spin_lock_irq(&mp->lock);
773 err = mii_ethtool_gset(&mp->mii, cmd);
774 spin_unlock_irq(&mp->lock);
775
776 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
777 cmd->supported &= ~SUPPORTED_1000baseT_Half;
778 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
779
780 return err;
781}
782
ab4384a6
DF		 783/*
784 * mv643xx_eth_open
785 *
786 * This function is called when openning the network device. The function
787 * should initialize all the hardware, initialize cyclic Rx/Tx
788 * descriptors chain and buffers and allocate an IRQ to the network
789 * device.
790 *
791 * Input : a pointer to the network device structure
792 *
793 * Output : zero of success , nonzero if fails.
794 */
795
796static int mv643xx_eth_open(struct net_device *dev)
1da177e4
LT		 797{
798 struct mv643xx_private *mp = netdev_priv(dev);
799 unsigned int port_num = mp->port_num;
800 unsigned int size;
ab4384a6
DF		 801 int err;
802
803 err = request_irq(dev->irq, mv643xx_eth_int_handler,
804 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
805 if (err) {
806 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
807 port_num);
808 return -EAGAIN;
809 }
1da177e4 810
1da177e4
LT		 811 eth_port_init(mp);
812
813 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
814
815 memset(&mp->timeout, 0, sizeof(struct timer_list));
816 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
817 mp->timeout.data = (unsigned long)dev;
818
819 mp->rx_task_busy = 0;
820 mp->rx_timer_flag = 0;
821
822 /* Allocate RX and TX skb rings */
823 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
824 GFP_KERNEL);
825 if (!mp->rx_skb) {
826 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
ab4384a6
DF		 827 err = -ENOMEM;
828 goto out_free_irq;
1da177e4
LT		 829 }
830 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
831 GFP_KERNEL);
832 if (!mp->tx_skb) {
833 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
ab4384a6
DF		 834 err = -ENOMEM;
835 goto out_free_rx_skb;
1da177e4
LT		 836 }
837
838 /* Allocate TX ring */
f98e36f1 839 mp->tx_desc_count = 0;
1da177e4
LT		 840 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
841 mp->tx_desc_area_size = size;
842
843 if (mp->tx_sram_size) {
844 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
845 mp->tx_sram_size);
846 mp->tx_desc_dma = mp->tx_sram_addr;
847 } else
848 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
849 &mp->tx_desc_dma,
850 GFP_KERNEL);
851
852 if (!mp->p_tx_desc_area) {
853 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
854 dev->name, size);
ab4384a6
DF		 855 err = -ENOMEM;
856 goto out_free_tx_skb;
1da177e4
LT		 857 }
858 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
859 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
860
861 ether_init_tx_desc_ring(mp);
862
863 /* Allocate RX ring */
f98e36f1 864 mp->rx_desc_count = 0;
1da177e4
LT		 865 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
866 mp->rx_desc_area_size = size;
867
868 if (mp->rx_sram_size) {
869 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
870 mp->rx_sram_size);
871 mp->rx_desc_dma = mp->rx_sram_addr;
872 } else
873 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
874 &mp->rx_desc_dma,
875 GFP_KERNEL);
876
877 if (!mp->p_rx_desc_area) {
878 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
879 dev->name, size);
880 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
881 dev->name);
882 if (mp->rx_sram_size)
dd09b1de 883 iounmap(mp->p_tx_desc_area);
1da177e4
LT		 884 else
885 dma_free_coherent(NULL, mp->tx_desc_area_size,
886 mp->p_tx_desc_area, mp->tx_desc_dma);
ab4384a6
DF		 887 err = -ENOMEM;
888 goto out_free_tx_skb;
1da177e4
LT		 889 }
890 memset((void *)mp->p_rx_desc_area, 0, size);
891
892 ether_init_rx_desc_ring(mp);
893
894 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
895
d0412d96
JC		 896 /* Clear any pending ethernet port interrupts */
897 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
898 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
899
ed9b5d45 900 eth_port_start(dev);
1da177e4
LT		 901
902 /* Interrupt Coalescing */
903
904#ifdef MV643XX_COAL
905 mp->rx_int_coal =
906 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
907#endif
908
909 mp->tx_int_coal =
910 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
911
8f518703
DF		 912 /* Unmask phy and link status changes interrupts */
913 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
7303fde8 914 ETH_INT_UNMASK_ALL_EXT);
1da177e4 915
8f518703 916 /* Unmask RX buffer and TX end interrupt */
7303fde8 917 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
d0412d96 918
1da177e4 919 return 0;
ab4384a6
DF		 920
921out_free_tx_skb:
922 kfree(mp->tx_skb);
923out_free_rx_skb:
924 kfree(mp->rx_skb);
925out_free_irq:
926 free_irq(dev->irq, dev);
927
928 return err;
1da177e4
LT		 929}
930
931static void mv643xx_eth_free_tx_rings(struct net_device *dev)
932{
933 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4
LT		 934
935 /* Stop Tx Queues */
ff561eef 936 mv643xx_eth_port_disable_tx(mp->port_num);
1da177e4 937
ff561eef
DF		 938 /* Free outstanding skb's on TX ring */
939 mv643xx_eth_free_all_tx_descs(dev);
940
941 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1da177e4
LT		 942
943 /* Free TX ring */
944 if (mp->tx_sram_size)
945 iounmap(mp->p_tx_desc_area);
946 else
947 dma_free_coherent(NULL, mp->tx_desc_area_size,
948 mp->p_tx_desc_area, mp->tx_desc_dma);
949}
950
951static void mv643xx_eth_free_rx_rings(struct net_device *dev)
952{
953 struct mv643xx_private *mp = netdev_priv(dev);
954 unsigned int port_num = mp->port_num;
955 int curr;
956
957 /* Stop RX Queues */
9f8dd319 958 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 959
960 /* Free preallocated skb's on RX rings */
f98e36f1 961 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1da177e4
LT		 962 if (mp->rx_skb[curr]) {
963 dev_kfree_skb(mp->rx_skb[curr]);
f98e36f1 964 mp->rx_desc_count--;
1da177e4
LT		 965 }
966 }
967
f98e36f1 968 if (mp->rx_desc_count)
1da177e4
LT		 969 printk(KERN_ERR
970 "%s: Error in freeing Rx Ring. %d skb's still"
971 " stuck in RX Ring - ignoring them\n", dev->name,
f98e36f1 972 mp->rx_desc_count);
1da177e4
LT		 973 /* Free RX ring */
974 if (mp->rx_sram_size)
975 iounmap(mp->p_rx_desc_area);
976 else
977 dma_free_coherent(NULL, mp->rx_desc_area_size,
978 mp->p_rx_desc_area, mp->rx_desc_dma);
979}
980
981/*
982 * mv643xx_eth_stop
983 *
984 * This function is used when closing the network device.
985 * It updates the hardware,
986 * release all memory that holds buffers and descriptors and release the IRQ.
987 * Input : a pointer to the device structure
988 * Output : zero if success , nonzero if fails
989 */
990
ab4384a6 991static int mv643xx_eth_stop(struct net_device *dev)
1da177e4
LT		 992{
993 struct mv643xx_private *mp = netdev_priv(dev);
994 unsigned int port_num = mp->port_num;
995
c2e5b352 996 /* Mask all interrupts on ethernet port */
7303fde8 997 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
c2e5b352 998 /* wait for previous write to complete */
8f518703
DF		 999 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1000
1001#ifdef MV643XX_NAPI
1002 netif_poll_disable(dev);
1003#endif
1da177e4
LT		 1004 netif_carrier_off(dev);
1005 netif_stop_queue(dev);
1006
1da177e4
LT		 1007 eth_port_reset(mp->port_num);
1008
8f518703
DF		 1009 mv643xx_eth_free_tx_rings(dev);
1010 mv643xx_eth_free_rx_rings(dev);
1da177e4 1011
8f518703
DF		 1012#ifdef MV643XX_NAPI
1013 netif_poll_enable(dev);
1014#endif
1da177e4 1015
1da177e4 1016 free_irq(dev->irq, dev);
1da177e4
LT		 1017
1018 return 0;
1019}
1020
1021#ifdef MV643XX_NAPI
1da177e4
LT		 1022/*
1023 * mv643xx_poll
1024 *
1025 * This function is used in case of NAPI
1026 */
1027static int mv643xx_poll(struct net_device *dev, int *budget)
1028{
1029 struct mv643xx_private *mp = netdev_priv(dev);
1030 int done = 1, orig_budget, work_done;
1031 unsigned int port_num = mp->port_num;
1da177e4
LT		 1032
1033#ifdef MV643XX_TX_FAST_REFILL
1034 if (++mp->tx_clean_threshold > 5) {
ff561eef 1035 mv643xx_eth_free_completed_tx_descs(dev);
1da177e4 1036 mp->tx_clean_threshold = 0;
1da177e4
LT		 1037 }
1038#endif
1039
1040 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1041 != (u32) mp->rx_used_desc_q) {
1042 orig_budget = *budget;
1043 if (orig_budget > dev->quota)
1044 orig_budget = dev->quota;
1045 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1046 mp->rx_task.func(dev);
1047 *budget -= work_done;
1048 dev->quota -= work_done;
1049 if (work_done >= orig_budget)
1050 done = 0;
1051 }
1052
1053 if (done) {
8f518703 1054 netif_rx_complete(dev);
1da177e4
LT		 1055 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1056 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1057 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
7303fde8 1058 ETH_INT_UNMASK_ALL);
1da177e4
LT		 1059 }
1060
1061 return done ? 0 : 1;
1062}
1063#endif
1064
c8aaea25
DF		 1065/**
1066 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1067 *
1068 * Hardware can't handle unaligned fragments smaller than 9 bytes.
f7ea3337
PJ		 1069 * This helper function detects that case.
1070 */
1071
1072static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1073{
b4de9051
DF		 1074 unsigned int frag;
1075 skb_frag_t *fragp;
f7ea3337 1076
b4de9051
DF		 1077 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1078 fragp = &skb_shinfo(skb)->frags[frag];
1079 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1080 return 1;
1081 }
1082 return 0;
f7ea3337
PJ		 1083}
1084
c8aaea25
DF		 1085/**
1086 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1087 */
1088static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1089{
1090 int tx_desc_curr;
1091
c8aaea25 1092 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
c8aaea25 1093
ff561eef 1094 tx_desc_curr = mp->tx_curr_desc_q;
c8aaea25
DF		 1095 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
1096
1097 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
1098
1099 return tx_desc_curr;
1100}
1101
1102/**
1103 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1da177e4 1104 *
c8aaea25
DF		 1105 * Ensure the data for each fragment to be transmitted is mapped properly,
1106 * then fill in descriptors in the tx hw queue.
1da177e4 1107 */
c8aaea25
DF		 1108static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1109 struct sk_buff *skb)
1da177e4 1110{
c8aaea25
DF		 1111 int frag;
1112 int tx_index;
1113 struct eth_tx_desc *desc;
1da177e4 1114
c8aaea25
DF		 1115 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1116 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1117
1118 tx_index = eth_alloc_tx_desc_index(mp);
1119 desc = &mp->p_tx_desc_area[tx_index];
1120
1121 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1122 /* Last Frag enables interrupt and frees the skb */
1123 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1124 desc->cmd_sts |= ETH_ZERO_PADDING |
1125 ETH_TX_LAST_DESC |
1126 ETH_TX_ENABLE_INTERRUPT;
1127 mp->tx_skb[tx_index] = skb;
1128 } else
1129 mp->tx_skb[tx_index] = 0;
1130
1131 desc = &mp->p_tx_desc_area[tx_index];
1132 desc->l4i_chk = 0;
1133 desc->byte_cnt = this_frag->size;
1134 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1135 this_frag->page_offset,
1136 this_frag->size,
1137 DMA_TO_DEVICE);
1da177e4 1138 }
c8aaea25 1139}
1da177e4 1140
c8aaea25
DF		 1141/**
1142 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1143 *
1144 * Ensure the data for an skb to be transmitted is mapped properly,
1145 * then fill in descriptors in the tx hw queue and start the hardware.
1146 */
ff561eef
DF		 1147static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1148 struct sk_buff *skb)
c8aaea25
DF		 1149{
1150 int tx_index;
1151 struct eth_tx_desc *desc;
1152 u32 cmd_sts;
1153 int length;
ff561eef 1154 int nr_frags = skb_shinfo(skb)->nr_frags;
1da177e4 1155
c8aaea25 1156 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1da177e4 1157
c8aaea25
DF		 1158 tx_index = eth_alloc_tx_desc_index(mp);
1159 desc = &mp->p_tx_desc_area[tx_index];
1160
ff561eef 1161 if (nr_frags) {
c8aaea25
DF		 1162 eth_tx_fill_frag_descs(mp, skb);
1163
1164 length = skb_headlen(skb);
1165 mp->tx_skb[tx_index] = 0;
1166 } else {
1167 cmd_sts |= ETH_ZERO_PADDING |
1168 ETH_TX_LAST_DESC |
1169 ETH_TX_ENABLE_INTERRUPT;
1170 length = skb->len;
1171 mp->tx_skb[tx_index] = skb;
f7ea3337
PJ		 1172 }
1173
c8aaea25
DF		 1174 desc->byte_cnt = length;
1175 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1da177e4 1176
c8aaea25
DF		 1177 if (skb->ip_summed == CHECKSUM_HW) {
1178 BUG_ON(skb->protocol != ETH_P_IP);
1179
1180 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1181 ETH_GEN_IP_V_4_CHECKSUM |
1182 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1183
1184 switch (skb->nh.iph->protocol) {
1185 case IPPROTO_UDP:
1186 cmd_sts |= ETH_UDP_FRAME;
1187 desc->l4i_chk = skb->h.uh->check;
1188 break;
1189 case IPPROTO_TCP:
1190 desc->l4i_chk = skb->h.th->check;
1191 break;
1192 default:
1193 BUG();
1da177e4 1194 }
1da177e4 1195 } else {
c8aaea25
DF		 1196 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1197 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1198 desc->l4i_chk = 0;
1199 }
1da177e4 1200
c8aaea25
DF		 1201 /* ensure all other descriptors are written before first cmd_sts */
1202 wmb();
1203 desc->cmd_sts = cmd_sts;
1da177e4 1204
c8aaea25
DF		 1205 /* ensure all descriptors are written before poking hardware */
1206 wmb();
ff561eef 1207 mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED);
1da177e4 1208
ff561eef 1209 mp->tx_desc_count += nr_frags + 1;
c8aaea25 1210}
1da177e4 1211
c8aaea25
DF		 1212/**
1213 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1214 *
1215 */
1216static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1217{
1218 struct mv643xx_private *mp = netdev_priv(dev);
1219 struct net_device_stats *stats = &mp->stats;
1220 unsigned long flags;
1da177e4 1221
c8aaea25
DF		 1222 BUG_ON(netif_queue_stopped(dev));
1223 BUG_ON(skb == NULL);
1224 BUG_ON(mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB);
1da177e4 1225
c8aaea25
DF		 1226 if (has_tiny_unaligned_frags(skb)) {
1227 if ((skb_linearize(skb, GFP_ATOMIC) != 0)) {
1228 stats->tx_dropped++;
1229 printk(KERN_DEBUG "%s: failed to linearize tiny "
1230 "unaligned fragment\n", dev->name);
1231 return 1;
1da177e4
LT		 1232 }
1233 }
f7ea3337 1234
c8aaea25 1235 spin_lock_irqsave(&mp->lock, flags);
1da177e4 1236
ff561eef
DF		 1237 eth_tx_submit_descs_for_skb(mp, skb);
1238 stats->tx_bytes = skb->len;
1da177e4
LT		 1239 stats->tx_packets++;
1240 dev->trans_start = jiffies;
1241
c8aaea25
DF		 1242 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1243 netif_stop_queue(dev);
1244
1da177e4
LT		 1245 spin_unlock_irqrestore(&mp->lock, flags);
1246
1247 return 0; /* success */
1248}
1249
1250/*
1251 * mv643xx_eth_get_stats
1252 *
1253 * Returns a pointer to the interface statistics.
1254 *
1255 * Input : dev - a pointer to the required interface
1256 *
1257 * Output : a pointer to the interface's statistics
1258 */
1259
1260static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1261{
1262 struct mv643xx_private *mp = netdev_priv(dev);
1263
1264 return &mp->stats;
1265}
1266
63c9e549 1267#ifdef CONFIG_NET_POLL_CONTROLLER
63c9e549
DF		 1268static void mv643xx_netpoll(struct net_device *netdev)
1269{
1270 struct mv643xx_private *mp = netdev_priv(netdev);
c2e5b352
DF		 1271 int port_num = mp->port_num;
1272
7303fde8 1273 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
c2e5b352
DF		 1274 /* wait for previous write to complete */
1275 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
63c9e549 1276
63c9e549 1277 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
c2e5b352 1278
7303fde8 1279 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
63c9e549
DF		 1280}
1281#endif
1282
d0412d96
JC		 1283static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
1284 int speed, int duplex,
1285 struct ethtool_cmd *cmd)
1286{
1287 struct mv643xx_private *mp = netdev_priv(dev);
1288
1289 memset(cmd, 0, sizeof(*cmd));
1290
1291 cmd->port = PORT_MII;
1292 cmd->transceiver = XCVR_INTERNAL;
1293 cmd->phy_address = phy_address;
1294
1295 if (speed == 0) {
1296 cmd->autoneg = AUTONEG_ENABLE;
1297 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1298 cmd->speed = SPEED_100;
1299 cmd->advertising = ADVERTISED_10baseT_Half |
1300 ADVERTISED_10baseT_Full |
1301 ADVERTISED_100baseT_Half |
1302 ADVERTISED_100baseT_Full;
1303 if (mp->mii.supports_gmii)
1304 cmd->advertising |= ADVERTISED_1000baseT_Full;
1305 } else {
1306 cmd->autoneg = AUTONEG_DISABLE;
1307 cmd->speed = speed;
1308 cmd->duplex = duplex;
1309 }
1310}
1311
1da177e4
LT		 1312/*/
1313 * mv643xx_eth_probe
1314 *
1315 * First function called after registering the network device.
1316 * It's purpose is to initialize the device as an ethernet device,
1317 * fill the ethernet device structure with pointers * to functions,
1318 * and set the MAC address of the interface
1319 *
1320 * Input : struct device *
1321 * Output : -ENOMEM if failed , 0 if success
1322 */
3ae5eaec 1323static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 1324{
1da177e4
LT		 1325 struct mv643xx_eth_platform_data *pd;
1326 int port_num = pdev->id;
1327 struct mv643xx_private *mp;
1328 struct net_device *dev;
1329 u8 *p;
1330 struct resource *res;
1331 int err;
d0412d96 1332 struct ethtool_cmd cmd;
01999873
DF		 1333 int duplex = DUPLEX_HALF;
1334 int speed = 0; /* default to auto-negotiation */
1da177e4
LT		 1335
1336 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1337 if (!dev)
1338 return -ENOMEM;
1339
3ae5eaec 1340 platform_set_drvdata(pdev, dev);
1da177e4
LT		 1341
1342 mp = netdev_priv(dev);
1343
1344 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1345 BUG_ON(!res);
1346 dev->irq = res->start;
1347
1348 mp->port_num = port_num;
1349
1350 dev->open = mv643xx_eth_open;
1351 dev->stop = mv643xx_eth_stop;
1352 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1353 dev->get_stats = mv643xx_eth_get_stats;
1354 dev->set_mac_address = mv643xx_eth_set_mac_address;
1355 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1356
1357 /* No need to Tx Timeout */
1358 dev->tx_timeout = mv643xx_eth_tx_timeout;
1359#ifdef MV643XX_NAPI
1360 dev->poll = mv643xx_poll;
1361 dev->weight = 64;
1362#endif
1363
63c9e549
DF		 1364#ifdef CONFIG_NET_POLL_CONTROLLER
1365 dev->poll_controller = mv643xx_netpoll;
1366#endif
1367
1da177e4
LT		 1368 dev->watchdog_timeo = 2 * HZ;
1369 dev->tx_queue_len = mp->tx_ring_size;
1370 dev->base_addr = 0;
1371 dev->change_mtu = mv643xx_eth_change_mtu;
d0412d96 1372 dev->do_ioctl = mv643xx_eth_do_ioctl;
1da177e4
LT		 1373 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1374
1375#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1376#ifdef MAX_SKB_FRAGS
1377 /*
1378 * Zero copy can only work if we use Discovery II memory. Else, we will
1379 * have to map the buffers to ISA memory which is only 16 MB
1380 */
63890576 1381 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4
LT		 1382#endif
1383#endif
1384
1385 /* Configure the timeout task */
1386 INIT_WORK(&mp->tx_timeout_task,
1387 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1388
1389 spin_lock_init(&mp->lock);
1390
1391 /* set default config values */
1392 eth_port_uc_addr_get(dev, dev->dev_addr);
1da177e4
LT		 1393 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1394 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1395
1396 pd = pdev->dev.platform_data;
1397 if (pd) {
01999873 1398 if (pd->mac_addr)
1da177e4
LT		 1399 memcpy(dev->dev_addr, pd->mac_addr, 6);
1400
1401 if (pd->phy_addr || pd->force_phy_addr)
1402 ethernet_phy_set(port_num, pd->phy_addr);
1403
1da177e4
LT		 1404 if (pd->rx_queue_size)
1405 mp->rx_ring_size = pd->rx_queue_size;
1406
1407 if (pd->tx_queue_size)
1408 mp->tx_ring_size = pd->tx_queue_size;
1409
1410 if (pd->tx_sram_size) {
1411 mp->tx_sram_size = pd->tx_sram_size;
1412 mp->tx_sram_addr = pd->tx_sram_addr;
1413 }
1414
1415 if (pd->rx_sram_size) {
1416 mp->rx_sram_size = pd->rx_sram_size;
1417 mp->rx_sram_addr = pd->rx_sram_addr;
1418 }
01999873
DF		 1419
1420 duplex = pd->duplex;
1421 speed = pd->speed;
1da177e4
LT		 1422 }
1423
c28a4f89
JC		 1424 /* Hook up MII support for ethtool */
1425 mp->mii.dev = dev;
1426 mp->mii.mdio_read = mv643xx_mdio_read;
1427 mp->mii.mdio_write = mv643xx_mdio_write;
1428 mp->mii.phy_id = ethernet_phy_get(port_num);
1429 mp->mii.phy_id_mask = 0x3f;
1430 mp->mii.reg_num_mask = 0x1f;
1431
1da177e4
LT		 1432 err = ethernet_phy_detect(port_num);
1433 if (err) {
1434 pr_debug("MV643xx ethernet port %d: "
1435 "No PHY detected at addr %d\n",
1436 port_num, ethernet_phy_get(port_num));
d0412d96 1437 goto out;
1da177e4
LT		 1438 }
1439
01999873 1440 ethernet_phy_reset(port_num);
c28a4f89 1441 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
d0412d96
JC		 1442 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
1443 mv643xx_eth_update_pscr(dev, &cmd);
1444 mv643xx_set_settings(dev, &cmd);
c28a4f89 1445
1da177e4
LT		 1446 err = register_netdev(dev);
1447 if (err)
1448 goto out;
1449
1450 p = dev->dev_addr;
1451 printk(KERN_NOTICE
1452 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1453 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1454
1455 if (dev->features & NETIF_F_SG)
1456 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1457
1458 if (dev->features & NETIF_F_IP_CSUM)
1459 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1460 dev->name);
1461
1462#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1463 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1464#endif
1465
1466#ifdef MV643XX_COAL
1467 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1468 dev->name);
1469#endif
1470
1471#ifdef MV643XX_NAPI
1472 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1473#endif
1474
b1529871
ND		 1475 if (mp->tx_sram_size > 0)
1476 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1477
1da177e4
LT		 1478 return 0;
1479
1480out:
1481 free_netdev(dev);
1482
1483 return err;
1484}
1485
3ae5eaec 1486static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 1487{
3ae5eaec 1488 struct net_device *dev = platform_get_drvdata(pdev);
1da177e4
LT		 1489
1490 unregister_netdev(dev);
1491 flush_scheduled_work();
1492
1493 free_netdev(dev);
3ae5eaec 1494 platform_set_drvdata(pdev, NULL);
1da177e4
LT		 1495 return 0;
1496}
1497
3ae5eaec 1498static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1da177e4 1499{
1da177e4
LT		 1500 struct resource *res;
1501
1502 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1503
1504 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1505 if (res == NULL)
1506 return -ENODEV;
1507
1508 mv643xx_eth_shared_base = ioremap(res->start,
1509 MV643XX_ETH_SHARED_REGS_SIZE);
1510 if (mv643xx_eth_shared_base == NULL)
1511 return -ENOMEM;
1512
1513 return 0;
1514
1515}
1516
3ae5eaec 1517static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1da177e4
LT		 1518{
1519 iounmap(mv643xx_eth_shared_base);
1520 mv643xx_eth_shared_base = NULL;
1521
1522 return 0;
1523}
1524
3ae5eaec 1525static struct platform_driver mv643xx_eth_driver = {
1da177e4
LT		 1526 .probe = mv643xx_eth_probe,
1527 .remove = mv643xx_eth_remove,
3ae5eaec
RK		 1528 .driver = {
1529 .name = MV643XX_ETH_NAME,
1530 },
1da177e4
LT		 1531};
1532
3ae5eaec 1533static struct platform_driver mv643xx_eth_shared_driver = {
1da177e4
LT		 1534 .probe = mv643xx_eth_shared_probe,
1535 .remove = mv643xx_eth_shared_remove,
3ae5eaec
RK		 1536 .driver = {
1537 .name = MV643XX_ETH_SHARED_NAME,
1538 },
1da177e4
LT		 1539};
1540
1541/*
1542 * mv643xx_init_module
1543 *
1544 * Registers the network drivers into the Linux kernel
1545 *
1546 * Input : N/A
1547 *
1548 * Output : N/A
1549 */
1550static int __init mv643xx_init_module(void)
1551{
1552 int rc;
1553
3ae5eaec 1554 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1da177e4 1555 if (!rc) {
3ae5eaec 1556 rc = platform_driver_register(&mv643xx_eth_driver);
1da177e4 1557 if (rc)
3ae5eaec 1558 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1559 }
1560 return rc;
1561}
1562
1563/*
1564 * mv643xx_cleanup_module
1565 *
1566 * Registers the network drivers into the Linux kernel
1567 *
1568 * Input : N/A
1569 *
1570 * Output : N/A
1571 */
1572static void __exit mv643xx_cleanup_module(void)
1573{
3ae5eaec
RK		 1574 platform_driver_unregister(&mv643xx_eth_driver);
1575 platform_driver_unregister(&mv643xx_eth_shared_driver);
1da177e4
LT		 1576}
1577
1578module_init(mv643xx_init_module);
1579module_exit(mv643xx_cleanup_module);
1580
1581MODULE_LICENSE("GPL");
1582MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1583 " and Dale Farnsworth");
1584MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1585
1586/*
1587 * The second part is the low level driver of the gigE ethernet ports.
1588 */
1589
1590/*
1591 * Marvell's Gigabit Ethernet controller low level driver
1592 *
1593 * DESCRIPTION:
1594 * This file introduce low level API to Marvell's Gigabit Ethernet
1595 * controller. This Gigabit Ethernet Controller driver API controls
1596 * 1) Operations (i.e. port init, start, reset etc').
1597 * 2) Data flow (i.e. port send, receive etc').
1598 * Each Gigabit Ethernet port is controlled via
1599 * struct mv643xx_private.
1600 * This struct includes user configuration information as well as
1601 * driver internal data needed for its operations.
1602 *
1603 * Supported Features:
1604 * - This low level driver is OS independent. Allocating memory for
1605 * the descriptor rings and buffers are not within the scope of
1606 * this driver.
1607 * - The user is free from Rx/Tx queue managing.
1608 * - This low level driver introduce functionality API that enable
1609 * the to operate Marvell's Gigabit Ethernet Controller in a
1610 * convenient way.
1611 * - Simple Gigabit Ethernet port operation API.
1612 * - Simple Gigabit Ethernet port data flow API.
1613 * - Data flow and operation API support per queue functionality.
1614 * - Support cached descriptors for better performance.
1615 * - Enable access to all four DRAM banks and internal SRAM memory
1616 * spaces.
1617 * - PHY access and control API.
1618 * - Port control register configuration API.
1619 * - Full control over Unicast and Multicast MAC configurations.
1620 *
1621 * Operation flow:
1622 *
1623 * Initialization phase
1624 * This phase complete the initialization of the the
1625 * mv643xx_private struct.
1626 * User information regarding port configuration has to be set
1627 * prior to calling the port initialization routine.
1628 *
1629 * In this phase any port Tx/Rx activity is halted, MIB counters
1630 * are cleared, PHY address is set according to user parameter and
1631 * access to DRAM and internal SRAM memory spaces.
1632 *
1633 * Driver ring initialization
1634 * Allocating memory for the descriptor rings and buffers is not
1635 * within the scope of this driver. Thus, the user is required to
1636 * allocate memory for the descriptors ring and buffers. Those
1637 * memory parameters are used by the Rx and Tx ring initialization
1638 * routines in order to curve the descriptor linked list in a form
1639 * of a ring.
1640 * Note: Pay special attention to alignment issues when using
1641 * cached descriptors/buffers. In this phase the driver store
1642 * information in the mv643xx_private struct regarding each queue
1643 * ring.
1644 *
1645 * Driver start
1646 * This phase prepares the Ethernet port for Rx and Tx activity.
1647 * It uses the information stored in the mv643xx_private struct to
1648 * initialize the various port registers.
1649 *
1650 * Data flow:
1651 * All packet references to/from the driver are done using
1652 * struct pkt_info.
1653 * This struct is a unified struct used with Rx and Tx operations.
1654 * This way the user is not required to be familiar with neither
1655 * Tx nor Rx descriptors structures.
1656 * The driver's descriptors rings are management by indexes.
1657 * Those indexes controls the ring resources and used to indicate
1658 * a SW resource error:
1659 * 'current'
1660 * This index points to the current available resource for use. For
1661 * example in Rx process this index will point to the descriptor
1662 * that will be passed to the user upon calling the receive
1663 * routine. In Tx process, this index will point to the descriptor
1664 * that will be assigned with the user packet info and transmitted.
1665 * 'used'
1666 * This index points to the descriptor that need to restore its
1667 * resources. For example in Rx process, using the Rx buffer return
1668 * API will attach the buffer returned in packet info to the
1669 * descriptor pointed by 'used'. In Tx process, using the Tx
1670 * descriptor return will merely return the user packet info with
1671 * the command status of the transmitted buffer pointed by the
1672 * 'used' index. Nevertheless, it is essential to use this routine
1673 * to update the 'used' index.
1674 * 'first'
1675 * This index supports Tx Scatter-Gather. It points to the first
1676 * descriptor of a packet assembled of multiple buffers. For
1677 * example when in middle of Such packet we have a Tx resource
1678 * error the 'curr' index get the value of 'first' to indicate
1679 * that the ring returned to its state before trying to transmit
1680 * this packet.
1681 *
1682 * Receive operation:
1683 * The eth_port_receive API set the packet information struct,
1684 * passed by the caller, with received information from the
1685 * 'current' SDMA descriptor.
1686 * It is the user responsibility to return this resource back
1687 * to the Rx descriptor ring to enable the reuse of this source.
1688 * Return Rx resource is done using the eth_rx_return_buff API.
1689 *
1da177e4
LT		 1690 * Prior to calling the initialization routine eth_port_init() the user
1691 * must set the following fields under mv643xx_private struct:
1692 * port_num User Ethernet port number.
1da177e4
LT		 1693 * port_config User port configuration value.
1694 * port_config_extend User port config extend value.
1695 * port_sdma_config User port SDMA config value.
1696 * port_serial_control User port serial control value.
1697 *
1698 * This driver data flow is done using the struct pkt_info which
1699 * is a unified struct for Rx and Tx operations:
1700 *
1701 * byte_cnt Tx/Rx descriptor buffer byte count.
1702 * l4i_chk CPU provided TCP Checksum. For Tx operation
1703 * only.
1704 * cmd_sts Tx/Rx descriptor command status.
1705 * buf_ptr Tx/Rx descriptor buffer pointer.
1706 * return_info Tx/Rx user resource return information.
1707 */
1708
1da177e4
LT		 1709/* PHY routines */
1710static int ethernet_phy_get(unsigned int eth_port_num);
1711static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1712
1713/* Ethernet Port routines */
cf4086c7 1714static void eth_port_set_filter_table_entry(int table, unsigned char entry);
1da177e4
LT		 1715
1716/*
1717 * eth_port_init - Initialize the Ethernet port driver
1718 *
1719 * DESCRIPTION:
1720 * This function prepares the ethernet port to start its activity:
1721 * 1) Completes the ethernet port driver struct initialization toward port
1722 * start routine.
1723 * 2) Resets the device to a quiescent state in case of warm reboot.
1724 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1725 * 4) Clean MAC tables. The reset status of those tables is unknown.
1726 * 5) Set PHY address.
1727 * Note: Call this routine prior to eth_port_start routine and after
1728 * setting user values in the user fields of Ethernet port control
1729 * struct.
1730 *
1731 * INPUT:
1732 * struct mv643xx_private *mp Ethernet port control struct
1733 *
1734 * OUTPUT:
1735 * See description.
1736 *
1737 * RETURN:
1738 * None.
1739 */
1740static void eth_port_init(struct mv643xx_private *mp)
1741{
1da177e4 1742 mp->rx_resource_err = 0;
1da177e4
LT		 1743
1744 eth_port_reset(mp->port_num);
1745
1746 eth_port_init_mac_tables(mp->port_num);
1da177e4
LT		 1747}
1748
1749/*
1750 * eth_port_start - Start the Ethernet port activity.
1751 *
1752 * DESCRIPTION:
1753 * This routine prepares the Ethernet port for Rx and Tx activity:
1754 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1755 * has been initialized a descriptor's ring (using
1756 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1757 * 2. Initialize and enable the Ethernet configuration port by writing to
1758 * the port's configuration and command registers.
1759 * 3. Initialize and enable the SDMA by writing to the SDMA's
1760 * configuration and command registers. After completing these steps,
1761 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1762 *
1763 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1764 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1765 * and ether_init_rx_desc_ring for Rx queues).
1766 *
1767 * INPUT:
ed9b5d45 1768 * dev - a pointer to the required interface
1da177e4
LT		 1769 *
1770 * OUTPUT:
1771 * Ethernet port is ready to receive and transmit.
1772 *
1773 * RETURN:
1774 * None.
1775 */
ed9b5d45 1776static void eth_port_start(struct net_device *dev)
1da177e4 1777{
ed9b5d45 1778 struct mv643xx_private *mp = netdev_priv(dev);
1da177e4
LT		 1779 unsigned int port_num = mp->port_num;
1780 int tx_curr_desc, rx_curr_desc;
d0412d96
JC		 1781 u32 pscr;
1782 struct ethtool_cmd ethtool_cmd;
1da177e4
LT		 1783
1784 /* Assignment of Tx CTRP of given queue */
1785 tx_curr_desc = mp->tx_curr_desc_q;
1786 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1787 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1788
1789 /* Assignment of Rx CRDP of given queue */
1790 rx_curr_desc = mp->rx_curr_desc_q;
1791 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1792 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1793
1794 /* Add the assigned Ethernet address to the port's address table */
ed9b5d45 1795 eth_port_uc_addr_set(port_num, dev->dev_addr);
1da177e4
LT		 1796
1797 /* Assign port configuration and command. */
01999873
DF		 1798 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num),
1799 MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE);
1800
1801 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1802 MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE);
1da177e4 1803
d0412d96 1804 pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
01999873
DF		 1805
1806 pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS);
d0412d96 1807 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4 1808
d0412d96
JC		 1809 pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1810 MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII |
1811 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX |
1812 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
1813 MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED;
1da177e4 1814
d0412d96 1815 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4 1816
d0412d96
JC		 1817 pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE;
1818 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1da177e4
LT		 1819
1820 /* Assign port SDMA configuration */
01999873
DF		 1821 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1822 MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE);
1da177e4
LT		 1823
1824 /* Enable port Rx. */
ff561eef 1825 mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
8f543718
DF		 1826
1827 /* Disable port bandwidth limits by clearing MTU register */
1828 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
d0412d96
JC		 1829
1830 /* save phy settings across reset */
1831 mv643xx_get_settings(dev, &ethtool_cmd);
1832 ethernet_phy_reset(mp->port_num);
1833 mv643xx_set_settings(dev, &ethtool_cmd);
1da177e4
LT		 1834}
1835
1836/*
1837 * eth_port_uc_addr_set - This function Set the port Unicast address.
1838 *
1839 * DESCRIPTION:
1840 * This function Set the port Ethernet MAC address.
1841 *
1842 * INPUT:
1843 * unsigned int eth_port_num Port number.
1844 * char * p_addr Address to be set
1845 *
1846 * OUTPUT:
cf4086c7
DF		 1847 * Set MAC address low and high registers. also calls
1848 * eth_port_set_filter_table_entry() to set the unicast
1849 * table with the proper information.
1da177e4
LT		 1850 *
1851 * RETURN:
1852 * N/A.
1853 *
1854 */
1855static void eth_port_uc_addr_set(unsigned int eth_port_num,
1856 unsigned char *p_addr)
1857{
1858 unsigned int mac_h;
1859 unsigned int mac_l;
cf4086c7 1860 int table;
1da177e4
LT		 1861
1862 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1863 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1864 (p_addr[3] << 0);
1865
1866 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1867 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1868
1869 /* Accept frames of this address */
cf4086c7
DF		 1870 table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(eth_port_num);
1871 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
1da177e4
LT		 1872}
1873
1874/*
1875 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1876 * (MAC address) from the ethernet hw registers.
1877 *
1878 * DESCRIPTION:
1879 * This function retrieves the port Ethernet MAC address.
1880 *
1881 * INPUT:
1882 * unsigned int eth_port_num Port number.
1883 * char *MacAddr pointer where the MAC address is stored
1884 *
1885 * OUTPUT:
1886 * Copy the MAC address to the location pointed to by MacAddr
1887 *
1888 * RETURN:
1889 * N/A.
1890 *
1891 */
1892static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1893{
1894 struct mv643xx_private *mp = netdev_priv(dev);
1895 unsigned int mac_h;
1896 unsigned int mac_l;
1897
1898 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1899 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1900
1901 p_addr[0] = (mac_h >> 24) & 0xff;
1902 p_addr[1] = (mac_h >> 16) & 0xff;
1903 p_addr[2] = (mac_h >> 8) & 0xff;
1904 p_addr[3] = mac_h & 0xff;
1905 p_addr[4] = (mac_l >> 8) & 0xff;
1906 p_addr[5] = mac_l & 0xff;
1907}
1908
16e03018
DF		 1909/*
1910 * The entries in each table are indexed by a hash of a packet's MAC
1911 * address. One bit in each entry determines whether the packet is
1912 * accepted. There are 4 entries (each 8 bits wide) in each register
1913 * of the table. The bits in each entry are defined as follows:
1914 * 0 Accept=1, Drop=0
1915 * 3-1 Queue (ETH_Q0=0)
1916 * 7-4 Reserved = 0;
1917 */
1918static void eth_port_set_filter_table_entry(int table, unsigned char entry)
1919{
1920 unsigned int table_reg;
1921 unsigned int tbl_offset;
1922 unsigned int reg_offset;
1923
1924 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1925 reg_offset = entry % 4; /* Entry offset within the register */
1926
1927 /* Set "accepts frame bit" at specified table entry */
1928 table_reg = mv_read(table + tbl_offset);
1929 table_reg |= 0x01 << (8 * reg_offset);
1930 mv_write(table + tbl_offset, table_reg);
1931}
1932
1933/*
1934 * eth_port_mc_addr - Multicast address settings.
1935 *
1936 * The MV device supports multicast using two tables:
1937 * 1) Special Multicast Table for MAC addresses of the form
1938 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1939 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1940 * Table entries in the DA-Filter table.
1941 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1942 * is used as an index to the Other Multicast Table entries in the
1943 * DA-Filter table. This function calculates the CRC-8bit value.
1944 * In either case, eth_port_set_filter_table_entry() is then called
1945 * to set to set the actual table entry.
1946 */
1947static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
1948{
1949 unsigned int mac_h;
1950 unsigned int mac_l;
1951 unsigned char crc_result = 0;
1952 int table;
1953 int mac_array[48];
1954 int crc[8];
1955 int i;
1956
1957 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1958 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
1959 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
1960 (eth_port_num);
1961 eth_port_set_filter_table_entry(table, p_addr[5]);
1962 return;
1963 }
1964
1965 /* Calculate CRC-8 out of the given address */
1966 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1967 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1968 (p_addr[4] << 8) | (p_addr[5] << 0);
1969
1970 for (i = 0; i < 32; i++)
1971 mac_array[i] = (mac_l >> i) & 0x1;
1972 for (i = 32; i < 48; i++)
1973 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1974
1975 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1976 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1977 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1978 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1979 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1980
1981 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1982 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1983 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1984 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1985 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1986 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1987 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1988
1989 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1990 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1991 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1992 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1993 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1994 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
1995
1996 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1997 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1998 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1999 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2000 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2001 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2002
2003 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2004 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2005 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2006 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2007 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2008 mac_array[3] ^ mac_array[2];
2009
2010 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2011 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2012 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2013 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2014 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2015 mac_array[4] ^ mac_array[3];
2016
2017 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2018 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2019 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2020 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2021 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2022 mac_array[4];
2023
2024 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2025 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2026 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2027 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2028 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2029
2030 for (i = 0; i < 8; i++)
2031 crc_result = crc_result | (crc[i] << i);
2032
2033 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2034 eth_port_set_filter_table_entry(table, crc_result);
2035}
2036
2037/*
2038 * Set the entire multicast list based on dev->mc_list.
2039 */
2040static void eth_port_set_multicast_list(struct net_device *dev)
2041{
2042
2043 struct dev_mc_list *mc_list;
2044 int i;
2045 int table_index;
2046 struct mv643xx_private *mp = netdev_priv(dev);
2047 unsigned int eth_port_num = mp->port_num;
2048
2049 /* If the device is in promiscuous mode or in all multicast mode,
2050 * we will fully populate both multicast tables with accept.
2051 * This is guaranteed to yield a match on all multicast addresses...
2052 */
2053 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2054 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
b4de9051
DF		 2055 /* Set all entries in DA filter special multicast
2056 * table (Ex_dFSMT)
2057 * Set for ETH_Q0 for now
2058 * Bits
2059 * 0 Accept=1, Drop=0
2060 * 3-1 Queue ETH_Q0=0
2061 * 7-4 Reserved = 0;
2062 */
2063 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2064
2065 /* Set all entries in DA filter other multicast
2066 * table (Ex_dFOMT)
2067 * Set for ETH_Q0 for now
2068 * Bits
2069 * 0 Accept=1, Drop=0
2070 * 3-1 Queue ETH_Q0=0
2071 * 7-4 Reserved = 0;
2072 */
2073 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2074 }
16e03018
DF		 2075 return;
2076 }
2077
2078 /* We will clear out multicast tables every time we get the list.
2079 * Then add the entire new list...
2080 */
2081 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2082 /* Clear DA filter special multicast table (Ex_dFSMT) */
2083 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2084 (eth_port_num) + table_index, 0);
2085
2086 /* Clear DA filter other multicast table (Ex_dFOMT) */
2087 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2088 (eth_port_num) + table_index, 0);
2089 }
2090
2091 /* Get pointer to net_device multicast list and add each one... */
2092 for (i = 0, mc_list = dev->mc_list;
2093 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2094 i++, mc_list = mc_list->next)
2095 if (mc_list->dmi_addrlen == 6)
2096 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2097}
2098
1da177e4
LT		 2099/*
2100 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2101 *
2102 * DESCRIPTION:
2103 * Go through all the DA filter tables (Unicast, Special Multicast &
2104 * Other Multicast) and set each entry to 0.
2105 *
2106 * INPUT:
2107 * unsigned int eth_port_num Ethernet Port number.
2108 *
2109 * OUTPUT:
2110 * Multicast and Unicast packets are rejected.
2111 *
2112 * RETURN:
2113 * None.
2114 */
2115static void eth_port_init_mac_tables(unsigned int eth_port_num)
2116{
2117 int table_index;
2118
2119 /* Clear DA filter unicast table (Ex_dFUT) */
2120 for (table_index = 0; table_index <= 0xC; table_index += 4)
cf4086c7
DF		 2121 mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2122 (eth_port_num) + table_index, 0);
1da177e4
LT		 2123
2124 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2125 /* Clear DA filter special multicast table (Ex_dFSMT) */
16e03018
DF		 2126 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2127 (eth_port_num) + table_index, 0);
1da177e4 2128 /* Clear DA filter other multicast table (Ex_dFOMT) */
16e03018
DF		 2129 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2130 (eth_port_num) + table_index, 0);
1da177e4
LT		 2131 }
2132}
2133
2134/*
2135 * eth_clear_mib_counters - Clear all MIB counters
2136 *
2137 * DESCRIPTION:
2138 * This function clears all MIB counters of a specific ethernet port.
2139 * A read from the MIB counter will reset the counter.
2140 *
2141 * INPUT:
2142 * unsigned int eth_port_num Ethernet Port number.
2143 *
2144 * OUTPUT:
2145 * After reading all MIB counters, the counters resets.
2146 *
2147 * RETURN:
2148 * MIB counter value.
2149 *
2150 */
2151static void eth_clear_mib_counters(unsigned int eth_port_num)
2152{
2153 int i;
2154
2155 /* Perform dummy reads from MIB counters */
2156 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2157 i += 4)
2158 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2159}
2160
2161static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2162{
2163 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2164}
2165
2166static void eth_update_mib_counters(struct mv643xx_private *mp)
2167{
2168 struct mv643xx_mib_counters *p = &mp->mib_counters;
2169 int offset;
2170
2171 p->good_octets_received +=
2172 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2173 p->good_octets_received +=
2174 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2175
2176 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2177 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2178 offset += 4)
2179 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2180
2181 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2182 p->good_octets_sent +=
2183 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2184
2185 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2186 offset <= ETH_MIB_LATE_COLLISION;
2187 offset += 4)
2188 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2189}
2190
2191/*
2192 * ethernet_phy_detect - Detect whether a phy is present
2193 *
2194 * DESCRIPTION:
2195 * This function tests whether there is a PHY present on
2196 * the specified port.
2197 *
2198 * INPUT:
2199 * unsigned int eth_port_num Ethernet Port number.
2200 *
2201 * OUTPUT:
2202 * None
2203 *
2204 * RETURN:
2205 * 0 on success
2206 * -ENODEV on failure
2207 *
2208 */
2209static int ethernet_phy_detect(unsigned int port_num)
2210{
2211 unsigned int phy_reg_data0;
2212 int auto_neg;
2213
2214 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2215 auto_neg = phy_reg_data0 & 0x1000;
2216 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2217 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2218
2219 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2220 if ((phy_reg_data0 & 0x1000) == auto_neg)
2221 return -ENODEV; /* change didn't take */
2222
2223 phy_reg_data0 ^= 0x1000;
2224 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2225 return 0;
2226}
2227
2228/*
2229 * ethernet_phy_get - Get the ethernet port PHY address.
2230 *
2231 * DESCRIPTION:
2232 * This routine returns the given ethernet port PHY address.
2233 *
2234 * INPUT:
2235 * unsigned int eth_port_num Ethernet Port number.
2236 *
2237 * OUTPUT:
2238 * None.
2239 *
2240 * RETURN:
2241 * PHY address.
2242 *
2243 */
2244static int ethernet_phy_get(unsigned int eth_port_num)
2245{
2246 unsigned int reg_data;
2247
2248 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2249
2250 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2251}
2252
2253/*
2254 * ethernet_phy_set - Set the ethernet port PHY address.
2255 *
2256 * DESCRIPTION:
2257 * This routine sets the given ethernet port PHY address.
2258 *
2259 * INPUT:
2260 * unsigned int eth_port_num Ethernet Port number.
2261 * int phy_addr PHY address.
2262 *
2263 * OUTPUT:
2264 * None.
2265 *
2266 * RETURN:
2267 * None.
2268 *
2269 */
2270static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2271{
2272 u32 reg_data;
2273 int addr_shift = 5 * eth_port_num;
2274
2275 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2276 reg_data &= ~(0x1f << addr_shift);
2277 reg_data |= (phy_addr & 0x1f) << addr_shift;
2278 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2279}
2280
2281/*
2282 * ethernet_phy_reset - Reset Ethernet port PHY.
2283 *
2284 * DESCRIPTION:
2285 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2286 *
2287 * INPUT:
2288 * unsigned int eth_port_num Ethernet Port number.
2289 *
2290 * OUTPUT:
2291 * The PHY is reset.
2292 *
2293 * RETURN:
2294 * None.
2295 *
2296 */
2297static void ethernet_phy_reset(unsigned int eth_port_num)
2298{
2299 unsigned int phy_reg_data;
2300
2301 /* Reset the PHY */
2302 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2303 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2304 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
d0412d96
JC		 2305
2306 /* wait for PHY to come out of reset */
2307 do {
2308 udelay(1);
2309 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2310 } while (phy_reg_data & 0x8000);
1da177e4
LT		 2311}
2312
9f8dd319 2313static void mv643xx_eth_port_enable_tx(unsigned int port_num,
12a87c64 2314 unsigned int queues)
9f8dd319 2315{
12a87c64 2316 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
9f8dd319
DF		 2317}
2318
2319static void mv643xx_eth_port_enable_rx(unsigned int port_num,
12a87c64 2320 unsigned int queues)
9f8dd319 2321{
12a87c64 2322 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
9f8dd319
DF		 2323}
2324
2325static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2326{
12a87c64 2327 u32 queues;
9f8dd319
DF		 2328
2329 /* Stop Tx port activity. Check port Tx activity. */
12a87c64 2330 queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
9f8dd319 2331 & 0xFF;
12a87c64
DF		 2332 if (queues) {
2333 /* Issue stop command for active queues only */
9f8dd319 2334 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
12a87c64 2335 (queues << 8));
9f8dd319
DF		 2336
2337 /* Wait for all Tx activity to terminate. */
2338 /* Check port cause register that all Tx queues are stopped */
2339 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2340 & 0xFF)
2341 udelay(PHY_WAIT_MICRO_SECONDS);
2342
2343 /* Wait for Tx FIFO to empty */
2344 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) &
2345 ETH_PORT_TX_FIFO_EMPTY)
2346 udelay(PHY_WAIT_MICRO_SECONDS);
2347 }
2348
12a87c64 2349 return queues;
9f8dd319
DF		 2350}
2351
2352static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2353{
12a87c64 2354 u32 queues;
9f8dd319
DF		 2355
2356 /* Stop Rx port activity. Check port Rx activity. */
12a87c64 2357 queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
e38fd1a0 2358 & 0xFF;
12a87c64
DF		 2359 if (queues) {
2360 /* Issue stop command for active queues only */
9f8dd319 2361 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
12a87c64 2362 (queues << 8));
9f8dd319
DF		 2363
2364 /* Wait for all Rx activity to terminate. */
2365 /* Check port cause register that all Rx queues are stopped */
2366 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2367 & 0xFF)
2368 udelay(PHY_WAIT_MICRO_SECONDS);
2369 }
2370
12a87c64 2371 return queues;
9f8dd319
DF		 2372}
2373
1da177e4
LT		 2374/*
2375 * eth_port_reset - Reset Ethernet port
2376 *
2377 * DESCRIPTION:
2378 * This routine resets the chip by aborting any SDMA engine activity and
2379 * clearing the MIB counters. The Receiver and the Transmit unit are in
2380 * idle state after this command is performed and the port is disabled.
2381 *
2382 * INPUT:
2383 * unsigned int eth_port_num Ethernet Port number.
2384 *
2385 * OUTPUT:
2386 * Channel activity is halted.
2387 *
2388 * RETURN:
2389 * None.
2390 *
2391 */
2392static void eth_port_reset(unsigned int port_num)
2393{
2394 unsigned int reg_data;
2395
9f8dd319
DF		 2396 mv643xx_eth_port_disable_tx(port_num);
2397 mv643xx_eth_port_disable_rx(port_num);
1da177e4
LT		 2398
2399 /* Clear all MIB counters */
2400 eth_clear_mib_counters(port_num);
2401
2402 /* Reset the Enable bit in the Configuration Register */
2403 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
d0412d96
JC		 2404 reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE |
2405 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
2406 MV643XX_ETH_FORCE_LINK_PASS);
1da177e4
LT		 2407 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2408}
2409
1da177e4 2410
1da177e4
LT		 2411/*
2412 * eth_port_read_smi_reg - Read PHY registers
2413 *
2414 * DESCRIPTION:
2415 * This routine utilize the SMI interface to interact with the PHY in
2416 * order to perform PHY register read.
2417 *
2418 * INPUT:
2419 * unsigned int port_num Ethernet Port number.
2420 * unsigned int phy_reg PHY register address offset.
2421 * unsigned int *value Register value buffer.
2422 *
2423 * OUTPUT:
2424 * Write the value of a specified PHY register into given buffer.
2425 *
2426 * RETURN:
2427 * false if the PHY is busy or read data is not in valid state.
2428 * true otherwise.
2429 *
2430 */
2431static void eth_port_read_smi_reg(unsigned int port_num,
2432 unsigned int phy_reg, unsigned int *value)
2433{
2434 int phy_addr = ethernet_phy_get(port_num);
2435 unsigned long flags;
2436 int i;
2437
2438 /* the SMI register is a shared resource */
2439 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2440
2441 /* wait for the SMI register to become available */
2442 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2443 if (i == PHY_WAIT_ITERATIONS) {
2444 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2445 goto out;
2446 }
2447 udelay(PHY_WAIT_MICRO_SECONDS);
2448 }
2449
2450 mv_write(MV643XX_ETH_SMI_REG,
2451 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2452
2453 /* now wait for the data to be valid */
2454 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2455 if (i == PHY_WAIT_ITERATIONS) {
2456 printk("mv643xx PHY read timeout, port %d\n", port_num);
2457 goto out;
2458 }
2459 udelay(PHY_WAIT_MICRO_SECONDS);
2460 }
2461
2462 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2463out:
2464 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2465}
2466
2467/*
2468 * eth_port_write_smi_reg - Write to PHY registers
2469 *
2470 * DESCRIPTION:
2471 * This routine utilize the SMI interface to interact with the PHY in
2472 * order to perform writes to PHY registers.
2473 *
2474 * INPUT:
2475 * unsigned int eth_port_num Ethernet Port number.
2476 * unsigned int phy_reg PHY register address offset.
2477 * unsigned int value Register value.
2478 *
2479 * OUTPUT:
2480 * Write the given value to the specified PHY register.
2481 *
2482 * RETURN:
2483 * false if the PHY is busy.
2484 * true otherwise.
2485 *
2486 */
2487static void eth_port_write_smi_reg(unsigned int eth_port_num,
2488 unsigned int phy_reg, unsigned int value)
2489{
2490 int phy_addr;
2491 int i;
2492 unsigned long flags;
2493
2494 phy_addr = ethernet_phy_get(eth_port_num);
2495
2496 /* the SMI register is a shared resource */
2497 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2498
2499 /* wait for the SMI register to become available */
2500 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2501 if (i == PHY_WAIT_ITERATIONS) {
2502 printk("mv643xx PHY busy timeout, port %d\n",
2503 eth_port_num);
2504 goto out;
2505 }
2506 udelay(PHY_WAIT_MICRO_SECONDS);
2507 }
2508
2509 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2510 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2511out:
2512 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2513}
2514
c28a4f89
JC		 2515/*
2516 * Wrappers for MII support library.
2517 */
2518static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2519{
2520 int val;
2521 struct mv643xx_private *mp = netdev_priv(dev);
2522
2523 eth_port_read_smi_reg(mp->port_num, location, &val);
2524 return val;
2525}
2526
2527static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2528{
2529 struct mv643xx_private *mp = netdev_priv(dev);
2530 eth_port_write_smi_reg(mp->port_num, location, val);
2531}
2532
1da177e4
LT		 2533/*
2534 * eth_port_receive - Get received information from Rx ring.
2535 *
2536 * DESCRIPTION:
2537 * This routine returns the received data to the caller. There is no
2538 * data copying during routine operation. All information is returned
2539 * using pointer to packet information struct passed from the caller.
2540 * If the routine exhausts Rx ring resources then the resource error flag
2541 * is set.
2542 *
2543 * INPUT:
2544 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2545 * struct pkt_info *p_pkt_info User packet buffer.
2546 *
2547 * OUTPUT:
2548 * Rx ring current and used indexes are updated.
2549 *
2550 * RETURN:
2551 * ETH_ERROR in case the routine can not access Rx desc ring.
2552 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2553 * ETH_END_OF_JOB if there is no received data.
2554 * ETH_OK otherwise.
2555 */
2556static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2557 struct pkt_info *p_pkt_info)
2558{
2559 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2560 volatile struct eth_rx_desc *p_rx_desc;
2561 unsigned int command_status;
8f518703 2562 unsigned long flags;
1da177e4
LT		 2563
2564 /* Do not process Rx ring in case of Rx ring resource error */
2565 if (mp->rx_resource_err)
2566 return ETH_QUEUE_FULL;
2567
8f518703
DF		 2568 spin_lock_irqsave(&mp->lock, flags);
2569
1da177e4
LT		 2570 /* Get the Rx Desc ring 'curr and 'used' indexes */
2571 rx_curr_desc = mp->rx_curr_desc_q;
2572 rx_used_desc = mp->rx_used_desc_q;
2573
2574 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2575
2576 /* The following parameters are used to save readings from memory */
2577 command_status = p_rx_desc->cmd_sts;
2578 rmb();
2579
2580 /* Nothing to receive... */
8f518703
DF		 2581 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2582 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 2583 return ETH_END_OF_JOB;
8f518703 2584 }
1da177e4
LT		 2585
2586 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2587 p_pkt_info->cmd_sts = command_status;
2588 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2589 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2590 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2591
b4de9051
DF		 2592 /*
2593 * Clean the return info field to indicate that the
2594 * packet has been moved to the upper layers
2595 */
1da177e4
LT		 2596 mp->rx_skb[rx_curr_desc] = NULL;
2597
2598 /* Update current index in data structure */
2599 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2600 mp->rx_curr_desc_q = rx_next_curr_desc;
2601
2602 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2603 if (rx_next_curr_desc == rx_used_desc)
2604 mp->rx_resource_err = 1;
2605
8f518703
DF		 2606 spin_unlock_irqrestore(&mp->lock, flags);
2607
1da177e4
LT		 2608 return ETH_OK;
2609}
2610
2611/*
2612 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2613 *
2614 * DESCRIPTION:
2615 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2616 * next 'used' descriptor and attached the returned buffer to it.
2617 * In case the Rx ring was in "resource error" condition, where there are
2618 * no available Rx resources, the function resets the resource error flag.
2619 *
2620 * INPUT:
2621 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2622 * struct pkt_info *p_pkt_info Information on returned buffer.
2623 *
2624 * OUTPUT:
2625 * New available Rx resource in Rx descriptor ring.
2626 *
2627 * RETURN:
2628 * ETH_ERROR in case the routine can not access Rx desc ring.
2629 * ETH_OK otherwise.
2630 */
2631static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2632 struct pkt_info *p_pkt_info)
2633{
2634 int used_rx_desc; /* Where to return Rx resource */
2635 volatile struct eth_rx_desc *p_used_rx_desc;
8f518703
DF		 2636 unsigned long flags;
2637
2638 spin_lock_irqsave(&mp->lock, flags);
1da177e4
LT		 2639
2640 /* Get 'used' Rx descriptor */
2641 used_rx_desc = mp->rx_used_desc_q;
2642 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2643
2644 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2645 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2646 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2647
2648 /* Flush the write pipe */
2649
2650 /* Return the descriptor to DMA ownership */
2651 wmb();
2652 p_used_rx_desc->cmd_sts =
2653 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2654 wmb();
2655
2656 /* Move the used descriptor pointer to the next descriptor */
2657 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2658
2659 /* Any Rx return cancels the Rx resource error status */
2660 mp->rx_resource_err = 0;
2661
8f518703
DF		 2662 spin_unlock_irqrestore(&mp->lock, flags);
2663
1da177e4
LT		 2664 return ETH_OK;
2665}
2666
2667/************* Begin ethtool support *************************/
2668
2669struct mv643xx_stats {
2670 char stat_string[ETH_GSTRING_LEN];
2671 int sizeof_stat;
2672 int stat_offset;
2673};
2674
2675#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
b4de9051 2676 offsetof(struct mv643xx_private, m)
1da177e4
LT		 2677
2678static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2679 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2680 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2681 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2682 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2683 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2684 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2685 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2686 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2687 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2688 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2689 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2690 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2691 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2692 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2693 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2694 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2695 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2696 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2697 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2698 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2699 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2700 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2701 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2702 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2703 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2704 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2705 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2706 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2707 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2708 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2709 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2710 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2711 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2712 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2713 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2714 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2715 { "collision", MV643XX_STAT(mib_counters.collision) },
2716 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2717};
2718
2719#define MV643XX_STATS_LEN \
2720 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2721
b4de9051
DF		 2722static void mv643xx_get_drvinfo(struct net_device *netdev,
2723 struct ethtool_drvinfo *drvinfo)
1da177e4
LT		 2724{
2725 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2726 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2727 strncpy(drvinfo->fw_version, "N/A", 32);
2728 strncpy(drvinfo->bus_info, "mv643xx", 32);
2729 drvinfo->n_stats = MV643XX_STATS_LEN;
2730}
2731
b4de9051 2732static int mv643xx_get_stats_count(struct net_device *netdev)
1da177e4
LT		 2733{
2734 return MV643XX_STATS_LEN;
2735}
2736
b4de9051
DF		 2737static void mv643xx_get_ethtool_stats(struct net_device *netdev,
2738 struct ethtool_stats *stats, uint64_t *data)
1da177e4
LT		 2739{
2740 struct mv643xx_private *mp = netdev->priv;
2741 int i;
2742
2743 eth_update_mib_counters(mp);
2744
b4de9051 2745 for (i = 0; i < MV643XX_STATS_LEN; i++) {
1da177e4 2746 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
b4de9051 2747 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
1da177e4
LT		 2748 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
2749 }
2750}
2751
b4de9051
DF		 2752static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
2753 uint8_t *data)
1da177e4
LT		 2754{
2755 int i;
2756
2757 switch(stringset) {
2758 case ETH_SS_STATS:
2759 for (i=0; i < MV643XX_STATS_LEN; i++) {
b4de9051
DF		 2760 memcpy(data + i * ETH_GSTRING_LEN,
2761 mv643xx_gstrings_stats[i].stat_string,
2762 ETH_GSTRING_LEN);
1da177e4
LT		 2763 }
2764 break;
2765 }
2766}
2767
d0412d96
JC		 2768static u32 mv643xx_eth_get_link(struct net_device *dev)
2769{
2770 struct mv643xx_private *mp = netdev_priv(dev);
2771
2772 return mii_link_ok(&mp->mii);
2773}
2774
2775static int mv643xx_eth_nway_restart(struct net_device *dev)
2776{
2777 struct mv643xx_private *mp = netdev_priv(dev);
2778
2779 return mii_nway_restart(&mp->mii);
2780}
2781
2782static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2783{
2784 struct mv643xx_private *mp = netdev_priv(dev);
2785
2786 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2787}
2788
1da177e4
LT		 2789static struct ethtool_ops mv643xx_ethtool_ops = {
2790 .get_settings = mv643xx_get_settings,
d0412d96 2791 .set_settings = mv643xx_set_settings,
1da177e4 2792 .get_drvinfo = mv643xx_get_drvinfo,
d0412d96 2793 .get_link = mv643xx_eth_get_link,
1da177e4
LT		 2794 .get_sg = ethtool_op_get_sg,
2795 .set_sg = ethtool_op_set_sg,
2796 .get_strings = mv643xx_get_strings,
2797 .get_stats_count = mv643xx_get_stats_count,
2798 .get_ethtool_stats = mv643xx_get_ethtool_stats,
d0412d96
JC		 2799 .get_strings = mv643xx_get_strings,
2800 .get_stats_count = mv643xx_get_stats_count,
2801 .get_ethtool_stats = mv643xx_get_ethtool_stats,
2802 .nway_reset = mv643xx_eth_nway_restart,
1da177e4
LT		 2803};
2804
2805/************* End ethtool support *************************/
Linux kernel - Deliverables
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