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mv643xx_eth: use auto phy polling for configuring (R)(G)MII interface
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
45675bc6 58static char mv643xx_eth_driver_version[] = "1.1";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 63
e5371493 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66#else
67#define MAX_DESCS_PER_SKB 1
68#endif
69
fbd6a754
LB		 70/*
71 * Registers shared between all ports.
72 */
3cb4667c
LB		 73#define PHY_ADDR 0x0000
74#define SMI_REG 0x0004
75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
82 * Per-port registers.
83 */
3cb4667c 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
ae9ae064 93#define TX_IN_PROGRESS 0x00000080
81600eea 94#define LINK_UP 0x00000002
3cb4667c 95#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
89df5fdc
LB		 96#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
97#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
3cb4667c 98#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
89df5fdc 99#define TX_BW_BURST(p) (0x045c + ((p) << 10))
3cb4667c 100#define INT_CAUSE(p) (0x0460 + ((p) << 10))
8fa89bf5 101#define INT_TX_END_0 0x00080000
226bb6b7 102#define INT_TX_END 0x07f80000
64da80a2 103#define INT_RX 0x0007fbfc
073a345c 104#define INT_EXT 0x00000002
3cb4667c 105#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 106#define INT_EXT_LINK 0x00100000
107#define INT_EXT_PHY 0x00010000
108#define INT_EXT_TX_ERROR_0 0x00000100
109#define INT_EXT_TX_0 0x00000001
3d6b35bc 110#define INT_EXT_TX 0x0000ffff
3cb4667c
LB		 111#define INT_MASK(p) (0x0468 + ((p) << 10))
112#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
113#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
1e881592
LB		 114#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
115#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
116#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
117#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
64da80a2 118#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
3cb4667c 119#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
3d6b35bc
LB		 120#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
121#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
122#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
123#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
3cb4667c
LB		 124#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 128
2679a550
LB		 129
130/*
131 * SDMA configuration register.
132 */
cd4ccf76 133#define RX_BURST_SIZE_16_64BIT (4 << 1)
fbd6a754 134#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 135#define BLM_TX_NO_SWAP (1 << 5)
cd4ccf76 136#define TX_BURST_SIZE_16_64BIT (4 << 22)
fbd6a754
LB		 137
138#if defined(__BIG_ENDIAN)
139#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76
LB		 140 RX_BURST_SIZE_16_64BIT | \
141 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 142#elif defined(__LITTLE_ENDIAN)
143#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
cd4ccf76 144 RX_BURST_SIZE_16_64BIT | \
fbd6a754
LB		 145 BLM_RX_NO_SWAP | \
146 BLM_TX_NO_SWAP | \
cd4ccf76 147 TX_BURST_SIZE_16_64BIT
fbd6a754
LB		 148#else
149#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
150#endif
151
2beff77b
LB		 152
153/*
154 * Port serial control register.
155 */
156#define SET_MII_SPEED_TO_100 (1 << 24)
157#define SET_GMII_SPEED_TO_1000 (1 << 23)
158#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 159#define MAX_RX_PACKET_9700BYTE (5 << 17)
2beff77b
LB		 160#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165#define FORCE_LINK_PASS (1 << 1)
166#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 167
cc9754b3
LB		 168#define DEFAULT_RX_QUEUE_SIZE 400
169#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 170
fbd6a754 171
7ca72a3b
LB		 172/*
173 * RX/TX descriptors.
fbd6a754
LB		 174 */
175#if defined(__BIG_ENDIAN)
cc9754b3 176struct rx_desc {
fbd6a754
LB		 177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
182};
183
cc9754b3 184struct tx_desc {
fbd6a754
LB		 185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
190};
191#elif defined(__LITTLE_ENDIAN)
cc9754b3 192struct rx_desc {
fbd6a754
LB		 193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
198};
199
cc9754b3 200struct tx_desc {
fbd6a754
LB		 201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
206};
207#else
208#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
209#endif
210
7ca72a3b 211/* RX & TX descriptor command */
cc9754b3 212#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 213
214/* RX & TX descriptor status */
cc9754b3 215#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 216
217/* RX descriptor status */
cc9754b3
LB		 218#define LAYER_4_CHECKSUM_OK 0x40000000
219#define RX_ENABLE_INTERRUPT 0x20000000
220#define RX_FIRST_DESC 0x08000000
221#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 222
223/* TX descriptor command */
cc9754b3
LB		 224#define TX_ENABLE_INTERRUPT 0x00800000
225#define GEN_CRC 0x00400000
226#define TX_FIRST_DESC 0x00200000
227#define TX_LAST_DESC 0x00100000
228#define ZERO_PADDING 0x00080000
229#define GEN_IP_V4_CHECKSUM 0x00040000
230#define GEN_TCP_UDP_CHECKSUM 0x00020000
231#define UDP_FRAME 0x00010000
7ca72a3b 232
cc9754b3 233#define TX_IHL_SHIFT 11
7ca72a3b
LB		 234
235
c9df406f 236/* global *******************************************************************/
e5371493 237struct mv643xx_eth_shared_private {
fc32b0e2
LB		 238 /*
239 * Ethernet controller base address.
240 */
cc9754b3 241 void __iomem *base;
c9df406f 242
fc32b0e2
LB		 243 /*
244 * Protects access to SMI_REG, which is shared between ports.
245 */
c9df406f
LB		 246 spinlock_t phy_lock;
247
fc32b0e2
LB		 248 /*
249 * Per-port MBUS window access register value.
250 */
c9df406f
LB		 251 u32 win_protect;
252
fc32b0e2
LB		 253 /*
254 * Hardware-specific parameters.
255 */
c9df406f 256 unsigned int t_clk;
773fc3ee 257 int extended_rx_coal_limit;
1e881592 258 int tx_bw_control_moved;
c9df406f
LB		 259};
260
261
262/* per-port *****************************************************************/
e5371493 263struct mib_counters {
fbd6a754
LB		 264 u64 good_octets_received;
265 u32 bad_octets_received;
266 u32 internal_mac_transmit_err;
267 u32 good_frames_received;
268 u32 bad_frames_received;
269 u32 broadcast_frames_received;
270 u32 multicast_frames_received;
271 u32 frames_64_octets;
272 u32 frames_65_to_127_octets;
273 u32 frames_128_to_255_octets;
274 u32 frames_256_to_511_octets;
275 u32 frames_512_to_1023_octets;
276 u32 frames_1024_to_max_octets;
277 u64 good_octets_sent;
278 u32 good_frames_sent;
279 u32 excessive_collision;
280 u32 multicast_frames_sent;
281 u32 broadcast_frames_sent;
282 u32 unrec_mac_control_received;
283 u32 fc_sent;
284 u32 good_fc_received;
285 u32 bad_fc_received;
286 u32 undersize_received;
287 u32 fragments_received;
288 u32 oversize_received;
289 u32 jabber_received;
290 u32 mac_receive_error;
291 u32 bad_crc_event;
292 u32 collision;
293 u32 late_collision;
294};
295
8a578111 296struct rx_queue {
64da80a2
LB		 297 int index;
298
8a578111
LB		 299 int rx_ring_size;
300
301 int rx_desc_count;
302 int rx_curr_desc;
303 int rx_used_desc;
304
305 struct rx_desc *rx_desc_area;
306 dma_addr_t rx_desc_dma;
307 int rx_desc_area_size;
308 struct sk_buff **rx_skb;
309
310 struct timer_list rx_oom;
311};
312
13d64285 313struct tx_queue {
3d6b35bc
LB		 314 int index;
315
13d64285 316 int tx_ring_size;
fbd6a754 317
13d64285
LB		 318 int tx_desc_count;
319 int tx_curr_desc;
320 int tx_used_desc;
fbd6a754 321
5daffe94 322 struct tx_desc *tx_desc_area;
fbd6a754
LB		 323 dma_addr_t tx_desc_dma;
324 int tx_desc_area_size;
325 struct sk_buff **tx_skb;
13d64285
LB		 326};
327
328struct mv643xx_eth_private {
329 struct mv643xx_eth_shared_private *shared;
fc32b0e2 330 int port_num;
13d64285 331
fc32b0e2 332 struct net_device *dev;
fbd6a754 333
fc32b0e2
LB		 334 struct mv643xx_eth_shared_private *shared_smi;
335 int phy_addr;
fbd6a754 336
fbd6a754 337 spinlock_t lock;
fbd6a754 338
fc32b0e2
LB		 339 struct mib_counters mib_counters;
340 struct work_struct tx_timeout_task;
fbd6a754 341 struct mii_if_info mii;
8a578111
LB		 342
343 /*
344 * RX state.
345 */
346 int default_rx_ring_size;
347 unsigned long rx_desc_sram_addr;
348 int rx_desc_sram_size;
64da80a2
LB		 349 u8 rxq_mask;
350 int rxq_primary;
8a578111 351 struct napi_struct napi;
64da80a2 352 struct rx_queue rxq[8];
13d64285
LB		 353
354 /*
355 * TX state.
356 */
357 int default_tx_ring_size;
358 unsigned long tx_desc_sram_addr;
359 int tx_desc_sram_size;
3d6b35bc
LB		 360 u8 txq_mask;
361 int txq_primary;
362 struct tx_queue txq[8];
13d64285
LB		 363#ifdef MV643XX_ETH_TX_FAST_REFILL
364 int tx_clean_threshold;
365#endif
fbd6a754 366};
1da177e4 367
fbd6a754 368
c9df406f 369/* port register accessors **************************************************/
e5371493 370static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 371{
cc9754b3 372 return readl(mp->shared->base + offset);
c9df406f 373}
fbd6a754 374
e5371493 375static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 376{
cc9754b3 377 writel(data, mp->shared->base + offset);
c9df406f 378}
fbd6a754 379
fbd6a754 380
c9df406f 381/* rxq/txq helper functions *************************************************/
8a578111 382static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 383{
64da80a2 384 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 385}
fbd6a754 386
13d64285
LB		 387static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
388{
3d6b35bc 389 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 390}
391
8a578111 392static void rxq_enable(struct rx_queue *rxq)
c9df406f 393{
8a578111 394 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 395 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
8a578111 396}
1da177e4 397
8a578111
LB		 398static void rxq_disable(struct rx_queue *rxq)
399{
400 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 401 u8 mask = 1 << rxq->index;
1da177e4 402
8a578111
LB		 403 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
404 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
405 udelay(10);
c9df406f
LB		 406}
407
6b368f68
LB		 408static void txq_reset_hw_ptr(struct tx_queue *txq)
409{
410 struct mv643xx_eth_private *mp = txq_to_mp(txq);
411 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
412 u32 addr;
413
414 addr = (u32)txq->tx_desc_dma;
415 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
416 wrl(mp, off, addr);
417}
418
13d64285 419static void txq_enable(struct tx_queue *txq)
1da177e4 420{
13d64285 421 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 422 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
1da177e4
LT		 423}
424
13d64285 425static void txq_disable(struct tx_queue *txq)
1da177e4 426{
13d64285 427 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 428 u8 mask = 1 << txq->index;
c9df406f 429
13d64285
LB		 430 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
431 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
432 udelay(10);
433}
434
435static void __txq_maybe_wake(struct tx_queue *txq)
436{
437 struct mv643xx_eth_private *mp = txq_to_mp(txq);
438
3d6b35bc
LB		 439 /*
440 * netif_{stop,wake}_queue() flow control only applies to
441 * the primary queue.
442 */
443 BUG_ON(txq->index != mp->txq_primary);
444
13d64285
LB		 445 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
446 netif_wake_queue(mp->dev);
1da177e4
LT		 447}
448
c9df406f
LB		 449
450/* rx ***********************************************************************/
13d64285 451static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 452
8a578111 453static void rxq_refill(struct rx_queue *rxq)
1da177e4 454{
8a578111 455 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
c9df406f 456 unsigned long flags;
1da177e4 457
c9df406f 458 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 459
8a578111
LB		 460 while (rxq->rx_desc_count < rxq->rx_ring_size) {
461 int skb_size;
de34f225
LB		 462 struct sk_buff *skb;
463 int unaligned;
464 int rx;
465
8a578111
LB		 466 /*
467 * Reserve 2+14 bytes for an ethernet header (the
468 * hardware automatically prepends 2 bytes of dummy
469 * data to each received packet), 4 bytes for a VLAN
470 * header, and 4 bytes for the trailing FCS -- 24
471 * bytes total.
472 */
473 skb_size = mp->dev->mtu + 24;
474
475 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
de34f225 476 if (skb == NULL)
1da177e4 477 break;
de34f225 478
908b637f 479 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 480 if (unaligned)
908b637f 481 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 482
8a578111
LB		 483 rxq->rx_desc_count++;
484 rx = rxq->rx_used_desc;
485 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
de34f225 486
8a578111
LB		 487 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
488 skb_size, DMA_FROM_DEVICE);
489 rxq->rx_desc_area[rx].buf_size = skb_size;
490 rxq->rx_skb[rx] = skb;
de34f225 491 wmb();
8a578111 492 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 493 RX_ENABLE_INTERRUPT;
494 wmb();
495
fc32b0e2
LB		 496 /*
497 * The hardware automatically prepends 2 bytes of
498 * dummy data to each received packet, so that the
499 * IP header ends up 16-byte aligned.
500 */
501 skb_reserve(skb, 2);
1da177e4 502 }
de34f225 503
12e4ab79 504 if (rxq->rx_desc_count != rxq->rx_ring_size) {
8a578111
LB		 505 rxq->rx_oom.expires = jiffies + (HZ / 10);
506 add_timer(&rxq->rx_oom);
1da177e4 507 }
de34f225
LB		 508
509 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 510}
511
8a578111 512static inline void rxq_refill_timer_wrapper(unsigned long data)
1da177e4 513{
8a578111 514 rxq_refill((struct rx_queue *)data);
1da177e4
LT		 515}
516
8a578111 517static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 518{
8a578111
LB		 519 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
520 struct net_device_stats *stats = &mp->dev->stats;
521 int rx;
1da177e4 522
8a578111
LB		 523 rx = 0;
524 while (rx < budget) {
fc32b0e2 525 struct rx_desc *rx_desc;
96587661 526 unsigned int cmd_sts;
fc32b0e2 527 struct sk_buff *skb;
96587661 528 unsigned long flags;
d344bff9 529
96587661 530 spin_lock_irqsave(&mp->lock, flags);
ff561eef 531
8a578111 532 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 533
96587661
LB		 534 cmd_sts = rx_desc->cmd_sts;
535 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
536 spin_unlock_irqrestore(&mp->lock, flags);
537 break;
538 }
539 rmb();
1da177e4 540
8a578111
LB		 541 skb = rxq->rx_skb[rxq->rx_curr_desc];
542 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 543
8a578111 544 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
ff561eef 545
96587661 546 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 547
fc32b0e2
LB		 548 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
549 mp->dev->mtu + 24, DMA_FROM_DEVICE);
8a578111
LB		 550 rxq->rx_desc_count--;
551 rx++;
b1dd9ca1 552
468d09f8
DF		 553 /*
554 * Update statistics.
fc32b0e2
LB		 555 *
556 * Note that the descriptor byte count includes 2 dummy
557 * bytes automatically inserted by the hardware at the
558 * start of the packet (which we don't count), and a 4
559 * byte CRC at the end of the packet (which we do count).
468d09f8 560 */
1da177e4 561 stats->rx_packets++;
fc32b0e2 562 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 563
1da177e4 564 /*
fc32b0e2
LB		 565 * In case we received a packet without first / last bits
566 * on, or the error summary bit is set, the packet needs
567 * to be dropped.
1da177e4 568 */
96587661 569 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 570 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 571 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 572 stats->rx_dropped++;
fc32b0e2 573
96587661 574 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 575 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 576 if (net_ratelimit())
fc32b0e2
LB		 577 dev_printk(KERN_ERR, &mp->dev->dev,
578 "received packet spanning "
579 "multiple descriptors\n");
1da177e4 580 }
fc32b0e2 581
96587661 582 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 583 stats->rx_errors++;
584
585 dev_kfree_skb_irq(skb);
586 } else {
587 /*
588 * The -4 is for the CRC in the trailer of the
589 * received packet
590 */
fc32b0e2 591 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 592
96587661 593 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 594 skb->ip_summed = CHECKSUM_UNNECESSARY;
595 skb->csum = htons(
96587661 596 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 597 }
8a578111 598 skb->protocol = eth_type_trans(skb, mp->dev);
e5371493 599#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 600 netif_receive_skb(skb);
601#else
602 netif_rx(skb);
603#endif
604 }
fc32b0e2 605
8a578111 606 mp->dev->last_rx = jiffies;
1da177e4 607 }
fc32b0e2 608
8a578111 609 rxq_refill(rxq);
1da177e4 610
8a578111 611 return rx;
1da177e4
LT		 612}
613
e5371493 614#ifdef MV643XX_ETH_NAPI
e5371493 615static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 616{
8a578111
LB		 617 struct mv643xx_eth_private *mp;
618 int rx;
64da80a2 619 int i;
8a578111
LB		 620
621 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 622
e5371493 623#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 624 if (++mp->tx_clean_threshold > 5) {
c9df406f 625 mp->tx_clean_threshold = 0;
3d6b35bc
LB		 626 for (i = 0; i < 8; i++)
627 if (mp->txq_mask & (1 << i))
628 txq_reclaim(mp->txq + i, 0);
4dfc1c87
LB		 629
630 if (netif_carrier_ok(mp->dev)) {
631 spin_lock(&mp->lock);
632 __txq_maybe_wake(mp->txq + mp->txq_primary);
633 spin_unlock(&mp->lock);
634 }
d0412d96 635 }
c9df406f 636#endif
d0412d96 637
64da80a2
LB		 638 rx = 0;
639 for (i = 7; rx < budget && i >= 0; i--)
640 if (mp->rxq_mask & (1 << i))
641 rx += rxq_process(mp->rxq + i, budget - rx);
d0412d96 642
8a578111
LB		 643 if (rx < budget) {
644 netif_rx_complete(mp->dev, napi);
645 wrl(mp, INT_CAUSE(mp->port_num), 0);
646 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
226bb6b7 647 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
d0412d96 648 }
c9df406f 649
8a578111 650 return rx;
d0412d96 651}
c9df406f 652#endif
d0412d96 653
c9df406f
LB		 654
655/* tx ***********************************************************************/
c9df406f 656static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 657{
13d64285 658 int frag;
1da177e4 659
c9df406f 660 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 661 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
662 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 663 return 1;
1da177e4 664 }
13d64285 665
c9df406f
LB		 666 return 0;
667}
7303fde8 668
13d64285 669static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 670{
671 int tx_desc_curr;
d0412d96 672
13d64285 673 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 674
13d64285
LB		 675 tx_desc_curr = txq->tx_curr_desc;
676 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
e4d00fa9 677
13d64285 678 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 679
c9df406f
LB		 680 return tx_desc_curr;
681}
468d09f8 682
13d64285 683static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 684{
13d64285 685 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 686 int frag;
1da177e4 687
13d64285
LB		 688 for (frag = 0; frag < nr_frags; frag++) {
689 skb_frag_t *this_frag;
690 int tx_index;
691 struct tx_desc *desc;
692
693 this_frag = &skb_shinfo(skb)->frags[frag];
694 tx_index = txq_alloc_desc_index(txq);
695 desc = &txq->tx_desc_area[tx_index];
696
697 /*
698 * The last fragment will generate an interrupt
699 * which will free the skb on TX completion.
700 */
701 if (frag == nr_frags - 1) {
702 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
703 ZERO_PADDING | TX_LAST_DESC |
704 TX_ENABLE_INTERRUPT;
705 txq->tx_skb[tx_index] = skb;
706 } else {
707 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
708 txq->tx_skb[tx_index] = NULL;
709 }
710
c9df406f
LB		 711 desc->l4i_chk = 0;
712 desc->byte_cnt = this_frag->size;
713 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
714 this_frag->page_offset,
715 this_frag->size,
716 DMA_TO_DEVICE);
717 }
1da177e4
LT		 718}
719
c9df406f
LB		 720static inline __be16 sum16_as_be(__sum16 sum)
721{
722 return (__force __be16)sum;
723}
1da177e4 724
13d64285 725static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 726{
8fa89bf5 727 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 728 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 729 int tx_index;
cc9754b3 730 struct tx_desc *desc;
c9df406f
LB		 731 u32 cmd_sts;
732 int length;
1da177e4 733
cc9754b3 734 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 735
13d64285
LB		 736 tx_index = txq_alloc_desc_index(txq);
737 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 738
739 if (nr_frags) {
13d64285 740 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 741
742 length = skb_headlen(skb);
13d64285 743 txq->tx_skb[tx_index] = NULL;
c9df406f 744 } else {
cc9754b3 745 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 746 length = skb->len;
13d64285 747 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 748 }
749
750 desc->byte_cnt = length;
751 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
752
753 if (skb->ip_summed == CHECKSUM_PARTIAL) {
754 BUG_ON(skb->protocol != htons(ETH_P_IP));
755
cc9754b3
LB		 756 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
757 GEN_IP_V4_CHECKSUM |
758 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 759
760 switch (ip_hdr(skb)->protocol) {
761 case IPPROTO_UDP:
cc9754b3 762 cmd_sts |= UDP_FRAME;
c9df406f
LB		 763 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
764 break;
765 case IPPROTO_TCP:
766 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
767 break;
768 default:
769 BUG();
770 }
771 } else {
772 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 773 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 774 desc->l4i_chk = 0;
775 }
776
777 /* ensure all other descriptors are written before first cmd_sts */
778 wmb();
779 desc->cmd_sts = cmd_sts;
780
8fa89bf5
LB		 781 /* clear TX_END interrupt status */
782 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
783 rdl(mp, INT_CAUSE(mp->port_num));
784
c9df406f
LB		 785 /* ensure all descriptors are written before poking hardware */
786 wmb();
13d64285 787 txq_enable(txq);
c9df406f 788
13d64285 789 txq->tx_desc_count += nr_frags + 1;
1da177e4 790}
1da177e4 791
fc32b0e2 792static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 793{
e5371493 794 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 795 struct net_device_stats *stats = &dev->stats;
13d64285 796 struct tx_queue *txq;
c9df406f 797 unsigned long flags;
afdb57a2 798
c9df406f
LB		 799 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
800 stats->tx_dropped++;
fc32b0e2
LB		 801 dev_printk(KERN_DEBUG, &dev->dev,
802 "failed to linearize skb with tiny "
803 "unaligned fragment\n");
c9df406f
LB		 804 return NETDEV_TX_BUSY;
805 }
806
807 spin_lock_irqsave(&mp->lock, flags);
808
3d6b35bc 809 txq = mp->txq + mp->txq_primary;
13d64285
LB		 810
811 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
c9df406f 812 spin_unlock_irqrestore(&mp->lock, flags);
3d6b35bc
LB		 813 if (txq->index == mp->txq_primary && net_ratelimit())
814 dev_printk(KERN_ERR, &dev->dev,
815 "primary tx queue full?!\n");
816 kfree_skb(skb);
817 return NETDEV_TX_OK;
c9df406f
LB		 818 }
819
13d64285 820 txq_submit_skb(txq, skb);
c9df406f
LB		 821 stats->tx_bytes += skb->len;
822 stats->tx_packets++;
823 dev->trans_start = jiffies;
824
3d6b35bc
LB		 825 if (txq->index == mp->txq_primary) {
826 int entries_left;
827
828 entries_left = txq->tx_ring_size - txq->tx_desc_count;
829 if (entries_left < MAX_DESCS_PER_SKB)
830 netif_stop_queue(dev);
831 }
c9df406f
LB		 832
833 spin_unlock_irqrestore(&mp->lock, flags);
834
835 return NETDEV_TX_OK;
1da177e4
LT		 836}
837
c9df406f 838
89df5fdc
LB		 839/* tx rate control **********************************************************/
840/*
841 * Set total maximum TX rate (shared by all TX queues for this port)
842 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
843 */
844static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
845{
846 int token_rate;
847 int mtu;
848 int bucket_size;
849
850 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
851 if (token_rate > 1023)
852 token_rate = 1023;
853
854 mtu = (mp->dev->mtu + 255) >> 8;
855 if (mtu > 63)
856 mtu = 63;
857
858 bucket_size = (burst + 255) >> 8;
859 if (bucket_size > 65535)
860 bucket_size = 65535;
861
1e881592
LB		 862 if (mp->shared->tx_bw_control_moved) {
863 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
864 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
865 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
866 } else {
867 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
868 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
869 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
870 }
89df5fdc
LB		 871}
872
873static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
874{
875 struct mv643xx_eth_private *mp = txq_to_mp(txq);
876 int token_rate;
877 int bucket_size;
878
879 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
880 if (token_rate > 1023)
881 token_rate = 1023;
882
883 bucket_size = (burst + 255) >> 8;
884 if (bucket_size > 65535)
885 bucket_size = 65535;
886
3d6b35bc
LB		 887 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
888 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
89df5fdc
LB		 889 (bucket_size << 10) | token_rate);
890}
891
892static void txq_set_fixed_prio_mode(struct tx_queue *txq)
893{
894 struct mv643xx_eth_private *mp = txq_to_mp(txq);
895 int off;
896 u32 val;
897
898 /*
899 * Turn on fixed priority mode.
900 */
1e881592
LB		 901 if (mp->shared->tx_bw_control_moved)
902 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
903 else
904 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 905
906 val = rdl(mp, off);
3d6b35bc 907 val |= 1 << txq->index;
89df5fdc
LB		 908 wrl(mp, off, val);
909}
910
911static void txq_set_wrr(struct tx_queue *txq, int weight)
912{
913 struct mv643xx_eth_private *mp = txq_to_mp(txq);
914 int off;
915 u32 val;
916
917 /*
918 * Turn off fixed priority mode.
919 */
1e881592
LB		 920 if (mp->shared->tx_bw_control_moved)
921 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
922 else
923 off = TXQ_FIX_PRIO_CONF(mp->port_num);
89df5fdc
LB		 924
925 val = rdl(mp, off);
3d6b35bc 926 val &= ~(1 << txq->index);
89df5fdc
LB		 927 wrl(mp, off, val);
928
929 /*
930 * Configure WRR weight for this queue.
931 */
3d6b35bc 932 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
89df5fdc
LB		 933
934 val = rdl(mp, off);
935 val = (val & ~0xff) | (weight & 0xff);
936 wrl(mp, off, val);
937}
938
939
c9df406f 940/* mii management interface *************************************************/
fc32b0e2
LB		 941#define SMI_BUSY 0x10000000
942#define SMI_READ_VALID 0x08000000
943#define SMI_OPCODE_READ 0x04000000
944#define SMI_OPCODE_WRITE 0x00000000
c9df406f 945
fc32b0e2
LB		 946static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
947 unsigned int reg, unsigned int *value)
1da177e4 948{
cc9754b3 949 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 950 unsigned long flags;
1da177e4
LT		 951 int i;
952
c9df406f
LB		 953 /* the SMI register is a shared resource */
954 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
955
956 /* wait for the SMI register to become available */
cc9754b3 957 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 958 if (i == 1000) {
c9df406f
LB		 959 printk("%s: PHY busy timeout\n", mp->dev->name);
960 goto out;
961 }
e1bea50a 962 udelay(10);
1da177e4
LT		 963 }
964
fc32b0e2 965 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 966
c9df406f 967 /* now wait for the data to be valid */
cc9754b3 968 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 969 if (i == 1000) {
c9df406f
LB		 970 printk("%s: PHY read timeout\n", mp->dev->name);
971 goto out;
972 }
e1bea50a 973 udelay(10);
c9df406f
LB		 974 }
975
976 *value = readl(smi_reg) & 0xffff;
977out:
978 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 979}
980
fc32b0e2
LB		 981static void smi_reg_write(struct mv643xx_eth_private *mp,
982 unsigned int addr,
983 unsigned int reg, unsigned int value)
1da177e4 984{
cc9754b3 985 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 986 unsigned long flags;
1da177e4
LT		 987 int i;
988
c9df406f
LB		 989 /* the SMI register is a shared resource */
990 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
991
992 /* wait for the SMI register to become available */
cc9754b3 993 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 994 if (i == 1000) {
c9df406f
LB		 995 printk("%s: PHY busy timeout\n", mp->dev->name);
996 goto out;
997 }
e1bea50a 998 udelay(10);
1da177e4
LT		 999 }
1000
fc32b0e2
LB		 1001 writel(SMI_OPCODE_WRITE | (reg << 21) |
1002 (addr << 16) | (value & 0xffff), smi_reg);
c9df406f
LB		 1003out:
1004 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1005}
1da177e4 1006
c9df406f
LB		 1007
1008/* mib counters *************************************************************/
fc32b0e2 1009static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1010{
fc32b0e2 1011 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1012}
1013
fc32b0e2 1014static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1015{
fc32b0e2
LB		 1016 int i;
1017
1018 for (i = 0; i < 0x80; i += 4)
1019 mib_read(mp, i);
c9df406f 1020}
d0412d96 1021
fc32b0e2 1022static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1023{
e5371493 1024 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1025
fc32b0e2
LB		 1026 p->good_octets_received += mib_read(mp, 0x00);
1027 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1028 p->bad_octets_received += mib_read(mp, 0x08);
1029 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1030 p->good_frames_received += mib_read(mp, 0x10);
1031 p->bad_frames_received += mib_read(mp, 0x14);
1032 p->broadcast_frames_received += mib_read(mp, 0x18);
1033 p->multicast_frames_received += mib_read(mp, 0x1c);
1034 p->frames_64_octets += mib_read(mp, 0x20);
1035 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1036 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1037 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1038 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1039 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1040 p->good_octets_sent += mib_read(mp, 0x38);
1041 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1042 p->good_frames_sent += mib_read(mp, 0x40);
1043 p->excessive_collision += mib_read(mp, 0x44);
1044 p->multicast_frames_sent += mib_read(mp, 0x48);
1045 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1046 p->unrec_mac_control_received += mib_read(mp, 0x50);
1047 p->fc_sent += mib_read(mp, 0x54);
1048 p->good_fc_received += mib_read(mp, 0x58);
1049 p->bad_fc_received += mib_read(mp, 0x5c);
1050 p->undersize_received += mib_read(mp, 0x60);
1051 p->fragments_received += mib_read(mp, 0x64);
1052 p->oversize_received += mib_read(mp, 0x68);
1053 p->jabber_received += mib_read(mp, 0x6c);
1054 p->mac_receive_error += mib_read(mp, 0x70);
1055 p->bad_crc_event += mib_read(mp, 0x74);
1056 p->collision += mib_read(mp, 0x78);
1057 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 1058}
1059
c9df406f
LB		 1060
1061/* ethtool ******************************************************************/
e5371493 1062struct mv643xx_eth_stats {
c9df406f
LB		 1063 char stat_string[ETH_GSTRING_LEN];
1064 int sizeof_stat;
16820054
LB		 1065 int netdev_off;
1066 int mp_off;
c9df406f
LB		 1067};
1068
16820054
LB		 1069#define SSTAT(m) \
1070 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1071 offsetof(struct net_device, stats.m), -1 }
1072
1073#define MIBSTAT(m) \
1074 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1075 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1076
1077static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1078 SSTAT(rx_packets),
1079 SSTAT(tx_packets),
1080 SSTAT(rx_bytes),
1081 SSTAT(tx_bytes),
1082 SSTAT(rx_errors),
1083 SSTAT(tx_errors),
1084 SSTAT(rx_dropped),
1085 SSTAT(tx_dropped),
1086 MIBSTAT(good_octets_received),
1087 MIBSTAT(bad_octets_received),
1088 MIBSTAT(internal_mac_transmit_err),
1089 MIBSTAT(good_frames_received),
1090 MIBSTAT(bad_frames_received),
1091 MIBSTAT(broadcast_frames_received),
1092 MIBSTAT(multicast_frames_received),
1093 MIBSTAT(frames_64_octets),
1094 MIBSTAT(frames_65_to_127_octets),
1095 MIBSTAT(frames_128_to_255_octets),
1096 MIBSTAT(frames_256_to_511_octets),
1097 MIBSTAT(frames_512_to_1023_octets),
1098 MIBSTAT(frames_1024_to_max_octets),
1099 MIBSTAT(good_octets_sent),
1100 MIBSTAT(good_frames_sent),
1101 MIBSTAT(excessive_collision),
1102 MIBSTAT(multicast_frames_sent),
1103 MIBSTAT(broadcast_frames_sent),
1104 MIBSTAT(unrec_mac_control_received),
1105 MIBSTAT(fc_sent),
1106 MIBSTAT(good_fc_received),
1107 MIBSTAT(bad_fc_received),
1108 MIBSTAT(undersize_received),
1109 MIBSTAT(fragments_received),
1110 MIBSTAT(oversize_received),
1111 MIBSTAT(jabber_received),
1112 MIBSTAT(mac_receive_error),
1113 MIBSTAT(bad_crc_event),
1114 MIBSTAT(collision),
1115 MIBSTAT(late_collision),
c9df406f
LB		 1116};
1117
e5371493 1118static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 1119{
e5371493 1120 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 1121 int err;
1122
1123 spin_lock_irq(&mp->lock);
1124 err = mii_ethtool_gset(&mp->mii, cmd);
1125 spin_unlock_irq(&mp->lock);
1126
fc32b0e2
LB		 1127 /*
1128 * The MAC does not support 1000baseT_Half.
1129 */
d0412d96
JC		 1130 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1131 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1132
1133 return err;
1134}
1135
bedfe324
LB		 1136static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1137{
81600eea
LB		 1138 struct mv643xx_eth_private *mp = netdev_priv(dev);
1139 u32 port_status;
1140
1141 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1142
bedfe324
LB		 1143 cmd->supported = SUPPORTED_MII;
1144 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1145 switch (port_status & PORT_SPEED_MASK) {
1146 case PORT_SPEED_10:
1147 cmd->speed = SPEED_10;
1148 break;
1149 case PORT_SPEED_100:
1150 cmd->speed = SPEED_100;
1151 break;
1152 case PORT_SPEED_1000:
1153 cmd->speed = SPEED_1000;
1154 break;
1155 default:
1156 cmd->speed = -1;
1157 break;
1158 }
1159 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1160 cmd->port = PORT_MII;
1161 cmd->phy_address = 0;
1162 cmd->transceiver = XCVR_INTERNAL;
1163 cmd->autoneg = AUTONEG_DISABLE;
1164 cmd->maxtxpkt = 1;
1165 cmd->maxrxpkt = 1;
1166
1167 return 0;
1168}
1169
e5371493 1170static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1171{
e5371493 1172 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 1173 int err;
1174
fc32b0e2
LB		 1175 /*
1176 * The MAC does not support 1000baseT_Half.
1177 */
1178 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1179
c9df406f
LB		 1180 spin_lock_irq(&mp->lock);
1181 err = mii_ethtool_sset(&mp->mii, cmd);
1182 spin_unlock_irq(&mp->lock);
85cf572c 1183
c9df406f
LB		 1184 return err;
1185}
1da177e4 1186
bedfe324
LB		 1187static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1188{
1189 return -EINVAL;
1190}
1191
fc32b0e2
LB		 1192static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1193 struct ethtool_drvinfo *drvinfo)
c9df406f 1194{
e5371493
LB		 1195 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1196 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 1197 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 1198 strncpy(drvinfo->bus_info, "platform", 32);
16820054 1199 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1200}
1da177e4 1201
fc32b0e2 1202static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1203{
e5371493 1204 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1205
c9df406f
LB		 1206 return mii_nway_restart(&mp->mii);
1207}
1da177e4 1208
bedfe324
LB		 1209static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1210{
1211 return -EINVAL;
1212}
1213
c9df406f
LB		 1214static u32 mv643xx_eth_get_link(struct net_device *dev)
1215{
e5371493 1216 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1217
c9df406f
LB		 1218 return mii_link_ok(&mp->mii);
1219}
1da177e4 1220
bedfe324
LB		 1221static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1222{
1223 return 1;
1224}
1225
fc32b0e2
LB		 1226static void mv643xx_eth_get_strings(struct net_device *dev,
1227 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1228{
1229 int i;
1da177e4 1230
fc32b0e2
LB		 1231 if (stringset == ETH_SS_STATS) {
1232 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1233 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1234 mv643xx_eth_stats[i].stat_string,
e5371493 1235 ETH_GSTRING_LEN);
c9df406f 1236 }
c9df406f
LB		 1237 }
1238}
1da177e4 1239
fc32b0e2
LB		 1240static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1241 struct ethtool_stats *stats,
1242 uint64_t *data)
c9df406f 1243{
fc32b0e2 1244 struct mv643xx_eth_private *mp = dev->priv;
c9df406f 1245 int i;
1da177e4 1246
fc32b0e2 1247 mib_counters_update(mp);
1da177e4 1248
16820054
LB		 1249 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1250 const struct mv643xx_eth_stats *stat;
1251 void *p;
1252
1253 stat = mv643xx_eth_stats + i;
1254
1255 if (stat->netdev_off >= 0)
1256 p = ((void *)mp->dev) + stat->netdev_off;
1257 else
1258 p = ((void *)mp) + stat->mp_off;
1259
1260 data[i] = (stat->sizeof_stat == 8) ?
1261 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1262 }
c9df406f 1263}
1da177e4 1264
fc32b0e2 1265static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1266{
fc32b0e2 1267 if (sset == ETH_SS_STATS)
16820054 1268 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1269
1270 return -EOPNOTSUPP;
c9df406f 1271}
1da177e4 1272
e5371493 1273static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1274 .get_settings = mv643xx_eth_get_settings,
1275 .set_settings = mv643xx_eth_set_settings,
1276 .get_drvinfo = mv643xx_eth_get_drvinfo,
1277 .nway_reset = mv643xx_eth_nway_reset,
1278 .get_link = mv643xx_eth_get_link,
c9df406f 1279 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1280 .get_strings = mv643xx_eth_get_strings,
1281 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1282 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1283};
1da177e4 1284
bedfe324
LB		 1285static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1286 .get_settings = mv643xx_eth_get_settings_phyless,
1287 .set_settings = mv643xx_eth_set_settings_phyless,
1288 .get_drvinfo = mv643xx_eth_get_drvinfo,
1289 .nway_reset = mv643xx_eth_nway_reset_phyless,
1290 .get_link = mv643xx_eth_get_link_phyless,
1291 .set_sg = ethtool_op_set_sg,
1292 .get_strings = mv643xx_eth_get_strings,
1293 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1294 .get_sset_count = mv643xx_eth_get_sset_count,
1295};
1296
bea3348e 1297
c9df406f 1298/* address handling *********************************************************/
5daffe94 1299static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1300{
c9df406f
LB		 1301 unsigned int mac_h;
1302 unsigned int mac_l;
1da177e4 1303
fc32b0e2
LB		 1304 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1305 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1306
5daffe94
LB		 1307 addr[0] = (mac_h >> 24) & 0xff;
1308 addr[1] = (mac_h >> 16) & 0xff;
1309 addr[2] = (mac_h >> 8) & 0xff;
1310 addr[3] = mac_h & 0xff;
1311 addr[4] = (mac_l >> 8) & 0xff;
1312 addr[5] = mac_l & 0xff;
c9df406f 1313}
1da177e4 1314
e5371493 1315static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1316{
fc32b0e2 1317 int i;
1da177e4 1318
fc32b0e2
LB		 1319 for (i = 0; i < 0x100; i += 4) {
1320 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1321 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1322 }
fc32b0e2
LB		 1323
1324 for (i = 0; i < 0x10; i += 4)
1325 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1326}
d0412d96 1327
e5371493 1328static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1329 int table, unsigned char entry)
c9df406f
LB		 1330{
1331 unsigned int table_reg;
ab4384a6 1332
c9df406f 1333 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1334 table_reg = rdl(mp, table + (entry & 0xfc));
1335 table_reg |= 0x01 << (8 * (entry & 3));
1336 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1337}
1338
5daffe94 1339static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1340{
c9df406f
LB		 1341 unsigned int mac_h;
1342 unsigned int mac_l;
1343 int table;
1da177e4 1344
fc32b0e2
LB		 1345 mac_l = (addr[4] << 8) | addr[5];
1346 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1347
fc32b0e2
LB		 1348 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1349 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1350
fc32b0e2 1351 table = UNICAST_TABLE(mp->port_num);
5daffe94 1352 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1353}
1354
fc32b0e2 1355static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1356{
e5371493 1357 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1358
fc32b0e2
LB		 1359 /* +2 is for the offset of the HW addr type */
1360 memcpy(dev->dev_addr, addr + 2, 6);
1361
cc9754b3
LB		 1362 init_mac_tables(mp);
1363 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1364
1365 return 0;
1366}
1367
69876569
LB		 1368static int addr_crc(unsigned char *addr)
1369{
1370 int crc = 0;
1371 int i;
1372
1373 for (i = 0; i < 6; i++) {
1374 int j;
1375
1376 crc = (crc ^ addr[i]) << 8;
1377 for (j = 7; j >= 0; j--) {
1378 if (crc & (0x100 << j))
1379 crc ^= 0x107 << j;
1380 }
1381 }
1382
1383 return crc;
1384}
1385
fc32b0e2 1386static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1387{
fc32b0e2
LB		 1388 struct mv643xx_eth_private *mp = netdev_priv(dev);
1389 u32 port_config;
1390 struct dev_addr_list *addr;
1391 int i;
c8aaea25 1392
fc32b0e2
LB		 1393 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1394 if (dev->flags & IFF_PROMISC)
1395 port_config |= UNICAST_PROMISCUOUS_MODE;
1396 else
1397 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1398 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1399
fc32b0e2
LB		 1400 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1401 int port_num = mp->port_num;
1402 u32 accept = 0x01010101;
c8aaea25 1403
fc32b0e2
LB		 1404 for (i = 0; i < 0x100; i += 4) {
1405 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1406 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1407 }
1408 return;
1409 }
c8aaea25 1410
fc32b0e2
LB		 1411 for (i = 0; i < 0x100; i += 4) {
1412 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1413 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1414 }
1415
fc32b0e2
LB		 1416 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1417 u8 *a = addr->da_addr;
1418 int table;
324ff2c1 1419
fc32b0e2
LB		 1420 if (addr->da_addrlen != 6)
1421 continue;
1da177e4 1422
fc32b0e2
LB		 1423 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1424 table = SPECIAL_MCAST_TABLE(mp->port_num);
1425 set_filter_table_entry(mp, table, a[5]);
1426 } else {
1427 int crc = addr_crc(a);
1da177e4 1428
fc32b0e2
LB		 1429 table = OTHER_MCAST_TABLE(mp->port_num);
1430 set_filter_table_entry(mp, table, crc);
1431 }
1432 }
c9df406f 1433}
c8aaea25 1434
c8aaea25 1435
c9df406f 1436/* rx/tx queue initialisation ***********************************************/
64da80a2 1437static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1438{
64da80a2 1439 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1440 struct rx_desc *rx_desc;
1441 int size;
c9df406f
LB		 1442 int i;
1443
64da80a2
LB		 1444 rxq->index = index;
1445
8a578111
LB		 1446 rxq->rx_ring_size = mp->default_rx_ring_size;
1447
1448 rxq->rx_desc_count = 0;
1449 rxq->rx_curr_desc = 0;
1450 rxq->rx_used_desc = 0;
1451
1452 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1453
64da80a2 1454 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1455 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1456 mp->rx_desc_sram_size);
1457 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1458 } else {
1459 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1460 &rxq->rx_desc_dma,
1461 GFP_KERNEL);
f7ea3337
PJ		 1462 }
1463
8a578111
LB		 1464 if (rxq->rx_desc_area == NULL) {
1465 dev_printk(KERN_ERR, &mp->dev->dev,
1466 "can't allocate rx ring (%d bytes)\n", size);
1467 goto out;
1468 }
1469 memset(rxq->rx_desc_area, 0, size);
1da177e4 1470
8a578111
LB		 1471 rxq->rx_desc_area_size = size;
1472 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1473 GFP_KERNEL);
1474 if (rxq->rx_skb == NULL) {
1475 dev_printk(KERN_ERR, &mp->dev->dev,
1476 "can't allocate rx skb ring\n");
1477 goto out_free;
1478 }
1479
1480 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1481 for (i = 0; i < rxq->rx_ring_size; i++) {
1482 int nexti = (i + 1) % rxq->rx_ring_size;
1483 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1484 nexti * sizeof(struct rx_desc);
1485 }
1486
1487 init_timer(&rxq->rx_oom);
1488 rxq->rx_oom.data = (unsigned long)rxq;
1489 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1490
1491 return 0;
1492
1493
1494out_free:
64da80a2 1495 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
8a578111
LB		 1496 iounmap(rxq->rx_desc_area);
1497 else
1498 dma_free_coherent(NULL, size,
1499 rxq->rx_desc_area,
1500 rxq->rx_desc_dma);
1501
1502out:
1503 return -ENOMEM;
c9df406f 1504}
c8aaea25 1505
8a578111 1506static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1507{
8a578111
LB		 1508 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1509 int i;
1510
1511 rxq_disable(rxq);
c8aaea25 1512
8a578111 1513 del_timer_sync(&rxq->rx_oom);
c9df406f 1514
8a578111
LB		 1515 for (i = 0; i < rxq->rx_ring_size; i++) {
1516 if (rxq->rx_skb[i]) {
1517 dev_kfree_skb(rxq->rx_skb[i]);
1518 rxq->rx_desc_count--;
1da177e4 1519 }
c8aaea25 1520 }
1da177e4 1521
8a578111
LB		 1522 if (rxq->rx_desc_count) {
1523 dev_printk(KERN_ERR, &mp->dev->dev,
1524 "error freeing rx ring -- %d skbs stuck\n",
1525 rxq->rx_desc_count);
1526 }
1527
64da80a2
LB		 1528 if (rxq->index == mp->rxq_primary &&
1529 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1530 iounmap(rxq->rx_desc_area);
c9df406f 1531 else
8a578111
LB		 1532 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1533 rxq->rx_desc_area, rxq->rx_desc_dma);
1534
1535 kfree(rxq->rx_skb);
c9df406f 1536}
1da177e4 1537
3d6b35bc 1538static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1539{
3d6b35bc 1540 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1541 struct tx_desc *tx_desc;
1542 int size;
c9df406f 1543 int i;
1da177e4 1544
3d6b35bc
LB		 1545 txq->index = index;
1546
13d64285
LB		 1547 txq->tx_ring_size = mp->default_tx_ring_size;
1548
1549 txq->tx_desc_count = 0;
1550 txq->tx_curr_desc = 0;
1551 txq->tx_used_desc = 0;
1552
1553 size = txq->tx_ring_size * sizeof(struct tx_desc);
1554
3d6b35bc 1555 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1556 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1557 mp->tx_desc_sram_size);
1558 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1559 } else {
1560 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1561 &txq->tx_desc_dma,
1562 GFP_KERNEL);
1563 }
1564
1565 if (txq->tx_desc_area == NULL) {
1566 dev_printk(KERN_ERR, &mp->dev->dev,
1567 "can't allocate tx ring (%d bytes)\n", size);
1568 goto out;
c9df406f 1569 }
13d64285
LB		 1570 memset(txq->tx_desc_area, 0, size);
1571
1572 txq->tx_desc_area_size = size;
1573 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1574 GFP_KERNEL);
1575 if (txq->tx_skb == NULL) {
1576 dev_printk(KERN_ERR, &mp->dev->dev,
1577 "can't allocate tx skb ring\n");
1578 goto out_free;
1579 }
1580
1581 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1582 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 1583 struct tx_desc *txd = tx_desc + i;
13d64285 1584 int nexti = (i + 1) % txq->tx_ring_size;
6b368f68
LB		 1585
1586 txd->cmd_sts = 0;
1587 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 1588 nexti * sizeof(struct tx_desc);
1589 }
1590
1591 return 0;
1592
c9df406f 1593
13d64285 1594out_free:
3d6b35bc 1595 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
13d64285
LB		 1596 iounmap(txq->tx_desc_area);
1597 else
1598 dma_free_coherent(NULL, size,
1599 txq->tx_desc_area,
1600 txq->tx_desc_dma);
c9df406f 1601
13d64285
LB		 1602out:
1603 return -ENOMEM;
c8aaea25 1604}
1da177e4 1605
13d64285 1606static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1607{
13d64285 1608 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1609 unsigned long flags;
1da177e4 1610
13d64285
LB		 1611 spin_lock_irqsave(&mp->lock, flags);
1612 while (txq->tx_desc_count > 0) {
1613 int tx_index;
1614 struct tx_desc *desc;
1615 u32 cmd_sts;
1616 struct sk_buff *skb;
1617 dma_addr_t addr;
1618 int count;
4d64e718 1619
13d64285
LB		 1620 tx_index = txq->tx_used_desc;
1621 desc = &txq->tx_desc_area[tx_index];
c9df406f 1622 cmd_sts = desc->cmd_sts;
4d64e718 1623
6b368f68
LB		 1624 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1625 if (!force)
1626 break;
1627 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1628 }
1da177e4 1629
13d64285
LB		 1630 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1631 txq->tx_desc_count--;
1da177e4 1632
c9df406f
LB		 1633 addr = desc->buf_ptr;
1634 count = desc->byte_cnt;
13d64285
LB		 1635 skb = txq->tx_skb[tx_index];
1636 txq->tx_skb[tx_index] = NULL;
c8aaea25 1637
cc9754b3 1638 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1639 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1640 mp->dev->stats.tx_errors++;
c9df406f 1641 }
1da177e4 1642
13d64285
LB		 1643 /*
1644 * Drop mp->lock while we free the skb.
1645 */
c9df406f 1646 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1647
cc9754b3 1648 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1649 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1650 else
1651 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1652
c9df406f
LB		 1653 if (skb)
1654 dev_kfree_skb_irq(skb);
63c9e549 1655
13d64285 1656 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1657 }
13d64285 1658 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1659}
1da177e4 1660
13d64285 1661static void txq_deinit(struct tx_queue *txq)
c9df406f 1662{
13d64285 1663 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1664
13d64285
LB		 1665 txq_disable(txq);
1666 txq_reclaim(txq, 1);
1da177e4 1667
13d64285 1668 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1669
3d6b35bc
LB		 1670 if (txq->index == mp->txq_primary &&
1671 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 1672 iounmap(txq->tx_desc_area);
c9df406f 1673 else
13d64285
LB		 1674 dma_free_coherent(NULL, txq->tx_desc_area_size,
1675 txq->tx_desc_area, txq->tx_desc_dma);
1676
1677 kfree(txq->tx_skb);
c9df406f 1678}
1da177e4 1679
1da177e4 1680
c9df406f 1681/* netdev ops and related ***************************************************/
fc32b0e2 1682static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1683{
1684 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1685 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1686 u32 int_cause;
1687 u32 int_cause_ext;
ce4e2e45 1688
226bb6b7
LB		 1689 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1690 (INT_TX_END | INT_RX | INT_EXT);
fc32b0e2
LB		 1691 if (int_cause == 0)
1692 return IRQ_NONE;
1693
1694 int_cause_ext = 0;
cc9754b3 1695 if (int_cause & INT_EXT) {
13d64285 1696 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
073a345c 1697 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
13d64285 1698 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1699 }
1da177e4 1700
fc32b0e2 1701 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
81600eea 1702 if (rdl(mp, PORT_STATUS(mp->port_num)) & LINK_UP) {
c9df406f
LB		 1703 if (!netif_carrier_ok(dev)) {
1704 netif_carrier_on(dev);
6b368f68 1705 netif_wake_queue(dev);
c9df406f
LB		 1706 }
1707 } else if (netif_carrier_ok(dev)) {
6b368f68
LB		 1708 int i;
1709
c9df406f
LB		 1710 netif_stop_queue(dev);
1711 netif_carrier_off(dev);
6b368f68
LB		 1712
1713 for (i = 0; i < 8; i++) {
1714 struct tx_queue *txq = mp->txq + i;
1715
1716 if (mp->txq_mask & (1 << i)) {
1717 txq_reclaim(txq, 1);
1718 txq_reset_hw_ptr(txq);
1719 }
1720 }
c9df406f
LB		 1721 }
1722 }
1da177e4 1723
64da80a2
LB		 1724 /*
1725 * RxBuffer or RxError set for any of the 8 queues?
1726 */
e5371493 1727#ifdef MV643XX_ETH_NAPI
cc9754b3 1728 if (int_cause & INT_RX) {
13d64285 1729 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1730 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1731
c9df406f 1732 netif_rx_schedule(dev, &mp->napi);
84dd619e 1733 }
c9df406f 1734#else
64da80a2
LB		 1735 if (int_cause & INT_RX) {
1736 int i;
1737
1738 for (i = 7; i >= 0; i--)
1739 if (mp->rxq_mask & (1 << i))
1740 rxq_process(mp->rxq + i, INT_MAX);
1741 }
c9df406f 1742#endif
fc32b0e2 1743
3d6b35bc
LB		 1744 /*
1745 * TxBuffer or TxError set for any of the 8 queues?
1746 */
13d64285 1747 if (int_cause_ext & INT_EXT_TX) {
3d6b35bc
LB		 1748 int i;
1749
1750 for (i = 0; i < 8; i++)
1751 if (mp->txq_mask & (1 << i))
1752 txq_reclaim(mp->txq + i, 0);
8fa89bf5
LB		 1753
1754 /*
1755 * Enough space again in the primary TX queue for a
1756 * full packet?
1757 */
6b368f68
LB		 1758 if (netif_carrier_ok(dev)) {
1759 spin_lock(&mp->lock);
1760 __txq_maybe_wake(mp->txq + mp->txq_primary);
1761 spin_unlock(&mp->lock);
1762 }
226bb6b7 1763 }
3d6b35bc 1764
226bb6b7
LB		 1765 /*
1766 * Any TxEnd interrupts?
1767 */
1768 if (int_cause & INT_TX_END) {
1769 int i;
1770
1771 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
8fa89bf5
LB		 1772
1773 spin_lock(&mp->lock);
226bb6b7
LB		 1774 for (i = 0; i < 8; i++) {
1775 struct tx_queue *txq = mp->txq + i;
8fa89bf5
LB		 1776 u32 hw_desc_ptr;
1777 u32 expected_ptr;
1778
1779 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1780 continue;
1781
1782 hw_desc_ptr =
1783 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1784 expected_ptr = (u32)txq->tx_desc_dma +
1785 txq->tx_curr_desc * sizeof(struct tx_desc);
1786
1787 if (hw_desc_ptr != expected_ptr)
226bb6b7
LB		 1788 txq_enable(txq);
1789 }
8fa89bf5 1790 spin_unlock(&mp->lock);
13d64285 1791 }
1da177e4 1792
c9df406f 1793 return IRQ_HANDLED;
1da177e4
LT		 1794}
1795
e5371493 1796static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1797{
fc32b0e2 1798 unsigned int data;
1da177e4 1799
7f106c1d
LB		 1800 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1801 data |= BMCR_RESET;
1802 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 1803
c9df406f
LB		 1804 do {
1805 udelay(1);
7f106c1d
LB		 1806 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1807 } while (data & BMCR_RESET);
1da177e4
LT		 1808}
1809
fc32b0e2 1810static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1811{
d0412d96 1812 u32 pscr;
8a578111 1813 int i;
1da177e4 1814
bedfe324
LB		 1815 /*
1816 * Perform PHY reset, if there is a PHY.
1817 */
1818 if (mp->phy_addr != -1) {
1819 struct ethtool_cmd cmd;
1820
1821 mv643xx_eth_get_settings(mp->dev, &cmd);
1822 phy_reset(mp);
1823 mv643xx_eth_set_settings(mp->dev, &cmd);
1824 }
1da177e4 1825
81600eea
LB		 1826 /*
1827 * Configure basic link parameters.
1828 */
1829 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1830
1831 pscr |= SERIAL_PORT_ENABLE;
1832 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1833
1834 pscr |= DO_NOT_FORCE_LINK_FAIL;
1835 if (mp->phy_addr == -1)
1836 pscr |= FORCE_LINK_PASS;
1837 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1838
1839 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1840
13d64285
LB		 1841 /*
1842 * Configure TX path and queues.
1843 */
89df5fdc 1844 tx_set_rate(mp, 1000000000, 16777216);
3d6b35bc
LB		 1845 for (i = 0; i < 8; i++) {
1846 struct tx_queue *txq = mp->txq + i;
13d64285 1847
3d6b35bc
LB		 1848 if ((mp->txq_mask & (1 << i)) == 0)
1849 continue;
1850
6b368f68 1851 txq_reset_hw_ptr(txq);
89df5fdc
LB		 1852 txq_set_rate(txq, 1000000000, 16777216);
1853 txq_set_fixed_prio_mode(txq);
13d64285
LB		 1854 }
1855
fc32b0e2
LB		 1856 /*
1857 * Add configured unicast address to address filter table.
1858 */
1859 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1860
d9a073ea
LB		 1861 /*
1862 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1863 * frames to RX queue #0.
1864 */
8a578111 1865 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1866
376489a2
LB		 1867 /*
1868 * Treat BPDUs as normal multicasts, and disable partition mode.
1869 */
8a578111 1870 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1871
8a578111 1872 /*
64da80a2 1873 * Enable the receive queues.
8a578111 1874 */
64da80a2
LB		 1875 for (i = 0; i < 8; i++) {
1876 struct rx_queue *rxq = mp->rxq + i;
1877 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
8a578111 1878 u32 addr;
1da177e4 1879
64da80a2
LB		 1880 if ((mp->rxq_mask & (1 << i)) == 0)
1881 continue;
1882
8a578111
LB		 1883 addr = (u32)rxq->rx_desc_dma;
1884 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1885 wrl(mp, off, addr);
1da177e4 1886
8a578111
LB		 1887 rxq_enable(rxq);
1888 }
1da177e4
LT		 1889}
1890
ffd86bbe 1891static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1892{
c9df406f 1893 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
773fc3ee 1894 u32 val;
1da177e4 1895
773fc3ee
LB		 1896 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1897 if (mp->shared->extended_rx_coal_limit) {
1898 if (coal > 0xffff)
1899 coal = 0xffff;
1900 val &= ~0x023fff80;
1901 val |= (coal & 0x8000) << 10;
1902 val |= (coal & 0x7fff) << 7;
1903 } else {
1904 if (coal > 0x3fff)
1905 coal = 0x3fff;
1906 val &= ~0x003fff00;
1907 val |= (coal & 0x3fff) << 8;
1908 }
1909 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1da177e4
LT		 1910}
1911
ffd86bbe 1912static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1913{
c9df406f 1914 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1915
fc32b0e2
LB		 1916 if (coal > 0x3fff)
1917 coal = 0x3fff;
1918 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1919}
1920
c9df406f 1921static int mv643xx_eth_open(struct net_device *dev)
16e03018 1922{
e5371493 1923 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1924 int err;
64da80a2 1925 int i;
16e03018 1926
fc32b0e2
LB		 1927 wrl(mp, INT_CAUSE(mp->port_num), 0);
1928 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1929 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 1930
fc32b0e2
LB		 1931 err = request_irq(dev->irq, mv643xx_eth_irq,
1932 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1933 dev->name, dev);
c9df406f 1934 if (err) {
fc32b0e2 1935 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 1936 return -EAGAIN;
16e03018
DF		 1937 }
1938
fc32b0e2 1939 init_mac_tables(mp);
16e03018 1940
64da80a2
LB		 1941 for (i = 0; i < 8; i++) {
1942 if ((mp->rxq_mask & (1 << i)) == 0)
1943 continue;
1944
1945 err = rxq_init(mp, i);
1946 if (err) {
1947 while (--i >= 0)
1948 if (mp->rxq_mask & (1 << i))
1949 rxq_deinit(mp->rxq + i);
1950 goto out;
1951 }
1952
1953 rxq_refill(mp->rxq + i);
1954 }
8a578111 1955
3d6b35bc
LB		 1956 for (i = 0; i < 8; i++) {
1957 if ((mp->txq_mask & (1 << i)) == 0)
1958 continue;
1959
1960 err = txq_init(mp, i);
1961 if (err) {
1962 while (--i >= 0)
1963 if (mp->txq_mask & (1 << i))
1964 txq_deinit(mp->txq + i);
1965 goto out_free;
1966 }
1967 }
16e03018 1968
e5371493 1969#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1970 napi_enable(&mp->napi);
1971#endif
16e03018 1972
fc32b0e2 1973 port_start(mp);
16e03018 1974
ffd86bbe
LB		 1975 set_rx_coal(mp, 0);
1976 set_tx_coal(mp, 0);
16e03018 1977
fc32b0e2
LB		 1978 wrl(mp, INT_MASK_EXT(mp->port_num),
1979 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 1980
226bb6b7 1981 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
16e03018 1982
c9df406f
LB		 1983 return 0;
1984
13d64285 1985
fc32b0e2 1986out_free:
64da80a2
LB		 1987 for (i = 0; i < 8; i++)
1988 if (mp->rxq_mask & (1 << i))
1989 rxq_deinit(mp->rxq + i);
fc32b0e2 1990out:
c9df406f
LB		 1991 free_irq(dev->irq, dev);
1992
1993 return err;
16e03018
DF		 1994}
1995
e5371493 1996static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 1997{
fc32b0e2 1998 unsigned int data;
64da80a2 1999 int i;
1da177e4 2000
64da80a2
LB		 2001 for (i = 0; i < 8; i++) {
2002 if (mp->rxq_mask & (1 << i))
2003 rxq_disable(mp->rxq + i);
3d6b35bc
LB		 2004 if (mp->txq_mask & (1 << i))
2005 txq_disable(mp->txq + i);
64da80a2 2006 }
ae9ae064
LB		 2007
2008 while (1) {
2009 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2010
2011 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2012 break;
13d64285 2013 udelay(10);
ae9ae064 2014 }
1da177e4 2015
c9df406f 2016 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 2017 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2018 data &= ~(SERIAL_PORT_ENABLE |
2019 DO_NOT_FORCE_LINK_FAIL |
2020 FORCE_LINK_PASS);
2021 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 2022}
2023
c9df406f 2024static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2025{
e5371493 2026 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2027 int i;
1da177e4 2028
fc32b0e2
LB		 2029 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2030 rdl(mp, INT_MASK(mp->port_num));
1da177e4 2031
e5371493 2032#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 2033 napi_disable(&mp->napi);
2034#endif
2035 netif_carrier_off(dev);
2036 netif_stop_queue(dev);
1da177e4 2037
fc32b0e2
LB		 2038 free_irq(dev->irq, dev);
2039
cc9754b3 2040 port_reset(mp);
fc32b0e2 2041 mib_counters_update(mp);
1da177e4 2042
64da80a2
LB		 2043 for (i = 0; i < 8; i++) {
2044 if (mp->rxq_mask & (1 << i))
2045 rxq_deinit(mp->rxq + i);
3d6b35bc
LB		 2046 if (mp->txq_mask & (1 << i))
2047 txq_deinit(mp->txq + i);
64da80a2 2048 }
1da177e4 2049
c9df406f 2050 return 0;
1da177e4
LT		 2051}
2052
fc32b0e2 2053static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2054{
e5371493 2055 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2056
bedfe324
LB		 2057 if (mp->phy_addr != -1)
2058 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2059
2060 return -EOPNOTSUPP;
1da177e4
LT		 2061}
2062
c9df406f 2063static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2064{
89df5fdc
LB		 2065 struct mv643xx_eth_private *mp = netdev_priv(dev);
2066
fc32b0e2 2067 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2068 return -EINVAL;
1da177e4 2069
c9df406f 2070 dev->mtu = new_mtu;
89df5fdc
LB		 2071 tx_set_rate(mp, 1000000000, 16777216);
2072
c9df406f
LB		 2073 if (!netif_running(dev))
2074 return 0;
1da177e4 2075
c9df406f
LB		 2076 /*
2077 * Stop and then re-open the interface. This will allocate RX
2078 * skbs of the new MTU.
2079 * There is a possible danger that the open will not succeed,
fc32b0e2 2080 * due to memory being full.
c9df406f
LB		 2081 */
2082 mv643xx_eth_stop(dev);
2083 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 2084 dev_printk(KERN_ERR, &dev->dev,
2085 "fatal error on re-opening device after "
2086 "MTU change\n");
c9df406f
LB		 2087 }
2088
2089 return 0;
1da177e4
LT		 2090}
2091
fc32b0e2 2092static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2093{
fc32b0e2 2094 struct mv643xx_eth_private *mp;
1da177e4 2095
fc32b0e2
LB		 2096 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2097 if (netif_running(mp->dev)) {
2098 netif_stop_queue(mp->dev);
c9df406f 2099
fc32b0e2
LB		 2100 port_reset(mp);
2101 port_start(mp);
c9df406f 2102
3d6b35bc 2103 __txq_maybe_wake(mp->txq + mp->txq_primary);
fc32b0e2 2104 }
c9df406f
LB		 2105}
2106
c9df406f 2107static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2108{
e5371493 2109 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2110
fc32b0e2 2111 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 2112
c9df406f 2113 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2114}
2115
c9df406f 2116#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2117static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2118{
fc32b0e2 2119 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2120
fc32b0e2
LB		 2121 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2122 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2123
fc32b0e2 2124 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2125
f2ca60f2 2126 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
9f8dd319 2127}
c9df406f 2128#endif
9f8dd319 2129
fc32b0e2 2130static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 2131{
e5371493 2132 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 2133 int val;
2134
fc32b0e2
LB		 2135 smi_reg_read(mp, addr, reg, &val);
2136
c9df406f 2137 return val;
9f8dd319
DF		 2138}
2139
fc32b0e2 2140static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 2141{
e5371493 2142 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 2143 smi_reg_write(mp, addr, reg, val);
c9df406f 2144}
9f8dd319 2145
9f8dd319 2146
c9df406f 2147/* platform glue ************************************************************/
e5371493
LB		 2148static void
2149mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2150 struct mbus_dram_target_info *dram)
c9df406f 2151{
cc9754b3 2152 void __iomem *base = msp->base;
c9df406f
LB		 2153 u32 win_enable;
2154 u32 win_protect;
2155 int i;
9f8dd319 2156
c9df406f
LB		 2157 for (i = 0; i < 6; i++) {
2158 writel(0, base + WINDOW_BASE(i));
2159 writel(0, base + WINDOW_SIZE(i));
2160 if (i < 4)
2161 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2162 }
2163
c9df406f
LB		 2164 win_enable = 0x3f;
2165 win_protect = 0;
2166
2167 for (i = 0; i < dram->num_cs; i++) {
2168 struct mbus_dram_window *cs = dram->cs + i;
2169
2170 writel((cs->base & 0xffff0000) |
2171 (cs->mbus_attr << 8) |
2172 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2173 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2174
2175 win_enable &= ~(1 << i);
2176 win_protect |= 3 << (2 * i);
2177 }
2178
2179 writel(win_enable, base + WINDOW_BAR_ENABLE);
2180 msp->win_protect = win_protect;
9f8dd319
DF		 2181}
2182
773fc3ee
LB		 2183static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2184{
2185 /*
2186 * Check whether we have a 14-bit coal limit field in bits
2187 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2188 * SDMA config register.
2189 */
2190 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2191 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2192 msp->extended_rx_coal_limit = 1;
2193 else
2194 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2195
2196 /*
2197 * Check whether the TX rate control registers are in the
2198 * old or the new place.
2199 */
2200 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2201 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2202 msp->tx_bw_control_moved = 1;
2203 else
2204 msp->tx_bw_control_moved = 0;
773fc3ee
LB		 2205}
2206
c9df406f 2207static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2208{
e5371493 2209 static int mv643xx_eth_version_printed = 0;
c9df406f 2210 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2211 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 2212 struct resource *res;
2213 int ret;
9f8dd319 2214
e5371493 2215 if (!mv643xx_eth_version_printed++)
7dde154d
LB		 2216 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2217 "driver version %s\n", mv643xx_eth_driver_version);
9f8dd319 2218
c9df406f
LB		 2219 ret = -EINVAL;
2220 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2221 if (res == NULL)
2222 goto out;
9f8dd319 2223
c9df406f
LB		 2224 ret = -ENOMEM;
2225 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2226 if (msp == NULL)
2227 goto out;
2228 memset(msp, 0, sizeof(*msp));
2229
cc9754b3
LB		 2230 msp->base = ioremap(res->start, res->end - res->start + 1);
2231 if (msp->base == NULL)
c9df406f
LB		 2232 goto out_free;
2233
2234 spin_lock_init(&msp->phy_lock);
c9df406f
LB		 2235
2236 /*
2237 * (Re-)program MBUS remapping windows if we are asked to.
2238 */
2239 if (pd != NULL && pd->dram != NULL)
2240 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2241
fc32b0e2
LB		 2242 /*
2243 * Detect hardware parameters.
2244 */
2245 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
773fc3ee 2246 infer_hw_params(msp);
fc32b0e2
LB		 2247
2248 platform_set_drvdata(pdev, msp);
2249
c9df406f
LB		 2250 return 0;
2251
2252out_free:
2253 kfree(msp);
2254out:
2255 return ret;
2256}
2257
2258static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2259{
e5371493 2260 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 2261
cc9754b3 2262 iounmap(msp->base);
c9df406f
LB		 2263 kfree(msp);
2264
2265 return 0;
9f8dd319
DF		 2266}
2267
c9df406f 2268static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2269 .probe = mv643xx_eth_shared_probe,
2270 .remove = mv643xx_eth_shared_remove,
c9df406f 2271 .driver = {
fc32b0e2 2272 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2273 .owner = THIS_MODULE,
2274 },
2275};
2276
e5371493 2277static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2278{
c9df406f 2279 int addr_shift = 5 * mp->port_num;
fc32b0e2 2280 u32 data;
1da177e4 2281
fc32b0e2
LB		 2282 data = rdl(mp, PHY_ADDR);
2283 data &= ~(0x1f << addr_shift);
2284 data |= (phy_addr & 0x1f) << addr_shift;
2285 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2286}
2287
e5371493 2288static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2289{
fc32b0e2
LB		 2290 unsigned int data;
2291
2292 data = rdl(mp, PHY_ADDR);
2293
2294 return (data >> (5 * mp->port_num)) & 0x1f;
2295}
2296
2297static void set_params(struct mv643xx_eth_private *mp,
2298 struct mv643xx_eth_platform_data *pd)
2299{
2300 struct net_device *dev = mp->dev;
2301
2302 if (is_valid_ether_addr(pd->mac_addr))
2303 memcpy(dev->dev_addr, pd->mac_addr, 6);
2304 else
2305 uc_addr_get(mp, dev->dev_addr);
2306
2307 if (pd->phy_addr == -1) {
2308 mp->shared_smi = NULL;
2309 mp->phy_addr = -1;
2310 } else {
2311 mp->shared_smi = mp->shared;
2312 if (pd->shared_smi != NULL)
2313 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2314
2315 if (pd->force_phy_addr || pd->phy_addr) {
2316 mp->phy_addr = pd->phy_addr & 0x3f;
2317 phy_addr_set(mp, mp->phy_addr);
2318 } else {
2319 mp->phy_addr = phy_addr_get(mp);
2320 }
2321 }
1da177e4 2322
fc32b0e2
LB		 2323 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2324 if (pd->rx_queue_size)
2325 mp->default_rx_ring_size = pd->rx_queue_size;
2326 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2327 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2328
64da80a2
LB		 2329 if (pd->rx_queue_mask)
2330 mp->rxq_mask = pd->rx_queue_mask;
2331 else
2332 mp->rxq_mask = 0x01;
2333 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2334
fc32b0e2
LB		 2335 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2336 if (pd->tx_queue_size)
2337 mp->default_tx_ring_size = pd->tx_queue_size;
2338 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2339 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc
LB		 2340
2341 if (pd->tx_queue_mask)
2342 mp->txq_mask = pd->tx_queue_mask;
2343 else
2344 mp->txq_mask = 0x01;
2345 mp->txq_primary = fls(mp->txq_mask) - 1;
1da177e4
LT		 2346}
2347
e5371493 2348static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 2349{
fc32b0e2
LB		 2350 unsigned int data;
2351 unsigned int data2;
2352
7f106c1d
LB		 2353 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
2354 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE);
1da177e4 2355
7f106c1d
LB		 2356 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data2);
2357 if (((data ^ data2) & BMCR_ANENABLE) == 0)
fc32b0e2 2358 return -ENODEV;
1da177e4 2359
7f106c1d 2360 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1da177e4 2361
c9df406f 2362 return 0;
1da177e4
LT		 2363}
2364
fc32b0e2
LB		 2365static int phy_init(struct mv643xx_eth_private *mp,
2366 struct mv643xx_eth_platform_data *pd)
c28a4f89 2367{
fc32b0e2
LB		 2368 struct ethtool_cmd cmd;
2369 int err;
c28a4f89 2370
fc32b0e2
LB		 2371 err = phy_detect(mp);
2372 if (err) {
2373 dev_printk(KERN_INFO, &mp->dev->dev,
2374 "no PHY detected at addr %d\n", mp->phy_addr);
2375 return err;
2376 }
2377 phy_reset(mp);
2378
2379 mp->mii.phy_id = mp->phy_addr;
2380 mp->mii.phy_id_mask = 0x3f;
2381 mp->mii.reg_num_mask = 0x1f;
2382 mp->mii.dev = mp->dev;
2383 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2384 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2385
fc32b0e2 2386 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2387
fc32b0e2
LB		 2388 memset(&cmd, 0, sizeof(cmd));
2389
2390 cmd.port = PORT_MII;
2391 cmd.transceiver = XCVR_INTERNAL;
2392 cmd.phy_address = mp->phy_addr;
2393 if (pd->speed == 0) {
2394 cmd.autoneg = AUTONEG_ENABLE;
2395 cmd.speed = SPEED_100;
2396 cmd.advertising = ADVERTISED_10baseT_Half |
2397 ADVERTISED_10baseT_Full |
2398 ADVERTISED_100baseT_Half |
2399 ADVERTISED_100baseT_Full;
c9df406f 2400 if (mp->mii.supports_gmii)
fc32b0e2 2401 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2402 } else {
fc32b0e2
LB		 2403 cmd.autoneg = AUTONEG_DISABLE;
2404 cmd.speed = pd->speed;
2405 cmd.duplex = pd->duplex;
c9df406f 2406 }
fc32b0e2 2407
fc32b0e2
LB		 2408 mv643xx_eth_set_settings(mp->dev, &cmd);
2409
2410 return 0;
c28a4f89
JC		 2411}
2412
81600eea
LB		 2413static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2414{
2415 u32 pscr;
2416
2417 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2418 if (pscr & SERIAL_PORT_ENABLE) {
2419 pscr &= ~SERIAL_PORT_ENABLE;
2420 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2421 }
2422
2423 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2424 if (mp->phy_addr == -1) {
2425 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2426 if (speed == SPEED_1000)
2427 pscr |= SET_GMII_SPEED_TO_1000;
2428 else if (speed == SPEED_100)
2429 pscr |= SET_MII_SPEED_TO_100;
2430
2431 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2432
2433 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2434 if (duplex == DUPLEX_FULL)
2435 pscr |= SET_FULL_DUPLEX_MODE;
2436 }
2437
2438 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2439}
2440
c9df406f 2441static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2442{
c9df406f 2443 struct mv643xx_eth_platform_data *pd;
e5371493 2444 struct mv643xx_eth_private *mp;
c9df406f 2445 struct net_device *dev;
c9df406f 2446 struct resource *res;
c9df406f 2447 DECLARE_MAC_BUF(mac);
fc32b0e2 2448 int err;
1da177e4 2449
c9df406f
LB		 2450 pd = pdev->dev.platform_data;
2451 if (pd == NULL) {
fc32b0e2
LB		 2452 dev_printk(KERN_ERR, &pdev->dev,
2453 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2454 return -ENODEV;
2455 }
1da177e4 2456
c9df406f 2457 if (pd->shared == NULL) {
fc32b0e2
LB		 2458 dev_printk(KERN_ERR, &pdev->dev,
2459 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2460 return -ENODEV;
2461 }
8f518703 2462
e5371493 2463 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2464 if (!dev)
2465 return -ENOMEM;
1da177e4 2466
c9df406f 2467 mp = netdev_priv(dev);
fc32b0e2
LB		 2468 platform_set_drvdata(pdev, mp);
2469
2470 mp->shared = platform_get_drvdata(pd->shared);
2471 mp->port_num = pd->port_number;
2472
c9df406f 2473 mp->dev = dev;
e5371493
LB		 2474#ifdef MV643XX_ETH_NAPI
2475 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2476#endif
1da177e4 2477
fc32b0e2
LB		 2478 set_params(mp, pd);
2479
2480 spin_lock_init(&mp->lock);
2481
2482 mib_counters_clear(mp);
2483 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2484
bedfe324
LB		 2485 if (mp->phy_addr != -1) {
2486 err = phy_init(mp, pd);
2487 if (err)
2488 goto out;
2489
2490 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2491 } else {
2492 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2493 }
81600eea 2494 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2
LB		 2495
2496
c9df406f
LB		 2497 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2498 BUG_ON(!res);
2499 dev->irq = res->start;
1da177e4 2500
fc32b0e2 2501 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2502 dev->open = mv643xx_eth_open;
2503 dev->stop = mv643xx_eth_stop;
c9df406f 2504 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2505 dev->set_mac_address = mv643xx_eth_set_mac_address;
2506 dev->do_ioctl = mv643xx_eth_ioctl;
2507 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2508 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2509#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2510 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2511#endif
c9df406f
LB		 2512 dev->watchdog_timeo = 2 * HZ;
2513 dev->base_addr = 0;
1da177e4 2514
e5371493 2515#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
b4de9051 2516 /*
c9df406f
LB		 2517 * Zero copy can only work if we use Discovery II memory. Else, we will
2518 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2519 */
c9df406f 2520 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
c9df406f 2521#endif
1da177e4 2522
fc32b0e2 2523 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2524
c9df406f 2525 if (mp->shared->win_protect)
fc32b0e2 2526 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2527
c9df406f
LB		 2528 err = register_netdev(dev);
2529 if (err)
2530 goto out;
1da177e4 2531
fc32b0e2
LB		 2532 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2533 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2534
c9df406f 2535 if (dev->features & NETIF_F_SG)
fc32b0e2 2536 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
1da177e4 2537
c9df406f 2538 if (dev->features & NETIF_F_IP_CSUM)
fc32b0e2 2539 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
1da177e4 2540
e5371493 2541#ifdef MV643XX_ETH_NAPI
fc32b0e2 2542 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
c9df406f 2543#endif
1da177e4 2544
13d64285 2545 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2546 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2547
c9df406f 2548 return 0;
1da177e4 2549
c9df406f
LB		 2550out:
2551 free_netdev(dev);
1da177e4 2552
c9df406f 2553 return err;
1da177e4
LT		 2554}
2555
c9df406f 2556static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2557{
fc32b0e2 2558 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2559
fc32b0e2 2560 unregister_netdev(mp->dev);
c9df406f 2561 flush_scheduled_work();
fc32b0e2 2562 free_netdev(mp->dev);
c9df406f 2563
c9df406f 2564 platform_set_drvdata(pdev, NULL);
fc32b0e2 2565
c9df406f 2566 return 0;
1da177e4
LT		 2567}
2568
c9df406f 2569static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2570{
fc32b0e2 2571 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2572
c9df406f 2573 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2574 wrl(mp, INT_MASK(mp->port_num), 0);
2575 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2576
fc32b0e2
LB		 2577 if (netif_running(mp->dev))
2578 port_reset(mp);
d0412d96
JC		 2579}
2580
c9df406f 2581static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2582 .probe = mv643xx_eth_probe,
2583 .remove = mv643xx_eth_remove,
2584 .shutdown = mv643xx_eth_shutdown,
c9df406f 2585 .driver = {
fc32b0e2 2586 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2587 .owner = THIS_MODULE,
2588 },
2589};
2590
e5371493 2591static int __init mv643xx_eth_init_module(void)
d0412d96 2592{
c9df406f 2593 int rc;
d0412d96 2594
c9df406f
LB		 2595 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2596 if (!rc) {
2597 rc = platform_driver_register(&mv643xx_eth_driver);
2598 if (rc)
2599 platform_driver_unregister(&mv643xx_eth_shared_driver);
2600 }
fc32b0e2 2601
c9df406f 2602 return rc;
d0412d96 2603}
fc32b0e2 2604module_init(mv643xx_eth_init_module);
d0412d96 2605
e5371493 2606static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2607{
c9df406f
LB		 2608 platform_driver_unregister(&mv643xx_eth_driver);
2609 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2610}
e5371493 2611module_exit(mv643xx_eth_cleanup_module);
1da177e4 2612
45675bc6
LB		 2613MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2614 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 2615MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2616MODULE_LICENSE("GPL");
c9df406f 2617MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2618MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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