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[PATCH] mv643xx: Disable per port bandwidth limits
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
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1da177e4
LT		 1/*
2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
7 *
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani (lachwani@pmc-sierra.com)
10 *
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
12 *
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
15 *
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 */
33#include <linux/init.h>
34#include <linux/dma-mapping.h>
35#include <linux/tcp.h>
36#include <linux/udp.h>
37#include <linux/etherdevice.h>
38
39#include <linux/bitops.h>
40#include <linux/delay.h>
41#include <linux/ethtool.h>
42#include <asm/io.h>
43#include <asm/types.h>
44#include <asm/pgtable.h>
45#include <asm/system.h>
46#include <asm/delay.h>
47#include "mv643xx_eth.h"
48
49/*
50 * The first part is the high level driver of the gigE ethernet ports.
51 */
52
53/* Constants */
54#define VLAN_HLEN 4
55#define FCS_LEN 4
56#define WRAP NET_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
57#define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
58
59#define INT_CAUSE_UNMASK_ALL 0x0007ffff
60#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
61#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
62#define INT_CAUSE_MASK_ALL 0x00000000
63#define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
64#define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
65#endif
66
67#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
68#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
69#else
70#define MAX_DESCS_PER_SKB 1
71#endif
72
73#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
74#define PHY_WAIT_MICRO_SECONDS 10
75
76/* Static function declarations */
77static int eth_port_link_is_up(unsigned int eth_port_num);
78static void eth_port_uc_addr_get(struct net_device *dev,
79 unsigned char *MacAddr);
80static int mv643xx_eth_real_open(struct net_device *);
81static int mv643xx_eth_real_stop(struct net_device *);
82static int mv643xx_eth_change_mtu(struct net_device *, int);
83static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
84static void eth_port_init_mac_tables(unsigned int eth_port_num);
85#ifdef MV643XX_NAPI
86static int mv643xx_poll(struct net_device *dev, int *budget);
87#endif
88static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
89static int ethernet_phy_detect(unsigned int eth_port_num);
90static struct ethtool_ops mv643xx_ethtool_ops;
91
92static char mv643xx_driver_name[] = "mv643xx_eth";
93static char mv643xx_driver_version[] = "1.0";
94
95static void __iomem *mv643xx_eth_shared_base;
96
97/* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
98static spinlock_t mv643xx_eth_phy_lock = SPIN_LOCK_UNLOCKED;
99
100static inline u32 mv_read(int offset)
101{
dc074a8a 102 void __iomem *reg_base;
1da177e4
LT		 103
104 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
105
106 return readl(reg_base + offset);
107}
108
109static inline void mv_write(int offset, u32 data)
110{
dc074a8a 111 void __iomem *reg_base;
1da177e4
LT		 112
113 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
114 writel(data, reg_base + offset);
115}
116
117/*
118 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
119 *
120 * Input : pointer to ethernet interface network device structure
121 * new mtu size
122 * Output : 0 upon success, -EINVAL upon failure
123 */
124static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
125{
126 struct mv643xx_private *mp = netdev_priv(dev);
127 unsigned long flags;
128
129 spin_lock_irqsave(&mp->lock, flags);
130
131 if ((new_mtu > 9500) || (new_mtu < 64)) {
132 spin_unlock_irqrestore(&mp->lock, flags);
133 return -EINVAL;
134 }
135
136 dev->mtu = new_mtu;
137 /*
138 * Stop then re-open the interface. This will allocate RX skb's with
139 * the new MTU.
140 * There is a possible danger that the open will not successed, due
141 * to memory is full, which might fail the open function.
142 */
143 if (netif_running(dev)) {
144 if (mv643xx_eth_real_stop(dev))
145 printk(KERN_ERR
146 "%s: Fatal error on stopping device\n",
147 dev->name);
148 if (mv643xx_eth_real_open(dev))
149 printk(KERN_ERR
150 "%s: Fatal error on opening device\n",
151 dev->name);
152 }
153
154 spin_unlock_irqrestore(&mp->lock, flags);
155 return 0;
156}
157
158/*
159 * mv643xx_eth_rx_task
160 *
161 * Fills / refills RX queue on a certain gigabit ethernet port
162 *
163 * Input : pointer to ethernet interface network device structure
164 * Output : N/A
165 */
166static void mv643xx_eth_rx_task(void *data)
167{
168 struct net_device *dev = (struct net_device *)data;
169 struct mv643xx_private *mp = netdev_priv(dev);
170 struct pkt_info pkt_info;
171 struct sk_buff *skb;
172
173 if (test_and_set_bit(0, &mp->rx_task_busy))
174 panic("%s: Error in test_set_bit / clear_bit", dev->name);
175
176 while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
177 skb = dev_alloc_skb(RX_SKB_SIZE);
178 if (!skb)
179 break;
180 mp->rx_ring_skbs++;
181 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
182 pkt_info.byte_cnt = RX_SKB_SIZE;
183 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
184 DMA_FROM_DEVICE);
185 pkt_info.return_info = skb;
186 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
187 printk(KERN_ERR
188 "%s: Error allocating RX Ring\n", dev->name);
189 break;
190 }
191 skb_reserve(skb, 2);
192 }
193 clear_bit(0, &mp->rx_task_busy);
194 /*
195 * If RX ring is empty of SKB, set a timer to try allocating
196 * again in a later time .
197 */
198 if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
199 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
200 /* After 100mSec */
201 mp->timeout.expires = jiffies + (HZ / 10);
202 add_timer(&mp->timeout);
203 mp->rx_timer_flag = 1;
204 }
205#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
206 else {
207 /* Return interrupts */
208 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
209 INT_CAUSE_UNMASK_ALL);
210 }
211#endif
212}
213
214/*
215 * mv643xx_eth_rx_task_timer_wrapper
216 *
217 * Timer routine to wake up RX queue filling task. This function is
218 * used only in case the RX queue is empty, and all alloc_skb has
219 * failed (due to out of memory event).
220 *
221 * Input : pointer to ethernet interface network device structure
222 * Output : N/A
223 */
224static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
225{
226 struct net_device *dev = (struct net_device *)data;
227 struct mv643xx_private *mp = netdev_priv(dev);
228
229 mp->rx_timer_flag = 0;
230 mv643xx_eth_rx_task((void *)data);
231}
232
233/*
234 * mv643xx_eth_update_mac_address
235 *
236 * Update the MAC address of the port in the address table
237 *
238 * Input : pointer to ethernet interface network device structure
239 * Output : N/A
240 */
241static void mv643xx_eth_update_mac_address(struct net_device *dev)
242{
243 struct mv643xx_private *mp = netdev_priv(dev);
244 unsigned int port_num = mp->port_num;
245
246 eth_port_init_mac_tables(port_num);
247 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
248 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
249}
250
251/*
252 * mv643xx_eth_set_rx_mode
253 *
254 * Change from promiscuos to regular rx mode
255 *
256 * Input : pointer to ethernet interface network device structure
257 * Output : N/A
258 */
259static void mv643xx_eth_set_rx_mode(struct net_device *dev)
260{
261 struct mv643xx_private *mp = netdev_priv(dev);
262 u32 config_reg;
263
264 config_reg = ethernet_get_config_reg(mp->port_num);
265 if (dev->flags & IFF_PROMISC)
266 config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
267 else
268 config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
269 ethernet_set_config_reg(mp->port_num, config_reg);
270}
271
272/*
273 * mv643xx_eth_set_mac_address
274 *
275 * Change the interface's mac address.
276 * No special hardware thing should be done because interface is always
277 * put in promiscuous mode.
278 *
279 * Input : pointer to ethernet interface network device structure and
280 * a pointer to the designated entry to be added to the cache.
281 * Output : zero upon success, negative upon failure
282 */
283static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
284{
285 int i;
286
287 for (i = 0; i < 6; i++)
288 /* +2 is for the offset of the HW addr type */
289 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
290 mv643xx_eth_update_mac_address(dev);
291 return 0;
292}
293
294/*
295 * mv643xx_eth_tx_timeout
296 *
297 * Called upon a timeout on transmitting a packet
298 *
299 * Input : pointer to ethernet interface network device structure.
300 * Output : N/A
301 */
302static void mv643xx_eth_tx_timeout(struct net_device *dev)
303{
304 struct mv643xx_private *mp = netdev_priv(dev);
305
306 printk(KERN_INFO "%s: TX timeout ", dev->name);
307
308 /* Do the reset outside of interrupt context */
309 schedule_work(&mp->tx_timeout_task);
310}
311
312/*
313 * mv643xx_eth_tx_timeout_task
314 *
315 * Actual routine to reset the adapter when a timeout on Tx has occurred
316 */
317static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
318{
319 struct mv643xx_private *mp = netdev_priv(dev);
320
321 netif_device_detach(dev);
322 eth_port_reset(mp->port_num);
323 eth_port_start(mp);
324 netif_device_attach(dev);
325}
326
327/*
328 * mv643xx_eth_free_tx_queue
329 *
330 * Input : dev - a pointer to the required interface
331 *
332 * Output : 0 if was able to release skb , nonzero otherwise
333 */
334static int mv643xx_eth_free_tx_queue(struct net_device *dev,
335 unsigned int eth_int_cause_ext)
336{
337 struct mv643xx_private *mp = netdev_priv(dev);
338 struct net_device_stats *stats = &mp->stats;
339 struct pkt_info pkt_info;
340 int released = 1;
341
342 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
343 return released;
344
345 spin_lock(&mp->lock);
346
347 /* Check only queue 0 */
348 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
349 if (pkt_info.cmd_sts & BIT0) {
350 printk("%s: Error in TX\n", dev->name);
351 stats->tx_errors++;
352 }
353
354 /*
355 * If return_info is different than 0, release the skb.
356 * The case where return_info is not 0 is only in case
357 * when transmitted a scatter/gather packet, where only
358 * last skb releases the whole chain.
359 */
360 if (pkt_info.return_info) {
361 if (skb_shinfo(pkt_info.return_info)->nr_frags)
362 dma_unmap_page(NULL, pkt_info.buf_ptr,
363 pkt_info.byte_cnt,
364 DMA_TO_DEVICE);
365 else
366 dma_unmap_single(NULL, pkt_info.buf_ptr,
367 pkt_info.byte_cnt,
368 DMA_TO_DEVICE);
369
370 dev_kfree_skb_irq(pkt_info.return_info);
371 released = 0;
1da177e4
LT		 372 } else
373 dma_unmap_page(NULL, pkt_info.buf_ptr,
374 pkt_info.byte_cnt, DMA_TO_DEVICE);
375 }
376
377 spin_unlock(&mp->lock);
378
379 return released;
380}
381
382/*
383 * mv643xx_eth_receive
384 *
385 * This function is forward packets that are received from the port's
386 * queues toward kernel core or FastRoute them to another interface.
387 *
388 * Input : dev - a pointer to the required interface
389 * max - maximum number to receive (0 means unlimted)
390 *
391 * Output : number of served packets
392 */
393#ifdef MV643XX_NAPI
394static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
395#else
396static int mv643xx_eth_receive_queue(struct net_device *dev)
397#endif
398{
399 struct mv643xx_private *mp = netdev_priv(dev);
400 struct net_device_stats *stats = &mp->stats;
401 unsigned int received_packets = 0;
402 struct sk_buff *skb;
403 struct pkt_info pkt_info;
404
405#ifdef MV643XX_NAPI
b1dd9ca1 406 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
1da177e4
LT		 407#else
408 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
409#endif
410 mp->rx_ring_skbs--;
411 received_packets++;
b1dd9ca1 412
1da177e4
LT		 413 /* Update statistics. Note byte count includes 4 byte CRC count */
414 stats->rx_packets++;
415 stats->rx_bytes += pkt_info.byte_cnt;
416 skb = pkt_info.return_info;
417 /*
418 * In case received a packet without first / last bits on OR
419 * the error summary bit is on, the packets needs to be dropeed.
420 */
421 if (((pkt_info.cmd_sts
422 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
423 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
424 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
425 stats->rx_dropped++;
426 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
427 ETH_RX_LAST_DESC)) !=
428 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
429 if (net_ratelimit())
430 printk(KERN_ERR
431 "%s: Received packet spread "
432 "on multiple descriptors\n",
433 dev->name);
434 }
435 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
436 stats->rx_errors++;
437
438 dev_kfree_skb_irq(skb);
439 } else {
440 /*
441 * The -4 is for the CRC in the trailer of the
442 * received packet
443 */
444 skb_put(skb, pkt_info.byte_cnt - 4);
445 skb->dev = dev;
446
447 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
448 skb->ip_summed = CHECKSUM_UNNECESSARY;
449 skb->csum = htons(
450 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
451 }
452 skb->protocol = eth_type_trans(skb, dev);
453#ifdef MV643XX_NAPI
454 netif_receive_skb(skb);
455#else
456 netif_rx(skb);
457#endif
458 }
459 }
460
461 return received_packets;
462}
463
464/*
465 * mv643xx_eth_int_handler
466 *
467 * Main interrupt handler for the gigbit ethernet ports
468 *
469 * Input : irq - irq number (not used)
470 * dev_id - a pointer to the required interface's data structure
471 * regs - not used
472 * Output : N/A
473 */
474
475static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
476 struct pt_regs *regs)
477{
478 struct net_device *dev = (struct net_device *)dev_id;
479 struct mv643xx_private *mp = netdev_priv(dev);
480 u32 eth_int_cause, eth_int_cause_ext = 0;
481 unsigned int port_num = mp->port_num;
482
483 /* Read interrupt cause registers */
484 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
485 INT_CAUSE_UNMASK_ALL;
486
487 if (eth_int_cause & BIT1)
488 eth_int_cause_ext = mv_read(
489 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
490 INT_CAUSE_UNMASK_ALL_EXT;
491
492#ifdef MV643XX_NAPI
493 if (!(eth_int_cause & 0x0007fffd)) {
494 /* Dont ack the Rx interrupt */
495#endif
496 /*
497 * Clear specific ethernet port intrerrupt registers by
498 * acknowleding relevant bits.
499 */
500 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
501 ~eth_int_cause);
502 if (eth_int_cause_ext != 0x0)
503 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
504 (port_num), ~eth_int_cause_ext);
505
506 /* UDP change : We may need this */
507 if ((eth_int_cause_ext & 0x0000ffff) &&
508 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
509 (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
510 netif_wake_queue(dev);
511#ifdef MV643XX_NAPI
512 } else {
513 if (netif_rx_schedule_prep(dev)) {
514 /* Mask all the interrupts */
515 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
516 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
517 (port_num), 0);
518 __netif_rx_schedule(dev);
519 }
520#else
521 if (eth_int_cause & (BIT2 | BIT11))
522 mv643xx_eth_receive_queue(dev, 0);
523
524 /*
525 * After forwarded received packets to upper layer, add a task
526 * in an interrupts enabled context that refills the RX ring
527 * with skb's.
528 */
529#ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
530 /* Unmask all interrupts on ethernet port */
531 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
532 INT_CAUSE_MASK_ALL);
533 queue_task(&mp->rx_task, &tq_immediate);
534 mark_bh(IMMEDIATE_BH);
535#else
536 mp->rx_task.func(dev);
537#endif
538#endif
539 }
540 /* PHY status changed */
541 if (eth_int_cause_ext & (BIT16 | BIT20)) {
542 if (eth_port_link_is_up(port_num)) {
543 netif_carrier_on(dev);
544 netif_wake_queue(dev);
545 /* Start TX queue */
546 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
547 (port_num), 1);
548 } else {
549 netif_carrier_off(dev);
550 netif_stop_queue(dev);
551 }
552 }
553
554 /*
555 * If no real interrupt occured, exit.
556 * This can happen when using gigE interrupt coalescing mechanism.
557 */
558 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
559 return IRQ_NONE;
560
561 return IRQ_HANDLED;
562}
563
564#ifdef MV643XX_COAL
565
566/*
567 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
568 *
569 * DESCRIPTION:
570 * This routine sets the RX coalescing interrupt mechanism parameter.
571 * This parameter is a timeout counter, that counts in 64 t_clk
572 * chunks ; that when timeout event occurs a maskable interrupt
573 * occurs.
574 * The parameter is calculated using the tClk of the MV-643xx chip
575 * , and the required delay of the interrupt in usec.
576 *
577 * INPUT:
578 * unsigned int eth_port_num Ethernet port number
579 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
580 * unsigned int delay Delay in usec
581 *
582 * OUTPUT:
583 * Interrupt coalescing mechanism value is set in MV-643xx chip.
584 *
585 * RETURN:
586 * The interrupt coalescing value set in the gigE port.
587 *
588 */
589static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
590 unsigned int t_clk, unsigned int delay)
591{
592 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
593
594 /* Set RX Coalescing mechanism */
595 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
596 ((coal & 0x3fff) << 8) |
597 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
598 & 0xffc000ff));
599
600 return coal;
601}
602#endif
603
604/*
605 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
606 *
607 * DESCRIPTION:
608 * This routine sets the TX coalescing interrupt mechanism parameter.
609 * This parameter is a timeout counter, that counts in 64 t_clk
610 * chunks ; that when timeout event occurs a maskable interrupt
611 * occurs.
612 * The parameter is calculated using the t_cLK frequency of the
613 * MV-643xx chip and the required delay in the interrupt in uSec
614 *
615 * INPUT:
616 * unsigned int eth_port_num Ethernet port number
617 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
618 * unsigned int delay Delay in uSeconds
619 *
620 * OUTPUT:
621 * Interrupt coalescing mechanism value is set in MV-643xx chip.
622 *
623 * RETURN:
624 * The interrupt coalescing value set in the gigE port.
625 *
626 */
627static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
628 unsigned int t_clk, unsigned int delay)
629{
630 unsigned int coal;
631 coal = ((t_clk / 1000000) * delay) / 64;
632 /* Set TX Coalescing mechanism */
633 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
634 coal << 4);
635 return coal;
636}
637
638/*
639 * mv643xx_eth_open
640 *
641 * This function is called when openning the network device. The function
642 * should initialize all the hardware, initialize cyclic Rx/Tx
643 * descriptors chain and buffers and allocate an IRQ to the network
644 * device.
645 *
646 * Input : a pointer to the network device structure
647 *
648 * Output : zero of success , nonzero if fails.
649 */
650
651static int mv643xx_eth_open(struct net_device *dev)
652{
653 struct mv643xx_private *mp = netdev_priv(dev);
654 unsigned int port_num = mp->port_num;
655 int err;
656
657 spin_lock_irq(&mp->lock);
658
659 err = request_irq(dev->irq, mv643xx_eth_int_handler,
16b81757 660 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
1da177e4
LT		 661
662 if (err) {
663 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
664 port_num);
665 err = -EAGAIN;
666 goto out;
667 }
668
669 if (mv643xx_eth_real_open(dev)) {
670 printk("%s: Error opening interface\n", dev->name);
671 err = -EBUSY;
672 goto out_free;
673 }
674
675 spin_unlock_irq(&mp->lock);
676
677 return 0;
678
679out_free:
680 free_irq(dev->irq, dev);
681
682out:
683 spin_unlock_irq(&mp->lock);
684
685 return err;
686}
687
688/*
689 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
690 *
691 * DESCRIPTION:
692 * This function prepares a Rx chained list of descriptors and packet
693 * buffers in a form of a ring. The routine must be called after port
694 * initialization routine and before port start routine.
695 * The Ethernet SDMA engine uses CPU bus addresses to access the various
696 * devices in the system (i.e. DRAM). This function uses the ethernet
697 * struct 'virtual to physical' routine (set by the user) to set the ring
698 * with physical addresses.
699 *
700 * INPUT:
701 * struct mv643xx_private *mp Ethernet Port Control srtuct.
702 *
703 * OUTPUT:
704 * The routine updates the Ethernet port control struct with information
705 * regarding the Rx descriptors and buffers.
706 *
707 * RETURN:
708 * None.
709 */
710static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
711{
712 volatile struct eth_rx_desc *p_rx_desc;
713 int rx_desc_num = mp->rx_ring_size;
714 int i;
715
716 /* initialize the next_desc_ptr links in the Rx descriptors ring */
717 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
718 for (i = 0; i < rx_desc_num; i++) {
719 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
720 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
721 }
722
723 /* Save Rx desc pointer to driver struct. */
724 mp->rx_curr_desc_q = 0;
725 mp->rx_used_desc_q = 0;
726
727 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
728
729 /* Add the queue to the list of RX queues of this port */
730 mp->port_rx_queue_command |= 1;
731}
732
733/*
734 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
735 *
736 * DESCRIPTION:
737 * This function prepares a Tx chained list of descriptors and packet
738 * buffers in a form of a ring. The routine must be called after port
739 * initialization routine and before port start routine.
740 * The Ethernet SDMA engine uses CPU bus addresses to access the various
741 * devices in the system (i.e. DRAM). This function uses the ethernet
742 * struct 'virtual to physical' routine (set by the user) to set the ring
743 * with physical addresses.
744 *
745 * INPUT:
746 * struct mv643xx_private *mp Ethernet Port Control srtuct.
747 *
748 * OUTPUT:
749 * The routine updates the Ethernet port control struct with information
750 * regarding the Tx descriptors and buffers.
751 *
752 * RETURN:
753 * None.
754 */
755static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
756{
757 int tx_desc_num = mp->tx_ring_size;
758 struct eth_tx_desc *p_tx_desc;
759 int i;
760
761 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
762 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
763 for (i = 0; i < tx_desc_num; i++) {
764 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
765 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
766 }
767
768 mp->tx_curr_desc_q = 0;
769 mp->tx_used_desc_q = 0;
770#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
771 mp->tx_first_desc_q = 0;
772#endif
773
774 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
775
776 /* Add the queue to the list of Tx queues of this port */
777 mp->port_tx_queue_command |= 1;
778}
779
780/* Helper function for mv643xx_eth_open */
781static int mv643xx_eth_real_open(struct net_device *dev)
782{
783 struct mv643xx_private *mp = netdev_priv(dev);
784 unsigned int port_num = mp->port_num;
785 unsigned int size;
786
787 /* Stop RX Queues */
788 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
789
790 /* Clear the ethernet port interrupts */
791 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
792 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
793
794 /* Unmask RX buffer and TX end interrupt */
795 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
796 INT_CAUSE_UNMASK_ALL);
797
798 /* Unmask phy and link status changes interrupts */
799 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
800 INT_CAUSE_UNMASK_ALL_EXT);
801
802 /* Set the MAC Address */
803 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
804
805 eth_port_init(mp);
806
807 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
808
809 memset(&mp->timeout, 0, sizeof(struct timer_list));
810 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
811 mp->timeout.data = (unsigned long)dev;
812
813 mp->rx_task_busy = 0;
814 mp->rx_timer_flag = 0;
815
816 /* Allocate RX and TX skb rings */
817 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
818 GFP_KERNEL);
819 if (!mp->rx_skb) {
820 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
821 return -ENOMEM;
822 }
823 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
824 GFP_KERNEL);
825 if (!mp->tx_skb) {
826 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
827 kfree(mp->rx_skb);
828 return -ENOMEM;
829 }
830
831 /* Allocate TX ring */
832 mp->tx_ring_skbs = 0;
833 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
834 mp->tx_desc_area_size = size;
835
836 if (mp->tx_sram_size) {
837 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
838 mp->tx_sram_size);
839 mp->tx_desc_dma = mp->tx_sram_addr;
840 } else
841 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
842 &mp->tx_desc_dma,
843 GFP_KERNEL);
844
845 if (!mp->p_tx_desc_area) {
846 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
847 dev->name, size);
848 kfree(mp->rx_skb);
849 kfree(mp->tx_skb);
850 return -ENOMEM;
851 }
852 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
853 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
854
855 ether_init_tx_desc_ring(mp);
856
857 /* Allocate RX ring */
858 mp->rx_ring_skbs = 0;
859 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
860 mp->rx_desc_area_size = size;
861
862 if (mp->rx_sram_size) {
863 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
864 mp->rx_sram_size);
865 mp->rx_desc_dma = mp->rx_sram_addr;
866 } else
867 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
868 &mp->rx_desc_dma,
869 GFP_KERNEL);
870
871 if (!mp->p_rx_desc_area) {
872 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
873 dev->name, size);
874 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
875 dev->name);
876 if (mp->rx_sram_size)
877 iounmap(mp->p_rx_desc_area);
878 else
879 dma_free_coherent(NULL, mp->tx_desc_area_size,
880 mp->p_tx_desc_area, mp->tx_desc_dma);
881 kfree(mp->rx_skb);
882 kfree(mp->tx_skb);
883 return -ENOMEM;
884 }
885 memset((void *)mp->p_rx_desc_area, 0, size);
886
887 ether_init_rx_desc_ring(mp);
888
889 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
890
891 eth_port_start(mp);
892
893 /* Interrupt Coalescing */
894
895#ifdef MV643XX_COAL
896 mp->rx_int_coal =
897 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
898#endif
899
900 mp->tx_int_coal =
901 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
902
903 netif_start_queue(dev);
904
905 return 0;
906}
907
908static void mv643xx_eth_free_tx_rings(struct net_device *dev)
909{
910 struct mv643xx_private *mp = netdev_priv(dev);
911 unsigned int port_num = mp->port_num;
912 unsigned int curr;
913
914 /* Stop Tx Queues */
915 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
916
917 /* Free outstanding skb's on TX rings */
918 for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
919 if (mp->tx_skb[curr]) {
920 dev_kfree_skb(mp->tx_skb[curr]);
921 mp->tx_ring_skbs--;
922 }
923 }
924 if (mp->tx_ring_skbs)
925 printk("%s: Error on Tx descriptor free - could not free %d"
926 " descriptors\n", dev->name, mp->tx_ring_skbs);
927
928 /* Free TX ring */
929 if (mp->tx_sram_size)
930 iounmap(mp->p_tx_desc_area);
931 else
932 dma_free_coherent(NULL, mp->tx_desc_area_size,
933 mp->p_tx_desc_area, mp->tx_desc_dma);
934}
935
936static void mv643xx_eth_free_rx_rings(struct net_device *dev)
937{
938 struct mv643xx_private *mp = netdev_priv(dev);
939 unsigned int port_num = mp->port_num;
940 int curr;
941
942 /* Stop RX Queues */
943 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
944
945 /* Free preallocated skb's on RX rings */
946 for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
947 if (mp->rx_skb[curr]) {
948 dev_kfree_skb(mp->rx_skb[curr]);
949 mp->rx_ring_skbs--;
950 }
951 }
952
953 if (mp->rx_ring_skbs)
954 printk(KERN_ERR
955 "%s: Error in freeing Rx Ring. %d skb's still"
956 " stuck in RX Ring - ignoring them\n", dev->name,
957 mp->rx_ring_skbs);
958 /* Free RX ring */
959 if (mp->rx_sram_size)
960 iounmap(mp->p_rx_desc_area);
961 else
962 dma_free_coherent(NULL, mp->rx_desc_area_size,
963 mp->p_rx_desc_area, mp->rx_desc_dma);
964}
965
966/*
967 * mv643xx_eth_stop
968 *
969 * This function is used when closing the network device.
970 * It updates the hardware,
971 * release all memory that holds buffers and descriptors and release the IRQ.
972 * Input : a pointer to the device structure
973 * Output : zero if success , nonzero if fails
974 */
975
976/* Helper function for mv643xx_eth_stop */
977
978static int mv643xx_eth_real_stop(struct net_device *dev)
979{
980 struct mv643xx_private *mp = netdev_priv(dev);
981 unsigned int port_num = mp->port_num;
982
983 netif_carrier_off(dev);
984 netif_stop_queue(dev);
985
986 mv643xx_eth_free_tx_rings(dev);
987 mv643xx_eth_free_rx_rings(dev);
988
989 eth_port_reset(mp->port_num);
990
991 /* Disable ethernet port interrupts */
992 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
993 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
994
995 /* Mask RX buffer and TX end interrupt */
996 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
997
998 /* Mask phy and link status changes interrupts */
999 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
1000
1001 return 0;
1002}
1003
1004static int mv643xx_eth_stop(struct net_device *dev)
1005{
1006 struct mv643xx_private *mp = netdev_priv(dev);
1007
1008 spin_lock_irq(&mp->lock);
1009
1010 mv643xx_eth_real_stop(dev);
1011
1012 free_irq(dev->irq, dev);
1013 spin_unlock_irq(&mp->lock);
1014
1015 return 0;
1016}
1017
1018#ifdef MV643XX_NAPI
1019static void mv643xx_tx(struct net_device *dev)
1020{
1021 struct mv643xx_private *mp = netdev_priv(dev);
1022 struct pkt_info pkt_info;
1023
1024 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
1025 if (pkt_info.return_info) {
1026 if (skb_shinfo(pkt_info.return_info)->nr_frags)
1027 dma_unmap_page(NULL, pkt_info.buf_ptr,
1028 pkt_info.byte_cnt,
1029 DMA_TO_DEVICE);
1030 else
1031 dma_unmap_single(NULL, pkt_info.buf_ptr,
1032 pkt_info.byte_cnt,
1033 DMA_TO_DEVICE);
1034
1035 dev_kfree_skb_irq(pkt_info.return_info);
1da177e4
LT		 1036 } else
1037 dma_unmap_page(NULL, pkt_info.buf_ptr,
1038 pkt_info.byte_cnt, DMA_TO_DEVICE);
1039 }
1040
1041 if (netif_queue_stopped(dev) &&
1042 mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
1043 netif_wake_queue(dev);
1044}
1045
1046/*
1047 * mv643xx_poll
1048 *
1049 * This function is used in case of NAPI
1050 */
1051static int mv643xx_poll(struct net_device *dev, int *budget)
1052{
1053 struct mv643xx_private *mp = netdev_priv(dev);
1054 int done = 1, orig_budget, work_done;
1055 unsigned int port_num = mp->port_num;
1056 unsigned long flags;
1057
1058#ifdef MV643XX_TX_FAST_REFILL
1059 if (++mp->tx_clean_threshold > 5) {
1060 spin_lock_irqsave(&mp->lock, flags);
1061 mv643xx_tx(dev);
1062 mp->tx_clean_threshold = 0;
1063 spin_unlock_irqrestore(&mp->lock, flags);
1064 }
1065#endif
1066
1067 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1068 != (u32) mp->rx_used_desc_q) {
1069 orig_budget = *budget;
1070 if (orig_budget > dev->quota)
1071 orig_budget = dev->quota;
1072 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1073 mp->rx_task.func(dev);
1074 *budget -= work_done;
1075 dev->quota -= work_done;
1076 if (work_done >= orig_budget)
1077 done = 0;
1078 }
1079
1080 if (done) {
1081 spin_lock_irqsave(&mp->lock, flags);
1082 __netif_rx_complete(dev);
1083 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1084 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1085 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1086 INT_CAUSE_UNMASK_ALL);
1087 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1088 INT_CAUSE_UNMASK_ALL_EXT);
1089 spin_unlock_irqrestore(&mp->lock, flags);
1090 }
1091
1092 return done ? 0 : 1;
1093}
1094#endif
1095
1096/*
1097 * mv643xx_eth_start_xmit
1098 *
1099 * This function is queues a packet in the Tx descriptor for
1100 * required port.
1101 *
1102 * Input : skb - a pointer to socket buffer
1103 * dev - a pointer to the required port
1104 *
1105 * Output : zero upon success
1106 */
1107static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1108{
1109 struct mv643xx_private *mp = netdev_priv(dev);
1110 struct net_device_stats *stats = &mp->stats;
1111 ETH_FUNC_RET_STATUS status;
1112 unsigned long flags;
1113 struct pkt_info pkt_info;
1114
1115 if (netif_queue_stopped(dev)) {
1116 printk(KERN_ERR
1117 "%s: Tried sending packet when interface is stopped\n",
1118 dev->name);
1119 return 1;
1120 }
1121
1122 /* This is a hard error, log it. */
1123 if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
1124 (skb_shinfo(skb)->nr_frags + 1)) {
1125 netif_stop_queue(dev);
1126 printk(KERN_ERR
1127 "%s: Bug in mv643xx_eth - Trying to transmit when"
1128 " queue full !\n", dev->name);
1129 return 1;
1130 }
1131
1132 /* Paranoid check - this shouldn't happen */
1133 if (skb == NULL) {
1134 stats->tx_dropped++;
1135 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1136 return 1;
1137 }
1138
1139 spin_lock_irqsave(&mp->lock, flags);
1140
1141 /* Update packet info data structure -- DMA owned, first last */
1142#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1143 if (!skb_shinfo(skb)->nr_frags) {
1144linear:
1145 if (skb->ip_summed != CHECKSUM_HW) {
26006360 1146 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1da177e4 1147 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1148 ETH_TX_FIRST_DESC |
1149 ETH_TX_LAST_DESC |
1150 5 << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1151 pkt_info.l4i_chk = 0;
1152 } else {
1da177e4
LT		 1153
1154 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
26006360
DF		 1155 ETH_TX_FIRST_DESC |
1156 ETH_TX_LAST_DESC |
1157 ETH_GEN_TCP_UDP_CHECKSUM |
1158 ETH_GEN_IP_V_4_CHECKSUM |
1159 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1160 /* CPU already calculated pseudo header checksum. */
1161 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1162 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1163 pkt_info.l4i_chk = skb->h.uh->check;
1164 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1165 pkt_info.l4i_chk = skb->h.th->check;
1166 else {
1167 printk(KERN_ERR
1168 "%s: chksum proto != TCP or UDP\n",
1169 dev->name);
1170 spin_unlock_irqrestore(&mp->lock, flags);
1171 return 1;
1172 }
1173 }
1174 pkt_info.byte_cnt = skb->len;
1175 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1176 DMA_TO_DEVICE);
1177 pkt_info.return_info = skb;
1da177e4
LT		 1178 status = eth_port_send(mp, &pkt_info);
1179 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1180 printk(KERN_ERR "%s: Error on transmitting packet\n",
1181 dev->name);
1182 stats->tx_bytes += pkt_info.byte_cnt;
1183 } else {
1184 unsigned int frag;
1da177e4
LT		 1185
1186 /* Since hardware can't handle unaligned fragments smaller
1187 * than 9 bytes, if we find any, we linearize the skb
1188 * and start again. When I've seen it, it's always been
1189 * the first frag (probably near the end of the page),
1190 * but we check all frags to be safe.
1191 */
1192 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1193 skb_frag_t *fragp;
1194
1195 fragp = &skb_shinfo(skb)->frags[frag];
1196 if (fragp->size <= 8 && fragp->page_offset & 0x7) {
1197 skb_linearize(skb, GFP_ATOMIC);
1198 printk(KERN_DEBUG "%s: unaligned tiny fragment"
1199 "%d of %d, fixed\n",
1200 dev->name, frag,
1201 skb_shinfo(skb)->nr_frags);
1202 goto linear;
1203 }
1204 }
1205
1206 /* first frag which is skb header */
1207 pkt_info.byte_cnt = skb_headlen(skb);
1208 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1209 skb_headlen(skb),
1210 DMA_TO_DEVICE);
1211 pkt_info.l4i_chk = 0;
1212 pkt_info.return_info = 0;
1da177e4 1213
26006360
DF		 1214 if (skb->ip_summed != CHECKSUM_HW)
1215 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1216 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1217 5 << ETH_TX_IHL_SHIFT;
1218 else {
1219 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1220 ETH_GEN_TCP_UDP_CHECKSUM |
1221 ETH_GEN_IP_V_4_CHECKSUM |
1222 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1da177e4
LT		 1223 /* CPU already calculated pseudo header checksum. */
1224 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1225 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1226 pkt_info.l4i_chk = skb->h.uh->check;
1227 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1228 pkt_info.l4i_chk = skb->h.th->check;
1229 else {
1230 printk(KERN_ERR
1231 "%s: chksum proto != TCP or UDP\n",
1232 dev->name);
1233 spin_unlock_irqrestore(&mp->lock, flags);
1234 return 1;
1235 }
1236 }
1237
1238 status = eth_port_send(mp, &pkt_info);
1239 if (status != ETH_OK) {
1240 if ((status == ETH_ERROR))
1241 printk(KERN_ERR
1242 "%s: Error on transmitting packet\n",
1243 dev->name);
1244 if (status == ETH_QUEUE_FULL)
1245 printk("Error on Queue Full \n");
1246 if (status == ETH_QUEUE_LAST_RESOURCE)
1247 printk("Tx resource error \n");
1248 }
1249 stats->tx_bytes += pkt_info.byte_cnt;
1250
1251 /* Check for the remaining frags */
1252 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1253 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1254 pkt_info.l4i_chk = 0x0000;
1255 pkt_info.cmd_sts = 0x00000000;
1256
1257 /* Last Frag enables interrupt and frees the skb */
1258 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1259 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1260 ETH_TX_LAST_DESC;
1261 pkt_info.return_info = skb;
1da177e4
LT		 1262 } else {
1263 pkt_info.return_info = 0;
1264 }
1265 pkt_info.l4i_chk = 0;
1266 pkt_info.byte_cnt = this_frag->size;
1267
1268 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1269 this_frag->page_offset,
1270 this_frag->size,
1271 DMA_TO_DEVICE);
1272
1273 status = eth_port_send(mp, &pkt_info);
1274
1275 if (status != ETH_OK) {
1276 if ((status == ETH_ERROR))
1277 printk(KERN_ERR "%s: Error on "
1278 "transmitting packet\n",
1279 dev->name);
1280
1281 if (status == ETH_QUEUE_LAST_RESOURCE)
1282 printk("Tx resource error \n");
1283
1284 if (status == ETH_QUEUE_FULL)
1285 printk("Queue is full \n");
1286 }
1287 stats->tx_bytes += pkt_info.byte_cnt;
1288 }
1289 }
1290#else
1291 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1292 ETH_TX_LAST_DESC;
1293 pkt_info.l4i_chk = 0;
1294 pkt_info.byte_cnt = skb->len;
1295 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1296 DMA_TO_DEVICE);
1297 pkt_info.return_info = skb;
1da177e4
LT		 1298 status = eth_port_send(mp, &pkt_info);
1299 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1300 printk(KERN_ERR "%s: Error on transmitting packet\n",
1301 dev->name);
1302 stats->tx_bytes += pkt_info.byte_cnt;
1303#endif
1304
1305 /* Check if TX queue can handle another skb. If not, then
1306 * signal higher layers to stop requesting TX
1307 */
1308 if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
1309 /*
1310 * Stop getting skb's from upper layers.
1311 * Getting skb's from upper layers will be enabled again after
1312 * packets are released.
1313 */
1314 netif_stop_queue(dev);
1315
1316 /* Update statistics and start of transmittion time */
1317 stats->tx_packets++;
1318 dev->trans_start = jiffies;
1319
1320 spin_unlock_irqrestore(&mp->lock, flags);
1321
1322 return 0; /* success */
1323}
1324
1325/*
1326 * mv643xx_eth_get_stats
1327 *
1328 * Returns a pointer to the interface statistics.
1329 *
1330 * Input : dev - a pointer to the required interface
1331 *
1332 * Output : a pointer to the interface's statistics
1333 */
1334
1335static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1336{
1337 struct mv643xx_private *mp = netdev_priv(dev);
1338
1339 return &mp->stats;
1340}
1341
1342/*/
1343 * mv643xx_eth_probe
1344 *
1345 * First function called after registering the network device.
1346 * It's purpose is to initialize the device as an ethernet device,
1347 * fill the ethernet device structure with pointers * to functions,
1348 * and set the MAC address of the interface
1349 *
1350 * Input : struct device *
1351 * Output : -ENOMEM if failed , 0 if success
1352 */
1353static int mv643xx_eth_probe(struct device *ddev)
1354{
1355 struct platform_device *pdev = to_platform_device(ddev);
1356 struct mv643xx_eth_platform_data *pd;
1357 int port_num = pdev->id;
1358 struct mv643xx_private *mp;
1359 struct net_device *dev;
1360 u8 *p;
1361 struct resource *res;
1362 int err;
1363
1364 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1365 if (!dev)
1366 return -ENOMEM;
1367
1368 dev_set_drvdata(ddev, dev);
1369
1370 mp = netdev_priv(dev);
1371
1372 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1373 BUG_ON(!res);
1374 dev->irq = res->start;
1375
1376 mp->port_num = port_num;
1377
1378 dev->open = mv643xx_eth_open;
1379 dev->stop = mv643xx_eth_stop;
1380 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1381 dev->get_stats = mv643xx_eth_get_stats;
1382 dev->set_mac_address = mv643xx_eth_set_mac_address;
1383 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1384
1385 /* No need to Tx Timeout */
1386 dev->tx_timeout = mv643xx_eth_tx_timeout;
1387#ifdef MV643XX_NAPI
1388 dev->poll = mv643xx_poll;
1389 dev->weight = 64;
1390#endif
1391
1392 dev->watchdog_timeo = 2 * HZ;
1393 dev->tx_queue_len = mp->tx_ring_size;
1394 dev->base_addr = 0;
1395 dev->change_mtu = mv643xx_eth_change_mtu;
1396 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1397
1398#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1399#ifdef MAX_SKB_FRAGS
1400 /*
1401 * Zero copy can only work if we use Discovery II memory. Else, we will
1402 * have to map the buffers to ISA memory which is only 16 MB
1403 */
1404 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
1405#endif
1406#endif
1407
1408 /* Configure the timeout task */
1409 INIT_WORK(&mp->tx_timeout_task,
1410 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1411
1412 spin_lock_init(&mp->lock);
1413
1414 /* set default config values */
1415 eth_port_uc_addr_get(dev, dev->dev_addr);
1416 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1417 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1418 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1419 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1420 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1421 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1422
1423 pd = pdev->dev.platform_data;
1424 if (pd) {
1425 if (pd->mac_addr != NULL)
1426 memcpy(dev->dev_addr, pd->mac_addr, 6);
1427
1428 if (pd->phy_addr || pd->force_phy_addr)
1429 ethernet_phy_set(port_num, pd->phy_addr);
1430
1431 if (pd->port_config || pd->force_port_config)
1432 mp->port_config = pd->port_config;
1433
1434 if (pd->port_config_extend || pd->force_port_config_extend)
1435 mp->port_config_extend = pd->port_config_extend;
1436
1437 if (pd->port_sdma_config || pd->force_port_sdma_config)
1438 mp->port_sdma_config = pd->port_sdma_config;
1439
1440 if (pd->port_serial_control || pd->force_port_serial_control)
1441 mp->port_serial_control = pd->port_serial_control;
1442
1443 if (pd->rx_queue_size)
1444 mp->rx_ring_size = pd->rx_queue_size;
1445
1446 if (pd->tx_queue_size)
1447 mp->tx_ring_size = pd->tx_queue_size;
1448
1449 if (pd->tx_sram_size) {
1450 mp->tx_sram_size = pd->tx_sram_size;
1451 mp->tx_sram_addr = pd->tx_sram_addr;
1452 }
1453
1454 if (pd->rx_sram_size) {
1455 mp->rx_sram_size = pd->rx_sram_size;
1456 mp->rx_sram_addr = pd->rx_sram_addr;
1457 }
1458 }
1459
1460 err = ethernet_phy_detect(port_num);
1461 if (err) {
1462 pr_debug("MV643xx ethernet port %d: "
1463 "No PHY detected at addr %d\n",
1464 port_num, ethernet_phy_get(port_num));
1465 return err;
1466 }
1467
1468 err = register_netdev(dev);
1469 if (err)
1470 goto out;
1471
1472 p = dev->dev_addr;
1473 printk(KERN_NOTICE
1474 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1475 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1476
1477 if (dev->features & NETIF_F_SG)
1478 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1479
1480 if (dev->features & NETIF_F_IP_CSUM)
1481 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1482 dev->name);
1483
1484#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1485 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1486#endif
1487
1488#ifdef MV643XX_COAL
1489 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1490 dev->name);
1491#endif
1492
1493#ifdef MV643XX_NAPI
1494 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1495#endif
1496
1497 return 0;
1498
1499out:
1500 free_netdev(dev);
1501
1502 return err;
1503}
1504
1505static int mv643xx_eth_remove(struct device *ddev)
1506{
1507 struct net_device *dev = dev_get_drvdata(ddev);
1508
1509 unregister_netdev(dev);
1510 flush_scheduled_work();
1511
1512 free_netdev(dev);
1513 dev_set_drvdata(ddev, NULL);
1514 return 0;
1515}
1516
1517static int mv643xx_eth_shared_probe(struct device *ddev)
1518{
1519 struct platform_device *pdev = to_platform_device(ddev);
1520 struct resource *res;
1521
1522 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1523
1524 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1525 if (res == NULL)
1526 return -ENODEV;
1527
1528 mv643xx_eth_shared_base = ioremap(res->start,
1529 MV643XX_ETH_SHARED_REGS_SIZE);
1530 if (mv643xx_eth_shared_base == NULL)
1531 return -ENOMEM;
1532
1533 return 0;
1534
1535}
1536
1537static int mv643xx_eth_shared_remove(struct device *ddev)
1538{
1539 iounmap(mv643xx_eth_shared_base);
1540 mv643xx_eth_shared_base = NULL;
1541
1542 return 0;
1543}
1544
1545static struct device_driver mv643xx_eth_driver = {
1546 .name = MV643XX_ETH_NAME,
1547 .bus = &platform_bus_type,
1548 .probe = mv643xx_eth_probe,
1549 .remove = mv643xx_eth_remove,
1550};
1551
1552static struct device_driver mv643xx_eth_shared_driver = {
1553 .name = MV643XX_ETH_SHARED_NAME,
1554 .bus = &platform_bus_type,
1555 .probe = mv643xx_eth_shared_probe,
1556 .remove = mv643xx_eth_shared_remove,
1557};
1558
1559/*
1560 * mv643xx_init_module
1561 *
1562 * Registers the network drivers into the Linux kernel
1563 *
1564 * Input : N/A
1565 *
1566 * Output : N/A
1567 */
1568static int __init mv643xx_init_module(void)
1569{
1570 int rc;
1571
1572 rc = driver_register(&mv643xx_eth_shared_driver);
1573 if (!rc) {
1574 rc = driver_register(&mv643xx_eth_driver);
1575 if (rc)
1576 driver_unregister(&mv643xx_eth_shared_driver);
1577 }
1578 return rc;
1579}
1580
1581/*
1582 * mv643xx_cleanup_module
1583 *
1584 * Registers the network drivers into the Linux kernel
1585 *
1586 * Input : N/A
1587 *
1588 * Output : N/A
1589 */
1590static void __exit mv643xx_cleanup_module(void)
1591{
1592 driver_unregister(&mv643xx_eth_driver);
1593 driver_unregister(&mv643xx_eth_shared_driver);
1594}
1595
1596module_init(mv643xx_init_module);
1597module_exit(mv643xx_cleanup_module);
1598
1599MODULE_LICENSE("GPL");
1600MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1601 " and Dale Farnsworth");
1602MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1603
1604/*
1605 * The second part is the low level driver of the gigE ethernet ports.
1606 */
1607
1608/*
1609 * Marvell's Gigabit Ethernet controller low level driver
1610 *
1611 * DESCRIPTION:
1612 * This file introduce low level API to Marvell's Gigabit Ethernet
1613 * controller. This Gigabit Ethernet Controller driver API controls
1614 * 1) Operations (i.e. port init, start, reset etc').
1615 * 2) Data flow (i.e. port send, receive etc').
1616 * Each Gigabit Ethernet port is controlled via
1617 * struct mv643xx_private.
1618 * This struct includes user configuration information as well as
1619 * driver internal data needed for its operations.
1620 *
1621 * Supported Features:
1622 * - This low level driver is OS independent. Allocating memory for
1623 * the descriptor rings and buffers are not within the scope of
1624 * this driver.
1625 * - The user is free from Rx/Tx queue managing.
1626 * - This low level driver introduce functionality API that enable
1627 * the to operate Marvell's Gigabit Ethernet Controller in a
1628 * convenient way.
1629 * - Simple Gigabit Ethernet port operation API.
1630 * - Simple Gigabit Ethernet port data flow API.
1631 * - Data flow and operation API support per queue functionality.
1632 * - Support cached descriptors for better performance.
1633 * - Enable access to all four DRAM banks and internal SRAM memory
1634 * spaces.
1635 * - PHY access and control API.
1636 * - Port control register configuration API.
1637 * - Full control over Unicast and Multicast MAC configurations.
1638 *
1639 * Operation flow:
1640 *
1641 * Initialization phase
1642 * This phase complete the initialization of the the
1643 * mv643xx_private struct.
1644 * User information regarding port configuration has to be set
1645 * prior to calling the port initialization routine.
1646 *
1647 * In this phase any port Tx/Rx activity is halted, MIB counters
1648 * are cleared, PHY address is set according to user parameter and
1649 * access to DRAM and internal SRAM memory spaces.
1650 *
1651 * Driver ring initialization
1652 * Allocating memory for the descriptor rings and buffers is not
1653 * within the scope of this driver. Thus, the user is required to
1654 * allocate memory for the descriptors ring and buffers. Those
1655 * memory parameters are used by the Rx and Tx ring initialization
1656 * routines in order to curve the descriptor linked list in a form
1657 * of a ring.
1658 * Note: Pay special attention to alignment issues when using
1659 * cached descriptors/buffers. In this phase the driver store
1660 * information in the mv643xx_private struct regarding each queue
1661 * ring.
1662 *
1663 * Driver start
1664 * This phase prepares the Ethernet port for Rx and Tx activity.
1665 * It uses the information stored in the mv643xx_private struct to
1666 * initialize the various port registers.
1667 *
1668 * Data flow:
1669 * All packet references to/from the driver are done using
1670 * struct pkt_info.
1671 * This struct is a unified struct used with Rx and Tx operations.
1672 * This way the user is not required to be familiar with neither
1673 * Tx nor Rx descriptors structures.
1674 * The driver's descriptors rings are management by indexes.
1675 * Those indexes controls the ring resources and used to indicate
1676 * a SW resource error:
1677 * 'current'
1678 * This index points to the current available resource for use. For
1679 * example in Rx process this index will point to the descriptor
1680 * that will be passed to the user upon calling the receive
1681 * routine. In Tx process, this index will point to the descriptor
1682 * that will be assigned with the user packet info and transmitted.
1683 * 'used'
1684 * This index points to the descriptor that need to restore its
1685 * resources. For example in Rx process, using the Rx buffer return
1686 * API will attach the buffer returned in packet info to the
1687 * descriptor pointed by 'used'. In Tx process, using the Tx
1688 * descriptor return will merely return the user packet info with
1689 * the command status of the transmitted buffer pointed by the
1690 * 'used' index. Nevertheless, it is essential to use this routine
1691 * to update the 'used' index.
1692 * 'first'
1693 * This index supports Tx Scatter-Gather. It points to the first
1694 * descriptor of a packet assembled of multiple buffers. For
1695 * example when in middle of Such packet we have a Tx resource
1696 * error the 'curr' index get the value of 'first' to indicate
1697 * that the ring returned to its state before trying to transmit
1698 * this packet.
1699 *
1700 * Receive operation:
1701 * The eth_port_receive API set the packet information struct,
1702 * passed by the caller, with received information from the
1703 * 'current' SDMA descriptor.
1704 * It is the user responsibility to return this resource back
1705 * to the Rx descriptor ring to enable the reuse of this source.
1706 * Return Rx resource is done using the eth_rx_return_buff API.
1707 *
1708 * Transmit operation:
1709 * The eth_port_send API supports Scatter-Gather which enables to
1710 * send a packet spanned over multiple buffers. This means that
1711 * for each packet info structure given by the user and put into
1712 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1713 * bit will be set in the packet info command status field. This
1714 * API also consider restriction regarding buffer alignments and
1715 * sizes.
1716 * The user must return a Tx resource after ensuring the buffer
1717 * has been transmitted to enable the Tx ring indexes to update.
1718 *
1719 * BOARD LAYOUT
1720 * This device is on-board. No jumper diagram is necessary.
1721 *
1722 * EXTERNAL INTERFACE
1723 *
1724 * Prior to calling the initialization routine eth_port_init() the user
1725 * must set the following fields under mv643xx_private struct:
1726 * port_num User Ethernet port number.
1727 * port_mac_addr[6] User defined port MAC address.
1728 * port_config User port configuration value.
1729 * port_config_extend User port config extend value.
1730 * port_sdma_config User port SDMA config value.
1731 * port_serial_control User port serial control value.
1732 *
1733 * This driver data flow is done using the struct pkt_info which
1734 * is a unified struct for Rx and Tx operations:
1735 *
1736 * byte_cnt Tx/Rx descriptor buffer byte count.
1737 * l4i_chk CPU provided TCP Checksum. For Tx operation
1738 * only.
1739 * cmd_sts Tx/Rx descriptor command status.
1740 * buf_ptr Tx/Rx descriptor buffer pointer.
1741 * return_info Tx/Rx user resource return information.
1742 */
1743
1744/* defines */
1745/* SDMA command macros */
1746#define ETH_ENABLE_TX_QUEUE(eth_port) \
1747 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1748
1749/* locals */
1750
1751/* PHY routines */
1752static int ethernet_phy_get(unsigned int eth_port_num);
1753static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1754
1755/* Ethernet Port routines */
1756static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1757 int option);
1758
1759/*
1760 * eth_port_init - Initialize the Ethernet port driver
1761 *
1762 * DESCRIPTION:
1763 * This function prepares the ethernet port to start its activity:
1764 * 1) Completes the ethernet port driver struct initialization toward port
1765 * start routine.
1766 * 2) Resets the device to a quiescent state in case of warm reboot.
1767 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1768 * 4) Clean MAC tables. The reset status of those tables is unknown.
1769 * 5) Set PHY address.
1770 * Note: Call this routine prior to eth_port_start routine and after
1771 * setting user values in the user fields of Ethernet port control
1772 * struct.
1773 *
1774 * INPUT:
1775 * struct mv643xx_private *mp Ethernet port control struct
1776 *
1777 * OUTPUT:
1778 * See description.
1779 *
1780 * RETURN:
1781 * None.
1782 */
1783static void eth_port_init(struct mv643xx_private *mp)
1784{
1785 mp->port_rx_queue_command = 0;
1786 mp->port_tx_queue_command = 0;
1787
1788 mp->rx_resource_err = 0;
1789 mp->tx_resource_err = 0;
1790
1791 eth_port_reset(mp->port_num);
1792
1793 eth_port_init_mac_tables(mp->port_num);
1794
1795 ethernet_phy_reset(mp->port_num);
1796}
1797
1798/*
1799 * eth_port_start - Start the Ethernet port activity.
1800 *
1801 * DESCRIPTION:
1802 * This routine prepares the Ethernet port for Rx and Tx activity:
1803 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1804 * has been initialized a descriptor's ring (using
1805 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1806 * 2. Initialize and enable the Ethernet configuration port by writing to
1807 * the port's configuration and command registers.
1808 * 3. Initialize and enable the SDMA by writing to the SDMA's
1809 * configuration and command registers. After completing these steps,
1810 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1811 *
1812 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1813 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1814 * and ether_init_rx_desc_ring for Rx queues).
1815 *
1816 * INPUT:
1817 * struct mv643xx_private *mp Ethernet port control struct
1818 *
1819 * OUTPUT:
1820 * Ethernet port is ready to receive and transmit.
1821 *
1822 * RETURN:
1823 * None.
1824 */
1825static void eth_port_start(struct mv643xx_private *mp)
1826{
1827 unsigned int port_num = mp->port_num;
1828 int tx_curr_desc, rx_curr_desc;
1829
1830 /* Assignment of Tx CTRP of given queue */
1831 tx_curr_desc = mp->tx_curr_desc_q;
1832 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1833 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1834
1835 /* Assignment of Rx CRDP of given queue */
1836 rx_curr_desc = mp->rx_curr_desc_q;
1837 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1838 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1839
1840 /* Add the assigned Ethernet address to the port's address table */
1841 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
1842
1843 /* Assign port configuration and command. */
1844 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1845
1846 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1847 mp->port_config_extend);
1848
1849
1850 /* Increase the Rx side buffer size if supporting GigE */
1851 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1852 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1853 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1854 else
1855 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1856 mp->port_serial_control);
1857
1858 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1859 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1860 MV643XX_ETH_SERIAL_PORT_ENABLE);
1861
1862 /* Assign port SDMA configuration */
1863 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1864 mp->port_sdma_config);
1865
1866 /* Enable port Rx. */
1867 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
1868 mp->port_rx_queue_command);
8f543718
DF		 1869
1870 /* Disable port bandwidth limits by clearing MTU register */
1871 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1da177e4
LT		 1872}
1873
1874/*
1875 * eth_port_uc_addr_set - This function Set the port Unicast address.
1876 *
1877 * DESCRIPTION:
1878 * This function Set the port Ethernet MAC address.
1879 *
1880 * INPUT:
1881 * unsigned int eth_port_num Port number.
1882 * char * p_addr Address to be set
1883 *
1884 * OUTPUT:
1885 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1886 * To set the unicast table with the proper information.
1887 *
1888 * RETURN:
1889 * N/A.
1890 *
1891 */
1892static void eth_port_uc_addr_set(unsigned int eth_port_num,
1893 unsigned char *p_addr)
1894{
1895 unsigned int mac_h;
1896 unsigned int mac_l;
1897
1898 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1899 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1900 (p_addr[3] << 0);
1901
1902 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1903 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1904
1905 /* Accept frames of this address */
1906 eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
1907
1908 return;
1909}
1910
1911/*
1912 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1913 * (MAC address) from the ethernet hw registers.
1914 *
1915 * DESCRIPTION:
1916 * This function retrieves the port Ethernet MAC address.
1917 *
1918 * INPUT:
1919 * unsigned int eth_port_num Port number.
1920 * char *MacAddr pointer where the MAC address is stored
1921 *
1922 * OUTPUT:
1923 * Copy the MAC address to the location pointed to by MacAddr
1924 *
1925 * RETURN:
1926 * N/A.
1927 *
1928 */
1929static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1930{
1931 struct mv643xx_private *mp = netdev_priv(dev);
1932 unsigned int mac_h;
1933 unsigned int mac_l;
1934
1935 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1936 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1937
1938 p_addr[0] = (mac_h >> 24) & 0xff;
1939 p_addr[1] = (mac_h >> 16) & 0xff;
1940 p_addr[2] = (mac_h >> 8) & 0xff;
1941 p_addr[3] = mac_h & 0xff;
1942 p_addr[4] = (mac_l >> 8) & 0xff;
1943 p_addr[5] = mac_l & 0xff;
1944}
1945
1946/*
1947 * eth_port_uc_addr - This function Set the port unicast address table
1948 *
1949 * DESCRIPTION:
1950 * This function locates the proper entry in the Unicast table for the
1951 * specified MAC nibble and sets its properties according to function
1952 * parameters.
1953 *
1954 * INPUT:
1955 * unsigned int eth_port_num Port number.
1956 * unsigned char uc_nibble Unicast MAC Address last nibble.
1957 * int option 0 = Add, 1 = remove address.
1958 *
1959 * OUTPUT:
1960 * This function add/removes MAC addresses from the port unicast address
1961 * table.
1962 *
1963 * RETURN:
1964 * true is output succeeded.
1965 * false if option parameter is invalid.
1966 *
1967 */
1968static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1969 int option)
1970{
1971 unsigned int unicast_reg;
1972 unsigned int tbl_offset;
1973 unsigned int reg_offset;
1974
1975 /* Locate the Unicast table entry */
1976 uc_nibble = (0xf & uc_nibble);
1977 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
1978 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
1979
1980 switch (option) {
1981 case REJECT_MAC_ADDR:
1982 /* Clear accepts frame bit at given unicast DA table entry */
1983 unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1984 (eth_port_num) + tbl_offset));
1985
1986 unicast_reg &= (0x0E << (8 * reg_offset));
1987
1988 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1989 (eth_port_num) + tbl_offset), unicast_reg);
1990 break;
1991
1992 case ACCEPT_MAC_ADDR:
1993 /* Set accepts frame bit at unicast DA filter table entry */
1994 unicast_reg =
1995 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1996 (eth_port_num) + tbl_offset));
1997
1998 unicast_reg |= (0x01 << (8 * reg_offset));
1999
2000 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2001 (eth_port_num) + tbl_offset), unicast_reg);
2002
2003 break;
2004
2005 default:
2006 return 0;
2007 }
2008
2009 return 1;
2010}
2011
2012/*
2013 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2014 *
2015 * DESCRIPTION:
2016 * Go through all the DA filter tables (Unicast, Special Multicast &
2017 * Other Multicast) and set each entry to 0.
2018 *
2019 * INPUT:
2020 * unsigned int eth_port_num Ethernet Port number.
2021 *
2022 * OUTPUT:
2023 * Multicast and Unicast packets are rejected.
2024 *
2025 * RETURN:
2026 * None.
2027 */
2028static void eth_port_init_mac_tables(unsigned int eth_port_num)
2029{
2030 int table_index;
2031
2032 /* Clear DA filter unicast table (Ex_dFUT) */
2033 for (table_index = 0; table_index <= 0xC; table_index += 4)
2034 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2035 (eth_port_num) + table_index), 0);
2036
2037 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2038 /* Clear DA filter special multicast table (Ex_dFSMT) */
2039 mv_write((MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2040 (eth_port_num) + table_index), 0);
2041 /* Clear DA filter other multicast table (Ex_dFOMT) */
2042 mv_write((MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2043 (eth_port_num) + table_index), 0);
2044 }
2045}
2046
2047/*
2048 * eth_clear_mib_counters - Clear all MIB counters
2049 *
2050 * DESCRIPTION:
2051 * This function clears all MIB counters of a specific ethernet port.
2052 * A read from the MIB counter will reset the counter.
2053 *
2054 * INPUT:
2055 * unsigned int eth_port_num Ethernet Port number.
2056 *
2057 * OUTPUT:
2058 * After reading all MIB counters, the counters resets.
2059 *
2060 * RETURN:
2061 * MIB counter value.
2062 *
2063 */
2064static void eth_clear_mib_counters(unsigned int eth_port_num)
2065{
2066 int i;
2067
2068 /* Perform dummy reads from MIB counters */
2069 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2070 i += 4)
2071 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2072}
2073
2074static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2075{
2076 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2077}
2078
2079static void eth_update_mib_counters(struct mv643xx_private *mp)
2080{
2081 struct mv643xx_mib_counters *p = &mp->mib_counters;
2082 int offset;
2083
2084 p->good_octets_received +=
2085 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2086 p->good_octets_received +=
2087 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2088
2089 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2090 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2091 offset += 4)
2092 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2093
2094 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2095 p->good_octets_sent +=
2096 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2097
2098 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2099 offset <= ETH_MIB_LATE_COLLISION;
2100 offset += 4)
2101 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2102}
2103
2104/*
2105 * ethernet_phy_detect - Detect whether a phy is present
2106 *
2107 * DESCRIPTION:
2108 * This function tests whether there is a PHY present on
2109 * the specified port.
2110 *
2111 * INPUT:
2112 * unsigned int eth_port_num Ethernet Port number.
2113 *
2114 * OUTPUT:
2115 * None
2116 *
2117 * RETURN:
2118 * 0 on success
2119 * -ENODEV on failure
2120 *
2121 */
2122static int ethernet_phy_detect(unsigned int port_num)
2123{
2124 unsigned int phy_reg_data0;
2125 int auto_neg;
2126
2127 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2128 auto_neg = phy_reg_data0 & 0x1000;
2129 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2130 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2131
2132 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2133 if ((phy_reg_data0 & 0x1000) == auto_neg)
2134 return -ENODEV; /* change didn't take */
2135
2136 phy_reg_data0 ^= 0x1000;
2137 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2138 return 0;
2139}
2140
2141/*
2142 * ethernet_phy_get - Get the ethernet port PHY address.
2143 *
2144 * DESCRIPTION:
2145 * This routine returns the given ethernet port PHY address.
2146 *
2147 * INPUT:
2148 * unsigned int eth_port_num Ethernet Port number.
2149 *
2150 * OUTPUT:
2151 * None.
2152 *
2153 * RETURN:
2154 * PHY address.
2155 *
2156 */
2157static int ethernet_phy_get(unsigned int eth_port_num)
2158{
2159 unsigned int reg_data;
2160
2161 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2162
2163 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2164}
2165
2166/*
2167 * ethernet_phy_set - Set the ethernet port PHY address.
2168 *
2169 * DESCRIPTION:
2170 * This routine sets the given ethernet port PHY address.
2171 *
2172 * INPUT:
2173 * unsigned int eth_port_num Ethernet Port number.
2174 * int phy_addr PHY address.
2175 *
2176 * OUTPUT:
2177 * None.
2178 *
2179 * RETURN:
2180 * None.
2181 *
2182 */
2183static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2184{
2185 u32 reg_data;
2186 int addr_shift = 5 * eth_port_num;
2187
2188 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2189 reg_data &= ~(0x1f << addr_shift);
2190 reg_data |= (phy_addr & 0x1f) << addr_shift;
2191 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2192}
2193
2194/*
2195 * ethernet_phy_reset - Reset Ethernet port PHY.
2196 *
2197 * DESCRIPTION:
2198 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2199 *
2200 * INPUT:
2201 * unsigned int eth_port_num Ethernet Port number.
2202 *
2203 * OUTPUT:
2204 * The PHY is reset.
2205 *
2206 * RETURN:
2207 * None.
2208 *
2209 */
2210static void ethernet_phy_reset(unsigned int eth_port_num)
2211{
2212 unsigned int phy_reg_data;
2213
2214 /* Reset the PHY */
2215 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2216 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2217 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2218}
2219
2220/*
2221 * eth_port_reset - Reset Ethernet port
2222 *
2223 * DESCRIPTION:
2224 * This routine resets the chip by aborting any SDMA engine activity and
2225 * clearing the MIB counters. The Receiver and the Transmit unit are in
2226 * idle state after this command is performed and the port is disabled.
2227 *
2228 * INPUT:
2229 * unsigned int eth_port_num Ethernet Port number.
2230 *
2231 * OUTPUT:
2232 * Channel activity is halted.
2233 *
2234 * RETURN:
2235 * None.
2236 *
2237 */
2238static void eth_port_reset(unsigned int port_num)
2239{
2240 unsigned int reg_data;
2241
2242 /* Stop Tx port activity. Check port Tx activity. */
2243 reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
2244
2245 if (reg_data & 0xFF) {
2246 /* Issue stop command for active channels only */
2247 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2248 (reg_data << 8));
2249
2250 /* Wait for all Tx activity to terminate. */
2251 /* Check port cause register that all Tx queues are stopped */
2252 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2253 & 0xFF)
2254 udelay(10);
2255 }
2256
2257 /* Stop Rx port activity. Check port Rx activity. */
2258 reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
2259
2260 if (reg_data & 0xFF) {
2261 /* Issue stop command for active channels only */
2262 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2263 (reg_data << 8));
2264
2265 /* Wait for all Rx activity to terminate. */
2266 /* Check port cause register that all Rx queues are stopped */
2267 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2268 & 0xFF)
2269 udelay(10);
2270 }
2271
2272 /* Clear all MIB counters */
2273 eth_clear_mib_counters(port_num);
2274
2275 /* Reset the Enable bit in the Configuration Register */
2276 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2277 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2278 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2279}
2280
2281/*
2282 * ethernet_set_config_reg - Set specified bits in configuration register.
2283 *
2284 * DESCRIPTION:
2285 * This function sets specified bits in the given ethernet
2286 * configuration register.
2287 *
2288 * INPUT:
2289 * unsigned int eth_port_num Ethernet Port number.
2290 * unsigned int value 32 bit value.
2291 *
2292 * OUTPUT:
2293 * The set bits in the value parameter are set in the configuration
2294 * register.
2295 *
2296 * RETURN:
2297 * None.
2298 *
2299 */
2300static void ethernet_set_config_reg(unsigned int eth_port_num,
2301 unsigned int value)
2302{
2303 unsigned int eth_config_reg;
2304
2305 eth_config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(eth_port_num));
2306 eth_config_reg |= value;
2307 mv_write(MV643XX_ETH_PORT_CONFIG_REG(eth_port_num), eth_config_reg);
2308}
2309
2310static int eth_port_autoneg_supported(unsigned int eth_port_num)
2311{
2312 unsigned int phy_reg_data0;
2313
2314 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2315
2316 return phy_reg_data0 & 0x1000;
2317}
2318
2319static int eth_port_link_is_up(unsigned int eth_port_num)
2320{
2321 unsigned int phy_reg_data1;
2322
2323 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2324
2325 if (eth_port_autoneg_supported(eth_port_num)) {
2326 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2327 return 1;
2328 } else if (phy_reg_data1 & 0x4) /* link up */
2329 return 1;
2330
2331 return 0;
2332}
2333
2334/*
2335 * ethernet_get_config_reg - Get the port configuration register
2336 *
2337 * DESCRIPTION:
2338 * This function returns the configuration register value of the given
2339 * ethernet port.
2340 *
2341 * INPUT:
2342 * unsigned int eth_port_num Ethernet Port number.
2343 *
2344 * OUTPUT:
2345 * None.
2346 *
2347 * RETURN:
2348 * Port configuration register value.
2349 */
2350static unsigned int ethernet_get_config_reg(unsigned int eth_port_num)
2351{
2352 unsigned int eth_config_reg;
2353
2354 eth_config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_EXTEND_REG
2355 (eth_port_num));
2356 return eth_config_reg;
2357}
2358
2359/*
2360 * eth_port_read_smi_reg - Read PHY registers
2361 *
2362 * DESCRIPTION:
2363 * This routine utilize the SMI interface to interact with the PHY in
2364 * order to perform PHY register read.
2365 *
2366 * INPUT:
2367 * unsigned int port_num Ethernet Port number.
2368 * unsigned int phy_reg PHY register address offset.
2369 * unsigned int *value Register value buffer.
2370 *
2371 * OUTPUT:
2372 * Write the value of a specified PHY register into given buffer.
2373 *
2374 * RETURN:
2375 * false if the PHY is busy or read data is not in valid state.
2376 * true otherwise.
2377 *
2378 */
2379static void eth_port_read_smi_reg(unsigned int port_num,
2380 unsigned int phy_reg, unsigned int *value)
2381{
2382 int phy_addr = ethernet_phy_get(port_num);
2383 unsigned long flags;
2384 int i;
2385
2386 /* the SMI register is a shared resource */
2387 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2388
2389 /* wait for the SMI register to become available */
2390 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2391 if (i == PHY_WAIT_ITERATIONS) {
2392 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2393 goto out;
2394 }
2395 udelay(PHY_WAIT_MICRO_SECONDS);
2396 }
2397
2398 mv_write(MV643XX_ETH_SMI_REG,
2399 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2400
2401 /* now wait for the data to be valid */
2402 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2403 if (i == PHY_WAIT_ITERATIONS) {
2404 printk("mv643xx PHY read timeout, port %d\n", port_num);
2405 goto out;
2406 }
2407 udelay(PHY_WAIT_MICRO_SECONDS);
2408 }
2409
2410 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2411out:
2412 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2413}
2414
2415/*
2416 * eth_port_write_smi_reg - Write to PHY registers
2417 *
2418 * DESCRIPTION:
2419 * This routine utilize the SMI interface to interact with the PHY in
2420 * order to perform writes to PHY registers.
2421 *
2422 * INPUT:
2423 * unsigned int eth_port_num Ethernet Port number.
2424 * unsigned int phy_reg PHY register address offset.
2425 * unsigned int value Register value.
2426 *
2427 * OUTPUT:
2428 * Write the given value to the specified PHY register.
2429 *
2430 * RETURN:
2431 * false if the PHY is busy.
2432 * true otherwise.
2433 *
2434 */
2435static void eth_port_write_smi_reg(unsigned int eth_port_num,
2436 unsigned int phy_reg, unsigned int value)
2437{
2438 int phy_addr;
2439 int i;
2440 unsigned long flags;
2441
2442 phy_addr = ethernet_phy_get(eth_port_num);
2443
2444 /* the SMI register is a shared resource */
2445 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2446
2447 /* wait for the SMI register to become available */
2448 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2449 if (i == PHY_WAIT_ITERATIONS) {
2450 printk("mv643xx PHY busy timeout, port %d\n",
2451 eth_port_num);
2452 goto out;
2453 }
2454 udelay(PHY_WAIT_MICRO_SECONDS);
2455 }
2456
2457 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2458 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2459out:
2460 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2461}
2462
2463/*
2464 * eth_port_send - Send an Ethernet packet
2465 *
2466 * DESCRIPTION:
2467 * This routine send a given packet described by p_pktinfo parameter. It
2468 * supports transmitting of a packet spaned over multiple buffers. The
2469 * routine updates 'curr' and 'first' indexes according to the packet
2470 * segment passed to the routine. In case the packet segment is first,
2471 * the 'first' index is update. In any case, the 'curr' index is updated.
2472 * If the routine get into Tx resource error it assigns 'curr' index as
2473 * 'first'. This way the function can abort Tx process of multiple
2474 * descriptors per packet.
2475 *
2476 * INPUT:
2477 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2478 * struct pkt_info *p_pkt_info User packet buffer.
2479 *
2480 * OUTPUT:
2481 * Tx ring 'curr' and 'first' indexes are updated.
2482 *
2483 * RETURN:
2484 * ETH_QUEUE_FULL in case of Tx resource error.
2485 * ETH_ERROR in case the routine can not access Tx desc ring.
2486 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2487 * ETH_OK otherwise.
2488 *
2489 */
2490#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2491/*
2492 * Modified to include the first descriptor pointer in case of SG
2493 */
2494static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2495 struct pkt_info *p_pkt_info)
2496{
2497 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2498 struct eth_tx_desc *current_descriptor;
2499 struct eth_tx_desc *first_descriptor;
2500 u32 command;
2501
2502 /* Do not process Tx ring in case of Tx ring resource error */
2503 if (mp->tx_resource_err)
2504 return ETH_QUEUE_FULL;
2505
2506 /*
2507 * The hardware requires that each buffer that is <= 8 bytes
2508 * in length must be aligned on an 8 byte boundary.
2509 */
2510 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2511 printk(KERN_ERR
2512 "mv643xx_eth port %d: packet size <= 8 problem\n",
2513 mp->port_num);
2514 return ETH_ERROR;
2515 }
2516
b111ceb6
DF		 2517 mp->tx_ring_skbs++;
2518 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2519
1da177e4
LT		 2520 /* Get the Tx Desc ring indexes */
2521 tx_desc_curr = mp->tx_curr_desc_q;
2522 tx_desc_used = mp->tx_used_desc_q;
2523
2524 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2525
2526 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2527
2528 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2529 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2530 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2531 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2532
2533 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2534 ETH_BUFFER_OWNED_BY_DMA;
2535 if (command & ETH_TX_FIRST_DESC) {
2536 tx_first_desc = tx_desc_curr;
2537 mp->tx_first_desc_q = tx_first_desc;
2538 first_descriptor = current_descriptor;
2539 mp->tx_first_command = command;
2540 } else {
2541 tx_first_desc = mp->tx_first_desc_q;
2542 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2543 BUG_ON(first_descriptor == NULL);
2544 current_descriptor->cmd_sts = command;
2545 }
2546
2547 if (command & ETH_TX_LAST_DESC) {
2548 wmb();
2549 first_descriptor->cmd_sts = mp->tx_first_command;
2550
2551 wmb();
2552 ETH_ENABLE_TX_QUEUE(mp->port_num);
2553
2554 /*
2555 * Finish Tx packet. Update first desc in case of Tx resource
2556 * error */
2557 tx_first_desc = tx_next_desc;
2558 mp->tx_first_desc_q = tx_first_desc;
2559 }
2560
2561 /* Check for ring index overlap in the Tx desc ring */
2562 if (tx_next_desc == tx_desc_used) {
2563 mp->tx_resource_err = 1;
2564 mp->tx_curr_desc_q = tx_first_desc;
2565
2566 return ETH_QUEUE_LAST_RESOURCE;
2567 }
2568
2569 mp->tx_curr_desc_q = tx_next_desc;
2570
2571 return ETH_OK;
2572}
2573#else
2574static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2575 struct pkt_info *p_pkt_info)
2576{
2577 int tx_desc_curr;
2578 int tx_desc_used;
2579 struct eth_tx_desc *current_descriptor;
2580 unsigned int command_status;
2581
2582 /* Do not process Tx ring in case of Tx ring resource error */
2583 if (mp->tx_resource_err)
2584 return ETH_QUEUE_FULL;
2585
b111ceb6
DF		 2586 mp->tx_ring_skbs++;
2587 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2588
1da177e4
LT		 2589 /* Get the Tx Desc ring indexes */
2590 tx_desc_curr = mp->tx_curr_desc_q;
2591 tx_desc_used = mp->tx_used_desc_q;
2592 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2593
2594 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2595 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2596 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2597 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2598
2599 /* Set last desc with DMA ownership and interrupt enable. */
2600 wmb();
2601 current_descriptor->cmd_sts = command_status |
2602 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2603
2604 wmb();
2605 ETH_ENABLE_TX_QUEUE(mp->port_num);
2606
2607 /* Finish Tx packet. Update first desc in case of Tx resource error */
2608 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2609
2610 /* Update the current descriptor */
2611 mp->tx_curr_desc_q = tx_desc_curr;
2612
2613 /* Check for ring index overlap in the Tx desc ring */
2614 if (tx_desc_curr == tx_desc_used) {
2615 mp->tx_resource_err = 1;
2616 return ETH_QUEUE_LAST_RESOURCE;
2617 }
2618
2619 return ETH_OK;
2620}
2621#endif
2622
2623/*
2624 * eth_tx_return_desc - Free all used Tx descriptors
2625 *
2626 * DESCRIPTION:
2627 * This routine returns the transmitted packet information to the caller.
2628 * It uses the 'first' index to support Tx desc return in case a transmit
2629 * of a packet spanned over multiple buffer still in process.
2630 * In case the Tx queue was in "resource error" condition, where there are
2631 * no available Tx resources, the function resets the resource error flag.
2632 *
2633 * INPUT:
2634 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2635 * struct pkt_info *p_pkt_info User packet buffer.
2636 *
2637 * OUTPUT:
2638 * Tx ring 'first' and 'used' indexes are updated.
2639 *
2640 * RETURN:
2641 * ETH_ERROR in case the routine can not access Tx desc ring.
2642 * ETH_RETRY in case there is transmission in process.
2643 * ETH_END_OF_JOB if the routine has nothing to release.
2644 * ETH_OK otherwise.
2645 *
2646 */
2647static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2648 struct pkt_info *p_pkt_info)
2649{
2650 int tx_desc_used;
2651#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2652 int tx_busy_desc = mp->tx_first_desc_q;
2653#else
2654 int tx_busy_desc = mp->tx_curr_desc_q;
2655#endif
2656 struct eth_tx_desc *p_tx_desc_used;
2657 unsigned int command_status;
2658
2659 /* Get the Tx Desc ring indexes */
2660 tx_desc_used = mp->tx_used_desc_q;
2661
2662 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2663
2664 /* Sanity check */
2665 if (p_tx_desc_used == NULL)
2666 return ETH_ERROR;
2667
2668 /* Stop release. About to overlap the current available Tx descriptor */
2669 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err)
2670 return ETH_END_OF_JOB;
2671
2672 command_status = p_tx_desc_used->cmd_sts;
2673
2674 /* Still transmitting... */
2675 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2676 return ETH_RETRY;
2677
2678 /* Pass the packet information to the caller */
2679 p_pkt_info->cmd_sts = command_status;
2680 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
2681 mp->tx_skb[tx_desc_used] = NULL;
2682
2683 /* Update the next descriptor to release. */
2684 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2685
2686 /* Any Tx return cancels the Tx resource error status */
2687 mp->tx_resource_err = 0;
2688
b111ceb6
DF		 2689 BUG_ON(mp->tx_ring_skbs == 0);
2690 mp->tx_ring_skbs--;
2691
1da177e4
LT		 2692 return ETH_OK;
2693}
2694
2695/*
2696 * eth_port_receive - Get received information from Rx ring.
2697 *
2698 * DESCRIPTION:
2699 * This routine returns the received data to the caller. There is no
2700 * data copying during routine operation. All information is returned
2701 * using pointer to packet information struct passed from the caller.
2702 * If the routine exhausts Rx ring resources then the resource error flag
2703 * is set.
2704 *
2705 * INPUT:
2706 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2707 * struct pkt_info *p_pkt_info User packet buffer.
2708 *
2709 * OUTPUT:
2710 * Rx ring current and used indexes are updated.
2711 *
2712 * RETURN:
2713 * ETH_ERROR in case the routine can not access Rx desc ring.
2714 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2715 * ETH_END_OF_JOB if there is no received data.
2716 * ETH_OK otherwise.
2717 */
2718static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2719 struct pkt_info *p_pkt_info)
2720{
2721 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2722 volatile struct eth_rx_desc *p_rx_desc;
2723 unsigned int command_status;
2724
2725 /* Do not process Rx ring in case of Rx ring resource error */
2726 if (mp->rx_resource_err)
2727 return ETH_QUEUE_FULL;
2728
2729 /* Get the Rx Desc ring 'curr and 'used' indexes */
2730 rx_curr_desc = mp->rx_curr_desc_q;
2731 rx_used_desc = mp->rx_used_desc_q;
2732
2733 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2734
2735 /* The following parameters are used to save readings from memory */
2736 command_status = p_rx_desc->cmd_sts;
2737 rmb();
2738
2739 /* Nothing to receive... */
2740 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2741 return ETH_END_OF_JOB;
2742
2743 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2744 p_pkt_info->cmd_sts = command_status;
2745 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2746 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2747 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2748
2749 /* Clean the return info field to indicate that the packet has been */
2750 /* moved to the upper layers */
2751 mp->rx_skb[rx_curr_desc] = NULL;
2752
2753 /* Update current index in data structure */
2754 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2755 mp->rx_curr_desc_q = rx_next_curr_desc;
2756
2757 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2758 if (rx_next_curr_desc == rx_used_desc)
2759 mp->rx_resource_err = 1;
2760
2761 return ETH_OK;
2762}
2763
2764/*
2765 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2766 *
2767 * DESCRIPTION:
2768 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2769 * next 'used' descriptor and attached the returned buffer to it.
2770 * In case the Rx ring was in "resource error" condition, where there are
2771 * no available Rx resources, the function resets the resource error flag.
2772 *
2773 * INPUT:
2774 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2775 * struct pkt_info *p_pkt_info Information on returned buffer.
2776 *
2777 * OUTPUT:
2778 * New available Rx resource in Rx descriptor ring.
2779 *
2780 * RETURN:
2781 * ETH_ERROR in case the routine can not access Rx desc ring.
2782 * ETH_OK otherwise.
2783 */
2784static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2785 struct pkt_info *p_pkt_info)
2786{
2787 int used_rx_desc; /* Where to return Rx resource */
2788 volatile struct eth_rx_desc *p_used_rx_desc;
2789
2790 /* Get 'used' Rx descriptor */
2791 used_rx_desc = mp->rx_used_desc_q;
2792 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2793
2794 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2795 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2796 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2797
2798 /* Flush the write pipe */
2799
2800 /* Return the descriptor to DMA ownership */
2801 wmb();
2802 p_used_rx_desc->cmd_sts =
2803 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2804 wmb();
2805
2806 /* Move the used descriptor pointer to the next descriptor */
2807 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2808
2809 /* Any Rx return cancels the Rx resource error status */
2810 mp->rx_resource_err = 0;
2811
2812 return ETH_OK;
2813}
2814
2815/************* Begin ethtool support *************************/
2816
2817struct mv643xx_stats {
2818 char stat_string[ETH_GSTRING_LEN];
2819 int sizeof_stat;
2820 int stat_offset;
2821};
2822
2823#define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2824 offsetof(struct mv643xx_private, m)
2825
2826static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2827 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2828 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2829 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2830 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2831 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2832 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2833 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2834 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2835 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2836 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2837 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2838 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2839 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2840 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2841 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2842 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2843 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2844 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2845 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2846 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2847 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2848 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2849 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2850 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2851 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2852 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2853 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2854 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2855 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2856 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2857 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2858 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2859 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2860 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2861 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2862 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2863 { "collision", MV643XX_STAT(mib_counters.collision) },
2864 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2865};
2866
2867#define MV643XX_STATS_LEN \
2868 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2869
2870static int
2871mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2872{
2873 struct mv643xx_private *mp = netdev->priv;
2874 int port_num = mp->port_num;
2875 int autoneg = eth_port_autoneg_supported(port_num);
2876 int mode_10_bit;
2877 int auto_duplex;
2878 int half_duplex = 0;
2879 int full_duplex = 0;
2880 int auto_speed;
2881 int speed_10 = 0;
2882 int speed_100 = 0;
2883 int speed_1000 = 0;
2884
2885 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2886 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
2887
2888 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
2889
2890 if (mode_10_bit) {
2891 ecmd->supported = SUPPORTED_10baseT_Half;
2892 } else {
2893 ecmd->supported = (SUPPORTED_10baseT_Half |
2894 SUPPORTED_10baseT_Full |
2895 SUPPORTED_100baseT_Half |
2896 SUPPORTED_100baseT_Full |
2897 SUPPORTED_1000baseT_Full |
2898 (autoneg ? SUPPORTED_Autoneg : 0) |
2899 SUPPORTED_TP);
2900
2901 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
2902 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
2903
2904 ecmd->advertising = ADVERTISED_TP;
2905
2906 if (autoneg) {
2907 ecmd->advertising |= ADVERTISED_Autoneg;
2908
2909 if (auto_duplex) {
2910 half_duplex = 1;
2911 full_duplex = 1;
2912 } else {
2913 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
2914 full_duplex = 1;
2915 else
2916 half_duplex = 1;
2917 }
2918
2919 if (auto_speed) {
2920 speed_10 = 1;
2921 speed_100 = 1;
2922 speed_1000 = 1;
2923 } else {
2924 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
2925 speed_1000 = 1;
2926 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
2927 speed_100 = 1;
2928 else
2929 speed_10 = 1;
2930 }
2931
2932 if (speed_10 & half_duplex)
2933 ecmd->advertising |= ADVERTISED_10baseT_Half;
2934 if (speed_10 & full_duplex)
2935 ecmd->advertising |= ADVERTISED_10baseT_Full;
2936 if (speed_100 & half_duplex)
2937 ecmd->advertising |= ADVERTISED_100baseT_Half;
2938 if (speed_100 & full_duplex)
2939 ecmd->advertising |= ADVERTISED_100baseT_Full;
2940 if (speed_1000)
2941 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2942 }
2943 }
2944
2945 ecmd->port = PORT_TP;
2946 ecmd->phy_address = ethernet_phy_get(port_num);
2947
2948 ecmd->transceiver = XCVR_EXTERNAL;
2949
2950 if (netif_carrier_ok(netdev)) {
2951 if (mode_10_bit)
2952 ecmd->speed = SPEED_10;
2953 else {
2954 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
2955 ecmd->speed = SPEED_1000;
2956 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
2957 ecmd->speed = SPEED_100;
2958 else
2959 ecmd->speed = SPEED_10;
2960 }
2961
2962 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
2963 ecmd->duplex = DUPLEX_FULL;
2964 else
2965 ecmd->duplex = DUPLEX_HALF;
2966 } else {
2967 ecmd->speed = -1;
2968 ecmd->duplex = -1;
2969 }
2970
2971 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2972 return 0;
2973}
2974
2975static void
2976mv643xx_get_drvinfo(struct net_device *netdev,
2977 struct ethtool_drvinfo *drvinfo)
2978{
2979 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2980 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2981 strncpy(drvinfo->fw_version, "N/A", 32);
2982 strncpy(drvinfo->bus_info, "mv643xx", 32);
2983 drvinfo->n_stats = MV643XX_STATS_LEN;
2984}
2985
2986static int
2987mv643xx_get_stats_count(struct net_device *netdev)
2988{
2989 return MV643XX_STATS_LEN;
2990}
2991
2992static void
2993mv643xx_get_ethtool_stats(struct net_device *netdev,
2994 struct ethtool_stats *stats, uint64_t *data)
2995{
2996 struct mv643xx_private *mp = netdev->priv;
2997 int i;
2998
2999 eth_update_mib_counters(mp);
3000
3001 for(i = 0; i < MV643XX_STATS_LEN; i++) {
3002 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
3003 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
3004 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3005 }
3006}
3007
3008static void
3009mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
3010{
3011 int i;
3012
3013 switch(stringset) {
3014 case ETH_SS_STATS:
3015 for (i=0; i < MV643XX_STATS_LEN; i++) {
3016 memcpy(data + i * ETH_GSTRING_LEN,
3017 mv643xx_gstrings_stats[i].stat_string,
3018 ETH_GSTRING_LEN);
3019 }
3020 break;
3021 }
3022}
3023
3024static struct ethtool_ops mv643xx_ethtool_ops = {
3025 .get_settings = mv643xx_get_settings,
3026 .get_drvinfo = mv643xx_get_drvinfo,
3027 .get_link = ethtool_op_get_link,
3028 .get_sg = ethtool_op_get_sg,
3029 .set_sg = ethtool_op_set_sg,
3030 .get_strings = mv643xx_get_strings,
3031 .get_stats_count = mv643xx_get_stats_count,
3032 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3033};
3034
3035/************* End ethtool support *************************/
Linux kernel - Deliverables
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