Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
1da177e4 LT |
41 | #include <linux/tcp.h> |
42 | #include <linux/udp.h> | |
43 | #include <linux/etherdevice.h> | |
1da177e4 LT |
44 | #include <linux/delay.h> |
45 | #include <linux/ethtool.h> | |
d052d1be | 46 | #include <linux/platform_device.h> |
fbd6a754 LB |
47 | #include <linux/module.h> |
48 | #include <linux/kernel.h> | |
49 | #include <linux/spinlock.h> | |
50 | #include <linux/workqueue.h> | |
51 | #include <linux/mii.h> | |
fbd6a754 | 52 | #include <linux/mv643xx_eth.h> |
1da177e4 LT |
53 | #include <asm/io.h> |
54 | #include <asm/types.h> | |
1da177e4 | 55 | #include <asm/system.h> |
fbd6a754 | 56 | |
c9df406f LB |
57 | static char mv643xx_driver_name[] = "mv643xx_eth"; |
58 | static char mv643xx_driver_version[] = "1.0"; | |
59 | ||
fbd6a754 LB |
60 | #define MV643XX_CHECKSUM_OFFLOAD_TX |
61 | #define MV643XX_NAPI | |
62 | #define MV643XX_TX_FAST_REFILL | |
63 | #undef MV643XX_COAL | |
64 | ||
fbd6a754 LB |
65 | #define MV643XX_TX_COAL 100 |
66 | #ifdef MV643XX_COAL | |
67 | #define MV643XX_RX_COAL 100 | |
68 | #endif | |
69 | ||
70 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX | |
71 | #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) | |
72 | #else | |
73 | #define MAX_DESCS_PER_SKB 1 | |
74 | #endif | |
75 | ||
76 | #define ETH_VLAN_HLEN 4 | |
77 | #define ETH_FCS_LEN 4 | |
78 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ | |
79 | #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ | |
80 | ETH_VLAN_HLEN + ETH_FCS_LEN) | |
81 | #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \ | |
82 | dma_get_cache_alignment()) | |
83 | ||
84 | /* | |
85 | * Registers shared between all ports. | |
86 | */ | |
3cb4667c LB |
87 | #define PHY_ADDR 0x0000 |
88 | #define SMI_REG 0x0004 | |
89 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) | |
90 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
91 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
92 | #define WINDOW_BAR_ENABLE 0x0290 | |
93 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
94 | |
95 | /* | |
96 | * Per-port registers. | |
97 | */ | |
3cb4667c | 98 | #define PORT_CONFIG(p) (0x0400 + ((p) << 10)) |
d9a073ea | 99 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
3cb4667c LB |
100 | #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10)) |
101 | #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) | |
102 | #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) | |
103 | #define SDMA_CONFIG(p) (0x041c + ((p) << 10)) | |
104 | #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) | |
105 | #define PORT_STATUS(p) (0x0444 + ((p) << 10)) | |
a2a41689 | 106 | #define TX_FIFO_EMPTY 0x00000400 |
3cb4667c LB |
107 | #define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) |
108 | #define TX_BW_MTU(p) (0x0458 + ((p) << 10)) | |
109 | #define INT_CAUSE(p) (0x0460 + ((p) << 10)) | |
073a345c LB |
110 | #define INT_RX 0x00000804 |
111 | #define INT_EXT 0x00000002 | |
3cb4667c | 112 | #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10)) |
073a345c LB |
113 | #define INT_EXT_LINK 0x00100000 |
114 | #define INT_EXT_PHY 0x00010000 | |
115 | #define INT_EXT_TX_ERROR_0 0x00000100 | |
116 | #define INT_EXT_TX_0 0x00000001 | |
117 | #define INT_EXT_TX 0x00000101 | |
3cb4667c LB |
118 | #define INT_MASK(p) (0x0468 + ((p) << 10)) |
119 | #define INT_MASK_EXT(p) (0x046c + ((p) << 10)) | |
120 | #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10)) | |
121 | #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10)) | |
122 | #define RXQ_COMMAND(p) (0x0680 + ((p) << 10)) | |
123 | #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10)) | |
124 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) | |
125 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
126 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
127 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 128 | |
2679a550 LB |
129 | |
130 | /* | |
131 | * SDMA configuration register. | |
132 | */ | |
fbd6a754 | 133 | #define RX_BURST_SIZE_4_64BIT (2 << 1) |
fbd6a754 | 134 | #define BLM_RX_NO_SWAP (1 << 4) |
fbd6a754 | 135 | #define BLM_TX_NO_SWAP (1 << 5) |
fbd6a754 | 136 | #define TX_BURST_SIZE_4_64BIT (2 << 22) |
fbd6a754 LB |
137 | |
138 | #if defined(__BIG_ENDIAN) | |
139 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
140 | RX_BURST_SIZE_4_64BIT | \ | |
fbd6a754 LB |
141 | TX_BURST_SIZE_4_64BIT |
142 | #elif defined(__LITTLE_ENDIAN) | |
143 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
144 | RX_BURST_SIZE_4_64BIT | \ | |
145 | BLM_RX_NO_SWAP | \ | |
146 | BLM_TX_NO_SWAP | \ | |
fbd6a754 LB |
147 | TX_BURST_SIZE_4_64BIT |
148 | #else | |
149 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
150 | #endif | |
151 | ||
2beff77b LB |
152 | |
153 | /* | |
154 | * Port serial control register. | |
155 | */ | |
156 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
157 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | |
158 | #define SET_FULL_DUPLEX_MODE (1 << 21) | |
fbd6a754 | 159 | #define MAX_RX_PACKET_1522BYTE (1 << 17) |
fbd6a754 LB |
160 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
161 | #define MAX_RX_PACKET_MASK (7 << 17) | |
2beff77b LB |
162 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
163 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | |
164 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | |
165 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | |
166 | #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) | |
167 | #define FORCE_LINK_PASS (1 << 1) | |
168 | #define SERIAL_PORT_ENABLE (1 << 0) | |
fbd6a754 | 169 | |
fbd6a754 LB |
170 | #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 |
171 | #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 | |
172 | ||
fbd6a754 LB |
173 | /* SMI reg */ |
174 | #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */ | |
175 | #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */ | |
176 | #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */ | |
177 | #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */ | |
178 | ||
179 | /* Interrupt Cause Register Bit Definitions */ | |
180 | ||
181 | /* SDMA command status fields macros */ | |
182 | ||
183 | /* Tx & Rx descriptors status */ | |
184 | #define ETH_ERROR_SUMMARY 0x00000001 | |
185 | ||
186 | /* Tx & Rx descriptors command */ | |
187 | #define ETH_BUFFER_OWNED_BY_DMA 0x80000000 | |
188 | ||
189 | /* Tx descriptors status */ | |
190 | #define ETH_LC_ERROR 0 | |
191 | #define ETH_UR_ERROR 0x00000002 | |
192 | #define ETH_RL_ERROR 0x00000004 | |
193 | #define ETH_LLC_SNAP_FORMAT 0x00000200 | |
194 | ||
195 | /* Rx descriptors status */ | |
196 | #define ETH_OVERRUN_ERROR 0x00000002 | |
197 | #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004 | |
198 | #define ETH_RESOURCE_ERROR 0x00000006 | |
199 | #define ETH_VLAN_TAGGED 0x00080000 | |
200 | #define ETH_BPDU_FRAME 0x00100000 | |
201 | #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000 | |
202 | #define ETH_OTHER_FRAME_TYPE 0x00400000 | |
203 | #define ETH_LAYER_2_IS_ETH_V_2 0x00800000 | |
204 | #define ETH_FRAME_TYPE_IP_V_4 0x01000000 | |
205 | #define ETH_FRAME_HEADER_OK 0x02000000 | |
206 | #define ETH_RX_LAST_DESC 0x04000000 | |
207 | #define ETH_RX_FIRST_DESC 0x08000000 | |
208 | #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000 | |
209 | #define ETH_RX_ENABLE_INTERRUPT 0x20000000 | |
210 | #define ETH_LAYER_4_CHECKSUM_OK 0x40000000 | |
211 | ||
212 | /* Rx descriptors byte count */ | |
213 | #define ETH_FRAME_FRAGMENTED 0x00000004 | |
214 | ||
215 | /* Tx descriptors command */ | |
216 | #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400 | |
217 | #define ETH_FRAME_SET_TO_VLAN 0x00008000 | |
218 | #define ETH_UDP_FRAME 0x00010000 | |
219 | #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000 | |
220 | #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000 | |
221 | #define ETH_ZERO_PADDING 0x00080000 | |
222 | #define ETH_TX_LAST_DESC 0x00100000 | |
223 | #define ETH_TX_FIRST_DESC 0x00200000 | |
224 | #define ETH_GEN_CRC 0x00400000 | |
225 | #define ETH_TX_ENABLE_INTERRUPT 0x00800000 | |
226 | #define ETH_AUTO_MODE 0x40000000 | |
227 | ||
228 | #define ETH_TX_IHL_SHIFT 11 | |
229 | ||
230 | /* typedefs */ | |
231 | ||
232 | typedef enum _eth_func_ret_status { | |
233 | ETH_OK, /* Returned as expected. */ | |
234 | ETH_ERROR, /* Fundamental error. */ | |
235 | ETH_RETRY, /* Could not process request. Try later.*/ | |
236 | ETH_END_OF_JOB, /* Ring has nothing to process. */ | |
237 | ETH_QUEUE_FULL, /* Ring resource error. */ | |
238 | ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ | |
239 | } ETH_FUNC_RET_STATUS; | |
240 | ||
fbd6a754 LB |
241 | /* These are for big-endian machines. Little endian needs different |
242 | * definitions. | |
243 | */ | |
244 | #if defined(__BIG_ENDIAN) | |
245 | struct eth_rx_desc { | |
246 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
247 | u16 buf_size; /* Buffer size */ | |
248 | u32 cmd_sts; /* Descriptor command status */ | |
249 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
250 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
251 | }; | |
252 | ||
253 | struct eth_tx_desc { | |
254 | u16 byte_cnt; /* buffer byte count */ | |
255 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
256 | u32 cmd_sts; /* Command/status field */ | |
257 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
258 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
259 | }; | |
260 | #elif defined(__LITTLE_ENDIAN) | |
261 | struct eth_rx_desc { | |
262 | u32 cmd_sts; /* Descriptor command status */ | |
263 | u16 buf_size; /* Buffer size */ | |
264 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
265 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
266 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
267 | }; | |
268 | ||
269 | struct eth_tx_desc { | |
270 | u32 cmd_sts; /* Command/status field */ | |
271 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
272 | u16 byte_cnt; /* buffer byte count */ | |
273 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
274 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
275 | }; | |
276 | #else | |
277 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
278 | #endif | |
279 | ||
280 | /* Unified struct for Rx and Tx operations. The user is not required to */ | |
281 | /* be familier with neither Tx nor Rx descriptors. */ | |
282 | struct pkt_info { | |
283 | unsigned short byte_cnt; /* Descriptor buffer byte count */ | |
284 | unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ | |
285 | unsigned int cmd_sts; /* Descriptor command status */ | |
286 | dma_addr_t buf_ptr; /* Descriptor buffer pointer */ | |
287 | struct sk_buff *return_info; /* User resource return information */ | |
288 | }; | |
289 | ||
c9df406f LB |
290 | |
291 | /* global *******************************************************************/ | |
292 | struct mv643xx_shared_private { | |
293 | void __iomem *eth_base; | |
294 | ||
295 | /* used to protect SMI_REG, which is shared across ports */ | |
296 | spinlock_t phy_lock; | |
297 | ||
298 | u32 win_protect; | |
299 | ||
300 | unsigned int t_clk; | |
301 | }; | |
302 | ||
303 | ||
304 | /* per-port *****************************************************************/ | |
fbd6a754 LB |
305 | struct mv643xx_mib_counters { |
306 | u64 good_octets_received; | |
307 | u32 bad_octets_received; | |
308 | u32 internal_mac_transmit_err; | |
309 | u32 good_frames_received; | |
310 | u32 bad_frames_received; | |
311 | u32 broadcast_frames_received; | |
312 | u32 multicast_frames_received; | |
313 | u32 frames_64_octets; | |
314 | u32 frames_65_to_127_octets; | |
315 | u32 frames_128_to_255_octets; | |
316 | u32 frames_256_to_511_octets; | |
317 | u32 frames_512_to_1023_octets; | |
318 | u32 frames_1024_to_max_octets; | |
319 | u64 good_octets_sent; | |
320 | u32 good_frames_sent; | |
321 | u32 excessive_collision; | |
322 | u32 multicast_frames_sent; | |
323 | u32 broadcast_frames_sent; | |
324 | u32 unrec_mac_control_received; | |
325 | u32 fc_sent; | |
326 | u32 good_fc_received; | |
327 | u32 bad_fc_received; | |
328 | u32 undersize_received; | |
329 | u32 fragments_received; | |
330 | u32 oversize_received; | |
331 | u32 jabber_received; | |
332 | u32 mac_receive_error; | |
333 | u32 bad_crc_event; | |
334 | u32 collision; | |
335 | u32 late_collision; | |
336 | }; | |
337 | ||
338 | struct mv643xx_private { | |
fa3959f4 | 339 | struct mv643xx_shared_private *shared; |
fbd6a754 LB |
340 | int port_num; /* User Ethernet port number */ |
341 | ||
ce4e2e45 LB |
342 | struct mv643xx_shared_private *shared_smi; |
343 | ||
fbd6a754 LB |
344 | u32 rx_sram_addr; /* Base address of rx sram area */ |
345 | u32 rx_sram_size; /* Size of rx sram area */ | |
346 | u32 tx_sram_addr; /* Base address of tx sram area */ | |
347 | u32 tx_sram_size; /* Size of tx sram area */ | |
348 | ||
349 | int rx_resource_err; /* Rx ring resource error flag */ | |
350 | ||
351 | /* Tx/Rx rings managment indexes fields. For driver use */ | |
352 | ||
353 | /* Next available and first returning Rx resource */ | |
354 | int rx_curr_desc_q, rx_used_desc_q; | |
355 | ||
356 | /* Next available and first returning Tx resource */ | |
357 | int tx_curr_desc_q, tx_used_desc_q; | |
358 | ||
359 | #ifdef MV643XX_TX_FAST_REFILL | |
360 | u32 tx_clean_threshold; | |
361 | #endif | |
362 | ||
363 | struct eth_rx_desc *p_rx_desc_area; | |
364 | dma_addr_t rx_desc_dma; | |
365 | int rx_desc_area_size; | |
366 | struct sk_buff **rx_skb; | |
367 | ||
368 | struct eth_tx_desc *p_tx_desc_area; | |
369 | dma_addr_t tx_desc_dma; | |
370 | int tx_desc_area_size; | |
371 | struct sk_buff **tx_skb; | |
372 | ||
373 | struct work_struct tx_timeout_task; | |
374 | ||
375 | struct net_device *dev; | |
376 | struct napi_struct napi; | |
377 | struct net_device_stats stats; | |
378 | struct mv643xx_mib_counters mib_counters; | |
379 | spinlock_t lock; | |
380 | /* Size of Tx Ring per queue */ | |
381 | int tx_ring_size; | |
382 | /* Number of tx descriptors in use */ | |
383 | int tx_desc_count; | |
384 | /* Size of Rx Ring per queue */ | |
385 | int rx_ring_size; | |
386 | /* Number of rx descriptors in use */ | |
387 | int rx_desc_count; | |
388 | ||
389 | /* | |
390 | * Used in case RX Ring is empty, which can be caused when | |
391 | * system does not have resources (skb's) | |
392 | */ | |
393 | struct timer_list timeout; | |
394 | ||
395 | u32 rx_int_coal; | |
396 | u32 tx_int_coal; | |
397 | struct mii_if_info mii; | |
398 | }; | |
1da177e4 | 399 | |
fbd6a754 | 400 | |
c9df406f LB |
401 | /* port register accessors **************************************************/ |
402 | static inline u32 rdl(struct mv643xx_private *mp, int offset) | |
403 | { | |
404 | return readl(mp->shared->eth_base + offset); | |
405 | } | |
fbd6a754 | 406 | |
c9df406f LB |
407 | static inline void wrl(struct mv643xx_private *mp, int offset, u32 data) |
408 | { | |
409 | writel(data, mp->shared->eth_base + offset); | |
410 | } | |
fbd6a754 | 411 | |
fbd6a754 | 412 | |
c9df406f LB |
413 | /* rxq/txq helper functions *************************************************/ |
414 | static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp, | |
415 | unsigned int queues) | |
416 | { | |
3cb4667c | 417 | wrl(mp, RXQ_COMMAND(mp->port_num), queues); |
c9df406f | 418 | } |
fbd6a754 | 419 | |
c9df406f LB |
420 | static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp) |
421 | { | |
422 | unsigned int port_num = mp->port_num; | |
423 | u32 queues; | |
fbd6a754 | 424 | |
c9df406f | 425 | /* Stop Rx port activity. Check port Rx activity. */ |
3cb4667c | 426 | queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF; |
c9df406f LB |
427 | if (queues) { |
428 | /* Issue stop command for active queues only */ | |
3cb4667c | 429 | wrl(mp, RXQ_COMMAND(port_num), (queues << 8)); |
1da177e4 | 430 | |
c9df406f LB |
431 | /* Wait for all Rx activity to terminate. */ |
432 | /* Check port cause register that all Rx queues are stopped */ | |
3cb4667c | 433 | while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF) |
e1bea50a | 434 | udelay(10); |
c9df406f | 435 | } |
1da177e4 | 436 | |
c9df406f LB |
437 | return queues; |
438 | } | |
439 | ||
440 | static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp, | |
441 | unsigned int queues) | |
1da177e4 | 442 | { |
3cb4667c | 443 | wrl(mp, TXQ_COMMAND(mp->port_num), queues); |
1da177e4 LT |
444 | } |
445 | ||
c9df406f | 446 | static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp) |
1da177e4 | 447 | { |
c9df406f LB |
448 | unsigned int port_num = mp->port_num; |
449 | u32 queues; | |
450 | ||
451 | /* Stop Tx port activity. Check port Tx activity. */ | |
3cb4667c | 452 | queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF; |
c9df406f LB |
453 | if (queues) { |
454 | /* Issue stop command for active queues only */ | |
3cb4667c | 455 | wrl(mp, TXQ_COMMAND(port_num), (queues << 8)); |
c9df406f LB |
456 | |
457 | /* Wait for all Tx activity to terminate. */ | |
458 | /* Check port cause register that all Tx queues are stopped */ | |
3cb4667c | 459 | while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF) |
e1bea50a | 460 | udelay(10); |
c9df406f LB |
461 | |
462 | /* Wait for Tx FIFO to empty */ | |
a2a41689 | 463 | while (rdl(mp, PORT_STATUS(port_num)) & TX_FIFO_EMPTY) |
e1bea50a | 464 | udelay(10); |
c9df406f LB |
465 | } |
466 | ||
467 | return queues; | |
1da177e4 LT |
468 | } |
469 | ||
c9df406f LB |
470 | |
471 | /* rx ***********************************************************************/ | |
472 | static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev); | |
473 | ||
1da177e4 | 474 | /* |
c9df406f | 475 | * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. |
1da177e4 | 476 | * |
c9df406f LB |
477 | * DESCRIPTION: |
478 | * This routine returns a Rx buffer back to the Rx ring. It retrieves the | |
479 | * next 'used' descriptor and attached the returned buffer to it. | |
480 | * In case the Rx ring was in "resource error" condition, where there are | |
481 | * no available Rx resources, the function resets the resource error flag. | |
482 | * | |
483 | * INPUT: | |
484 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
485 | * struct pkt_info *p_pkt_info Information on returned buffer. | |
486 | * | |
487 | * OUTPUT: | |
488 | * New available Rx resource in Rx descriptor ring. | |
489 | * | |
490 | * RETURN: | |
491 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
492 | * ETH_OK otherwise. | |
1da177e4 | 493 | */ |
c9df406f LB |
494 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, |
495 | struct pkt_info *p_pkt_info) | |
1da177e4 | 496 | { |
c9df406f LB |
497 | int used_rx_desc; /* Where to return Rx resource */ |
498 | volatile struct eth_rx_desc *p_used_rx_desc; | |
499 | unsigned long flags; | |
1da177e4 | 500 | |
c9df406f | 501 | spin_lock_irqsave(&mp->lock, flags); |
c0d0f2ca | 502 | |
c9df406f LB |
503 | /* Get 'used' Rx descriptor */ |
504 | used_rx_desc = mp->rx_used_desc_q; | |
505 | p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc]; | |
1da177e4 | 506 | |
c9df406f LB |
507 | p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; |
508 | p_used_rx_desc->buf_size = p_pkt_info->byte_cnt; | |
509 | mp->rx_skb[used_rx_desc] = p_pkt_info->return_info; | |
510 | ||
511 | /* Flush the write pipe */ | |
512 | ||
513 | /* Return the descriptor to DMA ownership */ | |
514 | wmb(); | |
515 | p_used_rx_desc->cmd_sts = | |
516 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; | |
517 | wmb(); | |
518 | ||
519 | /* Move the used descriptor pointer to the next descriptor */ | |
520 | mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size; | |
521 | ||
522 | /* Any Rx return cancels the Rx resource error status */ | |
523 | mp->rx_resource_err = 0; | |
524 | ||
525 | spin_unlock_irqrestore(&mp->lock, flags); | |
526 | ||
527 | return ETH_OK; | |
1da177e4 LT |
528 | } |
529 | ||
530 | /* | |
f78fb474 | 531 | * mv643xx_eth_rx_refill_descs |
1da177e4 LT |
532 | * |
533 | * Fills / refills RX queue on a certain gigabit ethernet port | |
534 | * | |
535 | * Input : pointer to ethernet interface network device structure | |
536 | * Output : N/A | |
537 | */ | |
f78fb474 | 538 | static void mv643xx_eth_rx_refill_descs(struct net_device *dev) |
1da177e4 | 539 | { |
1da177e4 LT |
540 | struct mv643xx_private *mp = netdev_priv(dev); |
541 | struct pkt_info pkt_info; | |
542 | struct sk_buff *skb; | |
b44cd572 | 543 | int unaligned; |
1da177e4 | 544 | |
f78fb474 | 545 | while (mp->rx_desc_count < mp->rx_ring_size) { |
908b637f | 546 | skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment()); |
1da177e4 LT |
547 | if (!skb) |
548 | break; | |
f98e36f1 | 549 | mp->rx_desc_count++; |
908b637f | 550 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
b44cd572 | 551 | if (unaligned) |
908b637f | 552 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); |
1da177e4 | 553 | pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT; |
7303fde8 DF |
554 | pkt_info.byte_cnt = ETH_RX_SKB_SIZE; |
555 | pkt_info.buf_ptr = dma_map_single(NULL, skb->data, | |
556 | ETH_RX_SKB_SIZE, DMA_FROM_DEVICE); | |
1da177e4 LT |
557 | pkt_info.return_info = skb; |
558 | if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) { | |
559 | printk(KERN_ERR | |
560 | "%s: Error allocating RX Ring\n", dev->name); | |
561 | break; | |
562 | } | |
7303fde8 | 563 | skb_reserve(skb, ETH_HW_IP_ALIGN); |
1da177e4 | 564 | } |
1da177e4 LT |
565 | /* |
566 | * If RX ring is empty of SKB, set a timer to try allocating | |
f78fb474 | 567 | * again at a later time. |
1da177e4 | 568 | */ |
f78fb474 | 569 | if (mp->rx_desc_count == 0) { |
1da177e4 | 570 | printk(KERN_INFO "%s: Rx ring is empty\n", dev->name); |
f78fb474 | 571 | mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */ |
1da177e4 | 572 | add_timer(&mp->timeout); |
1da177e4 | 573 | } |
1da177e4 LT |
574 | } |
575 | ||
576 | /* | |
f78fb474 | 577 | * mv643xx_eth_rx_refill_descs_timer_wrapper |
1da177e4 LT |
578 | * |
579 | * Timer routine to wake up RX queue filling task. This function is | |
580 | * used only in case the RX queue is empty, and all alloc_skb has | |
581 | * failed (due to out of memory event). | |
582 | * | |
583 | * Input : pointer to ethernet interface network device structure | |
584 | * Output : N/A | |
585 | */ | |
f78fb474 | 586 | static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data) |
1da177e4 | 587 | { |
f78fb474 | 588 | mv643xx_eth_rx_refill_descs((struct net_device *)data); |
1da177e4 LT |
589 | } |
590 | ||
591 | /* | |
c9df406f | 592 | * eth_port_receive - Get received information from Rx ring. |
1da177e4 | 593 | * |
c9df406f LB |
594 | * DESCRIPTION: |
595 | * This routine returns the received data to the caller. There is no | |
596 | * data copying during routine operation. All information is returned | |
597 | * using pointer to packet information struct passed from the caller. | |
598 | * If the routine exhausts Rx ring resources then the resource error flag | |
599 | * is set. | |
1da177e4 | 600 | * |
c9df406f LB |
601 | * INPUT: |
602 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
603 | * struct pkt_info *p_pkt_info User packet buffer. | |
1da177e4 | 604 | * |
c9df406f LB |
605 | * OUTPUT: |
606 | * Rx ring current and used indexes are updated. | |
1da177e4 | 607 | * |
c9df406f LB |
608 | * RETURN: |
609 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
610 | * ETH_QUEUE_FULL if Rx ring resources are exhausted. | |
611 | * ETH_END_OF_JOB if there is no received data. | |
612 | * ETH_OK otherwise. | |
1da177e4 | 613 | */ |
c9df406f LB |
614 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, |
615 | struct pkt_info *p_pkt_info) | |
1da177e4 | 616 | { |
c9df406f LB |
617 | int rx_next_curr_desc, rx_curr_desc, rx_used_desc; |
618 | volatile struct eth_rx_desc *p_rx_desc; | |
619 | unsigned int command_status; | |
620 | unsigned long flags; | |
1da177e4 | 621 | |
c9df406f LB |
622 | /* Do not process Rx ring in case of Rx ring resource error */ |
623 | if (mp->rx_resource_err) | |
624 | return ETH_QUEUE_FULL; | |
16e03018 | 625 | |
c9df406f | 626 | spin_lock_irqsave(&mp->lock, flags); |
1da177e4 | 627 | |
c9df406f LB |
628 | /* Get the Rx Desc ring 'curr and 'used' indexes */ |
629 | rx_curr_desc = mp->rx_curr_desc_q; | |
630 | rx_used_desc = mp->rx_used_desc_q; | |
1da177e4 | 631 | |
c9df406f | 632 | p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc]; |
1da177e4 | 633 | |
c9df406f LB |
634 | /* The following parameters are used to save readings from memory */ |
635 | command_status = p_rx_desc->cmd_sts; | |
636 | rmb(); | |
1da177e4 | 637 | |
c9df406f LB |
638 | /* Nothing to receive... */ |
639 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { | |
d344bff9 | 640 | spin_unlock_irqrestore(&mp->lock, flags); |
c9df406f LB |
641 | return ETH_END_OF_JOB; |
642 | } | |
d344bff9 | 643 | |
0a6cf74d | 644 | p_pkt_info->byte_cnt = p_rx_desc->byte_cnt - ETH_HW_IP_ALIGN; |
c9df406f | 645 | p_pkt_info->cmd_sts = command_status; |
0a6cf74d | 646 | p_pkt_info->buf_ptr = p_rx_desc->buf_ptr + ETH_HW_IP_ALIGN; |
c9df406f LB |
647 | p_pkt_info->return_info = mp->rx_skb[rx_curr_desc]; |
648 | p_pkt_info->l4i_chk = p_rx_desc->buf_size; | |
ff561eef | 649 | |
c9df406f LB |
650 | /* |
651 | * Clean the return info field to indicate that the | |
652 | * packet has been moved to the upper layers | |
653 | */ | |
654 | mp->rx_skb[rx_curr_desc] = NULL; | |
1da177e4 | 655 | |
c9df406f LB |
656 | /* Update current index in data structure */ |
657 | rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size; | |
658 | mp->rx_curr_desc_q = rx_next_curr_desc; | |
1da177e4 | 659 | |
c9df406f LB |
660 | /* Rx descriptors exhausted. Set the Rx ring resource error flag */ |
661 | if (rx_next_curr_desc == rx_used_desc) | |
662 | mp->rx_resource_err = 1; | |
ff561eef | 663 | |
c9df406f | 664 | spin_unlock_irqrestore(&mp->lock, flags); |
ff561eef | 665 | |
c9df406f | 666 | return ETH_OK; |
ff561eef DF |
667 | } |
668 | ||
1da177e4 LT |
669 | /* |
670 | * mv643xx_eth_receive | |
671 | * | |
672 | * This function is forward packets that are received from the port's | |
673 | * queues toward kernel core or FastRoute them to another interface. | |
674 | * | |
675 | * Input : dev - a pointer to the required interface | |
676 | * max - maximum number to receive (0 means unlimted) | |
677 | * | |
678 | * Output : number of served packets | |
679 | */ | |
1da177e4 | 680 | static int mv643xx_eth_receive_queue(struct net_device *dev, int budget) |
1da177e4 LT |
681 | { |
682 | struct mv643xx_private *mp = netdev_priv(dev); | |
09f75cd7 | 683 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
684 | unsigned int received_packets = 0; |
685 | struct sk_buff *skb; | |
686 | struct pkt_info pkt_info; | |
687 | ||
b1dd9ca1 | 688 | while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) { |
54caf44d | 689 | dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE, |
71d28725 | 690 | DMA_FROM_DEVICE); |
f98e36f1 | 691 | mp->rx_desc_count--; |
1da177e4 | 692 | received_packets++; |
b1dd9ca1 | 693 | |
468d09f8 DF |
694 | /* |
695 | * Update statistics. | |
696 | * Note byte count includes 4 byte CRC count | |
697 | */ | |
1da177e4 LT |
698 | stats->rx_packets++; |
699 | stats->rx_bytes += pkt_info.byte_cnt; | |
700 | skb = pkt_info.return_info; | |
701 | /* | |
702 | * In case received a packet without first / last bits on OR | |
703 | * the error summary bit is on, the packets needs to be dropeed. | |
704 | */ | |
705 | if (((pkt_info.cmd_sts | |
706 | & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != | |
707 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) | |
708 | || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { | |
709 | stats->rx_dropped++; | |
710 | if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC | | |
711 | ETH_RX_LAST_DESC)) != | |
712 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) { | |
713 | if (net_ratelimit()) | |
714 | printk(KERN_ERR | |
715 | "%s: Received packet spread " | |
716 | "on multiple descriptors\n", | |
717 | dev->name); | |
718 | } | |
719 | if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) | |
720 | stats->rx_errors++; | |
721 | ||
722 | dev_kfree_skb_irq(skb); | |
723 | } else { | |
724 | /* | |
725 | * The -4 is for the CRC in the trailer of the | |
726 | * received packet | |
727 | */ | |
728 | skb_put(skb, pkt_info.byte_cnt - 4); | |
1da177e4 LT |
729 | |
730 | if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) { | |
731 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
732 | skb->csum = htons( | |
733 | (pkt_info.cmd_sts & 0x0007fff8) >> 3); | |
734 | } | |
735 | skb->protocol = eth_type_trans(skb, dev); | |
736 | #ifdef MV643XX_NAPI | |
737 | netif_receive_skb(skb); | |
738 | #else | |
739 | netif_rx(skb); | |
740 | #endif | |
741 | } | |
12ad74f8 | 742 | dev->last_rx = jiffies; |
1da177e4 | 743 | } |
f78fb474 | 744 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
1da177e4 LT |
745 | |
746 | return received_packets; | |
747 | } | |
748 | ||
c9df406f LB |
749 | #ifdef MV643XX_NAPI |
750 | /* | |
751 | * mv643xx_poll | |
752 | * | |
753 | * This function is used in case of NAPI | |
754 | */ | |
755 | static int mv643xx_poll(struct napi_struct *napi, int budget) | |
d0412d96 | 756 | { |
c9df406f LB |
757 | struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi); |
758 | struct net_device *dev = mp->dev; | |
759 | unsigned int port_num = mp->port_num; | |
760 | int work_done; | |
d0412d96 | 761 | |
c9df406f LB |
762 | #ifdef MV643XX_TX_FAST_REFILL |
763 | if (++mp->tx_clean_threshold > 5) { | |
764 | mv643xx_eth_free_completed_tx_descs(dev); | |
765 | mp->tx_clean_threshold = 0; | |
d0412d96 | 766 | } |
c9df406f | 767 | #endif |
d0412d96 | 768 | |
c9df406f | 769 | work_done = 0; |
3cb4667c | 770 | if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num))) |
c9df406f LB |
771 | != (u32) mp->rx_used_desc_q) |
772 | work_done = mv643xx_eth_receive_queue(dev, budget); | |
d0412d96 | 773 | |
c9df406f LB |
774 | if (work_done < budget) { |
775 | netif_rx_complete(dev, napi); | |
3cb4667c LB |
776 | wrl(mp, INT_CAUSE(port_num), 0); |
777 | wrl(mp, INT_CAUSE_EXT(port_num), 0); | |
073a345c | 778 | wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT); |
d0412d96 | 779 | } |
c9df406f LB |
780 | |
781 | return work_done; | |
d0412d96 | 782 | } |
c9df406f | 783 | #endif |
d0412d96 | 784 | |
c9df406f LB |
785 | |
786 | /* tx ***********************************************************************/ | |
787 | /** | |
788 | * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments | |
1da177e4 | 789 | * |
c9df406f LB |
790 | * Hardware can't handle unaligned fragments smaller than 9 bytes. |
791 | * This helper function detects that case. | |
1da177e4 LT |
792 | */ |
793 | ||
c9df406f | 794 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 795 | { |
c9df406f LB |
796 | unsigned int frag; |
797 | skb_frag_t *fragp; | |
1da177e4 | 798 | |
c9df406f LB |
799 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
800 | fragp = &skb_shinfo(skb)->frags[frag]; | |
801 | if (fragp->size <= 8 && fragp->page_offset & 0x7) | |
802 | return 1; | |
1da177e4 | 803 | } |
c9df406f LB |
804 | return 0; |
805 | } | |
7303fde8 | 806 | |
c9df406f LB |
807 | /** |
808 | * eth_alloc_tx_desc_index - return the index of the next available tx desc | |
809 | */ | |
810 | static int eth_alloc_tx_desc_index(struct mv643xx_private *mp) | |
811 | { | |
812 | int tx_desc_curr; | |
d0412d96 | 813 | |
c9df406f | 814 | BUG_ON(mp->tx_desc_count >= mp->tx_ring_size); |
1da177e4 | 815 | |
c9df406f LB |
816 | tx_desc_curr = mp->tx_curr_desc_q; |
817 | mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size; | |
e4d00fa9 | 818 | |
c9df406f | 819 | BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q); |
468d09f8 | 820 | |
c9df406f LB |
821 | return tx_desc_curr; |
822 | } | |
468d09f8 | 823 | |
c9df406f LB |
824 | /** |
825 | * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments. | |
826 | * | |
827 | * Ensure the data for each fragment to be transmitted is mapped properly, | |
828 | * then fill in descriptors in the tx hw queue. | |
829 | */ | |
830 | static void eth_tx_fill_frag_descs(struct mv643xx_private *mp, | |
831 | struct sk_buff *skb) | |
832 | { | |
833 | int frag; | |
834 | int tx_index; | |
835 | struct eth_tx_desc *desc; | |
1da177e4 | 836 | |
c9df406f LB |
837 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
838 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; | |
839 | ||
840 | tx_index = eth_alloc_tx_desc_index(mp); | |
841 | desc = &mp->p_tx_desc_area[tx_index]; | |
842 | ||
843 | desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA; | |
844 | /* Last Frag enables interrupt and frees the skb */ | |
845 | if (frag == (skb_shinfo(skb)->nr_frags - 1)) { | |
846 | desc->cmd_sts |= ETH_ZERO_PADDING | | |
847 | ETH_TX_LAST_DESC | | |
848 | ETH_TX_ENABLE_INTERRUPT; | |
849 | mp->tx_skb[tx_index] = skb; | |
850 | } else | |
851 | mp->tx_skb[tx_index] = NULL; | |
852 | ||
853 | desc = &mp->p_tx_desc_area[tx_index]; | |
854 | desc->l4i_chk = 0; | |
855 | desc->byte_cnt = this_frag->size; | |
856 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
857 | this_frag->page_offset, | |
858 | this_frag->size, | |
859 | DMA_TO_DEVICE); | |
860 | } | |
1da177e4 LT |
861 | } |
862 | ||
c9df406f LB |
863 | static inline __be16 sum16_as_be(__sum16 sum) |
864 | { | |
865 | return (__force __be16)sum; | |
866 | } | |
1da177e4 | 867 | |
c9df406f LB |
868 | /** |
869 | * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw | |
1da177e4 | 870 | * |
c9df406f LB |
871 | * Ensure the data for an skb to be transmitted is mapped properly, |
872 | * then fill in descriptors in the tx hw queue and start the hardware. | |
1da177e4 | 873 | */ |
c9df406f LB |
874 | static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp, |
875 | struct sk_buff *skb) | |
1da177e4 | 876 | { |
c9df406f LB |
877 | int tx_index; |
878 | struct eth_tx_desc *desc; | |
879 | u32 cmd_sts; | |
880 | int length; | |
881 | int nr_frags = skb_shinfo(skb)->nr_frags; | |
1da177e4 | 882 | |
c9df406f | 883 | cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA; |
1da177e4 | 884 | |
c9df406f LB |
885 | tx_index = eth_alloc_tx_desc_index(mp); |
886 | desc = &mp->p_tx_desc_area[tx_index]; | |
887 | ||
888 | if (nr_frags) { | |
889 | eth_tx_fill_frag_descs(mp, skb); | |
890 | ||
891 | length = skb_headlen(skb); | |
892 | mp->tx_skb[tx_index] = NULL; | |
893 | } else { | |
894 | cmd_sts |= ETH_ZERO_PADDING | | |
895 | ETH_TX_LAST_DESC | | |
896 | ETH_TX_ENABLE_INTERRUPT; | |
897 | length = skb->len; | |
898 | mp->tx_skb[tx_index] = skb; | |
899 | } | |
900 | ||
901 | desc->byte_cnt = length; | |
902 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
903 | ||
904 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
905 | BUG_ON(skb->protocol != htons(ETH_P_IP)); | |
906 | ||
907 | cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | | |
908 | ETH_GEN_IP_V_4_CHECKSUM | | |
909 | ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; | |
910 | ||
911 | switch (ip_hdr(skb)->protocol) { | |
912 | case IPPROTO_UDP: | |
913 | cmd_sts |= ETH_UDP_FRAME; | |
914 | desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); | |
915 | break; | |
916 | case IPPROTO_TCP: | |
917 | desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); | |
918 | break; | |
919 | default: | |
920 | BUG(); | |
921 | } | |
922 | } else { | |
923 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ | |
924 | cmd_sts |= 5 << ETH_TX_IHL_SHIFT; | |
925 | desc->l4i_chk = 0; | |
926 | } | |
927 | ||
928 | /* ensure all other descriptors are written before first cmd_sts */ | |
929 | wmb(); | |
930 | desc->cmd_sts = cmd_sts; | |
931 | ||
932 | /* ensure all descriptors are written before poking hardware */ | |
933 | wmb(); | |
073a345c | 934 | mv643xx_eth_port_enable_tx(mp, 1); |
c9df406f LB |
935 | |
936 | mp->tx_desc_count += nr_frags + 1; | |
1da177e4 | 937 | } |
1da177e4 | 938 | |
c9df406f LB |
939 | /** |
940 | * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission | |
1da177e4 LT |
941 | * |
942 | */ | |
c9df406f | 943 | static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 944 | { |
c9df406f LB |
945 | struct mv643xx_private *mp = netdev_priv(dev); |
946 | struct net_device_stats *stats = &dev->stats; | |
947 | unsigned long flags; | |
afdb57a2 | 948 | |
c9df406f | 949 | BUG_ON(netif_queue_stopped(dev)); |
afdb57a2 | 950 | |
c9df406f LB |
951 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
952 | stats->tx_dropped++; | |
953 | printk(KERN_DEBUG "%s: failed to linearize tiny " | |
954 | "unaligned fragment\n", dev->name); | |
955 | return NETDEV_TX_BUSY; | |
956 | } | |
957 | ||
958 | spin_lock_irqsave(&mp->lock, flags); | |
959 | ||
960 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) { | |
961 | printk(KERN_ERR "%s: transmit with queue full\n", dev->name); | |
962 | netif_stop_queue(dev); | |
963 | spin_unlock_irqrestore(&mp->lock, flags); | |
964 | return NETDEV_TX_BUSY; | |
965 | } | |
966 | ||
967 | eth_tx_submit_descs_for_skb(mp, skb); | |
968 | stats->tx_bytes += skb->len; | |
969 | stats->tx_packets++; | |
970 | dev->trans_start = jiffies; | |
971 | ||
972 | if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) | |
973 | netif_stop_queue(dev); | |
974 | ||
975 | spin_unlock_irqrestore(&mp->lock, flags); | |
976 | ||
977 | return NETDEV_TX_OK; | |
1da177e4 LT |
978 | } |
979 | ||
c9df406f LB |
980 | |
981 | /* mii management interface *************************************************/ | |
982 | static int ethernet_phy_get(struct mv643xx_private *mp); | |
983 | ||
1da177e4 | 984 | /* |
c9df406f | 985 | * eth_port_read_smi_reg - Read PHY registers |
1da177e4 LT |
986 | * |
987 | * DESCRIPTION: | |
c9df406f LB |
988 | * This routine utilize the SMI interface to interact with the PHY in |
989 | * order to perform PHY register read. | |
1da177e4 LT |
990 | * |
991 | * INPUT: | |
c9df406f LB |
992 | * struct mv643xx_private *mp Ethernet Port. |
993 | * unsigned int phy_reg PHY register address offset. | |
994 | * unsigned int *value Register value buffer. | |
1da177e4 LT |
995 | * |
996 | * OUTPUT: | |
c9df406f | 997 | * Write the value of a specified PHY register into given buffer. |
1da177e4 LT |
998 | * |
999 | * RETURN: | |
c9df406f LB |
1000 | * false if the PHY is busy or read data is not in valid state. |
1001 | * true otherwise. | |
1002 | * | |
1da177e4 | 1003 | */ |
c9df406f LB |
1004 | static void eth_port_read_smi_reg(struct mv643xx_private *mp, |
1005 | unsigned int phy_reg, unsigned int *value) | |
1da177e4 | 1006 | { |
c9df406f LB |
1007 | void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; |
1008 | int phy_addr = ethernet_phy_get(mp); | |
1009 | unsigned long flags; | |
1da177e4 LT |
1010 | int i; |
1011 | ||
c9df406f LB |
1012 | /* the SMI register is a shared resource */ |
1013 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
1014 | ||
1015 | /* wait for the SMI register to become available */ | |
1016 | for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { | |
e1bea50a | 1017 | if (i == 1000) { |
c9df406f LB |
1018 | printk("%s: PHY busy timeout\n", mp->dev->name); |
1019 | goto out; | |
1020 | } | |
e1bea50a | 1021 | udelay(10); |
1da177e4 LT |
1022 | } |
1023 | ||
c9df406f LB |
1024 | writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ, |
1025 | smi_reg); | |
1da177e4 | 1026 | |
c9df406f LB |
1027 | /* now wait for the data to be valid */ |
1028 | for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) { | |
e1bea50a | 1029 | if (i == 1000) { |
c9df406f LB |
1030 | printk("%s: PHY read timeout\n", mp->dev->name); |
1031 | goto out; | |
1032 | } | |
e1bea50a | 1033 | udelay(10); |
c9df406f LB |
1034 | } |
1035 | ||
1036 | *value = readl(smi_reg) & 0xffff; | |
1037 | out: | |
1038 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1da177e4 LT |
1039 | } |
1040 | ||
1041 | /* | |
c9df406f | 1042 | * eth_port_write_smi_reg - Write to PHY registers |
1da177e4 LT |
1043 | * |
1044 | * DESCRIPTION: | |
c9df406f LB |
1045 | * This routine utilize the SMI interface to interact with the PHY in |
1046 | * order to perform writes to PHY registers. | |
1da177e4 LT |
1047 | * |
1048 | * INPUT: | |
c9df406f LB |
1049 | * struct mv643xx_private *mp Ethernet Port. |
1050 | * unsigned int phy_reg PHY register address offset. | |
1051 | * unsigned int value Register value. | |
1da177e4 LT |
1052 | * |
1053 | * OUTPUT: | |
c9df406f | 1054 | * Write the given value to the specified PHY register. |
1da177e4 LT |
1055 | * |
1056 | * RETURN: | |
c9df406f LB |
1057 | * false if the PHY is busy. |
1058 | * true otherwise. | |
1059 | * | |
1da177e4 | 1060 | */ |
c9df406f LB |
1061 | static void eth_port_write_smi_reg(struct mv643xx_private *mp, |
1062 | unsigned int phy_reg, unsigned int value) | |
1da177e4 | 1063 | { |
c9df406f LB |
1064 | void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG; |
1065 | int phy_addr = ethernet_phy_get(mp); | |
1066 | unsigned long flags; | |
1da177e4 LT |
1067 | int i; |
1068 | ||
c9df406f LB |
1069 | /* the SMI register is a shared resource */ |
1070 | spin_lock_irqsave(&mp->shared_smi->phy_lock, flags); | |
1071 | ||
1072 | /* wait for the SMI register to become available */ | |
1073 | for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) { | |
e1bea50a | 1074 | if (i == 1000) { |
c9df406f LB |
1075 | printk("%s: PHY busy timeout\n", mp->dev->name); |
1076 | goto out; | |
1077 | } | |
e1bea50a | 1078 | udelay(10); |
1da177e4 LT |
1079 | } |
1080 | ||
c9df406f LB |
1081 | writel((phy_addr << 16) | (phy_reg << 21) | |
1082 | ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg); | |
1083 | out: | |
1084 | spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags); | |
1085 | } | |
1da177e4 | 1086 | |
c9df406f LB |
1087 | |
1088 | /* mib counters *************************************************************/ | |
1089 | /* | |
1090 | * eth_clear_mib_counters - Clear all MIB counters | |
1091 | * | |
1092 | * DESCRIPTION: | |
1093 | * This function clears all MIB counters of a specific ethernet port. | |
1094 | * A read from the MIB counter will reset the counter. | |
1095 | * | |
1096 | * INPUT: | |
1097 | * struct mv643xx_private *mp Ethernet Port. | |
1098 | * | |
1099 | * OUTPUT: | |
1100 | * After reading all MIB counters, the counters resets. | |
1101 | * | |
1102 | * RETURN: | |
1103 | * MIB counter value. | |
1104 | * | |
1105 | */ | |
1106 | static void eth_clear_mib_counters(struct mv643xx_private *mp) | |
1107 | { | |
1108 | unsigned int port_num = mp->port_num; | |
1109 | int i; | |
1110 | ||
1111 | /* Perform dummy reads from MIB counters */ | |
4b8e3655 | 1112 | for (i = 0; i < 0x80; i += 4) |
3cb4667c | 1113 | rdl(mp, MIB_COUNTERS(port_num) + i); |
1da177e4 LT |
1114 | } |
1115 | ||
c9df406f | 1116 | static inline u32 read_mib(struct mv643xx_private *mp, int offset) |
d0412d96 | 1117 | { |
3cb4667c | 1118 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
c9df406f | 1119 | } |
d0412d96 | 1120 | |
c9df406f LB |
1121 | static void eth_update_mib_counters(struct mv643xx_private *mp) |
1122 | { | |
1123 | struct mv643xx_mib_counters *p = &mp->mib_counters; | |
4b8e3655 LB |
1124 | |
1125 | p->good_octets_received += read_mib(mp, 0x00); | |
1126 | p->good_octets_received += (u64)read_mib(mp, 0x04) << 32; | |
1127 | p->bad_octets_received += read_mib(mp, 0x08); | |
1128 | p->internal_mac_transmit_err += read_mib(mp, 0x0c); | |
1129 | p->good_frames_received += read_mib(mp, 0x10); | |
1130 | p->bad_frames_received += read_mib(mp, 0x14); | |
1131 | p->broadcast_frames_received += read_mib(mp, 0x18); | |
1132 | p->multicast_frames_received += read_mib(mp, 0x1c); | |
1133 | p->frames_64_octets += read_mib(mp, 0x20); | |
1134 | p->frames_65_to_127_octets += read_mib(mp, 0x24); | |
1135 | p->frames_128_to_255_octets += read_mib(mp, 0x28); | |
1136 | p->frames_256_to_511_octets += read_mib(mp, 0x2c); | |
1137 | p->frames_512_to_1023_octets += read_mib(mp, 0x30); | |
1138 | p->frames_1024_to_max_octets += read_mib(mp, 0x34); | |
1139 | p->good_octets_sent += read_mib(mp, 0x38); | |
1140 | p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32; | |
1141 | p->good_frames_sent += read_mib(mp, 0x40); | |
1142 | p->excessive_collision += read_mib(mp, 0x44); | |
1143 | p->multicast_frames_sent += read_mib(mp, 0x48); | |
1144 | p->broadcast_frames_sent += read_mib(mp, 0x4c); | |
1145 | p->unrec_mac_control_received += read_mib(mp, 0x50); | |
1146 | p->fc_sent += read_mib(mp, 0x54); | |
1147 | p->good_fc_received += read_mib(mp, 0x58); | |
1148 | p->bad_fc_received += read_mib(mp, 0x5c); | |
1149 | p->undersize_received += read_mib(mp, 0x60); | |
1150 | p->fragments_received += read_mib(mp, 0x64); | |
1151 | p->oversize_received += read_mib(mp, 0x68); | |
1152 | p->jabber_received += read_mib(mp, 0x6c); | |
1153 | p->mac_receive_error += read_mib(mp, 0x70); | |
1154 | p->bad_crc_event += read_mib(mp, 0x74); | |
1155 | p->collision += read_mib(mp, 0x78); | |
1156 | p->late_collision += read_mib(mp, 0x7c); | |
d0412d96 JC |
1157 | } |
1158 | ||
c9df406f LB |
1159 | |
1160 | /* ethtool ******************************************************************/ | |
1161 | struct mv643xx_stats { | |
1162 | char stat_string[ETH_GSTRING_LEN]; | |
1163 | int sizeof_stat; | |
1164 | int stat_offset; | |
1165 | }; | |
1166 | ||
1167 | #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \ | |
1168 | offsetof(struct mv643xx_private, m) | |
1169 | ||
1170 | static const struct mv643xx_stats mv643xx_gstrings_stats[] = { | |
1171 | { "rx_packets", MV643XX_STAT(stats.rx_packets) }, | |
1172 | { "tx_packets", MV643XX_STAT(stats.tx_packets) }, | |
1173 | { "rx_bytes", MV643XX_STAT(stats.rx_bytes) }, | |
1174 | { "tx_bytes", MV643XX_STAT(stats.tx_bytes) }, | |
1175 | { "rx_errors", MV643XX_STAT(stats.rx_errors) }, | |
1176 | { "tx_errors", MV643XX_STAT(stats.tx_errors) }, | |
1177 | { "rx_dropped", MV643XX_STAT(stats.rx_dropped) }, | |
1178 | { "tx_dropped", MV643XX_STAT(stats.tx_dropped) }, | |
1179 | { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) }, | |
1180 | { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) }, | |
1181 | { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) }, | |
1182 | { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) }, | |
1183 | { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) }, | |
1184 | { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) }, | |
1185 | { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) }, | |
1186 | { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) }, | |
1187 | { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) }, | |
1188 | { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) }, | |
1189 | { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) }, | |
1190 | { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) }, | |
1191 | { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) }, | |
1192 | { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) }, | |
1193 | { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) }, | |
1194 | { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) }, | |
1195 | { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) }, | |
1196 | { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) }, | |
1197 | { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) }, | |
1198 | { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) }, | |
1199 | { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) }, | |
1200 | { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) }, | |
1201 | { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) }, | |
1202 | { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) }, | |
1203 | { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) }, | |
1204 | { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) }, | |
1205 | { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) }, | |
1206 | { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) }, | |
1207 | { "collision", MV643XX_STAT(mib_counters.collision) }, | |
1208 | { "late_collision", MV643XX_STAT(mib_counters.late_collision) }, | |
1209 | }; | |
1210 | ||
1211 | #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats) | |
1212 | ||
d0412d96 JC |
1213 | static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1214 | { | |
1215 | struct mv643xx_private *mp = netdev_priv(dev); | |
1216 | int err; | |
1217 | ||
1218 | spin_lock_irq(&mp->lock); | |
1219 | err = mii_ethtool_gset(&mp->mii, cmd); | |
1220 | spin_unlock_irq(&mp->lock); | |
1221 | ||
1222 | /* The PHY may support 1000baseT_Half, but the mv643xx does not */ | |
1223 | cmd->supported &= ~SUPPORTED_1000baseT_Half; | |
1224 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1225 | ||
1226 | return err; | |
1227 | } | |
1228 | ||
c9df406f | 1229 | static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1230 | { |
1231 | struct mv643xx_private *mp = netdev_priv(dev); | |
ab4384a6 DF |
1232 | int err; |
1233 | ||
c9df406f LB |
1234 | spin_lock_irq(&mp->lock); |
1235 | err = mii_ethtool_sset(&mp->mii, cmd); | |
1236 | spin_unlock_irq(&mp->lock); | |
85cf572c | 1237 | |
c9df406f LB |
1238 | return err; |
1239 | } | |
1da177e4 | 1240 | |
c9df406f LB |
1241 | static void mv643xx_get_drvinfo(struct net_device *netdev, |
1242 | struct ethtool_drvinfo *drvinfo) | |
1243 | { | |
1244 | strncpy(drvinfo->driver, mv643xx_driver_name, 32); | |
1245 | strncpy(drvinfo->version, mv643xx_driver_version, 32); | |
1246 | strncpy(drvinfo->fw_version, "N/A", 32); | |
1247 | strncpy(drvinfo->bus_info, "mv643xx", 32); | |
1248 | drvinfo->n_stats = MV643XX_STATS_LEN; | |
1249 | } | |
1da177e4 | 1250 | |
c9df406f LB |
1251 | static int mv643xx_eth_nway_restart(struct net_device *dev) |
1252 | { | |
1253 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1254 | |
c9df406f LB |
1255 | return mii_nway_restart(&mp->mii); |
1256 | } | |
1da177e4 | 1257 | |
c9df406f LB |
1258 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
1259 | { | |
1260 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1261 | |
c9df406f LB |
1262 | return mii_link_ok(&mp->mii); |
1263 | } | |
1da177e4 | 1264 | |
c9df406f LB |
1265 | static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, |
1266 | uint8_t *data) | |
1267 | { | |
1268 | int i; | |
1da177e4 | 1269 | |
c9df406f LB |
1270 | switch(stringset) { |
1271 | case ETH_SS_STATS: | |
1272 | for (i=0; i < MV643XX_STATS_LEN; i++) { | |
1273 | memcpy(data + i * ETH_GSTRING_LEN, | |
1274 | mv643xx_gstrings_stats[i].stat_string, | |
1275 | ETH_GSTRING_LEN); | |
1276 | } | |
1277 | break; | |
1278 | } | |
1279 | } | |
1da177e4 | 1280 | |
c9df406f LB |
1281 | static void mv643xx_get_ethtool_stats(struct net_device *netdev, |
1282 | struct ethtool_stats *stats, uint64_t *data) | |
1283 | { | |
1284 | struct mv643xx_private *mp = netdev->priv; | |
1285 | int i; | |
1da177e4 | 1286 | |
c9df406f | 1287 | eth_update_mib_counters(mp); |
1da177e4 | 1288 | |
c9df406f LB |
1289 | for (i = 0; i < MV643XX_STATS_LEN; i++) { |
1290 | char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset; | |
1291 | data[i] = (mv643xx_gstrings_stats[i].sizeof_stat == | |
1292 | sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1293 | } |
c9df406f | 1294 | } |
1da177e4 | 1295 | |
c9df406f LB |
1296 | static int mv643xx_get_sset_count(struct net_device *netdev, int sset) |
1297 | { | |
1298 | switch (sset) { | |
1299 | case ETH_SS_STATS: | |
1300 | return MV643XX_STATS_LEN; | |
1301 | default: | |
1302 | return -EOPNOTSUPP; | |
1303 | } | |
1304 | } | |
1da177e4 | 1305 | |
c9df406f LB |
1306 | static const struct ethtool_ops mv643xx_ethtool_ops = { |
1307 | .get_settings = mv643xx_get_settings, | |
1308 | .set_settings = mv643xx_set_settings, | |
1309 | .get_drvinfo = mv643xx_get_drvinfo, | |
1310 | .get_link = mv643xx_eth_get_link, | |
1311 | .set_sg = ethtool_op_set_sg, | |
1312 | .get_sset_count = mv643xx_get_sset_count, | |
1313 | .get_ethtool_stats = mv643xx_get_ethtool_stats, | |
1314 | .get_strings = mv643xx_get_strings, | |
1315 | .nway_reset = mv643xx_eth_nway_restart, | |
1316 | }; | |
1da177e4 | 1317 | |
bea3348e | 1318 | |
c9df406f LB |
1319 | /* address handling *********************************************************/ |
1320 | /* | |
1321 | * eth_port_uc_addr_get - Read the MAC address from the port's hw registers | |
1322 | */ | |
1323 | static void eth_port_uc_addr_get(struct mv643xx_private *mp, | |
1324 | unsigned char *p_addr) | |
1325 | { | |
1326 | unsigned int port_num = mp->port_num; | |
1327 | unsigned int mac_h; | |
1328 | unsigned int mac_l; | |
1da177e4 | 1329 | |
c9df406f LB |
1330 | mac_h = rdl(mp, MAC_ADDR_HIGH(port_num)); |
1331 | mac_l = rdl(mp, MAC_ADDR_LOW(port_num)); | |
1da177e4 | 1332 | |
c9df406f LB |
1333 | p_addr[0] = (mac_h >> 24) & 0xff; |
1334 | p_addr[1] = (mac_h >> 16) & 0xff; | |
1335 | p_addr[2] = (mac_h >> 8) & 0xff; | |
1336 | p_addr[3] = mac_h & 0xff; | |
1337 | p_addr[4] = (mac_l >> 8) & 0xff; | |
1338 | p_addr[5] = mac_l & 0xff; | |
1339 | } | |
1da177e4 | 1340 | |
c9df406f LB |
1341 | /* |
1342 | * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables | |
1343 | * | |
1344 | * DESCRIPTION: | |
1345 | * Go through all the DA filter tables (Unicast, Special Multicast & | |
1346 | * Other Multicast) and set each entry to 0. | |
1347 | * | |
1348 | * INPUT: | |
1349 | * struct mv643xx_private *mp Ethernet Port. | |
1350 | * | |
1351 | * OUTPUT: | |
1352 | * Multicast and Unicast packets are rejected. | |
1353 | * | |
1354 | * RETURN: | |
1355 | * None. | |
1356 | */ | |
1357 | static void eth_port_init_mac_tables(struct mv643xx_private *mp) | |
1358 | { | |
1359 | unsigned int port_num = mp->port_num; | |
1360 | int table_index; | |
1da177e4 | 1361 | |
c9df406f LB |
1362 | /* Clear DA filter unicast table (Ex_dFUT) */ |
1363 | for (table_index = 0; table_index <= 0xC; table_index += 4) | |
3cb4667c | 1364 | wrl(mp, UNICAST_TABLE(port_num) + table_index, 0); |
1da177e4 | 1365 | |
c9df406f LB |
1366 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { |
1367 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
3cb4667c | 1368 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0); |
c9df406f | 1369 | /* Clear DA filter other multicast table (Ex_dFOMT) */ |
3cb4667c | 1370 | wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0); |
c9df406f LB |
1371 | } |
1372 | } | |
d0412d96 | 1373 | |
c9df406f LB |
1374 | /* |
1375 | * The entries in each table are indexed by a hash of a packet's MAC | |
1376 | * address. One bit in each entry determines whether the packet is | |
1377 | * accepted. There are 4 entries (each 8 bits wide) in each register | |
1378 | * of the table. The bits in each entry are defined as follows: | |
1379 | * 0 Accept=1, Drop=0 | |
1380 | * 3-1 Queue (ETH_Q0=0) | |
1381 | * 7-4 Reserved = 0; | |
1382 | */ | |
1383 | static void eth_port_set_filter_table_entry(struct mv643xx_private *mp, | |
1384 | int table, unsigned char entry) | |
1385 | { | |
1386 | unsigned int table_reg; | |
1387 | unsigned int tbl_offset; | |
1388 | unsigned int reg_offset; | |
ab4384a6 | 1389 | |
c9df406f LB |
1390 | tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */ |
1391 | reg_offset = entry % 4; /* Entry offset within the register */ | |
ab4384a6 | 1392 | |
c9df406f LB |
1393 | /* Set "accepts frame bit" at specified table entry */ |
1394 | table_reg = rdl(mp, table + tbl_offset); | |
1395 | table_reg |= 0x01 << (8 * reg_offset); | |
1396 | wrl(mp, table + tbl_offset, table_reg); | |
1da177e4 LT |
1397 | } |
1398 | ||
c9df406f LB |
1399 | /* |
1400 | * eth_port_uc_addr_set - Write a MAC address into the port's hw registers | |
1401 | */ | |
1402 | static void eth_port_uc_addr_set(struct mv643xx_private *mp, | |
1403 | unsigned char *p_addr) | |
1da177e4 | 1404 | { |
c9df406f LB |
1405 | unsigned int port_num = mp->port_num; |
1406 | unsigned int mac_h; | |
1407 | unsigned int mac_l; | |
1408 | int table; | |
1da177e4 | 1409 | |
c9df406f LB |
1410 | mac_l = (p_addr[4] << 8) | (p_addr[5]); |
1411 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | | |
1412 | (p_addr[3] << 0); | |
ff561eef | 1413 | |
c9df406f LB |
1414 | wrl(mp, MAC_ADDR_LOW(port_num), mac_l); |
1415 | wrl(mp, MAC_ADDR_HIGH(port_num), mac_h); | |
1da177e4 | 1416 | |
c9df406f | 1417 | /* Accept frames with this address */ |
3cb4667c | 1418 | table = UNICAST_TABLE(port_num); |
c9df406f | 1419 | eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f); |
1da177e4 LT |
1420 | } |
1421 | ||
c9df406f LB |
1422 | /* |
1423 | * mv643xx_eth_update_mac_address | |
1424 | * | |
1425 | * Update the MAC address of the port in the address table | |
1426 | * | |
1427 | * Input : pointer to ethernet interface network device structure | |
1428 | * Output : N/A | |
1429 | */ | |
1430 | static void mv643xx_eth_update_mac_address(struct net_device *dev) | |
1da177e4 LT |
1431 | { |
1432 | struct mv643xx_private *mp = netdev_priv(dev); | |
1da177e4 | 1433 | |
c9df406f LB |
1434 | eth_port_init_mac_tables(mp); |
1435 | eth_port_uc_addr_set(mp, dev->dev_addr); | |
1436 | } | |
1da177e4 LT |
1437 | |
1438 | /* | |
c9df406f | 1439 | * mv643xx_eth_set_mac_address |
1da177e4 | 1440 | * |
c9df406f LB |
1441 | * Change the interface's mac address. |
1442 | * No special hardware thing should be done because interface is always | |
1443 | * put in promiscuous mode. | |
1444 | * | |
1445 | * Input : pointer to ethernet interface network device structure and | |
1446 | * a pointer to the designated entry to be added to the cache. | |
1447 | * Output : zero upon success, negative upon failure | |
1da177e4 | 1448 | */ |
c9df406f | 1449 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) |
1da177e4 | 1450 | { |
c9df406f | 1451 | int i; |
1da177e4 | 1452 | |
c9df406f LB |
1453 | for (i = 0; i < 6; i++) |
1454 | /* +2 is for the offset of the HW addr type */ | |
1455 | dev->dev_addr[i] = ((unsigned char *)addr)[i + 2]; | |
1456 | mv643xx_eth_update_mac_address(dev); | |
1da177e4 LT |
1457 | return 0; |
1458 | } | |
1459 | ||
1da177e4 | 1460 | /* |
c9df406f | 1461 | * eth_port_mc_addr - Multicast address settings. |
1da177e4 | 1462 | * |
c9df406f LB |
1463 | * The MV device supports multicast using two tables: |
1464 | * 1) Special Multicast Table for MAC addresses of the form | |
1465 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF). | |
1466 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1467 | * Table entries in the DA-Filter table. | |
1468 | * 2) Other Multicast Table for multicast of another type. A CRC-8bit | |
1469 | * is used as an index to the Other Multicast Table entries in the | |
1470 | * DA-Filter table. This function calculates the CRC-8bit value. | |
1471 | * In either case, eth_port_set_filter_table_entry() is then called | |
1472 | * to set to set the actual table entry. | |
1da177e4 | 1473 | */ |
c9df406f | 1474 | static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr) |
1da177e4 | 1475 | { |
1da177e4 | 1476 | unsigned int port_num = mp->port_num; |
c9df406f LB |
1477 | unsigned int mac_h; |
1478 | unsigned int mac_l; | |
1479 | unsigned char crc_result = 0; | |
1480 | int table; | |
1481 | int mac_array[48]; | |
1482 | int crc[8]; | |
1483 | int i; | |
1da177e4 | 1484 | |
c9df406f LB |
1485 | if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) && |
1486 | (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) { | |
3cb4667c | 1487 | table = SPECIAL_MCAST_TABLE(port_num); |
c9df406f LB |
1488 | eth_port_set_filter_table_entry(mp, table, p_addr[5]); |
1489 | return; | |
1da177e4 | 1490 | } |
1da177e4 | 1491 | |
c9df406f LB |
1492 | /* Calculate CRC-8 out of the given address */ |
1493 | mac_h = (p_addr[0] << 8) | (p_addr[1]); | |
1494 | mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | | |
1495 | (p_addr[4] << 8) | (p_addr[5] << 0); | |
1da177e4 | 1496 | |
c9df406f LB |
1497 | for (i = 0; i < 32; i++) |
1498 | mac_array[i] = (mac_l >> i) & 0x1; | |
1499 | for (i = 32; i < 48; i++) | |
1500 | mac_array[i] = (mac_h >> (i - 32)) & 0x1; | |
1da177e4 | 1501 | |
c9df406f LB |
1502 | crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^ |
1503 | mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^ | |
1504 | mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ | |
1505 | mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^ | |
1506 | mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0]; | |
1da177e4 | 1507 | |
c9df406f LB |
1508 | crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ |
1509 | mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^ | |
1510 | mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ | |
1511 | mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^ | |
1512 | mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^ | |
1513 | mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ | |
1514 | mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0]; | |
f7ea3337 | 1515 | |
c9df406f LB |
1516 | crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^ |
1517 | mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^ | |
1518 | mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ | |
1519 | mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^ | |
1520 | mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ | |
1521 | mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0]; | |
f7ea3337 | 1522 | |
c9df406f LB |
1523 | crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^ |
1524 | mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^ | |
1525 | mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ | |
1526 | mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ | |
1527 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^ | |
1528 | mac_array[3] ^ mac_array[2] ^ mac_array[1]; | |
f7ea3337 | 1529 | |
c9df406f LB |
1530 | crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^ |
1531 | mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^ | |
1532 | mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ | |
1533 | mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^ | |
1534 | mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^ | |
1535 | mac_array[3] ^ mac_array[2]; | |
c8aaea25 | 1536 | |
c9df406f LB |
1537 | crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^ |
1538 | mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^ | |
1539 | mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ | |
1540 | mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^ | |
1541 | mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^ | |
1542 | mac_array[4] ^ mac_array[3]; | |
c8aaea25 | 1543 | |
c9df406f LB |
1544 | crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^ |
1545 | mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^ | |
1546 | mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ | |
1547 | mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^ | |
1548 | mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^ | |
1549 | mac_array[4]; | |
c8aaea25 | 1550 | |
c9df406f LB |
1551 | crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^ |
1552 | mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^ | |
1553 | mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ | |
1554 | mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^ | |
1555 | mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5]; | |
c8aaea25 | 1556 | |
c9df406f LB |
1557 | for (i = 0; i < 8; i++) |
1558 | crc_result = crc_result | (crc[i] << i); | |
1559 | ||
3cb4667c | 1560 | table = OTHER_MCAST_TABLE(port_num); |
c9df406f | 1561 | eth_port_set_filter_table_entry(mp, table, crc_result); |
c8aaea25 DF |
1562 | } |
1563 | ||
c9df406f LB |
1564 | /* |
1565 | * Set the entire multicast list based on dev->mc_list. | |
1da177e4 | 1566 | */ |
c9df406f | 1567 | static void eth_port_set_multicast_list(struct net_device *dev) |
1da177e4 | 1568 | { |
1da177e4 | 1569 | |
c9df406f LB |
1570 | struct dev_mc_list *mc_list; |
1571 | int i; | |
1572 | int table_index; | |
1573 | struct mv643xx_private *mp = netdev_priv(dev); | |
1574 | unsigned int eth_port_num = mp->port_num; | |
c8aaea25 | 1575 | |
c9df406f LB |
1576 | /* If the device is in promiscuous mode or in all multicast mode, |
1577 | * we will fully populate both multicast tables with accept. | |
1578 | * This is guaranteed to yield a match on all multicast addresses... | |
1579 | */ | |
1580 | if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) { | |
1581 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
1582 | /* Set all entries in DA filter special multicast | |
1583 | * table (Ex_dFSMT) | |
1584 | * Set for ETH_Q0 for now | |
1585 | * Bits | |
1586 | * 0 Accept=1, Drop=0 | |
1587 | * 3-1 Queue ETH_Q0=0 | |
1588 | * 7-4 Reserved = 0; | |
1589 | */ | |
3cb4667c | 1590 | wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0x01010101); |
c8aaea25 | 1591 | |
c9df406f LB |
1592 | /* Set all entries in DA filter other multicast |
1593 | * table (Ex_dFOMT) | |
1594 | * Set for ETH_Q0 for now | |
1595 | * Bits | |
1596 | * 0 Accept=1, Drop=0 | |
1597 | * 3-1 Queue ETH_Q0=0 | |
1598 | * 7-4 Reserved = 0; | |
1599 | */ | |
3cb4667c | 1600 | wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0x01010101); |
c9df406f LB |
1601 | } |
1602 | return; | |
1603 | } | |
c8aaea25 | 1604 | |
c9df406f LB |
1605 | /* We will clear out multicast tables every time we get the list. |
1606 | * Then add the entire new list... | |
1607 | */ | |
1608 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
1609 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
3cb4667c | 1610 | wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0); |
c9df406f LB |
1611 | |
1612 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
3cb4667c | 1613 | wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0); |
1da177e4 LT |
1614 | } |
1615 | ||
c9df406f LB |
1616 | /* Get pointer to net_device multicast list and add each one... */ |
1617 | for (i = 0, mc_list = dev->mc_list; | |
1618 | (i < 256) && (mc_list != NULL) && (i < dev->mc_count); | |
1619 | i++, mc_list = mc_list->next) | |
1620 | if (mc_list->dmi_addrlen == 6) | |
1621 | eth_port_mc_addr(mp, mc_list->dmi_addr); | |
324ff2c1 BB |
1622 | } |
1623 | ||
c9df406f LB |
1624 | /* |
1625 | * mv643xx_eth_set_rx_mode | |
c8aaea25 | 1626 | * |
c9df406f LB |
1627 | * Change from promiscuos to regular rx mode |
1628 | * | |
1629 | * Input : pointer to ethernet interface network device structure | |
1630 | * Output : N/A | |
c8aaea25 | 1631 | */ |
c9df406f | 1632 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) |
c8aaea25 | 1633 | { |
c9df406f LB |
1634 | struct mv643xx_private *mp = netdev_priv(dev); |
1635 | u32 config_reg; | |
1da177e4 | 1636 | |
3cb4667c | 1637 | config_reg = rdl(mp, PORT_CONFIG(mp->port_num)); |
c9df406f | 1638 | if (dev->flags & IFF_PROMISC) |
d9a073ea | 1639 | config_reg |= UNICAST_PROMISCUOUS_MODE; |
c9df406f | 1640 | else |
d9a073ea | 1641 | config_reg &= ~UNICAST_PROMISCUOUS_MODE; |
3cb4667c | 1642 | wrl(mp, PORT_CONFIG(mp->port_num), config_reg); |
1da177e4 | 1643 | |
c9df406f LB |
1644 | eth_port_set_multicast_list(dev); |
1645 | } | |
c8aaea25 | 1646 | |
c8aaea25 | 1647 | |
c9df406f LB |
1648 | /* rx/tx queue initialisation ***********************************************/ |
1649 | /* | |
1650 | * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. | |
1651 | * | |
1652 | * DESCRIPTION: | |
1653 | * This function prepares a Rx chained list of descriptors and packet | |
1654 | * buffers in a form of a ring. The routine must be called after port | |
1655 | * initialization routine and before port start routine. | |
1656 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
1657 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
1658 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
1659 | * with physical addresses. | |
1660 | * | |
1661 | * INPUT: | |
1662 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
1663 | * | |
1664 | * OUTPUT: | |
1665 | * The routine updates the Ethernet port control struct with information | |
1666 | * regarding the Rx descriptors and buffers. | |
1667 | * | |
1668 | * RETURN: | |
1669 | * None. | |
1670 | */ | |
1671 | static void ether_init_rx_desc_ring(struct mv643xx_private *mp) | |
1672 | { | |
1673 | volatile struct eth_rx_desc *p_rx_desc; | |
1674 | int rx_desc_num = mp->rx_ring_size; | |
1675 | int i; | |
1676 | ||
1677 | /* initialize the next_desc_ptr links in the Rx descriptors ring */ | |
1678 | p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area; | |
1679 | for (i = 0; i < rx_desc_num; i++) { | |
1680 | p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma + | |
1681 | ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc); | |
f7ea3337 PJ |
1682 | } |
1683 | ||
c9df406f LB |
1684 | /* Save Rx desc pointer to driver struct. */ |
1685 | mp->rx_curr_desc_q = 0; | |
1686 | mp->rx_used_desc_q = 0; | |
1da177e4 | 1687 | |
c9df406f LB |
1688 | mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc); |
1689 | } | |
c8aaea25 | 1690 | |
c9df406f LB |
1691 | static void mv643xx_eth_free_rx_rings(struct net_device *dev) |
1692 | { | |
1693 | struct mv643xx_private *mp = netdev_priv(dev); | |
1694 | int curr; | |
c8aaea25 | 1695 | |
c9df406f LB |
1696 | /* Stop RX Queues */ |
1697 | mv643xx_eth_port_disable_rx(mp); | |
1698 | ||
1699 | /* Free preallocated skb's on RX rings */ | |
1700 | for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) { | |
1701 | if (mp->rx_skb[curr]) { | |
1702 | dev_kfree_skb(mp->rx_skb[curr]); | |
1703 | mp->rx_desc_count--; | |
1da177e4 | 1704 | } |
c8aaea25 | 1705 | } |
1da177e4 | 1706 | |
c9df406f LB |
1707 | if (mp->rx_desc_count) |
1708 | printk(KERN_ERR | |
1709 | "%s: Error in freeing Rx Ring. %d skb's still" | |
1710 | " stuck in RX Ring - ignoring them\n", dev->name, | |
1711 | mp->rx_desc_count); | |
1712 | /* Free RX ring */ | |
1713 | if (mp->rx_sram_size) | |
1714 | iounmap(mp->p_rx_desc_area); | |
1715 | else | |
1716 | dma_free_coherent(NULL, mp->rx_desc_area_size, | |
1717 | mp->p_rx_desc_area, mp->rx_desc_dma); | |
1718 | } | |
1da177e4 | 1719 | |
c9df406f LB |
1720 | /* |
1721 | * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. | |
1722 | * | |
1723 | * DESCRIPTION: | |
1724 | * This function prepares a Tx chained list of descriptors and packet | |
1725 | * buffers in a form of a ring. The routine must be called after port | |
1726 | * initialization routine and before port start routine. | |
1727 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
1728 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
1729 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
1730 | * with physical addresses. | |
1731 | * | |
1732 | * INPUT: | |
1733 | * struct mv643xx_private *mp Ethernet Port Control srtuct. | |
1734 | * | |
1735 | * OUTPUT: | |
1736 | * The routine updates the Ethernet port control struct with information | |
1737 | * regarding the Tx descriptors and buffers. | |
1738 | * | |
1739 | * RETURN: | |
1740 | * None. | |
1741 | */ | |
1742 | static void ether_init_tx_desc_ring(struct mv643xx_private *mp) | |
1743 | { | |
1744 | int tx_desc_num = mp->tx_ring_size; | |
1745 | struct eth_tx_desc *p_tx_desc; | |
1746 | int i; | |
1da177e4 | 1747 | |
c9df406f LB |
1748 | /* Initialize the next_desc_ptr links in the Tx descriptors ring */ |
1749 | p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area; | |
1750 | for (i = 0; i < tx_desc_num; i++) { | |
1751 | p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma + | |
1752 | ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc); | |
1753 | } | |
1754 | ||
1755 | mp->tx_curr_desc_q = 0; | |
1756 | mp->tx_used_desc_q = 0; | |
1757 | ||
1758 | mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc); | |
c8aaea25 | 1759 | } |
1da177e4 | 1760 | |
c8aaea25 | 1761 | /** |
c9df406f | 1762 | * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors |
c8aaea25 | 1763 | * |
c9df406f | 1764 | * If force is non-zero, frees uncompleted descriptors as well |
c8aaea25 | 1765 | */ |
c9df406f | 1766 | static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force) |
c8aaea25 DF |
1767 | { |
1768 | struct mv643xx_private *mp = netdev_priv(dev); | |
c9df406f LB |
1769 | struct eth_tx_desc *desc; |
1770 | u32 cmd_sts; | |
1771 | struct sk_buff *skb; | |
c8aaea25 | 1772 | unsigned long flags; |
c9df406f LB |
1773 | int tx_index; |
1774 | dma_addr_t addr; | |
1775 | int count; | |
1776 | int released = 0; | |
1da177e4 | 1777 | |
c9df406f LB |
1778 | while (mp->tx_desc_count > 0) { |
1779 | spin_lock_irqsave(&mp->lock, flags); | |
94843566 | 1780 | |
c9df406f LB |
1781 | /* tx_desc_count might have changed before acquiring the lock */ |
1782 | if (mp->tx_desc_count <= 0) { | |
1783 | spin_unlock_irqrestore(&mp->lock, flags); | |
1784 | return released; | |
1785 | } | |
4d64e718 | 1786 | |
c9df406f LB |
1787 | tx_index = mp->tx_used_desc_q; |
1788 | desc = &mp->p_tx_desc_area[tx_index]; | |
1789 | cmd_sts = desc->cmd_sts; | |
4d64e718 | 1790 | |
c9df406f LB |
1791 | if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) { |
1792 | spin_unlock_irqrestore(&mp->lock, flags); | |
1793 | return released; | |
1794 | } | |
1da177e4 | 1795 | |
c9df406f LB |
1796 | mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size; |
1797 | mp->tx_desc_count--; | |
1da177e4 | 1798 | |
c9df406f LB |
1799 | addr = desc->buf_ptr; |
1800 | count = desc->byte_cnt; | |
1801 | skb = mp->tx_skb[tx_index]; | |
1802 | if (skb) | |
1803 | mp->tx_skb[tx_index] = NULL; | |
c8aaea25 | 1804 | |
c9df406f LB |
1805 | if (cmd_sts & ETH_ERROR_SUMMARY) { |
1806 | printk("%s: Error in TX\n", dev->name); | |
1807 | dev->stats.tx_errors++; | |
1808 | } | |
1da177e4 | 1809 | |
c9df406f | 1810 | spin_unlock_irqrestore(&mp->lock, flags); |
1da177e4 | 1811 | |
c9df406f LB |
1812 | if (cmd_sts & ETH_TX_FIRST_DESC) |
1813 | dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); | |
1814 | else | |
1815 | dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE); | |
c2e5b352 | 1816 | |
c9df406f LB |
1817 | if (skb) |
1818 | dev_kfree_skb_irq(skb); | |
63c9e549 | 1819 | |
c9df406f LB |
1820 | released = 1; |
1821 | } | |
c2e5b352 | 1822 | |
c9df406f | 1823 | return released; |
63c9e549 | 1824 | } |
63c9e549 | 1825 | |
c9df406f | 1826 | static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev) |
d0412d96 JC |
1827 | { |
1828 | struct mv643xx_private *mp = netdev_priv(dev); | |
1829 | ||
c9df406f LB |
1830 | if (mv643xx_eth_free_tx_descs(dev, 0) && |
1831 | mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
1832 | netif_wake_queue(dev); | |
d0412d96 JC |
1833 | } |
1834 | ||
c9df406f | 1835 | static void mv643xx_eth_free_all_tx_descs(struct net_device *dev) |
1da177e4 | 1836 | { |
c9df406f LB |
1837 | mv643xx_eth_free_tx_descs(dev, 1); |
1838 | } | |
1da177e4 | 1839 | |
c9df406f LB |
1840 | static void mv643xx_eth_free_tx_rings(struct net_device *dev) |
1841 | { | |
1842 | struct mv643xx_private *mp = netdev_priv(dev); | |
84dd619e | 1843 | |
c9df406f LB |
1844 | /* Stop Tx Queues */ |
1845 | mv643xx_eth_port_disable_tx(mp); | |
fa3959f4 | 1846 | |
c9df406f LB |
1847 | /* Free outstanding skb's on TX ring */ |
1848 | mv643xx_eth_free_all_tx_descs(dev); | |
1da177e4 | 1849 | |
c9df406f | 1850 | BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q); |
1da177e4 | 1851 | |
c9df406f LB |
1852 | /* Free TX ring */ |
1853 | if (mp->tx_sram_size) | |
1854 | iounmap(mp->p_tx_desc_area); | |
1855 | else | |
1856 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
1857 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
1858 | } | |
1da177e4 | 1859 | |
1da177e4 | 1860 | |
c9df406f LB |
1861 | /* netdev ops and related ***************************************************/ |
1862 | static void eth_port_reset(struct mv643xx_private *mp); | |
1da177e4 | 1863 | |
c9df406f LB |
1864 | /* Set the mv643xx port configuration register for the speed/duplex mode. */ |
1865 | static void mv643xx_eth_update_pscr(struct net_device *dev, | |
1866 | struct ethtool_cmd *ecmd) | |
1867 | { | |
1868 | struct mv643xx_private *mp = netdev_priv(dev); | |
1869 | int port_num = mp->port_num; | |
1870 | u32 o_pscr, n_pscr; | |
1871 | unsigned int queues; | |
1da177e4 | 1872 | |
3cb4667c | 1873 | o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num)); |
c9df406f | 1874 | n_pscr = o_pscr; |
63c9e549 | 1875 | |
c9df406f LB |
1876 | /* clear speed, duplex and rx buffer size fields */ |
1877 | n_pscr &= ~(SET_MII_SPEED_TO_100 | | |
1878 | SET_GMII_SPEED_TO_1000 | | |
1879 | SET_FULL_DUPLEX_MODE | | |
1880 | MAX_RX_PACKET_MASK); | |
1da177e4 | 1881 | |
c9df406f LB |
1882 | if (ecmd->duplex == DUPLEX_FULL) |
1883 | n_pscr |= SET_FULL_DUPLEX_MODE; | |
1da177e4 | 1884 | |
c9df406f LB |
1885 | if (ecmd->speed == SPEED_1000) |
1886 | n_pscr |= SET_GMII_SPEED_TO_1000 | | |
1887 | MAX_RX_PACKET_9700BYTE; | |
1888 | else { | |
1889 | if (ecmd->speed == SPEED_100) | |
1890 | n_pscr |= SET_MII_SPEED_TO_100; | |
1891 | n_pscr |= MAX_RX_PACKET_1522BYTE; | |
1892 | } | |
1da177e4 | 1893 | |
c9df406f LB |
1894 | if (n_pscr != o_pscr) { |
1895 | if ((o_pscr & SERIAL_PORT_ENABLE) == 0) | |
3cb4667c | 1896 | wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr); |
c9df406f LB |
1897 | else { |
1898 | queues = mv643xx_eth_port_disable_tx(mp); | |
1da177e4 | 1899 | |
c9df406f | 1900 | o_pscr &= ~SERIAL_PORT_ENABLE; |
3cb4667c LB |
1901 | wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr); |
1902 | wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr); | |
1903 | wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr); | |
c9df406f LB |
1904 | if (queues) |
1905 | mv643xx_eth_port_enable_tx(mp, queues); | |
1906 | } | |
1907 | } | |
1908 | } | |
84dd619e | 1909 | |
c9df406f LB |
1910 | /* |
1911 | * mv643xx_eth_int_handler | |
1912 | * | |
1913 | * Main interrupt handler for the gigbit ethernet ports | |
1914 | * | |
1915 | * Input : irq - irq number (not used) | |
1916 | * dev_id - a pointer to the required interface's data structure | |
1917 | * regs - not used | |
1918 | * Output : N/A | |
1919 | */ | |
f2ce825d | 1920 | |
c9df406f LB |
1921 | static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id) |
1922 | { | |
1923 | struct net_device *dev = (struct net_device *)dev_id; | |
1924 | struct mv643xx_private *mp = netdev_priv(dev); | |
1925 | u32 eth_int_cause, eth_int_cause_ext = 0; | |
1926 | unsigned int port_num = mp->port_num; | |
ce4e2e45 | 1927 | |
c9df406f | 1928 | /* Read interrupt cause registers */ |
073a345c LB |
1929 | eth_int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT); |
1930 | if (eth_int_cause & INT_EXT) { | |
3cb4667c | 1931 | eth_int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num)) |
073a345c | 1932 | & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
3cb4667c | 1933 | wrl(mp, INT_CAUSE_EXT(port_num), ~eth_int_cause_ext); |
c9df406f | 1934 | } |
1da177e4 | 1935 | |
c9df406f | 1936 | /* PHY status changed */ |
073a345c | 1937 | if (eth_int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) { |
c9df406f | 1938 | struct ethtool_cmd cmd; |
1da177e4 | 1939 | |
c9df406f LB |
1940 | if (mii_link_ok(&mp->mii)) { |
1941 | mii_ethtool_gset(&mp->mii, &cmd); | |
1942 | mv643xx_eth_update_pscr(dev, &cmd); | |
073a345c | 1943 | mv643xx_eth_port_enable_tx(mp, 1); |
c9df406f LB |
1944 | if (!netif_carrier_ok(dev)) { |
1945 | netif_carrier_on(dev); | |
1946 | if (mp->tx_ring_size - mp->tx_desc_count >= | |
1947 | MAX_DESCS_PER_SKB) | |
1948 | netif_wake_queue(dev); | |
1949 | } | |
1950 | } else if (netif_carrier_ok(dev)) { | |
1951 | netif_stop_queue(dev); | |
1952 | netif_carrier_off(dev); | |
1953 | } | |
1954 | } | |
1da177e4 | 1955 | |
c9df406f | 1956 | #ifdef MV643XX_NAPI |
073a345c | 1957 | if (eth_int_cause & INT_RX) { |
c9df406f | 1958 | /* schedule the NAPI poll routine to maintain port */ |
073a345c | 1959 | wrl(mp, INT_MASK(port_num), 0x00000000); |
1da177e4 | 1960 | |
c9df406f | 1961 | /* wait for previous write to complete */ |
3cb4667c | 1962 | rdl(mp, INT_MASK(port_num)); |
1da177e4 | 1963 | |
c9df406f | 1964 | netif_rx_schedule(dev, &mp->napi); |
84dd619e | 1965 | } |
c9df406f | 1966 | #else |
073a345c | 1967 | if (eth_int_cause & INT_RX) |
c9df406f LB |
1968 | mv643xx_eth_receive_queue(dev, INT_MAX); |
1969 | #endif | |
073a345c | 1970 | if (eth_int_cause_ext & INT_EXT_TX) |
c9df406f | 1971 | mv643xx_eth_free_completed_tx_descs(dev); |
1da177e4 | 1972 | |
f2ce825d | 1973 | /* |
c9df406f LB |
1974 | * If no real interrupt occured, exit. |
1975 | * This can happen when using gigE interrupt coalescing mechanism. | |
f2ce825d | 1976 | */ |
c9df406f LB |
1977 | if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0)) |
1978 | return IRQ_NONE; | |
1da177e4 | 1979 | |
c9df406f | 1980 | return IRQ_HANDLED; |
1da177e4 LT |
1981 | } |
1982 | ||
1da177e4 | 1983 | /* |
c9df406f | 1984 | * ethernet_phy_reset - Reset Ethernet port PHY. |
1da177e4 LT |
1985 | * |
1986 | * DESCRIPTION: | |
c9df406f | 1987 | * This routine utilizes the SMI interface to reset the ethernet port PHY. |
1da177e4 LT |
1988 | * |
1989 | * INPUT: | |
c9df406f | 1990 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
1991 | * |
1992 | * OUTPUT: | |
c9df406f | 1993 | * The PHY is reset. |
1da177e4 LT |
1994 | * |
1995 | * RETURN: | |
1996 | * None. | |
c9df406f | 1997 | * |
1da177e4 | 1998 | */ |
c9df406f | 1999 | static void ethernet_phy_reset(struct mv643xx_private *mp) |
1da177e4 | 2000 | { |
c9df406f | 2001 | unsigned int phy_reg_data; |
1da177e4 | 2002 | |
c9df406f LB |
2003 | /* Reset the PHY */ |
2004 | eth_port_read_smi_reg(mp, 0, &phy_reg_data); | |
2005 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ | |
2006 | eth_port_write_smi_reg(mp, 0, phy_reg_data); | |
1da177e4 | 2007 | |
c9df406f LB |
2008 | /* wait for PHY to come out of reset */ |
2009 | do { | |
2010 | udelay(1); | |
2011 | eth_port_read_smi_reg(mp, 0, &phy_reg_data); | |
2012 | } while (phy_reg_data & 0x8000); | |
1da177e4 LT |
2013 | } |
2014 | ||
2015 | /* | |
2016 | * eth_port_start - Start the Ethernet port activity. | |
2017 | * | |
2018 | * DESCRIPTION: | |
2019 | * This routine prepares the Ethernet port for Rx and Tx activity: | |
2020 | * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that | |
2021 | * has been initialized a descriptor's ring (using | |
2022 | * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx) | |
2023 | * 2. Initialize and enable the Ethernet configuration port by writing to | |
2024 | * the port's configuration and command registers. | |
2025 | * 3. Initialize and enable the SDMA by writing to the SDMA's | |
2026 | * configuration and command registers. After completing these steps, | |
2027 | * the ethernet port SDMA can starts to perform Rx and Tx activities. | |
2028 | * | |
2029 | * Note: Each Rx and Tx queue descriptor's list must be initialized prior | |
2030 | * to calling this function (use ether_init_tx_desc_ring for Tx queues | |
2031 | * and ether_init_rx_desc_ring for Rx queues). | |
2032 | * | |
2033 | * INPUT: | |
ed9b5d45 | 2034 | * dev - a pointer to the required interface |
1da177e4 LT |
2035 | * |
2036 | * OUTPUT: | |
2037 | * Ethernet port is ready to receive and transmit. | |
2038 | * | |
2039 | * RETURN: | |
2040 | * None. | |
2041 | */ | |
ed9b5d45 | 2042 | static void eth_port_start(struct net_device *dev) |
1da177e4 | 2043 | { |
ed9b5d45 | 2044 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 LT |
2045 | unsigned int port_num = mp->port_num; |
2046 | int tx_curr_desc, rx_curr_desc; | |
d0412d96 JC |
2047 | u32 pscr; |
2048 | struct ethtool_cmd ethtool_cmd; | |
1da177e4 LT |
2049 | |
2050 | /* Assignment of Tx CTRP of given queue */ | |
2051 | tx_curr_desc = mp->tx_curr_desc_q; | |
3cb4667c | 2052 | wrl(mp, TXQ_CURRENT_DESC_PTR(port_num), |
1da177e4 LT |
2053 | (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc)); |
2054 | ||
2055 | /* Assignment of Rx CRDP of given queue */ | |
2056 | rx_curr_desc = mp->rx_curr_desc_q; | |
3cb4667c | 2057 | wrl(mp, RXQ_CURRENT_DESC_PTR(port_num), |
1da177e4 LT |
2058 | (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc)); |
2059 | ||
2060 | /* Add the assigned Ethernet address to the port's address table */ | |
afdb57a2 | 2061 | eth_port_uc_addr_set(mp, dev->dev_addr); |
1da177e4 | 2062 | |
d9a073ea LB |
2063 | /* |
2064 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
2065 | * frames to RX queue #0. | |
2066 | */ | |
2067 | wrl(mp, PORT_CONFIG(port_num), 0x00000000); | |
01999873 | 2068 | |
376489a2 LB |
2069 | /* |
2070 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
2071 | */ | |
2072 | wrl(mp, PORT_CONFIG_EXT(port_num), 0x00000000); | |
1da177e4 | 2073 | |
3cb4667c | 2074 | pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num)); |
01999873 | 2075 | |
e4d00fa9 | 2076 | pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS); |
3cb4667c | 2077 | wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr); |
1da177e4 | 2078 | |
e4d00fa9 LB |
2079 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | |
2080 | DISABLE_AUTO_NEG_SPEED_GMII | | |
2beff77b | 2081 | DISABLE_AUTO_NEG_FOR_DUPLEX | |
e4d00fa9 LB |
2082 | DO_NOT_FORCE_LINK_FAIL | |
2083 | SERIAL_PORT_CONTROL_RESERVED; | |
1da177e4 | 2084 | |
3cb4667c | 2085 | wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr); |
1da177e4 | 2086 | |
e4d00fa9 | 2087 | pscr |= SERIAL_PORT_ENABLE; |
3cb4667c | 2088 | wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr); |
1da177e4 LT |
2089 | |
2090 | /* Assign port SDMA configuration */ | |
3cb4667c | 2091 | wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE); |
1da177e4 LT |
2092 | |
2093 | /* Enable port Rx. */ | |
073a345c | 2094 | mv643xx_eth_port_enable_rx(mp, 1); |
8f543718 DF |
2095 | |
2096 | /* Disable port bandwidth limits by clearing MTU register */ | |
3cb4667c | 2097 | wrl(mp, TX_BW_MTU(port_num), 0); |
d0412d96 JC |
2098 | |
2099 | /* save phy settings across reset */ | |
2100 | mv643xx_get_settings(dev, ðtool_cmd); | |
afdb57a2 | 2101 | ethernet_phy_reset(mp); |
d0412d96 | 2102 | mv643xx_set_settings(dev, ðtool_cmd); |
1da177e4 LT |
2103 | } |
2104 | ||
c9df406f LB |
2105 | #ifdef MV643XX_COAL |
2106 | ||
1da177e4 | 2107 | /* |
c9df406f LB |
2108 | * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path |
2109 | * | |
2110 | * DESCRIPTION: | |
2111 | * This routine sets the RX coalescing interrupt mechanism parameter. | |
2112 | * This parameter is a timeout counter, that counts in 64 t_clk | |
2113 | * chunks ; that when timeout event occurs a maskable interrupt | |
2114 | * occurs. | |
2115 | * The parameter is calculated using the tClk of the MV-643xx chip | |
2116 | * , and the required delay of the interrupt in usec. | |
2117 | * | |
2118 | * INPUT: | |
2119 | * struct mv643xx_private *mp Ethernet port | |
2120 | * unsigned int delay Delay in usec | |
2121 | * | |
2122 | * OUTPUT: | |
2123 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
2124 | * | |
2125 | * RETURN: | |
2126 | * The interrupt coalescing value set in the gigE port. | |
2127 | * | |
1da177e4 | 2128 | */ |
c9df406f LB |
2129 | static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp, |
2130 | unsigned int delay) | |
1da177e4 | 2131 | { |
afdb57a2 | 2132 | unsigned int port_num = mp->port_num; |
c9df406f | 2133 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 2134 | |
c9df406f | 2135 | /* Set RX Coalescing mechanism */ |
3cb4667c | 2136 | wrl(mp, SDMA_CONFIG(port_num), |
c9df406f | 2137 | ((coal & 0x3fff) << 8) | |
3cb4667c | 2138 | (rdl(mp, SDMA_CONFIG(port_num)) |
c9df406f | 2139 | & 0xffc000ff)); |
1da177e4 | 2140 | |
c9df406f | 2141 | return coal; |
1da177e4 | 2142 | } |
c9df406f | 2143 | #endif |
1da177e4 LT |
2144 | |
2145 | /* | |
c9df406f LB |
2146 | * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path |
2147 | * | |
2148 | * DESCRIPTION: | |
2149 | * This routine sets the TX coalescing interrupt mechanism parameter. | |
2150 | * This parameter is a timeout counter, that counts in 64 t_clk | |
2151 | * chunks ; that when timeout event occurs a maskable interrupt | |
2152 | * occurs. | |
2153 | * The parameter is calculated using the t_cLK frequency of the | |
2154 | * MV-643xx chip and the required delay in the interrupt in uSec | |
2155 | * | |
2156 | * INPUT: | |
2157 | * struct mv643xx_private *mp Ethernet port | |
2158 | * unsigned int delay Delay in uSeconds | |
2159 | * | |
2160 | * OUTPUT: | |
2161 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
2162 | * | |
2163 | * RETURN: | |
2164 | * The interrupt coalescing value set in the gigE port. | |
2165 | * | |
1da177e4 | 2166 | */ |
c9df406f LB |
2167 | static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp, |
2168 | unsigned int delay) | |
1da177e4 | 2169 | { |
c9df406f | 2170 | unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64; |
1da177e4 | 2171 | |
c9df406f | 2172 | /* Set TX Coalescing mechanism */ |
3cb4667c | 2173 | wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4); |
1da177e4 | 2174 | |
c9df406f | 2175 | return coal; |
1da177e4 LT |
2176 | } |
2177 | ||
16e03018 | 2178 | /* |
c9df406f LB |
2179 | * eth_port_init - Initialize the Ethernet port driver |
2180 | * | |
2181 | * DESCRIPTION: | |
2182 | * This function prepares the ethernet port to start its activity: | |
2183 | * 1) Completes the ethernet port driver struct initialization toward port | |
2184 | * start routine. | |
2185 | * 2) Resets the device to a quiescent state in case of warm reboot. | |
2186 | * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. | |
2187 | * 4) Clean MAC tables. The reset status of those tables is unknown. | |
2188 | * 5) Set PHY address. | |
2189 | * Note: Call this routine prior to eth_port_start routine and after | |
2190 | * setting user values in the user fields of Ethernet port control | |
2191 | * struct. | |
2192 | * | |
2193 | * INPUT: | |
2194 | * struct mv643xx_private *mp Ethernet port control struct | |
2195 | * | |
2196 | * OUTPUT: | |
2197 | * See description. | |
2198 | * | |
2199 | * RETURN: | |
2200 | * None. | |
16e03018 | 2201 | */ |
c9df406f | 2202 | static void eth_port_init(struct mv643xx_private *mp) |
16e03018 | 2203 | { |
c9df406f | 2204 | mp->rx_resource_err = 0; |
16e03018 | 2205 | |
c9df406f | 2206 | eth_port_reset(mp); |
16e03018 | 2207 | |
c9df406f | 2208 | eth_port_init_mac_tables(mp); |
16e03018 DF |
2209 | } |
2210 | ||
2211 | /* | |
c9df406f | 2212 | * mv643xx_eth_open |
16e03018 | 2213 | * |
c9df406f LB |
2214 | * This function is called when openning the network device. The function |
2215 | * should initialize all the hardware, initialize cyclic Rx/Tx | |
2216 | * descriptors chain and buffers and allocate an IRQ to the network | |
2217 | * device. | |
2218 | * | |
2219 | * Input : a pointer to the network device structure | |
2220 | * | |
2221 | * Output : zero of success , nonzero if fails. | |
16e03018 | 2222 | */ |
c9df406f LB |
2223 | |
2224 | static int mv643xx_eth_open(struct net_device *dev) | |
16e03018 | 2225 | { |
c9df406f | 2226 | struct mv643xx_private *mp = netdev_priv(dev); |
afdb57a2 | 2227 | unsigned int port_num = mp->port_num; |
c9df406f LB |
2228 | unsigned int size; |
2229 | int err; | |
16e03018 | 2230 | |
c9df406f | 2231 | /* Clear any pending ethernet port interrupts */ |
3cb4667c LB |
2232 | wrl(mp, INT_CAUSE(port_num), 0); |
2233 | wrl(mp, INT_CAUSE_EXT(port_num), 0); | |
c9df406f | 2234 | /* wait for previous write to complete */ |
3cb4667c | 2235 | rdl(mp, INT_CAUSE_EXT(port_num)); |
c9df406f LB |
2236 | |
2237 | err = request_irq(dev->irq, mv643xx_eth_int_handler, | |
2238 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev); | |
2239 | if (err) { | |
2240 | printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name); | |
2241 | return -EAGAIN; | |
16e03018 DF |
2242 | } |
2243 | ||
c9df406f | 2244 | eth_port_init(mp); |
16e03018 | 2245 | |
c9df406f LB |
2246 | memset(&mp->timeout, 0, sizeof(struct timer_list)); |
2247 | mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper; | |
2248 | mp->timeout.data = (unsigned long)dev; | |
16e03018 | 2249 | |
c9df406f LB |
2250 | /* Allocate RX and TX skb rings */ |
2251 | mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size, | |
2252 | GFP_KERNEL); | |
2253 | if (!mp->rx_skb) { | |
2254 | printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name); | |
2255 | err = -ENOMEM; | |
2256 | goto out_free_irq; | |
2257 | } | |
2258 | mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size, | |
2259 | GFP_KERNEL); | |
2260 | if (!mp->tx_skb) { | |
2261 | printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name); | |
2262 | err = -ENOMEM; | |
2263 | goto out_free_rx_skb; | |
2264 | } | |
16e03018 | 2265 | |
c9df406f LB |
2266 | /* Allocate TX ring */ |
2267 | mp->tx_desc_count = 0; | |
2268 | size = mp->tx_ring_size * sizeof(struct eth_tx_desc); | |
2269 | mp->tx_desc_area_size = size; | |
16e03018 | 2270 | |
c9df406f LB |
2271 | if (mp->tx_sram_size) { |
2272 | mp->p_tx_desc_area = ioremap(mp->tx_sram_addr, | |
2273 | mp->tx_sram_size); | |
2274 | mp->tx_desc_dma = mp->tx_sram_addr; | |
2275 | } else | |
2276 | mp->p_tx_desc_area = dma_alloc_coherent(NULL, size, | |
2277 | &mp->tx_desc_dma, | |
2278 | GFP_KERNEL); | |
16e03018 | 2279 | |
c9df406f LB |
2280 | if (!mp->p_tx_desc_area) { |
2281 | printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", | |
2282 | dev->name, size); | |
2283 | err = -ENOMEM; | |
2284 | goto out_free_tx_skb; | |
2285 | } | |
2286 | BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */ | |
2287 | memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size); | |
16e03018 | 2288 | |
c9df406f | 2289 | ether_init_tx_desc_ring(mp); |
16e03018 | 2290 | |
c9df406f LB |
2291 | /* Allocate RX ring */ |
2292 | mp->rx_desc_count = 0; | |
2293 | size = mp->rx_ring_size * sizeof(struct eth_rx_desc); | |
2294 | mp->rx_desc_area_size = size; | |
16e03018 | 2295 | |
c9df406f LB |
2296 | if (mp->rx_sram_size) { |
2297 | mp->p_rx_desc_area = ioremap(mp->rx_sram_addr, | |
2298 | mp->rx_sram_size); | |
2299 | mp->rx_desc_dma = mp->rx_sram_addr; | |
2300 | } else | |
2301 | mp->p_rx_desc_area = dma_alloc_coherent(NULL, size, | |
2302 | &mp->rx_desc_dma, | |
2303 | GFP_KERNEL); | |
16e03018 | 2304 | |
c9df406f LB |
2305 | if (!mp->p_rx_desc_area) { |
2306 | printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n", | |
2307 | dev->name, size); | |
2308 | printk(KERN_ERR "%s: Freeing previously allocated TX queues...", | |
2309 | dev->name); | |
2310 | if (mp->rx_sram_size) | |
2311 | iounmap(mp->p_tx_desc_area); | |
2312 | else | |
2313 | dma_free_coherent(NULL, mp->tx_desc_area_size, | |
2314 | mp->p_tx_desc_area, mp->tx_desc_dma); | |
2315 | err = -ENOMEM; | |
2316 | goto out_free_tx_skb; | |
2317 | } | |
2318 | memset((void *)mp->p_rx_desc_area, 0, size); | |
16e03018 | 2319 | |
c9df406f | 2320 | ether_init_rx_desc_ring(mp); |
16e03018 | 2321 | |
c9df406f | 2322 | mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */ |
16e03018 | 2323 | |
c9df406f LB |
2324 | #ifdef MV643XX_NAPI |
2325 | napi_enable(&mp->napi); | |
2326 | #endif | |
16e03018 | 2327 | |
c9df406f | 2328 | eth_port_start(dev); |
16e03018 | 2329 | |
c9df406f | 2330 | /* Interrupt Coalescing */ |
b4de9051 | 2331 | |
c9df406f LB |
2332 | #ifdef MV643XX_COAL |
2333 | mp->rx_int_coal = | |
2334 | eth_port_set_rx_coal(mp, MV643XX_RX_COAL); | |
2335 | #endif | |
2336 | ||
2337 | mp->tx_int_coal = | |
2338 | eth_port_set_tx_coal(mp, MV643XX_TX_COAL); | |
16e03018 | 2339 | |
c9df406f | 2340 | /* Unmask phy and link status changes interrupts */ |
073a345c | 2341 | wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX); |
16e03018 | 2342 | |
c9df406f | 2343 | /* Unmask RX buffer and TX end interrupt */ |
073a345c | 2344 | wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT); |
16e03018 | 2345 | |
c9df406f LB |
2346 | return 0; |
2347 | ||
2348 | out_free_tx_skb: | |
2349 | kfree(mp->tx_skb); | |
2350 | out_free_rx_skb: | |
2351 | kfree(mp->rx_skb); | |
2352 | out_free_irq: | |
2353 | free_irq(dev->irq, dev); | |
2354 | ||
2355 | return err; | |
16e03018 DF |
2356 | } |
2357 | ||
1da177e4 | 2358 | /* |
c9df406f | 2359 | * eth_port_reset - Reset Ethernet port |
1da177e4 LT |
2360 | * |
2361 | * DESCRIPTION: | |
c9df406f LB |
2362 | * This routine resets the chip by aborting any SDMA engine activity and |
2363 | * clearing the MIB counters. The Receiver and the Transmit unit are in | |
2364 | * idle state after this command is performed and the port is disabled. | |
1da177e4 LT |
2365 | * |
2366 | * INPUT: | |
afdb57a2 | 2367 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2368 | * |
2369 | * OUTPUT: | |
c9df406f | 2370 | * Channel activity is halted. |
1da177e4 LT |
2371 | * |
2372 | * RETURN: | |
2373 | * None. | |
c9df406f | 2374 | * |
1da177e4 | 2375 | */ |
c9df406f | 2376 | static void eth_port_reset(struct mv643xx_private *mp) |
1da177e4 | 2377 | { |
afdb57a2 | 2378 | unsigned int port_num = mp->port_num; |
c9df406f | 2379 | unsigned int reg_data; |
1da177e4 | 2380 | |
c9df406f LB |
2381 | mv643xx_eth_port_disable_tx(mp); |
2382 | mv643xx_eth_port_disable_rx(mp); | |
1da177e4 | 2383 | |
c9df406f LB |
2384 | /* Clear all MIB counters */ |
2385 | eth_clear_mib_counters(mp); | |
2386 | ||
2387 | /* Reset the Enable bit in the Configuration Register */ | |
3cb4667c | 2388 | reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num)); |
c9df406f LB |
2389 | reg_data &= ~(SERIAL_PORT_ENABLE | |
2390 | DO_NOT_FORCE_LINK_FAIL | | |
2391 | FORCE_LINK_PASS); | |
3cb4667c | 2392 | wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data); |
1da177e4 LT |
2393 | } |
2394 | ||
2395 | /* | |
c9df406f | 2396 | * mv643xx_eth_stop |
1da177e4 | 2397 | * |
c9df406f LB |
2398 | * This function is used when closing the network device. |
2399 | * It updates the hardware, | |
2400 | * release all memory that holds buffers and descriptors and release the IRQ. | |
2401 | * Input : a pointer to the device structure | |
2402 | * Output : zero if success , nonzero if fails | |
1da177e4 | 2403 | */ |
c9df406f LB |
2404 | |
2405 | static int mv643xx_eth_stop(struct net_device *dev) | |
1da177e4 | 2406 | { |
c9df406f | 2407 | struct mv643xx_private *mp = netdev_priv(dev); |
afdb57a2 | 2408 | unsigned int port_num = mp->port_num; |
1da177e4 | 2409 | |
c9df406f | 2410 | /* Mask all interrupts on ethernet port */ |
073a345c | 2411 | wrl(mp, INT_MASK(port_num), 0x00000000); |
c9df406f | 2412 | /* wait for previous write to complete */ |
3cb4667c | 2413 | rdl(mp, INT_MASK(port_num)); |
1da177e4 | 2414 | |
c9df406f LB |
2415 | #ifdef MV643XX_NAPI |
2416 | napi_disable(&mp->napi); | |
2417 | #endif | |
2418 | netif_carrier_off(dev); | |
2419 | netif_stop_queue(dev); | |
1da177e4 | 2420 | |
c9df406f | 2421 | eth_port_reset(mp); |
1da177e4 | 2422 | |
c9df406f LB |
2423 | mv643xx_eth_free_tx_rings(dev); |
2424 | mv643xx_eth_free_rx_rings(dev); | |
1da177e4 | 2425 | |
c9df406f | 2426 | free_irq(dev->irq, dev); |
1da177e4 | 2427 | |
c9df406f | 2428 | return 0; |
1da177e4 LT |
2429 | } |
2430 | ||
c9df406f | 2431 | static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2432 | { |
c9df406f | 2433 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 | 2434 | |
c9df406f | 2435 | return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL); |
1da177e4 LT |
2436 | } |
2437 | ||
2438 | /* | |
c9df406f | 2439 | * Changes MTU (maximum transfer unit) of the gigabit ethenret port |
1da177e4 | 2440 | * |
c9df406f LB |
2441 | * Input : pointer to ethernet interface network device structure |
2442 | * new mtu size | |
2443 | * Output : 0 upon success, -EINVAL upon failure | |
1da177e4 | 2444 | */ |
c9df406f | 2445 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2446 | { |
c9df406f LB |
2447 | if ((new_mtu > 9500) || (new_mtu < 64)) |
2448 | return -EINVAL; | |
1da177e4 | 2449 | |
c9df406f LB |
2450 | dev->mtu = new_mtu; |
2451 | if (!netif_running(dev)) | |
2452 | return 0; | |
1da177e4 | 2453 | |
c9df406f LB |
2454 | /* |
2455 | * Stop and then re-open the interface. This will allocate RX | |
2456 | * skbs of the new MTU. | |
2457 | * There is a possible danger that the open will not succeed, | |
2458 | * due to memory being full, which might fail the open function. | |
2459 | */ | |
2460 | mv643xx_eth_stop(dev); | |
2461 | if (mv643xx_eth_open(dev)) { | |
2462 | printk(KERN_ERR "%s: Fatal error on opening device\n", | |
2463 | dev->name); | |
2464 | } | |
2465 | ||
2466 | return 0; | |
1da177e4 LT |
2467 | } |
2468 | ||
2469 | /* | |
c9df406f | 2470 | * mv643xx_eth_tx_timeout_task |
1da177e4 | 2471 | * |
c9df406f | 2472 | * Actual routine to reset the adapter when a timeout on Tx has occurred |
1da177e4 | 2473 | */ |
c9df406f | 2474 | static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2475 | { |
c9df406f LB |
2476 | struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private, |
2477 | tx_timeout_task); | |
2478 | struct net_device *dev = mp->dev; | |
1da177e4 | 2479 | |
c9df406f LB |
2480 | if (!netif_running(dev)) |
2481 | return; | |
1da177e4 | 2482 | |
c9df406f LB |
2483 | netif_stop_queue(dev); |
2484 | ||
2485 | eth_port_reset(mp); | |
2486 | eth_port_start(dev); | |
2487 | ||
2488 | if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB) | |
2489 | netif_wake_queue(dev); | |
2490 | } | |
2491 | ||
2492 | /* | |
2493 | * mv643xx_eth_tx_timeout | |
1da177e4 | 2494 | * |
c9df406f | 2495 | * Called upon a timeout on transmitting a packet |
1da177e4 | 2496 | * |
c9df406f LB |
2497 | * Input : pointer to ethernet interface network device structure. |
2498 | * Output : N/A | |
1da177e4 | 2499 | */ |
c9df406f | 2500 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2501 | { |
c9df406f | 2502 | struct mv643xx_private *mp = netdev_priv(dev); |
1da177e4 | 2503 | |
c9df406f | 2504 | printk(KERN_INFO "%s: TX timeout ", dev->name); |
d0412d96 | 2505 | |
c9df406f LB |
2506 | /* Do the reset outside of interrupt context */ |
2507 | schedule_work(&mp->tx_timeout_task); | |
1da177e4 LT |
2508 | } |
2509 | ||
c9df406f LB |
2510 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2511 | static void mv643xx_netpoll(struct net_device *netdev) | |
9f8dd319 | 2512 | { |
c9df406f LB |
2513 | struct mv643xx_private *mp = netdev_priv(netdev); |
2514 | int port_num = mp->port_num; | |
2515 | ||
073a345c | 2516 | wrl(mp, INT_MASK(port_num), 0x00000000); |
c9df406f | 2517 | /* wait for previous write to complete */ |
3cb4667c | 2518 | rdl(mp, INT_MASK(port_num)); |
c9df406f LB |
2519 | |
2520 | mv643xx_eth_int_handler(netdev->irq, netdev); | |
2521 | ||
073a345c | 2522 | wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT); |
9f8dd319 | 2523 | } |
c9df406f | 2524 | #endif |
9f8dd319 | 2525 | |
c9df406f LB |
2526 | /* |
2527 | * Wrappers for MII support library. | |
2528 | */ | |
2529 | static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location) | |
9f8dd319 | 2530 | { |
c9df406f LB |
2531 | struct mv643xx_private *mp = netdev_priv(dev); |
2532 | int val; | |
2533 | ||
2534 | eth_port_read_smi_reg(mp, location, &val); | |
2535 | return val; | |
9f8dd319 DF |
2536 | } |
2537 | ||
c9df406f | 2538 | static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val) |
9f8dd319 | 2539 | { |
c9df406f LB |
2540 | struct mv643xx_private *mp = netdev_priv(dev); |
2541 | eth_port_write_smi_reg(mp, location, val); | |
2542 | } | |
9f8dd319 | 2543 | |
9f8dd319 | 2544 | |
c9df406f LB |
2545 | /* platform glue ************************************************************/ |
2546 | static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp, | |
2547 | struct mbus_dram_target_info *dram) | |
2548 | { | |
2549 | void __iomem *base = msp->eth_base; | |
2550 | u32 win_enable; | |
2551 | u32 win_protect; | |
2552 | int i; | |
9f8dd319 | 2553 | |
c9df406f LB |
2554 | for (i = 0; i < 6; i++) { |
2555 | writel(0, base + WINDOW_BASE(i)); | |
2556 | writel(0, base + WINDOW_SIZE(i)); | |
2557 | if (i < 4) | |
2558 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2559 | } |
2560 | ||
c9df406f LB |
2561 | win_enable = 0x3f; |
2562 | win_protect = 0; | |
2563 | ||
2564 | for (i = 0; i < dram->num_cs; i++) { | |
2565 | struct mbus_dram_window *cs = dram->cs + i; | |
2566 | ||
2567 | writel((cs->base & 0xffff0000) | | |
2568 | (cs->mbus_attr << 8) | | |
2569 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2570 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2571 | ||
2572 | win_enable &= ~(1 << i); | |
2573 | win_protect |= 3 << (2 * i); | |
2574 | } | |
2575 | ||
2576 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2577 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2578 | } |
2579 | ||
c9df406f | 2580 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2581 | { |
c9df406f LB |
2582 | static int mv643xx_version_printed = 0; |
2583 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; | |
2584 | struct mv643xx_shared_private *msp; | |
2585 | struct resource *res; | |
2586 | int ret; | |
9f8dd319 | 2587 | |
c9df406f LB |
2588 | if (!mv643xx_version_printed++) |
2589 | printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); | |
9f8dd319 | 2590 | |
c9df406f LB |
2591 | ret = -EINVAL; |
2592 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2593 | if (res == NULL) | |
2594 | goto out; | |
9f8dd319 | 2595 | |
c9df406f LB |
2596 | ret = -ENOMEM; |
2597 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2598 | if (msp == NULL) | |
2599 | goto out; | |
2600 | memset(msp, 0, sizeof(*msp)); | |
2601 | ||
2602 | msp->eth_base = ioremap(res->start, res->end - res->start + 1); | |
2603 | if (msp->eth_base == NULL) | |
2604 | goto out_free; | |
2605 | ||
2606 | spin_lock_init(&msp->phy_lock); | |
2607 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
2608 | ||
2609 | platform_set_drvdata(pdev, msp); | |
2610 | ||
2611 | /* | |
2612 | * (Re-)program MBUS remapping windows if we are asked to. | |
2613 | */ | |
2614 | if (pd != NULL && pd->dram != NULL) | |
2615 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2616 | ||
2617 | return 0; | |
2618 | ||
2619 | out_free: | |
2620 | kfree(msp); | |
2621 | out: | |
2622 | return ret; | |
2623 | } | |
2624 | ||
2625 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2626 | { | |
2627 | struct mv643xx_shared_private *msp = platform_get_drvdata(pdev); | |
2628 | ||
2629 | iounmap(msp->eth_base); | |
2630 | kfree(msp); | |
2631 | ||
2632 | return 0; | |
9f8dd319 DF |
2633 | } |
2634 | ||
c9df406f LB |
2635 | static struct platform_driver mv643xx_eth_shared_driver = { |
2636 | .probe = mv643xx_eth_shared_probe, | |
2637 | .remove = mv643xx_eth_shared_remove, | |
2638 | .driver = { | |
2639 | .name = MV643XX_ETH_SHARED_NAME, | |
2640 | .owner = THIS_MODULE, | |
2641 | }, | |
2642 | }; | |
2643 | ||
1da177e4 | 2644 | /* |
c9df406f | 2645 | * ethernet_phy_set - Set the ethernet port PHY address. |
1da177e4 LT |
2646 | * |
2647 | * DESCRIPTION: | |
c9df406f | 2648 | * This routine sets the given ethernet port PHY address. |
1da177e4 LT |
2649 | * |
2650 | * INPUT: | |
afdb57a2 | 2651 | * struct mv643xx_private *mp Ethernet Port. |
c9df406f | 2652 | * int phy_addr PHY address. |
1da177e4 LT |
2653 | * |
2654 | * OUTPUT: | |
c9df406f | 2655 | * None. |
1da177e4 LT |
2656 | * |
2657 | * RETURN: | |
2658 | * None. | |
2659 | * | |
2660 | */ | |
c9df406f | 2661 | static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr) |
1da177e4 | 2662 | { |
c9df406f LB |
2663 | u32 reg_data; |
2664 | int addr_shift = 5 * mp->port_num; | |
1da177e4 | 2665 | |
3cb4667c | 2666 | reg_data = rdl(mp, PHY_ADDR); |
c9df406f LB |
2667 | reg_data &= ~(0x1f << addr_shift); |
2668 | reg_data |= (phy_addr & 0x1f) << addr_shift; | |
3cb4667c | 2669 | wrl(mp, PHY_ADDR, reg_data); |
1da177e4 LT |
2670 | } |
2671 | ||
1da177e4 | 2672 | /* |
c9df406f | 2673 | * ethernet_phy_get - Get the ethernet port PHY address. |
1da177e4 LT |
2674 | * |
2675 | * DESCRIPTION: | |
c9df406f | 2676 | * This routine returns the given ethernet port PHY address. |
1da177e4 LT |
2677 | * |
2678 | * INPUT: | |
afdb57a2 | 2679 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2680 | * |
2681 | * OUTPUT: | |
c9df406f | 2682 | * None. |
1da177e4 LT |
2683 | * |
2684 | * RETURN: | |
c9df406f | 2685 | * PHY address. |
1da177e4 LT |
2686 | * |
2687 | */ | |
c9df406f | 2688 | static int ethernet_phy_get(struct mv643xx_private *mp) |
1da177e4 | 2689 | { |
c9df406f | 2690 | unsigned int reg_data; |
1da177e4 | 2691 | |
3cb4667c | 2692 | reg_data = rdl(mp, PHY_ADDR); |
1da177e4 | 2693 | |
c9df406f | 2694 | return ((reg_data >> (5 * mp->port_num)) & 0x1f); |
1da177e4 LT |
2695 | } |
2696 | ||
2697 | /* | |
c9df406f | 2698 | * ethernet_phy_detect - Detect whether a phy is present |
1da177e4 LT |
2699 | * |
2700 | * DESCRIPTION: | |
c9df406f LB |
2701 | * This function tests whether there is a PHY present on |
2702 | * the specified port. | |
1da177e4 LT |
2703 | * |
2704 | * INPUT: | |
afdb57a2 | 2705 | * struct mv643xx_private *mp Ethernet Port. |
1da177e4 LT |
2706 | * |
2707 | * OUTPUT: | |
c9df406f | 2708 | * None |
1da177e4 LT |
2709 | * |
2710 | * RETURN: | |
c9df406f LB |
2711 | * 0 on success |
2712 | * -ENODEV on failure | |
1da177e4 LT |
2713 | * |
2714 | */ | |
c9df406f | 2715 | static int ethernet_phy_detect(struct mv643xx_private *mp) |
1da177e4 | 2716 | { |
c9df406f LB |
2717 | unsigned int phy_reg_data0; |
2718 | int auto_neg; | |
1da177e4 | 2719 | |
c9df406f LB |
2720 | eth_port_read_smi_reg(mp, 0, &phy_reg_data0); |
2721 | auto_neg = phy_reg_data0 & 0x1000; | |
2722 | phy_reg_data0 ^= 0x1000; /* invert auto_neg */ | |
2723 | eth_port_write_smi_reg(mp, 0, phy_reg_data0); | |
1da177e4 | 2724 | |
c9df406f LB |
2725 | eth_port_read_smi_reg(mp, 0, &phy_reg_data0); |
2726 | if ((phy_reg_data0 & 0x1000) == auto_neg) | |
2727 | return -ENODEV; /* change didn't take */ | |
1da177e4 | 2728 | |
c9df406f LB |
2729 | phy_reg_data0 ^= 0x1000; |
2730 | eth_port_write_smi_reg(mp, 0, phy_reg_data0); | |
2731 | return 0; | |
1da177e4 LT |
2732 | } |
2733 | ||
c9df406f LB |
2734 | static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address, |
2735 | int speed, int duplex, | |
2736 | struct ethtool_cmd *cmd) | |
c28a4f89 | 2737 | { |
c28a4f89 JC |
2738 | struct mv643xx_private *mp = netdev_priv(dev); |
2739 | ||
c9df406f | 2740 | memset(cmd, 0, sizeof(*cmd)); |
c28a4f89 | 2741 | |
c9df406f LB |
2742 | cmd->port = PORT_MII; |
2743 | cmd->transceiver = XCVR_INTERNAL; | |
2744 | cmd->phy_address = phy_address; | |
2745 | ||
2746 | if (speed == 0) { | |
2747 | cmd->autoneg = AUTONEG_ENABLE; | |
2748 | /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */ | |
2749 | cmd->speed = SPEED_100; | |
2750 | cmd->advertising = ADVERTISED_10baseT_Half | | |
2751 | ADVERTISED_10baseT_Full | | |
2752 | ADVERTISED_100baseT_Half | | |
2753 | ADVERTISED_100baseT_Full; | |
2754 | if (mp->mii.supports_gmii) | |
2755 | cmd->advertising |= ADVERTISED_1000baseT_Full; | |
2756 | } else { | |
2757 | cmd->autoneg = AUTONEG_DISABLE; | |
2758 | cmd->speed = speed; | |
2759 | cmd->duplex = duplex; | |
2760 | } | |
c28a4f89 JC |
2761 | } |
2762 | ||
c9df406f LB |
2763 | /*/ |
2764 | * mv643xx_eth_probe | |
1da177e4 | 2765 | * |
c9df406f LB |
2766 | * First function called after registering the network device. |
2767 | * It's purpose is to initialize the device as an ethernet device, | |
2768 | * fill the ethernet device structure with pointers * to functions, | |
2769 | * and set the MAC address of the interface | |
1da177e4 | 2770 | * |
c9df406f LB |
2771 | * Input : struct device * |
2772 | * Output : -ENOMEM if failed , 0 if success | |
1da177e4 | 2773 | */ |
c9df406f | 2774 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2775 | { |
c9df406f LB |
2776 | struct mv643xx_eth_platform_data *pd; |
2777 | int port_num; | |
2778 | struct mv643xx_private *mp; | |
2779 | struct net_device *dev; | |
2780 | u8 *p; | |
2781 | struct resource *res; | |
2782 | int err; | |
2783 | struct ethtool_cmd cmd; | |
2784 | int duplex = DUPLEX_HALF; | |
2785 | int speed = 0; /* default to auto-negotiation */ | |
2786 | DECLARE_MAC_BUF(mac); | |
1da177e4 | 2787 | |
c9df406f LB |
2788 | pd = pdev->dev.platform_data; |
2789 | if (pd == NULL) { | |
2790 | printk(KERN_ERR "No mv643xx_eth_platform_data\n"); | |
2791 | return -ENODEV; | |
2792 | } | |
1da177e4 | 2793 | |
c9df406f LB |
2794 | if (pd->shared == NULL) { |
2795 | printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n"); | |
2796 | return -ENODEV; | |
2797 | } | |
8f518703 | 2798 | |
c9df406f LB |
2799 | dev = alloc_etherdev(sizeof(struct mv643xx_private)); |
2800 | if (!dev) | |
2801 | return -ENOMEM; | |
1da177e4 | 2802 | |
c9df406f | 2803 | platform_set_drvdata(pdev, dev); |
1da177e4 | 2804 | |
c9df406f LB |
2805 | mp = netdev_priv(dev); |
2806 | mp->dev = dev; | |
2807 | #ifdef MV643XX_NAPI | |
2808 | netif_napi_add(dev, &mp->napi, mv643xx_poll, 64); | |
2809 | #endif | |
1da177e4 | 2810 | |
c9df406f LB |
2811 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2812 | BUG_ON(!res); | |
2813 | dev->irq = res->start; | |
1da177e4 | 2814 | |
c9df406f LB |
2815 | dev->open = mv643xx_eth_open; |
2816 | dev->stop = mv643xx_eth_stop; | |
2817 | dev->hard_start_xmit = mv643xx_eth_start_xmit; | |
2818 | dev->set_mac_address = mv643xx_eth_set_mac_address; | |
2819 | dev->set_multicast_list = mv643xx_eth_set_rx_mode; | |
2820 | ||
2821 | /* No need to Tx Timeout */ | |
2822 | dev->tx_timeout = mv643xx_eth_tx_timeout; | |
2823 | ||
2824 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2825 | dev->poll_controller = mv643xx_netpoll; | |
2826 | #endif | |
2827 | ||
2828 | dev->watchdog_timeo = 2 * HZ; | |
2829 | dev->base_addr = 0; | |
2830 | dev->change_mtu = mv643xx_eth_change_mtu; | |
2831 | dev->do_ioctl = mv643xx_eth_do_ioctl; | |
2832 | SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops); | |
1da177e4 | 2833 | |
c9df406f LB |
2834 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
2835 | #ifdef MAX_SKB_FRAGS | |
b4de9051 | 2836 | /* |
c9df406f LB |
2837 | * Zero copy can only work if we use Discovery II memory. Else, we will |
2838 | * have to map the buffers to ISA memory which is only 16 MB | |
b4de9051 | 2839 | */ |
c9df406f LB |
2840 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
2841 | #endif | |
2842 | #endif | |
1da177e4 | 2843 | |
c9df406f LB |
2844 | /* Configure the timeout task */ |
2845 | INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task); | |
1da177e4 | 2846 | |
c9df406f | 2847 | spin_lock_init(&mp->lock); |
1da177e4 | 2848 | |
c9df406f LB |
2849 | mp->shared = platform_get_drvdata(pd->shared); |
2850 | port_num = mp->port_num = pd->port_number; | |
8f518703 | 2851 | |
c9df406f LB |
2852 | if (mp->shared->win_protect) |
2853 | wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect); | |
1da177e4 | 2854 | |
c9df406f LB |
2855 | mp->shared_smi = mp->shared; |
2856 | if (pd->shared_smi != NULL) | |
2857 | mp->shared_smi = platform_get_drvdata(pd->shared_smi); | |
2858 | ||
2859 | /* set default config values */ | |
2860 | eth_port_uc_addr_get(mp, dev->dev_addr); | |
2861 | mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE; | |
2862 | mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE; | |
2863 | ||
2864 | if (is_valid_ether_addr(pd->mac_addr)) | |
2865 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2866 | ||
2867 | if (pd->phy_addr || pd->force_phy_addr) | |
2868 | ethernet_phy_set(mp, pd->phy_addr); | |
8f518703 | 2869 | |
c9df406f LB |
2870 | if (pd->rx_queue_size) |
2871 | mp->rx_ring_size = pd->rx_queue_size; | |
1da177e4 | 2872 | |
c9df406f LB |
2873 | if (pd->tx_queue_size) |
2874 | mp->tx_ring_size = pd->tx_queue_size; | |
1da177e4 | 2875 | |
c9df406f LB |
2876 | if (pd->tx_sram_size) { |
2877 | mp->tx_sram_size = pd->tx_sram_size; | |
2878 | mp->tx_sram_addr = pd->tx_sram_addr; | |
2879 | } | |
1da177e4 | 2880 | |
c9df406f LB |
2881 | if (pd->rx_sram_size) { |
2882 | mp->rx_sram_size = pd->rx_sram_size; | |
2883 | mp->rx_sram_addr = pd->rx_sram_addr; | |
2884 | } | |
1da177e4 | 2885 | |
c9df406f LB |
2886 | duplex = pd->duplex; |
2887 | speed = pd->speed; | |
1da177e4 | 2888 | |
c9df406f LB |
2889 | /* Hook up MII support for ethtool */ |
2890 | mp->mii.dev = dev; | |
2891 | mp->mii.mdio_read = mv643xx_mdio_read; | |
2892 | mp->mii.mdio_write = mv643xx_mdio_write; | |
2893 | mp->mii.phy_id = ethernet_phy_get(mp); | |
2894 | mp->mii.phy_id_mask = 0x3f; | |
2895 | mp->mii.reg_num_mask = 0x1f; | |
1da177e4 | 2896 | |
c9df406f LB |
2897 | err = ethernet_phy_detect(mp); |
2898 | if (err) { | |
2899 | pr_debug("%s: No PHY detected at addr %d\n", | |
2900 | dev->name, ethernet_phy_get(mp)); | |
2901 | goto out; | |
2902 | } | |
1da177e4 | 2903 | |
c9df406f LB |
2904 | ethernet_phy_reset(mp); |
2905 | mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii); | |
2906 | mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd); | |
2907 | mv643xx_eth_update_pscr(dev, &cmd); | |
2908 | mv643xx_set_settings(dev, &cmd); | |
8f518703 | 2909 | |
c9df406f LB |
2910 | SET_NETDEV_DEV(dev, &pdev->dev); |
2911 | err = register_netdev(dev); | |
2912 | if (err) | |
2913 | goto out; | |
1da177e4 | 2914 | |
c9df406f LB |
2915 | p = dev->dev_addr; |
2916 | printk(KERN_NOTICE | |
2917 | "%s: port %d with MAC address %s\n", | |
2918 | dev->name, port_num, print_mac(mac, p)); | |
1da177e4 | 2919 | |
c9df406f LB |
2920 | if (dev->features & NETIF_F_SG) |
2921 | printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name); | |
1da177e4 | 2922 | |
c9df406f LB |
2923 | if (dev->features & NETIF_F_IP_CSUM) |
2924 | printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n", | |
2925 | dev->name); | |
1da177e4 | 2926 | |
c9df406f LB |
2927 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
2928 | printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name); | |
2929 | #endif | |
1da177e4 | 2930 | |
c9df406f LB |
2931 | #ifdef MV643XX_COAL |
2932 | printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n", | |
2933 | dev->name); | |
2934 | #endif | |
1da177e4 | 2935 | |
c9df406f LB |
2936 | #ifdef MV643XX_NAPI |
2937 | printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); | |
2938 | #endif | |
1da177e4 | 2939 | |
c9df406f LB |
2940 | if (mp->tx_sram_size > 0) |
2941 | printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); | |
1da177e4 | 2942 | |
c9df406f | 2943 | return 0; |
1da177e4 | 2944 | |
c9df406f LB |
2945 | out: |
2946 | free_netdev(dev); | |
1da177e4 | 2947 | |
c9df406f | 2948 | return err; |
1da177e4 LT |
2949 | } |
2950 | ||
c9df406f | 2951 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2952 | { |
c9df406f | 2953 | struct net_device *dev = platform_get_drvdata(pdev); |
1da177e4 | 2954 | |
c9df406f LB |
2955 | unregister_netdev(dev); |
2956 | flush_scheduled_work(); | |
2957 | ||
2958 | free_netdev(dev); | |
2959 | platform_set_drvdata(pdev, NULL); | |
2960 | return 0; | |
1da177e4 LT |
2961 | } |
2962 | ||
c9df406f | 2963 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 2964 | { |
c9df406f | 2965 | struct net_device *dev = platform_get_drvdata(pdev); |
d0412d96 | 2966 | struct mv643xx_private *mp = netdev_priv(dev); |
c9df406f | 2967 | unsigned int port_num = mp->port_num; |
d0412d96 | 2968 | |
c9df406f | 2969 | /* Mask all interrupts on ethernet port */ |
3cb4667c LB |
2970 | wrl(mp, INT_MASK(port_num), 0); |
2971 | rdl(mp, INT_MASK(port_num)); | |
c9df406f LB |
2972 | |
2973 | eth_port_reset(mp); | |
d0412d96 JC |
2974 | } |
2975 | ||
c9df406f LB |
2976 | static struct platform_driver mv643xx_eth_driver = { |
2977 | .probe = mv643xx_eth_probe, | |
2978 | .remove = mv643xx_eth_remove, | |
2979 | .shutdown = mv643xx_eth_shutdown, | |
2980 | .driver = { | |
2981 | .name = MV643XX_ETH_NAME, | |
2982 | .owner = THIS_MODULE, | |
2983 | }, | |
2984 | }; | |
2985 | ||
2986 | /* | |
2987 | * mv643xx_init_module | |
2988 | * | |
2989 | * Registers the network drivers into the Linux kernel | |
2990 | * | |
2991 | * Input : N/A | |
2992 | * | |
2993 | * Output : N/A | |
2994 | */ | |
2995 | static int __init mv643xx_init_module(void) | |
d0412d96 | 2996 | { |
c9df406f | 2997 | int rc; |
d0412d96 | 2998 | |
c9df406f LB |
2999 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
3000 | if (!rc) { | |
3001 | rc = platform_driver_register(&mv643xx_eth_driver); | |
3002 | if (rc) | |
3003 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
3004 | } | |
3005 | return rc; | |
d0412d96 JC |
3006 | } |
3007 | ||
c9df406f LB |
3008 | /* |
3009 | * mv643xx_cleanup_module | |
3010 | * | |
3011 | * Registers the network drivers into the Linux kernel | |
3012 | * | |
3013 | * Input : N/A | |
3014 | * | |
3015 | * Output : N/A | |
3016 | */ | |
3017 | static void __exit mv643xx_cleanup_module(void) | |
d0412d96 | 3018 | { |
c9df406f LB |
3019 | platform_driver_unregister(&mv643xx_eth_driver); |
3020 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 JC |
3021 | } |
3022 | ||
c9df406f LB |
3023 | module_init(mv643xx_init_module); |
3024 | module_exit(mv643xx_cleanup_module); | |
1da177e4 | 3025 | |
c9df406f LB |
3026 | MODULE_LICENSE("GPL"); |
3027 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" | |
3028 | " and Dale Farnsworth"); | |
3029 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); | |
3030 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); | |
3031 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |