Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
9c1bbdfe | 2 | * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports |
1da177e4 LT |
3 | * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> |
4 | * | |
5 | * Based on the 64360 driver from: | |
4547fa61 LB |
6 | * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> |
7 | * Rabeeh Khoury <rabeeh@marvell.com> | |
1da177e4 LT |
8 | * |
9 | * Copyright (C) 2003 PMC-Sierra, Inc., | |
3bb8a18a | 10 | * written by Manish Lachwani |
1da177e4 LT |
11 | * |
12 | * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> | |
13 | * | |
c8aaea25 | 14 | * Copyright (C) 2004-2006 MontaVista Software, Inc. |
1da177e4 LT |
15 | * Dale Farnsworth <dale@farnsworth.org> |
16 | * | |
17 | * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> | |
18 | * <sjhill@realitydiluted.com> | |
19 | * | |
4547fa61 LB |
20 | * Copyright (C) 2007-2008 Marvell Semiconductor |
21 | * Lennert Buytenhek <buytenh@marvell.com> | |
22 | * | |
1da177e4 LT |
23 | * This program is free software; you can redistribute it and/or |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version 2 | |
26 | * of the License, or (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
36 | */ | |
a779d38c | 37 | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/dma-mapping.h> | |
b6298c22 | 40 | #include <linux/in.h> |
c3efab8e | 41 | #include <linux/ip.h> |
1da177e4 LT |
42 | #include <linux/tcp.h> |
43 | #include <linux/udp.h> | |
44 | #include <linux/etherdevice.h> | |
1da177e4 LT |
45 | #include <linux/delay.h> |
46 | #include <linux/ethtool.h> | |
d052d1be | 47 | #include <linux/platform_device.h> |
fbd6a754 LB |
48 | #include <linux/module.h> |
49 | #include <linux/kernel.h> | |
50 | #include <linux/spinlock.h> | |
51 | #include <linux/workqueue.h> | |
ed94493f | 52 | #include <linux/phy.h> |
fbd6a754 | 53 | #include <linux/mv643xx_eth.h> |
10a9948d LB |
54 | #include <linux/io.h> |
55 | #include <linux/types.h> | |
1da177e4 | 56 | #include <asm/system.h> |
fbd6a754 | 57 | |
e5371493 | 58 | static char mv643xx_eth_driver_name[] = "mv643xx_eth"; |
042af53c | 59 | static char mv643xx_eth_driver_version[] = "1.4"; |
c9df406f | 60 | |
fbd6a754 | 61 | |
fbd6a754 LB |
62 | /* |
63 | * Registers shared between all ports. | |
64 | */ | |
3cb4667c LB |
65 | #define PHY_ADDR 0x0000 |
66 | #define SMI_REG 0x0004 | |
45c5d3bc LB |
67 | #define SMI_BUSY 0x10000000 |
68 | #define SMI_READ_VALID 0x08000000 | |
69 | #define SMI_OPCODE_READ 0x04000000 | |
70 | #define SMI_OPCODE_WRITE 0x00000000 | |
71 | #define ERR_INT_CAUSE 0x0080 | |
72 | #define ERR_INT_SMI_DONE 0x00000010 | |
73 | #define ERR_INT_MASK 0x0084 | |
3cb4667c LB |
74 | #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) |
75 | #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) | |
76 | #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) | |
77 | #define WINDOW_BAR_ENABLE 0x0290 | |
78 | #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) | |
fbd6a754 LB |
79 | |
80 | /* | |
37a6084f LB |
81 | * Main per-port registers. These live at offset 0x0400 for |
82 | * port #0, 0x0800 for port #1, and 0x0c00 for port #2. | |
fbd6a754 | 83 | */ |
37a6084f | 84 | #define PORT_CONFIG 0x0000 |
d9a073ea | 85 | #define UNICAST_PROMISCUOUS_MODE 0x00000001 |
37a6084f LB |
86 | #define PORT_CONFIG_EXT 0x0004 |
87 | #define MAC_ADDR_LOW 0x0014 | |
88 | #define MAC_ADDR_HIGH 0x0018 | |
89 | #define SDMA_CONFIG 0x001c | |
90 | #define PORT_SERIAL_CONTROL 0x003c | |
91 | #define PORT_STATUS 0x0044 | |
a2a41689 | 92 | #define TX_FIFO_EMPTY 0x00000400 |
ae9ae064 | 93 | #define TX_IN_PROGRESS 0x00000080 |
2f7eb47a LB |
94 | #define PORT_SPEED_MASK 0x00000030 |
95 | #define PORT_SPEED_1000 0x00000010 | |
96 | #define PORT_SPEED_100 0x00000020 | |
97 | #define PORT_SPEED_10 0x00000000 | |
98 | #define FLOW_CONTROL_ENABLED 0x00000008 | |
99 | #define FULL_DUPLEX 0x00000004 | |
81600eea | 100 | #define LINK_UP 0x00000002 |
37a6084f LB |
101 | #define TXQ_COMMAND 0x0048 |
102 | #define TXQ_FIX_PRIO_CONF 0x004c | |
103 | #define TX_BW_RATE 0x0050 | |
104 | #define TX_BW_MTU 0x0058 | |
105 | #define TX_BW_BURST 0x005c | |
106 | #define INT_CAUSE 0x0060 | |
226bb6b7 | 107 | #define INT_TX_END 0x07f80000 |
befefe21 | 108 | #define INT_RX 0x000003fc |
073a345c | 109 | #define INT_EXT 0x00000002 |
37a6084f | 110 | #define INT_CAUSE_EXT 0x0064 |
befefe21 LB |
111 | #define INT_EXT_LINK_PHY 0x00110000 |
112 | #define INT_EXT_TX 0x000000ff | |
37a6084f LB |
113 | #define INT_MASK 0x0068 |
114 | #define INT_MASK_EXT 0x006c | |
115 | #define TX_FIFO_URGENT_THRESHOLD 0x0074 | |
116 | #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc | |
117 | #define TX_BW_RATE_MOVED 0x00e0 | |
118 | #define TX_BW_MTU_MOVED 0x00e8 | |
119 | #define TX_BW_BURST_MOVED 0x00ec | |
120 | #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) | |
121 | #define RXQ_COMMAND 0x0280 | |
122 | #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) | |
123 | #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) | |
124 | #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) | |
125 | #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) | |
126 | ||
127 | /* | |
128 | * Misc per-port registers. | |
129 | */ | |
3cb4667c LB |
130 | #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) |
131 | #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) | |
132 | #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) | |
133 | #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) | |
fbd6a754 | 134 | |
2679a550 LB |
135 | |
136 | /* | |
137 | * SDMA configuration register. | |
138 | */ | |
e0c6ef93 | 139 | #define RX_BURST_SIZE_4_64BIT (2 << 1) |
cd4ccf76 | 140 | #define RX_BURST_SIZE_16_64BIT (4 << 1) |
fbd6a754 | 141 | #define BLM_RX_NO_SWAP (1 << 4) |
fbd6a754 | 142 | #define BLM_TX_NO_SWAP (1 << 5) |
e0c6ef93 | 143 | #define TX_BURST_SIZE_4_64BIT (2 << 22) |
cd4ccf76 | 144 | #define TX_BURST_SIZE_16_64BIT (4 << 22) |
fbd6a754 LB |
145 | |
146 | #if defined(__BIG_ENDIAN) | |
147 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
148 | (RX_BURST_SIZE_4_64BIT | \ |
149 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
150 | #elif defined(__LITTLE_ENDIAN) |
151 | #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ | |
e0c6ef93 LB |
152 | (RX_BURST_SIZE_4_64BIT | \ |
153 | BLM_RX_NO_SWAP | \ | |
154 | BLM_TX_NO_SWAP | \ | |
155 | TX_BURST_SIZE_4_64BIT) | |
fbd6a754 LB |
156 | #else |
157 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
158 | #endif | |
159 | ||
2beff77b LB |
160 | |
161 | /* | |
162 | * Port serial control register. | |
163 | */ | |
164 | #define SET_MII_SPEED_TO_100 (1 << 24) | |
165 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | |
166 | #define SET_FULL_DUPLEX_MODE (1 << 21) | |
fbd6a754 | 167 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
2beff77b LB |
168 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
169 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | |
170 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | |
171 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | |
172 | #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) | |
173 | #define FORCE_LINK_PASS (1 << 1) | |
174 | #define SERIAL_PORT_ENABLE (1 << 0) | |
fbd6a754 | 175 | |
2b4a624d LB |
176 | #define DEFAULT_RX_QUEUE_SIZE 128 |
177 | #define DEFAULT_TX_QUEUE_SIZE 256 | |
fbd6a754 | 178 | |
fbd6a754 | 179 | |
7ca72a3b LB |
180 | /* |
181 | * RX/TX descriptors. | |
fbd6a754 LB |
182 | */ |
183 | #if defined(__BIG_ENDIAN) | |
cc9754b3 | 184 | struct rx_desc { |
fbd6a754 LB |
185 | u16 byte_cnt; /* Descriptor buffer byte count */ |
186 | u16 buf_size; /* Buffer size */ | |
187 | u32 cmd_sts; /* Descriptor command status */ | |
188 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
189 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
190 | }; | |
191 | ||
cc9754b3 | 192 | struct tx_desc { |
fbd6a754 LB |
193 | u16 byte_cnt; /* buffer byte count */ |
194 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
195 | u32 cmd_sts; /* Command/status field */ | |
196 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
197 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
198 | }; | |
199 | #elif defined(__LITTLE_ENDIAN) | |
cc9754b3 | 200 | struct rx_desc { |
fbd6a754 LB |
201 | u32 cmd_sts; /* Descriptor command status */ |
202 | u16 buf_size; /* Buffer size */ | |
203 | u16 byte_cnt; /* Descriptor buffer byte count */ | |
204 | u32 buf_ptr; /* Descriptor buffer pointer */ | |
205 | u32 next_desc_ptr; /* Next descriptor pointer */ | |
206 | }; | |
207 | ||
cc9754b3 | 208 | struct tx_desc { |
fbd6a754 LB |
209 | u32 cmd_sts; /* Command/status field */ |
210 | u16 l4i_chk; /* CPU provided TCP checksum */ | |
211 | u16 byte_cnt; /* buffer byte count */ | |
212 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ | |
213 | u32 next_desc_ptr; /* Pointer to next descriptor */ | |
214 | }; | |
215 | #else | |
216 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | |
217 | #endif | |
218 | ||
7ca72a3b | 219 | /* RX & TX descriptor command */ |
cc9754b3 | 220 | #define BUFFER_OWNED_BY_DMA 0x80000000 |
7ca72a3b LB |
221 | |
222 | /* RX & TX descriptor status */ | |
cc9754b3 | 223 | #define ERROR_SUMMARY 0x00000001 |
7ca72a3b LB |
224 | |
225 | /* RX descriptor status */ | |
cc9754b3 LB |
226 | #define LAYER_4_CHECKSUM_OK 0x40000000 |
227 | #define RX_ENABLE_INTERRUPT 0x20000000 | |
228 | #define RX_FIRST_DESC 0x08000000 | |
229 | #define RX_LAST_DESC 0x04000000 | |
7ca72a3b LB |
230 | |
231 | /* TX descriptor command */ | |
cc9754b3 LB |
232 | #define TX_ENABLE_INTERRUPT 0x00800000 |
233 | #define GEN_CRC 0x00400000 | |
234 | #define TX_FIRST_DESC 0x00200000 | |
235 | #define TX_LAST_DESC 0x00100000 | |
236 | #define ZERO_PADDING 0x00080000 | |
237 | #define GEN_IP_V4_CHECKSUM 0x00040000 | |
238 | #define GEN_TCP_UDP_CHECKSUM 0x00020000 | |
239 | #define UDP_FRAME 0x00010000 | |
e32b6617 LB |
240 | #define MAC_HDR_EXTRA_4_BYTES 0x00008000 |
241 | #define MAC_HDR_EXTRA_8_BYTES 0x00000200 | |
7ca72a3b | 242 | |
cc9754b3 | 243 | #define TX_IHL_SHIFT 11 |
7ca72a3b LB |
244 | |
245 | ||
c9df406f | 246 | /* global *******************************************************************/ |
e5371493 | 247 | struct mv643xx_eth_shared_private { |
fc32b0e2 LB |
248 | /* |
249 | * Ethernet controller base address. | |
250 | */ | |
cc9754b3 | 251 | void __iomem *base; |
c9df406f | 252 | |
fc0eb9f2 LB |
253 | /* |
254 | * Points at the right SMI instance to use. | |
255 | */ | |
256 | struct mv643xx_eth_shared_private *smi; | |
257 | ||
fc32b0e2 | 258 | /* |
ed94493f | 259 | * Provides access to local SMI interface. |
fc32b0e2 | 260 | */ |
298cf9be | 261 | struct mii_bus *smi_bus; |
c9df406f | 262 | |
45c5d3bc LB |
263 | /* |
264 | * If we have access to the error interrupt pin (which is | |
265 | * somewhat misnamed as it not only reflects internal errors | |
266 | * but also reflects SMI completion), use that to wait for | |
267 | * SMI access completion instead of polling the SMI busy bit. | |
268 | */ | |
269 | int err_interrupt; | |
270 | wait_queue_head_t smi_busy_wait; | |
271 | ||
fc32b0e2 LB |
272 | /* |
273 | * Per-port MBUS window access register value. | |
274 | */ | |
c9df406f LB |
275 | u32 win_protect; |
276 | ||
fc32b0e2 LB |
277 | /* |
278 | * Hardware-specific parameters. | |
279 | */ | |
c9df406f | 280 | unsigned int t_clk; |
773fc3ee | 281 | int extended_rx_coal_limit; |
457b1d5a | 282 | int tx_bw_control; |
c9df406f LB |
283 | }; |
284 | ||
457b1d5a LB |
285 | #define TX_BW_CONTROL_ABSENT 0 |
286 | #define TX_BW_CONTROL_OLD_LAYOUT 1 | |
287 | #define TX_BW_CONTROL_NEW_LAYOUT 2 | |
288 | ||
e7d2f4db LB |
289 | static int mv643xx_eth_open(struct net_device *dev); |
290 | static int mv643xx_eth_stop(struct net_device *dev); | |
291 | ||
c9df406f LB |
292 | |
293 | /* per-port *****************************************************************/ | |
e5371493 | 294 | struct mib_counters { |
fbd6a754 LB |
295 | u64 good_octets_received; |
296 | u32 bad_octets_received; | |
297 | u32 internal_mac_transmit_err; | |
298 | u32 good_frames_received; | |
299 | u32 bad_frames_received; | |
300 | u32 broadcast_frames_received; | |
301 | u32 multicast_frames_received; | |
302 | u32 frames_64_octets; | |
303 | u32 frames_65_to_127_octets; | |
304 | u32 frames_128_to_255_octets; | |
305 | u32 frames_256_to_511_octets; | |
306 | u32 frames_512_to_1023_octets; | |
307 | u32 frames_1024_to_max_octets; | |
308 | u64 good_octets_sent; | |
309 | u32 good_frames_sent; | |
310 | u32 excessive_collision; | |
311 | u32 multicast_frames_sent; | |
312 | u32 broadcast_frames_sent; | |
313 | u32 unrec_mac_control_received; | |
314 | u32 fc_sent; | |
315 | u32 good_fc_received; | |
316 | u32 bad_fc_received; | |
317 | u32 undersize_received; | |
318 | u32 fragments_received; | |
319 | u32 oversize_received; | |
320 | u32 jabber_received; | |
321 | u32 mac_receive_error; | |
322 | u32 bad_crc_event; | |
323 | u32 collision; | |
324 | u32 late_collision; | |
325 | }; | |
326 | ||
8a578111 | 327 | struct rx_queue { |
64da80a2 LB |
328 | int index; |
329 | ||
8a578111 LB |
330 | int rx_ring_size; |
331 | ||
332 | int rx_desc_count; | |
333 | int rx_curr_desc; | |
334 | int rx_used_desc; | |
335 | ||
336 | struct rx_desc *rx_desc_area; | |
337 | dma_addr_t rx_desc_dma; | |
338 | int rx_desc_area_size; | |
339 | struct sk_buff **rx_skb; | |
8a578111 LB |
340 | }; |
341 | ||
13d64285 | 342 | struct tx_queue { |
3d6b35bc LB |
343 | int index; |
344 | ||
13d64285 | 345 | int tx_ring_size; |
fbd6a754 | 346 | |
13d64285 LB |
347 | int tx_desc_count; |
348 | int tx_curr_desc; | |
349 | int tx_used_desc; | |
fbd6a754 | 350 | |
5daffe94 | 351 | struct tx_desc *tx_desc_area; |
fbd6a754 LB |
352 | dma_addr_t tx_desc_dma; |
353 | int tx_desc_area_size; | |
99ab08e0 LB |
354 | |
355 | struct sk_buff_head tx_skb; | |
8fd89211 LB |
356 | |
357 | unsigned long tx_packets; | |
358 | unsigned long tx_bytes; | |
359 | unsigned long tx_dropped; | |
13d64285 LB |
360 | }; |
361 | ||
362 | struct mv643xx_eth_private { | |
363 | struct mv643xx_eth_shared_private *shared; | |
37a6084f | 364 | void __iomem *base; |
fc32b0e2 | 365 | int port_num; |
13d64285 | 366 | |
fc32b0e2 | 367 | struct net_device *dev; |
fbd6a754 | 368 | |
ed94493f | 369 | struct phy_device *phy; |
fbd6a754 | 370 | |
4ff3495a LB |
371 | struct timer_list mib_counters_timer; |
372 | spinlock_t mib_counters_lock; | |
fc32b0e2 | 373 | struct mib_counters mib_counters; |
4ff3495a | 374 | |
fc32b0e2 | 375 | struct work_struct tx_timeout_task; |
8a578111 | 376 | |
1fa38c58 LB |
377 | struct napi_struct napi; |
378 | u8 work_link; | |
379 | u8 work_tx; | |
380 | u8 work_tx_end; | |
381 | u8 work_rx; | |
382 | u8 work_rx_refill; | |
383 | u8 work_rx_oom; | |
384 | ||
2bcb4b0f LB |
385 | int skb_size; |
386 | struct sk_buff_head rx_recycle; | |
387 | ||
8a578111 LB |
388 | /* |
389 | * RX state. | |
390 | */ | |
e7d2f4db | 391 | int rx_ring_size; |
8a578111 LB |
392 | unsigned long rx_desc_sram_addr; |
393 | int rx_desc_sram_size; | |
f7981c1c | 394 | int rxq_count; |
2257e05c | 395 | struct timer_list rx_oom; |
64da80a2 | 396 | struct rx_queue rxq[8]; |
13d64285 LB |
397 | |
398 | /* | |
399 | * TX state. | |
400 | */ | |
e7d2f4db | 401 | int tx_ring_size; |
13d64285 LB |
402 | unsigned long tx_desc_sram_addr; |
403 | int tx_desc_sram_size; | |
f7981c1c | 404 | int txq_count; |
3d6b35bc | 405 | struct tx_queue txq[8]; |
fbd6a754 | 406 | }; |
1da177e4 | 407 | |
fbd6a754 | 408 | |
c9df406f | 409 | /* port register accessors **************************************************/ |
e5371493 | 410 | static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 411 | { |
cc9754b3 | 412 | return readl(mp->shared->base + offset); |
c9df406f | 413 | } |
fbd6a754 | 414 | |
37a6084f LB |
415 | static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) |
416 | { | |
417 | return readl(mp->base + offset); | |
418 | } | |
419 | ||
e5371493 | 420 | static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) |
c9df406f | 421 | { |
cc9754b3 | 422 | writel(data, mp->shared->base + offset); |
c9df406f | 423 | } |
fbd6a754 | 424 | |
37a6084f LB |
425 | static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) |
426 | { | |
427 | writel(data, mp->base + offset); | |
428 | } | |
429 | ||
fbd6a754 | 430 | |
c9df406f | 431 | /* rxq/txq helper functions *************************************************/ |
8a578111 | 432 | static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) |
c9df406f | 433 | { |
64da80a2 | 434 | return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); |
c9df406f | 435 | } |
fbd6a754 | 436 | |
13d64285 LB |
437 | static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) |
438 | { | |
3d6b35bc | 439 | return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); |
13d64285 LB |
440 | } |
441 | ||
8a578111 | 442 | static void rxq_enable(struct rx_queue *rxq) |
c9df406f | 443 | { |
8a578111 | 444 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
37a6084f | 445 | wrlp(mp, RXQ_COMMAND, 1 << rxq->index); |
8a578111 | 446 | } |
1da177e4 | 447 | |
8a578111 LB |
448 | static void rxq_disable(struct rx_queue *rxq) |
449 | { | |
450 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); | |
64da80a2 | 451 | u8 mask = 1 << rxq->index; |
1da177e4 | 452 | |
37a6084f LB |
453 | wrlp(mp, RXQ_COMMAND, mask << 8); |
454 | while (rdlp(mp, RXQ_COMMAND) & mask) | |
8a578111 | 455 | udelay(10); |
c9df406f LB |
456 | } |
457 | ||
6b368f68 LB |
458 | static void txq_reset_hw_ptr(struct tx_queue *txq) |
459 | { | |
460 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
6b368f68 LB |
461 | u32 addr; |
462 | ||
463 | addr = (u32)txq->tx_desc_dma; | |
464 | addr += txq->tx_curr_desc * sizeof(struct tx_desc); | |
37a6084f | 465 | wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); |
6b368f68 LB |
466 | } |
467 | ||
13d64285 | 468 | static void txq_enable(struct tx_queue *txq) |
1da177e4 | 469 | { |
13d64285 | 470 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
37a6084f | 471 | wrlp(mp, TXQ_COMMAND, 1 << txq->index); |
1da177e4 LT |
472 | } |
473 | ||
13d64285 | 474 | static void txq_disable(struct tx_queue *txq) |
1da177e4 | 475 | { |
13d64285 | 476 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
3d6b35bc | 477 | u8 mask = 1 << txq->index; |
c9df406f | 478 | |
37a6084f LB |
479 | wrlp(mp, TXQ_COMMAND, mask << 8); |
480 | while (rdlp(mp, TXQ_COMMAND) & mask) | |
13d64285 LB |
481 | udelay(10); |
482 | } | |
483 | ||
1fa38c58 | 484 | static void txq_maybe_wake(struct tx_queue *txq) |
13d64285 LB |
485 | { |
486 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
e5ef1de1 | 487 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
3d6b35bc | 488 | |
8fd89211 LB |
489 | if (netif_tx_queue_stopped(nq)) { |
490 | __netif_tx_lock(nq, smp_processor_id()); | |
491 | if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1) | |
492 | netif_tx_wake_queue(nq); | |
493 | __netif_tx_unlock(nq); | |
494 | } | |
1da177e4 LT |
495 | } |
496 | ||
c9df406f | 497 | |
1fa38c58 | 498 | /* rx napi ******************************************************************/ |
8a578111 | 499 | static int rxq_process(struct rx_queue *rxq, int budget) |
1da177e4 | 500 | { |
8a578111 LB |
501 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
502 | struct net_device_stats *stats = &mp->dev->stats; | |
503 | int rx; | |
1da177e4 | 504 | |
8a578111 | 505 | rx = 0; |
9e1f3772 | 506 | while (rx < budget && rxq->rx_desc_count) { |
fc32b0e2 | 507 | struct rx_desc *rx_desc; |
96587661 | 508 | unsigned int cmd_sts; |
fc32b0e2 | 509 | struct sk_buff *skb; |
6b8f90c2 | 510 | u16 byte_cnt; |
ff561eef | 511 | |
8a578111 | 512 | rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; |
1da177e4 | 513 | |
96587661 | 514 | cmd_sts = rx_desc->cmd_sts; |
2257e05c | 515 | if (cmd_sts & BUFFER_OWNED_BY_DMA) |
96587661 | 516 | break; |
96587661 | 517 | rmb(); |
1da177e4 | 518 | |
8a578111 LB |
519 | skb = rxq->rx_skb[rxq->rx_curr_desc]; |
520 | rxq->rx_skb[rxq->rx_curr_desc] = NULL; | |
ff561eef | 521 | |
9da78745 LB |
522 | rxq->rx_curr_desc++; |
523 | if (rxq->rx_curr_desc == rxq->rx_ring_size) | |
524 | rxq->rx_curr_desc = 0; | |
ff561eef | 525 | |
3a499481 | 526 | dma_unmap_single(NULL, rx_desc->buf_ptr, |
abe78717 | 527 | rx_desc->buf_size, DMA_FROM_DEVICE); |
8a578111 LB |
528 | rxq->rx_desc_count--; |
529 | rx++; | |
b1dd9ca1 | 530 | |
1fa38c58 LB |
531 | mp->work_rx_refill |= 1 << rxq->index; |
532 | ||
6b8f90c2 LB |
533 | byte_cnt = rx_desc->byte_cnt; |
534 | ||
468d09f8 DF |
535 | /* |
536 | * Update statistics. | |
fc32b0e2 LB |
537 | * |
538 | * Note that the descriptor byte count includes 2 dummy | |
539 | * bytes automatically inserted by the hardware at the | |
540 | * start of the packet (which we don't count), and a 4 | |
541 | * byte CRC at the end of the packet (which we do count). | |
468d09f8 | 542 | */ |
1da177e4 | 543 | stats->rx_packets++; |
6b8f90c2 | 544 | stats->rx_bytes += byte_cnt - 2; |
96587661 | 545 | |
1da177e4 | 546 | /* |
fc32b0e2 LB |
547 | * In case we received a packet without first / last bits |
548 | * on, or the error summary bit is set, the packet needs | |
549 | * to be dropped. | |
1da177e4 | 550 | */ |
f61e5547 LB |
551 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) |
552 | != (RX_FIRST_DESC | RX_LAST_DESC)) | |
553 | goto err; | |
554 | ||
555 | /* | |
556 | * The -4 is for the CRC in the trailer of the | |
557 | * received packet | |
558 | */ | |
559 | skb_put(skb, byte_cnt - 2 - 4); | |
560 | ||
561 | if (cmd_sts & LAYER_4_CHECKSUM_OK) | |
562 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
563 | skb->protocol = eth_type_trans(skb, mp->dev); | |
564 | netif_receive_skb(skb); | |
565 | ||
566 | continue; | |
567 | ||
568 | err: | |
569 | stats->rx_dropped++; | |
570 | ||
571 | if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != | |
572 | (RX_FIRST_DESC | RX_LAST_DESC)) { | |
573 | if (net_ratelimit()) | |
574 | dev_printk(KERN_ERR, &mp->dev->dev, | |
575 | "received packet spanning " | |
576 | "multiple descriptors\n"); | |
1da177e4 | 577 | } |
f61e5547 LB |
578 | |
579 | if (cmd_sts & ERROR_SUMMARY) | |
580 | stats->rx_errors++; | |
581 | ||
582 | dev_kfree_skb(skb); | |
1da177e4 | 583 | } |
fc32b0e2 | 584 | |
1fa38c58 LB |
585 | if (rx < budget) |
586 | mp->work_rx &= ~(1 << rxq->index); | |
587 | ||
8a578111 | 588 | return rx; |
1da177e4 LT |
589 | } |
590 | ||
1fa38c58 | 591 | static int rxq_refill(struct rx_queue *rxq, int budget) |
d0412d96 | 592 | { |
1fa38c58 | 593 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1fa38c58 | 594 | int refilled; |
8a578111 | 595 | |
1fa38c58 LB |
596 | refilled = 0; |
597 | while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { | |
598 | struct sk_buff *skb; | |
599 | int unaligned; | |
600 | int rx; | |
53771522 | 601 | struct rx_desc *rx_desc; |
d0412d96 | 602 | |
2bcb4b0f LB |
603 | skb = __skb_dequeue(&mp->rx_recycle); |
604 | if (skb == NULL) | |
605 | skb = dev_alloc_skb(mp->skb_size + | |
606 | dma_get_cache_alignment() - 1); | |
607 | ||
1fa38c58 LB |
608 | if (skb == NULL) { |
609 | mp->work_rx_oom |= 1 << rxq->index; | |
610 | goto oom; | |
611 | } | |
d0412d96 | 612 | |
1fa38c58 LB |
613 | unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1); |
614 | if (unaligned) | |
615 | skb_reserve(skb, dma_get_cache_alignment() - unaligned); | |
2257e05c | 616 | |
1fa38c58 LB |
617 | refilled++; |
618 | rxq->rx_desc_count++; | |
c9df406f | 619 | |
1fa38c58 LB |
620 | rx = rxq->rx_used_desc++; |
621 | if (rxq->rx_used_desc == rxq->rx_ring_size) | |
622 | rxq->rx_used_desc = 0; | |
2257e05c | 623 | |
53771522 LB |
624 | rx_desc = rxq->rx_desc_area + rx; |
625 | ||
626 | rx_desc->buf_ptr = dma_map_single(NULL, skb->data, | |
627 | mp->skb_size, DMA_FROM_DEVICE); | |
628 | rx_desc->buf_size = mp->skb_size; | |
1fa38c58 LB |
629 | rxq->rx_skb[rx] = skb; |
630 | wmb(); | |
53771522 | 631 | rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; |
1fa38c58 | 632 | wmb(); |
2257e05c | 633 | |
1fa38c58 LB |
634 | /* |
635 | * The hardware automatically prepends 2 bytes of | |
636 | * dummy data to each received packet, so that the | |
637 | * IP header ends up 16-byte aligned. | |
638 | */ | |
639 | skb_reserve(skb, 2); | |
640 | } | |
641 | ||
642 | if (refilled < budget) | |
643 | mp->work_rx_refill &= ~(1 << rxq->index); | |
644 | ||
645 | oom: | |
646 | return refilled; | |
d0412d96 JC |
647 | } |
648 | ||
c9df406f LB |
649 | |
650 | /* tx ***********************************************************************/ | |
c9df406f | 651 | static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) |
1da177e4 | 652 | { |
13d64285 | 653 | int frag; |
1da177e4 | 654 | |
c9df406f | 655 | for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { |
13d64285 LB |
656 | skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; |
657 | if (fragp->size <= 8 && fragp->page_offset & 7) | |
c9df406f | 658 | return 1; |
1da177e4 | 659 | } |
13d64285 | 660 | |
c9df406f LB |
661 | return 0; |
662 | } | |
7303fde8 | 663 | |
13d64285 | 664 | static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) |
c9df406f | 665 | { |
13d64285 | 666 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 667 | int frag; |
1da177e4 | 668 | |
13d64285 LB |
669 | for (frag = 0; frag < nr_frags; frag++) { |
670 | skb_frag_t *this_frag; | |
671 | int tx_index; | |
672 | struct tx_desc *desc; | |
673 | ||
674 | this_frag = &skb_shinfo(skb)->frags[frag]; | |
66823b92 LB |
675 | tx_index = txq->tx_curr_desc++; |
676 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
677 | txq->tx_curr_desc = 0; | |
13d64285 LB |
678 | desc = &txq->tx_desc_area[tx_index]; |
679 | ||
680 | /* | |
681 | * The last fragment will generate an interrupt | |
682 | * which will free the skb on TX completion. | |
683 | */ | |
684 | if (frag == nr_frags - 1) { | |
685 | desc->cmd_sts = BUFFER_OWNED_BY_DMA | | |
686 | ZERO_PADDING | TX_LAST_DESC | | |
687 | TX_ENABLE_INTERRUPT; | |
13d64285 LB |
688 | } else { |
689 | desc->cmd_sts = BUFFER_OWNED_BY_DMA; | |
13d64285 LB |
690 | } |
691 | ||
c9df406f LB |
692 | desc->l4i_chk = 0; |
693 | desc->byte_cnt = this_frag->size; | |
694 | desc->buf_ptr = dma_map_page(NULL, this_frag->page, | |
695 | this_frag->page_offset, | |
696 | this_frag->size, | |
697 | DMA_TO_DEVICE); | |
698 | } | |
1da177e4 LT |
699 | } |
700 | ||
c9df406f LB |
701 | static inline __be16 sum16_as_be(__sum16 sum) |
702 | { | |
703 | return (__force __be16)sum; | |
704 | } | |
1da177e4 | 705 | |
4df89bd5 | 706 | static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) |
1da177e4 | 707 | { |
8fa89bf5 | 708 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
13d64285 | 709 | int nr_frags = skb_shinfo(skb)->nr_frags; |
c9df406f | 710 | int tx_index; |
cc9754b3 | 711 | struct tx_desc *desc; |
c9df406f | 712 | u32 cmd_sts; |
4df89bd5 | 713 | u16 l4i_chk; |
c9df406f | 714 | int length; |
1da177e4 | 715 | |
cc9754b3 | 716 | cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; |
4df89bd5 | 717 | l4i_chk = 0; |
c9df406f LB |
718 | |
719 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
4df89bd5 | 720 | int tag_bytes; |
e32b6617 LB |
721 | |
722 | BUG_ON(skb->protocol != htons(ETH_P_IP) && | |
723 | skb->protocol != htons(ETH_P_8021Q)); | |
c9df406f | 724 | |
4df89bd5 LB |
725 | tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN; |
726 | if (unlikely(tag_bytes & ~12)) { | |
727 | if (skb_checksum_help(skb) == 0) | |
728 | goto no_csum; | |
729 | kfree_skb(skb); | |
730 | return 1; | |
731 | } | |
c9df406f | 732 | |
4df89bd5 | 733 | if (tag_bytes & 4) |
e32b6617 | 734 | cmd_sts |= MAC_HDR_EXTRA_4_BYTES; |
4df89bd5 | 735 | if (tag_bytes & 8) |
e32b6617 | 736 | cmd_sts |= MAC_HDR_EXTRA_8_BYTES; |
4df89bd5 LB |
737 | |
738 | cmd_sts |= GEN_TCP_UDP_CHECKSUM | | |
739 | GEN_IP_V4_CHECKSUM | | |
740 | ip_hdr(skb)->ihl << TX_IHL_SHIFT; | |
e32b6617 | 741 | |
c9df406f LB |
742 | switch (ip_hdr(skb)->protocol) { |
743 | case IPPROTO_UDP: | |
cc9754b3 | 744 | cmd_sts |= UDP_FRAME; |
4df89bd5 | 745 | l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); |
c9df406f LB |
746 | break; |
747 | case IPPROTO_TCP: | |
4df89bd5 | 748 | l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); |
c9df406f LB |
749 | break; |
750 | default: | |
751 | BUG(); | |
752 | } | |
753 | } else { | |
4df89bd5 | 754 | no_csum: |
c9df406f | 755 | /* Errata BTS #50, IHL must be 5 if no HW checksum */ |
cc9754b3 | 756 | cmd_sts |= 5 << TX_IHL_SHIFT; |
c9df406f LB |
757 | } |
758 | ||
66823b92 LB |
759 | tx_index = txq->tx_curr_desc++; |
760 | if (txq->tx_curr_desc == txq->tx_ring_size) | |
761 | txq->tx_curr_desc = 0; | |
4df89bd5 LB |
762 | desc = &txq->tx_desc_area[tx_index]; |
763 | ||
764 | if (nr_frags) { | |
765 | txq_submit_frag_skb(txq, skb); | |
766 | length = skb_headlen(skb); | |
767 | } else { | |
768 | cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; | |
769 | length = skb->len; | |
770 | } | |
771 | ||
772 | desc->l4i_chk = l4i_chk; | |
773 | desc->byte_cnt = length; | |
774 | desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); | |
775 | ||
99ab08e0 LB |
776 | __skb_queue_tail(&txq->tx_skb, skb); |
777 | ||
c9df406f LB |
778 | /* ensure all other descriptors are written before first cmd_sts */ |
779 | wmb(); | |
780 | desc->cmd_sts = cmd_sts; | |
781 | ||
1fa38c58 LB |
782 | /* clear TX_END status */ |
783 | mp->work_tx_end &= ~(1 << txq->index); | |
8fa89bf5 | 784 | |
c9df406f LB |
785 | /* ensure all descriptors are written before poking hardware */ |
786 | wmb(); | |
13d64285 | 787 | txq_enable(txq); |
c9df406f | 788 | |
13d64285 | 789 | txq->tx_desc_count += nr_frags + 1; |
4df89bd5 LB |
790 | |
791 | return 0; | |
1da177e4 | 792 | } |
1da177e4 | 793 | |
fc32b0e2 | 794 | static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 795 | { |
e5371493 | 796 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
e5ef1de1 | 797 | int queue; |
13d64285 | 798 | struct tx_queue *txq; |
e5ef1de1 | 799 | struct netdev_queue *nq; |
afdb57a2 | 800 | |
8fd89211 LB |
801 | queue = skb_get_queue_mapping(skb); |
802 | txq = mp->txq + queue; | |
803 | nq = netdev_get_tx_queue(dev, queue); | |
804 | ||
c9df406f | 805 | if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { |
8fd89211 | 806 | txq->tx_dropped++; |
fc32b0e2 LB |
807 | dev_printk(KERN_DEBUG, &dev->dev, |
808 | "failed to linearize skb with tiny " | |
809 | "unaligned fragment\n"); | |
c9df406f LB |
810 | return NETDEV_TX_BUSY; |
811 | } | |
812 | ||
17cd0a59 | 813 | if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { |
e5ef1de1 LB |
814 | if (net_ratelimit()) |
815 | dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n"); | |
3d6b35bc LB |
816 | kfree_skb(skb); |
817 | return NETDEV_TX_OK; | |
c9df406f LB |
818 | } |
819 | ||
4df89bd5 LB |
820 | if (!txq_submit_skb(txq, skb)) { |
821 | int entries_left; | |
822 | ||
823 | txq->tx_bytes += skb->len; | |
824 | txq->tx_packets++; | |
825 | dev->trans_start = jiffies; | |
c9df406f | 826 | |
4df89bd5 LB |
827 | entries_left = txq->tx_ring_size - txq->tx_desc_count; |
828 | if (entries_left < MAX_SKB_FRAGS + 1) | |
829 | netif_tx_stop_queue(nq); | |
830 | } | |
c9df406f | 831 | |
c9df406f | 832 | return NETDEV_TX_OK; |
1da177e4 LT |
833 | } |
834 | ||
c9df406f | 835 | |
1fa38c58 LB |
836 | /* tx napi ******************************************************************/ |
837 | static void txq_kick(struct tx_queue *txq) | |
838 | { | |
839 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 840 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
841 | u32 hw_desc_ptr; |
842 | u32 expected_ptr; | |
843 | ||
8fd89211 | 844 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 | 845 | |
37a6084f | 846 | if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) |
1fa38c58 LB |
847 | goto out; |
848 | ||
37a6084f | 849 | hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); |
1fa38c58 LB |
850 | expected_ptr = (u32)txq->tx_desc_dma + |
851 | txq->tx_curr_desc * sizeof(struct tx_desc); | |
852 | ||
853 | if (hw_desc_ptr != expected_ptr) | |
854 | txq_enable(txq); | |
855 | ||
856 | out: | |
8fd89211 | 857 | __netif_tx_unlock(nq); |
1fa38c58 LB |
858 | |
859 | mp->work_tx_end &= ~(1 << txq->index); | |
860 | } | |
861 | ||
862 | static int txq_reclaim(struct tx_queue *txq, int budget, int force) | |
863 | { | |
864 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
8fd89211 | 865 | struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); |
1fa38c58 LB |
866 | int reclaimed; |
867 | ||
8fd89211 | 868 | __netif_tx_lock(nq, smp_processor_id()); |
1fa38c58 LB |
869 | |
870 | reclaimed = 0; | |
871 | while (reclaimed < budget && txq->tx_desc_count > 0) { | |
872 | int tx_index; | |
873 | struct tx_desc *desc; | |
874 | u32 cmd_sts; | |
875 | struct sk_buff *skb; | |
1fa38c58 LB |
876 | |
877 | tx_index = txq->tx_used_desc; | |
878 | desc = &txq->tx_desc_area[tx_index]; | |
879 | cmd_sts = desc->cmd_sts; | |
880 | ||
881 | if (cmd_sts & BUFFER_OWNED_BY_DMA) { | |
882 | if (!force) | |
883 | break; | |
884 | desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; | |
885 | } | |
886 | ||
887 | txq->tx_used_desc = tx_index + 1; | |
888 | if (txq->tx_used_desc == txq->tx_ring_size) | |
889 | txq->tx_used_desc = 0; | |
890 | ||
891 | reclaimed++; | |
892 | txq->tx_desc_count--; | |
893 | ||
99ab08e0 LB |
894 | skb = NULL; |
895 | if (cmd_sts & TX_LAST_DESC) | |
896 | skb = __skb_dequeue(&txq->tx_skb); | |
1fa38c58 LB |
897 | |
898 | if (cmd_sts & ERROR_SUMMARY) { | |
899 | dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n"); | |
900 | mp->dev->stats.tx_errors++; | |
901 | } | |
902 | ||
a418950c LB |
903 | if (cmd_sts & TX_FIRST_DESC) { |
904 | dma_unmap_single(NULL, desc->buf_ptr, | |
905 | desc->byte_cnt, DMA_TO_DEVICE); | |
906 | } else { | |
907 | dma_unmap_page(NULL, desc->buf_ptr, | |
908 | desc->byte_cnt, DMA_TO_DEVICE); | |
909 | } | |
1fa38c58 | 910 | |
2bcb4b0f LB |
911 | if (skb != NULL) { |
912 | if (skb_queue_len(&mp->rx_recycle) < | |
e7d2f4db | 913 | mp->rx_ring_size && |
11b4aa03 LB |
914 | skb_recycle_check(skb, mp->skb_size + |
915 | dma_get_cache_alignment() - 1)) | |
2bcb4b0f LB |
916 | __skb_queue_head(&mp->rx_recycle, skb); |
917 | else | |
918 | dev_kfree_skb(skb); | |
919 | } | |
1fa38c58 LB |
920 | } |
921 | ||
8fd89211 LB |
922 | __netif_tx_unlock(nq); |
923 | ||
1fa38c58 LB |
924 | if (reclaimed < budget) |
925 | mp->work_tx &= ~(1 << txq->index); | |
926 | ||
1fa38c58 LB |
927 | return reclaimed; |
928 | } | |
929 | ||
930 | ||
89df5fdc LB |
931 | /* tx rate control **********************************************************/ |
932 | /* | |
933 | * Set total maximum TX rate (shared by all TX queues for this port) | |
934 | * to 'rate' bits per second, with a maximum burst of 'burst' bytes. | |
935 | */ | |
936 | static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) | |
937 | { | |
938 | int token_rate; | |
939 | int mtu; | |
940 | int bucket_size; | |
941 | ||
942 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
943 | if (token_rate > 1023) | |
944 | token_rate = 1023; | |
945 | ||
946 | mtu = (mp->dev->mtu + 255) >> 8; | |
947 | if (mtu > 63) | |
948 | mtu = 63; | |
949 | ||
950 | bucket_size = (burst + 255) >> 8; | |
951 | if (bucket_size > 65535) | |
952 | bucket_size = 65535; | |
953 | ||
457b1d5a LB |
954 | switch (mp->shared->tx_bw_control) { |
955 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f LB |
956 | wrlp(mp, TX_BW_RATE, token_rate); |
957 | wrlp(mp, TX_BW_MTU, mtu); | |
958 | wrlp(mp, TX_BW_BURST, bucket_size); | |
457b1d5a LB |
959 | break; |
960 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f LB |
961 | wrlp(mp, TX_BW_RATE_MOVED, token_rate); |
962 | wrlp(mp, TX_BW_MTU_MOVED, mtu); | |
963 | wrlp(mp, TX_BW_BURST_MOVED, bucket_size); | |
457b1d5a | 964 | break; |
1e881592 | 965 | } |
89df5fdc LB |
966 | } |
967 | ||
968 | static void txq_set_rate(struct tx_queue *txq, int rate, int burst) | |
969 | { | |
970 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
971 | int token_rate; | |
972 | int bucket_size; | |
973 | ||
974 | token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000); | |
975 | if (token_rate > 1023) | |
976 | token_rate = 1023; | |
977 | ||
978 | bucket_size = (burst + 255) >> 8; | |
979 | if (bucket_size > 65535) | |
980 | bucket_size = 65535; | |
981 | ||
37a6084f LB |
982 | wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); |
983 | wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); | |
89df5fdc LB |
984 | } |
985 | ||
986 | static void txq_set_fixed_prio_mode(struct tx_queue *txq) | |
987 | { | |
988 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
989 | int off; | |
990 | u32 val; | |
991 | ||
992 | /* | |
993 | * Turn on fixed priority mode. | |
994 | */ | |
457b1d5a LB |
995 | off = 0; |
996 | switch (mp->shared->tx_bw_control) { | |
997 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f | 998 | off = TXQ_FIX_PRIO_CONF; |
457b1d5a LB |
999 | break; |
1000 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f | 1001 | off = TXQ_FIX_PRIO_CONF_MOVED; |
457b1d5a LB |
1002 | break; |
1003 | } | |
89df5fdc | 1004 | |
457b1d5a | 1005 | if (off) { |
37a6084f | 1006 | val = rdlp(mp, off); |
457b1d5a | 1007 | val |= 1 << txq->index; |
37a6084f | 1008 | wrlp(mp, off, val); |
457b1d5a | 1009 | } |
89df5fdc LB |
1010 | } |
1011 | ||
1012 | static void txq_set_wrr(struct tx_queue *txq, int weight) | |
1013 | { | |
1014 | struct mv643xx_eth_private *mp = txq_to_mp(txq); | |
1015 | int off; | |
1016 | u32 val; | |
1017 | ||
1018 | /* | |
1019 | * Turn off fixed priority mode. | |
1020 | */ | |
457b1d5a LB |
1021 | off = 0; |
1022 | switch (mp->shared->tx_bw_control) { | |
1023 | case TX_BW_CONTROL_OLD_LAYOUT: | |
37a6084f | 1024 | off = TXQ_FIX_PRIO_CONF; |
457b1d5a LB |
1025 | break; |
1026 | case TX_BW_CONTROL_NEW_LAYOUT: | |
37a6084f | 1027 | off = TXQ_FIX_PRIO_CONF_MOVED; |
457b1d5a LB |
1028 | break; |
1029 | } | |
89df5fdc | 1030 | |
457b1d5a | 1031 | if (off) { |
37a6084f | 1032 | val = rdlp(mp, off); |
457b1d5a | 1033 | val &= ~(1 << txq->index); |
37a6084f | 1034 | wrlp(mp, off, val); |
89df5fdc | 1035 | |
457b1d5a LB |
1036 | /* |
1037 | * Configure WRR weight for this queue. | |
1038 | */ | |
89df5fdc | 1039 | |
37a6084f | 1040 | val = rdlp(mp, off); |
457b1d5a | 1041 | val = (val & ~0xff) | (weight & 0xff); |
37a6084f | 1042 | wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val); |
457b1d5a | 1043 | } |
89df5fdc LB |
1044 | } |
1045 | ||
1046 | ||
c9df406f | 1047 | /* mii management interface *************************************************/ |
45c5d3bc LB |
1048 | static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id) |
1049 | { | |
1050 | struct mv643xx_eth_shared_private *msp = dev_id; | |
1051 | ||
1052 | if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) { | |
1053 | writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE); | |
1054 | wake_up(&msp->smi_busy_wait); | |
1055 | return IRQ_HANDLED; | |
1056 | } | |
1057 | ||
1058 | return IRQ_NONE; | |
1059 | } | |
c9df406f | 1060 | |
45c5d3bc | 1061 | static int smi_is_done(struct mv643xx_eth_shared_private *msp) |
1da177e4 | 1062 | { |
45c5d3bc LB |
1063 | return !(readl(msp->base + SMI_REG) & SMI_BUSY); |
1064 | } | |
1da177e4 | 1065 | |
45c5d3bc LB |
1066 | static int smi_wait_ready(struct mv643xx_eth_shared_private *msp) |
1067 | { | |
1068 | if (msp->err_interrupt == NO_IRQ) { | |
1069 | int i; | |
c9df406f | 1070 | |
45c5d3bc LB |
1071 | for (i = 0; !smi_is_done(msp); i++) { |
1072 | if (i == 10) | |
1073 | return -ETIMEDOUT; | |
1074 | msleep(10); | |
c9df406f | 1075 | } |
45c5d3bc LB |
1076 | |
1077 | return 0; | |
1078 | } | |
1079 | ||
ee04448d LB |
1080 | if (!smi_is_done(msp)) { |
1081 | wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp), | |
1082 | msecs_to_jiffies(100)); | |
1083 | if (!smi_is_done(msp)) | |
1084 | return -ETIMEDOUT; | |
1085 | } | |
45c5d3bc LB |
1086 | |
1087 | return 0; | |
1088 | } | |
1089 | ||
ed94493f | 1090 | static int smi_bus_read(struct mii_bus *bus, int addr, int reg) |
45c5d3bc | 1091 | { |
ed94493f | 1092 | struct mv643xx_eth_shared_private *msp = bus->priv; |
45c5d3bc LB |
1093 | void __iomem *smi_reg = msp->base + SMI_REG; |
1094 | int ret; | |
1095 | ||
45c5d3bc | 1096 | if (smi_wait_ready(msp)) { |
10a9948d | 1097 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f | 1098 | return -ETIMEDOUT; |
1da177e4 LT |
1099 | } |
1100 | ||
fc32b0e2 | 1101 | writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg); |
1da177e4 | 1102 | |
45c5d3bc | 1103 | if (smi_wait_ready(msp)) { |
10a9948d | 1104 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f | 1105 | return -ETIMEDOUT; |
45c5d3bc LB |
1106 | } |
1107 | ||
1108 | ret = readl(smi_reg); | |
1109 | if (!(ret & SMI_READ_VALID)) { | |
10a9948d | 1110 | printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n"); |
ed94493f | 1111 | return -ENODEV; |
c9df406f LB |
1112 | } |
1113 | ||
ed94493f | 1114 | return ret & 0xffff; |
1da177e4 LT |
1115 | } |
1116 | ||
ed94493f | 1117 | static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val) |
1da177e4 | 1118 | { |
ed94493f | 1119 | struct mv643xx_eth_shared_private *msp = bus->priv; |
45c5d3bc | 1120 | void __iomem *smi_reg = msp->base + SMI_REG; |
1da177e4 | 1121 | |
45c5d3bc | 1122 | if (smi_wait_ready(msp)) { |
10a9948d | 1123 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
45c5d3bc | 1124 | return -ETIMEDOUT; |
1da177e4 LT |
1125 | } |
1126 | ||
fc32b0e2 | 1127 | writel(SMI_OPCODE_WRITE | (reg << 21) | |
ed94493f | 1128 | (addr << 16) | (val & 0xffff), smi_reg); |
45c5d3bc | 1129 | |
ed94493f | 1130 | if (smi_wait_ready(msp)) { |
10a9948d | 1131 | printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n"); |
ed94493f LB |
1132 | return -ETIMEDOUT; |
1133 | } | |
45c5d3bc LB |
1134 | |
1135 | return 0; | |
c9df406f | 1136 | } |
1da177e4 | 1137 | |
c9df406f | 1138 | |
8fd89211 LB |
1139 | /* statistics ***************************************************************/ |
1140 | static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) | |
1141 | { | |
1142 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1143 | struct net_device_stats *stats = &dev->stats; | |
1144 | unsigned long tx_packets = 0; | |
1145 | unsigned long tx_bytes = 0; | |
1146 | unsigned long tx_dropped = 0; | |
1147 | int i; | |
1148 | ||
1149 | for (i = 0; i < mp->txq_count; i++) { | |
1150 | struct tx_queue *txq = mp->txq + i; | |
1151 | ||
1152 | tx_packets += txq->tx_packets; | |
1153 | tx_bytes += txq->tx_bytes; | |
1154 | tx_dropped += txq->tx_dropped; | |
1155 | } | |
1156 | ||
1157 | stats->tx_packets = tx_packets; | |
1158 | stats->tx_bytes = tx_bytes; | |
1159 | stats->tx_dropped = tx_dropped; | |
1160 | ||
1161 | return stats; | |
1162 | } | |
1163 | ||
fc32b0e2 | 1164 | static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) |
c9df406f | 1165 | { |
fc32b0e2 | 1166 | return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); |
1da177e4 LT |
1167 | } |
1168 | ||
fc32b0e2 | 1169 | static void mib_counters_clear(struct mv643xx_eth_private *mp) |
d0412d96 | 1170 | { |
fc32b0e2 LB |
1171 | int i; |
1172 | ||
1173 | for (i = 0; i < 0x80; i += 4) | |
1174 | mib_read(mp, i); | |
c9df406f | 1175 | } |
d0412d96 | 1176 | |
fc32b0e2 | 1177 | static void mib_counters_update(struct mv643xx_eth_private *mp) |
c9df406f | 1178 | { |
e5371493 | 1179 | struct mib_counters *p = &mp->mib_counters; |
4b8e3655 | 1180 | |
4ff3495a | 1181 | spin_lock(&mp->mib_counters_lock); |
fc32b0e2 LB |
1182 | p->good_octets_received += mib_read(mp, 0x00); |
1183 | p->good_octets_received += (u64)mib_read(mp, 0x04) << 32; | |
1184 | p->bad_octets_received += mib_read(mp, 0x08); | |
1185 | p->internal_mac_transmit_err += mib_read(mp, 0x0c); | |
1186 | p->good_frames_received += mib_read(mp, 0x10); | |
1187 | p->bad_frames_received += mib_read(mp, 0x14); | |
1188 | p->broadcast_frames_received += mib_read(mp, 0x18); | |
1189 | p->multicast_frames_received += mib_read(mp, 0x1c); | |
1190 | p->frames_64_octets += mib_read(mp, 0x20); | |
1191 | p->frames_65_to_127_octets += mib_read(mp, 0x24); | |
1192 | p->frames_128_to_255_octets += mib_read(mp, 0x28); | |
1193 | p->frames_256_to_511_octets += mib_read(mp, 0x2c); | |
1194 | p->frames_512_to_1023_octets += mib_read(mp, 0x30); | |
1195 | p->frames_1024_to_max_octets += mib_read(mp, 0x34); | |
1196 | p->good_octets_sent += mib_read(mp, 0x38); | |
1197 | p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32; | |
1198 | p->good_frames_sent += mib_read(mp, 0x40); | |
1199 | p->excessive_collision += mib_read(mp, 0x44); | |
1200 | p->multicast_frames_sent += mib_read(mp, 0x48); | |
1201 | p->broadcast_frames_sent += mib_read(mp, 0x4c); | |
1202 | p->unrec_mac_control_received += mib_read(mp, 0x50); | |
1203 | p->fc_sent += mib_read(mp, 0x54); | |
1204 | p->good_fc_received += mib_read(mp, 0x58); | |
1205 | p->bad_fc_received += mib_read(mp, 0x5c); | |
1206 | p->undersize_received += mib_read(mp, 0x60); | |
1207 | p->fragments_received += mib_read(mp, 0x64); | |
1208 | p->oversize_received += mib_read(mp, 0x68); | |
1209 | p->jabber_received += mib_read(mp, 0x6c); | |
1210 | p->mac_receive_error += mib_read(mp, 0x70); | |
1211 | p->bad_crc_event += mib_read(mp, 0x74); | |
1212 | p->collision += mib_read(mp, 0x78); | |
1213 | p->late_collision += mib_read(mp, 0x7c); | |
4ff3495a LB |
1214 | spin_unlock(&mp->mib_counters_lock); |
1215 | ||
1216 | mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); | |
1217 | } | |
1218 | ||
1219 | static void mib_counters_timer_wrapper(unsigned long _mp) | |
1220 | { | |
1221 | struct mv643xx_eth_private *mp = (void *)_mp; | |
1222 | ||
1223 | mib_counters_update(mp); | |
d0412d96 JC |
1224 | } |
1225 | ||
c9df406f | 1226 | |
3e508034 LB |
1227 | /* interrupt coalescing *****************************************************/ |
1228 | /* | |
1229 | * Hardware coalescing parameters are set in units of 64 t_clk | |
1230 | * cycles. I.e.: | |
1231 | * | |
1232 | * coal_delay_in_usec = 64000000 * register_value / t_clk_rate | |
1233 | * | |
1234 | * register_value = coal_delay_in_usec * t_clk_rate / 64000000 | |
1235 | * | |
1236 | * In the ->set*() methods, we round the computed register value | |
1237 | * to the nearest integer. | |
1238 | */ | |
1239 | static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) | |
1240 | { | |
1241 | u32 val = rdlp(mp, SDMA_CONFIG); | |
1242 | u64 temp; | |
1243 | ||
1244 | if (mp->shared->extended_rx_coal_limit) | |
1245 | temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); | |
1246 | else | |
1247 | temp = (val & 0x003fff00) >> 8; | |
1248 | ||
1249 | temp *= 64000000; | |
1250 | do_div(temp, mp->shared->t_clk); | |
1251 | ||
1252 | return (unsigned int)temp; | |
1253 | } | |
1254 | ||
1255 | static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1256 | { | |
1257 | u64 temp; | |
1258 | u32 val; | |
1259 | ||
1260 | temp = (u64)usec * mp->shared->t_clk; | |
1261 | temp += 31999999; | |
1262 | do_div(temp, 64000000); | |
1263 | ||
1264 | val = rdlp(mp, SDMA_CONFIG); | |
1265 | if (mp->shared->extended_rx_coal_limit) { | |
1266 | if (temp > 0xffff) | |
1267 | temp = 0xffff; | |
1268 | val &= ~0x023fff80; | |
1269 | val |= (temp & 0x8000) << 10; | |
1270 | val |= (temp & 0x7fff) << 7; | |
1271 | } else { | |
1272 | if (temp > 0x3fff) | |
1273 | temp = 0x3fff; | |
1274 | val &= ~0x003fff00; | |
1275 | val |= (temp & 0x3fff) << 8; | |
1276 | } | |
1277 | wrlp(mp, SDMA_CONFIG, val); | |
1278 | } | |
1279 | ||
1280 | static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) | |
1281 | { | |
1282 | u64 temp; | |
1283 | ||
1284 | temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; | |
1285 | temp *= 64000000; | |
1286 | do_div(temp, mp->shared->t_clk); | |
1287 | ||
1288 | return (unsigned int)temp; | |
1289 | } | |
1290 | ||
1291 | static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) | |
1292 | { | |
1293 | u64 temp; | |
1294 | ||
1295 | temp = (u64)usec * mp->shared->t_clk; | |
1296 | temp += 31999999; | |
1297 | do_div(temp, 64000000); | |
1298 | ||
1299 | if (temp > 0x3fff) | |
1300 | temp = 0x3fff; | |
1301 | ||
1302 | wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); | |
1303 | } | |
1304 | ||
1305 | ||
c9df406f | 1306 | /* ethtool ******************************************************************/ |
e5371493 | 1307 | struct mv643xx_eth_stats { |
c9df406f LB |
1308 | char stat_string[ETH_GSTRING_LEN]; |
1309 | int sizeof_stat; | |
16820054 LB |
1310 | int netdev_off; |
1311 | int mp_off; | |
c9df406f LB |
1312 | }; |
1313 | ||
16820054 LB |
1314 | #define SSTAT(m) \ |
1315 | { #m, FIELD_SIZEOF(struct net_device_stats, m), \ | |
1316 | offsetof(struct net_device, stats.m), -1 } | |
1317 | ||
1318 | #define MIBSTAT(m) \ | |
1319 | { #m, FIELD_SIZEOF(struct mib_counters, m), \ | |
1320 | -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } | |
1321 | ||
1322 | static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { | |
1323 | SSTAT(rx_packets), | |
1324 | SSTAT(tx_packets), | |
1325 | SSTAT(rx_bytes), | |
1326 | SSTAT(tx_bytes), | |
1327 | SSTAT(rx_errors), | |
1328 | SSTAT(tx_errors), | |
1329 | SSTAT(rx_dropped), | |
1330 | SSTAT(tx_dropped), | |
1331 | MIBSTAT(good_octets_received), | |
1332 | MIBSTAT(bad_octets_received), | |
1333 | MIBSTAT(internal_mac_transmit_err), | |
1334 | MIBSTAT(good_frames_received), | |
1335 | MIBSTAT(bad_frames_received), | |
1336 | MIBSTAT(broadcast_frames_received), | |
1337 | MIBSTAT(multicast_frames_received), | |
1338 | MIBSTAT(frames_64_octets), | |
1339 | MIBSTAT(frames_65_to_127_octets), | |
1340 | MIBSTAT(frames_128_to_255_octets), | |
1341 | MIBSTAT(frames_256_to_511_octets), | |
1342 | MIBSTAT(frames_512_to_1023_octets), | |
1343 | MIBSTAT(frames_1024_to_max_octets), | |
1344 | MIBSTAT(good_octets_sent), | |
1345 | MIBSTAT(good_frames_sent), | |
1346 | MIBSTAT(excessive_collision), | |
1347 | MIBSTAT(multicast_frames_sent), | |
1348 | MIBSTAT(broadcast_frames_sent), | |
1349 | MIBSTAT(unrec_mac_control_received), | |
1350 | MIBSTAT(fc_sent), | |
1351 | MIBSTAT(good_fc_received), | |
1352 | MIBSTAT(bad_fc_received), | |
1353 | MIBSTAT(undersize_received), | |
1354 | MIBSTAT(fragments_received), | |
1355 | MIBSTAT(oversize_received), | |
1356 | MIBSTAT(jabber_received), | |
1357 | MIBSTAT(mac_receive_error), | |
1358 | MIBSTAT(bad_crc_event), | |
1359 | MIBSTAT(collision), | |
1360 | MIBSTAT(late_collision), | |
c9df406f LB |
1361 | }; |
1362 | ||
10a9948d | 1363 | static int |
6bdf576e LB |
1364 | mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp, |
1365 | struct ethtool_cmd *cmd) | |
d0412d96 | 1366 | { |
d0412d96 JC |
1367 | int err; |
1368 | ||
ed94493f LB |
1369 | err = phy_read_status(mp->phy); |
1370 | if (err == 0) | |
1371 | err = phy_ethtool_gset(mp->phy, cmd); | |
d0412d96 | 1372 | |
fc32b0e2 LB |
1373 | /* |
1374 | * The MAC does not support 1000baseT_Half. | |
1375 | */ | |
d0412d96 JC |
1376 | cmd->supported &= ~SUPPORTED_1000baseT_Half; |
1377 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1378 | ||
1379 | return err; | |
1380 | } | |
1381 | ||
10a9948d | 1382 | static int |
6bdf576e | 1383 | mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp, |
10a9948d | 1384 | struct ethtool_cmd *cmd) |
bedfe324 | 1385 | { |
81600eea LB |
1386 | u32 port_status; |
1387 | ||
37a6084f | 1388 | port_status = rdlp(mp, PORT_STATUS); |
81600eea | 1389 | |
bedfe324 LB |
1390 | cmd->supported = SUPPORTED_MII; |
1391 | cmd->advertising = ADVERTISED_MII; | |
81600eea LB |
1392 | switch (port_status & PORT_SPEED_MASK) { |
1393 | case PORT_SPEED_10: | |
1394 | cmd->speed = SPEED_10; | |
1395 | break; | |
1396 | case PORT_SPEED_100: | |
1397 | cmd->speed = SPEED_100; | |
1398 | break; | |
1399 | case PORT_SPEED_1000: | |
1400 | cmd->speed = SPEED_1000; | |
1401 | break; | |
1402 | default: | |
1403 | cmd->speed = -1; | |
1404 | break; | |
1405 | } | |
1406 | cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; | |
bedfe324 LB |
1407 | cmd->port = PORT_MII; |
1408 | cmd->phy_address = 0; | |
1409 | cmd->transceiver = XCVR_INTERNAL; | |
1410 | cmd->autoneg = AUTONEG_DISABLE; | |
1411 | cmd->maxtxpkt = 1; | |
1412 | cmd->maxrxpkt = 1; | |
1413 | ||
1414 | return 0; | |
1415 | } | |
1416 | ||
6bdf576e LB |
1417 | static int |
1418 | mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1419 | { | |
1420 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1421 | ||
1422 | if (mp->phy != NULL) | |
1423 | return mv643xx_eth_get_settings_phy(mp, cmd); | |
1424 | else | |
1425 | return mv643xx_eth_get_settings_phyless(mp, cmd); | |
1426 | } | |
1427 | ||
10a9948d LB |
1428 | static int |
1429 | mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1da177e4 | 1430 | { |
e5371493 | 1431 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
ab4384a6 | 1432 | |
6bdf576e LB |
1433 | if (mp->phy == NULL) |
1434 | return -EINVAL; | |
1435 | ||
fc32b0e2 LB |
1436 | /* |
1437 | * The MAC does not support 1000baseT_Half. | |
1438 | */ | |
1439 | cmd->advertising &= ~ADVERTISED_1000baseT_Half; | |
1440 | ||
ed94493f | 1441 | return phy_ethtool_sset(mp->phy, cmd); |
c9df406f | 1442 | } |
1da177e4 | 1443 | |
fc32b0e2 LB |
1444 | static void mv643xx_eth_get_drvinfo(struct net_device *dev, |
1445 | struct ethtool_drvinfo *drvinfo) | |
c9df406f | 1446 | { |
e5371493 LB |
1447 | strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32); |
1448 | strncpy(drvinfo->version, mv643xx_eth_driver_version, 32); | |
c9df406f | 1449 | strncpy(drvinfo->fw_version, "N/A", 32); |
fc32b0e2 | 1450 | strncpy(drvinfo->bus_info, "platform", 32); |
16820054 | 1451 | drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); |
c9df406f | 1452 | } |
1da177e4 | 1453 | |
fc32b0e2 | 1454 | static int mv643xx_eth_nway_reset(struct net_device *dev) |
c9df406f | 1455 | { |
e5371493 | 1456 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 1457 | |
6bdf576e LB |
1458 | if (mp->phy == NULL) |
1459 | return -EINVAL; | |
1da177e4 | 1460 | |
6bdf576e | 1461 | return genphy_restart_aneg(mp->phy); |
bedfe324 LB |
1462 | } |
1463 | ||
c9df406f LB |
1464 | static u32 mv643xx_eth_get_link(struct net_device *dev) |
1465 | { | |
ed94493f | 1466 | return !!netif_carrier_ok(dev); |
bedfe324 LB |
1467 | } |
1468 | ||
3e508034 LB |
1469 | static int |
1470 | mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1471 | { | |
1472 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1473 | ||
1474 | ec->rx_coalesce_usecs = get_rx_coal(mp); | |
1475 | ec->tx_coalesce_usecs = get_tx_coal(mp); | |
1476 | ||
1477 | return 0; | |
1478 | } | |
1479 | ||
1480 | static int | |
1481 | mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | |
1482 | { | |
1483 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1484 | ||
1485 | set_rx_coal(mp, ec->rx_coalesce_usecs); | |
1486 | set_tx_coal(mp, ec->tx_coalesce_usecs); | |
1487 | ||
1488 | return 0; | |
1489 | } | |
1490 | ||
e7d2f4db LB |
1491 | static void |
1492 | mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1493 | { | |
1494 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1495 | ||
1496 | er->rx_max_pending = 4096; | |
1497 | er->tx_max_pending = 4096; | |
1498 | er->rx_mini_max_pending = 0; | |
1499 | er->rx_jumbo_max_pending = 0; | |
1500 | ||
1501 | er->rx_pending = mp->rx_ring_size; | |
1502 | er->tx_pending = mp->tx_ring_size; | |
1503 | er->rx_mini_pending = 0; | |
1504 | er->rx_jumbo_pending = 0; | |
1505 | } | |
1506 | ||
1507 | static int | |
1508 | mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) | |
1509 | { | |
1510 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1511 | ||
1512 | if (er->rx_mini_pending || er->rx_jumbo_pending) | |
1513 | return -EINVAL; | |
1514 | ||
1515 | mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; | |
1516 | mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096; | |
1517 | ||
1518 | if (netif_running(dev)) { | |
1519 | mv643xx_eth_stop(dev); | |
1520 | if (mv643xx_eth_open(dev)) { | |
1521 | dev_printk(KERN_ERR, &dev->dev, | |
1522 | "fatal error on re-opening device after " | |
1523 | "ring param change\n"); | |
1524 | return -ENOMEM; | |
1525 | } | |
1526 | } | |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
d888b373 LB |
1531 | static u32 |
1532 | mv643xx_eth_get_rx_csum(struct net_device *dev) | |
1533 | { | |
1534 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1535 | ||
1536 | return !!(rdlp(mp, PORT_CONFIG) & 0x02000000); | |
1537 | } | |
1538 | ||
1539 | static int | |
1540 | mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum) | |
1541 | { | |
1542 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
1543 | ||
1544 | wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); | |
1545 | ||
1546 | return 0; | |
1547 | } | |
1548 | ||
fc32b0e2 LB |
1549 | static void mv643xx_eth_get_strings(struct net_device *dev, |
1550 | uint32_t stringset, uint8_t *data) | |
c9df406f LB |
1551 | { |
1552 | int i; | |
1da177e4 | 1553 | |
fc32b0e2 LB |
1554 | if (stringset == ETH_SS_STATS) { |
1555 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { | |
c9df406f | 1556 | memcpy(data + i * ETH_GSTRING_LEN, |
16820054 | 1557 | mv643xx_eth_stats[i].stat_string, |
e5371493 | 1558 | ETH_GSTRING_LEN); |
c9df406f | 1559 | } |
c9df406f LB |
1560 | } |
1561 | } | |
1da177e4 | 1562 | |
fc32b0e2 LB |
1563 | static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, |
1564 | struct ethtool_stats *stats, | |
1565 | uint64_t *data) | |
c9df406f | 1566 | { |
b9873841 | 1567 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 1568 | int i; |
1da177e4 | 1569 | |
8fd89211 | 1570 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 1571 | mib_counters_update(mp); |
1da177e4 | 1572 | |
16820054 LB |
1573 | for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { |
1574 | const struct mv643xx_eth_stats *stat; | |
1575 | void *p; | |
1576 | ||
1577 | stat = mv643xx_eth_stats + i; | |
1578 | ||
1579 | if (stat->netdev_off >= 0) | |
1580 | p = ((void *)mp->dev) + stat->netdev_off; | |
1581 | else | |
1582 | p = ((void *)mp) + stat->mp_off; | |
1583 | ||
1584 | data[i] = (stat->sizeof_stat == 8) ? | |
1585 | *(uint64_t *)p : *(uint32_t *)p; | |
1da177e4 | 1586 | } |
c9df406f | 1587 | } |
1da177e4 | 1588 | |
fc32b0e2 | 1589 | static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) |
c9df406f | 1590 | { |
fc32b0e2 | 1591 | if (sset == ETH_SS_STATS) |
16820054 | 1592 | return ARRAY_SIZE(mv643xx_eth_stats); |
fc32b0e2 LB |
1593 | |
1594 | return -EOPNOTSUPP; | |
c9df406f | 1595 | } |
1da177e4 | 1596 | |
e5371493 | 1597 | static const struct ethtool_ops mv643xx_eth_ethtool_ops = { |
fc32b0e2 LB |
1598 | .get_settings = mv643xx_eth_get_settings, |
1599 | .set_settings = mv643xx_eth_set_settings, | |
1600 | .get_drvinfo = mv643xx_eth_get_drvinfo, | |
1601 | .nway_reset = mv643xx_eth_nway_reset, | |
1602 | .get_link = mv643xx_eth_get_link, | |
3e508034 LB |
1603 | .get_coalesce = mv643xx_eth_get_coalesce, |
1604 | .set_coalesce = mv643xx_eth_set_coalesce, | |
e7d2f4db LB |
1605 | .get_ringparam = mv643xx_eth_get_ringparam, |
1606 | .set_ringparam = mv643xx_eth_set_ringparam, | |
d888b373 LB |
1607 | .get_rx_csum = mv643xx_eth_get_rx_csum, |
1608 | .set_rx_csum = mv643xx_eth_set_rx_csum, | |
b8df184f | 1609 | .set_tx_csum = ethtool_op_set_tx_csum, |
c9df406f | 1610 | .set_sg = ethtool_op_set_sg, |
fc32b0e2 LB |
1611 | .get_strings = mv643xx_eth_get_strings, |
1612 | .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, | |
e5371493 | 1613 | .get_sset_count = mv643xx_eth_get_sset_count, |
c9df406f | 1614 | }; |
1da177e4 | 1615 | |
bea3348e | 1616 | |
c9df406f | 1617 | /* address handling *********************************************************/ |
5daffe94 | 1618 | static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1619 | { |
66e63ffb LB |
1620 | unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); |
1621 | unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); | |
1da177e4 | 1622 | |
5daffe94 LB |
1623 | addr[0] = (mac_h >> 24) & 0xff; |
1624 | addr[1] = (mac_h >> 16) & 0xff; | |
1625 | addr[2] = (mac_h >> 8) & 0xff; | |
1626 | addr[3] = mac_h & 0xff; | |
1627 | addr[4] = (mac_l >> 8) & 0xff; | |
1628 | addr[5] = mac_l & 0xff; | |
c9df406f | 1629 | } |
1da177e4 | 1630 | |
66e63ffb | 1631 | static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) |
c9df406f | 1632 | { |
66e63ffb LB |
1633 | wrlp(mp, MAC_ADDR_HIGH, |
1634 | (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); | |
1635 | wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); | |
c9df406f | 1636 | } |
d0412d96 | 1637 | |
66e63ffb | 1638 | static u32 uc_addr_filter_mask(struct net_device *dev) |
c9df406f | 1639 | { |
66e63ffb LB |
1640 | struct dev_addr_list *uc_ptr; |
1641 | u32 nibbles; | |
1da177e4 | 1642 | |
66e63ffb LB |
1643 | if (dev->flags & IFF_PROMISC) |
1644 | return 0; | |
1da177e4 | 1645 | |
66e63ffb LB |
1646 | nibbles = 1 << (dev->dev_addr[5] & 0x0f); |
1647 | for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) { | |
1648 | if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5)) | |
1649 | return 0; | |
1650 | if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0) | |
1651 | return 0; | |
ff561eef | 1652 | |
66e63ffb LB |
1653 | nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f); |
1654 | } | |
1da177e4 | 1655 | |
66e63ffb | 1656 | return nibbles; |
1da177e4 LT |
1657 | } |
1658 | ||
66e63ffb | 1659 | static void mv643xx_eth_program_unicast_filter(struct net_device *dev) |
1da177e4 | 1660 | { |
e5371493 | 1661 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1662 | u32 port_config; |
1663 | u32 nibbles; | |
1664 | int i; | |
1da177e4 | 1665 | |
cc9754b3 | 1666 | uc_addr_set(mp, dev->dev_addr); |
1da177e4 | 1667 | |
66e63ffb LB |
1668 | port_config = rdlp(mp, PORT_CONFIG); |
1669 | nibbles = uc_addr_filter_mask(dev); | |
1670 | if (!nibbles) { | |
1671 | port_config |= UNICAST_PROMISCUOUS_MODE; | |
1672 | wrlp(mp, PORT_CONFIG, port_config); | |
1673 | return; | |
1674 | } | |
1675 | ||
1676 | for (i = 0; i < 16; i += 4) { | |
1677 | int off = UNICAST_TABLE(mp->port_num) + i; | |
1678 | u32 v; | |
1679 | ||
1680 | v = 0; | |
1681 | if (nibbles & 1) | |
1682 | v |= 0x00000001; | |
1683 | if (nibbles & 2) | |
1684 | v |= 0x00000100; | |
1685 | if (nibbles & 4) | |
1686 | v |= 0x00010000; | |
1687 | if (nibbles & 8) | |
1688 | v |= 0x01000000; | |
1689 | nibbles >>= 4; | |
1690 | ||
1691 | wrl(mp, off, v); | |
1692 | } | |
1693 | ||
1694 | port_config &= ~UNICAST_PROMISCUOUS_MODE; | |
1695 | wrlp(mp, PORT_CONFIG, port_config); | |
1da177e4 LT |
1696 | } |
1697 | ||
69876569 LB |
1698 | static int addr_crc(unsigned char *addr) |
1699 | { | |
1700 | int crc = 0; | |
1701 | int i; | |
1702 | ||
1703 | for (i = 0; i < 6; i++) { | |
1704 | int j; | |
1705 | ||
1706 | crc = (crc ^ addr[i]) << 8; | |
1707 | for (j = 7; j >= 0; j--) { | |
1708 | if (crc & (0x100 << j)) | |
1709 | crc ^= 0x107 << j; | |
1710 | } | |
1711 | } | |
1712 | ||
1713 | return crc; | |
1714 | } | |
1715 | ||
66e63ffb | 1716 | static void mv643xx_eth_program_multicast_filter(struct net_device *dev) |
1da177e4 | 1717 | { |
fc32b0e2 | 1718 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
66e63ffb LB |
1719 | u32 *mc_spec; |
1720 | u32 *mc_other; | |
fc32b0e2 LB |
1721 | struct dev_addr_list *addr; |
1722 | int i; | |
c8aaea25 | 1723 | |
fc32b0e2 | 1724 | if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { |
66e63ffb LB |
1725 | int port_num; |
1726 | u32 accept; | |
1727 | int i; | |
c8aaea25 | 1728 | |
66e63ffb LB |
1729 | oom: |
1730 | port_num = mp->port_num; | |
1731 | accept = 0x01010101; | |
fc32b0e2 LB |
1732 | for (i = 0; i < 0x100; i += 4) { |
1733 | wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); | |
1734 | wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); | |
c9df406f LB |
1735 | } |
1736 | return; | |
1737 | } | |
c8aaea25 | 1738 | |
66e63ffb LB |
1739 | mc_spec = kmalloc(0x200, GFP_KERNEL); |
1740 | if (mc_spec == NULL) | |
1741 | goto oom; | |
1742 | mc_other = mc_spec + (0x100 >> 2); | |
1743 | ||
1744 | memset(mc_spec, 0, 0x100); | |
1745 | memset(mc_other, 0, 0x100); | |
1da177e4 | 1746 | |
fc32b0e2 LB |
1747 | for (addr = dev->mc_list; addr != NULL; addr = addr->next) { |
1748 | u8 *a = addr->da_addr; | |
66e63ffb LB |
1749 | u32 *table; |
1750 | int entry; | |
1da177e4 | 1751 | |
fc32b0e2 | 1752 | if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { |
66e63ffb LB |
1753 | table = mc_spec; |
1754 | entry = a[5]; | |
fc32b0e2 | 1755 | } else { |
66e63ffb LB |
1756 | table = mc_other; |
1757 | entry = addr_crc(a); | |
fc32b0e2 | 1758 | } |
66e63ffb | 1759 | |
2b448334 | 1760 | table[entry >> 2] |= 1 << (8 * (entry & 3)); |
fc32b0e2 | 1761 | } |
66e63ffb LB |
1762 | |
1763 | for (i = 0; i < 0x100; i += 4) { | |
1764 | wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]); | |
1765 | wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]); | |
1766 | } | |
1767 | ||
1768 | kfree(mc_spec); | |
1769 | } | |
1770 | ||
1771 | static void mv643xx_eth_set_rx_mode(struct net_device *dev) | |
1772 | { | |
1773 | mv643xx_eth_program_unicast_filter(dev); | |
1774 | mv643xx_eth_program_multicast_filter(dev); | |
1775 | } | |
1776 | ||
1777 | static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) | |
1778 | { | |
1779 | struct sockaddr *sa = addr; | |
1780 | ||
1781 | memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); | |
1782 | ||
1783 | netif_addr_lock_bh(dev); | |
1784 | mv643xx_eth_program_unicast_filter(dev); | |
1785 | netif_addr_unlock_bh(dev); | |
1786 | ||
1787 | return 0; | |
c9df406f | 1788 | } |
c8aaea25 | 1789 | |
c8aaea25 | 1790 | |
c9df406f | 1791 | /* rx/tx queue initialisation ***********************************************/ |
64da80a2 | 1792 | static int rxq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1793 | { |
64da80a2 | 1794 | struct rx_queue *rxq = mp->rxq + index; |
8a578111 LB |
1795 | struct rx_desc *rx_desc; |
1796 | int size; | |
c9df406f LB |
1797 | int i; |
1798 | ||
64da80a2 LB |
1799 | rxq->index = index; |
1800 | ||
e7d2f4db | 1801 | rxq->rx_ring_size = mp->rx_ring_size; |
8a578111 LB |
1802 | |
1803 | rxq->rx_desc_count = 0; | |
1804 | rxq->rx_curr_desc = 0; | |
1805 | rxq->rx_used_desc = 0; | |
1806 | ||
1807 | size = rxq->rx_ring_size * sizeof(struct rx_desc); | |
1808 | ||
f7981c1c | 1809 | if (index == 0 && size <= mp->rx_desc_sram_size) { |
8a578111 LB |
1810 | rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, |
1811 | mp->rx_desc_sram_size); | |
1812 | rxq->rx_desc_dma = mp->rx_desc_sram_addr; | |
1813 | } else { | |
1814 | rxq->rx_desc_area = dma_alloc_coherent(NULL, size, | |
1815 | &rxq->rx_desc_dma, | |
1816 | GFP_KERNEL); | |
f7ea3337 PJ |
1817 | } |
1818 | ||
8a578111 LB |
1819 | if (rxq->rx_desc_area == NULL) { |
1820 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1821 | "can't allocate rx ring (%d bytes)\n", size); | |
1822 | goto out; | |
1823 | } | |
1824 | memset(rxq->rx_desc_area, 0, size); | |
1da177e4 | 1825 | |
8a578111 LB |
1826 | rxq->rx_desc_area_size = size; |
1827 | rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb), | |
1828 | GFP_KERNEL); | |
1829 | if (rxq->rx_skb == NULL) { | |
1830 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1831 | "can't allocate rx skb ring\n"); | |
1832 | goto out_free; | |
1833 | } | |
1834 | ||
1835 | rx_desc = (struct rx_desc *)rxq->rx_desc_area; | |
1836 | for (i = 0; i < rxq->rx_ring_size; i++) { | |
9da78745 LB |
1837 | int nexti; |
1838 | ||
1839 | nexti = i + 1; | |
1840 | if (nexti == rxq->rx_ring_size) | |
1841 | nexti = 0; | |
1842 | ||
8a578111 LB |
1843 | rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + |
1844 | nexti * sizeof(struct rx_desc); | |
1845 | } | |
1846 | ||
8a578111 LB |
1847 | return 0; |
1848 | ||
1849 | ||
1850 | out_free: | |
f7981c1c | 1851 | if (index == 0 && size <= mp->rx_desc_sram_size) |
8a578111 LB |
1852 | iounmap(rxq->rx_desc_area); |
1853 | else | |
1854 | dma_free_coherent(NULL, size, | |
1855 | rxq->rx_desc_area, | |
1856 | rxq->rx_desc_dma); | |
1857 | ||
1858 | out: | |
1859 | return -ENOMEM; | |
c9df406f | 1860 | } |
c8aaea25 | 1861 | |
8a578111 | 1862 | static void rxq_deinit(struct rx_queue *rxq) |
c9df406f | 1863 | { |
8a578111 LB |
1864 | struct mv643xx_eth_private *mp = rxq_to_mp(rxq); |
1865 | int i; | |
1866 | ||
1867 | rxq_disable(rxq); | |
c8aaea25 | 1868 | |
8a578111 LB |
1869 | for (i = 0; i < rxq->rx_ring_size; i++) { |
1870 | if (rxq->rx_skb[i]) { | |
1871 | dev_kfree_skb(rxq->rx_skb[i]); | |
1872 | rxq->rx_desc_count--; | |
1da177e4 | 1873 | } |
c8aaea25 | 1874 | } |
1da177e4 | 1875 | |
8a578111 LB |
1876 | if (rxq->rx_desc_count) { |
1877 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1878 | "error freeing rx ring -- %d skbs stuck\n", | |
1879 | rxq->rx_desc_count); | |
1880 | } | |
1881 | ||
f7981c1c | 1882 | if (rxq->index == 0 && |
64da80a2 | 1883 | rxq->rx_desc_area_size <= mp->rx_desc_sram_size) |
8a578111 | 1884 | iounmap(rxq->rx_desc_area); |
c9df406f | 1885 | else |
8a578111 LB |
1886 | dma_free_coherent(NULL, rxq->rx_desc_area_size, |
1887 | rxq->rx_desc_area, rxq->rx_desc_dma); | |
1888 | ||
1889 | kfree(rxq->rx_skb); | |
c9df406f | 1890 | } |
1da177e4 | 1891 | |
3d6b35bc | 1892 | static int txq_init(struct mv643xx_eth_private *mp, int index) |
c9df406f | 1893 | { |
3d6b35bc | 1894 | struct tx_queue *txq = mp->txq + index; |
13d64285 LB |
1895 | struct tx_desc *tx_desc; |
1896 | int size; | |
c9df406f | 1897 | int i; |
1da177e4 | 1898 | |
3d6b35bc LB |
1899 | txq->index = index; |
1900 | ||
e7d2f4db | 1901 | txq->tx_ring_size = mp->tx_ring_size; |
13d64285 LB |
1902 | |
1903 | txq->tx_desc_count = 0; | |
1904 | txq->tx_curr_desc = 0; | |
1905 | txq->tx_used_desc = 0; | |
1906 | ||
1907 | size = txq->tx_ring_size * sizeof(struct tx_desc); | |
1908 | ||
f7981c1c | 1909 | if (index == 0 && size <= mp->tx_desc_sram_size) { |
13d64285 LB |
1910 | txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, |
1911 | mp->tx_desc_sram_size); | |
1912 | txq->tx_desc_dma = mp->tx_desc_sram_addr; | |
1913 | } else { | |
1914 | txq->tx_desc_area = dma_alloc_coherent(NULL, size, | |
1915 | &txq->tx_desc_dma, | |
1916 | GFP_KERNEL); | |
1917 | } | |
1918 | ||
1919 | if (txq->tx_desc_area == NULL) { | |
1920 | dev_printk(KERN_ERR, &mp->dev->dev, | |
1921 | "can't allocate tx ring (%d bytes)\n", size); | |
99ab08e0 | 1922 | return -ENOMEM; |
c9df406f | 1923 | } |
13d64285 LB |
1924 | memset(txq->tx_desc_area, 0, size); |
1925 | ||
1926 | txq->tx_desc_area_size = size; | |
13d64285 LB |
1927 | |
1928 | tx_desc = (struct tx_desc *)txq->tx_desc_area; | |
1929 | for (i = 0; i < txq->tx_ring_size; i++) { | |
6b368f68 | 1930 | struct tx_desc *txd = tx_desc + i; |
9da78745 LB |
1931 | int nexti; |
1932 | ||
1933 | nexti = i + 1; | |
1934 | if (nexti == txq->tx_ring_size) | |
1935 | nexti = 0; | |
6b368f68 LB |
1936 | |
1937 | txd->cmd_sts = 0; | |
1938 | txd->next_desc_ptr = txq->tx_desc_dma + | |
13d64285 LB |
1939 | nexti * sizeof(struct tx_desc); |
1940 | } | |
1941 | ||
99ab08e0 | 1942 | skb_queue_head_init(&txq->tx_skb); |
c9df406f | 1943 | |
99ab08e0 | 1944 | return 0; |
c8aaea25 | 1945 | } |
1da177e4 | 1946 | |
13d64285 | 1947 | static void txq_deinit(struct tx_queue *txq) |
c9df406f | 1948 | { |
13d64285 | 1949 | struct mv643xx_eth_private *mp = txq_to_mp(txq); |
fa3959f4 | 1950 | |
13d64285 | 1951 | txq_disable(txq); |
1fa38c58 | 1952 | txq_reclaim(txq, txq->tx_ring_size, 1); |
1da177e4 | 1953 | |
13d64285 | 1954 | BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); |
1da177e4 | 1955 | |
f7981c1c | 1956 | if (txq->index == 0 && |
3d6b35bc | 1957 | txq->tx_desc_area_size <= mp->tx_desc_sram_size) |
13d64285 | 1958 | iounmap(txq->tx_desc_area); |
c9df406f | 1959 | else |
13d64285 LB |
1960 | dma_free_coherent(NULL, txq->tx_desc_area_size, |
1961 | txq->tx_desc_area, txq->tx_desc_dma); | |
c9df406f | 1962 | } |
1da177e4 | 1963 | |
1da177e4 | 1964 | |
c9df406f | 1965 | /* netdev ops and related ***************************************************/ |
1fa38c58 LB |
1966 | static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) |
1967 | { | |
1968 | u32 int_cause; | |
1969 | u32 int_cause_ext; | |
1970 | ||
37a6084f | 1971 | int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT); |
1fa38c58 LB |
1972 | if (int_cause == 0) |
1973 | return 0; | |
1974 | ||
1975 | int_cause_ext = 0; | |
1976 | if (int_cause & INT_EXT) | |
37a6084f | 1977 | int_cause_ext = rdlp(mp, INT_CAUSE_EXT); |
1fa38c58 LB |
1978 | |
1979 | int_cause &= INT_TX_END | INT_RX; | |
1980 | if (int_cause) { | |
37a6084f | 1981 | wrlp(mp, INT_CAUSE, ~int_cause); |
1fa38c58 | 1982 | mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & |
37a6084f | 1983 | ~(rdlp(mp, TXQ_COMMAND) & 0xff); |
1fa38c58 LB |
1984 | mp->work_rx |= (int_cause & INT_RX) >> 2; |
1985 | } | |
1986 | ||
1987 | int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; | |
1988 | if (int_cause_ext) { | |
37a6084f | 1989 | wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); |
1fa38c58 LB |
1990 | if (int_cause_ext & INT_EXT_LINK_PHY) |
1991 | mp->work_link = 1; | |
1992 | mp->work_tx |= int_cause_ext & INT_EXT_TX; | |
1993 | } | |
1994 | ||
1995 | return 1; | |
1996 | } | |
1997 | ||
1998 | static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) | |
1999 | { | |
2000 | struct net_device *dev = (struct net_device *)dev_id; | |
2001 | struct mv643xx_eth_private *mp = netdev_priv(dev); | |
2002 | ||
2003 | if (unlikely(!mv643xx_eth_collect_events(mp))) | |
2004 | return IRQ_NONE; | |
2005 | ||
37a6084f | 2006 | wrlp(mp, INT_MASK, 0); |
1fa38c58 LB |
2007 | napi_schedule(&mp->napi); |
2008 | ||
2009 | return IRQ_HANDLED; | |
2010 | } | |
2011 | ||
2f7eb47a LB |
2012 | static void handle_link_event(struct mv643xx_eth_private *mp) |
2013 | { | |
2014 | struct net_device *dev = mp->dev; | |
2015 | u32 port_status; | |
2016 | int speed; | |
2017 | int duplex; | |
2018 | int fc; | |
2019 | ||
37a6084f | 2020 | port_status = rdlp(mp, PORT_STATUS); |
2f7eb47a LB |
2021 | if (!(port_status & LINK_UP)) { |
2022 | if (netif_carrier_ok(dev)) { | |
2023 | int i; | |
2024 | ||
2025 | printk(KERN_INFO "%s: link down\n", dev->name); | |
2026 | ||
2027 | netif_carrier_off(dev); | |
2f7eb47a | 2028 | |
f7981c1c | 2029 | for (i = 0; i < mp->txq_count; i++) { |
2f7eb47a LB |
2030 | struct tx_queue *txq = mp->txq + i; |
2031 | ||
1fa38c58 | 2032 | txq_reclaim(txq, txq->tx_ring_size, 1); |
f7981c1c | 2033 | txq_reset_hw_ptr(txq); |
2f7eb47a LB |
2034 | } |
2035 | } | |
2036 | return; | |
2037 | } | |
2038 | ||
2039 | switch (port_status & PORT_SPEED_MASK) { | |
2040 | case PORT_SPEED_10: | |
2041 | speed = 10; | |
2042 | break; | |
2043 | case PORT_SPEED_100: | |
2044 | speed = 100; | |
2045 | break; | |
2046 | case PORT_SPEED_1000: | |
2047 | speed = 1000; | |
2048 | break; | |
2049 | default: | |
2050 | speed = -1; | |
2051 | break; | |
2052 | } | |
2053 | duplex = (port_status & FULL_DUPLEX) ? 1 : 0; | |
2054 | fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; | |
2055 | ||
2056 | printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " | |
2057 | "flow control %sabled\n", dev->name, | |
2058 | speed, duplex ? "full" : "half", | |
2059 | fc ? "en" : "dis"); | |
2060 | ||
4fdeca3f | 2061 | if (!netif_carrier_ok(dev)) |
2f7eb47a | 2062 | netif_carrier_on(dev); |
2f7eb47a LB |
2063 | } |
2064 | ||
1fa38c58 | 2065 | static int mv643xx_eth_poll(struct napi_struct *napi, int budget) |
c9df406f | 2066 | { |
1fa38c58 LB |
2067 | struct mv643xx_eth_private *mp; |
2068 | int work_done; | |
ce4e2e45 | 2069 | |
1fa38c58 | 2070 | mp = container_of(napi, struct mv643xx_eth_private, napi); |
fc32b0e2 | 2071 | |
1fa38c58 LB |
2072 | mp->work_rx_refill |= mp->work_rx_oom; |
2073 | mp->work_rx_oom = 0; | |
1da177e4 | 2074 | |
1fa38c58 LB |
2075 | work_done = 0; |
2076 | while (work_done < budget) { | |
2077 | u8 queue_mask; | |
2078 | int queue; | |
2079 | int work_tbd; | |
2080 | ||
2081 | if (mp->work_link) { | |
2082 | mp->work_link = 0; | |
2083 | handle_link_event(mp); | |
2084 | continue; | |
2085 | } | |
1da177e4 | 2086 | |
1fa38c58 LB |
2087 | queue_mask = mp->work_tx | mp->work_tx_end | |
2088 | mp->work_rx | mp->work_rx_refill; | |
2089 | if (!queue_mask) { | |
2090 | if (mv643xx_eth_collect_events(mp)) | |
2091 | continue; | |
2092 | break; | |
2093 | } | |
1da177e4 | 2094 | |
1fa38c58 LB |
2095 | queue = fls(queue_mask) - 1; |
2096 | queue_mask = 1 << queue; | |
2097 | ||
2098 | work_tbd = budget - work_done; | |
2099 | if (work_tbd > 16) | |
2100 | work_tbd = 16; | |
2101 | ||
2102 | if (mp->work_tx_end & queue_mask) { | |
2103 | txq_kick(mp->txq + queue); | |
2104 | } else if (mp->work_tx & queue_mask) { | |
2105 | work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); | |
2106 | txq_maybe_wake(mp->txq + queue); | |
2107 | } else if (mp->work_rx & queue_mask) { | |
2108 | work_done += rxq_process(mp->rxq + queue, work_tbd); | |
2109 | } else if (mp->work_rx_refill & queue_mask) { | |
2110 | work_done += rxq_refill(mp->rxq + queue, work_tbd); | |
2111 | } else { | |
2112 | BUG(); | |
2113 | } | |
84dd619e | 2114 | } |
fc32b0e2 | 2115 | |
1fa38c58 LB |
2116 | if (work_done < budget) { |
2117 | if (mp->work_rx_oom) | |
2118 | mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); | |
2119 | napi_complete(napi); | |
37a6084f | 2120 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); |
226bb6b7 | 2121 | } |
3d6b35bc | 2122 | |
1fa38c58 LB |
2123 | return work_done; |
2124 | } | |
8fa89bf5 | 2125 | |
1fa38c58 LB |
2126 | static inline void oom_timer_wrapper(unsigned long data) |
2127 | { | |
2128 | struct mv643xx_eth_private *mp = (void *)data; | |
1da177e4 | 2129 | |
1fa38c58 | 2130 | napi_schedule(&mp->napi); |
1da177e4 LT |
2131 | } |
2132 | ||
e5371493 | 2133 | static void phy_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2134 | { |
45c5d3bc LB |
2135 | int data; |
2136 | ||
ed94493f | 2137 | data = phy_read(mp->phy, MII_BMCR); |
45c5d3bc LB |
2138 | if (data < 0) |
2139 | return; | |
1da177e4 | 2140 | |
7f106c1d | 2141 | data |= BMCR_RESET; |
ed94493f | 2142 | if (phy_write(mp->phy, MII_BMCR, data) < 0) |
45c5d3bc | 2143 | return; |
1da177e4 | 2144 | |
c9df406f | 2145 | do { |
ed94493f | 2146 | data = phy_read(mp->phy, MII_BMCR); |
45c5d3bc | 2147 | } while (data >= 0 && data & BMCR_RESET); |
1da177e4 LT |
2148 | } |
2149 | ||
fc32b0e2 | 2150 | static void port_start(struct mv643xx_eth_private *mp) |
1da177e4 | 2151 | { |
d0412d96 | 2152 | u32 pscr; |
8a578111 | 2153 | int i; |
1da177e4 | 2154 | |
bedfe324 LB |
2155 | /* |
2156 | * Perform PHY reset, if there is a PHY. | |
2157 | */ | |
ed94493f | 2158 | if (mp->phy != NULL) { |
bedfe324 LB |
2159 | struct ethtool_cmd cmd; |
2160 | ||
2161 | mv643xx_eth_get_settings(mp->dev, &cmd); | |
2162 | phy_reset(mp); | |
2163 | mv643xx_eth_set_settings(mp->dev, &cmd); | |
2164 | } | |
1da177e4 | 2165 | |
81600eea LB |
2166 | /* |
2167 | * Configure basic link parameters. | |
2168 | */ | |
37a6084f | 2169 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
2170 | |
2171 | pscr |= SERIAL_PORT_ENABLE; | |
37a6084f | 2172 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2173 | |
2174 | pscr |= DO_NOT_FORCE_LINK_FAIL; | |
ed94493f | 2175 | if (mp->phy == NULL) |
81600eea | 2176 | pscr |= FORCE_LINK_PASS; |
37a6084f | 2177 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea | 2178 | |
37a6084f | 2179 | wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); |
81600eea | 2180 | |
13d64285 LB |
2181 | /* |
2182 | * Configure TX path and queues. | |
2183 | */ | |
89df5fdc | 2184 | tx_set_rate(mp, 1000000000, 16777216); |
f7981c1c | 2185 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc | 2186 | struct tx_queue *txq = mp->txq + i; |
13d64285 | 2187 | |
6b368f68 | 2188 | txq_reset_hw_ptr(txq); |
89df5fdc LB |
2189 | txq_set_rate(txq, 1000000000, 16777216); |
2190 | txq_set_fixed_prio_mode(txq); | |
13d64285 LB |
2191 | } |
2192 | ||
fc32b0e2 LB |
2193 | /* |
2194 | * Add configured unicast address to address filter table. | |
2195 | */ | |
66e63ffb | 2196 | mv643xx_eth_program_unicast_filter(mp->dev); |
1da177e4 | 2197 | |
d9a073ea LB |
2198 | /* |
2199 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | |
170e7108 LB |
2200 | * frames to RX queue #0, and include the pseudo-header when |
2201 | * calculating receive checksums. | |
d9a073ea | 2202 | */ |
37a6084f | 2203 | wrlp(mp, PORT_CONFIG, 0x02000000); |
01999873 | 2204 | |
376489a2 LB |
2205 | /* |
2206 | * Treat BPDUs as normal multicasts, and disable partition mode. | |
2207 | */ | |
37a6084f | 2208 | wrlp(mp, PORT_CONFIG_EXT, 0x00000000); |
01999873 | 2209 | |
8a578111 | 2210 | /* |
64da80a2 | 2211 | * Enable the receive queues. |
8a578111 | 2212 | */ |
f7981c1c | 2213 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 | 2214 | struct rx_queue *rxq = mp->rxq + i; |
8a578111 | 2215 | u32 addr; |
1da177e4 | 2216 | |
8a578111 LB |
2217 | addr = (u32)rxq->rx_desc_dma; |
2218 | addr += rxq->rx_curr_desc * sizeof(struct rx_desc); | |
37a6084f | 2219 | wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); |
1da177e4 | 2220 | |
8a578111 LB |
2221 | rxq_enable(rxq); |
2222 | } | |
1da177e4 LT |
2223 | } |
2224 | ||
2bcb4b0f LB |
2225 | static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) |
2226 | { | |
2227 | int skb_size; | |
2228 | ||
2229 | /* | |
2230 | * Reserve 2+14 bytes for an ethernet header (the hardware | |
2231 | * automatically prepends 2 bytes of dummy data to each | |
2232 | * received packet), 16 bytes for up to four VLAN tags, and | |
2233 | * 4 bytes for the trailing FCS -- 36 bytes total. | |
2234 | */ | |
2235 | skb_size = mp->dev->mtu + 36; | |
2236 | ||
2237 | /* | |
2238 | * Make sure that the skb size is a multiple of 8 bytes, as | |
2239 | * the lower three bits of the receive descriptor's buffer | |
2240 | * size field are ignored by the hardware. | |
2241 | */ | |
2242 | mp->skb_size = (skb_size + 7) & ~7; | |
2243 | } | |
2244 | ||
c9df406f | 2245 | static int mv643xx_eth_open(struct net_device *dev) |
16e03018 | 2246 | { |
e5371493 | 2247 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2248 | int err; |
64da80a2 | 2249 | int i; |
16e03018 | 2250 | |
37a6084f LB |
2251 | wrlp(mp, INT_CAUSE, 0); |
2252 | wrlp(mp, INT_CAUSE_EXT, 0); | |
2253 | rdlp(mp, INT_CAUSE_EXT); | |
c9df406f | 2254 | |
fc32b0e2 | 2255 | err = request_irq(dev->irq, mv643xx_eth_irq, |
2a1867a7 | 2256 | IRQF_SHARED, dev->name, dev); |
c9df406f | 2257 | if (err) { |
fc32b0e2 | 2258 | dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n"); |
c9df406f | 2259 | return -EAGAIN; |
16e03018 DF |
2260 | } |
2261 | ||
2bcb4b0f LB |
2262 | mv643xx_eth_recalc_skb_size(mp); |
2263 | ||
2257e05c LB |
2264 | napi_enable(&mp->napi); |
2265 | ||
2bcb4b0f LB |
2266 | skb_queue_head_init(&mp->rx_recycle); |
2267 | ||
f7981c1c | 2268 | for (i = 0; i < mp->rxq_count; i++) { |
64da80a2 LB |
2269 | err = rxq_init(mp, i); |
2270 | if (err) { | |
2271 | while (--i >= 0) | |
f7981c1c | 2272 | rxq_deinit(mp->rxq + i); |
64da80a2 LB |
2273 | goto out; |
2274 | } | |
2275 | ||
1fa38c58 | 2276 | rxq_refill(mp->rxq + i, INT_MAX); |
2257e05c LB |
2277 | } |
2278 | ||
1fa38c58 | 2279 | if (mp->work_rx_oom) { |
2257e05c LB |
2280 | mp->rx_oom.expires = jiffies + (HZ / 10); |
2281 | add_timer(&mp->rx_oom); | |
64da80a2 | 2282 | } |
8a578111 | 2283 | |
f7981c1c | 2284 | for (i = 0; i < mp->txq_count; i++) { |
3d6b35bc LB |
2285 | err = txq_init(mp, i); |
2286 | if (err) { | |
2287 | while (--i >= 0) | |
f7981c1c | 2288 | txq_deinit(mp->txq + i); |
3d6b35bc LB |
2289 | goto out_free; |
2290 | } | |
2291 | } | |
16e03018 | 2292 | |
2f7eb47a | 2293 | netif_carrier_off(dev); |
2f7eb47a | 2294 | |
fc32b0e2 | 2295 | port_start(mp); |
16e03018 | 2296 | |
ffd86bbe LB |
2297 | set_rx_coal(mp, 0); |
2298 | set_tx_coal(mp, 0); | |
16e03018 | 2299 | |
37a6084f LB |
2300 | wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); |
2301 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); | |
16e03018 | 2302 | |
c9df406f LB |
2303 | return 0; |
2304 | ||
13d64285 | 2305 | |
fc32b0e2 | 2306 | out_free: |
f7981c1c LB |
2307 | for (i = 0; i < mp->rxq_count; i++) |
2308 | rxq_deinit(mp->rxq + i); | |
fc32b0e2 | 2309 | out: |
c9df406f LB |
2310 | free_irq(dev->irq, dev); |
2311 | ||
2312 | return err; | |
16e03018 DF |
2313 | } |
2314 | ||
e5371493 | 2315 | static void port_reset(struct mv643xx_eth_private *mp) |
1da177e4 | 2316 | { |
fc32b0e2 | 2317 | unsigned int data; |
64da80a2 | 2318 | int i; |
1da177e4 | 2319 | |
f7981c1c LB |
2320 | for (i = 0; i < mp->rxq_count; i++) |
2321 | rxq_disable(mp->rxq + i); | |
2322 | for (i = 0; i < mp->txq_count; i++) | |
2323 | txq_disable(mp->txq + i); | |
ae9ae064 LB |
2324 | |
2325 | while (1) { | |
37a6084f | 2326 | u32 ps = rdlp(mp, PORT_STATUS); |
ae9ae064 LB |
2327 | |
2328 | if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) | |
2329 | break; | |
13d64285 | 2330 | udelay(10); |
ae9ae064 | 2331 | } |
1da177e4 | 2332 | |
c9df406f | 2333 | /* Reset the Enable bit in the Configuration Register */ |
37a6084f | 2334 | data = rdlp(mp, PORT_SERIAL_CONTROL); |
fc32b0e2 LB |
2335 | data &= ~(SERIAL_PORT_ENABLE | |
2336 | DO_NOT_FORCE_LINK_FAIL | | |
2337 | FORCE_LINK_PASS); | |
37a6084f | 2338 | wrlp(mp, PORT_SERIAL_CONTROL, data); |
1da177e4 LT |
2339 | } |
2340 | ||
c9df406f | 2341 | static int mv643xx_eth_stop(struct net_device *dev) |
1da177e4 | 2342 | { |
e5371493 | 2343 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
64da80a2 | 2344 | int i; |
1da177e4 | 2345 | |
fe65e704 | 2346 | wrlp(mp, INT_MASK_EXT, 0x00000000); |
37a6084f LB |
2347 | wrlp(mp, INT_MASK, 0x00000000); |
2348 | rdlp(mp, INT_MASK); | |
1da177e4 | 2349 | |
4ff3495a LB |
2350 | del_timer_sync(&mp->mib_counters_timer); |
2351 | ||
c9df406f | 2352 | napi_disable(&mp->napi); |
78fff83b | 2353 | |
2257e05c LB |
2354 | del_timer_sync(&mp->rx_oom); |
2355 | ||
c9df406f | 2356 | netif_carrier_off(dev); |
1da177e4 | 2357 | |
fc32b0e2 LB |
2358 | free_irq(dev->irq, dev); |
2359 | ||
cc9754b3 | 2360 | port_reset(mp); |
8fd89211 | 2361 | mv643xx_eth_get_stats(dev); |
fc32b0e2 | 2362 | mib_counters_update(mp); |
1da177e4 | 2363 | |
2bcb4b0f LB |
2364 | skb_queue_purge(&mp->rx_recycle); |
2365 | ||
f7981c1c LB |
2366 | for (i = 0; i < mp->rxq_count; i++) |
2367 | rxq_deinit(mp->rxq + i); | |
2368 | for (i = 0; i < mp->txq_count; i++) | |
2369 | txq_deinit(mp->txq + i); | |
1da177e4 | 2370 | |
c9df406f | 2371 | return 0; |
1da177e4 LT |
2372 | } |
2373 | ||
fc32b0e2 | 2374 | static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1da177e4 | 2375 | { |
e5371493 | 2376 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2377 | |
ed94493f LB |
2378 | if (mp->phy != NULL) |
2379 | return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd); | |
bedfe324 LB |
2380 | |
2381 | return -EOPNOTSUPP; | |
1da177e4 LT |
2382 | } |
2383 | ||
c9df406f | 2384 | static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 2385 | { |
89df5fdc LB |
2386 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
2387 | ||
fc32b0e2 | 2388 | if (new_mtu < 64 || new_mtu > 9500) |
c9df406f | 2389 | return -EINVAL; |
1da177e4 | 2390 | |
c9df406f | 2391 | dev->mtu = new_mtu; |
2bcb4b0f | 2392 | mv643xx_eth_recalc_skb_size(mp); |
89df5fdc LB |
2393 | tx_set_rate(mp, 1000000000, 16777216); |
2394 | ||
c9df406f LB |
2395 | if (!netif_running(dev)) |
2396 | return 0; | |
1da177e4 | 2397 | |
c9df406f LB |
2398 | /* |
2399 | * Stop and then re-open the interface. This will allocate RX | |
2400 | * skbs of the new MTU. | |
2401 | * There is a possible danger that the open will not succeed, | |
fc32b0e2 | 2402 | * due to memory being full. |
c9df406f LB |
2403 | */ |
2404 | mv643xx_eth_stop(dev); | |
2405 | if (mv643xx_eth_open(dev)) { | |
fc32b0e2 LB |
2406 | dev_printk(KERN_ERR, &dev->dev, |
2407 | "fatal error on re-opening device after " | |
2408 | "MTU change\n"); | |
c9df406f LB |
2409 | } |
2410 | ||
2411 | return 0; | |
1da177e4 LT |
2412 | } |
2413 | ||
fc32b0e2 | 2414 | static void tx_timeout_task(struct work_struct *ugly) |
1da177e4 | 2415 | { |
fc32b0e2 | 2416 | struct mv643xx_eth_private *mp; |
1da177e4 | 2417 | |
fc32b0e2 LB |
2418 | mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); |
2419 | if (netif_running(mp->dev)) { | |
e5ef1de1 | 2420 | netif_tx_stop_all_queues(mp->dev); |
fc32b0e2 LB |
2421 | port_reset(mp); |
2422 | port_start(mp); | |
e5ef1de1 | 2423 | netif_tx_wake_all_queues(mp->dev); |
fc32b0e2 | 2424 | } |
c9df406f LB |
2425 | } |
2426 | ||
c9df406f | 2427 | static void mv643xx_eth_tx_timeout(struct net_device *dev) |
1da177e4 | 2428 | { |
e5371493 | 2429 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
1da177e4 | 2430 | |
fc32b0e2 | 2431 | dev_printk(KERN_INFO, &dev->dev, "tx timeout\n"); |
d0412d96 | 2432 | |
c9df406f | 2433 | schedule_work(&mp->tx_timeout_task); |
1da177e4 LT |
2434 | } |
2435 | ||
c9df406f | 2436 | #ifdef CONFIG_NET_POLL_CONTROLLER |
fc32b0e2 | 2437 | static void mv643xx_eth_netpoll(struct net_device *dev) |
9f8dd319 | 2438 | { |
fc32b0e2 | 2439 | struct mv643xx_eth_private *mp = netdev_priv(dev); |
c9df406f | 2440 | |
37a6084f LB |
2441 | wrlp(mp, INT_MASK, 0x00000000); |
2442 | rdlp(mp, INT_MASK); | |
c9df406f | 2443 | |
fc32b0e2 | 2444 | mv643xx_eth_irq(dev->irq, dev); |
c9df406f | 2445 | |
37a6084f | 2446 | wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT); |
9f8dd319 | 2447 | } |
c9df406f | 2448 | #endif |
9f8dd319 | 2449 | |
9f8dd319 | 2450 | |
c9df406f | 2451 | /* platform glue ************************************************************/ |
e5371493 LB |
2452 | static void |
2453 | mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, | |
2454 | struct mbus_dram_target_info *dram) | |
c9df406f | 2455 | { |
cc9754b3 | 2456 | void __iomem *base = msp->base; |
c9df406f LB |
2457 | u32 win_enable; |
2458 | u32 win_protect; | |
2459 | int i; | |
9f8dd319 | 2460 | |
c9df406f LB |
2461 | for (i = 0; i < 6; i++) { |
2462 | writel(0, base + WINDOW_BASE(i)); | |
2463 | writel(0, base + WINDOW_SIZE(i)); | |
2464 | if (i < 4) | |
2465 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
9f8dd319 DF |
2466 | } |
2467 | ||
c9df406f LB |
2468 | win_enable = 0x3f; |
2469 | win_protect = 0; | |
2470 | ||
2471 | for (i = 0; i < dram->num_cs; i++) { | |
2472 | struct mbus_dram_window *cs = dram->cs + i; | |
2473 | ||
2474 | writel((cs->base & 0xffff0000) | | |
2475 | (cs->mbus_attr << 8) | | |
2476 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
2477 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
2478 | ||
2479 | win_enable &= ~(1 << i); | |
2480 | win_protect |= 3 << (2 * i); | |
2481 | } | |
2482 | ||
2483 | writel(win_enable, base + WINDOW_BAR_ENABLE); | |
2484 | msp->win_protect = win_protect; | |
9f8dd319 DF |
2485 | } |
2486 | ||
773fc3ee LB |
2487 | static void infer_hw_params(struct mv643xx_eth_shared_private *msp) |
2488 | { | |
2489 | /* | |
2490 | * Check whether we have a 14-bit coal limit field in bits | |
2491 | * [21:8], or a 16-bit coal limit in bits [25,21:7] of the | |
2492 | * SDMA config register. | |
2493 | */ | |
37a6084f LB |
2494 | writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); |
2495 | if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) | |
773fc3ee LB |
2496 | msp->extended_rx_coal_limit = 1; |
2497 | else | |
2498 | msp->extended_rx_coal_limit = 0; | |
1e881592 LB |
2499 | |
2500 | /* | |
457b1d5a LB |
2501 | * Check whether the MAC supports TX rate control, and if |
2502 | * yes, whether its associated registers are in the old or | |
2503 | * the new place. | |
1e881592 | 2504 | */ |
37a6084f LB |
2505 | writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); |
2506 | if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { | |
457b1d5a LB |
2507 | msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; |
2508 | } else { | |
37a6084f LB |
2509 | writel(7, msp->base + 0x0400 + TX_BW_RATE); |
2510 | if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) | |
457b1d5a LB |
2511 | msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; |
2512 | else | |
2513 | msp->tx_bw_control = TX_BW_CONTROL_ABSENT; | |
2514 | } | |
773fc3ee LB |
2515 | } |
2516 | ||
c9df406f | 2517 | static int mv643xx_eth_shared_probe(struct platform_device *pdev) |
9f8dd319 | 2518 | { |
10a9948d | 2519 | static int mv643xx_eth_version_printed; |
c9df406f | 2520 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
e5371493 | 2521 | struct mv643xx_eth_shared_private *msp; |
c9df406f LB |
2522 | struct resource *res; |
2523 | int ret; | |
9f8dd319 | 2524 | |
e5371493 | 2525 | if (!mv643xx_eth_version_printed++) |
7dde154d LB |
2526 | printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet " |
2527 | "driver version %s\n", mv643xx_eth_driver_version); | |
9f8dd319 | 2528 | |
c9df406f LB |
2529 | ret = -EINVAL; |
2530 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2531 | if (res == NULL) | |
2532 | goto out; | |
9f8dd319 | 2533 | |
c9df406f LB |
2534 | ret = -ENOMEM; |
2535 | msp = kmalloc(sizeof(*msp), GFP_KERNEL); | |
2536 | if (msp == NULL) | |
2537 | goto out; | |
2538 | memset(msp, 0, sizeof(*msp)); | |
2539 | ||
cc9754b3 LB |
2540 | msp->base = ioremap(res->start, res->end - res->start + 1); |
2541 | if (msp->base == NULL) | |
c9df406f LB |
2542 | goto out_free; |
2543 | ||
ed94493f LB |
2544 | /* |
2545 | * Set up and register SMI bus. | |
2546 | */ | |
2547 | if (pd == NULL || pd->shared_smi == NULL) { | |
298cf9be LB |
2548 | msp->smi_bus = mdiobus_alloc(); |
2549 | if (msp->smi_bus == NULL) | |
ed94493f | 2550 | goto out_unmap; |
298cf9be LB |
2551 | |
2552 | msp->smi_bus->priv = msp; | |
2553 | msp->smi_bus->name = "mv643xx_eth smi"; | |
2554 | msp->smi_bus->read = smi_bus_read; | |
2555 | msp->smi_bus->write = smi_bus_write, | |
2556 | snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); | |
2557 | msp->smi_bus->parent = &pdev->dev; | |
2558 | msp->smi_bus->phy_mask = 0xffffffff; | |
2559 | if (mdiobus_register(msp->smi_bus) < 0) | |
2560 | goto out_free_mii_bus; | |
ed94493f LB |
2561 | msp->smi = msp; |
2562 | } else { | |
fc0eb9f2 | 2563 | msp->smi = platform_get_drvdata(pd->shared_smi); |
ed94493f | 2564 | } |
c9df406f | 2565 | |
45c5d3bc LB |
2566 | msp->err_interrupt = NO_IRQ; |
2567 | init_waitqueue_head(&msp->smi_busy_wait); | |
2568 | ||
2569 | /* | |
2570 | * Check whether the error interrupt is hooked up. | |
2571 | */ | |
2572 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
2573 | if (res != NULL) { | |
2574 | int err; | |
2575 | ||
2576 | err = request_irq(res->start, mv643xx_eth_err_irq, | |
2577 | IRQF_SHARED, "mv643xx_eth", msp); | |
2578 | if (!err) { | |
2579 | writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK); | |
2580 | msp->err_interrupt = res->start; | |
2581 | } | |
2582 | } | |
2583 | ||
c9df406f LB |
2584 | /* |
2585 | * (Re-)program MBUS remapping windows if we are asked to. | |
2586 | */ | |
2587 | if (pd != NULL && pd->dram != NULL) | |
2588 | mv643xx_eth_conf_mbus_windows(msp, pd->dram); | |
2589 | ||
fc32b0e2 LB |
2590 | /* |
2591 | * Detect hardware parameters. | |
2592 | */ | |
2593 | msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000; | |
773fc3ee | 2594 | infer_hw_params(msp); |
fc32b0e2 LB |
2595 | |
2596 | platform_set_drvdata(pdev, msp); | |
2597 | ||
c9df406f LB |
2598 | return 0; |
2599 | ||
298cf9be LB |
2600 | out_free_mii_bus: |
2601 | mdiobus_free(msp->smi_bus); | |
ed94493f LB |
2602 | out_unmap: |
2603 | iounmap(msp->base); | |
c9df406f LB |
2604 | out_free: |
2605 | kfree(msp); | |
2606 | out: | |
2607 | return ret; | |
2608 | } | |
2609 | ||
2610 | static int mv643xx_eth_shared_remove(struct platform_device *pdev) | |
2611 | { | |
e5371493 | 2612 | struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); |
ed94493f | 2613 | struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data; |
c9df406f | 2614 | |
298cf9be | 2615 | if (pd == NULL || pd->shared_smi == NULL) { |
298cf9be | 2616 | mdiobus_unregister(msp->smi_bus); |
bcb3336c | 2617 | mdiobus_free(msp->smi_bus); |
298cf9be | 2618 | } |
45c5d3bc LB |
2619 | if (msp->err_interrupt != NO_IRQ) |
2620 | free_irq(msp->err_interrupt, msp); | |
cc9754b3 | 2621 | iounmap(msp->base); |
c9df406f LB |
2622 | kfree(msp); |
2623 | ||
2624 | return 0; | |
9f8dd319 DF |
2625 | } |
2626 | ||
c9df406f | 2627 | static struct platform_driver mv643xx_eth_shared_driver = { |
fc32b0e2 LB |
2628 | .probe = mv643xx_eth_shared_probe, |
2629 | .remove = mv643xx_eth_shared_remove, | |
c9df406f | 2630 | .driver = { |
fc32b0e2 | 2631 | .name = MV643XX_ETH_SHARED_NAME, |
c9df406f LB |
2632 | .owner = THIS_MODULE, |
2633 | }, | |
2634 | }; | |
2635 | ||
e5371493 | 2636 | static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) |
1da177e4 | 2637 | { |
c9df406f | 2638 | int addr_shift = 5 * mp->port_num; |
fc32b0e2 | 2639 | u32 data; |
1da177e4 | 2640 | |
fc32b0e2 LB |
2641 | data = rdl(mp, PHY_ADDR); |
2642 | data &= ~(0x1f << addr_shift); | |
2643 | data |= (phy_addr & 0x1f) << addr_shift; | |
2644 | wrl(mp, PHY_ADDR, data); | |
1da177e4 LT |
2645 | } |
2646 | ||
e5371493 | 2647 | static int phy_addr_get(struct mv643xx_eth_private *mp) |
1da177e4 | 2648 | { |
fc32b0e2 LB |
2649 | unsigned int data; |
2650 | ||
2651 | data = rdl(mp, PHY_ADDR); | |
2652 | ||
2653 | return (data >> (5 * mp->port_num)) & 0x1f; | |
2654 | } | |
2655 | ||
2656 | static void set_params(struct mv643xx_eth_private *mp, | |
2657 | struct mv643xx_eth_platform_data *pd) | |
2658 | { | |
2659 | struct net_device *dev = mp->dev; | |
2660 | ||
2661 | if (is_valid_ether_addr(pd->mac_addr)) | |
2662 | memcpy(dev->dev_addr, pd->mac_addr, 6); | |
2663 | else | |
2664 | uc_addr_get(mp, dev->dev_addr); | |
2665 | ||
e7d2f4db | 2666 | mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; |
fc32b0e2 | 2667 | if (pd->rx_queue_size) |
e7d2f4db | 2668 | mp->rx_ring_size = pd->rx_queue_size; |
fc32b0e2 LB |
2669 | mp->rx_desc_sram_addr = pd->rx_sram_addr; |
2670 | mp->rx_desc_sram_size = pd->rx_sram_size; | |
1da177e4 | 2671 | |
f7981c1c | 2672 | mp->rxq_count = pd->rx_queue_count ? : 1; |
64da80a2 | 2673 | |
e7d2f4db | 2674 | mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE; |
fc32b0e2 | 2675 | if (pd->tx_queue_size) |
e7d2f4db | 2676 | mp->tx_ring_size = pd->tx_queue_size; |
fc32b0e2 LB |
2677 | mp->tx_desc_sram_addr = pd->tx_sram_addr; |
2678 | mp->tx_desc_sram_size = pd->tx_sram_size; | |
3d6b35bc | 2679 | |
f7981c1c | 2680 | mp->txq_count = pd->tx_queue_count ? : 1; |
1da177e4 LT |
2681 | } |
2682 | ||
ed94493f LB |
2683 | static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, |
2684 | int phy_addr) | |
1da177e4 | 2685 | { |
298cf9be | 2686 | struct mii_bus *bus = mp->shared->smi->smi_bus; |
ed94493f LB |
2687 | struct phy_device *phydev; |
2688 | int start; | |
2689 | int num; | |
2690 | int i; | |
45c5d3bc | 2691 | |
ed94493f LB |
2692 | if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { |
2693 | start = phy_addr_get(mp) & 0x1f; | |
2694 | num = 32; | |
2695 | } else { | |
2696 | start = phy_addr & 0x1f; | |
2697 | num = 1; | |
2698 | } | |
45c5d3bc | 2699 | |
ed94493f LB |
2700 | phydev = NULL; |
2701 | for (i = 0; i < num; i++) { | |
2702 | int addr = (start + i) & 0x1f; | |
fc32b0e2 | 2703 | |
ed94493f LB |
2704 | if (bus->phy_map[addr] == NULL) |
2705 | mdiobus_scan(bus, addr); | |
1da177e4 | 2706 | |
ed94493f LB |
2707 | if (phydev == NULL) { |
2708 | phydev = bus->phy_map[addr]; | |
2709 | if (phydev != NULL) | |
2710 | phy_addr_set(mp, addr); | |
2711 | } | |
2712 | } | |
1da177e4 | 2713 | |
ed94493f | 2714 | return phydev; |
1da177e4 LT |
2715 | } |
2716 | ||
ed94493f | 2717 | static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) |
c28a4f89 | 2718 | { |
ed94493f | 2719 | struct phy_device *phy = mp->phy; |
c28a4f89 | 2720 | |
fc32b0e2 LB |
2721 | phy_reset(mp); |
2722 | ||
db1d7bf7 | 2723 | phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII); |
ed94493f LB |
2724 | |
2725 | if (speed == 0) { | |
2726 | phy->autoneg = AUTONEG_ENABLE; | |
2727 | phy->speed = 0; | |
2728 | phy->duplex = 0; | |
2729 | phy->advertising = phy->supported | ADVERTISED_Autoneg; | |
c9df406f | 2730 | } else { |
ed94493f LB |
2731 | phy->autoneg = AUTONEG_DISABLE; |
2732 | phy->advertising = 0; | |
2733 | phy->speed = speed; | |
2734 | phy->duplex = duplex; | |
c9df406f | 2735 | } |
ed94493f | 2736 | phy_start_aneg(phy); |
c28a4f89 JC |
2737 | } |
2738 | ||
81600eea LB |
2739 | static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) |
2740 | { | |
2741 | u32 pscr; | |
2742 | ||
37a6084f | 2743 | pscr = rdlp(mp, PORT_SERIAL_CONTROL); |
81600eea LB |
2744 | if (pscr & SERIAL_PORT_ENABLE) { |
2745 | pscr &= ~SERIAL_PORT_ENABLE; | |
37a6084f | 2746 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2747 | } |
2748 | ||
2749 | pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; | |
ed94493f | 2750 | if (mp->phy == NULL) { |
81600eea LB |
2751 | pscr |= DISABLE_AUTO_NEG_SPEED_GMII; |
2752 | if (speed == SPEED_1000) | |
2753 | pscr |= SET_GMII_SPEED_TO_1000; | |
2754 | else if (speed == SPEED_100) | |
2755 | pscr |= SET_MII_SPEED_TO_100; | |
2756 | ||
2757 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; | |
2758 | ||
2759 | pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; | |
2760 | if (duplex == DUPLEX_FULL) | |
2761 | pscr |= SET_FULL_DUPLEX_MODE; | |
2762 | } | |
2763 | ||
37a6084f | 2764 | wrlp(mp, PORT_SERIAL_CONTROL, pscr); |
81600eea LB |
2765 | } |
2766 | ||
c9df406f | 2767 | static int mv643xx_eth_probe(struct platform_device *pdev) |
1da177e4 | 2768 | { |
c9df406f | 2769 | struct mv643xx_eth_platform_data *pd; |
e5371493 | 2770 | struct mv643xx_eth_private *mp; |
c9df406f | 2771 | struct net_device *dev; |
c9df406f | 2772 | struct resource *res; |
fc32b0e2 | 2773 | int err; |
1da177e4 | 2774 | |
c9df406f LB |
2775 | pd = pdev->dev.platform_data; |
2776 | if (pd == NULL) { | |
fc32b0e2 LB |
2777 | dev_printk(KERN_ERR, &pdev->dev, |
2778 | "no mv643xx_eth_platform_data\n"); | |
c9df406f LB |
2779 | return -ENODEV; |
2780 | } | |
1da177e4 | 2781 | |
c9df406f | 2782 | if (pd->shared == NULL) { |
fc32b0e2 LB |
2783 | dev_printk(KERN_ERR, &pdev->dev, |
2784 | "no mv643xx_eth_platform_data->shared\n"); | |
c9df406f LB |
2785 | return -ENODEV; |
2786 | } | |
8f518703 | 2787 | |
e5ef1de1 | 2788 | dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); |
c9df406f LB |
2789 | if (!dev) |
2790 | return -ENOMEM; | |
1da177e4 | 2791 | |
c9df406f | 2792 | mp = netdev_priv(dev); |
fc32b0e2 LB |
2793 | platform_set_drvdata(pdev, mp); |
2794 | ||
2795 | mp->shared = platform_get_drvdata(pd->shared); | |
37a6084f | 2796 | mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); |
fc32b0e2 LB |
2797 | mp->port_num = pd->port_number; |
2798 | ||
c9df406f | 2799 | mp->dev = dev; |
78fff83b | 2800 | |
fc32b0e2 | 2801 | set_params(mp, pd); |
e5ef1de1 | 2802 | dev->real_num_tx_queues = mp->txq_count; |
fc32b0e2 | 2803 | |
ed94493f LB |
2804 | if (pd->phy_addr != MV643XX_ETH_PHY_NONE) |
2805 | mp->phy = phy_scan(mp, pd->phy_addr); | |
bedfe324 | 2806 | |
6bdf576e | 2807 | if (mp->phy != NULL) |
ed94493f | 2808 | phy_init(mp, pd->speed, pd->duplex); |
6bdf576e LB |
2809 | |
2810 | SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); | |
ed94493f | 2811 | |
81600eea | 2812 | init_pscr(mp, pd->speed, pd->duplex); |
fc32b0e2 | 2813 | |
4ff3495a LB |
2814 | |
2815 | mib_counters_clear(mp); | |
2816 | ||
2817 | init_timer(&mp->mib_counters_timer); | |
2818 | mp->mib_counters_timer.data = (unsigned long)mp; | |
2819 | mp->mib_counters_timer.function = mib_counters_timer_wrapper; | |
2820 | mp->mib_counters_timer.expires = jiffies + 30 * HZ; | |
2821 | add_timer(&mp->mib_counters_timer); | |
2822 | ||
2823 | spin_lock_init(&mp->mib_counters_lock); | |
2824 | ||
2825 | INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); | |
2826 | ||
2257e05c LB |
2827 | netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128); |
2828 | ||
2829 | init_timer(&mp->rx_oom); | |
2830 | mp->rx_oom.data = (unsigned long)mp; | |
2831 | mp->rx_oom.function = oom_timer_wrapper; | |
2832 | ||
fc32b0e2 | 2833 | |
c9df406f LB |
2834 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
2835 | BUG_ON(!res); | |
2836 | dev->irq = res->start; | |
1da177e4 | 2837 | |
8fd89211 | 2838 | dev->get_stats = mv643xx_eth_get_stats; |
fc32b0e2 | 2839 | dev->hard_start_xmit = mv643xx_eth_xmit; |
c9df406f LB |
2840 | dev->open = mv643xx_eth_open; |
2841 | dev->stop = mv643xx_eth_stop; | |
66e63ffb | 2842 | dev->set_rx_mode = mv643xx_eth_set_rx_mode; |
fc32b0e2 LB |
2843 | dev->set_mac_address = mv643xx_eth_set_mac_address; |
2844 | dev->do_ioctl = mv643xx_eth_ioctl; | |
2845 | dev->change_mtu = mv643xx_eth_change_mtu; | |
c9df406f | 2846 | dev->tx_timeout = mv643xx_eth_tx_timeout; |
c9df406f | 2847 | #ifdef CONFIG_NET_POLL_CONTROLLER |
e5371493 | 2848 | dev->poll_controller = mv643xx_eth_netpoll; |
c9df406f | 2849 | #endif |
c9df406f LB |
2850 | dev->watchdog_timeo = 2 * HZ; |
2851 | dev->base_addr = 0; | |
1da177e4 | 2852 | |
c9df406f | 2853 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; |
e32b6617 | 2854 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM; |
1da177e4 | 2855 | |
fc32b0e2 | 2856 | SET_NETDEV_DEV(dev, &pdev->dev); |
8f518703 | 2857 | |
c9df406f | 2858 | if (mp->shared->win_protect) |
fc32b0e2 | 2859 | wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); |
1da177e4 | 2860 | |
c9df406f LB |
2861 | err = register_netdev(dev); |
2862 | if (err) | |
2863 | goto out; | |
1da177e4 | 2864 | |
e174961c JB |
2865 | dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n", |
2866 | mp->port_num, dev->dev_addr); | |
1da177e4 | 2867 | |
13d64285 | 2868 | if (mp->tx_desc_sram_size > 0) |
fc32b0e2 | 2869 | dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n"); |
1da177e4 | 2870 | |
c9df406f | 2871 | return 0; |
1da177e4 | 2872 | |
c9df406f LB |
2873 | out: |
2874 | free_netdev(dev); | |
1da177e4 | 2875 | |
c9df406f | 2876 | return err; |
1da177e4 LT |
2877 | } |
2878 | ||
c9df406f | 2879 | static int mv643xx_eth_remove(struct platform_device *pdev) |
1da177e4 | 2880 | { |
fc32b0e2 | 2881 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
1da177e4 | 2882 | |
fc32b0e2 | 2883 | unregister_netdev(mp->dev); |
ed94493f LB |
2884 | if (mp->phy != NULL) |
2885 | phy_detach(mp->phy); | |
c9df406f | 2886 | flush_scheduled_work(); |
fc32b0e2 | 2887 | free_netdev(mp->dev); |
c9df406f | 2888 | |
c9df406f | 2889 | platform_set_drvdata(pdev, NULL); |
fc32b0e2 | 2890 | |
c9df406f | 2891 | return 0; |
1da177e4 LT |
2892 | } |
2893 | ||
c9df406f | 2894 | static void mv643xx_eth_shutdown(struct platform_device *pdev) |
d0412d96 | 2895 | { |
fc32b0e2 | 2896 | struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); |
d0412d96 | 2897 | |
c9df406f | 2898 | /* Mask all interrupts on ethernet port */ |
37a6084f LB |
2899 | wrlp(mp, INT_MASK, 0); |
2900 | rdlp(mp, INT_MASK); | |
c9df406f | 2901 | |
fc32b0e2 LB |
2902 | if (netif_running(mp->dev)) |
2903 | port_reset(mp); | |
d0412d96 JC |
2904 | } |
2905 | ||
c9df406f | 2906 | static struct platform_driver mv643xx_eth_driver = { |
fc32b0e2 LB |
2907 | .probe = mv643xx_eth_probe, |
2908 | .remove = mv643xx_eth_remove, | |
2909 | .shutdown = mv643xx_eth_shutdown, | |
c9df406f | 2910 | .driver = { |
fc32b0e2 | 2911 | .name = MV643XX_ETH_NAME, |
c9df406f LB |
2912 | .owner = THIS_MODULE, |
2913 | }, | |
2914 | }; | |
2915 | ||
e5371493 | 2916 | static int __init mv643xx_eth_init_module(void) |
d0412d96 | 2917 | { |
c9df406f | 2918 | int rc; |
d0412d96 | 2919 | |
c9df406f LB |
2920 | rc = platform_driver_register(&mv643xx_eth_shared_driver); |
2921 | if (!rc) { | |
2922 | rc = platform_driver_register(&mv643xx_eth_driver); | |
2923 | if (rc) | |
2924 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
2925 | } | |
fc32b0e2 | 2926 | |
c9df406f | 2927 | return rc; |
d0412d96 | 2928 | } |
fc32b0e2 | 2929 | module_init(mv643xx_eth_init_module); |
d0412d96 | 2930 | |
e5371493 | 2931 | static void __exit mv643xx_eth_cleanup_module(void) |
d0412d96 | 2932 | { |
c9df406f LB |
2933 | platform_driver_unregister(&mv643xx_eth_driver); |
2934 | platform_driver_unregister(&mv643xx_eth_shared_driver); | |
d0412d96 | 2935 | } |
e5371493 | 2936 | module_exit(mv643xx_eth_cleanup_module); |
1da177e4 | 2937 | |
45675bc6 LB |
2938 | MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " |
2939 | "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); | |
c9df406f | 2940 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); |
fc32b0e2 | 2941 | MODULE_LICENSE("GPL"); |
c9df406f | 2942 | MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); |
fc32b0e2 | 2943 | MODULE_ALIAS("platform:" MV643XX_ETH_NAME); |