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mv643xx_eth: general cleanup
[deliverable/linux.git] / drivers / net / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/dma-mapping.h>
b6298c22 40#include <linux/in.h>
1da177e4
LT		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/etherdevice.h>
1da177e4
LT		 44#include <linux/delay.h>
45#include <linux/ethtool.h>
d052d1be 46#include <linux/platform_device.h>
fbd6a754
LB		 47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/spinlock.h>
50#include <linux/workqueue.h>
51#include <linux/mii.h>
fbd6a754 52#include <linux/mv643xx_eth.h>
1da177e4
LT		 53#include <asm/io.h>
54#include <asm/types.h>
1da177e4 55#include <asm/system.h>
fbd6a754 56
e5371493
LB		 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58static char mv643xx_eth_driver_version[] = "1.0";
c9df406f 59
e5371493
LB		 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI
62#define MV643XX_ETH_TX_FAST_REFILL
fbd6a754 63
e5371493 64#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
fbd6a754
LB		 65#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
66#else
67#define MAX_DESCS_PER_SKB 1
68#endif
69
fbd6a754
LB		 70/*
71 * Registers shared between all ports.
72 */
3cb4667c
LB		 73#define PHY_ADDR 0x0000
74#define SMI_REG 0x0004
75#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78#define WINDOW_BAR_ENABLE 0x0290
79#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 80
81/*
82 * Per-port registers.
83 */
3cb4667c 84#define PORT_CONFIG(p) (0x0400 + ((p) << 10))
d9a073ea 85#define UNICAST_PROMISCUOUS_MODE 0x00000001
3cb4667c
LB		 86#define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89#define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
a2a41689 92#define TX_FIFO_EMPTY 0x00000400
3cb4667c
LB		 93#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
94#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
95#define INT_CAUSE(p) (0x0460 + ((p) << 10))
073a345c
LB		 96#define INT_RX 0x00000804
97#define INT_EXT 0x00000002
3cb4667c 98#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
073a345c
LB		 99#define INT_EXT_LINK 0x00100000
100#define INT_EXT_PHY 0x00010000
101#define INT_EXT_TX_ERROR_0 0x00000100
102#define INT_EXT_TX_0 0x00000001
103#define INT_EXT_TX 0x00000101
3cb4667c
LB		 104#define INT_MASK(p) (0x0468 + ((p) << 10))
105#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
106#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
107#define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
108#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
109#define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
110#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
111#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
112#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
113#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 114
2679a550
LB		 115
116/*
117 * SDMA configuration register.
118 */
fbd6a754 119#define RX_BURST_SIZE_4_64BIT (2 << 1)
fbd6a754 120#define BLM_RX_NO_SWAP (1 << 4)
fbd6a754 121#define BLM_TX_NO_SWAP (1 << 5)
fbd6a754 122#define TX_BURST_SIZE_4_64BIT (2 << 22)
fbd6a754
LB		 123
124#if defined(__BIG_ENDIAN)
125#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
126 RX_BURST_SIZE_4_64BIT | \
fbd6a754
LB		 127 TX_BURST_SIZE_4_64BIT
128#elif defined(__LITTLE_ENDIAN)
129#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
130 RX_BURST_SIZE_4_64BIT | \
131 BLM_RX_NO_SWAP | \
132 BLM_TX_NO_SWAP | \
fbd6a754
LB		 133 TX_BURST_SIZE_4_64BIT
134#else
135#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
136#endif
137
2beff77b
LB		 138
139/*
140 * Port serial control register.
141 */
142#define SET_MII_SPEED_TO_100 (1 << 24)
143#define SET_GMII_SPEED_TO_1000 (1 << 23)
144#define SET_FULL_DUPLEX_MODE (1 << 21)
fbd6a754 145#define MAX_RX_PACKET_1522BYTE (1 << 17)
fbd6a754
LB		 146#define MAX_RX_PACKET_9700BYTE (5 << 17)
147#define MAX_RX_PACKET_MASK (7 << 17)
2beff77b
LB		 148#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
149#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
150#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
151#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
152#define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
153#define FORCE_LINK_PASS (1 << 1)
154#define SERIAL_PORT_ENABLE (1 << 0)
fbd6a754 155
cc9754b3
LB		 156#define DEFAULT_RX_QUEUE_SIZE 400
157#define DEFAULT_TX_QUEUE_SIZE 800
fbd6a754 158
fbd6a754 159
7ca72a3b
LB		 160/*
161 * RX/TX descriptors.
fbd6a754
LB		 162 */
163#if defined(__BIG_ENDIAN)
cc9754b3 164struct rx_desc {
fbd6a754
LB		 165 u16 byte_cnt; /* Descriptor buffer byte count */
166 u16 buf_size; /* Buffer size */
167 u32 cmd_sts; /* Descriptor command status */
168 u32 next_desc_ptr; /* Next descriptor pointer */
169 u32 buf_ptr; /* Descriptor buffer pointer */
170};
171
cc9754b3 172struct tx_desc {
fbd6a754
LB		 173 u16 byte_cnt; /* buffer byte count */
174 u16 l4i_chk; /* CPU provided TCP checksum */
175 u32 cmd_sts; /* Command/status field */
176 u32 next_desc_ptr; /* Pointer to next descriptor */
177 u32 buf_ptr; /* pointer to buffer for this descriptor*/
178};
179#elif defined(__LITTLE_ENDIAN)
cc9754b3 180struct rx_desc {
fbd6a754
LB		 181 u32 cmd_sts; /* Descriptor command status */
182 u16 buf_size; /* Buffer size */
183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u32 buf_ptr; /* Descriptor buffer pointer */
185 u32 next_desc_ptr; /* Next descriptor pointer */
186};
187
cc9754b3 188struct tx_desc {
fbd6a754
LB		 189 u32 cmd_sts; /* Command/status field */
190 u16 l4i_chk; /* CPU provided TCP checksum */
191 u16 byte_cnt; /* buffer byte count */
192 u32 buf_ptr; /* pointer to buffer for this descriptor*/
193 u32 next_desc_ptr; /* Pointer to next descriptor */
194};
195#else
196#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
197#endif
198
7ca72a3b 199/* RX & TX descriptor command */
cc9754b3 200#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 201
202/* RX & TX descriptor status */
cc9754b3 203#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 204
205/* RX descriptor status */
cc9754b3
LB		 206#define LAYER_4_CHECKSUM_OK 0x40000000
207#define RX_ENABLE_INTERRUPT 0x20000000
208#define RX_FIRST_DESC 0x08000000
209#define RX_LAST_DESC 0x04000000
7ca72a3b
LB		 210
211/* TX descriptor command */
cc9754b3
LB		 212#define TX_ENABLE_INTERRUPT 0x00800000
213#define GEN_CRC 0x00400000
214#define TX_FIRST_DESC 0x00200000
215#define TX_LAST_DESC 0x00100000
216#define ZERO_PADDING 0x00080000
217#define GEN_IP_V4_CHECKSUM 0x00040000
218#define GEN_TCP_UDP_CHECKSUM 0x00020000
219#define UDP_FRAME 0x00010000
7ca72a3b 220
cc9754b3 221#define TX_IHL_SHIFT 11
7ca72a3b
LB		 222
223
c9df406f 224/* global *******************************************************************/
e5371493 225struct mv643xx_eth_shared_private {
fc32b0e2
LB		 226 /*
227 * Ethernet controller base address.
228 */
cc9754b3 229 void __iomem *base;
c9df406f 230
fc32b0e2
LB		 231 /*
232 * Protects access to SMI_REG, which is shared between ports.
233 */
c9df406f
LB		 234 spinlock_t phy_lock;
235
fc32b0e2
LB		 236 /*
237 * Per-port MBUS window access register value.
238 */
c9df406f
LB		 239 u32 win_protect;
240
fc32b0e2
LB		 241 /*
242 * Hardware-specific parameters.
243 */
c9df406f
LB		 244 unsigned int t_clk;
245};
246
247
248/* per-port *****************************************************************/
e5371493 249struct mib_counters {
fbd6a754
LB		 250 u64 good_octets_received;
251 u32 bad_octets_received;
252 u32 internal_mac_transmit_err;
253 u32 good_frames_received;
254 u32 bad_frames_received;
255 u32 broadcast_frames_received;
256 u32 multicast_frames_received;
257 u32 frames_64_octets;
258 u32 frames_65_to_127_octets;
259 u32 frames_128_to_255_octets;
260 u32 frames_256_to_511_octets;
261 u32 frames_512_to_1023_octets;
262 u32 frames_1024_to_max_octets;
263 u64 good_octets_sent;
264 u32 good_frames_sent;
265 u32 excessive_collision;
266 u32 multicast_frames_sent;
267 u32 broadcast_frames_sent;
268 u32 unrec_mac_control_received;
269 u32 fc_sent;
270 u32 good_fc_received;
271 u32 bad_fc_received;
272 u32 undersize_received;
273 u32 fragments_received;
274 u32 oversize_received;
275 u32 jabber_received;
276 u32 mac_receive_error;
277 u32 bad_crc_event;
278 u32 collision;
279 u32 late_collision;
280};
281
8a578111
LB		 282struct rx_queue {
283 int rx_ring_size;
284
285 int rx_desc_count;
286 int rx_curr_desc;
287 int rx_used_desc;
288
289 struct rx_desc *rx_desc_area;
290 dma_addr_t rx_desc_dma;
291 int rx_desc_area_size;
292 struct sk_buff **rx_skb;
293
294 struct timer_list rx_oom;
295};
296
13d64285
LB		 297struct tx_queue {
298 int tx_ring_size;
fbd6a754 299
13d64285
LB		 300 int tx_desc_count;
301 int tx_curr_desc;
302 int tx_used_desc;
fbd6a754 303
5daffe94 304 struct tx_desc *tx_desc_area;
fbd6a754
LB		 305 dma_addr_t tx_desc_dma;
306 int tx_desc_area_size;
307 struct sk_buff **tx_skb;
13d64285
LB		 308};
309
310struct mv643xx_eth_private {
311 struct mv643xx_eth_shared_private *shared;
fc32b0e2 312 int port_num;
13d64285 313
fc32b0e2 314 struct net_device *dev;
fbd6a754 315
fc32b0e2
LB		 316 struct mv643xx_eth_shared_private *shared_smi;
317 int phy_addr;
fbd6a754 318
fbd6a754 319 spinlock_t lock;
fbd6a754 320
fc32b0e2
LB		 321 struct mib_counters mib_counters;
322 struct work_struct tx_timeout_task;
fbd6a754 323 struct mii_if_info mii;
8a578111
LB		 324
325 /*
326 * RX state.
327 */
328 int default_rx_ring_size;
329 unsigned long rx_desc_sram_addr;
330 int rx_desc_sram_size;
331 struct napi_struct napi;
332 struct rx_queue rxq[1];
13d64285
LB		 333
334 /*
335 * TX state.
336 */
337 int default_tx_ring_size;
338 unsigned long tx_desc_sram_addr;
339 int tx_desc_sram_size;
340 struct tx_queue txq[1];
341#ifdef MV643XX_ETH_TX_FAST_REFILL
342 int tx_clean_threshold;
343#endif
fbd6a754 344};
1da177e4 345
fbd6a754 346
c9df406f 347/* port register accessors **************************************************/
e5371493 348static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 349{
cc9754b3 350 return readl(mp->shared->base + offset);
c9df406f 351}
fbd6a754 352
e5371493 353static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 354{
cc9754b3 355 writel(data, mp->shared->base + offset);
c9df406f 356}
fbd6a754 357
fbd6a754 358
c9df406f 359/* rxq/txq helper functions *************************************************/
8a578111 360static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 361{
8a578111 362 return container_of(rxq, struct mv643xx_eth_private, rxq[0]);
c9df406f 363}
fbd6a754 364
13d64285
LB		 365static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
366{
367 return container_of(txq, struct mv643xx_eth_private, txq[0]);
368}
369
8a578111 370static void rxq_enable(struct rx_queue *rxq)
c9df406f 371{
8a578111
LB		 372 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
373 wrl(mp, RXQ_COMMAND(mp->port_num), 1);
374}
1da177e4 375
8a578111
LB		 376static void rxq_disable(struct rx_queue *rxq)
377{
378 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
379 u8 mask = 1;
1da177e4 380
8a578111
LB		 381 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
382 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
383 udelay(10);
c9df406f
LB		 384}
385
13d64285 386static void txq_enable(struct tx_queue *txq)
1da177e4 387{
13d64285
LB		 388 struct mv643xx_eth_private *mp = txq_to_mp(txq);
389 wrl(mp, TXQ_COMMAND(mp->port_num), 1);
1da177e4
LT		 390}
391
13d64285 392static void txq_disable(struct tx_queue *txq)
1da177e4 393{
13d64285
LB		 394 struct mv643xx_eth_private *mp = txq_to_mp(txq);
395 u8 mask = 1;
c9df406f 396
13d64285
LB		 397 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
398 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
399 udelay(10);
400}
401
402static void __txq_maybe_wake(struct tx_queue *txq)
403{
404 struct mv643xx_eth_private *mp = txq_to_mp(txq);
405
406 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
407 netif_wake_queue(mp->dev);
1da177e4
LT		 408}
409
c9df406f
LB		 410
411/* rx ***********************************************************************/
13d64285 412static void txq_reclaim(struct tx_queue *txq, int force);
c9df406f 413
8a578111 414static void rxq_refill(struct rx_queue *rxq)
1da177e4 415{
8a578111 416 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
c9df406f 417 unsigned long flags;
1da177e4 418
c9df406f 419 spin_lock_irqsave(&mp->lock, flags);
c0d0f2ca 420
8a578111
LB		 421 while (rxq->rx_desc_count < rxq->rx_ring_size) {
422 int skb_size;
de34f225
LB		 423 struct sk_buff *skb;
424 int unaligned;
425 int rx;
426
8a578111
LB		 427 /*
428 * Reserve 2+14 bytes for an ethernet header (the
429 * hardware automatically prepends 2 bytes of dummy
430 * data to each received packet), 4 bytes for a VLAN
431 * header, and 4 bytes for the trailing FCS -- 24
432 * bytes total.
433 */
434 skb_size = mp->dev->mtu + 24;
435
436 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
de34f225 437 if (skb == NULL)
1da177e4 438 break;
de34f225 439
908b637f 440 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
b44cd572 441 if (unaligned)
908b637f 442 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
de34f225 443
8a578111
LB		 444 rxq->rx_desc_count++;
445 rx = rxq->rx_used_desc;
446 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
de34f225 447
8a578111
LB		 448 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
449 skb_size, DMA_FROM_DEVICE);
450 rxq->rx_desc_area[rx].buf_size = skb_size;
451 rxq->rx_skb[rx] = skb;
de34f225 452 wmb();
8a578111 453 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
de34f225
LB		 454 RX_ENABLE_INTERRUPT;
455 wmb();
456
fc32b0e2
LB		 457 /*
458 * The hardware automatically prepends 2 bytes of
459 * dummy data to each received packet, so that the
460 * IP header ends up 16-byte aligned.
461 */
462 skb_reserve(skb, 2);
1da177e4 463 }
de34f225 464
8a578111
LB		 465 if (rxq->rx_desc_count == 0) {
466 rxq->rx_oom.expires = jiffies + (HZ / 10);
467 add_timer(&rxq->rx_oom);
1da177e4 468 }
de34f225
LB		 469
470 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4
LT		 471}
472
8a578111 473static inline void rxq_refill_timer_wrapper(unsigned long data)
1da177e4 474{
8a578111 475 rxq_refill((struct rx_queue *)data);
1da177e4
LT		 476}
477
8a578111 478static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 479{
8a578111
LB		 480 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
481 struct net_device_stats *stats = &mp->dev->stats;
482 int rx;
1da177e4 483
8a578111
LB		 484 rx = 0;
485 while (rx < budget) {
fc32b0e2 486 struct rx_desc *rx_desc;
96587661 487 unsigned int cmd_sts;
fc32b0e2 488 struct sk_buff *skb;
96587661 489 unsigned long flags;
d344bff9 490
96587661 491 spin_lock_irqsave(&mp->lock, flags);
ff561eef 492
8a578111 493 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 494
96587661
LB		 495 cmd_sts = rx_desc->cmd_sts;
496 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
497 spin_unlock_irqrestore(&mp->lock, flags);
498 break;
499 }
500 rmb();
1da177e4 501
8a578111
LB		 502 skb = rxq->rx_skb[rxq->rx_curr_desc];
503 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 504
8a578111 505 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
ff561eef 506
96587661 507 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 508
fc32b0e2
LB		 509 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
510 mp->dev->mtu + 24, DMA_FROM_DEVICE);
8a578111
LB		 511 rxq->rx_desc_count--;
512 rx++;
b1dd9ca1 513
468d09f8
DF		 514 /*
515 * Update statistics.
fc32b0e2
LB		 516 *
517 * Note that the descriptor byte count includes 2 dummy
518 * bytes automatically inserted by the hardware at the
519 * start of the packet (which we don't count), and a 4
520 * byte CRC at the end of the packet (which we do count).
468d09f8 521 */
1da177e4 522 stats->rx_packets++;
fc32b0e2 523 stats->rx_bytes += rx_desc->byte_cnt - 2;
96587661 524
1da177e4 525 /*
fc32b0e2
LB		 526 * In case we received a packet without first / last bits
527 * on, or the error summary bit is set, the packet needs
528 * to be dropped.
1da177e4 529 */
96587661 530 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 531 (RX_FIRST_DESC | RX_LAST_DESC))
96587661 532 || (cmd_sts & ERROR_SUMMARY)) {
1da177e4 533 stats->rx_dropped++;
fc32b0e2 534
96587661 535 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
cc9754b3 536 (RX_FIRST_DESC | RX_LAST_DESC)) {
1da177e4 537 if (net_ratelimit())
fc32b0e2
LB		 538 dev_printk(KERN_ERR, &mp->dev->dev,
539 "received packet spanning "
540 "multiple descriptors\n");
1da177e4 541 }
fc32b0e2 542
96587661 543 if (cmd_sts & ERROR_SUMMARY)
1da177e4
LT		 544 stats->rx_errors++;
545
546 dev_kfree_skb_irq(skb);
547 } else {
548 /*
549 * The -4 is for the CRC in the trailer of the
550 * received packet
551 */
fc32b0e2 552 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
1da177e4 553
96587661 554 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
1da177e4
LT		 555 skb->ip_summed = CHECKSUM_UNNECESSARY;
556 skb->csum = htons(
96587661 557 (cmd_sts & 0x0007fff8) >> 3);
1da177e4 558 }
8a578111 559 skb->protocol = eth_type_trans(skb, mp->dev);
e5371493 560#ifdef MV643XX_ETH_NAPI
1da177e4
LT		 561 netif_receive_skb(skb);
562#else
563 netif_rx(skb);
564#endif
565 }
fc32b0e2 566
8a578111 567 mp->dev->last_rx = jiffies;
1da177e4 568 }
fc32b0e2 569
8a578111 570 rxq_refill(rxq);
1da177e4 571
8a578111 572 return rx;
1da177e4
LT		 573}
574
e5371493 575#ifdef MV643XX_ETH_NAPI
e5371493 576static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
d0412d96 577{
8a578111
LB		 578 struct mv643xx_eth_private *mp;
579 int rx;
580
581 mp = container_of(napi, struct mv643xx_eth_private, napi);
d0412d96 582
e5371493 583#ifdef MV643XX_ETH_TX_FAST_REFILL
c9df406f 584 if (++mp->tx_clean_threshold > 5) {
13d64285 585 txq_reclaim(mp->txq, 0);
c9df406f 586 mp->tx_clean_threshold = 0;
d0412d96 587 }
c9df406f 588#endif
d0412d96 589
8a578111 590 rx = rxq_process(mp->rxq, budget);
d0412d96 591
8a578111
LB		 592 if (rx < budget) {
593 netif_rx_complete(mp->dev, napi);
594 wrl(mp, INT_CAUSE(mp->port_num), 0);
595 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
596 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
d0412d96 597 }
c9df406f 598
8a578111 599 return rx;
d0412d96 600}
c9df406f 601#endif
d0412d96 602
c9df406f
LB		 603
604/* tx ***********************************************************************/
c9df406f 605static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 606{
13d64285 607 int frag;
1da177e4 608
c9df406f 609 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
13d64285
LB		 610 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
611 if (fragp->size <= 8 && fragp->page_offset & 7)
c9df406f 612 return 1;
1da177e4 613 }
13d64285 614
c9df406f
LB		 615 return 0;
616}
7303fde8 617
13d64285 618static int txq_alloc_desc_index(struct tx_queue *txq)
c9df406f
LB		 619{
620 int tx_desc_curr;
d0412d96 621
13d64285 622 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
1da177e4 623
13d64285
LB		 624 tx_desc_curr = txq->tx_curr_desc;
625 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
e4d00fa9 626
13d64285 627 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
468d09f8 628
c9df406f
LB		 629 return tx_desc_curr;
630}
468d09f8 631
13d64285 632static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 633{
13d64285 634 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 635 int frag;
1da177e4 636
13d64285
LB		 637 for (frag = 0; frag < nr_frags; frag++) {
638 skb_frag_t *this_frag;
639 int tx_index;
640 struct tx_desc *desc;
641
642 this_frag = &skb_shinfo(skb)->frags[frag];
643 tx_index = txq_alloc_desc_index(txq);
644 desc = &txq->tx_desc_area[tx_index];
645
646 /*
647 * The last fragment will generate an interrupt
648 * which will free the skb on TX completion.
649 */
650 if (frag == nr_frags - 1) {
651 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
652 ZERO_PADDING | TX_LAST_DESC |
653 TX_ENABLE_INTERRUPT;
654 txq->tx_skb[tx_index] = skb;
655 } else {
656 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
657 txq->tx_skb[tx_index] = NULL;
658 }
659
c9df406f
LB		 660 desc->l4i_chk = 0;
661 desc->byte_cnt = this_frag->size;
662 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
663 this_frag->page_offset,
664 this_frag->size,
665 DMA_TO_DEVICE);
666 }
1da177e4
LT		 667}
668
c9df406f
LB		 669static inline __be16 sum16_as_be(__sum16 sum)
670{
671 return (__force __be16)sum;
672}
1da177e4 673
13d64285 674static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 675{
13d64285 676 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 677 int tx_index;
cc9754b3 678 struct tx_desc *desc;
c9df406f
LB		 679 u32 cmd_sts;
680 int length;
1da177e4 681
cc9754b3 682 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
1da177e4 683
13d64285
LB		 684 tx_index = txq_alloc_desc_index(txq);
685 desc = &txq->tx_desc_area[tx_index];
c9df406f
LB		 686
687 if (nr_frags) {
13d64285 688 txq_submit_frag_skb(txq, skb);
c9df406f
LB		 689
690 length = skb_headlen(skb);
13d64285 691 txq->tx_skb[tx_index] = NULL;
c9df406f 692 } else {
cc9754b3 693 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
c9df406f 694 length = skb->len;
13d64285 695 txq->tx_skb[tx_index] = skb;
c9df406f
LB		 696 }
697
698 desc->byte_cnt = length;
699 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
700
701 if (skb->ip_summed == CHECKSUM_PARTIAL) {
702 BUG_ON(skb->protocol != htons(ETH_P_IP));
703
cc9754b3
LB		 704 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
705 GEN_IP_V4_CHECKSUM |
706 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
c9df406f
LB		 707
708 switch (ip_hdr(skb)->protocol) {
709 case IPPROTO_UDP:
cc9754b3 710 cmd_sts |= UDP_FRAME;
c9df406f
LB		 711 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
712 break;
713 case IPPROTO_TCP:
714 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
715 break;
716 default:
717 BUG();
718 }
719 } else {
720 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 721 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 722 desc->l4i_chk = 0;
723 }
724
725 /* ensure all other descriptors are written before first cmd_sts */
726 wmb();
727 desc->cmd_sts = cmd_sts;
728
729 /* ensure all descriptors are written before poking hardware */
730 wmb();
13d64285 731 txq_enable(txq);
c9df406f 732
13d64285 733 txq->tx_desc_count += nr_frags + 1;
1da177e4 734}
1da177e4 735
fc32b0e2 736static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 737{
e5371493 738 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 739 struct net_device_stats *stats = &dev->stats;
13d64285 740 struct tx_queue *txq;
c9df406f 741 unsigned long flags;
afdb57a2 742
c9df406f 743 BUG_ON(netif_queue_stopped(dev));
afdb57a2 744
c9df406f
LB		 745 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
746 stats->tx_dropped++;
fc32b0e2
LB		 747 dev_printk(KERN_DEBUG, &dev->dev,
748 "failed to linearize skb with tiny "
749 "unaligned fragment\n");
c9df406f
LB		 750 return NETDEV_TX_BUSY;
751 }
752
753 spin_lock_irqsave(&mp->lock, flags);
754
13d64285
LB		 755 txq = mp->txq;
756
757 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
c9df406f
LB		 758 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
759 netif_stop_queue(dev);
760 spin_unlock_irqrestore(&mp->lock, flags);
761 return NETDEV_TX_BUSY;
762 }
763
13d64285 764 txq_submit_skb(txq, skb);
c9df406f
LB		 765 stats->tx_bytes += skb->len;
766 stats->tx_packets++;
767 dev->trans_start = jiffies;
768
13d64285 769 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB)
c9df406f
LB		 770 netif_stop_queue(dev);
771
772 spin_unlock_irqrestore(&mp->lock, flags);
773
774 return NETDEV_TX_OK;
1da177e4
LT		 775}
776
c9df406f
LB		 777
778/* mii management interface *************************************************/
fc32b0e2
LB		 779#define SMI_BUSY 0x10000000
780#define SMI_READ_VALID 0x08000000
781#define SMI_OPCODE_READ 0x04000000
782#define SMI_OPCODE_WRITE 0x00000000
c9df406f 783
fc32b0e2
LB		 784static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
785 unsigned int reg, unsigned int *value)
1da177e4 786{
cc9754b3 787 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 788 unsigned long flags;
1da177e4
LT		 789 int i;
790
c9df406f
LB		 791 /* the SMI register is a shared resource */
792 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
793
794 /* wait for the SMI register to become available */
cc9754b3 795 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 796 if (i == 1000) {
c9df406f
LB		 797 printk("%s: PHY busy timeout\n", mp->dev->name);
798 goto out;
799 }
e1bea50a 800 udelay(10);
1da177e4
LT		 801 }
802
fc32b0e2 803 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 804
c9df406f 805 /* now wait for the data to be valid */
cc9754b3 806 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
e1bea50a 807 if (i == 1000) {
c9df406f
LB		 808 printk("%s: PHY read timeout\n", mp->dev->name);
809 goto out;
810 }
e1bea50a 811 udelay(10);
c9df406f
LB		 812 }
813
814 *value = readl(smi_reg) & 0xffff;
815out:
816 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1da177e4
LT		 817}
818
fc32b0e2
LB		 819static void smi_reg_write(struct mv643xx_eth_private *mp,
820 unsigned int addr,
821 unsigned int reg, unsigned int value)
1da177e4 822{
cc9754b3 823 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
c9df406f 824 unsigned long flags;
1da177e4
LT		 825 int i;
826
c9df406f
LB		 827 /* the SMI register is a shared resource */
828 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
829
830 /* wait for the SMI register to become available */
cc9754b3 831 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
e1bea50a 832 if (i == 1000) {
c9df406f
LB		 833 printk("%s: PHY busy timeout\n", mp->dev->name);
834 goto out;
835 }
e1bea50a 836 udelay(10);
1da177e4
LT		 837 }
838
fc32b0e2
LB		 839 writel(SMI_OPCODE_WRITE | (reg << 21) |
840 (addr << 16) | (value & 0xffff), smi_reg);
c9df406f
LB		 841out:
842 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
843}
1da177e4 844
c9df406f
LB		 845
846/* mib counters *************************************************************/
fc32b0e2 847static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 848{
fc32b0e2 849 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 850}
851
fc32b0e2 852static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 853{
fc32b0e2
LB		 854 int i;
855
856 for (i = 0; i < 0x80; i += 4)
857 mib_read(mp, i);
c9df406f 858}
d0412d96 859
fc32b0e2 860static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 861{
e5371493 862 struct mib_counters *p = &mp->mib_counters;
4b8e3655 863
fc32b0e2
LB		 864 p->good_octets_received += mib_read(mp, 0x00);
865 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
866 p->bad_octets_received += mib_read(mp, 0x08);
867 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
868 p->good_frames_received += mib_read(mp, 0x10);
869 p->bad_frames_received += mib_read(mp, 0x14);
870 p->broadcast_frames_received += mib_read(mp, 0x18);
871 p->multicast_frames_received += mib_read(mp, 0x1c);
872 p->frames_64_octets += mib_read(mp, 0x20);
873 p->frames_65_to_127_octets += mib_read(mp, 0x24);
874 p->frames_128_to_255_octets += mib_read(mp, 0x28);
875 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
876 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
877 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
878 p->good_octets_sent += mib_read(mp, 0x38);
879 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
880 p->good_frames_sent += mib_read(mp, 0x40);
881 p->excessive_collision += mib_read(mp, 0x44);
882 p->multicast_frames_sent += mib_read(mp, 0x48);
883 p->broadcast_frames_sent += mib_read(mp, 0x4c);
884 p->unrec_mac_control_received += mib_read(mp, 0x50);
885 p->fc_sent += mib_read(mp, 0x54);
886 p->good_fc_received += mib_read(mp, 0x58);
887 p->bad_fc_received += mib_read(mp, 0x5c);
888 p->undersize_received += mib_read(mp, 0x60);
889 p->fragments_received += mib_read(mp, 0x64);
890 p->oversize_received += mib_read(mp, 0x68);
891 p->jabber_received += mib_read(mp, 0x6c);
892 p->mac_receive_error += mib_read(mp, 0x70);
893 p->bad_crc_event += mib_read(mp, 0x74);
894 p->collision += mib_read(mp, 0x78);
895 p->late_collision += mib_read(mp, 0x7c);
d0412d96
JC		 896}
897
c9df406f
LB		 898
899/* ethtool ******************************************************************/
e5371493 900struct mv643xx_eth_stats {
c9df406f
LB		 901 char stat_string[ETH_GSTRING_LEN];
902 int sizeof_stat;
16820054
LB		 903 int netdev_off;
904 int mp_off;
c9df406f
LB		 905};
906
16820054
LB		 907#define SSTAT(m) \
908 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
909 offsetof(struct net_device, stats.m), -1 }
910
911#define MIBSTAT(m) \
912 { #m, FIELD_SIZEOF(struct mib_counters, m), \
913 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
914
915static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
916 SSTAT(rx_packets),
917 SSTAT(tx_packets),
918 SSTAT(rx_bytes),
919 SSTAT(tx_bytes),
920 SSTAT(rx_errors),
921 SSTAT(tx_errors),
922 SSTAT(rx_dropped),
923 SSTAT(tx_dropped),
924 MIBSTAT(good_octets_received),
925 MIBSTAT(bad_octets_received),
926 MIBSTAT(internal_mac_transmit_err),
927 MIBSTAT(good_frames_received),
928 MIBSTAT(bad_frames_received),
929 MIBSTAT(broadcast_frames_received),
930 MIBSTAT(multicast_frames_received),
931 MIBSTAT(frames_64_octets),
932 MIBSTAT(frames_65_to_127_octets),
933 MIBSTAT(frames_128_to_255_octets),
934 MIBSTAT(frames_256_to_511_octets),
935 MIBSTAT(frames_512_to_1023_octets),
936 MIBSTAT(frames_1024_to_max_octets),
937 MIBSTAT(good_octets_sent),
938 MIBSTAT(good_frames_sent),
939 MIBSTAT(excessive_collision),
940 MIBSTAT(multicast_frames_sent),
941 MIBSTAT(broadcast_frames_sent),
942 MIBSTAT(unrec_mac_control_received),
943 MIBSTAT(fc_sent),
944 MIBSTAT(good_fc_received),
945 MIBSTAT(bad_fc_received),
946 MIBSTAT(undersize_received),
947 MIBSTAT(fragments_received),
948 MIBSTAT(oversize_received),
949 MIBSTAT(jabber_received),
950 MIBSTAT(mac_receive_error),
951 MIBSTAT(bad_crc_event),
952 MIBSTAT(collision),
953 MIBSTAT(late_collision),
c9df406f
LB		 954};
955
e5371493 956static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
d0412d96 957{
e5371493 958 struct mv643xx_eth_private *mp = netdev_priv(dev);
d0412d96
JC		 959 int err;
960
961 spin_lock_irq(&mp->lock);
962 err = mii_ethtool_gset(&mp->mii, cmd);
963 spin_unlock_irq(&mp->lock);
964
fc32b0e2
LB		 965 /*
966 * The MAC does not support 1000baseT_Half.
967 */
d0412d96
JC		 968 cmd->supported &= ~SUPPORTED_1000baseT_Half;
969 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
970
971 return err;
972}
973
e5371493 974static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 975{
e5371493 976 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6
DF		 977 int err;
978
fc32b0e2
LB		 979 /*
980 * The MAC does not support 1000baseT_Half.
981 */
982 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
983
c9df406f
LB		 984 spin_lock_irq(&mp->lock);
985 err = mii_ethtool_sset(&mp->mii, cmd);
986 spin_unlock_irq(&mp->lock);
85cf572c 987
c9df406f
LB		 988 return err;
989}
1da177e4 990
fc32b0e2
LB		 991static void mv643xx_eth_get_drvinfo(struct net_device *dev,
992 struct ethtool_drvinfo *drvinfo)
c9df406f 993{
e5371493
LB		 994 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
995 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
c9df406f 996 strncpy(drvinfo->fw_version, "N/A", 32);
fc32b0e2 997 strncpy(drvinfo->bus_info, "platform", 32);
16820054 998 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 999}
1da177e4 1000
fc32b0e2 1001static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1002{
e5371493 1003 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1004
c9df406f
LB		 1005 return mii_nway_restart(&mp->mii);
1006}
1da177e4 1007
c9df406f
LB		 1008static u32 mv643xx_eth_get_link(struct net_device *dev)
1009{
e5371493 1010 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1011
c9df406f
LB		 1012 return mii_link_ok(&mp->mii);
1013}
1da177e4 1014
fc32b0e2
LB		 1015static void mv643xx_eth_get_strings(struct net_device *dev,
1016 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1017{
1018 int i;
1da177e4 1019
fc32b0e2
LB		 1020 if (stringset == ETH_SS_STATS) {
1021 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1022 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1023 mv643xx_eth_stats[i].stat_string,
e5371493 1024 ETH_GSTRING_LEN);
c9df406f 1025 }
c9df406f
LB		 1026 }
1027}
1da177e4 1028
fc32b0e2
LB		 1029static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1030 struct ethtool_stats *stats,
1031 uint64_t *data)
c9df406f 1032{
fc32b0e2 1033 struct mv643xx_eth_private *mp = dev->priv;
c9df406f 1034 int i;
1da177e4 1035
fc32b0e2 1036 mib_counters_update(mp);
1da177e4 1037
16820054
LB		 1038 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1039 const struct mv643xx_eth_stats *stat;
1040 void *p;
1041
1042 stat = mv643xx_eth_stats + i;
1043
1044 if (stat->netdev_off >= 0)
1045 p = ((void *)mp->dev) + stat->netdev_off;
1046 else
1047 p = ((void *)mp) + stat->mp_off;
1048
1049 data[i] = (stat->sizeof_stat == 8) ?
1050 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1051 }
c9df406f 1052}
1da177e4 1053
fc32b0e2 1054static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1055{
fc32b0e2 1056 if (sset == ETH_SS_STATS)
16820054 1057 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1058
1059 return -EOPNOTSUPP;
c9df406f 1060}
1da177e4 1061
e5371493 1062static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1063 .get_settings = mv643xx_eth_get_settings,
1064 .set_settings = mv643xx_eth_set_settings,
1065 .get_drvinfo = mv643xx_eth_get_drvinfo,
1066 .nway_reset = mv643xx_eth_nway_reset,
1067 .get_link = mv643xx_eth_get_link,
c9df406f 1068 .set_sg = ethtool_op_set_sg,
fc32b0e2
LB		 1069 .get_strings = mv643xx_eth_get_strings,
1070 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1071 .get_sset_count = mv643xx_eth_get_sset_count,
c9df406f 1072};
1da177e4 1073
bea3348e 1074
c9df406f 1075/* address handling *********************************************************/
5daffe94 1076static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1077{
c9df406f
LB		 1078 unsigned int mac_h;
1079 unsigned int mac_l;
1da177e4 1080
fc32b0e2
LB		 1081 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1082 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1da177e4 1083
5daffe94
LB		 1084 addr[0] = (mac_h >> 24) & 0xff;
1085 addr[1] = (mac_h >> 16) & 0xff;
1086 addr[2] = (mac_h >> 8) & 0xff;
1087 addr[3] = mac_h & 0xff;
1088 addr[4] = (mac_l >> 8) & 0xff;
1089 addr[5] = mac_l & 0xff;
c9df406f 1090}
1da177e4 1091
e5371493 1092static void init_mac_tables(struct mv643xx_eth_private *mp)
c9df406f 1093{
fc32b0e2 1094 int i;
1da177e4 1095
fc32b0e2
LB		 1096 for (i = 0; i < 0x100; i += 4) {
1097 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1098 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
c9df406f 1099 }
fc32b0e2
LB		 1100
1101 for (i = 0; i < 0x10; i += 4)
1102 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
c9df406f 1103}
d0412d96 1104
e5371493 1105static void set_filter_table_entry(struct mv643xx_eth_private *mp,
fc32b0e2 1106 int table, unsigned char entry)
c9df406f
LB		 1107{
1108 unsigned int table_reg;
ab4384a6 1109
c9df406f 1110 /* Set "accepts frame bit" at specified table entry */
fc32b0e2
LB		 1111 table_reg = rdl(mp, table + (entry & 0xfc));
1112 table_reg |= 0x01 << (8 * (entry & 3));
1113 wrl(mp, table + (entry & 0xfc), table_reg);
1da177e4
LT		 1114}
1115
5daffe94 1116static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1da177e4 1117{
c9df406f
LB		 1118 unsigned int mac_h;
1119 unsigned int mac_l;
1120 int table;
1da177e4 1121
fc32b0e2
LB		 1122 mac_l = (addr[4] << 8) | addr[5];
1123 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
ff561eef 1124
fc32b0e2
LB		 1125 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1126 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1da177e4 1127
fc32b0e2 1128 table = UNICAST_TABLE(mp->port_num);
5daffe94 1129 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1da177e4
LT		 1130}
1131
fc32b0e2 1132static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1da177e4 1133{
e5371493 1134 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1135
fc32b0e2
LB		 1136 /* +2 is for the offset of the HW addr type */
1137 memcpy(dev->dev_addr, addr + 2, 6);
1138
cc9754b3
LB		 1139 init_mac_tables(mp);
1140 uc_addr_set(mp, dev->dev_addr);
1da177e4
LT		 1141
1142 return 0;
1143}
1144
69876569
LB		 1145static int addr_crc(unsigned char *addr)
1146{
1147 int crc = 0;
1148 int i;
1149
1150 for (i = 0; i < 6; i++) {
1151 int j;
1152
1153 crc = (crc ^ addr[i]) << 8;
1154 for (j = 7; j >= 0; j--) {
1155 if (crc & (0x100 << j))
1156 crc ^= 0x107 << j;
1157 }
1158 }
1159
1160 return crc;
1161}
1162
fc32b0e2 1163static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1da177e4 1164{
fc32b0e2
LB		 1165 struct mv643xx_eth_private *mp = netdev_priv(dev);
1166 u32 port_config;
1167 struct dev_addr_list *addr;
1168 int i;
c8aaea25 1169
fc32b0e2
LB		 1170 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1171 if (dev->flags & IFF_PROMISC)
1172 port_config |= UNICAST_PROMISCUOUS_MODE;
1173 else
1174 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1175 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1da177e4 1176
fc32b0e2
LB		 1177 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1178 int port_num = mp->port_num;
1179 u32 accept = 0x01010101;
c8aaea25 1180
fc32b0e2
LB		 1181 for (i = 0; i < 0x100; i += 4) {
1182 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1183 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1184 }
1185 return;
1186 }
c8aaea25 1187
fc32b0e2
LB		 1188 for (i = 0; i < 0x100; i += 4) {
1189 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1190 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1da177e4
LT		 1191 }
1192
fc32b0e2
LB		 1193 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1194 u8 *a = addr->da_addr;
1195 int table;
324ff2c1 1196
fc32b0e2
LB		 1197 if (addr->da_addrlen != 6)
1198 continue;
1da177e4 1199
fc32b0e2
LB		 1200 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1201 table = SPECIAL_MCAST_TABLE(mp->port_num);
1202 set_filter_table_entry(mp, table, a[5]);
1203 } else {
1204 int crc = addr_crc(a);
1da177e4 1205
fc32b0e2
LB		 1206 table = OTHER_MCAST_TABLE(mp->port_num);
1207 set_filter_table_entry(mp, table, crc);
1208 }
1209 }
c9df406f 1210}
c8aaea25 1211
c8aaea25 1212
c9df406f 1213/* rx/tx queue initialisation ***********************************************/
8a578111 1214static int rxq_init(struct mv643xx_eth_private *mp)
c9df406f 1215{
8a578111
LB		 1216 struct rx_queue *rxq = mp->rxq;
1217 struct rx_desc *rx_desc;
1218 int size;
c9df406f
LB		 1219 int i;
1220
8a578111
LB		 1221 rxq->rx_ring_size = mp->default_rx_ring_size;
1222
1223 rxq->rx_desc_count = 0;
1224 rxq->rx_curr_desc = 0;
1225 rxq->rx_used_desc = 0;
1226
1227 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1228
1229 if (size <= mp->rx_desc_sram_size) {
1230 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1231 mp->rx_desc_sram_size);
1232 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1233 } else {
1234 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1235 &rxq->rx_desc_dma,
1236 GFP_KERNEL);
f7ea3337
PJ		 1237 }
1238
8a578111
LB		 1239 if (rxq->rx_desc_area == NULL) {
1240 dev_printk(KERN_ERR, &mp->dev->dev,
1241 "can't allocate rx ring (%d bytes)\n", size);
1242 goto out;
1243 }
1244 memset(rxq->rx_desc_area, 0, size);
1da177e4 1245
8a578111
LB		 1246 rxq->rx_desc_area_size = size;
1247 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1248 GFP_KERNEL);
1249 if (rxq->rx_skb == NULL) {
1250 dev_printk(KERN_ERR, &mp->dev->dev,
1251 "can't allocate rx skb ring\n");
1252 goto out_free;
1253 }
1254
1255 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1256 for (i = 0; i < rxq->rx_ring_size; i++) {
1257 int nexti = (i + 1) % rxq->rx_ring_size;
1258 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1259 nexti * sizeof(struct rx_desc);
1260 }
1261
1262 init_timer(&rxq->rx_oom);
1263 rxq->rx_oom.data = (unsigned long)rxq;
1264 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1265
1266 return 0;
1267
1268
1269out_free:
1270 if (size <= mp->rx_desc_sram_size)
1271 iounmap(rxq->rx_desc_area);
1272 else
1273 dma_free_coherent(NULL, size,
1274 rxq->rx_desc_area,
1275 rxq->rx_desc_dma);
1276
1277out:
1278 return -ENOMEM;
c9df406f 1279}
c8aaea25 1280
8a578111 1281static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1282{
8a578111
LB		 1283 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1284 int i;
1285
1286 rxq_disable(rxq);
c8aaea25 1287
8a578111 1288 del_timer_sync(&rxq->rx_oom);
c9df406f 1289
8a578111
LB		 1290 for (i = 0; i < rxq->rx_ring_size; i++) {
1291 if (rxq->rx_skb[i]) {
1292 dev_kfree_skb(rxq->rx_skb[i]);
1293 rxq->rx_desc_count--;
1da177e4 1294 }
c8aaea25 1295 }
1da177e4 1296
8a578111
LB		 1297 if (rxq->rx_desc_count) {
1298 dev_printk(KERN_ERR, &mp->dev->dev,
1299 "error freeing rx ring -- %d skbs stuck\n",
1300 rxq->rx_desc_count);
1301 }
1302
1303 if (rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1304 iounmap(rxq->rx_desc_area);
c9df406f 1305 else
8a578111
LB		 1306 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1307 rxq->rx_desc_area, rxq->rx_desc_dma);
1308
1309 kfree(rxq->rx_skb);
c9df406f 1310}
1da177e4 1311
13d64285 1312static int txq_init(struct mv643xx_eth_private *mp)
c9df406f 1313{
13d64285
LB		 1314 struct tx_queue *txq = mp->txq;
1315 struct tx_desc *tx_desc;
1316 int size;
c9df406f 1317 int i;
1da177e4 1318
13d64285
LB		 1319 txq->tx_ring_size = mp->default_tx_ring_size;
1320
1321 txq->tx_desc_count = 0;
1322 txq->tx_curr_desc = 0;
1323 txq->tx_used_desc = 0;
1324
1325 size = txq->tx_ring_size * sizeof(struct tx_desc);
1326
1327 if (size <= mp->tx_desc_sram_size) {
1328 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1329 mp->tx_desc_sram_size);
1330 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1331 } else {
1332 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1333 &txq->tx_desc_dma,
1334 GFP_KERNEL);
1335 }
1336
1337 if (txq->tx_desc_area == NULL) {
1338 dev_printk(KERN_ERR, &mp->dev->dev,
1339 "can't allocate tx ring (%d bytes)\n", size);
1340 goto out;
c9df406f 1341 }
13d64285
LB		 1342 memset(txq->tx_desc_area, 0, size);
1343
1344 txq->tx_desc_area_size = size;
1345 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1346 GFP_KERNEL);
1347 if (txq->tx_skb == NULL) {
1348 dev_printk(KERN_ERR, &mp->dev->dev,
1349 "can't allocate tx skb ring\n");
1350 goto out_free;
1351 }
1352
1353 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1354 for (i = 0; i < txq->tx_ring_size; i++) {
1355 int nexti = (i + 1) % txq->tx_ring_size;
1356 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1357 nexti * sizeof(struct tx_desc);
1358 }
1359
1360 return 0;
1361
c9df406f 1362
13d64285
LB		 1363out_free:
1364 if (size <= mp->tx_desc_sram_size)
1365 iounmap(txq->tx_desc_area);
1366 else
1367 dma_free_coherent(NULL, size,
1368 txq->tx_desc_area,
1369 txq->tx_desc_dma);
c9df406f 1370
13d64285
LB		 1371out:
1372 return -ENOMEM;
c8aaea25 1373}
1da177e4 1374
13d64285 1375static void txq_reclaim(struct tx_queue *txq, int force)
c8aaea25 1376{
13d64285 1377 struct mv643xx_eth_private *mp = txq_to_mp(txq);
c8aaea25 1378 unsigned long flags;
1da177e4 1379
13d64285
LB		 1380 spin_lock_irqsave(&mp->lock, flags);
1381 while (txq->tx_desc_count > 0) {
1382 int tx_index;
1383 struct tx_desc *desc;
1384 u32 cmd_sts;
1385 struct sk_buff *skb;
1386 dma_addr_t addr;
1387 int count;
4d64e718 1388
13d64285
LB		 1389 tx_index = txq->tx_used_desc;
1390 desc = &txq->tx_desc_area[tx_index];
c9df406f 1391 cmd_sts = desc->cmd_sts;
4d64e718 1392
13d64285
LB		 1393 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1394 break;
1da177e4 1395
13d64285
LB		 1396 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1397 txq->tx_desc_count--;
1da177e4 1398
c9df406f
LB		 1399 addr = desc->buf_ptr;
1400 count = desc->byte_cnt;
13d64285
LB		 1401 skb = txq->tx_skb[tx_index];
1402 txq->tx_skb[tx_index] = NULL;
c8aaea25 1403
cc9754b3 1404 if (cmd_sts & ERROR_SUMMARY) {
13d64285
LB		 1405 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1406 mp->dev->stats.tx_errors++;
c9df406f 1407 }
1da177e4 1408
13d64285
LB		 1409 /*
1410 * Drop mp->lock while we free the skb.
1411 */
c9df406f 1412 spin_unlock_irqrestore(&mp->lock, flags);
1da177e4 1413
cc9754b3 1414 if (cmd_sts & TX_FIRST_DESC)
c9df406f
LB		 1415 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1416 else
1417 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
c2e5b352 1418
c9df406f
LB		 1419 if (skb)
1420 dev_kfree_skb_irq(skb);
63c9e549 1421
13d64285 1422 spin_lock_irqsave(&mp->lock, flags);
c9df406f 1423 }
13d64285 1424 spin_unlock_irqrestore(&mp->lock, flags);
c9df406f 1425}
1da177e4 1426
13d64285 1427static void txq_deinit(struct tx_queue *txq)
c9df406f 1428{
13d64285 1429 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 1430
13d64285
LB		 1431 txq_disable(txq);
1432 txq_reclaim(txq, 1);
1da177e4 1433
13d64285 1434 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 1435
13d64285
LB		 1436 if (txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1437 iounmap(txq->tx_desc_area);
c9df406f 1438 else
13d64285
LB		 1439 dma_free_coherent(NULL, txq->tx_desc_area_size,
1440 txq->tx_desc_area, txq->tx_desc_dma);
1441
1442 kfree(txq->tx_skb);
c9df406f 1443}
1da177e4 1444
1da177e4 1445
c9df406f 1446/* netdev ops and related ***************************************************/
fc32b0e2 1447static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
c9df406f 1448{
13d64285
LB		 1449 u32 pscr_o;
1450 u32 pscr_n;
1da177e4 1451
13d64285 1452 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
63c9e549 1453
c9df406f 1454 /* clear speed, duplex and rx buffer size fields */
13d64285
LB		 1455 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1456 SET_GMII_SPEED_TO_1000 |
1457 SET_FULL_DUPLEX_MODE |
1458 MAX_RX_PACKET_MASK);
1da177e4 1459
fc32b0e2 1460 if (speed == SPEED_1000) {
13d64285
LB		 1461 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1462 } else {
fc32b0e2 1463 if (speed == SPEED_100)
13d64285
LB		 1464 pscr_n |= SET_MII_SPEED_TO_100;
1465 pscr_n |= MAX_RX_PACKET_1522BYTE;
c9df406f 1466 }
1da177e4 1467
fc32b0e2 1468 if (duplex == DUPLEX_FULL)
13d64285
LB		 1469 pscr_n |= SET_FULL_DUPLEX_MODE;
1470
1471 if (pscr_n != pscr_o) {
1472 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1473 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
c9df406f 1474 else {
13d64285
LB		 1475 txq_disable(mp->txq);
1476 pscr_o &= ~SERIAL_PORT_ENABLE;
1477 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1478 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1479 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1480 txq_enable(mp->txq);
c9df406f
LB		 1481 }
1482 }
1483}
84dd619e 1484
fc32b0e2 1485static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
c9df406f
LB		 1486{
1487 struct net_device *dev = (struct net_device *)dev_id;
e5371493 1488 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2
LB		 1489 u32 int_cause;
1490 u32 int_cause_ext;
ce4e2e45 1491
13d64285 1492 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & (INT_RX | INT_EXT);
fc32b0e2
LB		 1493 if (int_cause == 0)
1494 return IRQ_NONE;
1495
1496 int_cause_ext = 0;
cc9754b3 1497 if (int_cause & INT_EXT) {
13d64285 1498 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
073a345c 1499 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
13d64285 1500 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
c9df406f 1501 }
1da177e4 1502
fc32b0e2 1503 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
c9df406f 1504 if (mii_link_ok(&mp->mii)) {
13d64285
LB		 1505 struct ethtool_cmd cmd;
1506
c9df406f 1507 mii_ethtool_gset(&mp->mii, &cmd);
fc32b0e2 1508 update_pscr(mp, cmd.speed, cmd.duplex);
13d64285 1509 txq_enable(mp->txq);
c9df406f
LB		 1510 if (!netif_carrier_ok(dev)) {
1511 netif_carrier_on(dev);
13d64285 1512 __txq_maybe_wake(mp->txq);
c9df406f
LB		 1513 }
1514 } else if (netif_carrier_ok(dev)) {
1515 netif_stop_queue(dev);
1516 netif_carrier_off(dev);
1517 }
1518 }
1da177e4 1519
e5371493 1520#ifdef MV643XX_ETH_NAPI
cc9754b3 1521 if (int_cause & INT_RX) {
13d64285 1522 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
13d64285 1523 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1524
c9df406f 1525 netif_rx_schedule(dev, &mp->napi);
84dd619e 1526 }
c9df406f 1527#else
cc9754b3 1528 if (int_cause & INT_RX)
8a578111 1529 rxq_process(mp->rxq, INT_MAX);
c9df406f 1530#endif
fc32b0e2 1531
13d64285
LB		 1532 if (int_cause_ext & INT_EXT_TX) {
1533 txq_reclaim(mp->txq, 0);
1534 __txq_maybe_wake(mp->txq);
1535 }
1da177e4 1536
c9df406f 1537 return IRQ_HANDLED;
1da177e4
LT		 1538}
1539
e5371493 1540static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 1541{
fc32b0e2 1542 unsigned int data;
1da177e4 1543
fc32b0e2
LB		 1544 smi_reg_read(mp, mp->phy_addr, 0, &data);
1545 data |= 0x8000;
1546 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 1547
c9df406f
LB		 1548 do {
1549 udelay(1);
fc32b0e2
LB		 1550 smi_reg_read(mp, mp->phy_addr, 0, &data);
1551 } while (data & 0x8000);
1da177e4
LT		 1552}
1553
fc32b0e2 1554static void port_start(struct mv643xx_eth_private *mp)
1da177e4 1555{
d0412d96
JC		 1556 u32 pscr;
1557 struct ethtool_cmd ethtool_cmd;
8a578111 1558 int i;
1da177e4 1559
8a578111
LB		 1560 /*
1561 * Configure basic link parameters.
1562 */
1563 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1564 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1565 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1566 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1567 DISABLE_AUTO_NEG_SPEED_GMII |
1568 DISABLE_AUTO_NEG_FOR_DUPLEX |
1569 DO_NOT_FORCE_LINK_FAIL |
1570 SERIAL_PORT_CONTROL_RESERVED;
1571 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1572 pscr |= SERIAL_PORT_ENABLE;
1573 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1da177e4 1574
8a578111
LB		 1575 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1576
fc32b0e2 1577 mv643xx_eth_get_settings(mp->dev, &ethtool_cmd);
8a578111 1578 phy_reset(mp);
fc32b0e2 1579 mv643xx_eth_set_settings(mp->dev, &ethtool_cmd);
1da177e4 1580
13d64285
LB		 1581 /*
1582 * Configure TX path and queues.
1583 */
1584 wrl(mp, TX_BW_MTU(mp->port_num), 0);
1585 for (i = 0; i < 1; i++) {
1586 struct tx_queue *txq = mp->txq;
1587 int off = TXQ_CURRENT_DESC_PTR(mp->port_num);
1588 u32 addr;
1589
1590 addr = (u32)txq->tx_desc_dma;
1591 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1592 wrl(mp, off, addr);
1593 }
1594
fc32b0e2
LB		 1595 /*
1596 * Add configured unicast address to address filter table.
1597 */
1598 uc_addr_set(mp, mp->dev->dev_addr);
1da177e4 1599
d9a073ea
LB		 1600 /*
1601 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1602 * frames to RX queue #0.
1603 */
8a578111 1604 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
01999873 1605
376489a2
LB		 1606 /*
1607 * Treat BPDUs as normal multicasts, and disable partition mode.
1608 */
8a578111 1609 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
01999873 1610
8a578111
LB		 1611 /*
1612 * Enable the receive queue.
1613 */
1614 for (i = 0; i < 1; i++) {
1615 struct rx_queue *rxq = mp->rxq;
1616 int off = RXQ_CURRENT_DESC_PTR(mp->port_num);
1617 u32 addr;
1da177e4 1618
8a578111
LB		 1619 addr = (u32)rxq->rx_desc_dma;
1620 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1621 wrl(mp, off, addr);
1da177e4 1622
8a578111
LB		 1623 rxq_enable(rxq);
1624 }
1da177e4
LT		 1625}
1626
ffd86bbe 1627static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1628{
c9df406f 1629 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1630
fc32b0e2
LB		 1631 if (coal > 0x3fff)
1632 coal = 0x3fff;
1633
1634 wrl(mp, SDMA_CONFIG(mp->port_num),
c9df406f 1635 ((coal & 0x3fff) << 8) |
fc32b0e2 1636 (rdl(mp, SDMA_CONFIG(mp->port_num))
c9df406f 1637 & 0xffc000ff));
1da177e4
LT		 1638}
1639
ffd86bbe 1640static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1da177e4 1641{
c9df406f 1642 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1da177e4 1643
fc32b0e2
LB		 1644 if (coal > 0x3fff)
1645 coal = 0x3fff;
1646 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
16e03018
DF		 1647}
1648
c9df406f 1649static int mv643xx_eth_open(struct net_device *dev)
16e03018 1650{
e5371493 1651 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1652 int err;
16e03018 1653
fc32b0e2
LB		 1654 wrl(mp, INT_CAUSE(mp->port_num), 0);
1655 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1656 rdl(mp, INT_CAUSE_EXT(mp->port_num));
c9df406f 1657
fc32b0e2
LB		 1658 err = request_irq(dev->irq, mv643xx_eth_irq,
1659 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1660 dev->name, dev);
c9df406f 1661 if (err) {
fc32b0e2 1662 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
c9df406f 1663 return -EAGAIN;
16e03018
DF		 1664 }
1665
fc32b0e2 1666 init_mac_tables(mp);
16e03018 1667
8a578111
LB		 1668 err = rxq_init(mp);
1669 if (err)
fc32b0e2 1670 goto out;
8a578111
LB		 1671 rxq_refill(mp->rxq);
1672
13d64285
LB		 1673 err = txq_init(mp);
1674 if (err)
fc32b0e2 1675 goto out_free;
16e03018 1676
e5371493 1677#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1678 napi_enable(&mp->napi);
1679#endif
16e03018 1680
fc32b0e2 1681 port_start(mp);
16e03018 1682
ffd86bbe
LB		 1683 set_rx_coal(mp, 0);
1684 set_tx_coal(mp, 0);
16e03018 1685
fc32b0e2
LB		 1686 wrl(mp, INT_MASK_EXT(mp->port_num),
1687 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
16e03018 1688
fc32b0e2 1689 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
16e03018 1690
c9df406f
LB		 1691 return 0;
1692
13d64285 1693
fc32b0e2 1694out_free:
8a578111 1695 rxq_deinit(mp->rxq);
fc32b0e2 1696out:
c9df406f
LB		 1697 free_irq(dev->irq, dev);
1698
1699 return err;
16e03018
DF		 1700}
1701
e5371493 1702static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 1703{
fc32b0e2 1704 unsigned int data;
1da177e4 1705
13d64285 1706 txq_disable(mp->txq);
8a578111 1707 rxq_disable(mp->rxq);
13d64285
LB		 1708 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
1709 udelay(10);
1da177e4 1710
c9df406f 1711 /* Reset the Enable bit in the Configuration Register */
fc32b0e2
LB		 1712 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1713 data &= ~(SERIAL_PORT_ENABLE |
1714 DO_NOT_FORCE_LINK_FAIL |
1715 FORCE_LINK_PASS);
1716 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1da177e4
LT		 1717}
1718
c9df406f 1719static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 1720{
e5371493 1721 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1722
fc32b0e2
LB		 1723 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1724 rdl(mp, INT_MASK(mp->port_num));
1da177e4 1725
e5371493 1726#ifdef MV643XX_ETH_NAPI
c9df406f
LB		 1727 napi_disable(&mp->napi);
1728#endif
1729 netif_carrier_off(dev);
1730 netif_stop_queue(dev);
1da177e4 1731
fc32b0e2
LB		 1732 free_irq(dev->irq, dev);
1733
cc9754b3 1734 port_reset(mp);
fc32b0e2 1735 mib_counters_update(mp);
1da177e4 1736
13d64285 1737 txq_deinit(mp->txq);
8a578111 1738 rxq_deinit(mp->rxq);
1da177e4 1739
c9df406f 1740 return 0;
1da177e4
LT		 1741}
1742
fc32b0e2 1743static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 1744{
e5371493 1745 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1746
c9df406f 1747 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1da177e4
LT		 1748}
1749
c9df406f 1750static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 1751{
fc32b0e2 1752 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 1753 return -EINVAL;
1da177e4 1754
c9df406f
LB		 1755 dev->mtu = new_mtu;
1756 if (!netif_running(dev))
1757 return 0;
1da177e4 1758
c9df406f
LB		 1759 /*
1760 * Stop and then re-open the interface. This will allocate RX
1761 * skbs of the new MTU.
1762 * There is a possible danger that the open will not succeed,
fc32b0e2 1763 * due to memory being full.
c9df406f
LB		 1764 */
1765 mv643xx_eth_stop(dev);
1766 if (mv643xx_eth_open(dev)) {
fc32b0e2
LB		 1767 dev_printk(KERN_ERR, &dev->dev,
1768 "fatal error on re-opening device after "
1769 "MTU change\n");
c9df406f
LB		 1770 }
1771
1772 return 0;
1da177e4
LT		 1773}
1774
fc32b0e2 1775static void tx_timeout_task(struct work_struct *ugly)
1da177e4 1776{
fc32b0e2 1777 struct mv643xx_eth_private *mp;
1da177e4 1778
fc32b0e2
LB		 1779 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
1780 if (netif_running(mp->dev)) {
1781 netif_stop_queue(mp->dev);
c9df406f 1782
fc32b0e2
LB		 1783 port_reset(mp);
1784 port_start(mp);
c9df406f 1785
fc32b0e2
LB		 1786 __txq_maybe_wake(mp->txq);
1787 }
c9df406f
LB		 1788}
1789
c9df406f 1790static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 1791{
e5371493 1792 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1793
fc32b0e2 1794 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
d0412d96 1795
c9df406f 1796 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 1797}
1798
c9df406f 1799#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 1800static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 1801{
fc32b0e2 1802 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1803
fc32b0e2
LB		 1804 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1805 rdl(mp, INT_MASK(mp->port_num));
c9df406f 1806
fc32b0e2 1807 mv643xx_eth_irq(dev->irq, dev);
c9df406f 1808
fc32b0e2 1809 wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_CAUSE_EXT);
9f8dd319 1810}
c9df406f 1811#endif
9f8dd319 1812
fc32b0e2 1813static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
9f8dd319 1814{
e5371493 1815 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f
LB		 1816 int val;
1817
fc32b0e2
LB		 1818 smi_reg_read(mp, addr, reg, &val);
1819
c9df406f 1820 return val;
9f8dd319
DF		 1821}
1822
fc32b0e2 1823static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
9f8dd319 1824{
e5371493 1825 struct mv643xx_eth_private *mp = netdev_priv(dev);
fc32b0e2 1826 smi_reg_write(mp, addr, reg, val);
c9df406f 1827}
9f8dd319 1828
9f8dd319 1829
c9df406f 1830/* platform glue ************************************************************/
e5371493
LB		 1831static void
1832mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
1833 struct mbus_dram_target_info *dram)
c9df406f 1834{
cc9754b3 1835 void __iomem *base = msp->base;
c9df406f
LB		 1836 u32 win_enable;
1837 u32 win_protect;
1838 int i;
9f8dd319 1839
c9df406f
LB		 1840 for (i = 0; i < 6; i++) {
1841 writel(0, base + WINDOW_BASE(i));
1842 writel(0, base + WINDOW_SIZE(i));
1843 if (i < 4)
1844 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 1845 }
1846
c9df406f
LB		 1847 win_enable = 0x3f;
1848 win_protect = 0;
1849
1850 for (i = 0; i < dram->num_cs; i++) {
1851 struct mbus_dram_window *cs = dram->cs + i;
1852
1853 writel((cs->base & 0xffff0000) |
1854 (cs->mbus_attr << 8) |
1855 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1856 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1857
1858 win_enable &= ~(1 << i);
1859 win_protect |= 3 << (2 * i);
1860 }
1861
1862 writel(win_enable, base + WINDOW_BAR_ENABLE);
1863 msp->win_protect = win_protect;
9f8dd319
DF		 1864}
1865
c9df406f 1866static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 1867{
e5371493 1868 static int mv643xx_eth_version_printed = 0;
c9df406f 1869 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 1870 struct mv643xx_eth_shared_private *msp;
c9df406f
LB		 1871 struct resource *res;
1872 int ret;
9f8dd319 1873
e5371493 1874 if (!mv643xx_eth_version_printed++)
c9df406f 1875 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
9f8dd319 1876
c9df406f
LB		 1877 ret = -EINVAL;
1878 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1879 if (res == NULL)
1880 goto out;
9f8dd319 1881
c9df406f
LB		 1882 ret = -ENOMEM;
1883 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
1884 if (msp == NULL)
1885 goto out;
1886 memset(msp, 0, sizeof(*msp));
1887
cc9754b3
LB		 1888 msp->base = ioremap(res->start, res->end - res->start + 1);
1889 if (msp->base == NULL)
c9df406f
LB		 1890 goto out_free;
1891
1892 spin_lock_init(&msp->phy_lock);
c9df406f
LB		 1893
1894 /*
1895 * (Re-)program MBUS remapping windows if we are asked to.
1896 */
1897 if (pd != NULL && pd->dram != NULL)
1898 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
1899
fc32b0e2
LB		 1900 /*
1901 * Detect hardware parameters.
1902 */
1903 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
1904
1905 platform_set_drvdata(pdev, msp);
1906
c9df406f
LB		 1907 return 0;
1908
1909out_free:
1910 kfree(msp);
1911out:
1912 return ret;
1913}
1914
1915static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1916{
e5371493 1917 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
c9df406f 1918
cc9754b3 1919 iounmap(msp->base);
c9df406f
LB		 1920 kfree(msp);
1921
1922 return 0;
9f8dd319
DF		 1923}
1924
c9df406f 1925static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 1926 .probe = mv643xx_eth_shared_probe,
1927 .remove = mv643xx_eth_shared_remove,
c9df406f 1928 .driver = {
fc32b0e2 1929 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 1930 .owner = THIS_MODULE,
1931 },
1932};
1933
e5371493 1934static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 1935{
c9df406f 1936 int addr_shift = 5 * mp->port_num;
fc32b0e2 1937 u32 data;
1da177e4 1938
fc32b0e2
LB		 1939 data = rdl(mp, PHY_ADDR);
1940 data &= ~(0x1f << addr_shift);
1941 data |= (phy_addr & 0x1f) << addr_shift;
1942 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 1943}
1944
e5371493 1945static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 1946{
fc32b0e2
LB		 1947 unsigned int data;
1948
1949 data = rdl(mp, PHY_ADDR);
1950
1951 return (data >> (5 * mp->port_num)) & 0x1f;
1952}
1953
1954static void set_params(struct mv643xx_eth_private *mp,
1955 struct mv643xx_eth_platform_data *pd)
1956{
1957 struct net_device *dev = mp->dev;
1958
1959 if (is_valid_ether_addr(pd->mac_addr))
1960 memcpy(dev->dev_addr, pd->mac_addr, 6);
1961 else
1962 uc_addr_get(mp, dev->dev_addr);
1963
1964 if (pd->phy_addr == -1) {
1965 mp->shared_smi = NULL;
1966 mp->phy_addr = -1;
1967 } else {
1968 mp->shared_smi = mp->shared;
1969 if (pd->shared_smi != NULL)
1970 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
1971
1972 if (pd->force_phy_addr || pd->phy_addr) {
1973 mp->phy_addr = pd->phy_addr & 0x3f;
1974 phy_addr_set(mp, mp->phy_addr);
1975 } else {
1976 mp->phy_addr = phy_addr_get(mp);
1977 }
1978 }
1da177e4 1979
fc32b0e2
LB		 1980 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
1981 if (pd->rx_queue_size)
1982 mp->default_rx_ring_size = pd->rx_queue_size;
1983 mp->rx_desc_sram_addr = pd->rx_sram_addr;
1984 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 1985
fc32b0e2
LB		 1986 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
1987 if (pd->tx_queue_size)
1988 mp->default_tx_ring_size = pd->tx_queue_size;
1989 mp->tx_desc_sram_addr = pd->tx_sram_addr;
1990 mp->tx_desc_sram_size = pd->tx_sram_size;
1da177e4
LT		 1991}
1992
e5371493 1993static int phy_detect(struct mv643xx_eth_private *mp)
1da177e4 1994{
fc32b0e2
LB		 1995 unsigned int data;
1996 unsigned int data2;
1997
1998 smi_reg_read(mp, mp->phy_addr, 0, &data);
1999 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
1da177e4 2000
fc32b0e2
LB		 2001 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2002 if (((data ^ data2) & 0x1000) == 0)
2003 return -ENODEV;
1da177e4 2004
fc32b0e2 2005 smi_reg_write(mp, mp->phy_addr, 0, data);
1da177e4 2006
c9df406f 2007 return 0;
1da177e4
LT		 2008}
2009
fc32b0e2
LB		 2010static int phy_init(struct mv643xx_eth_private *mp,
2011 struct mv643xx_eth_platform_data *pd)
c28a4f89 2012{
fc32b0e2
LB		 2013 struct ethtool_cmd cmd;
2014 int err;
c28a4f89 2015
fc32b0e2
LB		 2016 err = phy_detect(mp);
2017 if (err) {
2018 dev_printk(KERN_INFO, &mp->dev->dev,
2019 "no PHY detected at addr %d\n", mp->phy_addr);
2020 return err;
2021 }
2022 phy_reset(mp);
2023
2024 mp->mii.phy_id = mp->phy_addr;
2025 mp->mii.phy_id_mask = 0x3f;
2026 mp->mii.reg_num_mask = 0x1f;
2027 mp->mii.dev = mp->dev;
2028 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2029 mp->mii.mdio_write = mv643xx_eth_mdio_write;
c28a4f89 2030
fc32b0e2 2031 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
c9df406f 2032
fc32b0e2
LB		 2033 memset(&cmd, 0, sizeof(cmd));
2034
2035 cmd.port = PORT_MII;
2036 cmd.transceiver = XCVR_INTERNAL;
2037 cmd.phy_address = mp->phy_addr;
2038 if (pd->speed == 0) {
2039 cmd.autoneg = AUTONEG_ENABLE;
2040 cmd.speed = SPEED_100;
2041 cmd.advertising = ADVERTISED_10baseT_Half |
2042 ADVERTISED_10baseT_Full |
2043 ADVERTISED_100baseT_Half |
2044 ADVERTISED_100baseT_Full;
c9df406f 2045 if (mp->mii.supports_gmii)
fc32b0e2 2046 cmd.advertising |= ADVERTISED_1000baseT_Full;
c9df406f 2047 } else {
fc32b0e2
LB		 2048 cmd.autoneg = AUTONEG_DISABLE;
2049 cmd.speed = pd->speed;
2050 cmd.duplex = pd->duplex;
c9df406f 2051 }
fc32b0e2
LB		 2052
2053 update_pscr(mp, cmd.speed, cmd.duplex);
2054 mv643xx_eth_set_settings(mp->dev, &cmd);
2055
2056 return 0;
c28a4f89
JC		 2057}
2058
c9df406f 2059static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2060{
c9df406f 2061 struct mv643xx_eth_platform_data *pd;
e5371493 2062 struct mv643xx_eth_private *mp;
c9df406f 2063 struct net_device *dev;
c9df406f 2064 struct resource *res;
c9df406f 2065 DECLARE_MAC_BUF(mac);
fc32b0e2 2066 int err;
1da177e4 2067
c9df406f
LB		 2068 pd = pdev->dev.platform_data;
2069 if (pd == NULL) {
fc32b0e2
LB		 2070 dev_printk(KERN_ERR, &pdev->dev,
2071 "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2072 return -ENODEV;
2073 }
1da177e4 2074
c9df406f 2075 if (pd->shared == NULL) {
fc32b0e2
LB		 2076 dev_printk(KERN_ERR, &pdev->dev,
2077 "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2078 return -ENODEV;
2079 }
8f518703 2080
e5371493 2081 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
c9df406f
LB		 2082 if (!dev)
2083 return -ENOMEM;
1da177e4 2084
c9df406f 2085 mp = netdev_priv(dev);
fc32b0e2
LB		 2086 platform_set_drvdata(pdev, mp);
2087
2088 mp->shared = platform_get_drvdata(pd->shared);
2089 mp->port_num = pd->port_number;
2090
c9df406f 2091 mp->dev = dev;
e5371493
LB		 2092#ifdef MV643XX_ETH_NAPI
2093 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
c9df406f 2094#endif
1da177e4 2095
fc32b0e2
LB		 2096 set_params(mp, pd);
2097
2098 spin_lock_init(&mp->lock);
2099
2100 mib_counters_clear(mp);
2101 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2102
2103 err = phy_init(mp, pd);
2104 if (err)
2105 goto out;
2106 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2107
2108
c9df406f
LB		 2109 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2110 BUG_ON(!res);
2111 dev->irq = res->start;
1da177e4 2112
fc32b0e2 2113 dev->hard_start_xmit = mv643xx_eth_xmit;
c9df406f
LB		 2114 dev->open = mv643xx_eth_open;
2115 dev->stop = mv643xx_eth_stop;
c9df406f 2116 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
fc32b0e2
LB		 2117 dev->set_mac_address = mv643xx_eth_set_mac_address;
2118 dev->do_ioctl = mv643xx_eth_ioctl;
2119 dev->change_mtu = mv643xx_eth_change_mtu;
c9df406f 2120 dev->tx_timeout = mv643xx_eth_tx_timeout;
c9df406f 2121#ifdef CONFIG_NET_POLL_CONTROLLER
e5371493 2122 dev->poll_controller = mv643xx_eth_netpoll;
c9df406f 2123#endif
c9df406f
LB		 2124 dev->watchdog_timeo = 2 * HZ;
2125 dev->base_addr = 0;
1da177e4 2126
e5371493 2127#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
b4de9051 2128 /*
c9df406f
LB		 2129 * Zero copy can only work if we use Discovery II memory. Else, we will
2130 * have to map the buffers to ISA memory which is only 16 MB
b4de9051 2131 */
c9df406f 2132 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
c9df406f 2133#endif
1da177e4 2134
fc32b0e2 2135 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2136
c9df406f 2137 if (mp->shared->win_protect)
fc32b0e2 2138 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2139
c9df406f
LB		 2140 err = register_netdev(dev);
2141 if (err)
2142 goto out;
1da177e4 2143
fc32b0e2
LB		 2144 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2145 mp->port_num, print_mac(mac, dev->dev_addr));
1da177e4 2146
c9df406f 2147 if (dev->features & NETIF_F_SG)
fc32b0e2 2148 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
1da177e4 2149
c9df406f 2150 if (dev->features & NETIF_F_IP_CSUM)
fc32b0e2 2151 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
1da177e4 2152
e5371493 2153#ifdef MV643XX_ETH_NAPI
fc32b0e2 2154 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
c9df406f 2155#endif
1da177e4 2156
13d64285 2157 if (mp->tx_desc_sram_size > 0)
fc32b0e2 2158 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
1da177e4 2159
c9df406f 2160 return 0;
1da177e4 2161
c9df406f
LB		 2162out:
2163 free_netdev(dev);
1da177e4 2164
c9df406f 2165 return err;
1da177e4
LT		 2166}
2167
c9df406f 2168static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2169{
fc32b0e2 2170 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2171
fc32b0e2 2172 unregister_netdev(mp->dev);
c9df406f 2173 flush_scheduled_work();
fc32b0e2 2174 free_netdev(mp->dev);
c9df406f 2175
c9df406f 2176 platform_set_drvdata(pdev, NULL);
fc32b0e2 2177
c9df406f 2178 return 0;
1da177e4
LT		 2179}
2180
c9df406f 2181static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 2182{
fc32b0e2 2183 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 2184
c9df406f 2185 /* Mask all interrupts on ethernet port */
fc32b0e2
LB		 2186 wrl(mp, INT_MASK(mp->port_num), 0);
2187 rdl(mp, INT_MASK(mp->port_num));
c9df406f 2188
fc32b0e2
LB		 2189 if (netif_running(mp->dev))
2190 port_reset(mp);
d0412d96
JC		 2191}
2192
c9df406f 2193static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 2194 .probe = mv643xx_eth_probe,
2195 .remove = mv643xx_eth_remove,
2196 .shutdown = mv643xx_eth_shutdown,
c9df406f 2197 .driver = {
fc32b0e2 2198 .name = MV643XX_ETH_NAME,
c9df406f
LB		 2199 .owner = THIS_MODULE,
2200 },
2201};
2202
e5371493 2203static int __init mv643xx_eth_init_module(void)
d0412d96 2204{
c9df406f 2205 int rc;
d0412d96 2206
c9df406f
LB		 2207 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2208 if (!rc) {
2209 rc = platform_driver_register(&mv643xx_eth_driver);
2210 if (rc)
2211 platform_driver_unregister(&mv643xx_eth_shared_driver);
2212 }
fc32b0e2 2213
c9df406f 2214 return rc;
d0412d96 2215}
fc32b0e2 2216module_init(mv643xx_eth_init_module);
d0412d96 2217
e5371493 2218static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 2219{
c9df406f
LB		 2220 platform_driver_unregister(&mv643xx_eth_driver);
2221 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 2222}
e5371493 2223module_exit(mv643xx_eth_cleanup_module);
1da177e4 2224
fc32b0e2
LB		 2225MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani "
2226 "and Dale Farnsworth");
c9df406f 2227MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 2228MODULE_LICENSE("GPL");
c9df406f 2229MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 2230MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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