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0da34b6d BG |
1 | /************************************************************************* |
2 | * myri10ge.c: Myricom Myri-10G Ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Myricom, Inc. | |
5 | * All rights reserved. | |
6 | * | |
7 | * Redistribution and use in source and binary forms, with or without | |
8 | * modification, are permitted provided that the following conditions | |
9 | * are met: | |
10 | * 1. Redistributions of source code must retain the above copyright | |
11 | * notice, this list of conditions and the following disclaimer. | |
12 | * 2. Redistributions in binary form must reproduce the above copyright | |
13 | * notice, this list of conditions and the following disclaimer in the | |
14 | * documentation and/or other materials provided with the distribution. | |
15 | * 3. Neither the name of Myricom, Inc. nor the names of its contributors | |
16 | * may be used to endorse or promote products derived from this software | |
17 | * without specific prior written permission. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND | |
20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE | |
23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |
27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |
28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |
29 | * SUCH DAMAGE. | |
30 | * | |
31 | * | |
32 | * If the eeprom on your board is not recent enough, you will need to get a | |
33 | * newer firmware image at: | |
34 | * http://www.myri.com/scs/download-Myri10GE.html | |
35 | * | |
36 | * Contact Information: | |
37 | * <help@myri.com> | |
38 | * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006 | |
39 | *************************************************************************/ | |
40 | ||
41 | #include <linux/tcp.h> | |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/skbuff.h> | |
44 | #include <linux/string.h> | |
45 | #include <linux/module.h> | |
46 | #include <linux/pci.h> | |
b10c0668 | 47 | #include <linux/dma-mapping.h> |
0da34b6d BG |
48 | #include <linux/etherdevice.h> |
49 | #include <linux/if_ether.h> | |
50 | #include <linux/if_vlan.h> | |
51 | #include <linux/ip.h> | |
52 | #include <linux/inet.h> | |
53 | #include <linux/in.h> | |
54 | #include <linux/ethtool.h> | |
55 | #include <linux/firmware.h> | |
56 | #include <linux/delay.h> | |
57 | #include <linux/version.h> | |
58 | #include <linux/timer.h> | |
59 | #include <linux/vmalloc.h> | |
60 | #include <linux/crc32.h> | |
61 | #include <linux/moduleparam.h> | |
62 | #include <linux/io.h> | |
63 | #include <net/checksum.h> | |
64 | #include <asm/byteorder.h> | |
65 | #include <asm/io.h> | |
0da34b6d BG |
66 | #include <asm/processor.h> |
67 | #ifdef CONFIG_MTRR | |
68 | #include <asm/mtrr.h> | |
69 | #endif | |
70 | ||
71 | #include "myri10ge_mcp.h" | |
72 | #include "myri10ge_mcp_gen_header.h" | |
73 | ||
b10c0668 | 74 | #define MYRI10GE_VERSION_STR "1.0.0" |
0da34b6d BG |
75 | |
76 | MODULE_DESCRIPTION("Myricom 10G driver (10GbE)"); | |
77 | MODULE_AUTHOR("Maintainer: help@myri.com"); | |
78 | MODULE_VERSION(MYRI10GE_VERSION_STR); | |
79 | MODULE_LICENSE("Dual BSD/GPL"); | |
80 | ||
81 | #define MYRI10GE_MAX_ETHER_MTU 9014 | |
82 | ||
83 | #define MYRI10GE_ETH_STOPPED 0 | |
84 | #define MYRI10GE_ETH_STOPPING 1 | |
85 | #define MYRI10GE_ETH_STARTING 2 | |
86 | #define MYRI10GE_ETH_RUNNING 3 | |
87 | #define MYRI10GE_ETH_OPEN_FAILED 4 | |
88 | ||
89 | #define MYRI10GE_EEPROM_STRINGS_SIZE 256 | |
90 | #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2) | |
91 | ||
92 | #define MYRI10GE_NO_CONFIRM_DATA 0xffffffff | |
93 | #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff | |
94 | ||
95 | struct myri10ge_rx_buffer_state { | |
96 | struct sk_buff *skb; | |
97 | DECLARE_PCI_UNMAP_ADDR(bus) | |
98 | DECLARE_PCI_UNMAP_LEN(len) | |
99 | }; | |
100 | ||
101 | struct myri10ge_tx_buffer_state { | |
102 | struct sk_buff *skb; | |
103 | int last; | |
104 | DECLARE_PCI_UNMAP_ADDR(bus) | |
105 | DECLARE_PCI_UNMAP_LEN(len) | |
106 | }; | |
107 | ||
108 | struct myri10ge_cmd { | |
109 | u32 data0; | |
110 | u32 data1; | |
111 | u32 data2; | |
112 | }; | |
113 | ||
114 | struct myri10ge_rx_buf { | |
115 | struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */ | |
116 | u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */ | |
117 | struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */ | |
118 | struct myri10ge_rx_buffer_state *info; | |
119 | int cnt; | |
120 | int alloc_fail; | |
121 | int mask; /* number of rx slots -1 */ | |
122 | }; | |
123 | ||
124 | struct myri10ge_tx_buf { | |
125 | struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */ | |
126 | u8 __iomem *wc_fifo; /* w/c send fifo address */ | |
127 | struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */ | |
128 | char *req_bytes; | |
129 | struct myri10ge_tx_buffer_state *info; | |
130 | int mask; /* number of transmit slots -1 */ | |
131 | int boundary; /* boundary transmits cannot cross */ | |
132 | int req ____cacheline_aligned; /* transmit slots submitted */ | |
133 | int pkt_start; /* packets started */ | |
134 | int done ____cacheline_aligned; /* transmit slots completed */ | |
135 | int pkt_done; /* packets completed */ | |
136 | }; | |
137 | ||
138 | struct myri10ge_rx_done { | |
139 | struct mcp_slot *entry; | |
140 | dma_addr_t bus; | |
141 | int cnt; | |
142 | int idx; | |
143 | }; | |
144 | ||
145 | struct myri10ge_priv { | |
146 | int running; /* running? */ | |
147 | int csum_flag; /* rx_csums? */ | |
148 | struct myri10ge_tx_buf tx; /* transmit ring */ | |
149 | struct myri10ge_rx_buf rx_small; | |
150 | struct myri10ge_rx_buf rx_big; | |
151 | struct myri10ge_rx_done rx_done; | |
152 | int small_bytes; | |
153 | struct net_device *dev; | |
154 | struct net_device_stats stats; | |
155 | u8 __iomem *sram; | |
156 | int sram_size; | |
157 | unsigned long board_span; | |
158 | unsigned long iomem_base; | |
159 | u32 __iomem *irq_claim; | |
160 | u32 __iomem *irq_deassert; | |
161 | char *mac_addr_string; | |
162 | struct mcp_cmd_response *cmd; | |
163 | dma_addr_t cmd_bus; | |
164 | struct mcp_irq_data *fw_stats; | |
165 | dma_addr_t fw_stats_bus; | |
166 | struct pci_dev *pdev; | |
167 | int msi_enabled; | |
168 | unsigned int link_state; | |
169 | unsigned int rdma_tags_available; | |
170 | int intr_coal_delay; | |
171 | u32 __iomem *intr_coal_delay_ptr; | |
172 | int mtrr; | |
173 | int wake_queue; | |
174 | int stop_queue; | |
175 | int down_cnt; | |
176 | wait_queue_head_t down_wq; | |
177 | struct work_struct watchdog_work; | |
178 | struct timer_list watchdog_timer; | |
179 | int watchdog_tx_done; | |
c54772e7 | 180 | int watchdog_tx_req; |
0da34b6d BG |
181 | int watchdog_resets; |
182 | int tx_linearized; | |
183 | int pause; | |
184 | char *fw_name; | |
185 | char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE]; | |
186 | char fw_version[128]; | |
187 | u8 mac_addr[6]; /* eeprom mac address */ | |
188 | unsigned long serial_number; | |
189 | int vendor_specific_offset; | |
85a7ea1b | 190 | int fw_multicast_support; |
0da34b6d BG |
191 | u32 devctl; |
192 | u16 msi_flags; | |
0da34b6d BG |
193 | u32 read_dma; |
194 | u32 write_dma; | |
195 | u32 read_write_dma; | |
c58ac5ca BG |
196 | u32 link_changes; |
197 | u32 msg_enable; | |
0da34b6d BG |
198 | }; |
199 | ||
200 | static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat"; | |
201 | static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat"; | |
202 | ||
203 | static char *myri10ge_fw_name = NULL; | |
204 | module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR); | |
205 | MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n"); | |
206 | ||
207 | static int myri10ge_ecrc_enable = 1; | |
208 | module_param(myri10ge_ecrc_enable, int, S_IRUGO); | |
209 | MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n"); | |
210 | ||
211 | static int myri10ge_max_intr_slots = 1024; | |
212 | module_param(myri10ge_max_intr_slots, int, S_IRUGO); | |
213 | MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n"); | |
214 | ||
215 | static int myri10ge_small_bytes = -1; /* -1 == auto */ | |
216 | module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR); | |
217 | MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n"); | |
218 | ||
219 | static int myri10ge_msi = 1; /* enable msi by default */ | |
220 | module_param(myri10ge_msi, int, S_IRUGO); | |
221 | MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n"); | |
222 | ||
223 | static int myri10ge_intr_coal_delay = 25; | |
224 | module_param(myri10ge_intr_coal_delay, int, S_IRUGO); | |
225 | MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n"); | |
226 | ||
227 | static int myri10ge_flow_control = 1; | |
228 | module_param(myri10ge_flow_control, int, S_IRUGO); | |
229 | MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n"); | |
230 | ||
231 | static int myri10ge_deassert_wait = 1; | |
232 | module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR); | |
233 | MODULE_PARM_DESC(myri10ge_deassert_wait, | |
234 | "Wait when deasserting legacy interrupts\n"); | |
235 | ||
236 | static int myri10ge_force_firmware = 0; | |
237 | module_param(myri10ge_force_firmware, int, S_IRUGO); | |
238 | MODULE_PARM_DESC(myri10ge_force_firmware, | |
239 | "Force firmware to assume aligned completions\n"); | |
240 | ||
241 | static int myri10ge_skb_cross_4k = 0; | |
242 | module_param(myri10ge_skb_cross_4k, int, S_IRUGO | S_IWUSR); | |
243 | MODULE_PARM_DESC(myri10ge_skb_cross_4k, | |
244 | "Can a small skb cross a 4KB boundary?\n"); | |
245 | ||
246 | static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN; | |
247 | module_param(myri10ge_initial_mtu, int, S_IRUGO); | |
248 | MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n"); | |
249 | ||
250 | static int myri10ge_napi_weight = 64; | |
251 | module_param(myri10ge_napi_weight, int, S_IRUGO); | |
252 | MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n"); | |
253 | ||
254 | static int myri10ge_watchdog_timeout = 1; | |
255 | module_param(myri10ge_watchdog_timeout, int, S_IRUGO); | |
256 | MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n"); | |
257 | ||
258 | static int myri10ge_max_irq_loops = 1048576; | |
259 | module_param(myri10ge_max_irq_loops, int, S_IRUGO); | |
260 | MODULE_PARM_DESC(myri10ge_max_irq_loops, | |
261 | "Set stuck legacy IRQ detection threshold\n"); | |
262 | ||
c58ac5ca BG |
263 | #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK |
264 | ||
265 | static int myri10ge_debug = -1; /* defaults above */ | |
266 | module_param(myri10ge_debug, int, 0); | |
267 | MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)"); | |
268 | ||
0da34b6d BG |
269 | #define MYRI10GE_FW_OFFSET 1024*1024 |
270 | #define MYRI10GE_HIGHPART_TO_U32(X) \ | |
271 | (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0) | |
272 | #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X)) | |
273 | ||
274 | #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8) | |
275 | ||
276 | static int | |
277 | myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd, | |
278 | struct myri10ge_cmd *data, int atomic) | |
279 | { | |
280 | struct mcp_cmd *buf; | |
281 | char buf_bytes[sizeof(*buf) + 8]; | |
282 | struct mcp_cmd_response *response = mgp->cmd; | |
e700f9f4 | 283 | char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD; |
0da34b6d BG |
284 | u32 dma_low, dma_high, result, value; |
285 | int sleep_total = 0; | |
286 | ||
287 | /* ensure buf is aligned to 8 bytes */ | |
288 | buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8); | |
289 | ||
290 | buf->data0 = htonl(data->data0); | |
291 | buf->data1 = htonl(data->data1); | |
292 | buf->data2 = htonl(data->data2); | |
293 | buf->cmd = htonl(cmd); | |
294 | dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus); | |
295 | dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus); | |
296 | ||
297 | buf->response_addr.low = htonl(dma_low); | |
298 | buf->response_addr.high = htonl(dma_high); | |
299 | response->result = MYRI10GE_NO_RESPONSE_RESULT; | |
300 | mb(); | |
301 | myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf)); | |
302 | ||
303 | /* wait up to 15ms. Longest command is the DMA benchmark, | |
304 | * which is capped at 5ms, but runs from a timeout handler | |
305 | * that runs every 7.8ms. So a 15ms timeout leaves us with | |
306 | * a 2.2ms margin | |
307 | */ | |
308 | if (atomic) { | |
309 | /* if atomic is set, do not sleep, | |
310 | * and try to get the completion quickly | |
311 | * (1ms will be enough for those commands) */ | |
312 | for (sleep_total = 0; | |
313 | sleep_total < 1000 | |
314 | && response->result == MYRI10GE_NO_RESPONSE_RESULT; | |
315 | sleep_total += 10) | |
316 | udelay(10); | |
317 | } else { | |
318 | /* use msleep for most command */ | |
319 | for (sleep_total = 0; | |
320 | sleep_total < 15 | |
321 | && response->result == MYRI10GE_NO_RESPONSE_RESULT; | |
322 | sleep_total++) | |
323 | msleep(1); | |
324 | } | |
325 | ||
326 | result = ntohl(response->result); | |
327 | value = ntohl(response->data); | |
328 | if (result != MYRI10GE_NO_RESPONSE_RESULT) { | |
329 | if (result == 0) { | |
330 | data->data0 = value; | |
331 | return 0; | |
85a7ea1b BG |
332 | } else if (result == MXGEFW_CMD_UNKNOWN) { |
333 | return -ENOSYS; | |
0da34b6d BG |
334 | } else { |
335 | dev_err(&mgp->pdev->dev, | |
336 | "command %d failed, result = %d\n", | |
337 | cmd, result); | |
338 | return -ENXIO; | |
339 | } | |
340 | } | |
341 | ||
342 | dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n", | |
343 | cmd, result); | |
344 | return -EAGAIN; | |
345 | } | |
346 | ||
347 | /* | |
348 | * The eeprom strings on the lanaiX have the format | |
349 | * SN=x\0 | |
350 | * MAC=x:x:x:x:x:x\0 | |
351 | * PT:ddd mmm xx xx:xx:xx xx\0 | |
352 | * PV:ddd mmm xx xx:xx:xx xx\0 | |
353 | */ | |
354 | static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp) | |
355 | { | |
356 | char *ptr, *limit; | |
357 | int i; | |
358 | ||
359 | ptr = mgp->eeprom_strings; | |
360 | limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE; | |
361 | ||
362 | while (*ptr != '\0' && ptr < limit) { | |
363 | if (memcmp(ptr, "MAC=", 4) == 0) { | |
364 | ptr += 4; | |
365 | mgp->mac_addr_string = ptr; | |
366 | for (i = 0; i < 6; i++) { | |
367 | if ((ptr + 2) > limit) | |
368 | goto abort; | |
369 | mgp->mac_addr[i] = | |
370 | simple_strtoul(ptr, &ptr, 16); | |
371 | ptr += 1; | |
372 | } | |
373 | } | |
374 | if (memcmp((const void *)ptr, "SN=", 3) == 0) { | |
375 | ptr += 3; | |
376 | mgp->serial_number = simple_strtoul(ptr, &ptr, 10); | |
377 | } | |
378 | while (ptr < limit && *ptr++) ; | |
379 | } | |
380 | ||
381 | return 0; | |
382 | ||
383 | abort: | |
384 | dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n"); | |
385 | return -ENXIO; | |
386 | } | |
387 | ||
388 | /* | |
389 | * Enable or disable periodic RDMAs from the host to make certain | |
390 | * chipsets resend dropped PCIe messages | |
391 | */ | |
392 | ||
393 | static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable) | |
394 | { | |
395 | char __iomem *submit; | |
396 | u32 buf[16]; | |
397 | u32 dma_low, dma_high; | |
398 | int i; | |
399 | ||
400 | /* clear confirmation addr */ | |
401 | mgp->cmd->data = 0; | |
402 | mb(); | |
403 | ||
404 | /* send a rdma command to the PCIe engine, and wait for the | |
405 | * response in the confirmation address. The firmware should | |
406 | * write a -1 there to indicate it is alive and well | |
407 | */ | |
408 | dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus); | |
409 | dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus); | |
410 | ||
411 | buf[0] = htonl(dma_high); /* confirm addr MSW */ | |
412 | buf[1] = htonl(dma_low); /* confirm addr LSW */ | |
413 | buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA); /* confirm data */ | |
414 | buf[3] = htonl(dma_high); /* dummy addr MSW */ | |
415 | buf[4] = htonl(dma_low); /* dummy addr LSW */ | |
416 | buf[5] = htonl(enable); /* enable? */ | |
417 | ||
e700f9f4 | 418 | submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA; |
0da34b6d BG |
419 | |
420 | myri10ge_pio_copy(submit, &buf, sizeof(buf)); | |
421 | for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++) | |
422 | msleep(1); | |
423 | if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) | |
424 | dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n", | |
425 | (enable ? "enable" : "disable")); | |
426 | } | |
427 | ||
428 | static int | |
429 | myri10ge_validate_firmware(struct myri10ge_priv *mgp, | |
430 | struct mcp_gen_header *hdr) | |
431 | { | |
432 | struct device *dev = &mgp->pdev->dev; | |
433 | int major, minor; | |
434 | ||
435 | /* check firmware type */ | |
436 | if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) { | |
437 | dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type)); | |
438 | return -EINVAL; | |
439 | } | |
440 | ||
441 | /* save firmware version for ethtool */ | |
442 | strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version)); | |
443 | ||
444 | sscanf(mgp->fw_version, "%d.%d", &major, &minor); | |
445 | ||
446 | if (!(major == MXGEFW_VERSION_MAJOR && minor == MXGEFW_VERSION_MINOR)) { | |
447 | dev_err(dev, "Found firmware version %s\n", mgp->fw_version); | |
448 | dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR, | |
449 | MXGEFW_VERSION_MINOR); | |
450 | return -EINVAL; | |
451 | } | |
452 | return 0; | |
453 | } | |
454 | ||
455 | static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size) | |
456 | { | |
457 | unsigned crc, reread_crc; | |
458 | const struct firmware *fw; | |
459 | struct device *dev = &mgp->pdev->dev; | |
460 | struct mcp_gen_header *hdr; | |
461 | size_t hdr_offset; | |
462 | int status; | |
e454358a | 463 | unsigned i; |
0da34b6d BG |
464 | |
465 | if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) { | |
466 | dev_err(dev, "Unable to load %s firmware image via hotplug\n", | |
467 | mgp->fw_name); | |
468 | status = -EINVAL; | |
469 | goto abort_with_nothing; | |
470 | } | |
471 | ||
472 | /* check size */ | |
473 | ||
474 | if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET || | |
475 | fw->size < MCP_HEADER_PTR_OFFSET + 4) { | |
476 | dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size); | |
477 | status = -EINVAL; | |
478 | goto abort_with_fw; | |
479 | } | |
480 | ||
481 | /* check id */ | |
482 | hdr_offset = ntohl(*(u32 *) (fw->data + MCP_HEADER_PTR_OFFSET)); | |
483 | if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) { | |
484 | dev_err(dev, "Bad firmware file\n"); | |
485 | status = -EINVAL; | |
486 | goto abort_with_fw; | |
487 | } | |
488 | hdr = (void *)(fw->data + hdr_offset); | |
489 | ||
490 | status = myri10ge_validate_firmware(mgp, hdr); | |
491 | if (status != 0) | |
492 | goto abort_with_fw; | |
493 | ||
494 | crc = crc32(~0, fw->data, fw->size); | |
e454358a BG |
495 | for (i = 0; i < fw->size; i += 256) { |
496 | myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i, | |
497 | fw->data + i, | |
498 | min(256U, (unsigned)(fw->size - i))); | |
499 | mb(); | |
500 | readb(mgp->sram); | |
b10c0668 | 501 | } |
0da34b6d BG |
502 | /* corruption checking is good for parity recovery and buggy chipset */ |
503 | memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size); | |
504 | reread_crc = crc32(~0, fw->data, fw->size); | |
505 | if (crc != reread_crc) { | |
506 | dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n", | |
507 | (unsigned)fw->size, reread_crc, crc); | |
508 | status = -EIO; | |
509 | goto abort_with_fw; | |
510 | } | |
511 | *size = (u32) fw->size; | |
512 | ||
513 | abort_with_fw: | |
514 | release_firmware(fw); | |
515 | ||
516 | abort_with_nothing: | |
517 | return status; | |
518 | } | |
519 | ||
520 | static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp) | |
521 | { | |
522 | struct mcp_gen_header *hdr; | |
523 | struct device *dev = &mgp->pdev->dev; | |
524 | const size_t bytes = sizeof(struct mcp_gen_header); | |
525 | size_t hdr_offset; | |
526 | int status; | |
527 | ||
528 | /* find running firmware header */ | |
529 | hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)); | |
530 | ||
531 | if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) { | |
532 | dev_err(dev, "Running firmware has bad header offset (%d)\n", | |
533 | (int)hdr_offset); | |
534 | return -EIO; | |
535 | } | |
536 | ||
537 | /* copy header of running firmware from SRAM to host memory to | |
538 | * validate firmware */ | |
539 | hdr = kmalloc(bytes, GFP_KERNEL); | |
540 | if (hdr == NULL) { | |
541 | dev_err(dev, "could not malloc firmware hdr\n"); | |
542 | return -ENOMEM; | |
543 | } | |
544 | memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes); | |
545 | status = myri10ge_validate_firmware(mgp, hdr); | |
546 | kfree(hdr); | |
547 | return status; | |
548 | } | |
549 | ||
550 | static int myri10ge_load_firmware(struct myri10ge_priv *mgp) | |
551 | { | |
552 | char __iomem *submit; | |
553 | u32 buf[16]; | |
554 | u32 dma_low, dma_high, size; | |
555 | int status, i; | |
556 | ||
b10c0668 | 557 | size = 0; |
0da34b6d BG |
558 | status = myri10ge_load_hotplug_firmware(mgp, &size); |
559 | if (status) { | |
560 | dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n"); | |
561 | ||
562 | /* Do not attempt to adopt firmware if there | |
563 | * was a bad crc */ | |
564 | if (status == -EIO) | |
565 | return status; | |
566 | ||
567 | status = myri10ge_adopt_running_firmware(mgp); | |
568 | if (status != 0) { | |
569 | dev_err(&mgp->pdev->dev, | |
570 | "failed to adopt running firmware\n"); | |
571 | return status; | |
572 | } | |
573 | dev_info(&mgp->pdev->dev, | |
574 | "Successfully adopted running firmware\n"); | |
575 | if (mgp->tx.boundary == 4096) { | |
576 | dev_warn(&mgp->pdev->dev, | |
577 | "Using firmware currently running on NIC" | |
578 | ". For optimal\n"); | |
579 | dev_warn(&mgp->pdev->dev, | |
580 | "performance consider loading optimized " | |
581 | "firmware\n"); | |
582 | dev_warn(&mgp->pdev->dev, "via hotplug\n"); | |
583 | } | |
584 | ||
585 | mgp->fw_name = "adopted"; | |
586 | mgp->tx.boundary = 2048; | |
587 | return status; | |
588 | } | |
589 | ||
590 | /* clear confirmation addr */ | |
591 | mgp->cmd->data = 0; | |
592 | mb(); | |
593 | ||
594 | /* send a reload command to the bootstrap MCP, and wait for the | |
595 | * response in the confirmation address. The firmware should | |
596 | * write a -1 there to indicate it is alive and well | |
597 | */ | |
598 | dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus); | |
599 | dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus); | |
600 | ||
601 | buf[0] = htonl(dma_high); /* confirm addr MSW */ | |
602 | buf[1] = htonl(dma_low); /* confirm addr LSW */ | |
603 | buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA); /* confirm data */ | |
604 | ||
605 | /* FIX: All newest firmware should un-protect the bottom of | |
606 | * the sram before handoff. However, the very first interfaces | |
607 | * do not. Therefore the handoff copy must skip the first 8 bytes | |
608 | */ | |
609 | buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */ | |
610 | buf[4] = htonl(size - 8); /* length of code */ | |
611 | buf[5] = htonl(8); /* where to copy to */ | |
612 | buf[6] = htonl(0); /* where to jump to */ | |
613 | ||
e700f9f4 | 614 | submit = mgp->sram + MXGEFW_BOOT_HANDOFF; |
0da34b6d BG |
615 | |
616 | myri10ge_pio_copy(submit, &buf, sizeof(buf)); | |
617 | mb(); | |
618 | msleep(1); | |
619 | mb(); | |
620 | i = 0; | |
621 | while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) { | |
622 | msleep(1); | |
623 | i++; | |
624 | } | |
625 | if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) { | |
626 | dev_err(&mgp->pdev->dev, "handoff failed\n"); | |
627 | return -ENXIO; | |
628 | } | |
629 | dev_info(&mgp->pdev->dev, "handoff confirmed\n"); | |
9a71db72 | 630 | myri10ge_dummy_rdma(mgp, 1); |
0da34b6d BG |
631 | |
632 | return 0; | |
633 | } | |
634 | ||
635 | static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr) | |
636 | { | |
637 | struct myri10ge_cmd cmd; | |
638 | int status; | |
639 | ||
640 | cmd.data0 = ((addr[0] << 24) | (addr[1] << 16) | |
641 | | (addr[2] << 8) | addr[3]); | |
642 | ||
643 | cmd.data1 = ((addr[4] << 8) | (addr[5])); | |
644 | ||
645 | status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0); | |
646 | return status; | |
647 | } | |
648 | ||
649 | static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause) | |
650 | { | |
651 | struct myri10ge_cmd cmd; | |
652 | int status, ctl; | |
653 | ||
654 | ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL; | |
655 | status = myri10ge_send_cmd(mgp, ctl, &cmd, 0); | |
656 | ||
657 | if (status) { | |
658 | printk(KERN_ERR | |
659 | "myri10ge: %s: Failed to set flow control mode\n", | |
660 | mgp->dev->name); | |
661 | return status; | |
662 | } | |
663 | mgp->pause = pause; | |
664 | return 0; | |
665 | } | |
666 | ||
667 | static void | |
668 | myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic) | |
669 | { | |
670 | struct myri10ge_cmd cmd; | |
671 | int status, ctl; | |
672 | ||
673 | ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC; | |
674 | status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic); | |
675 | if (status) | |
676 | printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n", | |
677 | mgp->dev->name); | |
678 | } | |
679 | ||
680 | static int myri10ge_reset(struct myri10ge_priv *mgp) | |
681 | { | |
682 | struct myri10ge_cmd cmd; | |
683 | int status; | |
684 | size_t bytes; | |
685 | u32 len; | |
686 | ||
687 | /* try to send a reset command to the card to see if it | |
688 | * is alive */ | |
689 | memset(&cmd, 0, sizeof(cmd)); | |
690 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0); | |
691 | if (status != 0) { | |
692 | dev_err(&mgp->pdev->dev, "failed reset\n"); | |
693 | return -ENXIO; | |
694 | } | |
695 | ||
696 | /* Now exchange information about interrupts */ | |
697 | ||
698 | bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry); | |
699 | memset(mgp->rx_done.entry, 0, bytes); | |
700 | cmd.data0 = (u32) bytes; | |
701 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0); | |
702 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus); | |
703 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus); | |
704 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0); | |
705 | ||
706 | status |= | |
707 | myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0); | |
708 | mgp->irq_claim = (__iomem u32 *) (mgp->sram + cmd.data0); | |
709 | if (!mgp->msi_enabled) { | |
710 | status |= myri10ge_send_cmd | |
711 | (mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, &cmd, 0); | |
712 | mgp->irq_deassert = (__iomem u32 *) (mgp->sram + cmd.data0); | |
713 | ||
714 | } | |
715 | status |= myri10ge_send_cmd | |
716 | (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0); | |
717 | mgp->intr_coal_delay_ptr = (__iomem u32 *) (mgp->sram + cmd.data0); | |
718 | if (status != 0) { | |
719 | dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n"); | |
720 | return status; | |
721 | } | |
722 | __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr); | |
723 | ||
724 | /* Run a small DMA test. | |
725 | * The magic multipliers to the length tell the firmware | |
726 | * to do DMA read, write, or read+write tests. The | |
727 | * results are returned in cmd.data0. The upper 16 | |
728 | * bits or the return is the number of transfers completed. | |
729 | * The lower 16 bits is the time in 0.5us ticks that the | |
730 | * transfers took to complete. | |
731 | */ | |
732 | ||
733 | len = mgp->tx.boundary; | |
734 | ||
735 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus); | |
736 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus); | |
737 | cmd.data2 = len * 0x10000; | |
738 | status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0); | |
739 | if (status == 0) | |
740 | mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / | |
741 | (cmd.data0 & 0xffff); | |
742 | else | |
743 | dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n", | |
744 | status); | |
745 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus); | |
746 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus); | |
747 | cmd.data2 = len * 0x1; | |
748 | status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0); | |
749 | if (status == 0) | |
750 | mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / | |
751 | (cmd.data0 & 0xffff); | |
752 | else | |
753 | dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n", | |
754 | status); | |
755 | ||
756 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus); | |
757 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus); | |
758 | cmd.data2 = len * 0x10001; | |
759 | status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0); | |
760 | if (status == 0) | |
761 | mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) / | |
762 | (cmd.data0 & 0xffff); | |
763 | else | |
764 | dev_warn(&mgp->pdev->dev, | |
765 | "DMA read/write benchmark failed: %d\n", status); | |
766 | ||
767 | memset(mgp->rx_done.entry, 0, bytes); | |
768 | ||
769 | /* reset mcp/driver shared state back to 0 */ | |
770 | mgp->tx.req = 0; | |
771 | mgp->tx.done = 0; | |
772 | mgp->tx.pkt_start = 0; | |
773 | mgp->tx.pkt_done = 0; | |
774 | mgp->rx_big.cnt = 0; | |
775 | mgp->rx_small.cnt = 0; | |
776 | mgp->rx_done.idx = 0; | |
777 | mgp->rx_done.cnt = 0; | |
c58ac5ca | 778 | mgp->link_changes = 0; |
0da34b6d BG |
779 | status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr); |
780 | myri10ge_change_promisc(mgp, 0, 0); | |
781 | myri10ge_change_pause(mgp, mgp->pause); | |
782 | return status; | |
783 | } | |
784 | ||
785 | static inline void | |
786 | myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst, | |
787 | struct mcp_kreq_ether_recv *src) | |
788 | { | |
789 | u32 low; | |
790 | ||
791 | low = src->addr_low; | |
792 | src->addr_low = DMA_32BIT_MASK; | |
793 | myri10ge_pio_copy(dst, src, 8 * sizeof(*src)); | |
794 | mb(); | |
795 | src->addr_low = low; | |
796 | __raw_writel(low, &dst->addr_low); | |
797 | mb(); | |
798 | } | |
799 | ||
800 | /* | |
b10c0668 | 801 | * Set of routines to get a new receive buffer. Any buffer which |
0da34b6d BG |
802 | * crosses a 4KB boundary must start on a 4KB boundary due to PCIe |
803 | * wdma restrictions. We also try to align any smaller allocation to | |
804 | * at least a 16 byte boundary for efficiency. We assume the linux | |
805 | * memory allocator works by powers of 2, and will not return memory | |
806 | * smaller than 2KB which crosses a 4KB boundary. If it does, we fall | |
807 | * back to allocating 2x as much space as required. | |
808 | * | |
809 | * We intend to replace large (>4KB) skb allocations by using | |
810 | * pages directly and building a fraglist in the near future. | |
811 | */ | |
812 | ||
fd6746da BG |
813 | static inline struct sk_buff *myri10ge_alloc_big(struct net_device *dev, |
814 | int bytes) | |
0da34b6d BG |
815 | { |
816 | struct sk_buff *skb; | |
817 | unsigned long data, roundup; | |
818 | ||
fd6746da | 819 | skb = netdev_alloc_skb(dev, bytes + 4096 + MXGEFW_PAD); |
0da34b6d BG |
820 | if (skb == NULL) |
821 | return NULL; | |
822 | ||
823 | /* Correct skb->truesize so that socket buffer | |
824 | * accounting is not confused the rounding we must | |
825 | * do to satisfy alignment constraints. | |
826 | */ | |
827 | skb->truesize -= 4096; | |
828 | ||
829 | data = (unsigned long)(skb->data); | |
830 | roundup = (-data) & (4095); | |
831 | skb_reserve(skb, roundup); | |
832 | return skb; | |
833 | } | |
834 | ||
835 | /* Allocate 2x as much space as required and use whichever portion | |
836 | * does not cross a 4KB boundary */ | |
fd6746da BG |
837 | static inline struct sk_buff *myri10ge_alloc_small_safe(struct net_device *dev, |
838 | unsigned int bytes) | |
0da34b6d BG |
839 | { |
840 | struct sk_buff *skb; | |
841 | unsigned long data, boundary; | |
842 | ||
fd6746da | 843 | skb = netdev_alloc_skb(dev, 2 * (bytes + MXGEFW_PAD) - 1); |
0da34b6d BG |
844 | if (unlikely(skb == NULL)) |
845 | return NULL; | |
846 | ||
847 | /* Correct skb->truesize so that socket buffer | |
848 | * accounting is not confused the rounding we must | |
849 | * do to satisfy alignment constraints. | |
850 | */ | |
851 | skb->truesize -= bytes + MXGEFW_PAD; | |
852 | ||
853 | data = (unsigned long)(skb->data); | |
854 | boundary = (data + 4095UL) & ~4095UL; | |
855 | if ((boundary - data) >= (bytes + MXGEFW_PAD)) | |
856 | return skb; | |
857 | ||
858 | skb_reserve(skb, boundary - data); | |
859 | return skb; | |
860 | } | |
861 | ||
862 | /* Allocate just enough space, and verify that the allocated | |
863 | * space does not cross a 4KB boundary */ | |
fd6746da BG |
864 | static inline struct sk_buff *myri10ge_alloc_small(struct net_device *dev, |
865 | int bytes) | |
0da34b6d BG |
866 | { |
867 | struct sk_buff *skb; | |
868 | unsigned long roundup, data, end; | |
869 | ||
fd6746da | 870 | skb = netdev_alloc_skb(dev, bytes + 16 + MXGEFW_PAD); |
0da34b6d BG |
871 | if (unlikely(skb == NULL)) |
872 | return NULL; | |
873 | ||
874 | /* Round allocated buffer to 16 byte boundary */ | |
875 | data = (unsigned long)(skb->data); | |
876 | roundup = (-data) & 15UL; | |
877 | skb_reserve(skb, roundup); | |
878 | /* Verify that the data buffer does not cross a page boundary */ | |
879 | data = (unsigned long)(skb->data); | |
880 | end = data + bytes + MXGEFW_PAD - 1; | |
881 | if (unlikely(((end >> 12) != (data >> 12)) && (data & 4095UL))) { | |
882 | printk(KERN_NOTICE | |
883 | "myri10ge_alloc_small: small skb crossed 4KB boundary\n"); | |
884 | myri10ge_skb_cross_4k = 1; | |
885 | dev_kfree_skb_any(skb); | |
fd6746da | 886 | skb = myri10ge_alloc_small_safe(dev, bytes); |
0da34b6d BG |
887 | } |
888 | return skb; | |
889 | } | |
890 | ||
891 | static inline int | |
fd6746da BG |
892 | myri10ge_getbuf(struct myri10ge_rx_buf *rx, struct myri10ge_priv *mgp, |
893 | int bytes, int idx) | |
0da34b6d | 894 | { |
fd6746da BG |
895 | struct net_device *dev = mgp->dev; |
896 | struct pci_dev *pdev = mgp->pdev; | |
0da34b6d BG |
897 | struct sk_buff *skb; |
898 | dma_addr_t bus; | |
899 | int len, retval = 0; | |
900 | ||
901 | bytes += VLAN_HLEN; /* account for 802.1q vlan tag */ | |
902 | ||
903 | if ((bytes + MXGEFW_PAD) > (4096 - 16) /* linux overhead */ ) | |
fd6746da | 904 | skb = myri10ge_alloc_big(dev, bytes); |
0da34b6d | 905 | else if (myri10ge_skb_cross_4k) |
fd6746da | 906 | skb = myri10ge_alloc_small_safe(dev, bytes); |
0da34b6d | 907 | else |
fd6746da | 908 | skb = myri10ge_alloc_small(dev, bytes); |
0da34b6d BG |
909 | |
910 | if (unlikely(skb == NULL)) { | |
911 | rx->alloc_fail++; | |
912 | retval = -ENOBUFS; | |
913 | goto done; | |
914 | } | |
915 | ||
916 | /* set len so that it only covers the area we | |
917 | * need mapped for DMA */ | |
918 | len = bytes + MXGEFW_PAD; | |
919 | ||
920 | bus = pci_map_single(pdev, skb->data, len, PCI_DMA_FROMDEVICE); | |
921 | rx->info[idx].skb = skb; | |
922 | pci_unmap_addr_set(&rx->info[idx], bus, bus); | |
923 | pci_unmap_len_set(&rx->info[idx], len, len); | |
924 | rx->shadow[idx].addr_low = htonl(MYRI10GE_LOWPART_TO_U32(bus)); | |
925 | rx->shadow[idx].addr_high = htonl(MYRI10GE_HIGHPART_TO_U32(bus)); | |
926 | ||
927 | done: | |
928 | /* copy 8 descriptors (64-bytes) to the mcp at a time */ | |
929 | if ((idx & 7) == 7) { | |
930 | if (rx->wc_fifo == NULL) | |
931 | myri10ge_submit_8rx(&rx->lanai[idx - 7], | |
932 | &rx->shadow[idx - 7]); | |
933 | else { | |
934 | mb(); | |
935 | myri10ge_pio_copy(rx->wc_fifo, | |
936 | &rx->shadow[idx - 7], 64); | |
937 | } | |
938 | } | |
939 | return retval; | |
940 | } | |
941 | ||
942 | static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, u16 hw_csum) | |
943 | { | |
944 | struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data); | |
945 | ||
946 | if ((skb->protocol == ntohs(ETH_P_8021Q)) && | |
947 | (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) || | |
948 | vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) { | |
949 | skb->csum = hw_csum; | |
950 | skb->ip_summed = CHECKSUM_HW; | |
951 | } | |
952 | } | |
953 | ||
954 | static inline unsigned long | |
955 | myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx, | |
956 | int bytes, int len, int csum) | |
957 | { | |
958 | dma_addr_t bus; | |
959 | struct sk_buff *skb; | |
960 | int idx, unmap_len; | |
961 | ||
962 | idx = rx->cnt & rx->mask; | |
963 | rx->cnt++; | |
964 | ||
965 | /* save a pointer to the received skb */ | |
966 | skb = rx->info[idx].skb; | |
967 | bus = pci_unmap_addr(&rx->info[idx], bus); | |
968 | unmap_len = pci_unmap_len(&rx->info[idx], len); | |
969 | ||
970 | /* try to replace the received skb */ | |
fd6746da | 971 | if (myri10ge_getbuf(rx, mgp, bytes, idx)) { |
0da34b6d BG |
972 | /* drop the frame -- the old skbuf is re-cycled */ |
973 | mgp->stats.rx_dropped += 1; | |
974 | return 0; | |
975 | } | |
976 | ||
977 | /* unmap the recvd skb */ | |
978 | pci_unmap_single(mgp->pdev, bus, unmap_len, PCI_DMA_FROMDEVICE); | |
979 | ||
980 | /* mcp implicitly skips 1st bytes so that packet is properly | |
981 | * aligned */ | |
982 | skb_reserve(skb, MXGEFW_PAD); | |
983 | ||
984 | /* set the length of the frame */ | |
985 | skb_put(skb, len); | |
986 | ||
987 | skb->protocol = eth_type_trans(skb, mgp->dev); | |
0da34b6d BG |
988 | if (mgp->csum_flag) { |
989 | if ((skb->protocol == ntohs(ETH_P_IP)) || | |
990 | (skb->protocol == ntohs(ETH_P_IPV6))) { | |
991 | skb->csum = ntohs((u16) csum); | |
992 | skb->ip_summed = CHECKSUM_HW; | |
993 | } else | |
994 | myri10ge_vlan_ip_csum(skb, ntohs((u16) csum)); | |
995 | } | |
996 | ||
997 | netif_receive_skb(skb); | |
998 | mgp->dev->last_rx = jiffies; | |
999 | return 1; | |
1000 | } | |
1001 | ||
1002 | static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index) | |
1003 | { | |
1004 | struct pci_dev *pdev = mgp->pdev; | |
1005 | struct myri10ge_tx_buf *tx = &mgp->tx; | |
1006 | struct sk_buff *skb; | |
1007 | int idx, len; | |
1008 | int limit = 0; | |
1009 | ||
1010 | while (tx->pkt_done != mcp_index) { | |
1011 | idx = tx->done & tx->mask; | |
1012 | skb = tx->info[idx].skb; | |
1013 | ||
1014 | /* Mark as free */ | |
1015 | tx->info[idx].skb = NULL; | |
1016 | if (tx->info[idx].last) { | |
1017 | tx->pkt_done++; | |
1018 | tx->info[idx].last = 0; | |
1019 | } | |
1020 | tx->done++; | |
1021 | len = pci_unmap_len(&tx->info[idx], len); | |
1022 | pci_unmap_len_set(&tx->info[idx], len, 0); | |
1023 | if (skb) { | |
1024 | mgp->stats.tx_bytes += skb->len; | |
1025 | mgp->stats.tx_packets++; | |
1026 | dev_kfree_skb_irq(skb); | |
1027 | if (len) | |
1028 | pci_unmap_single(pdev, | |
1029 | pci_unmap_addr(&tx->info[idx], | |
1030 | bus), len, | |
1031 | PCI_DMA_TODEVICE); | |
1032 | } else { | |
1033 | if (len) | |
1034 | pci_unmap_page(pdev, | |
1035 | pci_unmap_addr(&tx->info[idx], | |
1036 | bus), len, | |
1037 | PCI_DMA_TODEVICE); | |
1038 | } | |
1039 | ||
1040 | /* limit potential for livelock by only handling | |
1041 | * 2 full tx rings per call */ | |
1042 | if (unlikely(++limit > 2 * tx->mask)) | |
1043 | break; | |
1044 | } | |
1045 | /* start the queue if we've stopped it */ | |
1046 | if (netif_queue_stopped(mgp->dev) | |
1047 | && tx->req - tx->done < (tx->mask >> 1)) { | |
1048 | mgp->wake_queue++; | |
1049 | netif_wake_queue(mgp->dev); | |
1050 | } | |
1051 | } | |
1052 | ||
1053 | static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit) | |
1054 | { | |
1055 | struct myri10ge_rx_done *rx_done = &mgp->rx_done; | |
1056 | unsigned long rx_bytes = 0; | |
1057 | unsigned long rx_packets = 0; | |
1058 | unsigned long rx_ok; | |
1059 | ||
1060 | int idx = rx_done->idx; | |
1061 | int cnt = rx_done->cnt; | |
1062 | u16 length; | |
1063 | u16 checksum; | |
1064 | ||
1065 | while (rx_done->entry[idx].length != 0 && *limit != 0) { | |
1066 | length = ntohs(rx_done->entry[idx].length); | |
1067 | rx_done->entry[idx].length = 0; | |
1068 | checksum = ntohs(rx_done->entry[idx].checksum); | |
1069 | if (length <= mgp->small_bytes) | |
1070 | rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small, | |
1071 | mgp->small_bytes, | |
1072 | length, checksum); | |
1073 | else | |
1074 | rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big, | |
1075 | mgp->dev->mtu + ETH_HLEN, | |
1076 | length, checksum); | |
1077 | rx_packets += rx_ok; | |
1078 | rx_bytes += rx_ok * (unsigned long)length; | |
1079 | cnt++; | |
1080 | idx = cnt & (myri10ge_max_intr_slots - 1); | |
1081 | ||
1082 | /* limit potential for livelock by only handling a | |
1083 | * limited number of frames. */ | |
1084 | (*limit)--; | |
1085 | } | |
1086 | rx_done->idx = idx; | |
1087 | rx_done->cnt = cnt; | |
1088 | mgp->stats.rx_packets += rx_packets; | |
1089 | mgp->stats.rx_bytes += rx_bytes; | |
1090 | } | |
1091 | ||
1092 | static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp) | |
1093 | { | |
1094 | struct mcp_irq_data *stats = mgp->fw_stats; | |
1095 | ||
1096 | if (unlikely(stats->stats_updated)) { | |
1097 | if (mgp->link_state != stats->link_up) { | |
1098 | mgp->link_state = stats->link_up; | |
1099 | if (mgp->link_state) { | |
c58ac5ca BG |
1100 | if (netif_msg_link(mgp)) |
1101 | printk(KERN_INFO | |
1102 | "myri10ge: %s: link up\n", | |
1103 | mgp->dev->name); | |
0da34b6d | 1104 | netif_carrier_on(mgp->dev); |
c58ac5ca | 1105 | mgp->link_changes++; |
0da34b6d | 1106 | } else { |
c58ac5ca BG |
1107 | if (netif_msg_link(mgp)) |
1108 | printk(KERN_INFO | |
1109 | "myri10ge: %s: link down\n", | |
1110 | mgp->dev->name); | |
0da34b6d | 1111 | netif_carrier_off(mgp->dev); |
c58ac5ca | 1112 | mgp->link_changes++; |
0da34b6d BG |
1113 | } |
1114 | } | |
1115 | if (mgp->rdma_tags_available != | |
1116 | ntohl(mgp->fw_stats->rdma_tags_available)) { | |
1117 | mgp->rdma_tags_available = | |
1118 | ntohl(mgp->fw_stats->rdma_tags_available); | |
1119 | printk(KERN_WARNING "myri10ge: %s: RDMA timed out! " | |
1120 | "%d tags left\n", mgp->dev->name, | |
1121 | mgp->rdma_tags_available); | |
1122 | } | |
1123 | mgp->down_cnt += stats->link_down; | |
1124 | if (stats->link_down) | |
1125 | wake_up(&mgp->down_wq); | |
1126 | } | |
1127 | } | |
1128 | ||
1129 | static int myri10ge_poll(struct net_device *netdev, int *budget) | |
1130 | { | |
1131 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1132 | struct myri10ge_rx_done *rx_done = &mgp->rx_done; | |
1133 | int limit, orig_limit, work_done; | |
1134 | ||
1135 | /* process as many rx events as NAPI will allow */ | |
1136 | limit = min(*budget, netdev->quota); | |
1137 | orig_limit = limit; | |
1138 | myri10ge_clean_rx_done(mgp, &limit); | |
1139 | work_done = orig_limit - limit; | |
1140 | *budget -= work_done; | |
1141 | netdev->quota -= work_done; | |
1142 | ||
1143 | if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) { | |
1144 | netif_rx_complete(netdev); | |
1145 | __raw_writel(htonl(3), mgp->irq_claim); | |
1146 | return 0; | |
1147 | } | |
1148 | return 1; | |
1149 | } | |
1150 | ||
1151 | static irqreturn_t myri10ge_intr(int irq, void *arg, struct pt_regs *regs) | |
1152 | { | |
1153 | struct myri10ge_priv *mgp = arg; | |
1154 | struct mcp_irq_data *stats = mgp->fw_stats; | |
1155 | struct myri10ge_tx_buf *tx = &mgp->tx; | |
1156 | u32 send_done_count; | |
1157 | int i; | |
1158 | ||
1159 | /* make sure it is our IRQ, and that the DMA has finished */ | |
1160 | if (unlikely(!stats->valid)) | |
1161 | return (IRQ_NONE); | |
1162 | ||
1163 | /* low bit indicates receives are present, so schedule | |
1164 | * napi poll handler */ | |
1165 | if (stats->valid & 1) | |
1166 | netif_rx_schedule(mgp->dev); | |
1167 | ||
1168 | if (!mgp->msi_enabled) { | |
1169 | __raw_writel(0, mgp->irq_deassert); | |
1170 | if (!myri10ge_deassert_wait) | |
1171 | stats->valid = 0; | |
1172 | mb(); | |
1173 | } else | |
1174 | stats->valid = 0; | |
1175 | ||
1176 | /* Wait for IRQ line to go low, if using INTx */ | |
1177 | i = 0; | |
1178 | while (1) { | |
1179 | i++; | |
1180 | /* check for transmit completes and receives */ | |
1181 | send_done_count = ntohl(stats->send_done_count); | |
1182 | if (send_done_count != tx->pkt_done) | |
1183 | myri10ge_tx_done(mgp, (int)send_done_count); | |
1184 | if (unlikely(i > myri10ge_max_irq_loops)) { | |
1185 | printk(KERN_WARNING "myri10ge: %s: irq stuck?\n", | |
1186 | mgp->dev->name); | |
1187 | stats->valid = 0; | |
1188 | schedule_work(&mgp->watchdog_work); | |
1189 | } | |
1190 | if (likely(stats->valid == 0)) | |
1191 | break; | |
1192 | cpu_relax(); | |
1193 | barrier(); | |
1194 | } | |
1195 | ||
1196 | myri10ge_check_statblock(mgp); | |
1197 | ||
1198 | __raw_writel(htonl(3), mgp->irq_claim + 1); | |
1199 | return (IRQ_HANDLED); | |
1200 | } | |
1201 | ||
1202 | static int | |
1203 | myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
1204 | { | |
1205 | cmd->autoneg = AUTONEG_DISABLE; | |
1206 | cmd->speed = SPEED_10000; | |
1207 | cmd->duplex = DUPLEX_FULL; | |
1208 | return 0; | |
1209 | } | |
1210 | ||
1211 | static void | |
1212 | myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info) | |
1213 | { | |
1214 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1215 | ||
1216 | strlcpy(info->driver, "myri10ge", sizeof(info->driver)); | |
1217 | strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version)); | |
1218 | strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version)); | |
1219 | strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info)); | |
1220 | } | |
1221 | ||
1222 | static int | |
1223 | myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal) | |
1224 | { | |
1225 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1226 | coal->rx_coalesce_usecs = mgp->intr_coal_delay; | |
1227 | return 0; | |
1228 | } | |
1229 | ||
1230 | static int | |
1231 | myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal) | |
1232 | { | |
1233 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1234 | ||
1235 | mgp->intr_coal_delay = coal->rx_coalesce_usecs; | |
1236 | __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr); | |
1237 | return 0; | |
1238 | } | |
1239 | ||
1240 | static void | |
1241 | myri10ge_get_pauseparam(struct net_device *netdev, | |
1242 | struct ethtool_pauseparam *pause) | |
1243 | { | |
1244 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1245 | ||
1246 | pause->autoneg = 0; | |
1247 | pause->rx_pause = mgp->pause; | |
1248 | pause->tx_pause = mgp->pause; | |
1249 | } | |
1250 | ||
1251 | static int | |
1252 | myri10ge_set_pauseparam(struct net_device *netdev, | |
1253 | struct ethtool_pauseparam *pause) | |
1254 | { | |
1255 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1256 | ||
1257 | if (pause->tx_pause != mgp->pause) | |
1258 | return myri10ge_change_pause(mgp, pause->tx_pause); | |
1259 | if (pause->rx_pause != mgp->pause) | |
1260 | return myri10ge_change_pause(mgp, pause->tx_pause); | |
1261 | if (pause->autoneg != 0) | |
1262 | return -EINVAL; | |
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | static void | |
1267 | myri10ge_get_ringparam(struct net_device *netdev, | |
1268 | struct ethtool_ringparam *ring) | |
1269 | { | |
1270 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1271 | ||
1272 | ring->rx_mini_max_pending = mgp->rx_small.mask + 1; | |
1273 | ring->rx_max_pending = mgp->rx_big.mask + 1; | |
1274 | ring->rx_jumbo_max_pending = 0; | |
1275 | ring->tx_max_pending = mgp->rx_small.mask + 1; | |
1276 | ring->rx_mini_pending = ring->rx_mini_max_pending; | |
1277 | ring->rx_pending = ring->rx_max_pending; | |
1278 | ring->rx_jumbo_pending = ring->rx_jumbo_max_pending; | |
1279 | ring->tx_pending = ring->tx_max_pending; | |
1280 | } | |
1281 | ||
1282 | static u32 myri10ge_get_rx_csum(struct net_device *netdev) | |
1283 | { | |
1284 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1285 | if (mgp->csum_flag) | |
1286 | return 1; | |
1287 | else | |
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled) | |
1292 | { | |
1293 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1294 | if (csum_enabled) | |
1295 | mgp->csum_flag = MXGEFW_FLAGS_CKSUM; | |
1296 | else | |
1297 | mgp->csum_flag = 0; | |
1298 | return 0; | |
1299 | } | |
1300 | ||
1301 | static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = { | |
1302 | "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors", | |
1303 | "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions", | |
1304 | "rx_length_errors", "rx_over_errors", "rx_crc_errors", | |
1305 | "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors", | |
1306 | "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors", | |
1307 | "tx_heartbeat_errors", "tx_window_errors", | |
1308 | /* device-specific stats */ | |
2c1a1088 | 1309 | "tx_boundary", "WC", "irq", "MSI", |
0da34b6d BG |
1310 | "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs", |
1311 | "serial_number", "tx_pkt_start", "tx_pkt_done", | |
1312 | "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt", | |
1313 | "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized", | |
c58ac5ca | 1314 | "link_changes", "link_up", "dropped_link_overflow", |
85a7ea1b BG |
1315 | "dropped_link_error_or_filtered", "dropped_multicast_filtered", |
1316 | "dropped_runt", "dropped_overrun", "dropped_no_small_buffer", | |
0da34b6d BG |
1317 | "dropped_no_big_buffer" |
1318 | }; | |
1319 | ||
1320 | #define MYRI10GE_NET_STATS_LEN 21 | |
1321 | #define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN | |
1322 | ||
1323 | static void | |
1324 | myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data) | |
1325 | { | |
1326 | switch (stringset) { | |
1327 | case ETH_SS_STATS: | |
1328 | memcpy(data, *myri10ge_gstrings_stats, | |
1329 | sizeof(myri10ge_gstrings_stats)); | |
1330 | break; | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | static int myri10ge_get_stats_count(struct net_device *netdev) | |
1335 | { | |
1336 | return MYRI10GE_STATS_LEN; | |
1337 | } | |
1338 | ||
1339 | static void | |
1340 | myri10ge_get_ethtool_stats(struct net_device *netdev, | |
1341 | struct ethtool_stats *stats, u64 * data) | |
1342 | { | |
1343 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1344 | int i; | |
1345 | ||
1346 | for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++) | |
1347 | data[i] = ((unsigned long *)&mgp->stats)[i]; | |
1348 | ||
2c1a1088 BG |
1349 | data[i++] = (unsigned int)mgp->tx.boundary; |
1350 | data[i++] = (unsigned int)(mgp->mtrr >= 0); | |
1351 | data[i++] = (unsigned int)mgp->pdev->irq; | |
1352 | data[i++] = (unsigned int)mgp->msi_enabled; | |
0da34b6d BG |
1353 | data[i++] = (unsigned int)mgp->read_dma; |
1354 | data[i++] = (unsigned int)mgp->write_dma; | |
1355 | data[i++] = (unsigned int)mgp->read_write_dma; | |
1356 | data[i++] = (unsigned int)mgp->serial_number; | |
1357 | data[i++] = (unsigned int)mgp->tx.pkt_start; | |
1358 | data[i++] = (unsigned int)mgp->tx.pkt_done; | |
1359 | data[i++] = (unsigned int)mgp->tx.req; | |
1360 | data[i++] = (unsigned int)mgp->tx.done; | |
1361 | data[i++] = (unsigned int)mgp->rx_small.cnt; | |
1362 | data[i++] = (unsigned int)mgp->rx_big.cnt; | |
1363 | data[i++] = (unsigned int)mgp->wake_queue; | |
1364 | data[i++] = (unsigned int)mgp->stop_queue; | |
1365 | data[i++] = (unsigned int)mgp->watchdog_resets; | |
1366 | data[i++] = (unsigned int)mgp->tx_linearized; | |
c58ac5ca | 1367 | data[i++] = (unsigned int)mgp->link_changes; |
0da34b6d BG |
1368 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up); |
1369 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow); | |
1370 | data[i++] = | |
1371 | (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered); | |
85a7ea1b BG |
1372 | data[i++] = |
1373 | (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered); | |
0da34b6d BG |
1374 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt); |
1375 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun); | |
1376 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer); | |
1377 | data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer); | |
1378 | } | |
1379 | ||
c58ac5ca BG |
1380 | static void myri10ge_set_msglevel(struct net_device *netdev, u32 value) |
1381 | { | |
1382 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1383 | mgp->msg_enable = value; | |
1384 | } | |
1385 | ||
1386 | static u32 myri10ge_get_msglevel(struct net_device *netdev) | |
1387 | { | |
1388 | struct myri10ge_priv *mgp = netdev_priv(netdev); | |
1389 | return mgp->msg_enable; | |
1390 | } | |
1391 | ||
7282d491 | 1392 | static const struct ethtool_ops myri10ge_ethtool_ops = { |
0da34b6d BG |
1393 | .get_settings = myri10ge_get_settings, |
1394 | .get_drvinfo = myri10ge_get_drvinfo, | |
1395 | .get_coalesce = myri10ge_get_coalesce, | |
1396 | .set_coalesce = myri10ge_set_coalesce, | |
1397 | .get_pauseparam = myri10ge_get_pauseparam, | |
1398 | .set_pauseparam = myri10ge_set_pauseparam, | |
1399 | .get_ringparam = myri10ge_get_ringparam, | |
1400 | .get_rx_csum = myri10ge_get_rx_csum, | |
1401 | .set_rx_csum = myri10ge_set_rx_csum, | |
1402 | .get_tx_csum = ethtool_op_get_tx_csum, | |
b10c0668 | 1403 | .set_tx_csum = ethtool_op_set_tx_hw_csum, |
0da34b6d BG |
1404 | .get_sg = ethtool_op_get_sg, |
1405 | .set_sg = ethtool_op_set_sg, | |
1406 | #ifdef NETIF_F_TSO | |
1407 | .get_tso = ethtool_op_get_tso, | |
1408 | .set_tso = ethtool_op_set_tso, | |
1409 | #endif | |
1410 | .get_strings = myri10ge_get_strings, | |
1411 | .get_stats_count = myri10ge_get_stats_count, | |
c58ac5ca BG |
1412 | .get_ethtool_stats = myri10ge_get_ethtool_stats, |
1413 | .set_msglevel = myri10ge_set_msglevel, | |
1414 | .get_msglevel = myri10ge_get_msglevel | |
0da34b6d BG |
1415 | }; |
1416 | ||
1417 | static int myri10ge_allocate_rings(struct net_device *dev) | |
1418 | { | |
1419 | struct myri10ge_priv *mgp; | |
1420 | struct myri10ge_cmd cmd; | |
1421 | int tx_ring_size, rx_ring_size; | |
1422 | int tx_ring_entries, rx_ring_entries; | |
1423 | int i, status; | |
1424 | size_t bytes; | |
1425 | ||
1426 | mgp = netdev_priv(dev); | |
1427 | ||
1428 | /* get ring sizes */ | |
1429 | ||
1430 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0); | |
1431 | tx_ring_size = cmd.data0; | |
1432 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0); | |
1433 | rx_ring_size = cmd.data0; | |
1434 | ||
1435 | tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send); | |
1436 | rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr); | |
1437 | mgp->tx.mask = tx_ring_entries - 1; | |
1438 | mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1; | |
1439 | ||
1440 | /* allocate the host shadow rings */ | |
1441 | ||
1442 | bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4) | |
1443 | * sizeof(*mgp->tx.req_list); | |
1444 | mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL); | |
1445 | if (mgp->tx.req_bytes == NULL) | |
1446 | goto abort_with_nothing; | |
1447 | ||
1448 | /* ensure req_list entries are aligned to 8 bytes */ | |
1449 | mgp->tx.req_list = (struct mcp_kreq_ether_send *) | |
1450 | ALIGN((unsigned long)mgp->tx.req_bytes, 8); | |
1451 | ||
1452 | bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow); | |
1453 | mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL); | |
1454 | if (mgp->rx_small.shadow == NULL) | |
1455 | goto abort_with_tx_req_bytes; | |
1456 | ||
1457 | bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow); | |
1458 | mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL); | |
1459 | if (mgp->rx_big.shadow == NULL) | |
1460 | goto abort_with_rx_small_shadow; | |
1461 | ||
1462 | /* allocate the host info rings */ | |
1463 | ||
1464 | bytes = tx_ring_entries * sizeof(*mgp->tx.info); | |
1465 | mgp->tx.info = kzalloc(bytes, GFP_KERNEL); | |
1466 | if (mgp->tx.info == NULL) | |
1467 | goto abort_with_rx_big_shadow; | |
1468 | ||
1469 | bytes = rx_ring_entries * sizeof(*mgp->rx_small.info); | |
1470 | mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL); | |
1471 | if (mgp->rx_small.info == NULL) | |
1472 | goto abort_with_tx_info; | |
1473 | ||
1474 | bytes = rx_ring_entries * sizeof(*mgp->rx_big.info); | |
1475 | mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL); | |
1476 | if (mgp->rx_big.info == NULL) | |
1477 | goto abort_with_rx_small_info; | |
1478 | ||
1479 | /* Fill the receive rings */ | |
1480 | ||
1481 | for (i = 0; i <= mgp->rx_small.mask; i++) { | |
fd6746da | 1482 | status = myri10ge_getbuf(&mgp->rx_small, mgp, |
0da34b6d BG |
1483 | mgp->small_bytes, i); |
1484 | if (status) { | |
1485 | printk(KERN_ERR | |
1486 | "myri10ge: %s: alloced only %d small bufs\n", | |
1487 | dev->name, i); | |
1488 | goto abort_with_rx_small_ring; | |
1489 | } | |
1490 | } | |
1491 | ||
1492 | for (i = 0; i <= mgp->rx_big.mask; i++) { | |
1493 | status = | |
fd6746da | 1494 | myri10ge_getbuf(&mgp->rx_big, mgp, dev->mtu + ETH_HLEN, i); |
0da34b6d BG |
1495 | if (status) { |
1496 | printk(KERN_ERR | |
1497 | "myri10ge: %s: alloced only %d big bufs\n", | |
1498 | dev->name, i); | |
1499 | goto abort_with_rx_big_ring; | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | return 0; | |
1504 | ||
1505 | abort_with_rx_big_ring: | |
1506 | for (i = 0; i <= mgp->rx_big.mask; i++) { | |
1507 | if (mgp->rx_big.info[i].skb != NULL) | |
1508 | dev_kfree_skb_any(mgp->rx_big.info[i].skb); | |
1509 | if (pci_unmap_len(&mgp->rx_big.info[i], len)) | |
1510 | pci_unmap_single(mgp->pdev, | |
1511 | pci_unmap_addr(&mgp->rx_big.info[i], | |
1512 | bus), | |
1513 | pci_unmap_len(&mgp->rx_big.info[i], | |
1514 | len), | |
1515 | PCI_DMA_FROMDEVICE); | |
1516 | } | |
1517 | ||
1518 | abort_with_rx_small_ring: | |
1519 | for (i = 0; i <= mgp->rx_small.mask; i++) { | |
1520 | if (mgp->rx_small.info[i].skb != NULL) | |
1521 | dev_kfree_skb_any(mgp->rx_small.info[i].skb); | |
1522 | if (pci_unmap_len(&mgp->rx_small.info[i], len)) | |
1523 | pci_unmap_single(mgp->pdev, | |
1524 | pci_unmap_addr(&mgp->rx_small.info[i], | |
1525 | bus), | |
1526 | pci_unmap_len(&mgp->rx_small.info[i], | |
1527 | len), | |
1528 | PCI_DMA_FROMDEVICE); | |
1529 | } | |
1530 | kfree(mgp->rx_big.info); | |
1531 | ||
1532 | abort_with_rx_small_info: | |
1533 | kfree(mgp->rx_small.info); | |
1534 | ||
1535 | abort_with_tx_info: | |
1536 | kfree(mgp->tx.info); | |
1537 | ||
1538 | abort_with_rx_big_shadow: | |
1539 | kfree(mgp->rx_big.shadow); | |
1540 | ||
1541 | abort_with_rx_small_shadow: | |
1542 | kfree(mgp->rx_small.shadow); | |
1543 | ||
1544 | abort_with_tx_req_bytes: | |
1545 | kfree(mgp->tx.req_bytes); | |
1546 | mgp->tx.req_bytes = NULL; | |
1547 | mgp->tx.req_list = NULL; | |
1548 | ||
1549 | abort_with_nothing: | |
1550 | return status; | |
1551 | } | |
1552 | ||
1553 | static void myri10ge_free_rings(struct net_device *dev) | |
1554 | { | |
1555 | struct myri10ge_priv *mgp; | |
1556 | struct sk_buff *skb; | |
1557 | struct myri10ge_tx_buf *tx; | |
1558 | int i, len, idx; | |
1559 | ||
1560 | mgp = netdev_priv(dev); | |
1561 | ||
1562 | for (i = 0; i <= mgp->rx_big.mask; i++) { | |
1563 | if (mgp->rx_big.info[i].skb != NULL) | |
1564 | dev_kfree_skb_any(mgp->rx_big.info[i].skb); | |
1565 | if (pci_unmap_len(&mgp->rx_big.info[i], len)) | |
1566 | pci_unmap_single(mgp->pdev, | |
1567 | pci_unmap_addr(&mgp->rx_big.info[i], | |
1568 | bus), | |
1569 | pci_unmap_len(&mgp->rx_big.info[i], | |
1570 | len), | |
1571 | PCI_DMA_FROMDEVICE); | |
1572 | } | |
1573 | ||
1574 | for (i = 0; i <= mgp->rx_small.mask; i++) { | |
1575 | if (mgp->rx_small.info[i].skb != NULL) | |
1576 | dev_kfree_skb_any(mgp->rx_small.info[i].skb); | |
1577 | if (pci_unmap_len(&mgp->rx_small.info[i], len)) | |
1578 | pci_unmap_single(mgp->pdev, | |
1579 | pci_unmap_addr(&mgp->rx_small.info[i], | |
1580 | bus), | |
1581 | pci_unmap_len(&mgp->rx_small.info[i], | |
1582 | len), | |
1583 | PCI_DMA_FROMDEVICE); | |
1584 | } | |
1585 | ||
1586 | tx = &mgp->tx; | |
1587 | while (tx->done != tx->req) { | |
1588 | idx = tx->done & tx->mask; | |
1589 | skb = tx->info[idx].skb; | |
1590 | ||
1591 | /* Mark as free */ | |
1592 | tx->info[idx].skb = NULL; | |
1593 | tx->done++; | |
1594 | len = pci_unmap_len(&tx->info[idx], len); | |
1595 | pci_unmap_len_set(&tx->info[idx], len, 0); | |
1596 | if (skb) { | |
1597 | mgp->stats.tx_dropped++; | |
1598 | dev_kfree_skb_any(skb); | |
1599 | if (len) | |
1600 | pci_unmap_single(mgp->pdev, | |
1601 | pci_unmap_addr(&tx->info[idx], | |
1602 | bus), len, | |
1603 | PCI_DMA_TODEVICE); | |
1604 | } else { | |
1605 | if (len) | |
1606 | pci_unmap_page(mgp->pdev, | |
1607 | pci_unmap_addr(&tx->info[idx], | |
1608 | bus), len, | |
1609 | PCI_DMA_TODEVICE); | |
1610 | } | |
1611 | } | |
1612 | kfree(mgp->rx_big.info); | |
1613 | ||
1614 | kfree(mgp->rx_small.info); | |
1615 | ||
1616 | kfree(mgp->tx.info); | |
1617 | ||
1618 | kfree(mgp->rx_big.shadow); | |
1619 | ||
1620 | kfree(mgp->rx_small.shadow); | |
1621 | ||
1622 | kfree(mgp->tx.req_bytes); | |
1623 | mgp->tx.req_bytes = NULL; | |
1624 | mgp->tx.req_list = NULL; | |
1625 | } | |
1626 | ||
1627 | static int myri10ge_open(struct net_device *dev) | |
1628 | { | |
1629 | struct myri10ge_priv *mgp; | |
1630 | struct myri10ge_cmd cmd; | |
1631 | int status, big_pow2; | |
1632 | ||
1633 | mgp = netdev_priv(dev); | |
1634 | ||
1635 | if (mgp->running != MYRI10GE_ETH_STOPPED) | |
1636 | return -EBUSY; | |
1637 | ||
1638 | mgp->running = MYRI10GE_ETH_STARTING; | |
1639 | status = myri10ge_reset(mgp); | |
1640 | if (status != 0) { | |
1641 | printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name); | |
1642 | mgp->running = MYRI10GE_ETH_STOPPED; | |
1643 | return -ENXIO; | |
1644 | } | |
1645 | ||
1646 | /* decide what small buffer size to use. For good TCP rx | |
1647 | * performance, it is important to not receive 1514 byte | |
1648 | * frames into jumbo buffers, as it confuses the socket buffer | |
1649 | * accounting code, leading to drops and erratic performance. | |
1650 | */ | |
1651 | ||
1652 | if (dev->mtu <= ETH_DATA_LEN) | |
1653 | mgp->small_bytes = 128; /* enough for a TCP header */ | |
1654 | else | |
1655 | mgp->small_bytes = ETH_FRAME_LEN; /* enough for an ETH_DATA_LEN frame */ | |
1656 | ||
1657 | /* Override the small buffer size? */ | |
1658 | if (myri10ge_small_bytes > 0) | |
1659 | mgp->small_bytes = myri10ge_small_bytes; | |
1660 | ||
1661 | /* If the user sets an obscenely small MTU, adjust the small | |
1662 | * bytes down to nearly nothing */ | |
1663 | if (mgp->small_bytes >= (dev->mtu + ETH_HLEN)) | |
1664 | mgp->small_bytes = 64; | |
1665 | ||
1666 | /* get the lanai pointers to the send and receive rings */ | |
1667 | ||
1668 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0); | |
1669 | mgp->tx.lanai = | |
1670 | (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0); | |
1671 | ||
1672 | status |= | |
1673 | myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0); | |
1674 | mgp->rx_small.lanai = | |
1675 | (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0); | |
1676 | ||
1677 | status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0); | |
1678 | mgp->rx_big.lanai = | |
1679 | (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0); | |
1680 | ||
1681 | if (status != 0) { | |
1682 | printk(KERN_ERR | |
1683 | "myri10ge: %s: failed to get ring sizes or locations\n", | |
1684 | dev->name); | |
1685 | mgp->running = MYRI10GE_ETH_STOPPED; | |
1686 | return -ENXIO; | |
1687 | } | |
1688 | ||
1689 | if (mgp->mtrr >= 0) { | |
e700f9f4 BG |
1690 | mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4; |
1691 | mgp->rx_small.wc_fifo = | |
1692 | (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL; | |
1693 | mgp->rx_big.wc_fifo = | |
1694 | (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG; | |
0da34b6d BG |
1695 | } else { |
1696 | mgp->tx.wc_fifo = NULL; | |
1697 | mgp->rx_small.wc_fifo = NULL; | |
1698 | mgp->rx_big.wc_fifo = NULL; | |
1699 | } | |
1700 | ||
1701 | status = myri10ge_allocate_rings(dev); | |
1702 | if (status != 0) | |
1703 | goto abort_with_nothing; | |
1704 | ||
1705 | /* Firmware needs the big buff size as a power of 2. Lie and | |
1706 | * tell him the buffer is larger, because we only use 1 | |
1707 | * buffer/pkt, and the mtu will prevent overruns. | |
1708 | */ | |
1709 | big_pow2 = dev->mtu + ETH_HLEN + MXGEFW_PAD; | |
1710 | while ((big_pow2 & (big_pow2 - 1)) != 0) | |
1711 | big_pow2++; | |
1712 | ||
1713 | /* now give firmware buffers sizes, and MTU */ | |
1714 | cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN; | |
1715 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0); | |
1716 | cmd.data0 = mgp->small_bytes; | |
1717 | status |= | |
1718 | myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0); | |
1719 | cmd.data0 = big_pow2; | |
1720 | status |= | |
1721 | myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0); | |
1722 | if (status) { | |
1723 | printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n", | |
1724 | dev->name); | |
1725 | goto abort_with_rings; | |
1726 | } | |
1727 | ||
1728 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus); | |
1729 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus); | |
85a7ea1b BG |
1730 | cmd.data2 = sizeof(struct mcp_irq_data); |
1731 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0); | |
1732 | if (status == -ENOSYS) { | |
1733 | dma_addr_t bus = mgp->fw_stats_bus; | |
1734 | bus += offsetof(struct mcp_irq_data, send_done_count); | |
1735 | cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus); | |
1736 | cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus); | |
1737 | status = myri10ge_send_cmd(mgp, | |
1738 | MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, | |
1739 | &cmd, 0); | |
1740 | /* Firmware cannot support multicast without STATS_DMA_V2 */ | |
1741 | mgp->fw_multicast_support = 0; | |
1742 | } else { | |
1743 | mgp->fw_multicast_support = 1; | |
1744 | } | |
0da34b6d BG |
1745 | if (status) { |
1746 | printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n", | |
1747 | dev->name); | |
1748 | goto abort_with_rings; | |
1749 | } | |
1750 | ||
1751 | mgp->link_state = -1; | |
1752 | mgp->rdma_tags_available = 15; | |
1753 | ||
1754 | netif_poll_enable(mgp->dev); /* must happen prior to any irq */ | |
1755 | ||
1756 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0); | |
1757 | if (status) { | |
1758 | printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n", | |
1759 | dev->name); | |
1760 | goto abort_with_rings; | |
1761 | } | |
1762 | ||
1763 | mgp->wake_queue = 0; | |
1764 | mgp->stop_queue = 0; | |
1765 | mgp->running = MYRI10GE_ETH_RUNNING; | |
1766 | mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ; | |
1767 | add_timer(&mgp->watchdog_timer); | |
1768 | netif_wake_queue(dev); | |
1769 | return 0; | |
1770 | ||
1771 | abort_with_rings: | |
1772 | myri10ge_free_rings(dev); | |
1773 | ||
1774 | abort_with_nothing: | |
1775 | mgp->running = MYRI10GE_ETH_STOPPED; | |
1776 | return -ENOMEM; | |
1777 | } | |
1778 | ||
1779 | static int myri10ge_close(struct net_device *dev) | |
1780 | { | |
1781 | struct myri10ge_priv *mgp; | |
1782 | struct myri10ge_cmd cmd; | |
1783 | int status, old_down_cnt; | |
1784 | ||
1785 | mgp = netdev_priv(dev); | |
1786 | ||
1787 | if (mgp->running != MYRI10GE_ETH_RUNNING) | |
1788 | return 0; | |
1789 | ||
1790 | if (mgp->tx.req_bytes == NULL) | |
1791 | return 0; | |
1792 | ||
1793 | del_timer_sync(&mgp->watchdog_timer); | |
1794 | mgp->running = MYRI10GE_ETH_STOPPING; | |
1795 | netif_poll_disable(mgp->dev); | |
1796 | netif_carrier_off(dev); | |
1797 | netif_stop_queue(dev); | |
1798 | old_down_cnt = mgp->down_cnt; | |
1799 | mb(); | |
1800 | status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0); | |
1801 | if (status) | |
1802 | printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n", | |
1803 | dev->name); | |
1804 | ||
1805 | wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ); | |
1806 | if (old_down_cnt == mgp->down_cnt) | |
1807 | printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name); | |
1808 | ||
1809 | netif_tx_disable(dev); | |
1810 | ||
1811 | myri10ge_free_rings(dev); | |
1812 | ||
1813 | mgp->running = MYRI10GE_ETH_STOPPED; | |
1814 | return 0; | |
1815 | } | |
1816 | ||
1817 | /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy | |
1818 | * backwards one at a time and handle ring wraps */ | |
1819 | ||
1820 | static inline void | |
1821 | myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx, | |
1822 | struct mcp_kreq_ether_send *src, int cnt) | |
1823 | { | |
1824 | int idx, starting_slot; | |
1825 | starting_slot = tx->req; | |
1826 | while (cnt > 1) { | |
1827 | cnt--; | |
1828 | idx = (starting_slot + cnt) & tx->mask; | |
1829 | myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src)); | |
1830 | mb(); | |
1831 | } | |
1832 | } | |
1833 | ||
1834 | /* | |
1835 | * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy | |
1836 | * at most 32 bytes at a time, so as to avoid involving the software | |
1837 | * pio handler in the nic. We re-write the first segment's flags | |
1838 | * to mark them valid only after writing the entire chain. | |
1839 | */ | |
1840 | ||
1841 | static inline void | |
1842 | myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src, | |
1843 | int cnt) | |
1844 | { | |
1845 | int idx, i; | |
1846 | struct mcp_kreq_ether_send __iomem *dstp, *dst; | |
1847 | struct mcp_kreq_ether_send *srcp; | |
1848 | u8 last_flags; | |
1849 | ||
1850 | idx = tx->req & tx->mask; | |
1851 | ||
1852 | last_flags = src->flags; | |
1853 | src->flags = 0; | |
1854 | mb(); | |
1855 | dst = dstp = &tx->lanai[idx]; | |
1856 | srcp = src; | |
1857 | ||
1858 | if ((idx + cnt) < tx->mask) { | |
1859 | for (i = 0; i < (cnt - 1); i += 2) { | |
1860 | myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src)); | |
1861 | mb(); /* force write every 32 bytes */ | |
1862 | srcp += 2; | |
1863 | dstp += 2; | |
1864 | } | |
1865 | } else { | |
1866 | /* submit all but the first request, and ensure | |
1867 | * that it is submitted below */ | |
1868 | myri10ge_submit_req_backwards(tx, src, cnt); | |
1869 | i = 0; | |
1870 | } | |
1871 | if (i < cnt) { | |
1872 | /* submit the first request */ | |
1873 | myri10ge_pio_copy(dstp, srcp, sizeof(*src)); | |
1874 | mb(); /* barrier before setting valid flag */ | |
1875 | } | |
1876 | ||
1877 | /* re-write the last 32-bits with the valid flags */ | |
1878 | src->flags = last_flags; | |
1879 | __raw_writel(*((u32 *) src + 3), (u32 __iomem *) dst + 3); | |
1880 | tx->req += cnt; | |
1881 | mb(); | |
1882 | } | |
1883 | ||
1884 | static inline void | |
1885 | myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx, | |
1886 | struct mcp_kreq_ether_send *src, int cnt) | |
1887 | { | |
1888 | tx->req += cnt; | |
1889 | mb(); | |
1890 | while (cnt >= 4) { | |
1891 | myri10ge_pio_copy(tx->wc_fifo, src, 64); | |
1892 | mb(); | |
1893 | src += 4; | |
1894 | cnt -= 4; | |
1895 | } | |
1896 | if (cnt > 0) { | |
1897 | /* pad it to 64 bytes. The src is 64 bytes bigger than it | |
1898 | * needs to be so that we don't overrun it */ | |
e700f9f4 BG |
1899 | myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt), |
1900 | src, 64); | |
0da34b6d BG |
1901 | mb(); |
1902 | } | |
1903 | } | |
1904 | ||
1905 | /* | |
1906 | * Transmit a packet. We need to split the packet so that a single | |
1907 | * segment does not cross myri10ge->tx.boundary, so this makes segment | |
1908 | * counting tricky. So rather than try to count segments up front, we | |
1909 | * just give up if there are too few segments to hold a reasonably | |
1910 | * fragmented packet currently available. If we run | |
1911 | * out of segments while preparing a packet for DMA, we just linearize | |
1912 | * it and try again. | |
1913 | */ | |
1914 | ||
1915 | static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev) | |
1916 | { | |
1917 | struct myri10ge_priv *mgp = netdev_priv(dev); | |
1918 | struct mcp_kreq_ether_send *req; | |
1919 | struct myri10ge_tx_buf *tx = &mgp->tx; | |
1920 | struct skb_frag_struct *frag; | |
1921 | dma_addr_t bus; | |
1922 | u32 low, high_swapped; | |
1923 | unsigned int len; | |
1924 | int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments; | |
1925 | u16 pseudo_hdr_offset, cksum_offset; | |
1926 | int cum_len, seglen, boundary, rdma_count; | |
1927 | u8 flags, odd_flag; | |
1928 | ||
1929 | again: | |
1930 | req = tx->req_list; | |
1931 | avail = tx->mask - 1 - (tx->req - tx->done); | |
1932 | ||
1933 | mss = 0; | |
1934 | max_segments = MXGEFW_MAX_SEND_DESC; | |
1935 | ||
1936 | #ifdef NETIF_F_TSO | |
1937 | if (skb->len > (dev->mtu + ETH_HLEN)) { | |
7967168c | 1938 | mss = skb_shinfo(skb)->gso_size; |
0da34b6d BG |
1939 | if (mss != 0) |
1940 | max_segments = MYRI10GE_MAX_SEND_DESC_TSO; | |
1941 | } | |
1942 | #endif /*NETIF_F_TSO */ | |
1943 | ||
1944 | if ((unlikely(avail < max_segments))) { | |
1945 | /* we are out of transmit resources */ | |
1946 | mgp->stop_queue++; | |
1947 | netif_stop_queue(dev); | |
1948 | return 1; | |
1949 | } | |
1950 | ||
1951 | /* Setup checksum offloading, if needed */ | |
1952 | cksum_offset = 0; | |
1953 | pseudo_hdr_offset = 0; | |
1954 | odd_flag = 0; | |
1955 | flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST); | |
1956 | if (likely(skb->ip_summed == CHECKSUM_HW)) { | |
1957 | cksum_offset = (skb->h.raw - skb->data); | |
1958 | pseudo_hdr_offset = (skb->h.raw + skb->csum) - skb->data; | |
1959 | /* If the headers are excessively large, then we must | |
1960 | * fall back to a software checksum */ | |
1961 | if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) { | |
1962 | if (skb_checksum_help(skb, 0)) | |
1963 | goto drop; | |
1964 | cksum_offset = 0; | |
1965 | pseudo_hdr_offset = 0; | |
1966 | } else { | |
1967 | pseudo_hdr_offset = htons(pseudo_hdr_offset); | |
1968 | odd_flag = MXGEFW_FLAGS_ALIGN_ODD; | |
1969 | flags |= MXGEFW_FLAGS_CKSUM; | |
1970 | } | |
1971 | } | |
1972 | ||
1973 | cum_len = 0; | |
1974 | ||
1975 | #ifdef NETIF_F_TSO | |
1976 | if (mss) { /* TSO */ | |
1977 | /* this removes any CKSUM flag from before */ | |
1978 | flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST); | |
1979 | ||
1980 | /* negative cum_len signifies to the | |
1981 | * send loop that we are still in the | |
1982 | * header portion of the TSO packet. | |
1983 | * TSO header must be at most 134 bytes long */ | |
1984 | cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2)); | |
1985 | ||
1986 | /* for TSO, pseudo_hdr_offset holds mss. | |
1987 | * The firmware figures out where to put | |
1988 | * the checksum by parsing the header. */ | |
1989 | pseudo_hdr_offset = htons(mss); | |
1990 | } else | |
1991 | #endif /*NETIF_F_TSO */ | |
1992 | /* Mark small packets, and pad out tiny packets */ | |
1993 | if (skb->len <= MXGEFW_SEND_SMALL_SIZE) { | |
1994 | flags |= MXGEFW_FLAGS_SMALL; | |
1995 | ||
1996 | /* pad frames to at least ETH_ZLEN bytes */ | |
1997 | if (unlikely(skb->len < ETH_ZLEN)) { | |
5b057c6b | 1998 | if (skb_padto(skb, ETH_ZLEN)) { |
0da34b6d BG |
1999 | /* The packet is gone, so we must |
2000 | * return 0 */ | |
2001 | mgp->stats.tx_dropped += 1; | |
2002 | return 0; | |
2003 | } | |
2004 | /* adjust the len to account for the zero pad | |
2005 | * so that the nic can know how long it is */ | |
2006 | skb->len = ETH_ZLEN; | |
2007 | } | |
2008 | } | |
2009 | ||
2010 | /* map the skb for DMA */ | |
2011 | len = skb->len - skb->data_len; | |
2012 | idx = tx->req & tx->mask; | |
2013 | tx->info[idx].skb = skb; | |
2014 | bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
2015 | pci_unmap_addr_set(&tx->info[idx], bus, bus); | |
2016 | pci_unmap_len_set(&tx->info[idx], len, len); | |
2017 | ||
2018 | frag_cnt = skb_shinfo(skb)->nr_frags; | |
2019 | frag_idx = 0; | |
2020 | count = 0; | |
2021 | rdma_count = 0; | |
2022 | ||
2023 | /* "rdma_count" is the number of RDMAs belonging to the | |
2024 | * current packet BEFORE the current send request. For | |
2025 | * non-TSO packets, this is equal to "count". | |
2026 | * For TSO packets, rdma_count needs to be reset | |
2027 | * to 0 after a segment cut. | |
2028 | * | |
2029 | * The rdma_count field of the send request is | |
2030 | * the number of RDMAs of the packet starting at | |
2031 | * that request. For TSO send requests with one ore more cuts | |
2032 | * in the middle, this is the number of RDMAs starting | |
2033 | * after the last cut in the request. All previous | |
2034 | * segments before the last cut implicitly have 1 RDMA. | |
2035 | * | |
2036 | * Since the number of RDMAs is not known beforehand, | |
2037 | * it must be filled-in retroactively - after each | |
2038 | * segmentation cut or at the end of the entire packet. | |
2039 | */ | |
2040 | ||
2041 | while (1) { | |
2042 | /* Break the SKB or Fragment up into pieces which | |
2043 | * do not cross mgp->tx.boundary */ | |
2044 | low = MYRI10GE_LOWPART_TO_U32(bus); | |
2045 | high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus)); | |
2046 | while (len) { | |
2047 | u8 flags_next; | |
2048 | int cum_len_next; | |
2049 | ||
2050 | if (unlikely(count == max_segments)) | |
2051 | goto abort_linearize; | |
2052 | ||
2053 | boundary = (low + tx->boundary) & ~(tx->boundary - 1); | |
2054 | seglen = boundary - low; | |
2055 | if (seglen > len) | |
2056 | seglen = len; | |
2057 | flags_next = flags & ~MXGEFW_FLAGS_FIRST; | |
2058 | cum_len_next = cum_len + seglen; | |
2059 | #ifdef NETIF_F_TSO | |
2060 | if (mss) { /* TSO */ | |
2061 | (req - rdma_count)->rdma_count = rdma_count + 1; | |
2062 | ||
2063 | if (likely(cum_len >= 0)) { /* payload */ | |
2064 | int next_is_first, chop; | |
2065 | ||
2066 | chop = (cum_len_next > mss); | |
2067 | cum_len_next = cum_len_next % mss; | |
2068 | next_is_first = (cum_len_next == 0); | |
2069 | flags |= chop * MXGEFW_FLAGS_TSO_CHOP; | |
2070 | flags_next |= next_is_first * | |
2071 | MXGEFW_FLAGS_FIRST; | |
2072 | rdma_count |= -(chop | next_is_first); | |
2073 | rdma_count += chop & !next_is_first; | |
2074 | } else if (likely(cum_len_next >= 0)) { /* header ends */ | |
2075 | int small; | |
2076 | ||
2077 | rdma_count = -1; | |
2078 | cum_len_next = 0; | |
2079 | seglen = -cum_len; | |
2080 | small = (mss <= MXGEFW_SEND_SMALL_SIZE); | |
2081 | flags_next = MXGEFW_FLAGS_TSO_PLD | | |
2082 | MXGEFW_FLAGS_FIRST | | |
2083 | (small * MXGEFW_FLAGS_SMALL); | |
2084 | } | |
2085 | } | |
2086 | #endif /* NETIF_F_TSO */ | |
2087 | req->addr_high = high_swapped; | |
2088 | req->addr_low = htonl(low); | |
2089 | req->pseudo_hdr_offset = pseudo_hdr_offset; | |
2090 | req->pad = 0; /* complete solid 16-byte block; does this matter? */ | |
2091 | req->rdma_count = 1; | |
2092 | req->length = htons(seglen); | |
2093 | req->cksum_offset = cksum_offset; | |
2094 | req->flags = flags | ((cum_len & 1) * odd_flag); | |
2095 | ||
2096 | low += seglen; | |
2097 | len -= seglen; | |
2098 | cum_len = cum_len_next; | |
2099 | flags = flags_next; | |
2100 | req++; | |
2101 | count++; | |
2102 | rdma_count++; | |
2103 | if (unlikely(cksum_offset > seglen)) | |
2104 | cksum_offset -= seglen; | |
2105 | else | |
2106 | cksum_offset = 0; | |
2107 | } | |
2108 | if (frag_idx == frag_cnt) | |
2109 | break; | |
2110 | ||
2111 | /* map next fragment for DMA */ | |
2112 | idx = (count + tx->req) & tx->mask; | |
2113 | frag = &skb_shinfo(skb)->frags[frag_idx]; | |
2114 | frag_idx++; | |
2115 | len = frag->size; | |
2116 | bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset, | |
2117 | len, PCI_DMA_TODEVICE); | |
2118 | pci_unmap_addr_set(&tx->info[idx], bus, bus); | |
2119 | pci_unmap_len_set(&tx->info[idx], len, len); | |
2120 | } | |
2121 | ||
2122 | (req - rdma_count)->rdma_count = rdma_count; | |
2123 | #ifdef NETIF_F_TSO | |
2124 | if (mss) | |
2125 | do { | |
2126 | req--; | |
2127 | req->flags |= MXGEFW_FLAGS_TSO_LAST; | |
2128 | } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP | | |
2129 | MXGEFW_FLAGS_FIRST))); | |
2130 | #endif | |
2131 | idx = ((count - 1) + tx->req) & tx->mask; | |
2132 | tx->info[idx].last = 1; | |
2133 | if (tx->wc_fifo == NULL) | |
2134 | myri10ge_submit_req(tx, tx->req_list, count); | |
2135 | else | |
2136 | myri10ge_submit_req_wc(tx, tx->req_list, count); | |
2137 | tx->pkt_start++; | |
2138 | if ((avail - count) < MXGEFW_MAX_SEND_DESC) { | |
2139 | mgp->stop_queue++; | |
2140 | netif_stop_queue(dev); | |
2141 | } | |
2142 | dev->trans_start = jiffies; | |
2143 | return 0; | |
2144 | ||
2145 | abort_linearize: | |
2146 | /* Free any DMA resources we've alloced and clear out the skb | |
2147 | * slot so as to not trip up assertions, and to avoid a | |
2148 | * double-free if linearizing fails */ | |
2149 | ||
2150 | last_idx = (idx + 1) & tx->mask; | |
2151 | idx = tx->req & tx->mask; | |
2152 | tx->info[idx].skb = NULL; | |
2153 | do { | |
2154 | len = pci_unmap_len(&tx->info[idx], len); | |
2155 | if (len) { | |
2156 | if (tx->info[idx].skb != NULL) | |
2157 | pci_unmap_single(mgp->pdev, | |
2158 | pci_unmap_addr(&tx->info[idx], | |
2159 | bus), len, | |
2160 | PCI_DMA_TODEVICE); | |
2161 | else | |
2162 | pci_unmap_page(mgp->pdev, | |
2163 | pci_unmap_addr(&tx->info[idx], | |
2164 | bus), len, | |
2165 | PCI_DMA_TODEVICE); | |
2166 | pci_unmap_len_set(&tx->info[idx], len, 0); | |
2167 | tx->info[idx].skb = NULL; | |
2168 | } | |
2169 | idx = (idx + 1) & tx->mask; | |
2170 | } while (idx != last_idx); | |
89114afd | 2171 | if (skb_is_gso(skb)) { |
0da34b6d BG |
2172 | printk(KERN_ERR |
2173 | "myri10ge: %s: TSO but wanted to linearize?!?!?\n", | |
2174 | mgp->dev->name); | |
2175 | goto drop; | |
2176 | } | |
2177 | ||
bec0e859 | 2178 | if (skb_linearize(skb)) |
0da34b6d BG |
2179 | goto drop; |
2180 | ||
2181 | mgp->tx_linearized++; | |
2182 | goto again; | |
2183 | ||
2184 | drop: | |
2185 | dev_kfree_skb_any(skb); | |
2186 | mgp->stats.tx_dropped += 1; | |
2187 | return 0; | |
2188 | ||
2189 | } | |
2190 | ||
2191 | static struct net_device_stats *myri10ge_get_stats(struct net_device *dev) | |
2192 | { | |
2193 | struct myri10ge_priv *mgp = netdev_priv(dev); | |
2194 | return &mgp->stats; | |
2195 | } | |
2196 | ||
2197 | static void myri10ge_set_multicast_list(struct net_device *dev) | |
2198 | { | |
85a7ea1b BG |
2199 | struct myri10ge_cmd cmd; |
2200 | struct myri10ge_priv *mgp; | |
2201 | struct dev_mc_list *mc_list; | |
2202 | int err; | |
2203 | ||
2204 | mgp = netdev_priv(dev); | |
0da34b6d BG |
2205 | /* can be called from atomic contexts, |
2206 | * pass 1 to force atomicity in myri10ge_send_cmd() */ | |
85a7ea1b BG |
2207 | myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1); |
2208 | ||
2209 | /* This firmware is known to not support multicast */ | |
2210 | if (!mgp->fw_multicast_support) | |
2211 | return; | |
2212 | ||
2213 | /* Disable multicast filtering */ | |
2214 | ||
2215 | err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1); | |
2216 | if (err != 0) { | |
2217 | printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI," | |
2218 | " error status: %d\n", dev->name, err); | |
2219 | goto abort; | |
2220 | } | |
2221 | ||
2222 | if (dev->flags & IFF_ALLMULTI) { | |
2223 | /* request to disable multicast filtering, so quit here */ | |
2224 | return; | |
2225 | } | |
2226 | ||
2227 | /* Flush the filters */ | |
2228 | ||
2229 | err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, | |
2230 | &cmd, 1); | |
2231 | if (err != 0) { | |
2232 | printk(KERN_ERR | |
2233 | "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS" | |
2234 | ", error status: %d\n", dev->name, err); | |
2235 | goto abort; | |
2236 | } | |
2237 | ||
2238 | /* Walk the multicast list, and add each address */ | |
2239 | for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) { | |
2240 | memcpy(&cmd.data0, &mc_list->dmi_addr, 4); | |
2241 | memcpy(&cmd.data1, ((char *)&mc_list->dmi_addr) + 4, 2); | |
2242 | cmd.data0 = htonl(cmd.data0); | |
2243 | cmd.data1 = htonl(cmd.data1); | |
2244 | err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP, | |
2245 | &cmd, 1); | |
2246 | ||
2247 | if (err != 0) { | |
2248 | printk(KERN_ERR "myri10ge: %s: Failed " | |
2249 | "MXGEFW_JOIN_MULTICAST_GROUP, error status:" | |
2250 | "%d\t", dev->name, err); | |
2251 | printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n", | |
2252 | ((unsigned char *)&mc_list->dmi_addr)[0], | |
2253 | ((unsigned char *)&mc_list->dmi_addr)[1], | |
2254 | ((unsigned char *)&mc_list->dmi_addr)[2], | |
2255 | ((unsigned char *)&mc_list->dmi_addr)[3], | |
2256 | ((unsigned char *)&mc_list->dmi_addr)[4], | |
2257 | ((unsigned char *)&mc_list->dmi_addr)[5] | |
2258 | ); | |
2259 | goto abort; | |
2260 | } | |
2261 | } | |
2262 | /* Enable multicast filtering */ | |
2263 | err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1); | |
2264 | if (err != 0) { | |
2265 | printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI," | |
2266 | "error status: %d\n", dev->name, err); | |
2267 | goto abort; | |
2268 | } | |
2269 | ||
2270 | return; | |
2271 | ||
2272 | abort: | |
2273 | return; | |
0da34b6d BG |
2274 | } |
2275 | ||
2276 | static int myri10ge_set_mac_address(struct net_device *dev, void *addr) | |
2277 | { | |
2278 | struct sockaddr *sa = addr; | |
2279 | struct myri10ge_priv *mgp = netdev_priv(dev); | |
2280 | int status; | |
2281 | ||
2282 | if (!is_valid_ether_addr(sa->sa_data)) | |
2283 | return -EADDRNOTAVAIL; | |
2284 | ||
2285 | status = myri10ge_update_mac_address(mgp, sa->sa_data); | |
2286 | if (status != 0) { | |
2287 | printk(KERN_ERR | |
2288 | "myri10ge: %s: changing mac address failed with %d\n", | |
2289 | dev->name, status); | |
2290 | return status; | |
2291 | } | |
2292 | ||
2293 | /* change the dev structure */ | |
2294 | memcpy(dev->dev_addr, sa->sa_data, 6); | |
2295 | return 0; | |
2296 | } | |
2297 | ||
2298 | static int myri10ge_change_mtu(struct net_device *dev, int new_mtu) | |
2299 | { | |
2300 | struct myri10ge_priv *mgp = netdev_priv(dev); | |
2301 | int error = 0; | |
2302 | ||
2303 | if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) { | |
2304 | printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n", | |
2305 | dev->name, new_mtu); | |
2306 | return -EINVAL; | |
2307 | } | |
2308 | printk(KERN_INFO "%s: changing mtu from %d to %d\n", | |
2309 | dev->name, dev->mtu, new_mtu); | |
2310 | if (mgp->running) { | |
2311 | /* if we change the mtu on an active device, we must | |
2312 | * reset the device so the firmware sees the change */ | |
2313 | myri10ge_close(dev); | |
2314 | dev->mtu = new_mtu; | |
2315 | myri10ge_open(dev); | |
2316 | } else | |
2317 | dev->mtu = new_mtu; | |
2318 | ||
2319 | return error; | |
2320 | } | |
2321 | ||
2322 | /* | |
2323 | * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary. | |
2324 | * Only do it if the bridge is a root port since we don't want to disturb | |
2325 | * any other device, except if forced with myri10ge_ecrc_enable > 1. | |
2326 | */ | |
2327 | ||
0da34b6d BG |
2328 | static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp) |
2329 | { | |
2330 | struct pci_dev *bridge = mgp->pdev->bus->self; | |
2331 | struct device *dev = &mgp->pdev->dev; | |
2332 | unsigned cap; | |
2333 | unsigned err_cap; | |
2334 | u16 val; | |
2335 | u8 ext_type; | |
2336 | int ret; | |
2337 | ||
2338 | if (!myri10ge_ecrc_enable || !bridge) | |
2339 | return; | |
2340 | ||
2341 | /* check that the bridge is a root port */ | |
2342 | cap = pci_find_capability(bridge, PCI_CAP_ID_EXP); | |
2343 | pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val); | |
2344 | ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4; | |
2345 | if (ext_type != PCI_EXP_TYPE_ROOT_PORT) { | |
2346 | if (myri10ge_ecrc_enable > 1) { | |
2347 | struct pci_dev *old_bridge = bridge; | |
2348 | ||
2349 | /* Walk the hierarchy up to the root port | |
2350 | * where ECRC has to be enabled */ | |
2351 | do { | |
2352 | bridge = bridge->bus->self; | |
2353 | if (!bridge) { | |
2354 | dev_err(dev, | |
2355 | "Failed to find root port" | |
2356 | " to force ECRC\n"); | |
2357 | return; | |
2358 | } | |
2359 | cap = | |
2360 | pci_find_capability(bridge, PCI_CAP_ID_EXP); | |
2361 | pci_read_config_word(bridge, | |
2362 | cap + PCI_CAP_FLAGS, &val); | |
2363 | ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4; | |
2364 | } while (ext_type != PCI_EXP_TYPE_ROOT_PORT); | |
2365 | ||
2366 | dev_info(dev, | |
2367 | "Forcing ECRC on non-root port %s" | |
2368 | " (enabling on root port %s)\n", | |
2369 | pci_name(old_bridge), pci_name(bridge)); | |
2370 | } else { | |
2371 | dev_err(dev, | |
2372 | "Not enabling ECRC on non-root port %s\n", | |
2373 | pci_name(bridge)); | |
2374 | return; | |
2375 | } | |
2376 | } | |
2377 | ||
2378 | cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR); | |
0da34b6d BG |
2379 | if (!cap) |
2380 | return; | |
2381 | ||
2382 | ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap); | |
2383 | if (ret) { | |
2384 | dev_err(dev, "failed reading ext-conf-space of %s\n", | |
2385 | pci_name(bridge)); | |
2386 | dev_err(dev, "\t pci=nommconf in use? " | |
2387 | "or buggy/incomplete/absent ACPI MCFG attr?\n"); | |
2388 | return; | |
2389 | } | |
2390 | if (!(err_cap & PCI_ERR_CAP_ECRC_GENC)) | |
2391 | return; | |
2392 | ||
2393 | err_cap |= PCI_ERR_CAP_ECRC_GENE; | |
2394 | pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap); | |
2395 | dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge)); | |
2396 | mgp->tx.boundary = 4096; | |
2397 | mgp->fw_name = myri10ge_fw_aligned; | |
2398 | } | |
2399 | ||
2400 | /* | |
2401 | * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput | |
2402 | * when the PCI-E Completion packets are aligned on an 8-byte | |
2403 | * boundary. Some PCI-E chip sets always align Completion packets; on | |
2404 | * the ones that do not, the alignment can be enforced by enabling | |
2405 | * ECRC generation (if supported). | |
2406 | * | |
2407 | * When PCI-E Completion packets are not aligned, it is actually more | |
2408 | * efficient to limit Read-DMA transactions to 2KB, rather than 4KB. | |
2409 | * | |
2410 | * If the driver can neither enable ECRC nor verify that it has | |
2411 | * already been enabled, then it must use a firmware image which works | |
2412 | * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it | |
2413 | * should also ensure that it never gives the device a Read-DMA which is | |
2414 | * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is | |
2415 | * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat) | |
2416 | * firmware image, and set tx.boundary to 4KB. | |
2417 | */ | |
2418 | ||
2419 | #define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132 | |
ce7f9368 BG |
2420 | #define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7 |
2421 | #define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa | |
0da34b6d BG |
2422 | |
2423 | static void myri10ge_select_firmware(struct myri10ge_priv *mgp) | |
2424 | { | |
2425 | struct pci_dev *bridge = mgp->pdev->bus->self; | |
2426 | ||
2427 | mgp->tx.boundary = 2048; | |
2428 | mgp->fw_name = myri10ge_fw_unaligned; | |
2429 | ||
2430 | if (myri10ge_force_firmware == 0) { | |
ce7f9368 BG |
2431 | int link_width, exp_cap; |
2432 | u16 lnk; | |
2433 | ||
2434 | exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP); | |
2435 | pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk); | |
2436 | link_width = (lnk >> 4) & 0x3f; | |
2437 | ||
0da34b6d BG |
2438 | myri10ge_enable_ecrc(mgp); |
2439 | ||
ce7f9368 BG |
2440 | /* Check to see if Link is less than 8 or if the |
2441 | * upstream bridge is known to provide aligned | |
2442 | * completions */ | |
2443 | if (link_width < 8) { | |
2444 | dev_info(&mgp->pdev->dev, "PCIE x%d Link\n", | |
2445 | link_width); | |
2446 | mgp->tx.boundary = 4096; | |
2447 | mgp->fw_name = myri10ge_fw_aligned; | |
2448 | } else if (bridge && | |
2449 | /* ServerWorks HT2000/HT1000 */ | |
2450 | ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS | |
2451 | && bridge->device == | |
2452 | PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE) | |
2453 | /* All Intel E5000 PCIE ports */ | |
2454 | || (bridge->vendor == PCI_VENDOR_ID_INTEL | |
2455 | && bridge->device >= | |
2456 | PCI_DEVICE_ID_INTEL_E5000_PCIE23 | |
2457 | && bridge->device <= | |
2458 | PCI_DEVICE_ID_INTEL_E5000_PCIE47))) { | |
0da34b6d BG |
2459 | dev_info(&mgp->pdev->dev, |
2460 | "Assuming aligned completions (0x%x:0x%x)\n", | |
2461 | bridge->vendor, bridge->device); | |
2462 | mgp->tx.boundary = 4096; | |
2463 | mgp->fw_name = myri10ge_fw_aligned; | |
2464 | } | |
2465 | } else { | |
2466 | if (myri10ge_force_firmware == 1) { | |
2467 | dev_info(&mgp->pdev->dev, | |
2468 | "Assuming aligned completions (forced)\n"); | |
2469 | mgp->tx.boundary = 4096; | |
2470 | mgp->fw_name = myri10ge_fw_aligned; | |
2471 | } else { | |
2472 | dev_info(&mgp->pdev->dev, | |
2473 | "Assuming unaligned completions (forced)\n"); | |
2474 | mgp->tx.boundary = 2048; | |
2475 | mgp->fw_name = myri10ge_fw_unaligned; | |
2476 | } | |
2477 | } | |
2478 | if (myri10ge_fw_name != NULL) { | |
2479 | dev_info(&mgp->pdev->dev, "overriding firmware to %s\n", | |
2480 | myri10ge_fw_name); | |
2481 | mgp->fw_name = myri10ge_fw_name; | |
2482 | } | |
2483 | } | |
2484 | ||
2485 | static void myri10ge_save_state(struct myri10ge_priv *mgp) | |
2486 | { | |
2487 | struct pci_dev *pdev = mgp->pdev; | |
2488 | int cap; | |
2489 | ||
2490 | pci_save_state(pdev); | |
2491 | /* now save PCIe and MSI state that Linux will not | |
2492 | * save for us */ | |
2493 | cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
2494 | pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, &mgp->devctl); | |
2495 | cap = pci_find_capability(pdev, PCI_CAP_ID_MSI); | |
2496 | pci_read_config_word(pdev, cap + PCI_MSI_FLAGS, &mgp->msi_flags); | |
2497 | } | |
2498 | ||
2499 | static void myri10ge_restore_state(struct myri10ge_priv *mgp) | |
2500 | { | |
2501 | struct pci_dev *pdev = mgp->pdev; | |
2502 | int cap; | |
2503 | ||
2504 | /* restore PCIe and MSI state that linux will not */ | |
2505 | cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
2506 | pci_write_config_dword(pdev, cap + PCI_CAP_ID_EXP, mgp->devctl); | |
2507 | cap = pci_find_capability(pdev, PCI_CAP_ID_MSI); | |
2508 | pci_write_config_word(pdev, cap + PCI_MSI_FLAGS, mgp->msi_flags); | |
2509 | ||
2510 | pci_restore_state(pdev); | |
2511 | } | |
2512 | ||
2513 | #ifdef CONFIG_PM | |
2514 | ||
2515 | static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state) | |
2516 | { | |
2517 | struct myri10ge_priv *mgp; | |
2518 | struct net_device *netdev; | |
2519 | ||
2520 | mgp = pci_get_drvdata(pdev); | |
2521 | if (mgp == NULL) | |
2522 | return -EINVAL; | |
2523 | netdev = mgp->dev; | |
2524 | ||
2525 | netif_device_detach(netdev); | |
2526 | if (netif_running(netdev)) { | |
2527 | printk(KERN_INFO "myri10ge: closing %s\n", netdev->name); | |
2528 | rtnl_lock(); | |
2529 | myri10ge_close(netdev); | |
2530 | rtnl_unlock(); | |
2531 | } | |
2532 | myri10ge_dummy_rdma(mgp, 0); | |
2533 | free_irq(pdev->irq, mgp); | |
2534 | myri10ge_save_state(mgp); | |
2535 | pci_disable_device(pdev); | |
2536 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
2537 | return 0; | |
2538 | } | |
2539 | ||
2540 | static int myri10ge_resume(struct pci_dev *pdev) | |
2541 | { | |
2542 | struct myri10ge_priv *mgp; | |
2543 | struct net_device *netdev; | |
2544 | int status; | |
2545 | u16 vendor; | |
2546 | ||
2547 | mgp = pci_get_drvdata(pdev); | |
2548 | if (mgp == NULL) | |
2549 | return -EINVAL; | |
2550 | netdev = mgp->dev; | |
2551 | pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */ | |
2552 | msleep(5); /* give card time to respond */ | |
2553 | pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor); | |
2554 | if (vendor == 0xffff) { | |
2555 | printk(KERN_ERR "myri10ge: %s: device disappeared!\n", | |
2556 | mgp->dev->name); | |
2557 | return -EIO; | |
2558 | } | |
2559 | myri10ge_restore_state(mgp); | |
4c2248cc BG |
2560 | |
2561 | status = pci_enable_device(pdev); | |
2562 | if (status < 0) { | |
2563 | dev_err(&pdev->dev, "failed to enable device\n"); | |
2564 | return -EIO; | |
2565 | } | |
2566 | ||
0da34b6d BG |
2567 | pci_set_master(pdev); |
2568 | ||
1fb9df5d | 2569 | status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED, |
0da34b6d BG |
2570 | netdev->name, mgp); |
2571 | if (status != 0) { | |
2572 | dev_err(&pdev->dev, "failed to allocate IRQ\n"); | |
4c2248cc | 2573 | goto abort_with_enabled; |
0da34b6d BG |
2574 | } |
2575 | ||
2576 | myri10ge_reset(mgp); | |
013b68bf | 2577 | myri10ge_dummy_rdma(mgp, 1); |
0da34b6d BG |
2578 | |
2579 | /* Save configuration space to be restored if the | |
2580 | * nic resets due to a parity error */ | |
2581 | myri10ge_save_state(mgp); | |
2582 | ||
2583 | if (netif_running(netdev)) { | |
2584 | rtnl_lock(); | |
2585 | myri10ge_open(netdev); | |
2586 | rtnl_unlock(); | |
2587 | } | |
2588 | netif_device_attach(netdev); | |
2589 | ||
2590 | return 0; | |
2591 | ||
4c2248cc BG |
2592 | abort_with_enabled: |
2593 | pci_disable_device(pdev); | |
0da34b6d BG |
2594 | return -EIO; |
2595 | ||
2596 | } | |
2597 | ||
2598 | #endif /* CONFIG_PM */ | |
2599 | ||
2600 | static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp) | |
2601 | { | |
2602 | struct pci_dev *pdev = mgp->pdev; | |
2603 | int vs = mgp->vendor_specific_offset; | |
2604 | u32 reboot; | |
2605 | ||
2606 | /*enter read32 mode */ | |
2607 | pci_write_config_byte(pdev, vs + 0x10, 0x3); | |
2608 | ||
2609 | /*read REBOOT_STATUS (0xfffffff0) */ | |
2610 | pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0); | |
2611 | pci_read_config_dword(pdev, vs + 0x14, &reboot); | |
2612 | return reboot; | |
2613 | } | |
2614 | ||
2615 | /* | |
2616 | * This watchdog is used to check whether the board has suffered | |
2617 | * from a parity error and needs to be recovered. | |
2618 | */ | |
2619 | static void myri10ge_watchdog(void *arg) | |
2620 | { | |
2621 | struct myri10ge_priv *mgp = arg; | |
2622 | u32 reboot; | |
2623 | int status; | |
2624 | u16 cmd, vendor; | |
2625 | ||
2626 | mgp->watchdog_resets++; | |
2627 | pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd); | |
2628 | if ((cmd & PCI_COMMAND_MASTER) == 0) { | |
2629 | /* Bus master DMA disabled? Check to see | |
2630 | * if the card rebooted due to a parity error | |
2631 | * For now, just report it */ | |
2632 | reboot = myri10ge_read_reboot(mgp); | |
2633 | printk(KERN_ERR | |
2634 | "myri10ge: %s: NIC rebooted (0x%x), resetting\n", | |
2635 | mgp->dev->name, reboot); | |
2636 | /* | |
2637 | * A rebooted nic will come back with config space as | |
2638 | * it was after power was applied to PCIe bus. | |
2639 | * Attempt to restore config space which was saved | |
2640 | * when the driver was loaded, or the last time the | |
2641 | * nic was resumed from power saving mode. | |
2642 | */ | |
2643 | myri10ge_restore_state(mgp); | |
2644 | } else { | |
2645 | /* if we get back -1's from our slot, perhaps somebody | |
2646 | * powered off our card. Don't try to reset it in | |
2647 | * this case */ | |
2648 | if (cmd == 0xffff) { | |
2649 | pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor); | |
2650 | if (vendor == 0xffff) { | |
2651 | printk(KERN_ERR | |
2652 | "myri10ge: %s: device disappeared!\n", | |
2653 | mgp->dev->name); | |
2654 | return; | |
2655 | } | |
2656 | } | |
2657 | /* Perhaps it is a software error. Try to reset */ | |
2658 | ||
2659 | printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n", | |
2660 | mgp->dev->name); | |
2661 | printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n", | |
2662 | mgp->dev->name, mgp->tx.req, mgp->tx.done, | |
2663 | mgp->tx.pkt_start, mgp->tx.pkt_done, | |
2664 | (int)ntohl(mgp->fw_stats->send_done_count)); | |
2665 | msleep(2000); | |
2666 | printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n", | |
2667 | mgp->dev->name, mgp->tx.req, mgp->tx.done, | |
2668 | mgp->tx.pkt_start, mgp->tx.pkt_done, | |
2669 | (int)ntohl(mgp->fw_stats->send_done_count)); | |
2670 | } | |
2671 | rtnl_lock(); | |
2672 | myri10ge_close(mgp->dev); | |
2673 | status = myri10ge_load_firmware(mgp); | |
2674 | if (status != 0) | |
2675 | printk(KERN_ERR "myri10ge: %s: failed to load firmware\n", | |
2676 | mgp->dev->name); | |
2677 | else | |
2678 | myri10ge_open(mgp->dev); | |
2679 | rtnl_unlock(); | |
2680 | } | |
2681 | ||
2682 | /* | |
2683 | * We use our own timer routine rather than relying upon | |
2684 | * netdev->tx_timeout because we have a very large hardware transmit | |
2685 | * queue. Due to the large queue, the netdev->tx_timeout function | |
2686 | * cannot detect a NIC with a parity error in a timely fashion if the | |
2687 | * NIC is lightly loaded. | |
2688 | */ | |
2689 | static void myri10ge_watchdog_timer(unsigned long arg) | |
2690 | { | |
2691 | struct myri10ge_priv *mgp; | |
2692 | ||
2693 | mgp = (struct myri10ge_priv *)arg; | |
2694 | if (mgp->tx.req != mgp->tx.done && | |
c54772e7 BG |
2695 | mgp->tx.done == mgp->watchdog_tx_done && |
2696 | mgp->watchdog_tx_req != mgp->watchdog_tx_done) | |
0da34b6d BG |
2697 | /* nic seems like it might be stuck.. */ |
2698 | schedule_work(&mgp->watchdog_work); | |
2699 | else | |
2700 | /* rearm timer */ | |
2701 | mod_timer(&mgp->watchdog_timer, | |
2702 | jiffies + myri10ge_watchdog_timeout * HZ); | |
2703 | ||
2704 | mgp->watchdog_tx_done = mgp->tx.done; | |
c54772e7 | 2705 | mgp->watchdog_tx_req = mgp->tx.req; |
0da34b6d BG |
2706 | } |
2707 | ||
2708 | static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
2709 | { | |
2710 | struct net_device *netdev; | |
2711 | struct myri10ge_priv *mgp; | |
2712 | struct device *dev = &pdev->dev; | |
2713 | size_t bytes; | |
2714 | int i; | |
2715 | int status = -ENXIO; | |
2716 | int cap; | |
2717 | int dac_enabled; | |
2718 | u16 val; | |
2719 | ||
2720 | netdev = alloc_etherdev(sizeof(*mgp)); | |
2721 | if (netdev == NULL) { | |
2722 | dev_err(dev, "Could not allocate ethernet device\n"); | |
2723 | return -ENOMEM; | |
2724 | } | |
2725 | ||
2726 | mgp = netdev_priv(netdev); | |
2727 | memset(mgp, 0, sizeof(*mgp)); | |
2728 | mgp->dev = netdev; | |
2729 | mgp->pdev = pdev; | |
2730 | mgp->csum_flag = MXGEFW_FLAGS_CKSUM; | |
2731 | mgp->pause = myri10ge_flow_control; | |
2732 | mgp->intr_coal_delay = myri10ge_intr_coal_delay; | |
c58ac5ca | 2733 | mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT); |
0da34b6d BG |
2734 | init_waitqueue_head(&mgp->down_wq); |
2735 | ||
2736 | if (pci_enable_device(pdev)) { | |
2737 | dev_err(&pdev->dev, "pci_enable_device call failed\n"); | |
2738 | status = -ENODEV; | |
2739 | goto abort_with_netdev; | |
2740 | } | |
2741 | myri10ge_select_firmware(mgp); | |
2742 | ||
2743 | /* Find the vendor-specific cap so we can check | |
2744 | * the reboot register later on */ | |
2745 | mgp->vendor_specific_offset | |
2746 | = pci_find_capability(pdev, PCI_CAP_ID_VNDR); | |
2747 | ||
2748 | /* Set our max read request to 4KB */ | |
2749 | cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
2750 | if (cap < 64) { | |
2751 | dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap); | |
2752 | goto abort_with_netdev; | |
2753 | } | |
2754 | status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val); | |
2755 | if (status != 0) { | |
2756 | dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n", | |
2757 | status); | |
2758 | goto abort_with_netdev; | |
2759 | } | |
2760 | val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12); | |
2761 | status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val); | |
2762 | if (status != 0) { | |
2763 | dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n", | |
2764 | status); | |
2765 | goto abort_with_netdev; | |
2766 | } | |
2767 | ||
2768 | pci_set_master(pdev); | |
2769 | dac_enabled = 1; | |
2770 | status = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | |
2771 | if (status != 0) { | |
2772 | dac_enabled = 0; | |
2773 | dev_err(&pdev->dev, | |
2774 | "64-bit pci address mask was refused, trying 32-bit"); | |
2775 | status = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2776 | } | |
2777 | if (status != 0) { | |
2778 | dev_err(&pdev->dev, "Error %d setting DMA mask\n", status); | |
2779 | goto abort_with_netdev; | |
2780 | } | |
b10c0668 BG |
2781 | mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd), |
2782 | &mgp->cmd_bus, GFP_KERNEL); | |
0da34b6d BG |
2783 | if (mgp->cmd == NULL) |
2784 | goto abort_with_netdev; | |
2785 | ||
b10c0668 BG |
2786 | mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats), |
2787 | &mgp->fw_stats_bus, GFP_KERNEL); | |
0da34b6d BG |
2788 | if (mgp->fw_stats == NULL) |
2789 | goto abort_with_cmd; | |
2790 | ||
2791 | mgp->board_span = pci_resource_len(pdev, 0); | |
2792 | mgp->iomem_base = pci_resource_start(pdev, 0); | |
2793 | mgp->mtrr = -1; | |
2794 | #ifdef CONFIG_MTRR | |
2795 | mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span, | |
2796 | MTRR_TYPE_WRCOMB, 1); | |
2797 | #endif | |
2798 | /* Hack. need to get rid of these magic numbers */ | |
2799 | mgp->sram_size = | |
2800 | 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100; | |
2801 | if (mgp->sram_size > mgp->board_span) { | |
2802 | dev_err(&pdev->dev, "board span %ld bytes too small\n", | |
2803 | mgp->board_span); | |
2804 | goto abort_with_wc; | |
2805 | } | |
2806 | mgp->sram = ioremap(mgp->iomem_base, mgp->board_span); | |
2807 | if (mgp->sram == NULL) { | |
2808 | dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n", | |
2809 | mgp->board_span, mgp->iomem_base); | |
2810 | status = -ENXIO; | |
2811 | goto abort_with_wc; | |
2812 | } | |
2813 | memcpy_fromio(mgp->eeprom_strings, | |
2814 | mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE, | |
2815 | MYRI10GE_EEPROM_STRINGS_SIZE); | |
2816 | memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2); | |
2817 | status = myri10ge_read_mac_addr(mgp); | |
2818 | if (status) | |
2819 | goto abort_with_ioremap; | |
2820 | ||
2821 | for (i = 0; i < ETH_ALEN; i++) | |
2822 | netdev->dev_addr[i] = mgp->mac_addr[i]; | |
2823 | ||
2824 | /* allocate rx done ring */ | |
2825 | bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry); | |
b10c0668 BG |
2826 | mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes, |
2827 | &mgp->rx_done.bus, GFP_KERNEL); | |
0da34b6d BG |
2828 | if (mgp->rx_done.entry == NULL) |
2829 | goto abort_with_ioremap; | |
2830 | memset(mgp->rx_done.entry, 0, bytes); | |
2831 | ||
2832 | status = myri10ge_load_firmware(mgp); | |
2833 | if (status != 0) { | |
2834 | dev_err(&pdev->dev, "failed to load firmware\n"); | |
2835 | goto abort_with_rx_done; | |
2836 | } | |
2837 | ||
2838 | status = myri10ge_reset(mgp); | |
2839 | if (status != 0) { | |
2840 | dev_err(&pdev->dev, "failed reset\n"); | |
2841 | goto abort_with_firmware; | |
2842 | } | |
2843 | ||
2844 | if (myri10ge_msi) { | |
2845 | status = pci_enable_msi(pdev); | |
2846 | if (status != 0) | |
2847 | dev_err(&pdev->dev, | |
2848 | "Error %d setting up MSI; falling back to xPIC\n", | |
2849 | status); | |
2850 | else | |
2851 | mgp->msi_enabled = 1; | |
2852 | } | |
2853 | ||
1fb9df5d | 2854 | status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED, |
0da34b6d BG |
2855 | netdev->name, mgp); |
2856 | if (status != 0) { | |
2857 | dev_err(&pdev->dev, "failed to allocate IRQ\n"); | |
2858 | goto abort_with_firmware; | |
2859 | } | |
2860 | ||
2861 | pci_set_drvdata(pdev, mgp); | |
2862 | if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU) | |
2863 | myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN; | |
2864 | if ((myri10ge_initial_mtu + ETH_HLEN) < 68) | |
2865 | myri10ge_initial_mtu = 68; | |
2866 | netdev->mtu = myri10ge_initial_mtu; | |
2867 | netdev->open = myri10ge_open; | |
2868 | netdev->stop = myri10ge_close; | |
2869 | netdev->hard_start_xmit = myri10ge_xmit; | |
2870 | netdev->get_stats = myri10ge_get_stats; | |
2871 | netdev->base_addr = mgp->iomem_base; | |
2872 | netdev->irq = pdev->irq; | |
2873 | netdev->change_mtu = myri10ge_change_mtu; | |
2874 | netdev->set_multicast_list = myri10ge_set_multicast_list; | |
2875 | netdev->set_mac_address = myri10ge_set_mac_address; | |
2876 | netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO; | |
2877 | if (dac_enabled) | |
2878 | netdev->features |= NETIF_F_HIGHDMA; | |
2879 | netdev->poll = myri10ge_poll; | |
2880 | netdev->weight = myri10ge_napi_weight; | |
2881 | ||
2882 | /* Save configuration space to be restored if the | |
2883 | * nic resets due to a parity error */ | |
2884 | myri10ge_save_state(mgp); | |
0da34b6d BG |
2885 | |
2886 | /* Setup the watchdog timer */ | |
2887 | setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer, | |
2888 | (unsigned long)mgp); | |
2889 | ||
2890 | SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops); | |
2891 | INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog, mgp); | |
2892 | status = register_netdev(netdev); | |
2893 | if (status != 0) { | |
2894 | dev_err(&pdev->dev, "register_netdev failed: %d\n", status); | |
2895 | goto abort_with_irq; | |
2896 | } | |
d6020787 BG |
2897 | dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n", |
2898 | (mgp->msi_enabled ? "MSI" : "xPIC"), | |
2899 | pdev->irq, mgp->tx.boundary, mgp->fw_name, | |
2900 | (mgp->mtrr >= 0 ? "Enabled" : "Disabled")); | |
0da34b6d BG |
2901 | |
2902 | return 0; | |
2903 | ||
2904 | abort_with_irq: | |
2905 | free_irq(pdev->irq, mgp); | |
2906 | if (mgp->msi_enabled) | |
2907 | pci_disable_msi(pdev); | |
2908 | ||
2909 | abort_with_firmware: | |
2910 | myri10ge_dummy_rdma(mgp, 0); | |
2911 | ||
2912 | abort_with_rx_done: | |
2913 | bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry); | |
b10c0668 BG |
2914 | dma_free_coherent(&pdev->dev, bytes, |
2915 | mgp->rx_done.entry, mgp->rx_done.bus); | |
0da34b6d BG |
2916 | |
2917 | abort_with_ioremap: | |
2918 | iounmap(mgp->sram); | |
2919 | ||
2920 | abort_with_wc: | |
2921 | #ifdef CONFIG_MTRR | |
2922 | if (mgp->mtrr >= 0) | |
2923 | mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span); | |
2924 | #endif | |
b10c0668 BG |
2925 | dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats), |
2926 | mgp->fw_stats, mgp->fw_stats_bus); | |
0da34b6d BG |
2927 | |
2928 | abort_with_cmd: | |
b10c0668 BG |
2929 | dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd), |
2930 | mgp->cmd, mgp->cmd_bus); | |
0da34b6d BG |
2931 | |
2932 | abort_with_netdev: | |
2933 | ||
2934 | free_netdev(netdev); | |
2935 | return status; | |
2936 | } | |
2937 | ||
2938 | /* | |
2939 | * myri10ge_remove | |
2940 | * | |
2941 | * Does what is necessary to shutdown one Myrinet device. Called | |
2942 | * once for each Myrinet card by the kernel when a module is | |
2943 | * unloaded. | |
2944 | */ | |
2945 | static void myri10ge_remove(struct pci_dev *pdev) | |
2946 | { | |
2947 | struct myri10ge_priv *mgp; | |
2948 | struct net_device *netdev; | |
2949 | size_t bytes; | |
2950 | ||
2951 | mgp = pci_get_drvdata(pdev); | |
2952 | if (mgp == NULL) | |
2953 | return; | |
2954 | ||
2955 | flush_scheduled_work(); | |
2956 | netdev = mgp->dev; | |
2957 | unregister_netdev(netdev); | |
2958 | free_irq(pdev->irq, mgp); | |
2959 | if (mgp->msi_enabled) | |
2960 | pci_disable_msi(pdev); | |
2961 | ||
2962 | myri10ge_dummy_rdma(mgp, 0); | |
2963 | ||
2964 | bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry); | |
b10c0668 BG |
2965 | dma_free_coherent(&pdev->dev, bytes, |
2966 | mgp->rx_done.entry, mgp->rx_done.bus); | |
0da34b6d BG |
2967 | |
2968 | iounmap(mgp->sram); | |
2969 | ||
2970 | #ifdef CONFIG_MTRR | |
2971 | if (mgp->mtrr >= 0) | |
2972 | mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span); | |
2973 | #endif | |
b10c0668 BG |
2974 | dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats), |
2975 | mgp->fw_stats, mgp->fw_stats_bus); | |
0da34b6d | 2976 | |
b10c0668 BG |
2977 | dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd), |
2978 | mgp->cmd, mgp->cmd_bus); | |
0da34b6d BG |
2979 | |
2980 | free_netdev(netdev); | |
2981 | pci_set_drvdata(pdev, NULL); | |
2982 | } | |
2983 | ||
b10c0668 | 2984 | #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008 |
0da34b6d BG |
2985 | |
2986 | static struct pci_device_id myri10ge_pci_tbl[] = { | |
b10c0668 | 2987 | {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)}, |
0da34b6d BG |
2988 | {0}, |
2989 | }; | |
2990 | ||
2991 | static struct pci_driver myri10ge_driver = { | |
2992 | .name = "myri10ge", | |
2993 | .probe = myri10ge_probe, | |
2994 | .remove = myri10ge_remove, | |
2995 | .id_table = myri10ge_pci_tbl, | |
2996 | #ifdef CONFIG_PM | |
2997 | .suspend = myri10ge_suspend, | |
2998 | .resume = myri10ge_resume, | |
2999 | #endif | |
3000 | }; | |
3001 | ||
3002 | static __init int myri10ge_init_module(void) | |
3003 | { | |
3004 | printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name, | |
3005 | MYRI10GE_VERSION_STR); | |
3006 | return pci_register_driver(&myri10ge_driver); | |
3007 | } | |
3008 | ||
3009 | module_init(myri10ge_init_module); | |
3010 | ||
3011 | static __exit void myri10ge_cleanup_module(void) | |
3012 | { | |
3013 | pci_unregister_driver(&myri10ge_driver); | |
3014 | } | |
3015 | ||
3016 | module_exit(myri10ge_cleanup_module); |