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Merge branch 'dell-wmi' into release
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
e3fd5534 4 * Copyright (C) 2005 - 2009 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
981813d8 52#include <linux/dca.h>
0da34b6d
BG		 53#include <linux/ip.h>
54#include <linux/inet.h>
55#include <linux/in.h>
56#include <linux/ethtool.h>
57#include <linux/firmware.h>
58#include <linux/delay.h>
0da34b6d
BG		 59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
4b860abf 78#define MYRI10GE_VERSION_STR "1.5.1-1.453"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
236bb5e6
BG		 105#define MYRI10GE_MAX_SLICES 32
106
0da34b6d 107struct myri10ge_rx_buffer_state {
dd50f336
BG		 108 struct page *page;
109 int page_offset;
0da34b6d
BG		 110 DECLARE_PCI_UNMAP_ADDR(bus)
111 DECLARE_PCI_UNMAP_LEN(len)
112};
113
114struct myri10ge_tx_buffer_state {
115 struct sk_buff *skb;
116 int last;
117 DECLARE_PCI_UNMAP_ADDR(bus)
118 DECLARE_PCI_UNMAP_LEN(len)
119};
120
121struct myri10ge_cmd {
122 u32 data0;
123 u32 data1;
124 u32 data2;
125};
126
127struct myri10ge_rx_buf {
128 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 129 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
130 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 131 struct page *page;
132 dma_addr_t bus;
133 int page_offset;
0da34b6d 134 int cnt;
dd50f336 135 int fill_cnt;
0da34b6d
BG		 136 int alloc_fail;
137 int mask; /* number of rx slots -1 */
dd50f336 138 int watchdog_needed;
0da34b6d
BG		 139};
140
141struct myri10ge_tx_buf {
142 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 143 __be32 __iomem *send_go; /* "go" doorbell ptr */
144 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 145 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
146 char *req_bytes;
147 struct myri10ge_tx_buffer_state *info;
148 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 149 int req ____cacheline_aligned; /* transmit slots submitted */
150 int pkt_start; /* packets started */
b53bef84
BG		 151 int stop_queue;
152 int linearized;
0da34b6d
BG		 153 int done ____cacheline_aligned; /* transmit slots completed */
154 int pkt_done; /* packets completed */
b53bef84 155 int wake_queue;
236bb5e6 156 int queue_active;
0da34b6d
BG		 157};
158
159struct myri10ge_rx_done {
160 struct mcp_slot *entry;
161 dma_addr_t bus;
162 int cnt;
163 int idx;
1e6e9342
AG		 164 struct net_lro_mgr lro_mgr;
165 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 166};
167
b53bef84
BG		 168struct myri10ge_slice_netstats {
169 unsigned long rx_packets;
170 unsigned long tx_packets;
171 unsigned long rx_bytes;
172 unsigned long tx_bytes;
173 unsigned long rx_dropped;
174 unsigned long tx_dropped;
175};
176
177struct myri10ge_slice_state {
0da34b6d
BG		 178 struct myri10ge_tx_buf tx; /* transmit ring */
179 struct myri10ge_rx_buf rx_small;
180 struct myri10ge_rx_buf rx_big;
181 struct myri10ge_rx_done rx_done;
b53bef84
BG		 182 struct net_device *dev;
183 struct napi_struct napi;
184 struct myri10ge_priv *mgp;
185 struct myri10ge_slice_netstats stats;
186 __be32 __iomem *irq_claim;
187 struct mcp_irq_data *fw_stats;
188 dma_addr_t fw_stats_bus;
189 int watchdog_tx_done;
190 int watchdog_tx_req;
d0234215 191 int watchdog_rx_done;
5dd2d332 192#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 193 int cached_dca_tag;
194 int cpu;
195 __be32 __iomem *dca_tag;
196#endif
0dcffac1 197 char irq_desc[32];
b53bef84
BG		 198};
199
200struct myri10ge_priv {
0dcffac1 201 struct myri10ge_slice_state *ss;
b53bef84 202 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 203 int num_slices;
b53bef84
BG		 204 int running; /* running? */
205 int csum_flag; /* rx_csums? */
0da34b6d 206 int small_bytes;
dd50f336 207 int big_bytes;
fa0a90d9 208 int max_intr_slots;
0da34b6d 209 struct net_device *dev;
b53bef84 210 spinlock_t stats_lock;
0da34b6d
BG		 211 u8 __iomem *sram;
212 int sram_size;
213 unsigned long board_span;
214 unsigned long iomem_base;
40f6cff5 215 __be32 __iomem *irq_deassert;
0da34b6d
BG		 216 char *mac_addr_string;
217 struct mcp_cmd_response *cmd;
218 dma_addr_t cmd_bus;
0da34b6d
BG		 219 struct pci_dev *pdev;
220 int msi_enabled;
0dcffac1
BG		 221 int msix_enabled;
222 struct msix_entry *msix_vectors;
5dd2d332 223#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 224 int dca_enabled;
225#endif
66341fff 226 u32 link_state;
0da34b6d
BG		 227 unsigned int rdma_tags_available;
228 int intr_coal_delay;
40f6cff5 229 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 230 int mtrr;
276e26c3 231 int wc_enabled;
0da34b6d
BG		 232 int down_cnt;
233 wait_queue_head_t down_wq;
234 struct work_struct watchdog_work;
235 struct timer_list watchdog_timer;
0da34b6d 236 int watchdog_resets;
b53bef84 237 int watchdog_pause;
0da34b6d
BG		 238 int pause;
239 char *fw_name;
240 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 241 char *product_code_string;
0da34b6d 242 char fw_version[128];
9dc6f0e7
BG		 243 int fw_ver_major;
244 int fw_ver_minor;
245 int fw_ver_tiny;
246 int adopted_rx_filter_bug;
0da34b6d
BG		 247 u8 mac_addr[6]; /* eeprom mac address */
248 unsigned long serial_number;
249 int vendor_specific_offset;
85a7ea1b 250 int fw_multicast_support;
4f93fde0
BG		 251 unsigned long features;
252 u32 max_tso6;
0da34b6d
BG		 253 u32 read_dma;
254 u32 write_dma;
255 u32 read_write_dma;
c58ac5ca
BG		 256 u32 link_changes;
257 u32 msg_enable;
2d90b0aa 258 unsigned int board_number;
d0234215 259 int rebooted;
0da34b6d
BG		 260};
261
262static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
263static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 264static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
265static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
b9721d5a
BH		 266MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
267MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
268MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
269MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
0da34b6d
BG		 270
271static char *myri10ge_fw_name = NULL;
272module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 273MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 274
2d90b0aa
BG		 275#define MYRI10GE_MAX_BOARDS 8
276static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 277 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 278module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
279 0444);
280MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
281
0da34b6d
BG		 282static int myri10ge_ecrc_enable = 1;
283module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 284MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 285
0da34b6d
BG		 286static int myri10ge_small_bytes = -1; /* -1 == auto */
287module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 288MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 289
290static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 291module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 292MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 293
f761fae1 294static int myri10ge_intr_coal_delay = 75;
0da34b6d 295module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 296MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 297
298static int myri10ge_flow_control = 1;
299module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 300MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 301
302static int myri10ge_deassert_wait = 1;
303module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
304MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 305 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 306
307static int myri10ge_force_firmware = 0;
308module_param(myri10ge_force_firmware, int, S_IRUGO);
309MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 310 "Force firmware to assume aligned completions");
0da34b6d 311
0da34b6d
BG		 312static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
313module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 314MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 315
316static int myri10ge_napi_weight = 64;
317module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 318MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 319
320static int myri10ge_watchdog_timeout = 1;
321module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 322MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 323
324static int myri10ge_max_irq_loops = 1048576;
325module_param(myri10ge_max_irq_loops, int, S_IRUGO);
326MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 327 "Set stuck legacy IRQ detection threshold");
0da34b6d 328
c58ac5ca
BG		 329#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
330
331static int myri10ge_debug = -1; /* defaults above */
332module_param(myri10ge_debug, int, 0);
333MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
334
1e6e9342
AG		 335static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
336module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 337MODULE_PARM_DESC(myri10ge_lro_max_pkts,
338 "Number of LRO packets to be aggregated");
1e6e9342 339
dd50f336
BG		 340static int myri10ge_fill_thresh = 256;
341module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 342MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 343
f181137f
BG		 344static int myri10ge_reset_recover = 1;
345
0dcffac1
BG		 346static int myri10ge_max_slices = 1;
347module_param(myri10ge_max_slices, int, S_IRUGO);
348MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
349
4b860abf 350static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
0dcffac1
BG		 351module_param(myri10ge_rss_hash, int, S_IRUGO);
352MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
353
981813d8
BG		 354static int myri10ge_dca = 1;
355module_param(myri10ge_dca, int, S_IRUGO);
356MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
357
0da34b6d
BG		 358#define MYRI10GE_FW_OFFSET 1024*1024
359#define MYRI10GE_HIGHPART_TO_U32(X) \
360(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
361#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
362
363#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
364
2f76216f 365static void myri10ge_set_multicast_list(struct net_device *dev);
61357325
SH		 366static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
367 struct net_device *dev);
2f76216f 368
6250223e 369static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 370{
6250223e 371 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 372}
373
59081825
BG		 374static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
375
0da34b6d
BG		 376static int
377myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
378 struct myri10ge_cmd *data, int atomic)
379{
380 struct mcp_cmd *buf;
381 char buf_bytes[sizeof(*buf) + 8];
382 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 383 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 384 u32 dma_low, dma_high, result, value;
385 int sleep_total = 0;
386
387 /* ensure buf is aligned to 8 bytes */
388 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
389
390 buf->data0 = htonl(data->data0);
391 buf->data1 = htonl(data->data1);
392 buf->data2 = htonl(data->data2);
393 buf->cmd = htonl(cmd);
394 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
395 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
396
397 buf->response_addr.low = htonl(dma_low);
398 buf->response_addr.high = htonl(dma_high);
40f6cff5 399 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 400 mb();
401 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
402
403 /* wait up to 15ms. Longest command is the DMA benchmark,
404 * which is capped at 5ms, but runs from a timeout handler
405 * that runs every 7.8ms. So a 15ms timeout leaves us with
406 * a 2.2ms margin
407 */
408 if (atomic) {
409 /* if atomic is set, do not sleep,
410 * and try to get the completion quickly
411 * (1ms will be enough for those commands) */
412 for (sleep_total = 0;
8e95a202
JP		 413 sleep_total < 1000 &&
414 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 415 sleep_total += 10) {
0da34b6d 416 udelay(10);
bd2db0cf
BG		 417 mb();
418 }
0da34b6d
BG		 419 } else {
420 /* use msleep for most command */
421 for (sleep_total = 0;
8e95a202
JP		 422 sleep_total < 15 &&
423 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 424 sleep_total++)
425 msleep(1);
426 }
427
428 result = ntohl(response->result);
429 value = ntohl(response->data);
430 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
431 if (result == 0) {
432 data->data0 = value;
433 return 0;
85a7ea1b
BG		 434 } else if (result == MXGEFW_CMD_UNKNOWN) {
435 return -ENOSYS;
5443e9ea
BG		 436 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
437 return -E2BIG;
236bb5e6
BG		 438 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
439 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
440 (data->
441 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
442 0) {
443 return -ERANGE;
0da34b6d
BG		 444 } else {
445 dev_err(&mgp->pdev->dev,
446 "command %d failed, result = %d\n",
447 cmd, result);
448 return -ENXIO;
449 }
450 }
451
452 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
453 cmd, result);
454 return -EAGAIN;
455}
456
457/*
458 * The eeprom strings on the lanaiX have the format
459 * SN=x\0
460 * MAC=x:x:x:x:x:x\0
461 * PT:ddd mmm xx xx:xx:xx xx\0
462 * PV:ddd mmm xx xx:xx:xx xx\0
463 */
464static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
465{
466 char *ptr, *limit;
467 int i;
468
469 ptr = mgp->eeprom_strings;
470 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
471
472 while (*ptr != '\0' && ptr < limit) {
473 if (memcmp(ptr, "MAC=", 4) == 0) {
474 ptr += 4;
475 mgp->mac_addr_string = ptr;
476 for (i = 0; i < 6; i++) {
477 if ((ptr + 2) > limit)
478 goto abort;
479 mgp->mac_addr[i] =
480 simple_strtoul(ptr, &ptr, 16);
481 ptr += 1;
482 }
483 }
c0bf8801
BG		 484 if (memcmp(ptr, "PC=", 3) == 0) {
485 ptr += 3;
486 mgp->product_code_string = ptr;
487 }
0da34b6d
BG		 488 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
489 ptr += 3;
490 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
491 }
492 while (ptr < limit && *ptr++) ;
493 }
494
495 return 0;
496
497abort:
498 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
499 return -ENXIO;
500}
501
502/*
503 * Enable or disable periodic RDMAs from the host to make certain
504 * chipsets resend dropped PCIe messages
505 */
506
507static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
508{
509 char __iomem *submit;
f8fd57c1 510 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 511 u32 dma_low, dma_high;
512 int i;
513
514 /* clear confirmation addr */
515 mgp->cmd->data = 0;
516 mb();
517
518 /* send a rdma command to the PCIe engine, and wait for the
519 * response in the confirmation address. The firmware should
520 * write a -1 there to indicate it is alive and well
521 */
522 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
523 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
524
525 buf[0] = htonl(dma_high); /* confirm addr MSW */
526 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 527 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 528 buf[3] = htonl(dma_high); /* dummy addr MSW */
529 buf[4] = htonl(dma_low); /* dummy addr LSW */
530 buf[5] = htonl(enable); /* enable? */
531
e700f9f4 532 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 533
534 myri10ge_pio_copy(submit, &buf, sizeof(buf));
535 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
536 msleep(1);
537 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
538 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
539 (enable ? "enable" : "disable"));
540}
541
542static int
543myri10ge_validate_firmware(struct myri10ge_priv *mgp,
544 struct mcp_gen_header *hdr)
545{
546 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 547
548 /* check firmware type */
549 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
550 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
551 return -EINVAL;
552 }
553
554 /* save firmware version for ethtool */
555 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
556
9dc6f0e7
BG		 557 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
558 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 559
8e95a202
JP		 560 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
561 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 562 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
563 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
564 MXGEFW_VERSION_MINOR);
565 return -EINVAL;
566 }
567 return 0;
568}
569
570static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
571{
572 unsigned crc, reread_crc;
573 const struct firmware *fw;
574 struct device *dev = &mgp->pdev->dev;
b0d31d6b 575 unsigned char *fw_readback;
0da34b6d
BG		 576 struct mcp_gen_header *hdr;
577 size_t hdr_offset;
578 int status;
e454358a 579 unsigned i;
0da34b6d
BG		 580
581 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
582 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
583 mgp->fw_name);
584 status = -EINVAL;
585 goto abort_with_nothing;
586 }
587
588 /* check size */
589
590 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
591 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
592 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
593 status = -EINVAL;
594 goto abort_with_fw;
595 }
596
597 /* check id */
40f6cff5 598 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 599 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
600 dev_err(dev, "Bad firmware file\n");
601 status = -EINVAL;
602 goto abort_with_fw;
603 }
604 hdr = (void *)(fw->data + hdr_offset);
605
606 status = myri10ge_validate_firmware(mgp, hdr);
607 if (status != 0)
608 goto abort_with_fw;
609
610 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 611 for (i = 0; i < fw->size; i += 256) {
612 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
613 fw->data + i,
614 min(256U, (unsigned)(fw->size - i)));
615 mb();
616 readb(mgp->sram);
b10c0668 617 }
b0d31d6b
DW		 618 fw_readback = vmalloc(fw->size);
619 if (!fw_readback) {
620 status = -ENOMEM;
621 goto abort_with_fw;
622 }
0da34b6d 623 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 624 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
625 reread_crc = crc32(~0, fw_readback, fw->size);
626 vfree(fw_readback);
0da34b6d
BG		 627 if (crc != reread_crc) {
628 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
629 (unsigned)fw->size, reread_crc, crc);
630 status = -EIO;
631 goto abort_with_fw;
632 }
633 *size = (u32) fw->size;
634
635abort_with_fw:
636 release_firmware(fw);
637
638abort_with_nothing:
639 return status;
640}
641
642static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
643{
644 struct mcp_gen_header *hdr;
645 struct device *dev = &mgp->pdev->dev;
646 const size_t bytes = sizeof(struct mcp_gen_header);
647 size_t hdr_offset;
648 int status;
649
650 /* find running firmware header */
66341fff 651 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 652
653 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
654 dev_err(dev, "Running firmware has bad header offset (%d)\n",
655 (int)hdr_offset);
656 return -EIO;
657 }
658
659 /* copy header of running firmware from SRAM to host memory to
660 * validate firmware */
661 hdr = kmalloc(bytes, GFP_KERNEL);
662 if (hdr == NULL) {
663 dev_err(dev, "could not malloc firmware hdr\n");
664 return -ENOMEM;
665 }
666 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
667 status = myri10ge_validate_firmware(mgp, hdr);
668 kfree(hdr);
9dc6f0e7
BG		 669
670 /* check to see if adopted firmware has bug where adopting
671 * it will cause broadcasts to be filtered unless the NIC
672 * is kept in ALLMULTI mode */
673 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
674 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
675 mgp->adopted_rx_filter_bug = 1;
676 dev_warn(dev, "Adopting fw %d.%d.%d: "
677 "working around rx filter bug\n",
678 mgp->fw_ver_major, mgp->fw_ver_minor,
679 mgp->fw_ver_tiny);
680 }
0da34b6d
BG		 681 return status;
682}
683
0178ec3d 684static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 685{
686 struct myri10ge_cmd cmd;
687 int status;
688
689 /* probe for IPv6 TSO support */
690 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
691 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
692 &cmd, 0);
693 if (status == 0) {
694 mgp->max_tso6 = cmd.data0;
695 mgp->features |= NETIF_F_TSO6;
696 }
697
698 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
699 if (status != 0) {
700 dev_err(&mgp->pdev->dev,
701 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
702 return -ENXIO;
703 }
704
705 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
706
707 return 0;
708}
709
0dcffac1 710static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 711{
712 char __iomem *submit;
f8fd57c1 713 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 714 u32 dma_low, dma_high, size;
715 int status, i;
716
b10c0668 717 size = 0;
0da34b6d
BG		 718 status = myri10ge_load_hotplug_firmware(mgp, &size);
719 if (status) {
0dcffac1
BG		 720 if (!adopt)
721 return status;
0da34b6d
BG		 722 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
723
724 /* Do not attempt to adopt firmware if there
725 * was a bad crc */
726 if (status == -EIO)
727 return status;
728
729 status = myri10ge_adopt_running_firmware(mgp);
730 if (status != 0) {
731 dev_err(&mgp->pdev->dev,
732 "failed to adopt running firmware\n");
733 return status;
734 }
735 dev_info(&mgp->pdev->dev,
736 "Successfully adopted running firmware\n");
b53bef84 737 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 738 dev_warn(&mgp->pdev->dev,
739 "Using firmware currently running on NIC"
740 ". For optimal\n");
741 dev_warn(&mgp->pdev->dev,
742 "performance consider loading optimized "
743 "firmware\n");
744 dev_warn(&mgp->pdev->dev, "via hotplug\n");
745 }
746
747 mgp->fw_name = "adopted";
b53bef84 748 mgp->tx_boundary = 2048;
fa0a90d9
BG		 749 myri10ge_dummy_rdma(mgp, 1);
750 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 751 return status;
752 }
753
754 /* clear confirmation addr */
755 mgp->cmd->data = 0;
756 mb();
757
758 /* send a reload command to the bootstrap MCP, and wait for the
759 * response in the confirmation address. The firmware should
760 * write a -1 there to indicate it is alive and well
761 */
762 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
763 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
764
765 buf[0] = htonl(dma_high); /* confirm addr MSW */
766 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 767 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 768
769 /* FIX: All newest firmware should un-protect the bottom of
770 * the sram before handoff. However, the very first interfaces
771 * do not. Therefore the handoff copy must skip the first 8 bytes
772 */
773 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
774 buf[4] = htonl(size - 8); /* length of code */
775 buf[5] = htonl(8); /* where to copy to */
776 buf[6] = htonl(0); /* where to jump to */
777
e700f9f4 778 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 779
780 myri10ge_pio_copy(submit, &buf, sizeof(buf));
781 mb();
782 msleep(1);
783 mb();
784 i = 0;
d93ca2a4
BG		 785 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
786 msleep(1 << i);
0da34b6d
BG		 787 i++;
788 }
789 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
790 dev_err(&mgp->pdev->dev, "handoff failed\n");
791 return -ENXIO;
792 }
9a71db72 793 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 794 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 795
fa0a90d9 796 return status;
0da34b6d
BG		 797}
798
799static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
800{
801 struct myri10ge_cmd cmd;
802 int status;
803
804 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
805 | (addr[2] << 8) | addr[3]);
806
807 cmd.data1 = ((addr[4] << 8) | (addr[5]));
808
809 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
810 return status;
811}
812
813static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
814{
815 struct myri10ge_cmd cmd;
816 int status, ctl;
817
818 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
819 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
820
821 if (status) {
822 printk(KERN_ERR
823 "myri10ge: %s: Failed to set flow control mode\n",
824 mgp->dev->name);
825 return status;
826 }
827 mgp->pause = pause;
828 return 0;
829}
830
831static void
832myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
833{
834 struct myri10ge_cmd cmd;
835 int status, ctl;
836
837 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
838 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
839 if (status)
840 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
841 mgp->dev->name);
842}
843
0d6ac257 844static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 845{
846 struct myri10ge_cmd cmd;
847 int status;
0da34b6d 848 u32 len;
34fdccea
BG		 849 struct page *dmatest_page;
850 dma_addr_t dmatest_bus;
0d6ac257
BG		 851 char *test = " ";
852
853 dmatest_page = alloc_page(GFP_KERNEL);
854 if (!dmatest_page)
855 return -ENOMEM;
856 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
857 DMA_BIDIRECTIONAL);
858
859 /* Run a small DMA test.
860 * The magic multipliers to the length tell the firmware
861 * to do DMA read, write, or read+write tests. The
862 * results are returned in cmd.data0. The upper 16
863 * bits or the return is the number of transfers completed.
864 * The lower 16 bits is the time in 0.5us ticks that the
865 * transfers took to complete.
866 */
867
b53bef84 868 len = mgp->tx_boundary;
0d6ac257
BG		 869
870 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
871 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
872 cmd.data2 = len * 0x10000;
873 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
874 if (status != 0) {
875 test = "read";
876 goto abort;
877 }
878 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
879 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
880 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
881 cmd.data2 = len * 0x1;
882 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
883 if (status != 0) {
884 test = "write";
885 goto abort;
886 }
887 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
888
889 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
890 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
891 cmd.data2 = len * 0x10001;
892 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
893 if (status != 0) {
894 test = "read/write";
895 goto abort;
896 }
897 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
898 (cmd.data0 & 0xffff);
899
900abort:
901 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
902 put_page(dmatest_page);
903
904 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
905 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
906 test, status);
907
908 return status;
909}
910
911static int myri10ge_reset(struct myri10ge_priv *mgp)
912{
913 struct myri10ge_cmd cmd;
0dcffac1
BG		 914 struct myri10ge_slice_state *ss;
915 int i, status;
0d6ac257 916 size_t bytes;
5dd2d332 917#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 918 unsigned long dca_tag_off;
919#endif
0da34b6d
BG		 920
921 /* try to send a reset command to the card to see if it
922 * is alive */
923 memset(&cmd, 0, sizeof(cmd));
924 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
925 if (status != 0) {
926 dev_err(&mgp->pdev->dev, "failed reset\n");
927 return -ENXIO;
928 }
0d6ac257
BG		 929
930 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 931 /*
932 * Use non-ndis mcp_slot (eg, 4 bytes total,
933 * no toeplitz hash value returned. Older firmware will
934 * not understand this command, but will use the correct
935 * sized mcp_slot, so we ignore error returns
936 */
937 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
938 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 939
940 /* Now exchange information about interrupts */
941
0dcffac1 942 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 943 cmd.data0 = (u32) bytes;
944 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 945
946 /*
947 * Even though we already know how many slices are supported
948 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
949 * has magic side effects, and must be called after a reset.
950 * It must be called prior to calling any RSS related cmds,
951 * including assigning an interrupt queue for anything but
952 * slice 0. It must also be called *after*
953 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
954 * the firmware to compute offsets.
955 */
956
957 if (mgp->num_slices > 1) {
958
959 /* ask the maximum number of slices it supports */
960 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
961 &cmd, 0);
962 if (status != 0) {
963 dev_err(&mgp->pdev->dev,
964 "failed to get number of slices\n");
965 }
966
967 /*
968 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
969 * to setting up the interrupt queue DMA
970 */
971
972 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 973 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
974 if (mgp->dev->real_num_tx_queues > 1)
975 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 976 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
977 &cmd, 0);
236bb5e6
BG		 978
979 /* Firmware older than 1.4.32 only supports multiple
980 * RX queues, so if we get an error, first retry using a
981 * single TX queue before giving up */
982 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
983 mgp->dev->real_num_tx_queues = 1;
984 cmd.data0 = mgp->num_slices;
985 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
986 status = myri10ge_send_cmd(mgp,
987 MXGEFW_CMD_ENABLE_RSS_QUEUES,
988 &cmd, 0);
989 }
990
0dcffac1
BG		 991 if (status != 0) {
992 dev_err(&mgp->pdev->dev,
993 "failed to set number of slices\n");
994
995 return status;
996 }
997 }
998 for (i = 0; i < mgp->num_slices; i++) {
999 ss = &mgp->ss[i];
1000 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1001 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1002 cmd.data2 = i;
1003 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1004 &cmd, 0);
1005 };
0da34b6d
BG		 1006
1007 status |=
1008 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1009 for (i = 0; i < mgp->num_slices; i++) {
1010 ss = &mgp->ss[i];
1011 ss->irq_claim =
1012 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1013 }
df30a740
BG		 1014 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1015 &cmd, 0);
1016 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1017
0da34b6d
BG		 1018 status |= myri10ge_send_cmd
1019 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1020 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1021 if (status != 0) {
1022 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1023 return status;
1024 }
40f6cff5 1025 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1026
5dd2d332 1027#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1028 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1029 dca_tag_off = cmd.data0;
1030 for (i = 0; i < mgp->num_slices; i++) {
1031 ss = &mgp->ss[i];
1032 if (status == 0) {
1033 ss->dca_tag = (__iomem __be32 *)
1034 (mgp->sram + dca_tag_off + 4 * i);
1035 } else {
1036 ss->dca_tag = NULL;
1037 }
1038 }
4ee2ac51 1039#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1040
0da34b6d 1041 /* reset mcp/driver shared state back to 0 */
0dcffac1 1042
c58ac5ca 1043 mgp->link_changes = 0;
0dcffac1
BG		 1044 for (i = 0; i < mgp->num_slices; i++) {
1045 ss = &mgp->ss[i];
1046
1047 memset(ss->rx_done.entry, 0, bytes);
1048 ss->tx.req = 0;
1049 ss->tx.done = 0;
1050 ss->tx.pkt_start = 0;
1051 ss->tx.pkt_done = 0;
1052 ss->rx_big.cnt = 0;
1053 ss->rx_small.cnt = 0;
1054 ss->rx_done.idx = 0;
1055 ss->rx_done.cnt = 0;
1056 ss->tx.wake_queue = 0;
1057 ss->tx.stop_queue = 0;
1058 }
1059
0da34b6d 1060 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1061 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1062 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1063 return status;
1064}
1065
5dd2d332 1066#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1067static void
1068myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1069{
1070 ss->cpu = cpu;
1071 ss->cached_dca_tag = tag;
1072 put_be32(htonl(tag), ss->dca_tag);
1073}
1074
1075static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1076{
1077 int cpu = get_cpu();
1078 int tag;
1079
1080 if (cpu != ss->cpu) {
1081 tag = dca_get_tag(cpu);
1082 if (ss->cached_dca_tag != tag)
1083 myri10ge_write_dca(ss, cpu, tag);
1084 }
1085 put_cpu();
1086}
1087
1088static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1089{
1090 int err, i;
1091 struct pci_dev *pdev = mgp->pdev;
1092
1093 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1094 return;
1095 if (!myri10ge_dca) {
1096 dev_err(&pdev->dev, "dca disabled by administrator\n");
1097 return;
1098 }
1099 err = dca_add_requester(&pdev->dev);
1100 if (err) {
330554cb
BG		 1101 if (err != -ENODEV)
1102 dev_err(&pdev->dev,
1103 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1104 return;
1105 }
1106 mgp->dca_enabled = 1;
1107 for (i = 0; i < mgp->num_slices; i++)
1108 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1109}
1110
1111static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1112{
1113 struct pci_dev *pdev = mgp->pdev;
1114 int err;
1115
1116 if (!mgp->dca_enabled)
1117 return;
1118 mgp->dca_enabled = 0;
1119 err = dca_remove_requester(&pdev->dev);
1120}
1121
1122static int myri10ge_notify_dca_device(struct device *dev, void *data)
1123{
1124 struct myri10ge_priv *mgp;
1125 unsigned long event;
1126
1127 mgp = dev_get_drvdata(dev);
1128 event = *(unsigned long *)data;
1129
1130 if (event == DCA_PROVIDER_ADD)
1131 myri10ge_setup_dca(mgp);
1132 else if (event == DCA_PROVIDER_REMOVE)
1133 myri10ge_teardown_dca(mgp);
1134 return 0;
1135}
4ee2ac51 1136#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1137
0da34b6d
BG		 1138static inline void
1139myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1140 struct mcp_kreq_ether_recv *src)
1141{
40f6cff5 1142 __be32 low;
0da34b6d
BG		 1143
1144 low = src->addr_low;
284901a9 1145 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1146 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1147 mb();
1148 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1149 mb();
1150 src->addr_low = low;
40f6cff5 1151 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1152 mb();
1153}
1154
40f6cff5 1155static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1156{
1157 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1158
40f6cff5 1159 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1160 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1161 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1162 skb->csum = hw_csum;
84fa7933 1163 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1164 }
1165}
1166
dd50f336
BG		 1167static inline void
1168myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1169 struct skb_frag_struct *rx_frags, int len, int hlen)
1170{
1171 struct skb_frag_struct *skb_frags;
1172
1173 skb->len = skb->data_len = len;
1174 skb->truesize = len + sizeof(struct sk_buff);
1175 /* attach the page(s) */
1176
1177 skb_frags = skb_shinfo(skb)->frags;
1178 while (len > 0) {
1179 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1180 len -= rx_frags->size;
1181 skb_frags++;
1182 rx_frags++;
1183 skb_shinfo(skb)->nr_frags++;
1184 }
1185
1186 /* pskb_may_pull is not available in irq context, but
1187 * skb_pull() (for ether_pad and eth_type_trans()) requires
1188 * the beginning of the packet in skb_headlen(), move it
1189 * manually */
27d7ff46 1190 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 1191 skb_shinfo(skb)->frags[0].page_offset += hlen;
1192 skb_shinfo(skb)->frags[0].size -= hlen;
1193 skb->data_len -= hlen;
1194 skb->tail += hlen;
1195 skb_pull(skb, MXGEFW_PAD);
1196}
1197
1198static void
1199myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1200 int bytes, int watchdog)
1201{
1202 struct page *page;
1203 int idx;
1204
1205 if (unlikely(rx->watchdog_needed && !watchdog))
1206 return;
1207
1208 /* try to refill entire ring */
1209 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1210 idx = rx->fill_cnt & rx->mask;
ae8509b1 1211 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1212 /* we can use part of previous page */
1213 get_page(rx->page);
1214 } else {
1215 /* we need a new page */
1216 page =
1217 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1218 MYRI10GE_ALLOC_ORDER);
1219 if (unlikely(page == NULL)) {
1220 if (rx->fill_cnt - rx->cnt < 16)
1221 rx->watchdog_needed = 1;
1222 return;
1223 }
1224 rx->page = page;
1225 rx->page_offset = 0;
1226 rx->bus = pci_map_page(mgp->pdev, page, 0,
1227 MYRI10GE_ALLOC_SIZE,
1228 PCI_DMA_FROMDEVICE);
1229 }
1230 rx->info[idx].page = rx->page;
1231 rx->info[idx].page_offset = rx->page_offset;
1232 /* note that this is the address of the start of the
1233 * page */
1234 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1235 rx->shadow[idx].addr_low =
1236 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1237 rx->shadow[idx].addr_high =
1238 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1239
1240 /* start next packet on a cacheline boundary */
1241 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1242
1243#if MYRI10GE_ALLOC_SIZE > 4096
1244 /* don't cross a 4KB boundary */
1245 if ((rx->page_offset >> 12) !=
1246 ((rx->page_offset + bytes - 1) >> 12))
1247 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1248#endif
dd50f336
BG		 1249 rx->fill_cnt++;
1250
1251 /* copy 8 descriptors to the firmware at a time */
1252 if ((idx & 7) == 7) {
e454e7e2
BG		 1253 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1254 &rx->shadow[idx - 7]);
dd50f336
BG		 1255 }
1256 }
1257}
1258
1259static inline void
1260myri10ge_unmap_rx_page(struct pci_dev *pdev,
1261 struct myri10ge_rx_buffer_state *info, int bytes)
1262{
1263 /* unmap the recvd page if we're the only or last user of it */
1264 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1265 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1266 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1267 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1268 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1269 }
1270}
1271
1272#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1273 * page into an skb */
1274
1275static inline int
b53bef84 1276myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
52ea6fb3 1277 int bytes, int len, __wsum csum)
dd50f336 1278{
b53bef84 1279 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1280 struct sk_buff *skb;
1281 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1282 int i, idx, hlen, remainder;
1283 struct pci_dev *pdev = mgp->pdev;
1284 struct net_device *dev = mgp->dev;
1285 u8 *va;
1286
1287 len += MXGEFW_PAD;
1288 idx = rx->cnt & rx->mask;
1289 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1290 prefetch(va);
1291 /* Fill skb_frag_struct(s) with data from our receive */
1292 for (i = 0, remainder = len; remainder > 0; i++) {
1293 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1294 rx_frags[i].page = rx->info[idx].page;
1295 rx_frags[i].page_offset = rx->info[idx].page_offset;
1296 if (remainder < MYRI10GE_ALLOC_SIZE)
1297 rx_frags[i].size = remainder;
1298 else
1299 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1300 rx->cnt++;
1301 idx = rx->cnt & rx->mask;
1302 remainder -= MYRI10GE_ALLOC_SIZE;
1303 }
1304
3a0c7d2d 1305 if (dev->features & NETIF_F_LRO) {
1e6e9342
AG		 1306 rx_frags[0].page_offset += MXGEFW_PAD;
1307 rx_frags[0].size -= MXGEFW_PAD;
1308 len -= MXGEFW_PAD;
b53bef84 1309 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
b53bef84 1310 /* opaque, will come back in get_frag_header */
0dcffac1 1311 len, len,
b53bef84 1312 (void *)(__force unsigned long)csum, csum);
0dcffac1 1313
1e6e9342
AG		 1314 return 1;
1315 }
1316
dd50f336
BG		 1317 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1318
e636b2ea
BG		 1319 /* allocate an skb to attach the page(s) to. This is done
1320 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1321
1322 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1323 if (unlikely(skb == NULL)) {
d6279c88 1324 ss->stats.rx_dropped++;
dd50f336
BG		 1325 do {
1326 i--;
1327 put_page(rx_frags[i].page);
1328 } while (i != 0);
1329 return 0;
1330 }
1331
1332 /* Attach the pages to the skb, and trim off any padding */
1333 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1334 if (skb_shinfo(skb)->frags[0].size <= 0) {
1335 put_page(skb_shinfo(skb)->frags[0].page);
1336 skb_shinfo(skb)->nr_frags = 0;
1337 }
1338 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 1339 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
dd50f336
BG		 1340
1341 if (mgp->csum_flag) {
1342 if ((skb->protocol == htons(ETH_P_IP)) ||
1343 (skb->protocol == htons(ETH_P_IPV6))) {
1344 skb->csum = csum;
1345 skb->ip_summed = CHECKSUM_COMPLETE;
1346 } else
1347 myri10ge_vlan_ip_csum(skb, csum);
1348 }
1349 netif_receive_skb(skb);
dd50f336
BG		 1350 return 1;
1351}
1352
b53bef84
BG		 1353static inline void
1354myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1355{
b53bef84
BG		 1356 struct pci_dev *pdev = ss->mgp->pdev;
1357 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1358 struct netdev_queue *dev_queue;
0da34b6d
BG		 1359 struct sk_buff *skb;
1360 int idx, len;
0da34b6d
BG		 1361
1362 while (tx->pkt_done != mcp_index) {
1363 idx = tx->done & tx->mask;
1364 skb = tx->info[idx].skb;
1365
1366 /* Mark as free */
1367 tx->info[idx].skb = NULL;
1368 if (tx->info[idx].last) {
1369 tx->pkt_done++;
1370 tx->info[idx].last = 0;
1371 }
1372 tx->done++;
1373 len = pci_unmap_len(&tx->info[idx], len);
1374 pci_unmap_len_set(&tx->info[idx], len, 0);
1375 if (skb) {
b53bef84
BG		 1376 ss->stats.tx_bytes += skb->len;
1377 ss->stats.tx_packets++;
0da34b6d
BG		 1378 dev_kfree_skb_irq(skb);
1379 if (len)
1380 pci_unmap_single(pdev,
1381 pci_unmap_addr(&tx->info[idx],
1382 bus), len,
1383 PCI_DMA_TODEVICE);
1384 } else {
1385 if (len)
1386 pci_unmap_page(pdev,
1387 pci_unmap_addr(&tx->info[idx],
1388 bus), len,
1389 PCI_DMA_TODEVICE);
1390 }
0da34b6d 1391 }
236bb5e6
BG		 1392
1393 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1394 /*
1395 * Make a minimal effort to prevent the NIC from polling an
1396 * idle tx queue. If we can't get the lock we leave the queue
1397 * active. In this case, either a thread was about to start
1398 * using the queue anyway, or we lost a race and the NIC will
1399 * waste some of its resources polling an inactive queue for a
1400 * while.
1401 */
1402
1403 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1404 __netif_tx_trylock(dev_queue)) {
1405 if (tx->req == tx->done) {
1406 tx->queue_active = 0;
1407 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1408 mb();
6824a105 1409 mmiowb();
236bb5e6
BG		 1410 }
1411 __netif_tx_unlock(dev_queue);
1412 }
1413
0da34b6d 1414 /* start the queue if we've stopped it */
8e95a202
JP		 1415 if (netif_tx_queue_stopped(dev_queue) &&
1416 tx->req - tx->done < (tx->mask >> 1)) {
b53bef84 1417 tx->wake_queue++;
236bb5e6 1418 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1419 }
1420}
1421
b53bef84
BG		 1422static inline int
1423myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1424{
b53bef84
BG		 1425 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1426 struct myri10ge_priv *mgp = ss->mgp;
18af3e7c 1427 struct net_device *netdev = mgp->dev;
0da34b6d
BG		 1428 unsigned long rx_bytes = 0;
1429 unsigned long rx_packets = 0;
1430 unsigned long rx_ok;
1431
1432 int idx = rx_done->idx;
1433 int cnt = rx_done->cnt;
bea3348e 1434 int work_done = 0;
0da34b6d 1435 u16 length;
40f6cff5 1436 __wsum checksum;
0da34b6d 1437
c956a240 1438 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1439 length = ntohs(rx_done->entry[idx].length);
1440 rx_done->entry[idx].length = 0;
40f6cff5 1441 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1442 if (length <= mgp->small_bytes)
b53bef84 1443 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
52ea6fb3
BG		 1444 mgp->small_bytes,
1445 length, checksum);
0da34b6d 1446 else
b53bef84 1447 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
52ea6fb3
BG		 1448 mgp->big_bytes,
1449 length, checksum);
0da34b6d
BG		 1450 rx_packets += rx_ok;
1451 rx_bytes += rx_ok * (unsigned long)length;
1452 cnt++;
014377a1 1453 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1454 work_done++;
0da34b6d
BG		 1455 }
1456 rx_done->idx = idx;
1457 rx_done->cnt = cnt;
b53bef84
BG		 1458 ss->stats.rx_packets += rx_packets;
1459 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1460
18af3e7c 1461 if (netdev->features & NETIF_F_LRO)
1e6e9342
AG		 1462 lro_flush_all(&rx_done->lro_mgr);
1463
c7dab99b 1464 /* restock receive rings if needed */
b53bef84
BG		 1465 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1466 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1467 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1468 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1469 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1470
bea3348e 1471 return work_done;
0da34b6d
BG		 1472}
1473
1474static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1475{
0dcffac1 1476 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1477
1478 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1479 unsigned link_up = ntohl(stats->link_up);
1480 if (mgp->link_state != link_up) {
1481 mgp->link_state = link_up;
1482
1483 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1484 if (netif_msg_link(mgp))
1485 printk(KERN_INFO
1486 "myri10ge: %s: link up\n",
1487 mgp->dev->name);
0da34b6d 1488 netif_carrier_on(mgp->dev);
c58ac5ca 1489 mgp->link_changes++;
0da34b6d 1490 } else {
c58ac5ca
BG		 1491 if (netif_msg_link(mgp))
1492 printk(KERN_INFO
798a95db
BG		 1493 "myri10ge: %s: link %s\n",
1494 mgp->dev->name,
1495 (link_up == MXGEFW_LINK_MYRINET ?
1496 "mismatch (Myrinet detected)" :
1497 "down"));
0da34b6d 1498 netif_carrier_off(mgp->dev);
c58ac5ca 1499 mgp->link_changes++;
0da34b6d
BG		 1500 }
1501 }
1502 if (mgp->rdma_tags_available !=
b53bef84 1503 ntohl(stats->rdma_tags_available)) {
0da34b6d 1504 mgp->rdma_tags_available =
b53bef84 1505 ntohl(stats->rdma_tags_available);
0da34b6d
BG		 1506 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1507 "%d tags left\n", mgp->dev->name,
1508 mgp->rdma_tags_available);
1509 }
1510 mgp->down_cnt += stats->link_down;
1511 if (stats->link_down)
1512 wake_up(&mgp->down_wq);
1513 }
1514}
1515
bea3348e 1516static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1517{
b53bef84
BG		 1518 struct myri10ge_slice_state *ss =
1519 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1520 int work_done;
0da34b6d 1521
5dd2d332 1522#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1523 if (ss->mgp->dca_enabled)
1524 myri10ge_update_dca(ss);
1525#endif
1526
0da34b6d 1527 /* process as many rx events as NAPI will allow */
b53bef84 1528 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1529
4ec24119 1530 if (work_done < budget) {
288379f0 1531 napi_complete(napi);
b53bef84 1532 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1533 }
bea3348e 1534 return work_done;
0da34b6d
BG		 1535}
1536
7d12e780 1537static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1538{
b53bef84
BG		 1539 struct myri10ge_slice_state *ss = arg;
1540 struct myri10ge_priv *mgp = ss->mgp;
1541 struct mcp_irq_data *stats = ss->fw_stats;
1542 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1543 u32 send_done_count;
1544 int i;
1545
236bb5e6
BG		 1546 /* an interrupt on a non-zero receive-only slice is implicitly
1547 * valid since MSI-X irqs are not shared */
1548 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1549 napi_schedule(&ss->napi);
0dcffac1
BG		 1550 return (IRQ_HANDLED);
1551 }
1552
0da34b6d
BG		 1553 /* make sure it is our IRQ, and that the DMA has finished */
1554 if (unlikely(!stats->valid))
1555 return (IRQ_NONE);
1556
1557 /* low bit indicates receives are present, so schedule
1558 * napi poll handler */
1559 if (stats->valid & 1)
288379f0 1560 napi_schedule(&ss->napi);
0da34b6d 1561
0dcffac1 1562 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1563 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1564 if (!myri10ge_deassert_wait)
1565 stats->valid = 0;
1566 mb();
1567 } else
1568 stats->valid = 0;
1569
1570 /* Wait for IRQ line to go low, if using INTx */
1571 i = 0;
1572 while (1) {
1573 i++;
1574 /* check for transmit completes and receives */
1575 send_done_count = ntohl(stats->send_done_count);
1576 if (send_done_count != tx->pkt_done)
b53bef84 1577 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d
BG		 1578 if (unlikely(i > myri10ge_max_irq_loops)) {
1579 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1580 mgp->dev->name);
1581 stats->valid = 0;
1582 schedule_work(&mgp->watchdog_work);
1583 }
1584 if (likely(stats->valid == 0))
1585 break;
1586 cpu_relax();
1587 barrier();
1588 }
1589
236bb5e6
BG		 1590 /* Only slice 0 updates stats */
1591 if (ss == mgp->ss)
1592 myri10ge_check_statblock(mgp);
0da34b6d 1593
b53bef84 1594 put_be32(htonl(3), ss->irq_claim + 1);
0da34b6d
BG		 1595 return (IRQ_HANDLED);
1596}
1597
1598static int
1599myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1600{
c0bf8801
BG		 1601 struct myri10ge_priv *mgp = netdev_priv(netdev);
1602 char *ptr;
1603 int i;
1604
0da34b6d
BG		 1605 cmd->autoneg = AUTONEG_DISABLE;
1606 cmd->speed = SPEED_10000;
1607 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1608
1609 /*
1610 * parse the product code to deterimine the interface type
1611 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1612 * after the 3rd dash in the driver's cached copy of the
1613 * EEPROM's product code string.
1614 */
1615 ptr = mgp->product_code_string;
1616 if (ptr == NULL) {
1617 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
99f5f87e 1618 netdev->name);
c0bf8801
BG		 1619 return 0;
1620 }
1621 for (i = 0; i < 3; i++, ptr++) {
1622 ptr = strchr(ptr, '-');
1623 if (ptr == NULL) {
1624 printk(KERN_ERR "myri10ge: %s: Invalid product "
1625 "code %s\n", netdev->name,
1626 mgp->product_code_string);
1627 return 0;
1628 }
1629 }
196f17eb
BG		 1630 if (*ptr == '2')
1631 ptr++;
1632 if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1633 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
c0bf8801 1634 cmd->port = PORT_FIBRE;
196f17eb
BG		 1635 cmd->supported |= SUPPORTED_FIBRE;
1636 cmd->advertising |= ADVERTISED_FIBRE;
1637 } else {
1638 cmd->port = PORT_OTHER;
c0bf8801 1639 }
196f17eb
BG		 1640 if (*ptr == 'R' || *ptr == 'S')
1641 cmd->transceiver = XCVR_EXTERNAL;
1642 else
1643 cmd->transceiver = XCVR_INTERNAL;
1644
0da34b6d
BG		 1645 return 0;
1646}
1647
1648static void
1649myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1650{
1651 struct myri10ge_priv *mgp = netdev_priv(netdev);
1652
1653 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1654 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1655 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1656 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1657}
1658
1659static int
1660myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1661{
1662 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1663
0da34b6d
BG		 1664 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1665 return 0;
1666}
1667
1668static int
1669myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1670{
1671 struct myri10ge_priv *mgp = netdev_priv(netdev);
1672
1673 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1674 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1675 return 0;
1676}
1677
1678static void
1679myri10ge_get_pauseparam(struct net_device *netdev,
1680 struct ethtool_pauseparam *pause)
1681{
1682 struct myri10ge_priv *mgp = netdev_priv(netdev);
1683
1684 pause->autoneg = 0;
1685 pause->rx_pause = mgp->pause;
1686 pause->tx_pause = mgp->pause;
1687}
1688
1689static int
1690myri10ge_set_pauseparam(struct net_device *netdev,
1691 struct ethtool_pauseparam *pause)
1692{
1693 struct myri10ge_priv *mgp = netdev_priv(netdev);
1694
1695 if (pause->tx_pause != mgp->pause)
1696 return myri10ge_change_pause(mgp, pause->tx_pause);
1697 if (pause->rx_pause != mgp->pause)
1698 return myri10ge_change_pause(mgp, pause->tx_pause);
1699 if (pause->autoneg != 0)
1700 return -EINVAL;
1701 return 0;
1702}
1703
1704static void
1705myri10ge_get_ringparam(struct net_device *netdev,
1706 struct ethtool_ringparam *ring)
1707{
1708 struct myri10ge_priv *mgp = netdev_priv(netdev);
1709
0dcffac1
BG		 1710 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1711 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1712 ring->rx_jumbo_max_pending = 0;
6498be3f 1713 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1714 ring->rx_mini_pending = ring->rx_mini_max_pending;
1715 ring->rx_pending = ring->rx_max_pending;
1716 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1717 ring->tx_pending = ring->tx_max_pending;
1718}
1719
1720static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1721{
1722 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1723
0da34b6d
BG		 1724 if (mgp->csum_flag)
1725 return 1;
1726 else
1727 return 0;
1728}
1729
1730static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1731{
1732 struct myri10ge_priv *mgp = netdev_priv(netdev);
3a0c7d2d 1733 int err = 0;
99f5f87e 1734
0da34b6d
BG		 1735 if (csum_enabled)
1736 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3a0c7d2d
BG		 1737 else {
1738 u32 flags = ethtool_op_get_flags(netdev);
1739 err = ethtool_op_set_flags(netdev, (flags & ~ETH_FLAG_LRO));
0da34b6d 1740 mgp->csum_flag = 0;
3a0c7d2d
BG		 1741
1742 }
1743 return err;
0da34b6d
BG		 1744}
1745
4f93fde0
BG		 1746static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1747{
1748 struct myri10ge_priv *mgp = netdev_priv(netdev);
1749 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1750
1751 if (tso_enabled)
1752 netdev->features |= flags;
1753 else
1754 netdev->features &= ~flags;
1755 return 0;
1756}
1757
b53bef84 1758static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1759 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1760 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1761 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1762 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1763 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1764 "tx_heartbeat_errors", "tx_window_errors",
1765 /* device-specific stats */
0dcffac1 1766 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1767 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1768 "serial_number", "watchdog_resets",
5dd2d332 1769#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1770 "dca_capable_firmware", "dca_device_present",
981813d8 1771#endif
c58ac5ca 1772 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1773 "dropped_link_error_or_filtered",
1774 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1775 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1776 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1777 "dropped_no_big_buffer"
1778};
1779
1780static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1781 "----------- slice ---------",
1782 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1783 "rx_small_cnt", "rx_big_cnt",
1784 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1785 "LRO flushed",
1e6e9342 1786 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1787};
1788
1789#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1790#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1791#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1792
1793static void
1794myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1795{
0dcffac1
BG		 1796 struct myri10ge_priv *mgp = netdev_priv(netdev);
1797 int i;
1798
0da34b6d
BG		 1799 switch (stringset) {
1800 case ETH_SS_STATS:
b53bef84
BG		 1801 memcpy(data, *myri10ge_gstrings_main_stats,
1802 sizeof(myri10ge_gstrings_main_stats));
1803 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1804 for (i = 0; i < mgp->num_slices; i++) {
1805 memcpy(data, *myri10ge_gstrings_slice_stats,
1806 sizeof(myri10ge_gstrings_slice_stats));
1807 data += sizeof(myri10ge_gstrings_slice_stats);
1808 }
0da34b6d
BG		 1809 break;
1810 }
1811}
1812
b9f2c044 1813static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1814{
0dcffac1
BG		 1815 struct myri10ge_priv *mgp = netdev_priv(netdev);
1816
b9f2c044
JG		 1817 switch (sset) {
1818 case ETH_SS_STATS:
0dcffac1
BG		 1819 return MYRI10GE_MAIN_STATS_LEN +
1820 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1821 default:
1822 return -EOPNOTSUPP;
1823 }
0da34b6d
BG		 1824}
1825
1826static void
1827myri10ge_get_ethtool_stats(struct net_device *netdev,
1828 struct ethtool_stats *stats, u64 * data)
1829{
1830 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1831 struct myri10ge_slice_state *ss;
0dcffac1 1832 int slice;
0da34b6d
BG		 1833 int i;
1834
59081825
BG		 1835 /* force stats update */
1836 (void)myri10ge_get_stats(netdev);
0da34b6d 1837 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
6dc34941 1838 data[i] = ((unsigned long *)&netdev->stats)[i];
0da34b6d 1839
b53bef84 1840 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1841 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1842 data[i++] = (unsigned int)mgp->pdev->irq;
1843 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1844 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1845 data[i++] = (unsigned int)mgp->read_dma;
1846 data[i++] = (unsigned int)mgp->write_dma;
1847 data[i++] = (unsigned int)mgp->read_write_dma;
1848 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1849 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1850#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1851 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1852 data[i++] = (unsigned int)(mgp->dca_enabled);
1853#endif
c58ac5ca 1854 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1855
1856 /* firmware stats are useful only in the first slice */
0dcffac1 1857 ss = &mgp->ss[0];
b53bef84
BG		 1858 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1859 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1860 data[i++] =
b53bef84
BG		 1861 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1862 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1863 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1864 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1865 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1866 data[i++] =
b53bef84
BG		 1867 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1868 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1869 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1870 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1871 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1872
0dcffac1
BG		 1873 for (slice = 0; slice < mgp->num_slices; slice++) {
1874 ss = &mgp->ss[slice];
1875 data[i++] = slice;
1876 data[i++] = (unsigned int)ss->tx.pkt_start;
1877 data[i++] = (unsigned int)ss->tx.pkt_done;
1878 data[i++] = (unsigned int)ss->tx.req;
1879 data[i++] = (unsigned int)ss->tx.done;
1880 data[i++] = (unsigned int)ss->rx_small.cnt;
1881 data[i++] = (unsigned int)ss->rx_big.cnt;
1882 data[i++] = (unsigned int)ss->tx.wake_queue;
1883 data[i++] = (unsigned int)ss->tx.stop_queue;
1884 data[i++] = (unsigned int)ss->tx.linearized;
1885 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1886 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1887 if (ss->rx_done.lro_mgr.stats.flushed)
1888 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1889 ss->rx_done.lro_mgr.stats.flushed;
1890 else
1891 data[i++] = 0;
1892 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1893 }
0da34b6d
BG		 1894}
1895
c58ac5ca
BG		 1896static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1897{
1898 struct myri10ge_priv *mgp = netdev_priv(netdev);
1899 mgp->msg_enable = value;
1900}
1901
1902static u32 myri10ge_get_msglevel(struct net_device *netdev)
1903{
1904 struct myri10ge_priv *mgp = netdev_priv(netdev);
1905 return mgp->msg_enable;
1906}
1907
7282d491 1908static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1909 .get_settings = myri10ge_get_settings,
1910 .get_drvinfo = myri10ge_get_drvinfo,
1911 .get_coalesce = myri10ge_get_coalesce,
1912 .set_coalesce = myri10ge_set_coalesce,
1913 .get_pauseparam = myri10ge_get_pauseparam,
1914 .set_pauseparam = myri10ge_set_pauseparam,
1915 .get_ringparam = myri10ge_get_ringparam,
1916 .get_rx_csum = myri10ge_get_rx_csum,
1917 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1918 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1919 .set_sg = ethtool_op_set_sg,
4f93fde0 1920 .set_tso = myri10ge_set_tso,
6ffdd071 1921 .get_link = ethtool_op_get_link,
0da34b6d 1922 .get_strings = myri10ge_get_strings,
b9f2c044 1923 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1924 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1925 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d
BG		 1926 .get_msglevel = myri10ge_get_msglevel,
1927 .get_flags = ethtool_op_get_flags,
1928 .set_flags = ethtool_op_set_flags
0da34b6d
BG		 1929};
1930
b53bef84 1931static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1932{
b53bef84 1933 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1934 struct myri10ge_cmd cmd;
b53bef84 1935 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1936 int tx_ring_size, rx_ring_size;
1937 int tx_ring_entries, rx_ring_entries;
0dcffac1 1938 int i, slice, status;
0da34b6d
BG		 1939 size_t bytes;
1940
0da34b6d 1941 /* get ring sizes */
0dcffac1
BG		 1942 slice = ss - mgp->ss;
1943 cmd.data0 = slice;
0da34b6d
BG		 1944 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1945 tx_ring_size = cmd.data0;
0dcffac1 1946 cmd.data0 = slice;
0da34b6d 1947 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1948 if (status != 0)
1949 return status;
0da34b6d
BG		 1950 rx_ring_size = cmd.data0;
1951
1952 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1953 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1954 ss->tx.mask = tx_ring_entries - 1;
1955 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1956
355c7265
BG		 1957 status = -ENOMEM;
1958
0da34b6d
BG		 1959 /* allocate the host shadow rings */
1960
1961 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1962 * sizeof(*ss->tx.req_list);
1963 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1964 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1965 goto abort_with_nothing;
1966
1967 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1968 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1969 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 1970 ss->tx.queue_active = 0;
0da34b6d 1971
b53bef84
BG		 1972 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1973 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1974 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1975 goto abort_with_tx_req_bytes;
1976
b53bef84
BG		 1977 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1978 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1979 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1980 goto abort_with_rx_small_shadow;
1981
1982 /* allocate the host info rings */
1983
b53bef84
BG		 1984 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1985 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1986 if (ss->tx.info == NULL)
0da34b6d
BG		 1987 goto abort_with_rx_big_shadow;
1988
b53bef84
BG		 1989 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1990 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1991 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1992 goto abort_with_tx_info;
1993
b53bef84
BG		 1994 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1995 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1996 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1997 goto abort_with_rx_small_info;
1998
1999 /* Fill the receive rings */
b53bef84
BG		 2000 ss->rx_big.cnt = 0;
2001 ss->rx_small.cnt = 0;
2002 ss->rx_big.fill_cnt = 0;
2003 ss->rx_small.fill_cnt = 0;
2004 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
2005 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2006 ss->rx_small.watchdog_needed = 0;
2007 ss->rx_big.watchdog_needed = 0;
2008 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 2009 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 2010
b53bef84 2011 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
0dcffac1
BG		 2012 printk(KERN_ERR
2013 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
2014 dev->name, slice, ss->rx_small.fill_cnt);
c7dab99b 2015 goto abort_with_rx_small_ring;
0da34b6d
BG		 2016 }
2017
b53bef84
BG		 2018 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2019 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
0dcffac1
BG		 2020 printk(KERN_ERR
2021 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
2022 dev->name, slice, ss->rx_big.fill_cnt);
c7dab99b 2023 goto abort_with_rx_big_ring;
0da34b6d
BG		 2024 }
2025
2026 return 0;
2027
2028abort_with_rx_big_ring:
b53bef84
BG		 2029 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2030 int idx = i & ss->rx_big.mask;
2031 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2032 mgp->big_bytes);
b53bef84 2033 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2034 }
2035
2036abort_with_rx_small_ring:
b53bef84
BG		 2037 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2038 int idx = i & ss->rx_small.mask;
2039 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2040 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2041 put_page(ss->rx_small.info[idx].page);
0da34b6d 2042 }
c7dab99b 2043
b53bef84 2044 kfree(ss->rx_big.info);
0da34b6d
BG		 2045
2046abort_with_rx_small_info:
b53bef84 2047 kfree(ss->rx_small.info);
0da34b6d
BG		 2048
2049abort_with_tx_info:
b53bef84 2050 kfree(ss->tx.info);
0da34b6d
BG		 2051
2052abort_with_rx_big_shadow:
b53bef84 2053 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2054
2055abort_with_rx_small_shadow:
b53bef84 2056 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2057
2058abort_with_tx_req_bytes:
b53bef84
BG		 2059 kfree(ss->tx.req_bytes);
2060 ss->tx.req_bytes = NULL;
2061 ss->tx.req_list = NULL;
0da34b6d
BG		 2062
2063abort_with_nothing:
2064 return status;
2065}
2066
b53bef84 2067static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2068{
b53bef84 2069 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2070 struct sk_buff *skb;
2071 struct myri10ge_tx_buf *tx;
2072 int i, len, idx;
2073
0dcffac1
BG		 2074 /* If not allocated, skip it */
2075 if (ss->tx.req_list == NULL)
2076 return;
2077
b53bef84
BG		 2078 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2079 idx = i & ss->rx_big.mask;
2080 if (i == ss->rx_big.fill_cnt - 1)
2081 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2082 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2083 mgp->big_bytes);
b53bef84 2084 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2085 }
2086
b53bef84
BG		 2087 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2088 idx = i & ss->rx_small.mask;
2089 if (i == ss->rx_small.fill_cnt - 1)
2090 ss->rx_small.info[idx].page_offset =
c7dab99b 2091 MYRI10GE_ALLOC_SIZE;
b53bef84 2092 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2093 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2094 put_page(ss->rx_small.info[idx].page);
c7dab99b 2095 }
b53bef84 2096 tx = &ss->tx;
0da34b6d
BG		 2097 while (tx->done != tx->req) {
2098 idx = tx->done & tx->mask;
2099 skb = tx->info[idx].skb;
2100
2101 /* Mark as free */
2102 tx->info[idx].skb = NULL;
2103 tx->done++;
2104 len = pci_unmap_len(&tx->info[idx], len);
2105 pci_unmap_len_set(&tx->info[idx], len, 0);
2106 if (skb) {
b53bef84 2107 ss->stats.tx_dropped++;
0da34b6d
BG		 2108 dev_kfree_skb_any(skb);
2109 if (len)
2110 pci_unmap_single(mgp->pdev,
2111 pci_unmap_addr(&tx->info[idx],
2112 bus), len,
2113 PCI_DMA_TODEVICE);
2114 } else {
2115 if (len)
2116 pci_unmap_page(mgp->pdev,
2117 pci_unmap_addr(&tx->info[idx],
2118 bus), len,
2119 PCI_DMA_TODEVICE);
2120 }
2121 }
b53bef84 2122 kfree(ss->rx_big.info);
0da34b6d 2123
b53bef84 2124 kfree(ss->rx_small.info);
0da34b6d 2125
b53bef84 2126 kfree(ss->tx.info);
0da34b6d 2127
b53bef84 2128 kfree(ss->rx_big.shadow);
0da34b6d 2129
b53bef84 2130 kfree(ss->rx_small.shadow);
0da34b6d 2131
b53bef84
BG		 2132 kfree(ss->tx.req_bytes);
2133 ss->tx.req_bytes = NULL;
2134 ss->tx.req_list = NULL;
0da34b6d
BG		 2135}
2136
df30a740
BG		 2137static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2138{
2139 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2140 struct myri10ge_slice_state *ss;
2141 struct net_device *netdev = mgp->dev;
2142 int i;
df30a740
BG		 2143 int status;
2144
0dcffac1
BG		 2145 mgp->msi_enabled = 0;
2146 mgp->msix_enabled = 0;
2147 status = 0;
df30a740 2148 if (myri10ge_msi) {
0dcffac1
BG		 2149 if (mgp->num_slices > 1) {
2150 status =
2151 pci_enable_msix(pdev, mgp->msix_vectors,
2152 mgp->num_slices);
2153 if (status == 0) {
2154 mgp->msix_enabled = 1;
2155 } else {
2156 dev_err(&pdev->dev,
2157 "Error %d setting up MSI-X\n", status);
2158 return status;
2159 }
2160 }
2161 if (mgp->msix_enabled == 0) {
2162 status = pci_enable_msi(pdev);
2163 if (status != 0) {
2164 dev_err(&pdev->dev,
2165 "Error %d setting up MSI; falling back to xPIC\n",
2166 status);
2167 } else {
2168 mgp->msi_enabled = 1;
2169 }
2170 }
df30a740 2171 }
0dcffac1
BG		 2172 if (mgp->msix_enabled) {
2173 for (i = 0; i < mgp->num_slices; i++) {
2174 ss = &mgp->ss[i];
2175 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2176 "%s:slice-%d", netdev->name, i);
2177 status = request_irq(mgp->msix_vectors[i].vector,
2178 myri10ge_intr, 0, ss->irq_desc,
2179 ss);
2180 if (status != 0) {
2181 dev_err(&pdev->dev,
2182 "slice %d failed to allocate IRQ\n", i);
2183 i--;
2184 while (i >= 0) {
2185 free_irq(mgp->msix_vectors[i].vector,
2186 &mgp->ss[i]);
2187 i--;
2188 }
2189 pci_disable_msix(pdev);
2190 return status;
2191 }
2192 }
2193 } else {
2194 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2195 mgp->dev->name, &mgp->ss[0]);
2196 if (status != 0) {
2197 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2198 if (mgp->msi_enabled)
2199 pci_disable_msi(pdev);
2200 }
df30a740
BG		 2201 }
2202 return status;
2203}
2204
2205static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2206{
2207 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2208 int i;
df30a740 2209
0dcffac1
BG		 2210 if (mgp->msix_enabled) {
2211 for (i = 0; i < mgp->num_slices; i++)
2212 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2213 } else {
2214 free_irq(pdev->irq, &mgp->ss[0]);
2215 }
df30a740
BG		 2216 if (mgp->msi_enabled)
2217 pci_disable_msi(pdev);
0dcffac1
BG		 2218 if (mgp->msix_enabled)
2219 pci_disable_msix(pdev);
df30a740
BG		 2220}
2221
1e6e9342
AG		 2222static int
2223myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2224 void **ip_hdr, void **tcpudp_hdr,
2225 u64 * hdr_flags, void *priv)
2226{
2227 struct ethhdr *eh;
2228 struct vlan_ethhdr *veh;
2229 struct iphdr *iph;
2230 u8 *va = page_address(frag->page) + frag->page_offset;
2231 unsigned long ll_hlen;
66341fff
AV		 2232 /* passed opaque through lro_receive_frags() */
2233 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 2234
2235 /* find the mac header, aborting if not IPv4 */
2236
2237 eh = (struct ethhdr *)va;
2238 *mac_hdr = eh;
2239 ll_hlen = ETH_HLEN;
2240 if (eh->h_proto != htons(ETH_P_IP)) {
2241 if (eh->h_proto == htons(ETH_P_8021Q)) {
2242 veh = (struct vlan_ethhdr *)va;
2243 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2244 return -1;
2245
2246 ll_hlen += VLAN_HLEN;
2247
2248 /*
2249 * HW checksum starts ETH_HLEN bytes into
2250 * frame, so we must subtract off the VLAN
2251 * header's checksum before csum can be used
2252 */
2253 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2254 VLAN_HLEN, 0));
2255 } else {
2256 return -1;
2257 }
2258 }
2259 *hdr_flags = LRO_IPV4;
2260
2261 iph = (struct iphdr *)(va + ll_hlen);
2262 *ip_hdr = iph;
2263 if (iph->protocol != IPPROTO_TCP)
2264 return -1;
bcb09dc2
BG		 2265 if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2266 return -1;
1e6e9342
AG		 2267 *hdr_flags |= LRO_TCP;
2268 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2269
2270 /* verify the IP checksum */
2271 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2272 return -1;
2273
2274 /* verify the checksum */
2275 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2276 ntohs(iph->tot_len) - (iph->ihl << 2),
2277 IPPROTO_TCP, csum)))
2278 return -1;
2279
2280 return 0;
2281}
2282
77929732
BG		 2283static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2284{
2285 struct myri10ge_cmd cmd;
2286 struct myri10ge_slice_state *ss;
2287 int status;
2288
2289 ss = &mgp->ss[slice];
236bb5e6
BG		 2290 status = 0;
2291 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2292 cmd.data0 = slice;
2293 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2294 &cmd, 0);
2295 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2296 (mgp->sram + cmd.data0);
2297 }
77929732
BG		 2298 cmd.data0 = slice;
2299 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2300 &cmd, 0);
2301 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2302 (mgp->sram + cmd.data0);
2303
2304 cmd.data0 = slice;
2305 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2306 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2307 (mgp->sram + cmd.data0);
2308
236bb5e6
BG		 2309 ss->tx.send_go = (__iomem __be32 *)
2310 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2311 ss->tx.send_stop = (__iomem __be32 *)
2312 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2313 return status;
2314
2315}
2316
2317static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2318{
2319 struct myri10ge_cmd cmd;
2320 struct myri10ge_slice_state *ss;
2321 int status;
2322
2323 ss = &mgp->ss[slice];
2324 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2325 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2326 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2327 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2328 if (status == -ENOSYS) {
2329 dma_addr_t bus = ss->fw_stats_bus;
2330 if (slice != 0)
2331 return -EINVAL;
2332 bus += offsetof(struct mcp_irq_data, send_done_count);
2333 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2334 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2335 status = myri10ge_send_cmd(mgp,
2336 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2337 &cmd, 0);
2338 /* Firmware cannot support multicast without STATS_DMA_V2 */
2339 mgp->fw_multicast_support = 0;
2340 } else {
2341 mgp->fw_multicast_support = 1;
2342 }
2343 return 0;
2344}
77929732 2345
0da34b6d
BG		 2346static int myri10ge_open(struct net_device *dev)
2347{
0dcffac1 2348 struct myri10ge_slice_state *ss;
b53bef84 2349 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2350 struct myri10ge_cmd cmd;
0dcffac1
BG		 2351 int i, status, big_pow2, slice;
2352 u8 *itable;
1e6e9342 2353 struct net_lro_mgr *lro_mgr;
0da34b6d 2354
0da34b6d
BG		 2355 if (mgp->running != MYRI10GE_ETH_STOPPED)
2356 return -EBUSY;
2357
2358 mgp->running = MYRI10GE_ETH_STARTING;
2359 status = myri10ge_reset(mgp);
2360 if (status != 0) {
2361 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 2362 goto abort_with_nothing;
0da34b6d
BG		 2363 }
2364
0dcffac1
BG		 2365 if (mgp->num_slices > 1) {
2366 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2367 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2368 if (mgp->dev->real_num_tx_queues > 1)
2369 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2370 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2371 &cmd, 0);
2372 if (status != 0) {
2373 printk(KERN_ERR
2374 "myri10ge: %s: failed to set number of slices\n",
2375 dev->name);
2376 goto abort_with_nothing;
2377 }
2378 /* setup the indirection table */
2379 cmd.data0 = mgp->num_slices;
2380 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2381 &cmd, 0);
2382
2383 status |= myri10ge_send_cmd(mgp,
2384 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2385 &cmd, 0);
2386 if (status != 0) {
2387 printk(KERN_ERR
2388 "myri10ge: %s: failed to setup rss tables\n",
2389 dev->name);
236bb5e6 2390 goto abort_with_nothing;
0dcffac1
BG		 2391 }
2392
2393 /* just enable an identity mapping */
2394 itable = mgp->sram + cmd.data0;
2395 for (i = 0; i < mgp->num_slices; i++)
2396 __raw_writeb(i, &itable[i]);
2397
2398 cmd.data0 = 1;
2399 cmd.data1 = myri10ge_rss_hash;
2400 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2401 &cmd, 0);
2402 if (status != 0) {
2403 printk(KERN_ERR
2404 "myri10ge: %s: failed to enable slices\n",
2405 dev->name);
2406 goto abort_with_nothing;
2407 }
2408 }
2409
df30a740
BG		 2410 status = myri10ge_request_irq(mgp);
2411 if (status != 0)
2412 goto abort_with_nothing;
2413
0da34b6d
BG		 2414 /* decide what small buffer size to use. For good TCP rx
2415 * performance, it is important to not receive 1514 byte
2416 * frames into jumbo buffers, as it confuses the socket buffer
2417 * accounting code, leading to drops and erratic performance.
2418 */
2419
2420 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2421 /* enough for a TCP header */
2422 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2423 ? (128 - MXGEFW_PAD)
2424 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2425 else
de3c4507
BG		 2426 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2427 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2428
2429 /* Override the small buffer size? */
2430 if (myri10ge_small_bytes > 0)
2431 mgp->small_bytes = myri10ge_small_bytes;
2432
0da34b6d
BG		 2433 /* Firmware needs the big buff size as a power of 2. Lie and
2434 * tell him the buffer is larger, because we only use 1
2435 * buffer/pkt, and the mtu will prevent overruns.
2436 */
13348bee 2437 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2438 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2439 while (!is_power_of_2(big_pow2))
c7dab99b 2440 big_pow2++;
13348bee 2441 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2442 } else {
2443 big_pow2 = MYRI10GE_ALLOC_SIZE;
2444 mgp->big_bytes = big_pow2;
2445 }
2446
0dcffac1
BG		 2447 /* setup the per-slice data structures */
2448 for (slice = 0; slice < mgp->num_slices; slice++) {
2449 ss = &mgp->ss[slice];
2450
2451 status = myri10ge_get_txrx(mgp, slice);
2452 if (status != 0) {
2453 printk(KERN_ERR
2454 "myri10ge: %s: failed to get ring sizes or locations\n",
2455 dev->name);
2456 goto abort_with_rings;
2457 }
2458 status = myri10ge_allocate_rings(ss);
2459 if (status != 0)
2460 goto abort_with_rings;
236bb5e6
BG		 2461
2462 /* only firmware which supports multiple TX queues
2463 * supports setting up the tx stats on non-zero
2464 * slices */
2465 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2466 status = myri10ge_set_stats(mgp, slice);
2467 if (status) {
2468 printk(KERN_ERR
2469 "myri10ge: %s: Couldn't set stats DMA\n",
2470 dev->name);
2471 goto abort_with_rings;
2472 }
2473
2474 lro_mgr = &ss->rx_done.lro_mgr;
2475 lro_mgr->dev = dev;
2476 lro_mgr->features = LRO_F_NAPI;
2477 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2478 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2479 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2480 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2481 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2482 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
636d2f68 2483 lro_mgr->frag_align_pad = 2;
0dcffac1
BG		 2484 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2485 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2486
2487 /* must happen prior to any irq */
2488 napi_enable(&(ss)->napi);
2489 }
0da34b6d
BG		 2490
2491 /* now give firmware buffers sizes, and MTU */
2492 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2493 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2494 cmd.data0 = mgp->small_bytes;
2495 status |=
2496 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2497 cmd.data0 = big_pow2;
2498 status |=
2499 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2500 if (status) {
2501 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2502 dev->name);
2503 goto abort_with_rings;
2504 }
2505
0dcffac1
BG		 2506 /*
2507 * Set Linux style TSO mode; this is needed only on newer
2508 * firmware versions. Older versions default to Linux
2509 * style TSO
2510 */
2511 cmd.data0 = 0;
2512 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2513 if (status && status != -ENOSYS) {
2514 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
0da34b6d
BG		 2515 dev->name);
2516 goto abort_with_rings;
2517 }
2518
66341fff 2519 mgp->link_state = ~0U;
0da34b6d
BG		 2520 mgp->rdma_tags_available = 15;
2521
0da34b6d
BG		 2522 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2523 if (status) {
2524 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2525 dev->name);
2526 goto abort_with_rings;
2527 }
2528
0da34b6d
BG		 2529 mgp->running = MYRI10GE_ETH_RUNNING;
2530 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2531 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2532 netif_tx_wake_all_queues(dev);
2533
0da34b6d
BG		 2534 return 0;
2535
2536abort_with_rings:
051d36f3
BG		 2537 while (slice) {
2538 slice--;
2539 napi_disable(&mgp->ss[slice].napi);
2540 }
0dcffac1
BG		 2541 for (i = 0; i < mgp->num_slices; i++)
2542 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2543
df30a740
BG		 2544 myri10ge_free_irq(mgp);
2545
0da34b6d
BG		 2546abort_with_nothing:
2547 mgp->running = MYRI10GE_ETH_STOPPED;
2548 return -ENOMEM;
2549}
2550
2551static int myri10ge_close(struct net_device *dev)
2552{
b53bef84 2553 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2554 struct myri10ge_cmd cmd;
2555 int status, old_down_cnt;
0dcffac1 2556 int i;
0da34b6d 2557
0da34b6d
BG		 2558 if (mgp->running != MYRI10GE_ETH_RUNNING)
2559 return 0;
2560
0dcffac1 2561 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2562 return 0;
2563
2564 del_timer_sync(&mgp->watchdog_timer);
2565 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2566 for (i = 0; i < mgp->num_slices; i++) {
2567 napi_disable(&mgp->ss[i].napi);
2568 }
0da34b6d 2569 netif_carrier_off(dev);
236bb5e6
BG		 2570
2571 netif_tx_stop_all_queues(dev);
d0234215
BG		 2572 if (mgp->rebooted == 0) {
2573 old_down_cnt = mgp->down_cnt;
2574 mb();
2575 status =
2576 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2577 if (status)
2578 printk(KERN_ERR
2579 "myri10ge: %s: Couldn't bring down link\n",
2580 dev->name);
0da34b6d 2581
d0234215
BG		 2582 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2583 HZ);
2584 if (old_down_cnt == mgp->down_cnt)
2585 printk(KERN_ERR "myri10ge: %s never got down irq\n",
2586 dev->name);
2587 }
0da34b6d 2588 netif_tx_disable(dev);
df30a740 2589 myri10ge_free_irq(mgp);
0dcffac1
BG		 2590 for (i = 0; i < mgp->num_slices; i++)
2591 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2592
2593 mgp->running = MYRI10GE_ETH_STOPPED;
2594 return 0;
2595}
2596
2597/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2598 * backwards one at a time and handle ring wraps */
2599
2600static inline void
2601myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2602 struct mcp_kreq_ether_send *src, int cnt)
2603{
2604 int idx, starting_slot;
2605 starting_slot = tx->req;
2606 while (cnt > 1) {
2607 cnt--;
2608 idx = (starting_slot + cnt) & tx->mask;
2609 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2610 mb();
2611 }
2612}
2613
2614/*
2615 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2616 * at most 32 bytes at a time, so as to avoid involving the software
2617 * pio handler in the nic. We re-write the first segment's flags
2618 * to mark them valid only after writing the entire chain.
2619 */
2620
2621static inline void
2622myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2623 int cnt)
2624{
2625 int idx, i;
2626 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2627 struct mcp_kreq_ether_send *srcp;
2628 u8 last_flags;
2629
2630 idx = tx->req & tx->mask;
2631
2632 last_flags = src->flags;
2633 src->flags = 0;
2634 mb();
2635 dst = dstp = &tx->lanai[idx];
2636 srcp = src;
2637
2638 if ((idx + cnt) < tx->mask) {
2639 for (i = 0; i < (cnt - 1); i += 2) {
2640 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2641 mb(); /* force write every 32 bytes */
2642 srcp += 2;
2643 dstp += 2;
2644 }
2645 } else {
2646 /* submit all but the first request, and ensure
2647 * that it is submitted below */
2648 myri10ge_submit_req_backwards(tx, src, cnt);
2649 i = 0;
2650 }
2651 if (i < cnt) {
2652 /* submit the first request */
2653 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2654 mb(); /* barrier before setting valid flag */
2655 }
2656
2657 /* re-write the last 32-bits with the valid flags */
2658 src->flags = last_flags;
40f6cff5 2659 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2660 tx->req += cnt;
2661 mb();
2662}
2663
0da34b6d
BG		 2664/*
2665 * Transmit a packet. We need to split the packet so that a single
b53bef84 2666 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2667 * counting tricky. So rather than try to count segments up front, we
2668 * just give up if there are too few segments to hold a reasonably
2669 * fragmented packet currently available. If we run
2670 * out of segments while preparing a packet for DMA, we just linearize
2671 * it and try again.
2672 */
2673
61357325
SH		 2674static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2675 struct net_device *dev)
0da34b6d
BG		 2676{
2677 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2678 struct myri10ge_slice_state *ss;
0da34b6d 2679 struct mcp_kreq_ether_send *req;
b53bef84 2680 struct myri10ge_tx_buf *tx;
0da34b6d 2681 struct skb_frag_struct *frag;
236bb5e6 2682 struct netdev_queue *netdev_queue;
0da34b6d 2683 dma_addr_t bus;
40f6cff5
AV		 2684 u32 low;
2685 __be32 high_swapped;
0da34b6d
BG		 2686 unsigned int len;
2687 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2688 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2689 int cum_len, seglen, boundary, rdma_count;
2690 u8 flags, odd_flag;
2691
236bb5e6 2692 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2693 ss = &mgp->ss[queue];
2694 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2695 tx = &ss->tx;
236bb5e6 2696
0da34b6d
BG		 2697again:
2698 req = tx->req_list;
2699 avail = tx->mask - 1 - (tx->req - tx->done);
2700
2701 mss = 0;
2702 max_segments = MXGEFW_MAX_SEND_DESC;
2703
917690cd 2704 if (skb_is_gso(skb)) {
7967168c 2705 mss = skb_shinfo(skb)->gso_size;
917690cd 2706 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2707 }
0da34b6d
BG		 2708
2709 if ((unlikely(avail < max_segments))) {
2710 /* we are out of transmit resources */
b53bef84 2711 tx->stop_queue++;
236bb5e6 2712 netif_tx_stop_queue(netdev_queue);
5b548140 2713 return NETDEV_TX_BUSY;
0da34b6d
BG		 2714 }
2715
2716 /* Setup checksum offloading, if needed */
2717 cksum_offset = 0;
2718 pseudo_hdr_offset = 0;
2719 odd_flag = 0;
2720 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2721 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2722 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2723 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2724 /* If the headers are excessively large, then we must
2725 * fall back to a software checksum */
4f93fde0
BG		 2726 if (unlikely(!mss && (cksum_offset > 255 ||
2727 pseudo_hdr_offset > 127))) {
84fa7933 2728 if (skb_checksum_help(skb))
0da34b6d
BG		 2729 goto drop;
2730 cksum_offset = 0;
2731 pseudo_hdr_offset = 0;
2732 } else {
0da34b6d
BG		 2733 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2734 flags |= MXGEFW_FLAGS_CKSUM;
2735 }
2736 }
2737
2738 cum_len = 0;
2739
0da34b6d
BG		 2740 if (mss) { /* TSO */
2741 /* this removes any CKSUM flag from before */
2742 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2743
2744 /* negative cum_len signifies to the
2745 * send loop that we are still in the
2746 * header portion of the TSO packet.
4f93fde0 2747 * TSO header can be at most 1KB long */
ab6a5bb6 2748 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2749
4f93fde0
BG		 2750 /* for IPv6 TSO, the checksum offset stores the
2751 * TCP header length, to save the firmware from
2752 * the need to parse the headers */
2753 if (skb_is_gso_v6(skb)) {
2754 cksum_offset = tcp_hdrlen(skb);
2755 /* Can only handle headers <= max_tso6 long */
2756 if (unlikely(-cum_len > mgp->max_tso6))
2757 return myri10ge_sw_tso(skb, dev);
2758 }
0da34b6d
BG		 2759 /* for TSO, pseudo_hdr_offset holds mss.
2760 * The firmware figures out where to put
2761 * the checksum by parsing the header. */
40f6cff5 2762 pseudo_hdr_offset = mss;
0da34b6d 2763 } else
0da34b6d
BG		 2764 /* Mark small packets, and pad out tiny packets */
2765 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2766 flags |= MXGEFW_FLAGS_SMALL;
2767
2768 /* pad frames to at least ETH_ZLEN bytes */
2769 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2770 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2771 /* The packet is gone, so we must
2772 * return 0 */
b53bef84 2773 ss->stats.tx_dropped += 1;
6ed10654 2774 return NETDEV_TX_OK;
0da34b6d
BG		 2775 }
2776 /* adjust the len to account for the zero pad
2777 * so that the nic can know how long it is */
2778 skb->len = ETH_ZLEN;
2779 }
2780 }
2781
2782 /* map the skb for DMA */
2783 len = skb->len - skb->data_len;
2784 idx = tx->req & tx->mask;
2785 tx->info[idx].skb = skb;
2786 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2787 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2788 pci_unmap_len_set(&tx->info[idx], len, len);
2789
2790 frag_cnt = skb_shinfo(skb)->nr_frags;
2791 frag_idx = 0;
2792 count = 0;
2793 rdma_count = 0;
2794
2795 /* "rdma_count" is the number of RDMAs belonging to the
2796 * current packet BEFORE the current send request. For
2797 * non-TSO packets, this is equal to "count".
2798 * For TSO packets, rdma_count needs to be reset
2799 * to 0 after a segment cut.
2800 *
2801 * The rdma_count field of the send request is
2802 * the number of RDMAs of the packet starting at
2803 * that request. For TSO send requests with one ore more cuts
2804 * in the middle, this is the number of RDMAs starting
2805 * after the last cut in the request. All previous
2806 * segments before the last cut implicitly have 1 RDMA.
2807 *
2808 * Since the number of RDMAs is not known beforehand,
2809 * it must be filled-in retroactively - after each
2810 * segmentation cut or at the end of the entire packet.
2811 */
2812
2813 while (1) {
2814 /* Break the SKB or Fragment up into pieces which
b53bef84 2815 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2816 low = MYRI10GE_LOWPART_TO_U32(bus);
2817 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2818 while (len) {
2819 u8 flags_next;
2820 int cum_len_next;
2821
2822 if (unlikely(count == max_segments))
2823 goto abort_linearize;
2824
b53bef84
BG		 2825 boundary =
2826 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2827 seglen = boundary - low;
2828 if (seglen > len)
2829 seglen = len;
2830 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2831 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2832 if (mss) { /* TSO */
2833 (req - rdma_count)->rdma_count = rdma_count + 1;
2834
2835 if (likely(cum_len >= 0)) { /* payload */
2836 int next_is_first, chop;
2837
2838 chop = (cum_len_next > mss);
2839 cum_len_next = cum_len_next % mss;
2840 next_is_first = (cum_len_next == 0);
2841 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2842 flags_next |= next_is_first *
2843 MXGEFW_FLAGS_FIRST;
2844 rdma_count |= -(chop | next_is_first);
2845 rdma_count += chop & !next_is_first;
2846 } else if (likely(cum_len_next >= 0)) { /* header ends */
2847 int small;
2848
2849 rdma_count = -1;
2850 cum_len_next = 0;
2851 seglen = -cum_len;
2852 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2853 flags_next = MXGEFW_FLAGS_TSO_PLD |
2854 MXGEFW_FLAGS_FIRST |
2855 (small * MXGEFW_FLAGS_SMALL);
2856 }
2857 }
0da34b6d
BG		 2858 req->addr_high = high_swapped;
2859 req->addr_low = htonl(low);
40f6cff5 2860 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2861 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2862 req->rdma_count = 1;
2863 req->length = htons(seglen);
2864 req->cksum_offset = cksum_offset;
2865 req->flags = flags | ((cum_len & 1) * odd_flag);
2866
2867 low += seglen;
2868 len -= seglen;
2869 cum_len = cum_len_next;
2870 flags = flags_next;
2871 req++;
2872 count++;
2873 rdma_count++;
4f93fde0
BG		 2874 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2875 if (unlikely(cksum_offset > seglen))
2876 cksum_offset -= seglen;
2877 else
2878 cksum_offset = 0;
2879 }
0da34b6d
BG		 2880 }
2881 if (frag_idx == frag_cnt)
2882 break;
2883
2884 /* map next fragment for DMA */
2885 idx = (count + tx->req) & tx->mask;
2886 frag = &skb_shinfo(skb)->frags[frag_idx];
2887 frag_idx++;
2888 len = frag->size;
2889 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2890 len, PCI_DMA_TODEVICE);
2891 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2892 pci_unmap_len_set(&tx->info[idx], len, len);
2893 }
2894
2895 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2896 if (mss)
2897 do {
2898 req--;
2899 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2900 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2901 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2902 idx = ((count - 1) + tx->req) & tx->mask;
2903 tx->info[idx].last = 1;
e454e7e2 2904 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 2905 /* if using multiple tx queues, make sure NIC polls the
2906 * current slice */
2907 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2908 tx->queue_active = 1;
2909 put_be32(htonl(1), tx->send_go);
8c2f5fa5 2910 mb();
6824a105 2911 mmiowb();
236bb5e6 2912 }
0da34b6d
BG		 2913 tx->pkt_start++;
2914 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2915 tx->stop_queue++;
236bb5e6 2916 netif_tx_stop_queue(netdev_queue);
0da34b6d 2917 }
6ed10654 2918 return NETDEV_TX_OK;
0da34b6d
BG		 2919
2920abort_linearize:
2921 /* Free any DMA resources we've alloced and clear out the skb
2922 * slot so as to not trip up assertions, and to avoid a
2923 * double-free if linearizing fails */
2924
2925 last_idx = (idx + 1) & tx->mask;
2926 idx = tx->req & tx->mask;
2927 tx->info[idx].skb = NULL;
2928 do {
2929 len = pci_unmap_len(&tx->info[idx], len);
2930 if (len) {
2931 if (tx->info[idx].skb != NULL)
2932 pci_unmap_single(mgp->pdev,
2933 pci_unmap_addr(&tx->info[idx],
2934 bus), len,
2935 PCI_DMA_TODEVICE);
2936 else
2937 pci_unmap_page(mgp->pdev,
2938 pci_unmap_addr(&tx->info[idx],
2939 bus), len,
2940 PCI_DMA_TODEVICE);
2941 pci_unmap_len_set(&tx->info[idx], len, 0);
2942 tx->info[idx].skb = NULL;
2943 }
2944 idx = (idx + 1) & tx->mask;
2945 } while (idx != last_idx);
89114afd 2946 if (skb_is_gso(skb)) {
0da34b6d
BG		 2947 printk(KERN_ERR
2948 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2949 mgp->dev->name);
2950 goto drop;
2951 }
2952
bec0e859 2953 if (skb_linearize(skb))
0da34b6d
BG		 2954 goto drop;
2955
b53bef84 2956 tx->linearized++;
0da34b6d
BG		 2957 goto again;
2958
2959drop:
2960 dev_kfree_skb_any(skb);
b53bef84 2961 ss->stats.tx_dropped += 1;
6ed10654 2962 return NETDEV_TX_OK;
0da34b6d
BG		 2963
2964}
2965
61357325
SH		 2966static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
2967 struct net_device *dev)
4f93fde0
BG		 2968{
2969 struct sk_buff *segs, *curr;
b53bef84 2970 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 2971 struct myri10ge_slice_state *ss;
61357325 2972 netdev_tx_t status;
4f93fde0
BG		 2973
2974 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2975 if (IS_ERR(segs))
4f93fde0
BG		 2976 goto drop;
2977
2978 while (segs) {
2979 curr = segs;
2980 segs = segs->next;
2981 curr->next = NULL;
2982 status = myri10ge_xmit(curr, dev);
2983 if (status != 0) {
2984 dev_kfree_skb_any(curr);
2985 if (segs != NULL) {
2986 curr = segs;
2987 segs = segs->next;
2988 curr->next = NULL;
2989 dev_kfree_skb_any(segs);
2990 }
2991 goto drop;
2992 }
2993 }
2994 dev_kfree_skb_any(skb);
ec634fe3 2995 return NETDEV_TX_OK;
4f93fde0
BG		 2996
2997drop:
d6279c88 2998 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 2999 dev_kfree_skb_any(skb);
d6279c88 3000 ss->stats.tx_dropped += 1;
ec634fe3 3001 return NETDEV_TX_OK;
4f93fde0
BG		 3002}
3003
0da34b6d
BG		 3004static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
3005{
3006 struct myri10ge_priv *mgp = netdev_priv(dev);
0dcffac1 3007 struct myri10ge_slice_netstats *slice_stats;
6dc34941 3008 struct net_device_stats *stats = &dev->stats;
0dcffac1
BG		 3009 int i;
3010
59081825 3011 spin_lock(&mgp->stats_lock);
0dcffac1
BG		 3012 memset(stats, 0, sizeof(*stats));
3013 for (i = 0; i < mgp->num_slices; i++) {
3014 slice_stats = &mgp->ss[i].stats;
3015 stats->rx_packets += slice_stats->rx_packets;
3016 stats->tx_packets += slice_stats->tx_packets;
3017 stats->rx_bytes += slice_stats->rx_bytes;
3018 stats->tx_bytes += slice_stats->tx_bytes;
3019 stats->rx_dropped += slice_stats->rx_dropped;
3020 stats->tx_dropped += slice_stats->tx_dropped;
3021 }
59081825 3022 spin_unlock(&mgp->stats_lock);
0dcffac1 3023 return stats;
0da34b6d
BG		 3024}
3025
3026static void myri10ge_set_multicast_list(struct net_device *dev)
3027{
b53bef84 3028 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 3029 struct myri10ge_cmd cmd;
85a7ea1b 3030 struct dev_mc_list *mc_list;
6250223e 3031 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 3032 int err;
3033
0da34b6d
BG		 3034 /* can be called from atomic contexts,
3035 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 3036 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3037
3038 /* This firmware is known to not support multicast */
2f76216f 3039 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 3040 return;
3041
3042 /* Disable multicast filtering */
3043
3044 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3045 if (err != 0) {
3046 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
3047 " error status: %d\n", dev->name, err);
3048 goto abort;
3049 }
3050
2f76216f 3051 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 3052 /* request to disable multicast filtering, so quit here */
3053 return;
3054 }
3055
3056 /* Flush the filters */
3057
3058 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3059 &cmd, 1);
3060 if (err != 0) {
3061 printk(KERN_ERR
3062 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
3063 ", error status: %d\n", dev->name, err);
3064 goto abort;
3065 }
3066
3067 /* Walk the multicast list, and add each address */
3068 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 3069 memcpy(data, &mc_list->dmi_addr, 6);
3070 cmd.data0 = ntohl(data[0]);
3071 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 3072 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3073 &cmd, 1);
3074
3075 if (err != 0) {
3076 printk(KERN_ERR "myri10ge: %s: Failed "
3077 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
3078 "%d\t", dev->name, err);
e174961c 3079 printk(KERN_ERR "MAC %pM\n", mc_list->dmi_addr);
85a7ea1b
BG		 3080 goto abort;
3081 }
3082 }
3083 /* Enable multicast filtering */
3084 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3085 if (err != 0) {
3086 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3087 "error status: %d\n", dev->name, err);
3088 goto abort;
3089 }
3090
3091 return;
3092
3093abort:
3094 return;
0da34b6d
BG		 3095}
3096
3097static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3098{
3099 struct sockaddr *sa = addr;
3100 struct myri10ge_priv *mgp = netdev_priv(dev);
3101 int status;
3102
3103 if (!is_valid_ether_addr(sa->sa_data))
3104 return -EADDRNOTAVAIL;
3105
3106 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3107 if (status != 0) {
3108 printk(KERN_ERR
3109 "myri10ge: %s: changing mac address failed with %d\n",
3110 dev->name, status);
3111 return status;
3112 }
3113
3114 /* change the dev structure */
3115 memcpy(dev->dev_addr, sa->sa_data, 6);
3116 return 0;
3117}
3118
3119static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3120{
3121 struct myri10ge_priv *mgp = netdev_priv(dev);
3122 int error = 0;
3123
3124 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3125 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3126 dev->name, new_mtu);
3127 return -EINVAL;
3128 }
3129 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3130 dev->name, dev->mtu, new_mtu);
3131 if (mgp->running) {
3132 /* if we change the mtu on an active device, we must
3133 * reset the device so the firmware sees the change */
3134 myri10ge_close(dev);
3135 dev->mtu = new_mtu;
3136 myri10ge_open(dev);
3137 } else
3138 dev->mtu = new_mtu;
3139
3140 return error;
3141}
3142
3143/*
3144 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3145 * Only do it if the bridge is a root port since we don't want to disturb
3146 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3147 */
3148
0da34b6d
BG		 3149static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3150{
3151 struct pci_dev *bridge = mgp->pdev->bus->self;
3152 struct device *dev = &mgp->pdev->dev;
3153 unsigned cap;
3154 unsigned err_cap;
3155 u16 val;
3156 u8 ext_type;
3157 int ret;
3158
3159 if (!myri10ge_ecrc_enable || !bridge)
3160 return;
3161
3162 /* check that the bridge is a root port */
3163 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3164 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3165 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3166 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3167 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3168 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3169
3170 /* Walk the hierarchy up to the root port
3171 * where ECRC has to be enabled */
3172 do {
eca3fd83 3173 prev_bridge = bridge;
0da34b6d 3174 bridge = bridge->bus->self;
eca3fd83 3175 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3176 dev_err(dev,
3177 "Failed to find root port"
3178 " to force ECRC\n");
3179 return;
3180 }
3181 cap =
3182 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3183 pci_read_config_word(bridge,
3184 cap + PCI_CAP_FLAGS, &val);
3185 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3186 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3187
3188 dev_info(dev,
3189 "Forcing ECRC on non-root port %s"
3190 " (enabling on root port %s)\n",
3191 pci_name(old_bridge), pci_name(bridge));
3192 } else {
3193 dev_err(dev,
3194 "Not enabling ECRC on non-root port %s\n",
3195 pci_name(bridge));
3196 return;
3197 }
3198 }
3199
3200 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3201 if (!cap)
3202 return;
3203
3204 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3205 if (ret) {
3206 dev_err(dev, "failed reading ext-conf-space of %s\n",
3207 pci_name(bridge));
3208 dev_err(dev, "\t pci=nommconf in use? "
3209 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3210 return;
3211 }
3212 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3213 return;
3214
3215 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3216 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3217 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3218}
3219
3220/*
3221 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3222 * when the PCI-E Completion packets are aligned on an 8-byte
3223 * boundary. Some PCI-E chip sets always align Completion packets; on
3224 * the ones that do not, the alignment can be enforced by enabling
3225 * ECRC generation (if supported).
3226 *
3227 * When PCI-E Completion packets are not aligned, it is actually more
3228 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3229 *
3230 * If the driver can neither enable ECRC nor verify that it has
3231 * already been enabled, then it must use a firmware image which works
0dcffac1 3232 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3233 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3234 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3235 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3236 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3237 */
3238
5443e9ea 3239static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3240{
5443e9ea
BG		 3241 struct pci_dev *pdev = mgp->pdev;
3242 struct device *dev = &pdev->dev;
302d242c 3243 int status;
0da34b6d 3244
b53bef84 3245 mgp->tx_boundary = 4096;
5443e9ea
BG		 3246 /*
3247 * Verify the max read request size was set to 4KB
3248 * before trying the test with 4KB.
3249 */
302d242c
BG		 3250 status = pcie_get_readrq(pdev);
3251 if (status < 0) {
5443e9ea
BG		 3252 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3253 goto abort;
3254 }
302d242c
BG		 3255 if (status != 4096) {
3256 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3257 mgp->tx_boundary = 2048;
5443e9ea
BG		 3258 }
3259 /*
3260 * load the optimized firmware (which assumes aligned PCIe
3261 * completions) in order to see if it works on this host.
3262 */
3263 mgp->fw_name = myri10ge_fw_aligned;
0dcffac1 3264 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3265 if (status != 0) {
3266 goto abort;
3267 }
3268
3269 /*
3270 * Enable ECRC if possible
3271 */
3272 myri10ge_enable_ecrc(mgp);
3273
3274 /*
3275 * Run a DMA test which watches for unaligned completions and
3276 * aborts on the first one seen.
3277 */
3278
3279 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3280 if (status == 0)
3281 return; /* keep the aligned firmware */
3282
3283 if (status != -E2BIG)
3284 dev_warn(dev, "DMA test failed: %d\n", status);
3285 if (status == -ENOSYS)
3286 dev_warn(dev, "Falling back to ethp! "
3287 "Please install up to date fw\n");
3288abort:
3289 /* fall back to using the unaligned firmware */
b53bef84 3290 mgp->tx_boundary = 2048;
0da34b6d
BG		 3291 mgp->fw_name = myri10ge_fw_unaligned;
3292
5443e9ea
BG		 3293}
3294
3295static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3296{
2d90b0aa
BG		 3297 int overridden = 0;
3298
0da34b6d 3299 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 3300 int link_width, exp_cap;
3301 u16 lnk;
3302
3303 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3304 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3305 link_width = (lnk >> 4) & 0x3f;
3306
ce7f9368
BG		 3307 /* Check to see if Link is less than 8 or if the
3308 * upstream bridge is known to provide aligned
3309 * completions */
3310 if (link_width < 8) {
3311 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3312 link_width);
b53bef84 3313 mgp->tx_boundary = 4096;
ce7f9368 3314 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 3315 } else {
3316 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3317 }
3318 } else {
3319 if (myri10ge_force_firmware == 1) {
3320 dev_info(&mgp->pdev->dev,
3321 "Assuming aligned completions (forced)\n");
b53bef84 3322 mgp->tx_boundary = 4096;
0da34b6d
BG		 3323 mgp->fw_name = myri10ge_fw_aligned;
3324 } else {
3325 dev_info(&mgp->pdev->dev,
3326 "Assuming unaligned completions (forced)\n");
b53bef84 3327 mgp->tx_boundary = 2048;
0da34b6d
BG		 3328 mgp->fw_name = myri10ge_fw_unaligned;
3329 }
3330 }
3331 if (myri10ge_fw_name != NULL) {
2d90b0aa 3332 overridden = 1;
0da34b6d
BG		 3333 mgp->fw_name = myri10ge_fw_name;
3334 }
2d90b0aa
BG		 3335 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3336 myri10ge_fw_names[mgp->board_number] != NULL &&
3337 strlen(myri10ge_fw_names[mgp->board_number])) {
3338 mgp->fw_name = myri10ge_fw_names[mgp->board_number];
3339 overridden = 1;
3340 }
3341 if (overridden)
3342 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3343 mgp->fw_name);
0da34b6d
BG		 3344}
3345
0da34b6d 3346#ifdef CONFIG_PM
0da34b6d
BG		 3347static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3348{
3349 struct myri10ge_priv *mgp;
3350 struct net_device *netdev;
3351
3352 mgp = pci_get_drvdata(pdev);
3353 if (mgp == NULL)
3354 return -EINVAL;
3355 netdev = mgp->dev;
3356
3357 netif_device_detach(netdev);
3358 if (netif_running(netdev)) {
3359 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3360 rtnl_lock();
3361 myri10ge_close(netdev);
3362 rtnl_unlock();
3363 }
3364 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3365 pci_save_state(pdev);
0da34b6d 3366 pci_disable_device(pdev);
1a63e846
BG		 3367
3368 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3369}
3370
3371static int myri10ge_resume(struct pci_dev *pdev)
3372{
3373 struct myri10ge_priv *mgp;
3374 struct net_device *netdev;
3375 int status;
3376 u16 vendor;
3377
3378 mgp = pci_get_drvdata(pdev);
3379 if (mgp == NULL)
3380 return -EINVAL;
3381 netdev = mgp->dev;
3382 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3383 msleep(5); /* give card time to respond */
3384 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3385 if (vendor == 0xffff) {
3386 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3387 mgp->dev->name);
3388 return -EIO;
3389 }
83f6e152 3390
1a63e846
BG		 3391 status = pci_restore_state(pdev);
3392 if (status)
3393 return status;
4c2248cc
BG		 3394
3395 status = pci_enable_device(pdev);
1a63e846 3396 if (status) {
4c2248cc 3397 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3398 return status;
4c2248cc
BG		 3399 }
3400
0da34b6d
BG		 3401 pci_set_master(pdev);
3402
0da34b6d 3403 myri10ge_reset(mgp);
013b68bf 3404 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3405
3406 /* Save configuration space to be restored if the
3407 * nic resets due to a parity error */
83f6e152 3408 pci_save_state(pdev);
0da34b6d
BG		 3409
3410 if (netif_running(netdev)) {
3411 rtnl_lock();
df30a740 3412 status = myri10ge_open(netdev);
0da34b6d 3413 rtnl_unlock();
df30a740
BG		 3414 if (status != 0)
3415 goto abort_with_enabled;
3416
0da34b6d
BG		 3417 }
3418 netif_device_attach(netdev);
3419
3420 return 0;
3421
4c2248cc
BG		 3422abort_with_enabled:
3423 pci_disable_device(pdev);
0da34b6d
BG		 3424 return -EIO;
3425
3426}
0da34b6d
BG		 3427#endif /* CONFIG_PM */
3428
3429static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3430{
3431 struct pci_dev *pdev = mgp->pdev;
3432 int vs = mgp->vendor_specific_offset;
3433 u32 reboot;
3434
3435 /*enter read32 mode */
3436 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3437
3438 /*read REBOOT_STATUS (0xfffffff0) */
3439 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3440 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3441 return reboot;
3442}
3443
3444/*
3445 * This watchdog is used to check whether the board has suffered
3446 * from a parity error and needs to be recovered.
3447 */
c4028958 3448static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3449{
c4028958 3450 struct myri10ge_priv *mgp =
6250223e 3451 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 3452 struct myri10ge_tx_buf *tx;
0da34b6d 3453 u32 reboot;
d0234215 3454 int status, rebooted;
0dcffac1 3455 int i;
0da34b6d
BG		 3456 u16 cmd, vendor;
3457
3458 mgp->watchdog_resets++;
3459 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
d0234215 3460 rebooted = 0;
0da34b6d
BG		 3461 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3462 /* Bus master DMA disabled? Check to see
3463 * if the card rebooted due to a parity error
3464 * For now, just report it */
3465 reboot = myri10ge_read_reboot(mgp);
3466 printk(KERN_ERR
f181137f
BG		 3467 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3468 mgp->dev->name, reboot,
3469 myri10ge_reset_recover ? " " : " not");
3470 if (myri10ge_reset_recover == 0)
3471 return;
d0234215
BG		 3472 rtnl_lock();
3473 mgp->rebooted = 1;
3474 rebooted = 1;
3475 myri10ge_close(mgp->dev);
f181137f 3476 myri10ge_reset_recover--;
d0234215 3477 mgp->rebooted = 0;
0da34b6d
BG		 3478 /*
3479 * A rebooted nic will come back with config space as
3480 * it was after power was applied to PCIe bus.
3481 * Attempt to restore config space which was saved
3482 * when the driver was loaded, or the last time the
3483 * nic was resumed from power saving mode.
3484 */
83f6e152 3485 pci_restore_state(mgp->pdev);
7adda30c
BG		 3486
3487 /* save state again for accounting reasons */
83f6e152 3488 pci_save_state(mgp->pdev);
7adda30c 3489
0da34b6d
BG		 3490 } else {
3491 /* if we get back -1's from our slot, perhaps somebody
3492 * powered off our card. Don't try to reset it in
3493 * this case */
3494 if (cmd == 0xffff) {
3495 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3496 if (vendor == 0xffff) {
3497 printk(KERN_ERR
3498 "myri10ge: %s: device disappeared!\n",
3499 mgp->dev->name);
3500 return;
3501 }
3502 }
3503 /* Perhaps it is a software error. Try to reset */
3504
3505 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3506 mgp->dev->name);
0dcffac1
BG		 3507 for (i = 0; i < mgp->num_slices; i++) {
3508 tx = &mgp->ss[i].tx;
3509 printk(KERN_INFO
236bb5e6
BG		 3510 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3511 mgp->dev->name, i, tx->queue_active, tx->req,
3512 tx->done, tx->pkt_start, tx->pkt_done,
0dcffac1
BG		 3513 (int)ntohl(mgp->ss[i].fw_stats->
3514 send_done_count));
3515 msleep(2000);
3516 printk(KERN_INFO
236bb5e6
BG		 3517 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3518 mgp->dev->name, i, tx->queue_active, tx->req,
3519 tx->done, tx->pkt_start, tx->pkt_done,
0dcffac1
BG		 3520 (int)ntohl(mgp->ss[i].fw_stats->
3521 send_done_count));
3522 }
0da34b6d 3523 }
236bb5e6 3524
d0234215
BG		 3525 if (!rebooted) {
3526 rtnl_lock();
3527 myri10ge_close(mgp->dev);
3528 }
0dcffac1 3529 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3530 if (status != 0)
3531 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3532 mgp->dev->name);
3533 else
3534 myri10ge_open(mgp->dev);
3535 rtnl_unlock();
3536}
3537
3538/*
3539 * We use our own timer routine rather than relying upon
3540 * netdev->tx_timeout because we have a very large hardware transmit
3541 * queue. Due to the large queue, the netdev->tx_timeout function
3542 * cannot detect a NIC with a parity error in a timely fashion if the
3543 * NIC is lightly loaded.
3544 */
3545static void myri10ge_watchdog_timer(unsigned long arg)
3546{
3547 struct myri10ge_priv *mgp;
b53bef84 3548 struct myri10ge_slice_state *ss;
d0234215 3549 int i, reset_needed, busy_slice_cnt;
626fda94 3550 u32 rx_pause_cnt;
d0234215 3551 u16 cmd;
0da34b6d
BG		 3552
3553 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3554
0dcffac1 3555 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
d0234215 3556 busy_slice_cnt = 0;
0dcffac1
BG		 3557 for (i = 0, reset_needed = 0;
3558 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3559
0dcffac1
BG		 3560 ss = &mgp->ss[i];
3561 if (ss->rx_small.watchdog_needed) {
3562 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3563 mgp->small_bytes + MXGEFW_PAD,
3564 1);
3565 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3566 myri10ge_fill_thresh)
3567 ss->rx_small.watchdog_needed = 0;
3568 }
3569 if (ss->rx_big.watchdog_needed) {
3570 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3571 mgp->big_bytes, 1);
3572 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3573 myri10ge_fill_thresh)
3574 ss->rx_big.watchdog_needed = 0;
3575 }
3576
3577 if (ss->tx.req != ss->tx.done &&
3578 ss->tx.done == ss->watchdog_tx_done &&
3579 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3580 /* nic seems like it might be stuck.. */
3581 if (rx_pause_cnt != mgp->watchdog_pause) {
3582 if (net_ratelimit())
236bb5e6
BG		 3583 printk(KERN_WARNING
3584 "myri10ge %s slice %d:"
0dcffac1 3585 "TX paused, check link partner\n",
236bb5e6 3586 mgp->dev->name, i);
0dcffac1 3587 } else {
236bb5e6
BG		 3588 printk(KERN_WARNING
3589 "myri10ge %s slice %d stuck:",
3590 mgp->dev->name, i);
0dcffac1
BG		 3591 reset_needed = 1;
3592 }
626fda94 3593 }
d0234215
BG		 3594 if (ss->watchdog_tx_done != ss->tx.done ||
3595 ss->watchdog_rx_done != ss->rx_done.cnt) {
3596 busy_slice_cnt++;
3597 }
0dcffac1
BG		 3598 ss->watchdog_tx_done = ss->tx.done;
3599 ss->watchdog_tx_req = ss->tx.req;
d0234215
BG		 3600 ss->watchdog_rx_done = ss->rx_done.cnt;
3601 }
3602 /* if we've sent or received no traffic, poll the NIC to
3603 * ensure it is still there. Otherwise, we risk not noticing
3604 * an error in a timely fashion */
3605 if (busy_slice_cnt == 0) {
3606 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3607 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3608 reset_needed = 1;
3609 }
626fda94 3610 }
626fda94 3611 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3612
3613 if (reset_needed) {
3614 schedule_work(&mgp->watchdog_work);
3615 } else {
3616 /* rearm timer */
3617 mod_timer(&mgp->watchdog_timer,
3618 jiffies + myri10ge_watchdog_timeout * HZ);
3619 }
0da34b6d
BG		 3620}
3621
77929732
BG		 3622static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3623{
3624 struct myri10ge_slice_state *ss;
3625 struct pci_dev *pdev = mgp->pdev;
3626 size_t bytes;
3627 int i;
3628
3629 if (mgp->ss == NULL)
3630 return;
3631
3632 for (i = 0; i < mgp->num_slices; i++) {
3633 ss = &mgp->ss[i];
3634 if (ss->rx_done.entry != NULL) {
3635 bytes = mgp->max_intr_slots *
3636 sizeof(*ss->rx_done.entry);
3637 dma_free_coherent(&pdev->dev, bytes,
3638 ss->rx_done.entry, ss->rx_done.bus);
3639 ss->rx_done.entry = NULL;
3640 }
3641 if (ss->fw_stats != NULL) {
3642 bytes = sizeof(*ss->fw_stats);
3643 dma_free_coherent(&pdev->dev, bytes,
3644 ss->fw_stats, ss->fw_stats_bus);
3645 ss->fw_stats = NULL;
3646 }
3647 }
3648 kfree(mgp->ss);
3649 mgp->ss = NULL;
3650}
3651
3652static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3653{
3654 struct myri10ge_slice_state *ss;
3655 struct pci_dev *pdev = mgp->pdev;
3656 size_t bytes;
3657 int i;
3658
3659 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3660 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3661 if (mgp->ss == NULL) {
3662 return -ENOMEM;
3663 }
3664
3665 for (i = 0; i < mgp->num_slices; i++) {
3666 ss = &mgp->ss[i];
3667 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3668 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3669 &ss->rx_done.bus,
3670 GFP_KERNEL);
3671 if (ss->rx_done.entry == NULL)
3672 goto abort;
3673 memset(ss->rx_done.entry, 0, bytes);
3674 bytes = sizeof(*ss->fw_stats);
3675 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3676 &ss->fw_stats_bus,
3677 GFP_KERNEL);
3678 if (ss->fw_stats == NULL)
3679 goto abort;
3680 ss->mgp = mgp;
3681 ss->dev = mgp->dev;
3682 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3683 myri10ge_napi_weight);
3684 }
3685 return 0;
3686abort:
3687 myri10ge_free_slices(mgp);
3688 return -ENOMEM;
3689}
3690
3691/*
3692 * This function determines the number of slices supported.
3693 * The number slices is the minumum of the number of CPUS,
3694 * the number of MSI-X irqs supported, the number of slices
3695 * supported by the firmware
3696 */
3697static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3698{
3699 struct myri10ge_cmd cmd;
3700 struct pci_dev *pdev = mgp->pdev;
3701 char *old_fw;
3702 int i, status, ncpus, msix_cap;
3703
3704 mgp->num_slices = 1;
3705 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3706 ncpus = num_online_cpus();
3707
3708 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3709 (myri10ge_max_slices == -1 && ncpus < 2))
3710 return;
3711
3712 /* try to load the slice aware rss firmware */
3713 old_fw = mgp->fw_name;
13b2738c
BG		 3714 if (myri10ge_fw_name != NULL) {
3715 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3716 myri10ge_fw_name);
3717 mgp->fw_name = myri10ge_fw_name;
3718 } else if (old_fw == myri10ge_fw_aligned)
77929732
BG		 3719 mgp->fw_name = myri10ge_fw_rss_aligned;
3720 else
3721 mgp->fw_name = myri10ge_fw_rss_unaligned;
3722 status = myri10ge_load_firmware(mgp, 0);
3723 if (status != 0) {
3724 dev_info(&pdev->dev, "Rss firmware not found\n");
3725 return;
3726 }
3727
3728 /* hit the board with a reset to ensure it is alive */
3729 memset(&cmd, 0, sizeof(cmd));
3730 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3731 if (status != 0) {
3732 dev_err(&mgp->pdev->dev, "failed reset\n");
3733 goto abort_with_fw;
3734 return;
3735 }
3736
3737 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3738
3739 /* tell it the size of the interrupt queues */
3740 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3741 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3742 if (status != 0) {
3743 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3744 goto abort_with_fw;
3745 }
3746
3747 /* ask the maximum number of slices it supports */
3748 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3749 if (status != 0)
3750 goto abort_with_fw;
3751 else
3752 mgp->num_slices = cmd.data0;
3753
3754 /* Only allow multiple slices if MSI-X is usable */
3755 if (!myri10ge_msi) {
3756 goto abort_with_fw;
3757 }
3758
3759 /* if the admin did not specify a limit to how many
3760 * slices we should use, cap it automatically to the
3761 * number of CPUs currently online */
3762 if (myri10ge_max_slices == -1)
3763 myri10ge_max_slices = ncpus;
3764
3765 if (mgp->num_slices > myri10ge_max_slices)
3766 mgp->num_slices = myri10ge_max_slices;
3767
3768 /* Now try to allocate as many MSI-X vectors as we have
3769 * slices. We give up on MSI-X if we can only get a single
3770 * vector. */
3771
3772 mgp->msix_vectors = kzalloc(mgp->num_slices *
3773 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3774 if (mgp->msix_vectors == NULL)
3775 goto disable_msix;
3776 for (i = 0; i < mgp->num_slices; i++) {
3777 mgp->msix_vectors[i].entry = i;
3778 }
3779
3780 while (mgp->num_slices > 1) {
3781 /* make sure it is a power of two */
3782 while (!is_power_of_2(mgp->num_slices))
3783 mgp->num_slices--;
3784 if (mgp->num_slices == 1)
3785 goto disable_msix;
3786 status = pci_enable_msix(pdev, mgp->msix_vectors,
3787 mgp->num_slices);
3788 if (status == 0) {
3789 pci_disable_msix(pdev);
3790 return;
3791 }
3792 if (status > 0)
3793 mgp->num_slices = status;
3794 else
3795 goto disable_msix;
3796 }
3797
3798disable_msix:
3799 if (mgp->msix_vectors != NULL) {
3800 kfree(mgp->msix_vectors);
3801 mgp->msix_vectors = NULL;
3802 }
3803
3804abort_with_fw:
3805 mgp->num_slices = 1;
3806 mgp->fw_name = old_fw;
3807 myri10ge_load_firmware(mgp, 0);
3808}
77929732 3809
8126089f
SH		 3810static const struct net_device_ops myri10ge_netdev_ops = {
3811 .ndo_open = myri10ge_open,
3812 .ndo_stop = myri10ge_close,
3813 .ndo_start_xmit = myri10ge_xmit,
3814 .ndo_get_stats = myri10ge_get_stats,
3815 .ndo_validate_addr = eth_validate_addr,
3816 .ndo_change_mtu = myri10ge_change_mtu,
3817 .ndo_set_multicast_list = myri10ge_set_multicast_list,
3818 .ndo_set_mac_address = myri10ge_set_mac_address,
3819};
3820
0da34b6d
BG		 3821static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3822{
3823 struct net_device *netdev;
3824 struct myri10ge_priv *mgp;
3825 struct device *dev = &pdev->dev;
0da34b6d
BG		 3826 int i;
3827 int status = -ENXIO;
0da34b6d 3828 int dac_enabled;
00b5e505 3829 unsigned hdr_offset, ss_offset;
2d90b0aa 3830 static int board_number;
0da34b6d 3831
236bb5e6 3832 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
0da34b6d
BG		 3833 if (netdev == NULL) {
3834 dev_err(dev, "Could not allocate ethernet device\n");
3835 return -ENOMEM;
3836 }
3837
b245fb67
MH		 3838 SET_NETDEV_DEV(netdev, &pdev->dev);
3839
0da34b6d 3840 mgp = netdev_priv(netdev);
0da34b6d
BG		 3841 mgp->dev = netdev;
3842 mgp->pdev = pdev;
3843 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3844 mgp->pause = myri10ge_flow_control;
3845 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3846 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3847 mgp->board_number = board_number;
0da34b6d
BG		 3848 init_waitqueue_head(&mgp->down_wq);
3849
3850 if (pci_enable_device(pdev)) {
3851 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3852 status = -ENODEV;
3853 goto abort_with_netdev;
3854 }
0da34b6d
BG		 3855
3856 /* Find the vendor-specific cap so we can check
3857 * the reboot register later on */
3858 mgp->vendor_specific_offset
3859 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3860
3861 /* Set our max read request to 4KB */
302d242c 3862 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3863 if (status != 0) {
3864 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3865 status);
e3fd5534 3866 goto abort_with_enabled;
0da34b6d
BG		 3867 }
3868
3869 pci_set_master(pdev);
3870 dac_enabled = 1;
6a35528a 3871 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3872 if (status != 0) {
3873 dac_enabled = 0;
3874 dev_err(&pdev->dev,
898eb71c
JP		 3875 "64-bit pci address mask was refused, "
3876 "trying 32-bit\n");
284901a9 3877 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 3878 }
3879 if (status != 0) {
3880 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 3881 goto abort_with_enabled;
0da34b6d 3882 }
6a35528a 3883 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 3884 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3885 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d 3886 if (mgp->cmd == NULL)
e3fd5534 3887 goto abort_with_enabled;
0da34b6d 3888
0da34b6d
BG		 3889 mgp->board_span = pci_resource_len(pdev, 0);
3890 mgp->iomem_base = pci_resource_start(pdev, 0);
3891 mgp->mtrr = -1;
276e26c3 3892 mgp->wc_enabled = 0;
0da34b6d
BG		 3893#ifdef CONFIG_MTRR
3894 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3895 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3896 if (mgp->mtrr >= 0)
3897 mgp->wc_enabled = 1;
0da34b6d 3898#endif
c7f80993 3899 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3900 if (mgp->sram == NULL) {
3901 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3902 mgp->board_span, mgp->iomem_base);
3903 status = -ENXIO;
c7f80993 3904 goto abort_with_mtrr;
0da34b6d 3905 }
00b5e505
BG		 3906 hdr_offset =
3907 ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3908 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3909 mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3910 if (mgp->sram_size > mgp->board_span ||
3911 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3912 dev_err(&pdev->dev,
3913 "invalid sram_size %dB or board span %ldB\n",
3914 mgp->sram_size, mgp->board_span);
3915 goto abort_with_ioremap;
3916 }
0da34b6d 3917 memcpy_fromio(mgp->eeprom_strings,
00b5e505 3918 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 3919 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3920 status = myri10ge_read_mac_addr(mgp);
3921 if (status)
3922 goto abort_with_ioremap;
3923
3924 for (i = 0; i < ETH_ALEN; i++)
3925 netdev->dev_addr[i] = mgp->mac_addr[i];
3926
5443e9ea
BG		 3927 myri10ge_select_firmware(mgp);
3928
0dcffac1 3929 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3930 if (status != 0) {
3931 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3932 goto abort_with_ioremap;
3933 }
3934 myri10ge_probe_slices(mgp);
3935 status = myri10ge_alloc_slices(mgp);
3936 if (status != 0) {
3937 dev_err(&pdev->dev, "failed to alloc slice state\n");
3938 goto abort_with_firmware;
0da34b6d 3939 }
236bb5e6 3940 netdev->real_num_tx_queues = mgp->num_slices;
0da34b6d
BG		 3941 status = myri10ge_reset(mgp);
3942 if (status != 0) {
3943 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3944 goto abort_with_slices;
0da34b6d 3945 }
5dd2d332 3946#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3947 myri10ge_setup_dca(mgp);
3948#endif
0da34b6d
BG		 3949 pci_set_drvdata(pdev, mgp);
3950 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3951 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3952 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3953 myri10ge_initial_mtu = 68;
8126089f
SH		 3954
3955 netdev->netdev_ops = &myri10ge_netdev_ops;
0da34b6d 3956 netdev->mtu = myri10ge_initial_mtu;
0da34b6d 3957 netdev->base_addr = mgp->iomem_base;
4f93fde0 3958 netdev->features = mgp->features;
236bb5e6 3959
0da34b6d
BG		 3960 if (dac_enabled)
3961 netdev->features |= NETIF_F_HIGHDMA;
2552c31b 3962 netdev->features |= NETIF_F_LRO;
0da34b6d 3963
dddc045e
BG		 3964 netdev->vlan_features |= mgp->features;
3965 if (mgp->fw_ver_tiny < 37)
3966 netdev->vlan_features &= ~NETIF_F_TSO6;
3967 if (mgp->fw_ver_tiny < 32)
3968 netdev->vlan_features &= ~NETIF_F_TSO;
3969
21d05db1
BG		 3970 /* make sure we can get an irq, and that MSI can be
3971 * setup (if available). Also ensure netdev->irq
3972 * is set to correct value if MSI is enabled */
3973 status = myri10ge_request_irq(mgp);
3974 if (status != 0)
3975 goto abort_with_firmware;
3976 netdev->irq = pdev->irq;
3977 myri10ge_free_irq(mgp);
3978
0da34b6d
BG		 3979 /* Save configuration space to be restored if the
3980 * nic resets due to a parity error */
83f6e152 3981 pci_save_state(pdev);
0da34b6d
BG		 3982
3983 /* Setup the watchdog timer */
3984 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3985 (unsigned long)mgp);
3986
59081825 3987 spin_lock_init(&mgp->stats_lock);
0da34b6d 3988 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3989 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3990 status = register_netdev(netdev);
3991 if (status != 0) {
3992 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3993 goto abort_with_state;
0da34b6d 3994 }
0dcffac1
BG		 3995 if (mgp->msix_enabled)
3996 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3997 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3998 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3999 else
4000 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
4001 mgp->msi_enabled ? "MSI" : "xPIC",
4002 netdev->irq, mgp->tx_boundary, mgp->fw_name,
4003 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d 4004
2d90b0aa 4005 board_number++;
0da34b6d
BG		 4006 return 0;
4007
7adda30c 4008abort_with_state:
83f6e152 4009 pci_restore_state(pdev);
0da34b6d 4010
0dcffac1
BG		 4011abort_with_slices:
4012 myri10ge_free_slices(mgp);
4013
0da34b6d
BG		 4014abort_with_firmware:
4015 myri10ge_dummy_rdma(mgp, 0);
4016
0da34b6d 4017abort_with_ioremap:
0f840011
BG		 4018 if (mgp->mac_addr_string != NULL)
4019 dev_err(&pdev->dev,
4020 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
4021 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 4022 iounmap(mgp->sram);
4023
c7f80993 4024abort_with_mtrr:
0da34b6d
BG		 4025#ifdef CONFIG_MTRR
4026 if (mgp->mtrr >= 0)
4027 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4028#endif
b10c0668
BG		 4029 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4030 mgp->cmd, mgp->cmd_bus);
0da34b6d 4031
e3fd5534
BG		 4032abort_with_enabled:
4033 pci_disable_device(pdev);
0da34b6d 4034
e3fd5534 4035abort_with_netdev:
0da34b6d
BG		 4036 free_netdev(netdev);
4037 return status;
4038}
4039
4040/*
4041 * myri10ge_remove
4042 *
4043 * Does what is necessary to shutdown one Myrinet device. Called
4044 * once for each Myrinet card by the kernel when a module is
4045 * unloaded.
4046 */
4047static void myri10ge_remove(struct pci_dev *pdev)
4048{
4049 struct myri10ge_priv *mgp;
4050 struct net_device *netdev;
0da34b6d
BG		 4051
4052 mgp = pci_get_drvdata(pdev);
4053 if (mgp == NULL)
4054 return;
4055
4056 flush_scheduled_work();
4057 netdev = mgp->dev;
4058 unregister_netdev(netdev);
0da34b6d 4059
5dd2d332 4060#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4061 myri10ge_teardown_dca(mgp);
4062#endif
0da34b6d
BG		 4063 myri10ge_dummy_rdma(mgp, 0);
4064
7adda30c 4065 /* avoid a memory leak */
83f6e152 4066 pci_restore_state(pdev);
7adda30c 4067
0da34b6d
BG		 4068 iounmap(mgp->sram);
4069
4070#ifdef CONFIG_MTRR
4071 if (mgp->mtrr >= 0)
4072 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4073#endif
0dcffac1
BG		 4074 myri10ge_free_slices(mgp);
4075 if (mgp->msix_vectors != NULL)
4076 kfree(mgp->msix_vectors);
b10c0668
BG		 4077 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4078 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 4079
4080 free_netdev(netdev);
e3fd5534 4081 pci_disable_device(pdev);
0da34b6d
BG		 4082 pci_set_drvdata(pdev, NULL);
4083}
4084
b10c0668 4085#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 4086#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 4087
4088static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 4089 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 4090 {PCI_DEVICE
4091 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 4092 {0},
4093};
4094
97131079
BG		 4095MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4096
0da34b6d
BG		 4097static struct pci_driver myri10ge_driver = {
4098 .name = "myri10ge",
4099 .probe = myri10ge_probe,
4100 .remove = myri10ge_remove,
4101 .id_table = myri10ge_pci_tbl,
4102#ifdef CONFIG_PM
4103 .suspend = myri10ge_suspend,
4104 .resume = myri10ge_resume,
4105#endif
4106};
4107
5dd2d332 4108#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4109static int
4110myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4111{
4112 int err = driver_for_each_device(&myri10ge_driver.driver,
4113 NULL, &event,
4114 myri10ge_notify_dca_device);
4115
4116 if (err)
4117 return NOTIFY_BAD;
4118 return NOTIFY_DONE;
4119}
4120
4121static struct notifier_block myri10ge_dca_notifier = {
4122 .notifier_call = myri10ge_notify_dca,
4123 .next = NULL,
4124 .priority = 0,
4125};
4ee2ac51 4126#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4127
0da34b6d
BG		 4128static __init int myri10ge_init_module(void)
4129{
4130 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
4131 MYRI10GE_VERSION_STR);
0dcffac1 4132
236bb5e6 4133 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
0dcffac1
BG		 4134 printk(KERN_ERR
4135 "%s: Illegal rssh hash type %d, defaulting to source port\n",
4136 myri10ge_driver.name, myri10ge_rss_hash);
4137 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4138 }
5dd2d332 4139#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4140 dca_register_notify(&myri10ge_dca_notifier);
4141#endif
236bb5e6
BG		 4142 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4143 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4144
0da34b6d
BG		 4145 return pci_register_driver(&myri10ge_driver);
4146}
4147
4148module_init(myri10ge_init_module);
4149
4150static __exit void myri10ge_cleanup_module(void)
4151{
5dd2d332 4152#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4153 dca_unregister_notify(&myri10ge_dca_notifier);
4154#endif
0da34b6d
BG		 4155 pci_unregister_driver(&myri10ge_driver);
4156}
4157
4158module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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