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myri10ge: fix the invokation of lro_flush_all
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
e3fd5534 4 * Copyright (C) 2005 - 2009 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
981813d8 52#include <linux/dca.h>
0da34b6d
BG		 53#include <linux/ip.h>
54#include <linux/inet.h>
55#include <linux/in.h>
56#include <linux/ethtool.h>
57#include <linux/firmware.h>
58#include <linux/delay.h>
0da34b6d
BG		 59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
e5488ce5 78#define MYRI10GE_VERSION_STR "1.5.0-1.415"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
236bb5e6
BG		 105#define MYRI10GE_MAX_SLICES 32
106
0da34b6d 107struct myri10ge_rx_buffer_state {
dd50f336
BG		 108 struct page *page;
109 int page_offset;
0da34b6d
BG		 110 DECLARE_PCI_UNMAP_ADDR(bus)
111 DECLARE_PCI_UNMAP_LEN(len)
112};
113
114struct myri10ge_tx_buffer_state {
115 struct sk_buff *skb;
116 int last;
117 DECLARE_PCI_UNMAP_ADDR(bus)
118 DECLARE_PCI_UNMAP_LEN(len)
119};
120
121struct myri10ge_cmd {
122 u32 data0;
123 u32 data1;
124 u32 data2;
125};
126
127struct myri10ge_rx_buf {
128 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 129 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
130 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 131 struct page *page;
132 dma_addr_t bus;
133 int page_offset;
0da34b6d 134 int cnt;
dd50f336 135 int fill_cnt;
0da34b6d
BG		 136 int alloc_fail;
137 int mask; /* number of rx slots -1 */
dd50f336 138 int watchdog_needed;
0da34b6d
BG		 139};
140
141struct myri10ge_tx_buf {
142 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 143 __be32 __iomem *send_go; /* "go" doorbell ptr */
144 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 145 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
146 char *req_bytes;
147 struct myri10ge_tx_buffer_state *info;
148 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 149 int req ____cacheline_aligned; /* transmit slots submitted */
150 int pkt_start; /* packets started */
b53bef84
BG		 151 int stop_queue;
152 int linearized;
0da34b6d
BG		 153 int done ____cacheline_aligned; /* transmit slots completed */
154 int pkt_done; /* packets completed */
b53bef84 155 int wake_queue;
236bb5e6 156 int queue_active;
0da34b6d
BG		 157};
158
159struct myri10ge_rx_done {
160 struct mcp_slot *entry;
161 dma_addr_t bus;
162 int cnt;
163 int idx;
1e6e9342
AG		 164 struct net_lro_mgr lro_mgr;
165 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 166};
167
b53bef84
BG		 168struct myri10ge_slice_netstats {
169 unsigned long rx_packets;
170 unsigned long tx_packets;
171 unsigned long rx_bytes;
172 unsigned long tx_bytes;
173 unsigned long rx_dropped;
174 unsigned long tx_dropped;
175};
176
177struct myri10ge_slice_state {
0da34b6d
BG		 178 struct myri10ge_tx_buf tx; /* transmit ring */
179 struct myri10ge_rx_buf rx_small;
180 struct myri10ge_rx_buf rx_big;
181 struct myri10ge_rx_done rx_done;
b53bef84
BG		 182 struct net_device *dev;
183 struct napi_struct napi;
184 struct myri10ge_priv *mgp;
185 struct myri10ge_slice_netstats stats;
186 __be32 __iomem *irq_claim;
187 struct mcp_irq_data *fw_stats;
188 dma_addr_t fw_stats_bus;
189 int watchdog_tx_done;
190 int watchdog_tx_req;
5dd2d332 191#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 192 int cached_dca_tag;
193 int cpu;
194 __be32 __iomem *dca_tag;
195#endif
0dcffac1 196 char irq_desc[32];
b53bef84
BG		 197};
198
199struct myri10ge_priv {
0dcffac1 200 struct myri10ge_slice_state *ss;
b53bef84 201 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 202 int num_slices;
b53bef84
BG		 203 int running; /* running? */
204 int csum_flag; /* rx_csums? */
0da34b6d 205 int small_bytes;
dd50f336 206 int big_bytes;
fa0a90d9 207 int max_intr_slots;
0da34b6d
BG		 208 struct net_device *dev;
209 struct net_device_stats stats;
b53bef84 210 spinlock_t stats_lock;
0da34b6d
BG		 211 u8 __iomem *sram;
212 int sram_size;
213 unsigned long board_span;
214 unsigned long iomem_base;
40f6cff5 215 __be32 __iomem *irq_deassert;
0da34b6d
BG		 216 char *mac_addr_string;
217 struct mcp_cmd_response *cmd;
218 dma_addr_t cmd_bus;
0da34b6d
BG		 219 struct pci_dev *pdev;
220 int msi_enabled;
0dcffac1
BG		 221 int msix_enabled;
222 struct msix_entry *msix_vectors;
5dd2d332 223#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 224 int dca_enabled;
225#endif
66341fff 226 u32 link_state;
0da34b6d
BG		 227 unsigned int rdma_tags_available;
228 int intr_coal_delay;
40f6cff5 229 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 230 int mtrr;
276e26c3 231 int wc_enabled;
0da34b6d
BG		 232 int down_cnt;
233 wait_queue_head_t down_wq;
234 struct work_struct watchdog_work;
235 struct timer_list watchdog_timer;
0da34b6d 236 int watchdog_resets;
b53bef84 237 int watchdog_pause;
0da34b6d
BG		 238 int pause;
239 char *fw_name;
240 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 241 char *product_code_string;
0da34b6d 242 char fw_version[128];
9dc6f0e7
BG		 243 int fw_ver_major;
244 int fw_ver_minor;
245 int fw_ver_tiny;
246 int adopted_rx_filter_bug;
0da34b6d
BG		 247 u8 mac_addr[6]; /* eeprom mac address */
248 unsigned long serial_number;
249 int vendor_specific_offset;
85a7ea1b 250 int fw_multicast_support;
4f93fde0
BG		 251 unsigned long features;
252 u32 max_tso6;
0da34b6d
BG		 253 u32 read_dma;
254 u32 write_dma;
255 u32 read_write_dma;
c58ac5ca
BG		 256 u32 link_changes;
257 u32 msg_enable;
2d90b0aa 258 unsigned int board_number;
0da34b6d
BG		 259};
260
261static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
262static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 263static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
264static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
0da34b6d
BG		 265
266static char *myri10ge_fw_name = NULL;
267module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
d1ce3a0f 268MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 269
2d90b0aa
BG		 270#define MYRI10GE_MAX_BOARDS 8
271static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 272 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 273module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
274 0444);
275MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
276
0da34b6d
BG		 277static int myri10ge_ecrc_enable = 1;
278module_param(myri10ge_ecrc_enable, int, S_IRUGO);
d1ce3a0f 279MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 280
0da34b6d
BG		 281static int myri10ge_small_bytes = -1; /* -1 == auto */
282module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
d1ce3a0f 283MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 284
285static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 286module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
d1ce3a0f 287MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 288
f761fae1 289static int myri10ge_intr_coal_delay = 75;
0da34b6d 290module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
d1ce3a0f 291MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 292
293static int myri10ge_flow_control = 1;
294module_param(myri10ge_flow_control, int, S_IRUGO);
d1ce3a0f 295MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 296
297static int myri10ge_deassert_wait = 1;
298module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
299MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 300 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 301
302static int myri10ge_force_firmware = 0;
303module_param(myri10ge_force_firmware, int, S_IRUGO);
304MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 305 "Force firmware to assume aligned completions");
0da34b6d 306
0da34b6d
BG		 307static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
308module_param(myri10ge_initial_mtu, int, S_IRUGO);
d1ce3a0f 309MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 310
311static int myri10ge_napi_weight = 64;
312module_param(myri10ge_napi_weight, int, S_IRUGO);
d1ce3a0f 313MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 314
315static int myri10ge_watchdog_timeout = 1;
316module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
d1ce3a0f 317MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 318
319static int myri10ge_max_irq_loops = 1048576;
320module_param(myri10ge_max_irq_loops, int, S_IRUGO);
321MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 322 "Set stuck legacy IRQ detection threshold");
0da34b6d 323
c58ac5ca
BG		 324#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
325
326static int myri10ge_debug = -1; /* defaults above */
327module_param(myri10ge_debug, int, 0);
328MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
329
1e6e9342
AG		 330static int myri10ge_lro = 1;
331module_param(myri10ge_lro, int, S_IRUGO);
d1ce3a0f 332MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
1e6e9342
AG		 333
334static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
335module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
d1ce3a0f
BG		 336MODULE_PARM_DESC(myri10ge_lro_max_pkts,
337 "Number of LRO packets to be aggregated");
1e6e9342 338
dd50f336
BG		 339static int myri10ge_fill_thresh = 256;
340module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
d1ce3a0f 341MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 342
f181137f
BG		 343static int myri10ge_reset_recover = 1;
344
0dcffac1
BG		 345static int myri10ge_max_slices = 1;
346module_param(myri10ge_max_slices, int, S_IRUGO);
347MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
348
349static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
350module_param(myri10ge_rss_hash, int, S_IRUGO);
351MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
352
981813d8
BG		 353static int myri10ge_dca = 1;
354module_param(myri10ge_dca, int, S_IRUGO);
355MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
356
0da34b6d
BG		 357#define MYRI10GE_FW_OFFSET 1024*1024
358#define MYRI10GE_HIGHPART_TO_U32(X) \
359(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
360#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
361
362#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
363
2f76216f 364static void myri10ge_set_multicast_list(struct net_device *dev);
4f93fde0 365static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
2f76216f 366
6250223e 367static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 368{
6250223e 369 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 370}
371
59081825
BG		 372static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
373
0da34b6d
BG		 374static int
375myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
376 struct myri10ge_cmd *data, int atomic)
377{
378 struct mcp_cmd *buf;
379 char buf_bytes[sizeof(*buf) + 8];
380 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 381 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 382 u32 dma_low, dma_high, result, value;
383 int sleep_total = 0;
384
385 /* ensure buf is aligned to 8 bytes */
386 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
387
388 buf->data0 = htonl(data->data0);
389 buf->data1 = htonl(data->data1);
390 buf->data2 = htonl(data->data2);
391 buf->cmd = htonl(cmd);
392 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
393 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
394
395 buf->response_addr.low = htonl(dma_low);
396 buf->response_addr.high = htonl(dma_high);
40f6cff5 397 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 398 mb();
399 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
400
401 /* wait up to 15ms. Longest command is the DMA benchmark,
402 * which is capped at 5ms, but runs from a timeout handler
403 * that runs every 7.8ms. So a 15ms timeout leaves us with
404 * a 2.2ms margin
405 */
406 if (atomic) {
407 /* if atomic is set, do not sleep,
408 * and try to get the completion quickly
409 * (1ms will be enough for those commands) */
410 for (sleep_total = 0;
411 sleep_total < 1000
40f6cff5 412 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 413 sleep_total += 10) {
0da34b6d 414 udelay(10);
bd2db0cf
BG		 415 mb();
416 }
0da34b6d
BG		 417 } else {
418 /* use msleep for most command */
419 for (sleep_total = 0;
420 sleep_total < 15
40f6cff5 421 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 422 sleep_total++)
423 msleep(1);
424 }
425
426 result = ntohl(response->result);
427 value = ntohl(response->data);
428 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
429 if (result == 0) {
430 data->data0 = value;
431 return 0;
85a7ea1b
BG		 432 } else if (result == MXGEFW_CMD_UNKNOWN) {
433 return -ENOSYS;
5443e9ea
BG		 434 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
435 return -E2BIG;
236bb5e6
BG		 436 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
437 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
438 (data->
439 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
440 0) {
441 return -ERANGE;
0da34b6d
BG		 442 } else {
443 dev_err(&mgp->pdev->dev,
444 "command %d failed, result = %d\n",
445 cmd, result);
446 return -ENXIO;
447 }
448 }
449
450 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
451 cmd, result);
452 return -EAGAIN;
453}
454
455/*
456 * The eeprom strings on the lanaiX have the format
457 * SN=x\0
458 * MAC=x:x:x:x:x:x\0
459 * PT:ddd mmm xx xx:xx:xx xx\0
460 * PV:ddd mmm xx xx:xx:xx xx\0
461 */
462static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
463{
464 char *ptr, *limit;
465 int i;
466
467 ptr = mgp->eeprom_strings;
468 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
469
470 while (*ptr != '\0' && ptr < limit) {
471 if (memcmp(ptr, "MAC=", 4) == 0) {
472 ptr += 4;
473 mgp->mac_addr_string = ptr;
474 for (i = 0; i < 6; i++) {
475 if ((ptr + 2) > limit)
476 goto abort;
477 mgp->mac_addr[i] =
478 simple_strtoul(ptr, &ptr, 16);
479 ptr += 1;
480 }
481 }
c0bf8801
BG		 482 if (memcmp(ptr, "PC=", 3) == 0) {
483 ptr += 3;
484 mgp->product_code_string = ptr;
485 }
0da34b6d
BG		 486 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
487 ptr += 3;
488 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
489 }
490 while (ptr < limit && *ptr++) ;
491 }
492
493 return 0;
494
495abort:
496 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
497 return -ENXIO;
498}
499
500/*
501 * Enable or disable periodic RDMAs from the host to make certain
502 * chipsets resend dropped PCIe messages
503 */
504
505static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
506{
507 char __iomem *submit;
f8fd57c1 508 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 509 u32 dma_low, dma_high;
510 int i;
511
512 /* clear confirmation addr */
513 mgp->cmd->data = 0;
514 mb();
515
516 /* send a rdma command to the PCIe engine, and wait for the
517 * response in the confirmation address. The firmware should
518 * write a -1 there to indicate it is alive and well
519 */
520 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
521 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
522
523 buf[0] = htonl(dma_high); /* confirm addr MSW */
524 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 525 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 526 buf[3] = htonl(dma_high); /* dummy addr MSW */
527 buf[4] = htonl(dma_low); /* dummy addr LSW */
528 buf[5] = htonl(enable); /* enable? */
529
e700f9f4 530 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 531
532 myri10ge_pio_copy(submit, &buf, sizeof(buf));
533 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
534 msleep(1);
535 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
536 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
537 (enable ? "enable" : "disable"));
538}
539
540static int
541myri10ge_validate_firmware(struct myri10ge_priv *mgp,
542 struct mcp_gen_header *hdr)
543{
544 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 545
546 /* check firmware type */
547 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
548 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
549 return -EINVAL;
550 }
551
552 /* save firmware version for ethtool */
553 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
554
9dc6f0e7
BG		 555 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
556 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 557
9dc6f0e7
BG		 558 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
559 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 560 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
561 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
562 MXGEFW_VERSION_MINOR);
563 return -EINVAL;
564 }
565 return 0;
566}
567
568static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
569{
570 unsigned crc, reread_crc;
571 const struct firmware *fw;
572 struct device *dev = &mgp->pdev->dev;
b0d31d6b 573 unsigned char *fw_readback;
0da34b6d
BG		 574 struct mcp_gen_header *hdr;
575 size_t hdr_offset;
576 int status;
e454358a 577 unsigned i;
0da34b6d
BG		 578
579 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
580 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
581 mgp->fw_name);
582 status = -EINVAL;
583 goto abort_with_nothing;
584 }
585
586 /* check size */
587
588 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
589 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
590 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
591 status = -EINVAL;
592 goto abort_with_fw;
593 }
594
595 /* check id */
40f6cff5 596 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 597 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
598 dev_err(dev, "Bad firmware file\n");
599 status = -EINVAL;
600 goto abort_with_fw;
601 }
602 hdr = (void *)(fw->data + hdr_offset);
603
604 status = myri10ge_validate_firmware(mgp, hdr);
605 if (status != 0)
606 goto abort_with_fw;
607
608 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 609 for (i = 0; i < fw->size; i += 256) {
610 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
611 fw->data + i,
612 min(256U, (unsigned)(fw->size - i)));
613 mb();
614 readb(mgp->sram);
b10c0668 615 }
b0d31d6b
DW		 616 fw_readback = vmalloc(fw->size);
617 if (!fw_readback) {
618 status = -ENOMEM;
619 goto abort_with_fw;
620 }
0da34b6d 621 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 622 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
623 reread_crc = crc32(~0, fw_readback, fw->size);
624 vfree(fw_readback);
0da34b6d
BG		 625 if (crc != reread_crc) {
626 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
627 (unsigned)fw->size, reread_crc, crc);
628 status = -EIO;
629 goto abort_with_fw;
630 }
631 *size = (u32) fw->size;
632
633abort_with_fw:
634 release_firmware(fw);
635
636abort_with_nothing:
637 return status;
638}
639
640static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
641{
642 struct mcp_gen_header *hdr;
643 struct device *dev = &mgp->pdev->dev;
644 const size_t bytes = sizeof(struct mcp_gen_header);
645 size_t hdr_offset;
646 int status;
647
648 /* find running firmware header */
66341fff 649 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 650
651 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
652 dev_err(dev, "Running firmware has bad header offset (%d)\n",
653 (int)hdr_offset);
654 return -EIO;
655 }
656
657 /* copy header of running firmware from SRAM to host memory to
658 * validate firmware */
659 hdr = kmalloc(bytes, GFP_KERNEL);
660 if (hdr == NULL) {
661 dev_err(dev, "could not malloc firmware hdr\n");
662 return -ENOMEM;
663 }
664 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
665 status = myri10ge_validate_firmware(mgp, hdr);
666 kfree(hdr);
9dc6f0e7
BG		 667
668 /* check to see if adopted firmware has bug where adopting
669 * it will cause broadcasts to be filtered unless the NIC
670 * is kept in ALLMULTI mode */
671 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
672 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
673 mgp->adopted_rx_filter_bug = 1;
674 dev_warn(dev, "Adopting fw %d.%d.%d: "
675 "working around rx filter bug\n",
676 mgp->fw_ver_major, mgp->fw_ver_minor,
677 mgp->fw_ver_tiny);
678 }
0da34b6d
BG		 679 return status;
680}
681
0178ec3d 682static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 683{
684 struct myri10ge_cmd cmd;
685 int status;
686
687 /* probe for IPv6 TSO support */
688 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
689 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
690 &cmd, 0);
691 if (status == 0) {
692 mgp->max_tso6 = cmd.data0;
693 mgp->features |= NETIF_F_TSO6;
694 }
695
696 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
697 if (status != 0) {
698 dev_err(&mgp->pdev->dev,
699 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
700 return -ENXIO;
701 }
702
703 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
704
705 return 0;
706}
707
0dcffac1 708static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 709{
710 char __iomem *submit;
f8fd57c1 711 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 712 u32 dma_low, dma_high, size;
713 int status, i;
714
b10c0668 715 size = 0;
0da34b6d
BG		 716 status = myri10ge_load_hotplug_firmware(mgp, &size);
717 if (status) {
0dcffac1
BG		 718 if (!adopt)
719 return status;
0da34b6d
BG		 720 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
721
722 /* Do not attempt to adopt firmware if there
723 * was a bad crc */
724 if (status == -EIO)
725 return status;
726
727 status = myri10ge_adopt_running_firmware(mgp);
728 if (status != 0) {
729 dev_err(&mgp->pdev->dev,
730 "failed to adopt running firmware\n");
731 return status;
732 }
733 dev_info(&mgp->pdev->dev,
734 "Successfully adopted running firmware\n");
b53bef84 735 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 736 dev_warn(&mgp->pdev->dev,
737 "Using firmware currently running on NIC"
738 ". For optimal\n");
739 dev_warn(&mgp->pdev->dev,
740 "performance consider loading optimized "
741 "firmware\n");
742 dev_warn(&mgp->pdev->dev, "via hotplug\n");
743 }
744
745 mgp->fw_name = "adopted";
b53bef84 746 mgp->tx_boundary = 2048;
fa0a90d9
BG		 747 myri10ge_dummy_rdma(mgp, 1);
748 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 749 return status;
750 }
751
752 /* clear confirmation addr */
753 mgp->cmd->data = 0;
754 mb();
755
756 /* send a reload command to the bootstrap MCP, and wait for the
757 * response in the confirmation address. The firmware should
758 * write a -1 there to indicate it is alive and well
759 */
760 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
761 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
762
763 buf[0] = htonl(dma_high); /* confirm addr MSW */
764 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 765 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 766
767 /* FIX: All newest firmware should un-protect the bottom of
768 * the sram before handoff. However, the very first interfaces
769 * do not. Therefore the handoff copy must skip the first 8 bytes
770 */
771 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
772 buf[4] = htonl(size - 8); /* length of code */
773 buf[5] = htonl(8); /* where to copy to */
774 buf[6] = htonl(0); /* where to jump to */
775
e700f9f4 776 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 777
778 myri10ge_pio_copy(submit, &buf, sizeof(buf));
779 mb();
780 msleep(1);
781 mb();
782 i = 0;
d93ca2a4
BG		 783 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
784 msleep(1 << i);
0da34b6d
BG		 785 i++;
786 }
787 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
788 dev_err(&mgp->pdev->dev, "handoff failed\n");
789 return -ENXIO;
790 }
9a71db72 791 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 792 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 793
fa0a90d9 794 return status;
0da34b6d
BG		 795}
796
797static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
798{
799 struct myri10ge_cmd cmd;
800 int status;
801
802 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
803 | (addr[2] << 8) | addr[3]);
804
805 cmd.data1 = ((addr[4] << 8) | (addr[5]));
806
807 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
808 return status;
809}
810
811static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
812{
813 struct myri10ge_cmd cmd;
814 int status, ctl;
815
816 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
817 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
818
819 if (status) {
820 printk(KERN_ERR
821 "myri10ge: %s: Failed to set flow control mode\n",
822 mgp->dev->name);
823 return status;
824 }
825 mgp->pause = pause;
826 return 0;
827}
828
829static void
830myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
831{
832 struct myri10ge_cmd cmd;
833 int status, ctl;
834
835 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
836 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
837 if (status)
838 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
839 mgp->dev->name);
840}
841
0d6ac257 842static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 843{
844 struct myri10ge_cmd cmd;
845 int status;
0da34b6d 846 u32 len;
34fdccea
BG		 847 struct page *dmatest_page;
848 dma_addr_t dmatest_bus;
0d6ac257
BG		 849 char *test = " ";
850
851 dmatest_page = alloc_page(GFP_KERNEL);
852 if (!dmatest_page)
853 return -ENOMEM;
854 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
855 DMA_BIDIRECTIONAL);
856
857 /* Run a small DMA test.
858 * The magic multipliers to the length tell the firmware
859 * to do DMA read, write, or read+write tests. The
860 * results are returned in cmd.data0. The upper 16
861 * bits or the return is the number of transfers completed.
862 * The lower 16 bits is the time in 0.5us ticks that the
863 * transfers took to complete.
864 */
865
b53bef84 866 len = mgp->tx_boundary;
0d6ac257
BG		 867
868 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
869 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
870 cmd.data2 = len * 0x10000;
871 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
872 if (status != 0) {
873 test = "read";
874 goto abort;
875 }
876 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
877 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
878 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
879 cmd.data2 = len * 0x1;
880 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
881 if (status != 0) {
882 test = "write";
883 goto abort;
884 }
885 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
886
887 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
888 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
889 cmd.data2 = len * 0x10001;
890 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
891 if (status != 0) {
892 test = "read/write";
893 goto abort;
894 }
895 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
896 (cmd.data0 & 0xffff);
897
898abort:
899 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
900 put_page(dmatest_page);
901
902 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
903 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
904 test, status);
905
906 return status;
907}
908
909static int myri10ge_reset(struct myri10ge_priv *mgp)
910{
911 struct myri10ge_cmd cmd;
0dcffac1
BG		 912 struct myri10ge_slice_state *ss;
913 int i, status;
0d6ac257 914 size_t bytes;
5dd2d332 915#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 916 unsigned long dca_tag_off;
917#endif
0da34b6d
BG		 918
919 /* try to send a reset command to the card to see if it
920 * is alive */
921 memset(&cmd, 0, sizeof(cmd));
922 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
923 if (status != 0) {
924 dev_err(&mgp->pdev->dev, "failed reset\n");
925 return -ENXIO;
926 }
0d6ac257
BG		 927
928 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 929 /*
930 * Use non-ndis mcp_slot (eg, 4 bytes total,
931 * no toeplitz hash value returned. Older firmware will
932 * not understand this command, but will use the correct
933 * sized mcp_slot, so we ignore error returns
934 */
935 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
936 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 937
938 /* Now exchange information about interrupts */
939
0dcffac1 940 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 941 cmd.data0 = (u32) bytes;
942 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 943
944 /*
945 * Even though we already know how many slices are supported
946 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
947 * has magic side effects, and must be called after a reset.
948 * It must be called prior to calling any RSS related cmds,
949 * including assigning an interrupt queue for anything but
950 * slice 0. It must also be called *after*
951 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
952 * the firmware to compute offsets.
953 */
954
955 if (mgp->num_slices > 1) {
956
957 /* ask the maximum number of slices it supports */
958 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
959 &cmd, 0);
960 if (status != 0) {
961 dev_err(&mgp->pdev->dev,
962 "failed to get number of slices\n");
963 }
964
965 /*
966 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
967 * to setting up the interrupt queue DMA
968 */
969
970 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 971 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
972 if (mgp->dev->real_num_tx_queues > 1)
973 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 974 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
975 &cmd, 0);
236bb5e6
BG		 976
977 /* Firmware older than 1.4.32 only supports multiple
978 * RX queues, so if we get an error, first retry using a
979 * single TX queue before giving up */
980 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
981 mgp->dev->real_num_tx_queues = 1;
982 cmd.data0 = mgp->num_slices;
983 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
984 status = myri10ge_send_cmd(mgp,
985 MXGEFW_CMD_ENABLE_RSS_QUEUES,
986 &cmd, 0);
987 }
988
0dcffac1
BG		 989 if (status != 0) {
990 dev_err(&mgp->pdev->dev,
991 "failed to set number of slices\n");
992
993 return status;
994 }
995 }
996 for (i = 0; i < mgp->num_slices; i++) {
997 ss = &mgp->ss[i];
998 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
999 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1000 cmd.data2 = i;
1001 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1002 &cmd, 0);
1003 };
0da34b6d
BG		 1004
1005 status |=
1006 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1007 for (i = 0; i < mgp->num_slices; i++) {
1008 ss = &mgp->ss[i];
1009 ss->irq_claim =
1010 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1011 }
df30a740
BG		 1012 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1013 &cmd, 0);
1014 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1015
0da34b6d
BG		 1016 status |= myri10ge_send_cmd
1017 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1018 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1019 if (status != 0) {
1020 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1021 return status;
1022 }
40f6cff5 1023 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1024
5dd2d332 1025#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1026 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1027 dca_tag_off = cmd.data0;
1028 for (i = 0; i < mgp->num_slices; i++) {
1029 ss = &mgp->ss[i];
1030 if (status == 0) {
1031 ss->dca_tag = (__iomem __be32 *)
1032 (mgp->sram + dca_tag_off + 4 * i);
1033 } else {
1034 ss->dca_tag = NULL;
1035 }
1036 }
4ee2ac51 1037#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1038
0da34b6d 1039 /* reset mcp/driver shared state back to 0 */
0dcffac1 1040
c58ac5ca 1041 mgp->link_changes = 0;
0dcffac1
BG		 1042 for (i = 0; i < mgp->num_slices; i++) {
1043 ss = &mgp->ss[i];
1044
1045 memset(ss->rx_done.entry, 0, bytes);
1046 ss->tx.req = 0;
1047 ss->tx.done = 0;
1048 ss->tx.pkt_start = 0;
1049 ss->tx.pkt_done = 0;
1050 ss->rx_big.cnt = 0;
1051 ss->rx_small.cnt = 0;
1052 ss->rx_done.idx = 0;
1053 ss->rx_done.cnt = 0;
1054 ss->tx.wake_queue = 0;
1055 ss->tx.stop_queue = 0;
1056 }
1057
0da34b6d 1058 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1059 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1060 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1061 return status;
1062}
1063
5dd2d332 1064#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1065static void
1066myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1067{
1068 ss->cpu = cpu;
1069 ss->cached_dca_tag = tag;
1070 put_be32(htonl(tag), ss->dca_tag);
1071}
1072
1073static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1074{
1075 int cpu = get_cpu();
1076 int tag;
1077
1078 if (cpu != ss->cpu) {
1079 tag = dca_get_tag(cpu);
1080 if (ss->cached_dca_tag != tag)
1081 myri10ge_write_dca(ss, cpu, tag);
1082 }
1083 put_cpu();
1084}
1085
1086static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1087{
1088 int err, i;
1089 struct pci_dev *pdev = mgp->pdev;
1090
1091 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1092 return;
1093 if (!myri10ge_dca) {
1094 dev_err(&pdev->dev, "dca disabled by administrator\n");
1095 return;
1096 }
1097 err = dca_add_requester(&pdev->dev);
1098 if (err) {
330554cb
BG		 1099 if (err != -ENODEV)
1100 dev_err(&pdev->dev,
1101 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1102 return;
1103 }
1104 mgp->dca_enabled = 1;
1105 for (i = 0; i < mgp->num_slices; i++)
1106 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1107}
1108
1109static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1110{
1111 struct pci_dev *pdev = mgp->pdev;
1112 int err;
1113
1114 if (!mgp->dca_enabled)
1115 return;
1116 mgp->dca_enabled = 0;
1117 err = dca_remove_requester(&pdev->dev);
1118}
1119
1120static int myri10ge_notify_dca_device(struct device *dev, void *data)
1121{
1122 struct myri10ge_priv *mgp;
1123 unsigned long event;
1124
1125 mgp = dev_get_drvdata(dev);
1126 event = *(unsigned long *)data;
1127
1128 if (event == DCA_PROVIDER_ADD)
1129 myri10ge_setup_dca(mgp);
1130 else if (event == DCA_PROVIDER_REMOVE)
1131 myri10ge_teardown_dca(mgp);
1132 return 0;
1133}
4ee2ac51 1134#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1135
0da34b6d
BG		 1136static inline void
1137myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1138 struct mcp_kreq_ether_recv *src)
1139{
40f6cff5 1140 __be32 low;
0da34b6d
BG		 1141
1142 low = src->addr_low;
284901a9 1143 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1144 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1145 mb();
1146 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1147 mb();
1148 src->addr_low = low;
40f6cff5 1149 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1150 mb();
1151}
1152
40f6cff5 1153static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1154{
1155 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1156
40f6cff5 1157 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1158 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1159 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1160 skb->csum = hw_csum;
84fa7933 1161 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1162 }
1163}
1164
dd50f336
BG		 1165static inline void
1166myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1167 struct skb_frag_struct *rx_frags, int len, int hlen)
1168{
1169 struct skb_frag_struct *skb_frags;
1170
1171 skb->len = skb->data_len = len;
1172 skb->truesize = len + sizeof(struct sk_buff);
1173 /* attach the page(s) */
1174
1175 skb_frags = skb_shinfo(skb)->frags;
1176 while (len > 0) {
1177 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1178 len -= rx_frags->size;
1179 skb_frags++;
1180 rx_frags++;
1181 skb_shinfo(skb)->nr_frags++;
1182 }
1183
1184 /* pskb_may_pull is not available in irq context, but
1185 * skb_pull() (for ether_pad and eth_type_trans()) requires
1186 * the beginning of the packet in skb_headlen(), move it
1187 * manually */
27d7ff46 1188 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 1189 skb_shinfo(skb)->frags[0].page_offset += hlen;
1190 skb_shinfo(skb)->frags[0].size -= hlen;
1191 skb->data_len -= hlen;
1192 skb->tail += hlen;
1193 skb_pull(skb, MXGEFW_PAD);
1194}
1195
1196static void
1197myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1198 int bytes, int watchdog)
1199{
1200 struct page *page;
1201 int idx;
1202
1203 if (unlikely(rx->watchdog_needed && !watchdog))
1204 return;
1205
1206 /* try to refill entire ring */
1207 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1208 idx = rx->fill_cnt & rx->mask;
ae8509b1 1209 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1210 /* we can use part of previous page */
1211 get_page(rx->page);
1212 } else {
1213 /* we need a new page */
1214 page =
1215 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1216 MYRI10GE_ALLOC_ORDER);
1217 if (unlikely(page == NULL)) {
1218 if (rx->fill_cnt - rx->cnt < 16)
1219 rx->watchdog_needed = 1;
1220 return;
1221 }
1222 rx->page = page;
1223 rx->page_offset = 0;
1224 rx->bus = pci_map_page(mgp->pdev, page, 0,
1225 MYRI10GE_ALLOC_SIZE,
1226 PCI_DMA_FROMDEVICE);
1227 }
1228 rx->info[idx].page = rx->page;
1229 rx->info[idx].page_offset = rx->page_offset;
1230 /* note that this is the address of the start of the
1231 * page */
1232 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1233 rx->shadow[idx].addr_low =
1234 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1235 rx->shadow[idx].addr_high =
1236 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1237
1238 /* start next packet on a cacheline boundary */
1239 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1240
1241#if MYRI10GE_ALLOC_SIZE > 4096
1242 /* don't cross a 4KB boundary */
1243 if ((rx->page_offset >> 12) !=
1244 ((rx->page_offset + bytes - 1) >> 12))
1245 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1246#endif
dd50f336
BG		 1247 rx->fill_cnt++;
1248
1249 /* copy 8 descriptors to the firmware at a time */
1250 if ((idx & 7) == 7) {
e454e7e2
BG		 1251 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1252 &rx->shadow[idx - 7]);
dd50f336
BG		 1253 }
1254 }
1255}
1256
1257static inline void
1258myri10ge_unmap_rx_page(struct pci_dev *pdev,
1259 struct myri10ge_rx_buffer_state *info, int bytes)
1260{
1261 /* unmap the recvd page if we're the only or last user of it */
1262 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1263 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1264 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1265 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1266 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1267 }
1268}
1269
1270#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1271 * page into an skb */
1272
1273static inline int
b53bef84 1274myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
52ea6fb3 1275 int bytes, int len, __wsum csum)
dd50f336 1276{
b53bef84 1277 struct myri10ge_priv *mgp = ss->mgp;
dd50f336
BG		 1278 struct sk_buff *skb;
1279 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1280 int i, idx, hlen, remainder;
1281 struct pci_dev *pdev = mgp->pdev;
1282 struct net_device *dev = mgp->dev;
1283 u8 *va;
1284
1285 len += MXGEFW_PAD;
1286 idx = rx->cnt & rx->mask;
1287 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1288 prefetch(va);
1289 /* Fill skb_frag_struct(s) with data from our receive */
1290 for (i = 0, remainder = len; remainder > 0; i++) {
1291 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1292 rx_frags[i].page = rx->info[idx].page;
1293 rx_frags[i].page_offset = rx->info[idx].page_offset;
1294 if (remainder < MYRI10GE_ALLOC_SIZE)
1295 rx_frags[i].size = remainder;
1296 else
1297 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1298 rx->cnt++;
1299 idx = rx->cnt & rx->mask;
1300 remainder -= MYRI10GE_ALLOC_SIZE;
1301 }
1302
3a0c7d2d 1303 if (dev->features & NETIF_F_LRO) {
1e6e9342
AG		 1304 rx_frags[0].page_offset += MXGEFW_PAD;
1305 rx_frags[0].size -= MXGEFW_PAD;
1306 len -= MXGEFW_PAD;
b53bef84 1307 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
b53bef84 1308 /* opaque, will come back in get_frag_header */
0dcffac1 1309 len, len,
b53bef84 1310 (void *)(__force unsigned long)csum, csum);
0dcffac1 1311
1e6e9342
AG		 1312 return 1;
1313 }
1314
dd50f336
BG		 1315 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1316
e636b2ea
BG		 1317 /* allocate an skb to attach the page(s) to. This is done
1318 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1319
1320 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1321 if (unlikely(skb == NULL)) {
d6279c88 1322 ss->stats.rx_dropped++;
dd50f336
BG		 1323 do {
1324 i--;
1325 put_page(rx_frags[i].page);
1326 } while (i != 0);
1327 return 0;
1328 }
1329
1330 /* Attach the pages to the skb, and trim off any padding */
1331 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1332 if (skb_shinfo(skb)->frags[0].size <= 0) {
1333 put_page(skb_shinfo(skb)->frags[0].page);
1334 skb_shinfo(skb)->nr_frags = 0;
1335 }
1336 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 1337 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
dd50f336
BG		 1338
1339 if (mgp->csum_flag) {
1340 if ((skb->protocol == htons(ETH_P_IP)) ||
1341 (skb->protocol == htons(ETH_P_IPV6))) {
1342 skb->csum = csum;
1343 skb->ip_summed = CHECKSUM_COMPLETE;
1344 } else
1345 myri10ge_vlan_ip_csum(skb, csum);
1346 }
1347 netif_receive_skb(skb);
dd50f336
BG		 1348 return 1;
1349}
1350
b53bef84
BG		 1351static inline void
1352myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1353{
b53bef84
BG		 1354 struct pci_dev *pdev = ss->mgp->pdev;
1355 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1356 struct netdev_queue *dev_queue;
0da34b6d
BG		 1357 struct sk_buff *skb;
1358 int idx, len;
0da34b6d
BG		 1359
1360 while (tx->pkt_done != mcp_index) {
1361 idx = tx->done & tx->mask;
1362 skb = tx->info[idx].skb;
1363
1364 /* Mark as free */
1365 tx->info[idx].skb = NULL;
1366 if (tx->info[idx].last) {
1367 tx->pkt_done++;
1368 tx->info[idx].last = 0;
1369 }
1370 tx->done++;
1371 len = pci_unmap_len(&tx->info[idx], len);
1372 pci_unmap_len_set(&tx->info[idx], len, 0);
1373 if (skb) {
b53bef84
BG		 1374 ss->stats.tx_bytes += skb->len;
1375 ss->stats.tx_packets++;
0da34b6d
BG		 1376 dev_kfree_skb_irq(skb);
1377 if (len)
1378 pci_unmap_single(pdev,
1379 pci_unmap_addr(&tx->info[idx],
1380 bus), len,
1381 PCI_DMA_TODEVICE);
1382 } else {
1383 if (len)
1384 pci_unmap_page(pdev,
1385 pci_unmap_addr(&tx->info[idx],
1386 bus), len,
1387 PCI_DMA_TODEVICE);
1388 }
0da34b6d 1389 }
236bb5e6
BG		 1390
1391 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1392 /*
1393 * Make a minimal effort to prevent the NIC from polling an
1394 * idle tx queue. If we can't get the lock we leave the queue
1395 * active. In this case, either a thread was about to start
1396 * using the queue anyway, or we lost a race and the NIC will
1397 * waste some of its resources polling an inactive queue for a
1398 * while.
1399 */
1400
1401 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1402 __netif_tx_trylock(dev_queue)) {
1403 if (tx->req == tx->done) {
1404 tx->queue_active = 0;
1405 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1406 mb();
6824a105 1407 mmiowb();
236bb5e6
BG		 1408 }
1409 __netif_tx_unlock(dev_queue);
1410 }
1411
0da34b6d 1412 /* start the queue if we've stopped it */
236bb5e6 1413 if (netif_tx_queue_stopped(dev_queue)
0da34b6d 1414 && tx->req - tx->done < (tx->mask >> 1)) {
b53bef84 1415 tx->wake_queue++;
236bb5e6 1416 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1417 }
1418}
1419
b53bef84
BG		 1420static inline int
1421myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1422{
b53bef84
BG		 1423 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1424 struct myri10ge_priv *mgp = ss->mgp;
18af3e7c 1425 struct net_device *netdev = mgp->dev;
0da34b6d
BG		 1426 unsigned long rx_bytes = 0;
1427 unsigned long rx_packets = 0;
1428 unsigned long rx_ok;
1429
1430 int idx = rx_done->idx;
1431 int cnt = rx_done->cnt;
bea3348e 1432 int work_done = 0;
0da34b6d 1433 u16 length;
40f6cff5 1434 __wsum checksum;
0da34b6d 1435
c956a240 1436 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1437 length = ntohs(rx_done->entry[idx].length);
1438 rx_done->entry[idx].length = 0;
40f6cff5 1439 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1440 if (length <= mgp->small_bytes)
b53bef84 1441 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
52ea6fb3
BG		 1442 mgp->small_bytes,
1443 length, checksum);
0da34b6d 1444 else
b53bef84 1445 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
52ea6fb3
BG		 1446 mgp->big_bytes,
1447 length, checksum);
0da34b6d
BG		 1448 rx_packets += rx_ok;
1449 rx_bytes += rx_ok * (unsigned long)length;
1450 cnt++;
014377a1 1451 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1452 work_done++;
0da34b6d
BG		 1453 }
1454 rx_done->idx = idx;
1455 rx_done->cnt = cnt;
b53bef84
BG		 1456 ss->stats.rx_packets += rx_packets;
1457 ss->stats.rx_bytes += rx_bytes;
c7dab99b 1458
18af3e7c 1459 if (netdev->features & NETIF_F_LRO)
1e6e9342
AG		 1460 lro_flush_all(&rx_done->lro_mgr);
1461
c7dab99b 1462 /* restock receive rings if needed */
b53bef84
BG		 1463 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1464 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1465 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1466 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1467 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1468
bea3348e 1469 return work_done;
0da34b6d
BG		 1470}
1471
1472static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1473{
0dcffac1 1474 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1475
1476 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1477 unsigned link_up = ntohl(stats->link_up);
1478 if (mgp->link_state != link_up) {
1479 mgp->link_state = link_up;
1480
1481 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1482 if (netif_msg_link(mgp))
1483 printk(KERN_INFO
1484 "myri10ge: %s: link up\n",
1485 mgp->dev->name);
0da34b6d 1486 netif_carrier_on(mgp->dev);
c58ac5ca 1487 mgp->link_changes++;
0da34b6d 1488 } else {
c58ac5ca
BG		 1489 if (netif_msg_link(mgp))
1490 printk(KERN_INFO
798a95db
BG		 1491 "myri10ge: %s: link %s\n",
1492 mgp->dev->name,
1493 (link_up == MXGEFW_LINK_MYRINET ?
1494 "mismatch (Myrinet detected)" :
1495 "down"));
0da34b6d 1496 netif_carrier_off(mgp->dev);
c58ac5ca 1497 mgp->link_changes++;
0da34b6d
BG		 1498 }
1499 }
1500 if (mgp->rdma_tags_available !=
b53bef84 1501 ntohl(stats->rdma_tags_available)) {
0da34b6d 1502 mgp->rdma_tags_available =
b53bef84 1503 ntohl(stats->rdma_tags_available);
0da34b6d
BG		 1504 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1505 "%d tags left\n", mgp->dev->name,
1506 mgp->rdma_tags_available);
1507 }
1508 mgp->down_cnt += stats->link_down;
1509 if (stats->link_down)
1510 wake_up(&mgp->down_wq);
1511 }
1512}
1513
bea3348e 1514static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1515{
b53bef84
BG		 1516 struct myri10ge_slice_state *ss =
1517 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1518 int work_done;
0da34b6d 1519
5dd2d332 1520#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1521 if (ss->mgp->dca_enabled)
1522 myri10ge_update_dca(ss);
1523#endif
1524
0da34b6d 1525 /* process as many rx events as NAPI will allow */
b53bef84 1526 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1527
4ec24119 1528 if (work_done < budget) {
288379f0 1529 napi_complete(napi);
b53bef84 1530 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1531 }
bea3348e 1532 return work_done;
0da34b6d
BG		 1533}
1534
7d12e780 1535static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1536{
b53bef84
BG		 1537 struct myri10ge_slice_state *ss = arg;
1538 struct myri10ge_priv *mgp = ss->mgp;
1539 struct mcp_irq_data *stats = ss->fw_stats;
1540 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1541 u32 send_done_count;
1542 int i;
1543
236bb5e6
BG		 1544 /* an interrupt on a non-zero receive-only slice is implicitly
1545 * valid since MSI-X irqs are not shared */
1546 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1547 napi_schedule(&ss->napi);
0dcffac1
BG		 1548 return (IRQ_HANDLED);
1549 }
1550
0da34b6d
BG		 1551 /* make sure it is our IRQ, and that the DMA has finished */
1552 if (unlikely(!stats->valid))
1553 return (IRQ_NONE);
1554
1555 /* low bit indicates receives are present, so schedule
1556 * napi poll handler */
1557 if (stats->valid & 1)
288379f0 1558 napi_schedule(&ss->napi);
0da34b6d 1559
0dcffac1 1560 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1561 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1562 if (!myri10ge_deassert_wait)
1563 stats->valid = 0;
1564 mb();
1565 } else
1566 stats->valid = 0;
1567
1568 /* Wait for IRQ line to go low, if using INTx */
1569 i = 0;
1570 while (1) {
1571 i++;
1572 /* check for transmit completes and receives */
1573 send_done_count = ntohl(stats->send_done_count);
1574 if (send_done_count != tx->pkt_done)
b53bef84 1575 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d
BG		 1576 if (unlikely(i > myri10ge_max_irq_loops)) {
1577 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1578 mgp->dev->name);
1579 stats->valid = 0;
1580 schedule_work(&mgp->watchdog_work);
1581 }
1582 if (likely(stats->valid == 0))
1583 break;
1584 cpu_relax();
1585 barrier();
1586 }
1587
236bb5e6
BG		 1588 /* Only slice 0 updates stats */
1589 if (ss == mgp->ss)
1590 myri10ge_check_statblock(mgp);
0da34b6d 1591
b53bef84 1592 put_be32(htonl(3), ss->irq_claim + 1);
0da34b6d
BG		 1593 return (IRQ_HANDLED);
1594}
1595
1596static int
1597myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1598{
c0bf8801
BG		 1599 struct myri10ge_priv *mgp = netdev_priv(netdev);
1600 char *ptr;
1601 int i;
1602
0da34b6d
BG		 1603 cmd->autoneg = AUTONEG_DISABLE;
1604 cmd->speed = SPEED_10000;
1605 cmd->duplex = DUPLEX_FULL;
c0bf8801
BG		 1606
1607 /*
1608 * parse the product code to deterimine the interface type
1609 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1610 * after the 3rd dash in the driver's cached copy of the
1611 * EEPROM's product code string.
1612 */
1613 ptr = mgp->product_code_string;
1614 if (ptr == NULL) {
1615 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
99f5f87e 1616 netdev->name);
c0bf8801
BG		 1617 return 0;
1618 }
1619 for (i = 0; i < 3; i++, ptr++) {
1620 ptr = strchr(ptr, '-');
1621 if (ptr == NULL) {
1622 printk(KERN_ERR "myri10ge: %s: Invalid product "
1623 "code %s\n", netdev->name,
1624 mgp->product_code_string);
1625 return 0;
1626 }
1627 }
1628 if (*ptr == 'R' || *ptr == 'Q') {
1629 /* We've found either an XFP or quad ribbon fiber */
1630 cmd->port = PORT_FIBRE;
1631 }
0da34b6d
BG		 1632 return 0;
1633}
1634
1635static void
1636myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1637{
1638 struct myri10ge_priv *mgp = netdev_priv(netdev);
1639
1640 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1641 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1642 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1643 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1644}
1645
1646static int
1647myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1648{
1649 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1650
0da34b6d
BG		 1651 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1652 return 0;
1653}
1654
1655static int
1656myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1657{
1658 struct myri10ge_priv *mgp = netdev_priv(netdev);
1659
1660 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1661 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1662 return 0;
1663}
1664
1665static void
1666myri10ge_get_pauseparam(struct net_device *netdev,
1667 struct ethtool_pauseparam *pause)
1668{
1669 struct myri10ge_priv *mgp = netdev_priv(netdev);
1670
1671 pause->autoneg = 0;
1672 pause->rx_pause = mgp->pause;
1673 pause->tx_pause = mgp->pause;
1674}
1675
1676static int
1677myri10ge_set_pauseparam(struct net_device *netdev,
1678 struct ethtool_pauseparam *pause)
1679{
1680 struct myri10ge_priv *mgp = netdev_priv(netdev);
1681
1682 if (pause->tx_pause != mgp->pause)
1683 return myri10ge_change_pause(mgp, pause->tx_pause);
1684 if (pause->rx_pause != mgp->pause)
1685 return myri10ge_change_pause(mgp, pause->tx_pause);
1686 if (pause->autoneg != 0)
1687 return -EINVAL;
1688 return 0;
1689}
1690
1691static void
1692myri10ge_get_ringparam(struct net_device *netdev,
1693 struct ethtool_ringparam *ring)
1694{
1695 struct myri10ge_priv *mgp = netdev_priv(netdev);
1696
0dcffac1
BG		 1697 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1698 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1699 ring->rx_jumbo_max_pending = 0;
6498be3f 1700 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1701 ring->rx_mini_pending = ring->rx_mini_max_pending;
1702 ring->rx_pending = ring->rx_max_pending;
1703 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1704 ring->tx_pending = ring->tx_max_pending;
1705}
1706
1707static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1708{
1709 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1710
0da34b6d
BG		 1711 if (mgp->csum_flag)
1712 return 1;
1713 else
1714 return 0;
1715}
1716
1717static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1718{
1719 struct myri10ge_priv *mgp = netdev_priv(netdev);
3a0c7d2d 1720 int err = 0;
99f5f87e 1721
0da34b6d
BG		 1722 if (csum_enabled)
1723 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3a0c7d2d
BG		 1724 else {
1725 u32 flags = ethtool_op_get_flags(netdev);
1726 err = ethtool_op_set_flags(netdev, (flags & ~ETH_FLAG_LRO));
0da34b6d 1727 mgp->csum_flag = 0;
3a0c7d2d
BG		 1728
1729 }
1730 return err;
0da34b6d
BG		 1731}
1732
4f93fde0
BG		 1733static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1734{
1735 struct myri10ge_priv *mgp = netdev_priv(netdev);
1736 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1737
1738 if (tso_enabled)
1739 netdev->features |= flags;
1740 else
1741 netdev->features &= ~flags;
1742 return 0;
1743}
1744
b53bef84 1745static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1746 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1747 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1748 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1749 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1750 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1751 "tx_heartbeat_errors", "tx_window_errors",
1752 /* device-specific stats */
0dcffac1 1753 "tx_boundary", "WC", "irq", "MSI", "MSIX",
0da34b6d 1754 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1755 "serial_number", "watchdog_resets",
5dd2d332 1756#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1757 "dca_capable_firmware", "dca_device_present",
981813d8 1758#endif
c58ac5ca 1759 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1760 "dropped_link_error_or_filtered",
1761 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1762 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1763 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1764 "dropped_no_big_buffer"
1765};
1766
1767static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1768 "----------- slice ---------",
1769 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1770 "rx_small_cnt", "rx_big_cnt",
1771 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1772 "LRO flushed",
1e6e9342 1773 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1774};
1775
1776#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1777#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1778#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1779
1780static void
1781myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1782{
0dcffac1
BG		 1783 struct myri10ge_priv *mgp = netdev_priv(netdev);
1784 int i;
1785
0da34b6d
BG		 1786 switch (stringset) {
1787 case ETH_SS_STATS:
b53bef84
BG		 1788 memcpy(data, *myri10ge_gstrings_main_stats,
1789 sizeof(myri10ge_gstrings_main_stats));
1790 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1791 for (i = 0; i < mgp->num_slices; i++) {
1792 memcpy(data, *myri10ge_gstrings_slice_stats,
1793 sizeof(myri10ge_gstrings_slice_stats));
1794 data += sizeof(myri10ge_gstrings_slice_stats);
1795 }
0da34b6d
BG		 1796 break;
1797 }
1798}
1799
b9f2c044 1800static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1801{
0dcffac1
BG		 1802 struct myri10ge_priv *mgp = netdev_priv(netdev);
1803
b9f2c044
JG		 1804 switch (sset) {
1805 case ETH_SS_STATS:
0dcffac1
BG		 1806 return MYRI10GE_MAIN_STATS_LEN +
1807 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1808 default:
1809 return -EOPNOTSUPP;
1810 }
0da34b6d
BG		 1811}
1812
1813static void
1814myri10ge_get_ethtool_stats(struct net_device *netdev,
1815 struct ethtool_stats *stats, u64 * data)
1816{
1817 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1818 struct myri10ge_slice_state *ss;
0dcffac1 1819 int slice;
0da34b6d
BG		 1820 int i;
1821
59081825
BG		 1822 /* force stats update */
1823 (void)myri10ge_get_stats(netdev);
0da34b6d
BG		 1824 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1825 data[i] = ((unsigned long *)&mgp->stats)[i];
1826
b53bef84 1827 data[i++] = (unsigned int)mgp->tx_boundary;
276e26c3 1828 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1829 data[i++] = (unsigned int)mgp->pdev->irq;
1830 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1831 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1832 data[i++] = (unsigned int)mgp->read_dma;
1833 data[i++] = (unsigned int)mgp->write_dma;
1834 data[i++] = (unsigned int)mgp->read_write_dma;
1835 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1836 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1837#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1838 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1839 data[i++] = (unsigned int)(mgp->dca_enabled);
1840#endif
c58ac5ca 1841 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1842
1843 /* firmware stats are useful only in the first slice */
0dcffac1 1844 ss = &mgp->ss[0];
b53bef84
BG		 1845 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1846 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1847 data[i++] =
b53bef84
BG		 1848 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1849 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1850 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1851 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1852 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1853 data[i++] =
b53bef84
BG		 1854 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1855 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1856 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1857 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1858 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1859
0dcffac1
BG		 1860 for (slice = 0; slice < mgp->num_slices; slice++) {
1861 ss = &mgp->ss[slice];
1862 data[i++] = slice;
1863 data[i++] = (unsigned int)ss->tx.pkt_start;
1864 data[i++] = (unsigned int)ss->tx.pkt_done;
1865 data[i++] = (unsigned int)ss->tx.req;
1866 data[i++] = (unsigned int)ss->tx.done;
1867 data[i++] = (unsigned int)ss->rx_small.cnt;
1868 data[i++] = (unsigned int)ss->rx_big.cnt;
1869 data[i++] = (unsigned int)ss->tx.wake_queue;
1870 data[i++] = (unsigned int)ss->tx.stop_queue;
1871 data[i++] = (unsigned int)ss->tx.linearized;
1872 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1873 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1874 if (ss->rx_done.lro_mgr.stats.flushed)
1875 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1876 ss->rx_done.lro_mgr.stats.flushed;
1877 else
1878 data[i++] = 0;
1879 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1880 }
0da34b6d
BG		 1881}
1882
c58ac5ca
BG		 1883static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1884{
1885 struct myri10ge_priv *mgp = netdev_priv(netdev);
1886 mgp->msg_enable = value;
1887}
1888
1889static u32 myri10ge_get_msglevel(struct net_device *netdev)
1890{
1891 struct myri10ge_priv *mgp = netdev_priv(netdev);
1892 return mgp->msg_enable;
1893}
1894
7282d491 1895static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1896 .get_settings = myri10ge_get_settings,
1897 .get_drvinfo = myri10ge_get_drvinfo,
1898 .get_coalesce = myri10ge_get_coalesce,
1899 .set_coalesce = myri10ge_set_coalesce,
1900 .get_pauseparam = myri10ge_get_pauseparam,
1901 .set_pauseparam = myri10ge_set_pauseparam,
1902 .get_ringparam = myri10ge_get_ringparam,
1903 .get_rx_csum = myri10ge_get_rx_csum,
1904 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1905 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1906 .set_sg = ethtool_op_set_sg,
4f93fde0 1907 .set_tso = myri10ge_set_tso,
6ffdd071 1908 .get_link = ethtool_op_get_link,
0da34b6d 1909 .get_strings = myri10ge_get_strings,
b9f2c044 1910 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1911 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1912 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d
BG		 1913 .get_msglevel = myri10ge_get_msglevel,
1914 .get_flags = ethtool_op_get_flags,
1915 .set_flags = ethtool_op_set_flags
0da34b6d
BG		 1916};
1917
b53bef84 1918static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1919{
b53bef84 1920 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1921 struct myri10ge_cmd cmd;
b53bef84 1922 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1923 int tx_ring_size, rx_ring_size;
1924 int tx_ring_entries, rx_ring_entries;
0dcffac1 1925 int i, slice, status;
0da34b6d
BG		 1926 size_t bytes;
1927
0da34b6d 1928 /* get ring sizes */
0dcffac1
BG		 1929 slice = ss - mgp->ss;
1930 cmd.data0 = slice;
0da34b6d
BG		 1931 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1932 tx_ring_size = cmd.data0;
0dcffac1 1933 cmd.data0 = slice;
0da34b6d 1934 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1935 if (status != 0)
1936 return status;
0da34b6d
BG		 1937 rx_ring_size = cmd.data0;
1938
1939 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1940 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1941 ss->tx.mask = tx_ring_entries - 1;
1942 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1943
355c7265
BG		 1944 status = -ENOMEM;
1945
0da34b6d
BG		 1946 /* allocate the host shadow rings */
1947
1948 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1949 * sizeof(*ss->tx.req_list);
1950 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1951 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1952 goto abort_with_nothing;
1953
1954 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1955 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1956 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 1957 ss->tx.queue_active = 0;
0da34b6d 1958
b53bef84
BG		 1959 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1960 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1961 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1962 goto abort_with_tx_req_bytes;
1963
b53bef84
BG		 1964 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1965 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1966 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1967 goto abort_with_rx_small_shadow;
1968
1969 /* allocate the host info rings */
1970
b53bef84
BG		 1971 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1972 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1973 if (ss->tx.info == NULL)
0da34b6d
BG		 1974 goto abort_with_rx_big_shadow;
1975
b53bef84
BG		 1976 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1977 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1978 if (ss->rx_small.info == NULL)
0da34b6d
BG		 1979 goto abort_with_tx_info;
1980
b53bef84
BG		 1981 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1982 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1983 if (ss->rx_big.info == NULL)
0da34b6d
BG		 1984 goto abort_with_rx_small_info;
1985
1986 /* Fill the receive rings */
b53bef84
BG		 1987 ss->rx_big.cnt = 0;
1988 ss->rx_small.cnt = 0;
1989 ss->rx_big.fill_cnt = 0;
1990 ss->rx_small.fill_cnt = 0;
1991 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1992 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1993 ss->rx_small.watchdog_needed = 0;
1994 ss->rx_big.watchdog_needed = 0;
1995 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1996 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1997
b53bef84 1998 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
0dcffac1
BG		 1999 printk(KERN_ERR
2000 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
2001 dev->name, slice, ss->rx_small.fill_cnt);
c7dab99b 2002 goto abort_with_rx_small_ring;
0da34b6d
BG		 2003 }
2004
b53bef84
BG		 2005 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2006 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
0dcffac1
BG		 2007 printk(KERN_ERR
2008 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
2009 dev->name, slice, ss->rx_big.fill_cnt);
c7dab99b 2010 goto abort_with_rx_big_ring;
0da34b6d
BG		 2011 }
2012
2013 return 0;
2014
2015abort_with_rx_big_ring:
b53bef84
BG		 2016 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2017 int idx = i & ss->rx_big.mask;
2018 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2019 mgp->big_bytes);
b53bef84 2020 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2021 }
2022
2023abort_with_rx_small_ring:
b53bef84
BG		 2024 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2025 int idx = i & ss->rx_small.mask;
2026 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2027 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2028 put_page(ss->rx_small.info[idx].page);
0da34b6d 2029 }
c7dab99b 2030
b53bef84 2031 kfree(ss->rx_big.info);
0da34b6d
BG		 2032
2033abort_with_rx_small_info:
b53bef84 2034 kfree(ss->rx_small.info);
0da34b6d
BG		 2035
2036abort_with_tx_info:
b53bef84 2037 kfree(ss->tx.info);
0da34b6d
BG		 2038
2039abort_with_rx_big_shadow:
b53bef84 2040 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2041
2042abort_with_rx_small_shadow:
b53bef84 2043 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2044
2045abort_with_tx_req_bytes:
b53bef84
BG		 2046 kfree(ss->tx.req_bytes);
2047 ss->tx.req_bytes = NULL;
2048 ss->tx.req_list = NULL;
0da34b6d
BG		 2049
2050abort_with_nothing:
2051 return status;
2052}
2053
b53bef84 2054static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2055{
b53bef84 2056 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2057 struct sk_buff *skb;
2058 struct myri10ge_tx_buf *tx;
2059 int i, len, idx;
2060
0dcffac1
BG		 2061 /* If not allocated, skip it */
2062 if (ss->tx.req_list == NULL)
2063 return;
2064
b53bef84
BG		 2065 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2066 idx = i & ss->rx_big.mask;
2067 if (i == ss->rx_big.fill_cnt - 1)
2068 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2069 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2070 mgp->big_bytes);
b53bef84 2071 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2072 }
2073
b53bef84
BG		 2074 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2075 idx = i & ss->rx_small.mask;
2076 if (i == ss->rx_small.fill_cnt - 1)
2077 ss->rx_small.info[idx].page_offset =
c7dab99b 2078 MYRI10GE_ALLOC_SIZE;
b53bef84 2079 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2080 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2081 put_page(ss->rx_small.info[idx].page);
c7dab99b 2082 }
b53bef84 2083 tx = &ss->tx;
0da34b6d
BG		 2084 while (tx->done != tx->req) {
2085 idx = tx->done & tx->mask;
2086 skb = tx->info[idx].skb;
2087
2088 /* Mark as free */
2089 tx->info[idx].skb = NULL;
2090 tx->done++;
2091 len = pci_unmap_len(&tx->info[idx], len);
2092 pci_unmap_len_set(&tx->info[idx], len, 0);
2093 if (skb) {
b53bef84 2094 ss->stats.tx_dropped++;
0da34b6d
BG		 2095 dev_kfree_skb_any(skb);
2096 if (len)
2097 pci_unmap_single(mgp->pdev,
2098 pci_unmap_addr(&tx->info[idx],
2099 bus), len,
2100 PCI_DMA_TODEVICE);
2101 } else {
2102 if (len)
2103 pci_unmap_page(mgp->pdev,
2104 pci_unmap_addr(&tx->info[idx],
2105 bus), len,
2106 PCI_DMA_TODEVICE);
2107 }
2108 }
b53bef84 2109 kfree(ss->rx_big.info);
0da34b6d 2110
b53bef84 2111 kfree(ss->rx_small.info);
0da34b6d 2112
b53bef84 2113 kfree(ss->tx.info);
0da34b6d 2114
b53bef84 2115 kfree(ss->rx_big.shadow);
0da34b6d 2116
b53bef84 2117 kfree(ss->rx_small.shadow);
0da34b6d 2118
b53bef84
BG		 2119 kfree(ss->tx.req_bytes);
2120 ss->tx.req_bytes = NULL;
2121 ss->tx.req_list = NULL;
0da34b6d
BG		 2122}
2123
df30a740
BG		 2124static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2125{
2126 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2127 struct myri10ge_slice_state *ss;
2128 struct net_device *netdev = mgp->dev;
2129 int i;
df30a740
BG		 2130 int status;
2131
0dcffac1
BG		 2132 mgp->msi_enabled = 0;
2133 mgp->msix_enabled = 0;
2134 status = 0;
df30a740 2135 if (myri10ge_msi) {
0dcffac1
BG		 2136 if (mgp->num_slices > 1) {
2137 status =
2138 pci_enable_msix(pdev, mgp->msix_vectors,
2139 mgp->num_slices);
2140 if (status == 0) {
2141 mgp->msix_enabled = 1;
2142 } else {
2143 dev_err(&pdev->dev,
2144 "Error %d setting up MSI-X\n", status);
2145 return status;
2146 }
2147 }
2148 if (mgp->msix_enabled == 0) {
2149 status = pci_enable_msi(pdev);
2150 if (status != 0) {
2151 dev_err(&pdev->dev,
2152 "Error %d setting up MSI; falling back to xPIC\n",
2153 status);
2154 } else {
2155 mgp->msi_enabled = 1;
2156 }
2157 }
df30a740 2158 }
0dcffac1
BG		 2159 if (mgp->msix_enabled) {
2160 for (i = 0; i < mgp->num_slices; i++) {
2161 ss = &mgp->ss[i];
2162 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2163 "%s:slice-%d", netdev->name, i);
2164 status = request_irq(mgp->msix_vectors[i].vector,
2165 myri10ge_intr, 0, ss->irq_desc,
2166 ss);
2167 if (status != 0) {
2168 dev_err(&pdev->dev,
2169 "slice %d failed to allocate IRQ\n", i);
2170 i--;
2171 while (i >= 0) {
2172 free_irq(mgp->msix_vectors[i].vector,
2173 &mgp->ss[i]);
2174 i--;
2175 }
2176 pci_disable_msix(pdev);
2177 return status;
2178 }
2179 }
2180 } else {
2181 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2182 mgp->dev->name, &mgp->ss[0]);
2183 if (status != 0) {
2184 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2185 if (mgp->msi_enabled)
2186 pci_disable_msi(pdev);
2187 }
df30a740
BG		 2188 }
2189 return status;
2190}
2191
2192static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2193{
2194 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2195 int i;
df30a740 2196
0dcffac1
BG		 2197 if (mgp->msix_enabled) {
2198 for (i = 0; i < mgp->num_slices; i++)
2199 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2200 } else {
2201 free_irq(pdev->irq, &mgp->ss[0]);
2202 }
df30a740
BG		 2203 if (mgp->msi_enabled)
2204 pci_disable_msi(pdev);
0dcffac1
BG		 2205 if (mgp->msix_enabled)
2206 pci_disable_msix(pdev);
df30a740
BG		 2207}
2208
1e6e9342
AG		 2209static int
2210myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2211 void **ip_hdr, void **tcpudp_hdr,
2212 u64 * hdr_flags, void *priv)
2213{
2214 struct ethhdr *eh;
2215 struct vlan_ethhdr *veh;
2216 struct iphdr *iph;
2217 u8 *va = page_address(frag->page) + frag->page_offset;
2218 unsigned long ll_hlen;
66341fff
AV		 2219 /* passed opaque through lro_receive_frags() */
2220 __wsum csum = (__force __wsum) (unsigned long)priv;
1e6e9342
AG		 2221
2222 /* find the mac header, aborting if not IPv4 */
2223
2224 eh = (struct ethhdr *)va;
2225 *mac_hdr = eh;
2226 ll_hlen = ETH_HLEN;
2227 if (eh->h_proto != htons(ETH_P_IP)) {
2228 if (eh->h_proto == htons(ETH_P_8021Q)) {
2229 veh = (struct vlan_ethhdr *)va;
2230 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2231 return -1;
2232
2233 ll_hlen += VLAN_HLEN;
2234
2235 /*
2236 * HW checksum starts ETH_HLEN bytes into
2237 * frame, so we must subtract off the VLAN
2238 * header's checksum before csum can be used
2239 */
2240 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2241 VLAN_HLEN, 0));
2242 } else {
2243 return -1;
2244 }
2245 }
2246 *hdr_flags = LRO_IPV4;
2247
2248 iph = (struct iphdr *)(va + ll_hlen);
2249 *ip_hdr = iph;
2250 if (iph->protocol != IPPROTO_TCP)
2251 return -1;
bcb09dc2
BG		 2252 if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2253 return -1;
1e6e9342
AG		 2254 *hdr_flags |= LRO_TCP;
2255 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2256
2257 /* verify the IP checksum */
2258 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2259 return -1;
2260
2261 /* verify the checksum */
2262 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2263 ntohs(iph->tot_len) - (iph->ihl << 2),
2264 IPPROTO_TCP, csum)))
2265 return -1;
2266
2267 return 0;
2268}
2269
77929732
BG		 2270static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2271{
2272 struct myri10ge_cmd cmd;
2273 struct myri10ge_slice_state *ss;
2274 int status;
2275
2276 ss = &mgp->ss[slice];
236bb5e6
BG		 2277 status = 0;
2278 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2279 cmd.data0 = slice;
2280 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2281 &cmd, 0);
2282 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2283 (mgp->sram + cmd.data0);
2284 }
77929732
BG		 2285 cmd.data0 = slice;
2286 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2287 &cmd, 0);
2288 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2289 (mgp->sram + cmd.data0);
2290
2291 cmd.data0 = slice;
2292 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2293 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2294 (mgp->sram + cmd.data0);
2295
236bb5e6
BG		 2296 ss->tx.send_go = (__iomem __be32 *)
2297 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2298 ss->tx.send_stop = (__iomem __be32 *)
2299 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2300 return status;
2301
2302}
2303
2304static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2305{
2306 struct myri10ge_cmd cmd;
2307 struct myri10ge_slice_state *ss;
2308 int status;
2309
2310 ss = &mgp->ss[slice];
2311 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2312 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2313 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2314 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2315 if (status == -ENOSYS) {
2316 dma_addr_t bus = ss->fw_stats_bus;
2317 if (slice != 0)
2318 return -EINVAL;
2319 bus += offsetof(struct mcp_irq_data, send_done_count);
2320 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2321 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2322 status = myri10ge_send_cmd(mgp,
2323 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2324 &cmd, 0);
2325 /* Firmware cannot support multicast without STATS_DMA_V2 */
2326 mgp->fw_multicast_support = 0;
2327 } else {
2328 mgp->fw_multicast_support = 1;
2329 }
2330 return 0;
2331}
77929732 2332
0da34b6d
BG		 2333static int myri10ge_open(struct net_device *dev)
2334{
0dcffac1 2335 struct myri10ge_slice_state *ss;
b53bef84 2336 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2337 struct myri10ge_cmd cmd;
0dcffac1
BG		 2338 int i, status, big_pow2, slice;
2339 u8 *itable;
1e6e9342 2340 struct net_lro_mgr *lro_mgr;
0da34b6d 2341
0da34b6d
BG		 2342 if (mgp->running != MYRI10GE_ETH_STOPPED)
2343 return -EBUSY;
2344
2345 mgp->running = MYRI10GE_ETH_STARTING;
2346 status = myri10ge_reset(mgp);
2347 if (status != 0) {
2348 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 2349 goto abort_with_nothing;
0da34b6d
BG		 2350 }
2351
0dcffac1
BG		 2352 if (mgp->num_slices > 1) {
2353 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2354 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2355 if (mgp->dev->real_num_tx_queues > 1)
2356 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2357 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2358 &cmd, 0);
2359 if (status != 0) {
2360 printk(KERN_ERR
2361 "myri10ge: %s: failed to set number of slices\n",
2362 dev->name);
2363 goto abort_with_nothing;
2364 }
2365 /* setup the indirection table */
2366 cmd.data0 = mgp->num_slices;
2367 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2368 &cmd, 0);
2369
2370 status |= myri10ge_send_cmd(mgp,
2371 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2372 &cmd, 0);
2373 if (status != 0) {
2374 printk(KERN_ERR
2375 "myri10ge: %s: failed to setup rss tables\n",
2376 dev->name);
236bb5e6 2377 goto abort_with_nothing;
0dcffac1
BG		 2378 }
2379
2380 /* just enable an identity mapping */
2381 itable = mgp->sram + cmd.data0;
2382 for (i = 0; i < mgp->num_slices; i++)
2383 __raw_writeb(i, &itable[i]);
2384
2385 cmd.data0 = 1;
2386 cmd.data1 = myri10ge_rss_hash;
2387 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2388 &cmd, 0);
2389 if (status != 0) {
2390 printk(KERN_ERR
2391 "myri10ge: %s: failed to enable slices\n",
2392 dev->name);
2393 goto abort_with_nothing;
2394 }
2395 }
2396
df30a740
BG		 2397 status = myri10ge_request_irq(mgp);
2398 if (status != 0)
2399 goto abort_with_nothing;
2400
0da34b6d
BG		 2401 /* decide what small buffer size to use. For good TCP rx
2402 * performance, it is important to not receive 1514 byte
2403 * frames into jumbo buffers, as it confuses the socket buffer
2404 * accounting code, leading to drops and erratic performance.
2405 */
2406
2407 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2408 /* enough for a TCP header */
2409 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2410 ? (128 - MXGEFW_PAD)
2411 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2412 else
de3c4507
BG		 2413 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2414 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2415
2416 /* Override the small buffer size? */
2417 if (myri10ge_small_bytes > 0)
2418 mgp->small_bytes = myri10ge_small_bytes;
2419
0da34b6d
BG		 2420 /* Firmware needs the big buff size as a power of 2. Lie and
2421 * tell him the buffer is larger, because we only use 1
2422 * buffer/pkt, and the mtu will prevent overruns.
2423 */
13348bee 2424 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2425 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2426 while (!is_power_of_2(big_pow2))
c7dab99b 2427 big_pow2++;
13348bee 2428 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2429 } else {
2430 big_pow2 = MYRI10GE_ALLOC_SIZE;
2431 mgp->big_bytes = big_pow2;
2432 }
2433
0dcffac1
BG		 2434 /* setup the per-slice data structures */
2435 for (slice = 0; slice < mgp->num_slices; slice++) {
2436 ss = &mgp->ss[slice];
2437
2438 status = myri10ge_get_txrx(mgp, slice);
2439 if (status != 0) {
2440 printk(KERN_ERR
2441 "myri10ge: %s: failed to get ring sizes or locations\n",
2442 dev->name);
2443 goto abort_with_rings;
2444 }
2445 status = myri10ge_allocate_rings(ss);
2446 if (status != 0)
2447 goto abort_with_rings;
236bb5e6
BG		 2448
2449 /* only firmware which supports multiple TX queues
2450 * supports setting up the tx stats on non-zero
2451 * slices */
2452 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2453 status = myri10ge_set_stats(mgp, slice);
2454 if (status) {
2455 printk(KERN_ERR
2456 "myri10ge: %s: Couldn't set stats DMA\n",
2457 dev->name);
2458 goto abort_with_rings;
2459 }
2460
2461 lro_mgr = &ss->rx_done.lro_mgr;
2462 lro_mgr->dev = dev;
2463 lro_mgr->features = LRO_F_NAPI;
2464 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2465 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2466 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2467 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2468 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2469 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
636d2f68 2470 lro_mgr->frag_align_pad = 2;
0dcffac1
BG		 2471 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2472 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2473
2474 /* must happen prior to any irq */
2475 napi_enable(&(ss)->napi);
2476 }
0da34b6d
BG		 2477
2478 /* now give firmware buffers sizes, and MTU */
2479 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2480 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2481 cmd.data0 = mgp->small_bytes;
2482 status |=
2483 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2484 cmd.data0 = big_pow2;
2485 status |=
2486 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2487 if (status) {
2488 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2489 dev->name);
2490 goto abort_with_rings;
2491 }
2492
0dcffac1
BG		 2493 /*
2494 * Set Linux style TSO mode; this is needed only on newer
2495 * firmware versions. Older versions default to Linux
2496 * style TSO
2497 */
2498 cmd.data0 = 0;
2499 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2500 if (status && status != -ENOSYS) {
2501 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
0da34b6d
BG		 2502 dev->name);
2503 goto abort_with_rings;
2504 }
2505
66341fff 2506 mgp->link_state = ~0U;
0da34b6d
BG		 2507 mgp->rdma_tags_available = 15;
2508
0da34b6d
BG		 2509 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2510 if (status) {
2511 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2512 dev->name);
2513 goto abort_with_rings;
2514 }
2515
0da34b6d
BG		 2516 mgp->running = MYRI10GE_ETH_RUNNING;
2517 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2518 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2519 netif_tx_wake_all_queues(dev);
2520
0da34b6d
BG		 2521 return 0;
2522
2523abort_with_rings:
051d36f3
BG		 2524 while (slice) {
2525 slice--;
2526 napi_disable(&mgp->ss[slice].napi);
2527 }
0dcffac1
BG		 2528 for (i = 0; i < mgp->num_slices; i++)
2529 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2530
df30a740
BG		 2531 myri10ge_free_irq(mgp);
2532
0da34b6d
BG		 2533abort_with_nothing:
2534 mgp->running = MYRI10GE_ETH_STOPPED;
2535 return -ENOMEM;
2536}
2537
2538static int myri10ge_close(struct net_device *dev)
2539{
b53bef84 2540 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2541 struct myri10ge_cmd cmd;
2542 int status, old_down_cnt;
0dcffac1 2543 int i;
0da34b6d 2544
0da34b6d
BG		 2545 if (mgp->running != MYRI10GE_ETH_RUNNING)
2546 return 0;
2547
0dcffac1 2548 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2549 return 0;
2550
2551 del_timer_sync(&mgp->watchdog_timer);
2552 mgp->running = MYRI10GE_ETH_STOPPING;
0dcffac1
BG		 2553 for (i = 0; i < mgp->num_slices; i++) {
2554 napi_disable(&mgp->ss[i].napi);
2555 }
0da34b6d 2556 netif_carrier_off(dev);
236bb5e6
BG		 2557
2558 netif_tx_stop_all_queues(dev);
0da34b6d
BG		 2559 old_down_cnt = mgp->down_cnt;
2560 mb();
2561 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2562 if (status)
2563 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2564 dev->name);
2565
2566 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2567 if (old_down_cnt == mgp->down_cnt)
2568 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2569
2570 netif_tx_disable(dev);
df30a740 2571 myri10ge_free_irq(mgp);
0dcffac1
BG		 2572 for (i = 0; i < mgp->num_slices; i++)
2573 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2574
2575 mgp->running = MYRI10GE_ETH_STOPPED;
2576 return 0;
2577}
2578
2579/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2580 * backwards one at a time and handle ring wraps */
2581
2582static inline void
2583myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2584 struct mcp_kreq_ether_send *src, int cnt)
2585{
2586 int idx, starting_slot;
2587 starting_slot = tx->req;
2588 while (cnt > 1) {
2589 cnt--;
2590 idx = (starting_slot + cnt) & tx->mask;
2591 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2592 mb();
2593 }
2594}
2595
2596/*
2597 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2598 * at most 32 bytes at a time, so as to avoid involving the software
2599 * pio handler in the nic. We re-write the first segment's flags
2600 * to mark them valid only after writing the entire chain.
2601 */
2602
2603static inline void
2604myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2605 int cnt)
2606{
2607 int idx, i;
2608 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2609 struct mcp_kreq_ether_send *srcp;
2610 u8 last_flags;
2611
2612 idx = tx->req & tx->mask;
2613
2614 last_flags = src->flags;
2615 src->flags = 0;
2616 mb();
2617 dst = dstp = &tx->lanai[idx];
2618 srcp = src;
2619
2620 if ((idx + cnt) < tx->mask) {
2621 for (i = 0; i < (cnt - 1); i += 2) {
2622 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2623 mb(); /* force write every 32 bytes */
2624 srcp += 2;
2625 dstp += 2;
2626 }
2627 } else {
2628 /* submit all but the first request, and ensure
2629 * that it is submitted below */
2630 myri10ge_submit_req_backwards(tx, src, cnt);
2631 i = 0;
2632 }
2633 if (i < cnt) {
2634 /* submit the first request */
2635 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2636 mb(); /* barrier before setting valid flag */
2637 }
2638
2639 /* re-write the last 32-bits with the valid flags */
2640 src->flags = last_flags;
40f6cff5 2641 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2642 tx->req += cnt;
2643 mb();
2644}
2645
0da34b6d
BG		 2646/*
2647 * Transmit a packet. We need to split the packet so that a single
b53bef84 2648 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2649 * counting tricky. So rather than try to count segments up front, we
2650 * just give up if there are too few segments to hold a reasonably
2651 * fragmented packet currently available. If we run
2652 * out of segments while preparing a packet for DMA, we just linearize
2653 * it and try again.
2654 */
2655
2656static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2657{
2658 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2659 struct myri10ge_slice_state *ss;
0da34b6d 2660 struct mcp_kreq_ether_send *req;
b53bef84 2661 struct myri10ge_tx_buf *tx;
0da34b6d 2662 struct skb_frag_struct *frag;
236bb5e6 2663 struct netdev_queue *netdev_queue;
0da34b6d 2664 dma_addr_t bus;
40f6cff5
AV		 2665 u32 low;
2666 __be32 high_swapped;
0da34b6d
BG		 2667 unsigned int len;
2668 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2669 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2670 int cum_len, seglen, boundary, rdma_count;
2671 u8 flags, odd_flag;
2672
236bb5e6 2673 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2674 ss = &mgp->ss[queue];
2675 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2676 tx = &ss->tx;
236bb5e6 2677
0da34b6d
BG		 2678again:
2679 req = tx->req_list;
2680 avail = tx->mask - 1 - (tx->req - tx->done);
2681
2682 mss = 0;
2683 max_segments = MXGEFW_MAX_SEND_DESC;
2684
917690cd 2685 if (skb_is_gso(skb)) {
7967168c 2686 mss = skb_shinfo(skb)->gso_size;
917690cd 2687 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2688 }
0da34b6d
BG		 2689
2690 if ((unlikely(avail < max_segments))) {
2691 /* we are out of transmit resources */
b53bef84 2692 tx->stop_queue++;
236bb5e6 2693 netif_tx_stop_queue(netdev_queue);
0da34b6d
BG		 2694 return 1;
2695 }
2696
2697 /* Setup checksum offloading, if needed */
2698 cksum_offset = 0;
2699 pseudo_hdr_offset = 0;
2700 odd_flag = 0;
2701 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2702 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2703 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2704 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2705 /* If the headers are excessively large, then we must
2706 * fall back to a software checksum */
4f93fde0
BG		 2707 if (unlikely(!mss && (cksum_offset > 255 ||
2708 pseudo_hdr_offset > 127))) {
84fa7933 2709 if (skb_checksum_help(skb))
0da34b6d
BG		 2710 goto drop;
2711 cksum_offset = 0;
2712 pseudo_hdr_offset = 0;
2713 } else {
0da34b6d
BG		 2714 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2715 flags |= MXGEFW_FLAGS_CKSUM;
2716 }
2717 }
2718
2719 cum_len = 0;
2720
0da34b6d
BG		 2721 if (mss) { /* TSO */
2722 /* this removes any CKSUM flag from before */
2723 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2724
2725 /* negative cum_len signifies to the
2726 * send loop that we are still in the
2727 * header portion of the TSO packet.
4f93fde0 2728 * TSO header can be at most 1KB long */
ab6a5bb6 2729 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2730
4f93fde0
BG		 2731 /* for IPv6 TSO, the checksum offset stores the
2732 * TCP header length, to save the firmware from
2733 * the need to parse the headers */
2734 if (skb_is_gso_v6(skb)) {
2735 cksum_offset = tcp_hdrlen(skb);
2736 /* Can only handle headers <= max_tso6 long */
2737 if (unlikely(-cum_len > mgp->max_tso6))
2738 return myri10ge_sw_tso(skb, dev);
2739 }
0da34b6d
BG		 2740 /* for TSO, pseudo_hdr_offset holds mss.
2741 * The firmware figures out where to put
2742 * the checksum by parsing the header. */
40f6cff5 2743 pseudo_hdr_offset = mss;
0da34b6d 2744 } else
0da34b6d
BG		 2745 /* Mark small packets, and pad out tiny packets */
2746 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2747 flags |= MXGEFW_FLAGS_SMALL;
2748
2749 /* pad frames to at least ETH_ZLEN bytes */
2750 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2751 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2752 /* The packet is gone, so we must
2753 * return 0 */
b53bef84 2754 ss->stats.tx_dropped += 1;
0da34b6d
BG		 2755 return 0;
2756 }
2757 /* adjust the len to account for the zero pad
2758 * so that the nic can know how long it is */
2759 skb->len = ETH_ZLEN;
2760 }
2761 }
2762
2763 /* map the skb for DMA */
2764 len = skb->len - skb->data_len;
2765 idx = tx->req & tx->mask;
2766 tx->info[idx].skb = skb;
2767 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2768 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2769 pci_unmap_len_set(&tx->info[idx], len, len);
2770
2771 frag_cnt = skb_shinfo(skb)->nr_frags;
2772 frag_idx = 0;
2773 count = 0;
2774 rdma_count = 0;
2775
2776 /* "rdma_count" is the number of RDMAs belonging to the
2777 * current packet BEFORE the current send request. For
2778 * non-TSO packets, this is equal to "count".
2779 * For TSO packets, rdma_count needs to be reset
2780 * to 0 after a segment cut.
2781 *
2782 * The rdma_count field of the send request is
2783 * the number of RDMAs of the packet starting at
2784 * that request. For TSO send requests with one ore more cuts
2785 * in the middle, this is the number of RDMAs starting
2786 * after the last cut in the request. All previous
2787 * segments before the last cut implicitly have 1 RDMA.
2788 *
2789 * Since the number of RDMAs is not known beforehand,
2790 * it must be filled-in retroactively - after each
2791 * segmentation cut or at the end of the entire packet.
2792 */
2793
2794 while (1) {
2795 /* Break the SKB or Fragment up into pieces which
b53bef84 2796 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2797 low = MYRI10GE_LOWPART_TO_U32(bus);
2798 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2799 while (len) {
2800 u8 flags_next;
2801 int cum_len_next;
2802
2803 if (unlikely(count == max_segments))
2804 goto abort_linearize;
2805
b53bef84
BG		 2806 boundary =
2807 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2808 seglen = boundary - low;
2809 if (seglen > len)
2810 seglen = len;
2811 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2812 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2813 if (mss) { /* TSO */
2814 (req - rdma_count)->rdma_count = rdma_count + 1;
2815
2816 if (likely(cum_len >= 0)) { /* payload */
2817 int next_is_first, chop;
2818
2819 chop = (cum_len_next > mss);
2820 cum_len_next = cum_len_next % mss;
2821 next_is_first = (cum_len_next == 0);
2822 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2823 flags_next |= next_is_first *
2824 MXGEFW_FLAGS_FIRST;
2825 rdma_count |= -(chop | next_is_first);
2826 rdma_count += chop & !next_is_first;
2827 } else if (likely(cum_len_next >= 0)) { /* header ends */
2828 int small;
2829
2830 rdma_count = -1;
2831 cum_len_next = 0;
2832 seglen = -cum_len;
2833 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2834 flags_next = MXGEFW_FLAGS_TSO_PLD |
2835 MXGEFW_FLAGS_FIRST |
2836 (small * MXGEFW_FLAGS_SMALL);
2837 }
2838 }
0da34b6d
BG		 2839 req->addr_high = high_swapped;
2840 req->addr_low = htonl(low);
40f6cff5 2841 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2842 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2843 req->rdma_count = 1;
2844 req->length = htons(seglen);
2845 req->cksum_offset = cksum_offset;
2846 req->flags = flags | ((cum_len & 1) * odd_flag);
2847
2848 low += seglen;
2849 len -= seglen;
2850 cum_len = cum_len_next;
2851 flags = flags_next;
2852 req++;
2853 count++;
2854 rdma_count++;
4f93fde0
BG		 2855 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2856 if (unlikely(cksum_offset > seglen))
2857 cksum_offset -= seglen;
2858 else
2859 cksum_offset = 0;
2860 }
0da34b6d
BG		 2861 }
2862 if (frag_idx == frag_cnt)
2863 break;
2864
2865 /* map next fragment for DMA */
2866 idx = (count + tx->req) & tx->mask;
2867 frag = &skb_shinfo(skb)->frags[frag_idx];
2868 frag_idx++;
2869 len = frag->size;
2870 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2871 len, PCI_DMA_TODEVICE);
2872 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2873 pci_unmap_len_set(&tx->info[idx], len, len);
2874 }
2875
2876 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2877 if (mss)
2878 do {
2879 req--;
2880 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2881 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2882 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2883 idx = ((count - 1) + tx->req) & tx->mask;
2884 tx->info[idx].last = 1;
e454e7e2 2885 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 2886 /* if using multiple tx queues, make sure NIC polls the
2887 * current slice */
2888 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2889 tx->queue_active = 1;
2890 put_be32(htonl(1), tx->send_go);
8c2f5fa5 2891 mb();
6824a105 2892 mmiowb();
236bb5e6 2893 }
0da34b6d
BG		 2894 tx->pkt_start++;
2895 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2896 tx->stop_queue++;
236bb5e6 2897 netif_tx_stop_queue(netdev_queue);
0da34b6d
BG		 2898 }
2899 dev->trans_start = jiffies;
2900 return 0;
2901
2902abort_linearize:
2903 /* Free any DMA resources we've alloced and clear out the skb
2904 * slot so as to not trip up assertions, and to avoid a
2905 * double-free if linearizing fails */
2906
2907 last_idx = (idx + 1) & tx->mask;
2908 idx = tx->req & tx->mask;
2909 tx->info[idx].skb = NULL;
2910 do {
2911 len = pci_unmap_len(&tx->info[idx], len);
2912 if (len) {
2913 if (tx->info[idx].skb != NULL)
2914 pci_unmap_single(mgp->pdev,
2915 pci_unmap_addr(&tx->info[idx],
2916 bus), len,
2917 PCI_DMA_TODEVICE);
2918 else
2919 pci_unmap_page(mgp->pdev,
2920 pci_unmap_addr(&tx->info[idx],
2921 bus), len,
2922 PCI_DMA_TODEVICE);
2923 pci_unmap_len_set(&tx->info[idx], len, 0);
2924 tx->info[idx].skb = NULL;
2925 }
2926 idx = (idx + 1) & tx->mask;
2927 } while (idx != last_idx);
89114afd 2928 if (skb_is_gso(skb)) {
0da34b6d
BG		 2929 printk(KERN_ERR
2930 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2931 mgp->dev->name);
2932 goto drop;
2933 }
2934
bec0e859 2935 if (skb_linearize(skb))
0da34b6d
BG		 2936 goto drop;
2937
b53bef84 2938 tx->linearized++;
0da34b6d
BG		 2939 goto again;
2940
2941drop:
2942 dev_kfree_skb_any(skb);
b53bef84 2943 ss->stats.tx_dropped += 1;
0da34b6d
BG		 2944 return 0;
2945
2946}
2947
4f93fde0
BG		 2948static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2949{
2950 struct sk_buff *segs, *curr;
b53bef84 2951 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 2952 struct myri10ge_slice_state *ss;
4f93fde0
BG		 2953 int status;
2954
2955 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2956 if (IS_ERR(segs))
4f93fde0
BG		 2957 goto drop;
2958
2959 while (segs) {
2960 curr = segs;
2961 segs = segs->next;
2962 curr->next = NULL;
2963 status = myri10ge_xmit(curr, dev);
2964 if (status != 0) {
2965 dev_kfree_skb_any(curr);
2966 if (segs != NULL) {
2967 curr = segs;
2968 segs = segs->next;
2969 curr->next = NULL;
2970 dev_kfree_skb_any(segs);
2971 }
2972 goto drop;
2973 }
2974 }
2975 dev_kfree_skb_any(skb);
2976 return 0;
2977
2978drop:
d6279c88 2979 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 2980 dev_kfree_skb_any(skb);
d6279c88 2981 ss->stats.tx_dropped += 1;
4f93fde0
BG		 2982 return 0;
2983}
2984
0da34b6d
BG		 2985static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2986{
2987 struct myri10ge_priv *mgp = netdev_priv(dev);
0dcffac1
BG		 2988 struct myri10ge_slice_netstats *slice_stats;
2989 struct net_device_stats *stats = &mgp->stats;
2990 int i;
2991
59081825 2992 spin_lock(&mgp->stats_lock);
0dcffac1
BG		 2993 memset(stats, 0, sizeof(*stats));
2994 for (i = 0; i < mgp->num_slices; i++) {
2995 slice_stats = &mgp->ss[i].stats;
2996 stats->rx_packets += slice_stats->rx_packets;
2997 stats->tx_packets += slice_stats->tx_packets;
2998 stats->rx_bytes += slice_stats->rx_bytes;
2999 stats->tx_bytes += slice_stats->tx_bytes;
3000 stats->rx_dropped += slice_stats->rx_dropped;
3001 stats->tx_dropped += slice_stats->tx_dropped;
3002 }
59081825 3003 spin_unlock(&mgp->stats_lock);
0dcffac1 3004 return stats;
0da34b6d
BG		 3005}
3006
3007static void myri10ge_set_multicast_list(struct net_device *dev)
3008{
b53bef84 3009 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 3010 struct myri10ge_cmd cmd;
85a7ea1b 3011 struct dev_mc_list *mc_list;
6250223e 3012 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 3013 int err;
3014
0da34b6d
BG		 3015 /* can be called from atomic contexts,
3016 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 3017 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3018
3019 /* This firmware is known to not support multicast */
2f76216f 3020 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 3021 return;
3022
3023 /* Disable multicast filtering */
3024
3025 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3026 if (err != 0) {
3027 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
3028 " error status: %d\n", dev->name, err);
3029 goto abort;
3030 }
3031
2f76216f 3032 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 3033 /* request to disable multicast filtering, so quit here */
3034 return;
3035 }
3036
3037 /* Flush the filters */
3038
3039 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3040 &cmd, 1);
3041 if (err != 0) {
3042 printk(KERN_ERR
3043 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
3044 ", error status: %d\n", dev->name, err);
3045 goto abort;
3046 }
3047
3048 /* Walk the multicast list, and add each address */
3049 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 3050 memcpy(data, &mc_list->dmi_addr, 6);
3051 cmd.data0 = ntohl(data[0]);
3052 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 3053 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3054 &cmd, 1);
3055
3056 if (err != 0) {
3057 printk(KERN_ERR "myri10ge: %s: Failed "
3058 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
3059 "%d\t", dev->name, err);
e174961c 3060 printk(KERN_ERR "MAC %pM\n", mc_list->dmi_addr);
85a7ea1b
BG		 3061 goto abort;
3062 }
3063 }
3064 /* Enable multicast filtering */
3065 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3066 if (err != 0) {
3067 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3068 "error status: %d\n", dev->name, err);
3069 goto abort;
3070 }
3071
3072 return;
3073
3074abort:
3075 return;
0da34b6d
BG		 3076}
3077
3078static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3079{
3080 struct sockaddr *sa = addr;
3081 struct myri10ge_priv *mgp = netdev_priv(dev);
3082 int status;
3083
3084 if (!is_valid_ether_addr(sa->sa_data))
3085 return -EADDRNOTAVAIL;
3086
3087 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3088 if (status != 0) {
3089 printk(KERN_ERR
3090 "myri10ge: %s: changing mac address failed with %d\n",
3091 dev->name, status);
3092 return status;
3093 }
3094
3095 /* change the dev structure */
3096 memcpy(dev->dev_addr, sa->sa_data, 6);
3097 return 0;
3098}
3099
3100static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3101{
3102 struct myri10ge_priv *mgp = netdev_priv(dev);
3103 int error = 0;
3104
3105 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3106 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3107 dev->name, new_mtu);
3108 return -EINVAL;
3109 }
3110 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3111 dev->name, dev->mtu, new_mtu);
3112 if (mgp->running) {
3113 /* if we change the mtu on an active device, we must
3114 * reset the device so the firmware sees the change */
3115 myri10ge_close(dev);
3116 dev->mtu = new_mtu;
3117 myri10ge_open(dev);
3118 } else
3119 dev->mtu = new_mtu;
3120
3121 return error;
3122}
3123
3124/*
3125 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3126 * Only do it if the bridge is a root port since we don't want to disturb
3127 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3128 */
3129
0da34b6d
BG		 3130static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3131{
3132 struct pci_dev *bridge = mgp->pdev->bus->self;
3133 struct device *dev = &mgp->pdev->dev;
3134 unsigned cap;
3135 unsigned err_cap;
3136 u16 val;
3137 u8 ext_type;
3138 int ret;
3139
3140 if (!myri10ge_ecrc_enable || !bridge)
3141 return;
3142
3143 /* check that the bridge is a root port */
3144 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3145 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3146 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3147 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3148 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3149 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3150
3151 /* Walk the hierarchy up to the root port
3152 * where ECRC has to be enabled */
3153 do {
eca3fd83 3154 prev_bridge = bridge;
0da34b6d 3155 bridge = bridge->bus->self;
eca3fd83 3156 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3157 dev_err(dev,
3158 "Failed to find root port"
3159 " to force ECRC\n");
3160 return;
3161 }
3162 cap =
3163 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3164 pci_read_config_word(bridge,
3165 cap + PCI_CAP_FLAGS, &val);
3166 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3167 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3168
3169 dev_info(dev,
3170 "Forcing ECRC on non-root port %s"
3171 " (enabling on root port %s)\n",
3172 pci_name(old_bridge), pci_name(bridge));
3173 } else {
3174 dev_err(dev,
3175 "Not enabling ECRC on non-root port %s\n",
3176 pci_name(bridge));
3177 return;
3178 }
3179 }
3180
3181 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3182 if (!cap)
3183 return;
3184
3185 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3186 if (ret) {
3187 dev_err(dev, "failed reading ext-conf-space of %s\n",
3188 pci_name(bridge));
3189 dev_err(dev, "\t pci=nommconf in use? "
3190 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3191 return;
3192 }
3193 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3194 return;
3195
3196 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3197 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3198 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3199}
3200
3201/*
3202 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3203 * when the PCI-E Completion packets are aligned on an 8-byte
3204 * boundary. Some PCI-E chip sets always align Completion packets; on
3205 * the ones that do not, the alignment can be enforced by enabling
3206 * ECRC generation (if supported).
3207 *
3208 * When PCI-E Completion packets are not aligned, it is actually more
3209 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3210 *
3211 * If the driver can neither enable ECRC nor verify that it has
3212 * already been enabled, then it must use a firmware image which works
0dcffac1 3213 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3214 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3215 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3216 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3217 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3218 */
3219
5443e9ea 3220static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3221{
5443e9ea
BG		 3222 struct pci_dev *pdev = mgp->pdev;
3223 struct device *dev = &pdev->dev;
302d242c 3224 int status;
0da34b6d 3225
b53bef84 3226 mgp->tx_boundary = 4096;
5443e9ea
BG		 3227 /*
3228 * Verify the max read request size was set to 4KB
3229 * before trying the test with 4KB.
3230 */
302d242c
BG		 3231 status = pcie_get_readrq(pdev);
3232 if (status < 0) {
5443e9ea
BG		 3233 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3234 goto abort;
3235 }
302d242c
BG		 3236 if (status != 4096) {
3237 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3238 mgp->tx_boundary = 2048;
5443e9ea
BG		 3239 }
3240 /*
3241 * load the optimized firmware (which assumes aligned PCIe
3242 * completions) in order to see if it works on this host.
3243 */
3244 mgp->fw_name = myri10ge_fw_aligned;
0dcffac1 3245 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3246 if (status != 0) {
3247 goto abort;
3248 }
3249
3250 /*
3251 * Enable ECRC if possible
3252 */
3253 myri10ge_enable_ecrc(mgp);
3254
3255 /*
3256 * Run a DMA test which watches for unaligned completions and
3257 * aborts on the first one seen.
3258 */
3259
3260 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3261 if (status == 0)
3262 return; /* keep the aligned firmware */
3263
3264 if (status != -E2BIG)
3265 dev_warn(dev, "DMA test failed: %d\n", status);
3266 if (status == -ENOSYS)
3267 dev_warn(dev, "Falling back to ethp! "
3268 "Please install up to date fw\n");
3269abort:
3270 /* fall back to using the unaligned firmware */
b53bef84 3271 mgp->tx_boundary = 2048;
0da34b6d
BG		 3272 mgp->fw_name = myri10ge_fw_unaligned;
3273
5443e9ea
BG		 3274}
3275
3276static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3277{
2d90b0aa
BG		 3278 int overridden = 0;
3279
0da34b6d 3280 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 3281 int link_width, exp_cap;
3282 u16 lnk;
3283
3284 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3285 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3286 link_width = (lnk >> 4) & 0x3f;
3287
ce7f9368
BG		 3288 /* Check to see if Link is less than 8 or if the
3289 * upstream bridge is known to provide aligned
3290 * completions */
3291 if (link_width < 8) {
3292 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3293 link_width);
b53bef84 3294 mgp->tx_boundary = 4096;
ce7f9368 3295 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 3296 } else {
3297 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3298 }
3299 } else {
3300 if (myri10ge_force_firmware == 1) {
3301 dev_info(&mgp->pdev->dev,
3302 "Assuming aligned completions (forced)\n");
b53bef84 3303 mgp->tx_boundary = 4096;
0da34b6d
BG		 3304 mgp->fw_name = myri10ge_fw_aligned;
3305 } else {
3306 dev_info(&mgp->pdev->dev,
3307 "Assuming unaligned completions (forced)\n");
b53bef84 3308 mgp->tx_boundary = 2048;
0da34b6d
BG		 3309 mgp->fw_name = myri10ge_fw_unaligned;
3310 }
3311 }
3312 if (myri10ge_fw_name != NULL) {
2d90b0aa 3313 overridden = 1;
0da34b6d
BG		 3314 mgp->fw_name = myri10ge_fw_name;
3315 }
2d90b0aa
BG		 3316 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3317 myri10ge_fw_names[mgp->board_number] != NULL &&
3318 strlen(myri10ge_fw_names[mgp->board_number])) {
3319 mgp->fw_name = myri10ge_fw_names[mgp->board_number];
3320 overridden = 1;
3321 }
3322 if (overridden)
3323 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3324 mgp->fw_name);
0da34b6d
BG		 3325}
3326
0da34b6d 3327#ifdef CONFIG_PM
0da34b6d
BG		 3328static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3329{
3330 struct myri10ge_priv *mgp;
3331 struct net_device *netdev;
3332
3333 mgp = pci_get_drvdata(pdev);
3334 if (mgp == NULL)
3335 return -EINVAL;
3336 netdev = mgp->dev;
3337
3338 netif_device_detach(netdev);
3339 if (netif_running(netdev)) {
3340 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3341 rtnl_lock();
3342 myri10ge_close(netdev);
3343 rtnl_unlock();
3344 }
3345 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3346 pci_save_state(pdev);
0da34b6d 3347 pci_disable_device(pdev);
1a63e846
BG		 3348
3349 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3350}
3351
3352static int myri10ge_resume(struct pci_dev *pdev)
3353{
3354 struct myri10ge_priv *mgp;
3355 struct net_device *netdev;
3356 int status;
3357 u16 vendor;
3358
3359 mgp = pci_get_drvdata(pdev);
3360 if (mgp == NULL)
3361 return -EINVAL;
3362 netdev = mgp->dev;
3363 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3364 msleep(5); /* give card time to respond */
3365 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3366 if (vendor == 0xffff) {
3367 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3368 mgp->dev->name);
3369 return -EIO;
3370 }
83f6e152 3371
1a63e846
BG		 3372 status = pci_restore_state(pdev);
3373 if (status)
3374 return status;
4c2248cc
BG		 3375
3376 status = pci_enable_device(pdev);
1a63e846 3377 if (status) {
4c2248cc 3378 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3379 return status;
4c2248cc
BG		 3380 }
3381
0da34b6d
BG		 3382 pci_set_master(pdev);
3383
0da34b6d 3384 myri10ge_reset(mgp);
013b68bf 3385 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3386
3387 /* Save configuration space to be restored if the
3388 * nic resets due to a parity error */
83f6e152 3389 pci_save_state(pdev);
0da34b6d
BG		 3390
3391 if (netif_running(netdev)) {
3392 rtnl_lock();
df30a740 3393 status = myri10ge_open(netdev);
0da34b6d 3394 rtnl_unlock();
df30a740
BG		 3395 if (status != 0)
3396 goto abort_with_enabled;
3397
0da34b6d
BG		 3398 }
3399 netif_device_attach(netdev);
3400
3401 return 0;
3402
4c2248cc
BG		 3403abort_with_enabled:
3404 pci_disable_device(pdev);
0da34b6d
BG		 3405 return -EIO;
3406
3407}
0da34b6d
BG		 3408#endif /* CONFIG_PM */
3409
3410static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3411{
3412 struct pci_dev *pdev = mgp->pdev;
3413 int vs = mgp->vendor_specific_offset;
3414 u32 reboot;
3415
3416 /*enter read32 mode */
3417 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3418
3419 /*read REBOOT_STATUS (0xfffffff0) */
3420 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3421 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3422 return reboot;
3423}
3424
3425/*
3426 * This watchdog is used to check whether the board has suffered
3427 * from a parity error and needs to be recovered.
3428 */
c4028958 3429static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3430{
c4028958 3431 struct myri10ge_priv *mgp =
6250223e 3432 container_of(work, struct myri10ge_priv, watchdog_work);
b53bef84 3433 struct myri10ge_tx_buf *tx;
0da34b6d
BG		 3434 u32 reboot;
3435 int status;
0dcffac1 3436 int i;
0da34b6d
BG		 3437 u16 cmd, vendor;
3438
3439 mgp->watchdog_resets++;
3440 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3441 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3442 /* Bus master DMA disabled? Check to see
3443 * if the card rebooted due to a parity error
3444 * For now, just report it */
3445 reboot = myri10ge_read_reboot(mgp);
3446 printk(KERN_ERR
f181137f
BG		 3447 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3448 mgp->dev->name, reboot,
3449 myri10ge_reset_recover ? " " : " not");
3450 if (myri10ge_reset_recover == 0)
3451 return;
3452
3453 myri10ge_reset_recover--;
3454
0da34b6d
BG		 3455 /*
3456 * A rebooted nic will come back with config space as
3457 * it was after power was applied to PCIe bus.
3458 * Attempt to restore config space which was saved
3459 * when the driver was loaded, or the last time the
3460 * nic was resumed from power saving mode.
3461 */
83f6e152 3462 pci_restore_state(mgp->pdev);
7adda30c
BG		 3463
3464 /* save state again for accounting reasons */
83f6e152 3465 pci_save_state(mgp->pdev);
7adda30c 3466
0da34b6d
BG		 3467 } else {
3468 /* if we get back -1's from our slot, perhaps somebody
3469 * powered off our card. Don't try to reset it in
3470 * this case */
3471 if (cmd == 0xffff) {
3472 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3473 if (vendor == 0xffff) {
3474 printk(KERN_ERR
3475 "myri10ge: %s: device disappeared!\n",
3476 mgp->dev->name);
3477 return;
3478 }
3479 }
3480 /* Perhaps it is a software error. Try to reset */
3481
3482 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3483 mgp->dev->name);
0dcffac1
BG		 3484 for (i = 0; i < mgp->num_slices; i++) {
3485 tx = &mgp->ss[i].tx;
3486 printk(KERN_INFO
236bb5e6
BG		 3487 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3488 mgp->dev->name, i, tx->queue_active, tx->req,
3489 tx->done, tx->pkt_start, tx->pkt_done,
0dcffac1
BG		 3490 (int)ntohl(mgp->ss[i].fw_stats->
3491 send_done_count));
3492 msleep(2000);
3493 printk(KERN_INFO
236bb5e6
BG		 3494 "myri10ge: %s: (%d): %d %d %d %d %d %d\n",
3495 mgp->dev->name, i, tx->queue_active, tx->req,
3496 tx->done, tx->pkt_start, tx->pkt_done,
0dcffac1
BG		 3497 (int)ntohl(mgp->ss[i].fw_stats->
3498 send_done_count));
3499 }
0da34b6d 3500 }
236bb5e6 3501
0da34b6d
BG		 3502 rtnl_lock();
3503 myri10ge_close(mgp->dev);
0dcffac1 3504 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3505 if (status != 0)
3506 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3507 mgp->dev->name);
3508 else
3509 myri10ge_open(mgp->dev);
3510 rtnl_unlock();
3511}
3512
3513/*
3514 * We use our own timer routine rather than relying upon
3515 * netdev->tx_timeout because we have a very large hardware transmit
3516 * queue. Due to the large queue, the netdev->tx_timeout function
3517 * cannot detect a NIC with a parity error in a timely fashion if the
3518 * NIC is lightly loaded.
3519 */
3520static void myri10ge_watchdog_timer(unsigned long arg)
3521{
3522 struct myri10ge_priv *mgp;
b53bef84 3523 struct myri10ge_slice_state *ss;
0dcffac1 3524 int i, reset_needed;
626fda94 3525 u32 rx_pause_cnt;
0da34b6d
BG		 3526
3527 mgp = (struct myri10ge_priv *)arg;
c7dab99b 3528
0dcffac1
BG		 3529 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3530 for (i = 0, reset_needed = 0;
3531 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3532
0dcffac1
BG		 3533 ss = &mgp->ss[i];
3534 if (ss->rx_small.watchdog_needed) {
3535 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3536 mgp->small_bytes + MXGEFW_PAD,
3537 1);
3538 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3539 myri10ge_fill_thresh)
3540 ss->rx_small.watchdog_needed = 0;
3541 }
3542 if (ss->rx_big.watchdog_needed) {
3543 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3544 mgp->big_bytes, 1);
3545 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3546 myri10ge_fill_thresh)
3547 ss->rx_big.watchdog_needed = 0;
3548 }
3549
3550 if (ss->tx.req != ss->tx.done &&
3551 ss->tx.done == ss->watchdog_tx_done &&
3552 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3553 /* nic seems like it might be stuck.. */
3554 if (rx_pause_cnt != mgp->watchdog_pause) {
3555 if (net_ratelimit())
236bb5e6
BG		 3556 printk(KERN_WARNING
3557 "myri10ge %s slice %d:"
0dcffac1 3558 "TX paused, check link partner\n",
236bb5e6 3559 mgp->dev->name, i);
0dcffac1 3560 } else {
236bb5e6
BG		 3561 printk(KERN_WARNING
3562 "myri10ge %s slice %d stuck:",
3563 mgp->dev->name, i);
0dcffac1
BG		 3564 reset_needed = 1;
3565 }
626fda94 3566 }
0dcffac1
BG		 3567 ss->watchdog_tx_done = ss->tx.done;
3568 ss->watchdog_tx_req = ss->tx.req;
626fda94 3569 }
626fda94 3570 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3571
3572 if (reset_needed) {
3573 schedule_work(&mgp->watchdog_work);
3574 } else {
3575 /* rearm timer */
3576 mod_timer(&mgp->watchdog_timer,
3577 jiffies + myri10ge_watchdog_timeout * HZ);
3578 }
0da34b6d
BG		 3579}
3580
77929732
BG		 3581static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3582{
3583 struct myri10ge_slice_state *ss;
3584 struct pci_dev *pdev = mgp->pdev;
3585 size_t bytes;
3586 int i;
3587
3588 if (mgp->ss == NULL)
3589 return;
3590
3591 for (i = 0; i < mgp->num_slices; i++) {
3592 ss = &mgp->ss[i];
3593 if (ss->rx_done.entry != NULL) {
3594 bytes = mgp->max_intr_slots *
3595 sizeof(*ss->rx_done.entry);
3596 dma_free_coherent(&pdev->dev, bytes,
3597 ss->rx_done.entry, ss->rx_done.bus);
3598 ss->rx_done.entry = NULL;
3599 }
3600 if (ss->fw_stats != NULL) {
3601 bytes = sizeof(*ss->fw_stats);
3602 dma_free_coherent(&pdev->dev, bytes,
3603 ss->fw_stats, ss->fw_stats_bus);
3604 ss->fw_stats = NULL;
3605 }
3606 }
3607 kfree(mgp->ss);
3608 mgp->ss = NULL;
3609}
3610
3611static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3612{
3613 struct myri10ge_slice_state *ss;
3614 struct pci_dev *pdev = mgp->pdev;
3615 size_t bytes;
3616 int i;
3617
3618 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3619 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3620 if (mgp->ss == NULL) {
3621 return -ENOMEM;
3622 }
3623
3624 for (i = 0; i < mgp->num_slices; i++) {
3625 ss = &mgp->ss[i];
3626 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3627 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3628 &ss->rx_done.bus,
3629 GFP_KERNEL);
3630 if (ss->rx_done.entry == NULL)
3631 goto abort;
3632 memset(ss->rx_done.entry, 0, bytes);
3633 bytes = sizeof(*ss->fw_stats);
3634 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3635 &ss->fw_stats_bus,
3636 GFP_KERNEL);
3637 if (ss->fw_stats == NULL)
3638 goto abort;
3639 ss->mgp = mgp;
3640 ss->dev = mgp->dev;
3641 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3642 myri10ge_napi_weight);
3643 }
3644 return 0;
3645abort:
3646 myri10ge_free_slices(mgp);
3647 return -ENOMEM;
3648}
3649
3650/*
3651 * This function determines the number of slices supported.
3652 * The number slices is the minumum of the number of CPUS,
3653 * the number of MSI-X irqs supported, the number of slices
3654 * supported by the firmware
3655 */
3656static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3657{
3658 struct myri10ge_cmd cmd;
3659 struct pci_dev *pdev = mgp->pdev;
3660 char *old_fw;
3661 int i, status, ncpus, msix_cap;
3662
3663 mgp->num_slices = 1;
3664 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3665 ncpus = num_online_cpus();
3666
3667 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3668 (myri10ge_max_slices == -1 && ncpus < 2))
3669 return;
3670
3671 /* try to load the slice aware rss firmware */
3672 old_fw = mgp->fw_name;
13b2738c
BG		 3673 if (myri10ge_fw_name != NULL) {
3674 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3675 myri10ge_fw_name);
3676 mgp->fw_name = myri10ge_fw_name;
3677 } else if (old_fw == myri10ge_fw_aligned)
77929732
BG		 3678 mgp->fw_name = myri10ge_fw_rss_aligned;
3679 else
3680 mgp->fw_name = myri10ge_fw_rss_unaligned;
3681 status = myri10ge_load_firmware(mgp, 0);
3682 if (status != 0) {
3683 dev_info(&pdev->dev, "Rss firmware not found\n");
3684 return;
3685 }
3686
3687 /* hit the board with a reset to ensure it is alive */
3688 memset(&cmd, 0, sizeof(cmd));
3689 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3690 if (status != 0) {
3691 dev_err(&mgp->pdev->dev, "failed reset\n");
3692 goto abort_with_fw;
3693 return;
3694 }
3695
3696 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3697
3698 /* tell it the size of the interrupt queues */
3699 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3700 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3701 if (status != 0) {
3702 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3703 goto abort_with_fw;
3704 }
3705
3706 /* ask the maximum number of slices it supports */
3707 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3708 if (status != 0)
3709 goto abort_with_fw;
3710 else
3711 mgp->num_slices = cmd.data0;
3712
3713 /* Only allow multiple slices if MSI-X is usable */
3714 if (!myri10ge_msi) {
3715 goto abort_with_fw;
3716 }
3717
3718 /* if the admin did not specify a limit to how many
3719 * slices we should use, cap it automatically to the
3720 * number of CPUs currently online */
3721 if (myri10ge_max_slices == -1)
3722 myri10ge_max_slices = ncpus;
3723
3724 if (mgp->num_slices > myri10ge_max_slices)
3725 mgp->num_slices = myri10ge_max_slices;
3726
3727 /* Now try to allocate as many MSI-X vectors as we have
3728 * slices. We give up on MSI-X if we can only get a single
3729 * vector. */
3730
3731 mgp->msix_vectors = kzalloc(mgp->num_slices *
3732 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3733 if (mgp->msix_vectors == NULL)
3734 goto disable_msix;
3735 for (i = 0; i < mgp->num_slices; i++) {
3736 mgp->msix_vectors[i].entry = i;
3737 }
3738
3739 while (mgp->num_slices > 1) {
3740 /* make sure it is a power of two */
3741 while (!is_power_of_2(mgp->num_slices))
3742 mgp->num_slices--;
3743 if (mgp->num_slices == 1)
3744 goto disable_msix;
3745 status = pci_enable_msix(pdev, mgp->msix_vectors,
3746 mgp->num_slices);
3747 if (status == 0) {
3748 pci_disable_msix(pdev);
3749 return;
3750 }
3751 if (status > 0)
3752 mgp->num_slices = status;
3753 else
3754 goto disable_msix;
3755 }
3756
3757disable_msix:
3758 if (mgp->msix_vectors != NULL) {
3759 kfree(mgp->msix_vectors);
3760 mgp->msix_vectors = NULL;
3761 }
3762
3763abort_with_fw:
3764 mgp->num_slices = 1;
3765 mgp->fw_name = old_fw;
3766 myri10ge_load_firmware(mgp, 0);
3767}
77929732 3768
8126089f
SH		 3769static const struct net_device_ops myri10ge_netdev_ops = {
3770 .ndo_open = myri10ge_open,
3771 .ndo_stop = myri10ge_close,
3772 .ndo_start_xmit = myri10ge_xmit,
3773 .ndo_get_stats = myri10ge_get_stats,
3774 .ndo_validate_addr = eth_validate_addr,
3775 .ndo_change_mtu = myri10ge_change_mtu,
3776 .ndo_set_multicast_list = myri10ge_set_multicast_list,
3777 .ndo_set_mac_address = myri10ge_set_mac_address,
3778};
3779
0da34b6d
BG		 3780static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3781{
3782 struct net_device *netdev;
3783 struct myri10ge_priv *mgp;
3784 struct device *dev = &pdev->dev;
0da34b6d
BG		 3785 int i;
3786 int status = -ENXIO;
0da34b6d 3787 int dac_enabled;
00b5e505 3788 unsigned hdr_offset, ss_offset;
2d90b0aa 3789 static int board_number;
0da34b6d 3790
236bb5e6 3791 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
0da34b6d
BG		 3792 if (netdev == NULL) {
3793 dev_err(dev, "Could not allocate ethernet device\n");
3794 return -ENOMEM;
3795 }
3796
b245fb67
MH		 3797 SET_NETDEV_DEV(netdev, &pdev->dev);
3798
0da34b6d 3799 mgp = netdev_priv(netdev);
0da34b6d
BG		 3800 mgp->dev = netdev;
3801 mgp->pdev = pdev;
3802 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3803 mgp->pause = myri10ge_flow_control;
3804 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3805 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3806 mgp->board_number = board_number;
0da34b6d
BG		 3807 init_waitqueue_head(&mgp->down_wq);
3808
3809 if (pci_enable_device(pdev)) {
3810 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3811 status = -ENODEV;
3812 goto abort_with_netdev;
3813 }
0da34b6d
BG		 3814
3815 /* Find the vendor-specific cap so we can check
3816 * the reboot register later on */
3817 mgp->vendor_specific_offset
3818 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3819
3820 /* Set our max read request to 4KB */
302d242c 3821 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3822 if (status != 0) {
3823 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3824 status);
e3fd5534 3825 goto abort_with_enabled;
0da34b6d
BG		 3826 }
3827
3828 pci_set_master(pdev);
3829 dac_enabled = 1;
6a35528a 3830 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3831 if (status != 0) {
3832 dac_enabled = 0;
3833 dev_err(&pdev->dev,
898eb71c
JP		 3834 "64-bit pci address mask was refused, "
3835 "trying 32-bit\n");
284901a9 3836 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 3837 }
3838 if (status != 0) {
3839 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 3840 goto abort_with_enabled;
0da34b6d 3841 }
6a35528a 3842 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 3843 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3844 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d 3845 if (mgp->cmd == NULL)
e3fd5534 3846 goto abort_with_enabled;
0da34b6d 3847
0da34b6d
BG		 3848 mgp->board_span = pci_resource_len(pdev, 0);
3849 mgp->iomem_base = pci_resource_start(pdev, 0);
3850 mgp->mtrr = -1;
276e26c3 3851 mgp->wc_enabled = 0;
0da34b6d
BG		 3852#ifdef CONFIG_MTRR
3853 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3854 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3855 if (mgp->mtrr >= 0)
3856 mgp->wc_enabled = 1;
0da34b6d 3857#endif
c7f80993 3858 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3859 if (mgp->sram == NULL) {
3860 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3861 mgp->board_span, mgp->iomem_base);
3862 status = -ENXIO;
c7f80993 3863 goto abort_with_mtrr;
0da34b6d 3864 }
00b5e505
BG		 3865 hdr_offset =
3866 ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3867 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3868 mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3869 if (mgp->sram_size > mgp->board_span ||
3870 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3871 dev_err(&pdev->dev,
3872 "invalid sram_size %dB or board span %ldB\n",
3873 mgp->sram_size, mgp->board_span);
3874 goto abort_with_ioremap;
3875 }
0da34b6d 3876 memcpy_fromio(mgp->eeprom_strings,
00b5e505 3877 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 3878 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3879 status = myri10ge_read_mac_addr(mgp);
3880 if (status)
3881 goto abort_with_ioremap;
3882
3883 for (i = 0; i < ETH_ALEN; i++)
3884 netdev->dev_addr[i] = mgp->mac_addr[i];
3885
5443e9ea
BG		 3886 myri10ge_select_firmware(mgp);
3887
0dcffac1 3888 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3889 if (status != 0) {
3890 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3891 goto abort_with_ioremap;
3892 }
3893 myri10ge_probe_slices(mgp);
3894 status = myri10ge_alloc_slices(mgp);
3895 if (status != 0) {
3896 dev_err(&pdev->dev, "failed to alloc slice state\n");
3897 goto abort_with_firmware;
0da34b6d 3898 }
236bb5e6 3899 netdev->real_num_tx_queues = mgp->num_slices;
0da34b6d
BG		 3900 status = myri10ge_reset(mgp);
3901 if (status != 0) {
3902 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3903 goto abort_with_slices;
0da34b6d 3904 }
5dd2d332 3905#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3906 myri10ge_setup_dca(mgp);
3907#endif
0da34b6d
BG		 3908 pci_set_drvdata(pdev, mgp);
3909 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3910 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3911 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3912 myri10ge_initial_mtu = 68;
8126089f
SH		 3913
3914 netdev->netdev_ops = &myri10ge_netdev_ops;
0da34b6d 3915 netdev->mtu = myri10ge_initial_mtu;
0da34b6d 3916 netdev->base_addr = mgp->iomem_base;
4f93fde0 3917 netdev->features = mgp->features;
236bb5e6 3918
0da34b6d
BG		 3919 if (dac_enabled)
3920 netdev->features |= NETIF_F_HIGHDMA;
3a0c7d2d
BG		 3921 if (myri10ge_lro)
3922 netdev->features |= NETIF_F_LRO;
0da34b6d 3923
21d05db1
BG		 3924 /* make sure we can get an irq, and that MSI can be
3925 * setup (if available). Also ensure netdev->irq
3926 * is set to correct value if MSI is enabled */
3927 status = myri10ge_request_irq(mgp);
3928 if (status != 0)
3929 goto abort_with_firmware;
3930 netdev->irq = pdev->irq;
3931 myri10ge_free_irq(mgp);
3932
0da34b6d
BG		 3933 /* Save configuration space to be restored if the
3934 * nic resets due to a parity error */
83f6e152 3935 pci_save_state(pdev);
0da34b6d
BG		 3936
3937 /* Setup the watchdog timer */
3938 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3939 (unsigned long)mgp);
3940
59081825 3941 spin_lock_init(&mgp->stats_lock);
0da34b6d 3942 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3943 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3944 status = register_netdev(netdev);
3945 if (status != 0) {
3946 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3947 goto abort_with_state;
0da34b6d 3948 }
0dcffac1
BG		 3949 if (mgp->msix_enabled)
3950 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3951 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3952 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3953 else
3954 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3955 mgp->msi_enabled ? "MSI" : "xPIC",
3956 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3957 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d 3958
2d90b0aa 3959 board_number++;
0da34b6d
BG		 3960 return 0;
3961
7adda30c 3962abort_with_state:
83f6e152 3963 pci_restore_state(pdev);
0da34b6d 3964
0dcffac1
BG		 3965abort_with_slices:
3966 myri10ge_free_slices(mgp);
3967
0da34b6d
BG		 3968abort_with_firmware:
3969 myri10ge_dummy_rdma(mgp, 0);
3970
0da34b6d 3971abort_with_ioremap:
0f840011
BG		 3972 if (mgp->mac_addr_string != NULL)
3973 dev_err(&pdev->dev,
3974 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
3975 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 3976 iounmap(mgp->sram);
3977
c7f80993 3978abort_with_mtrr:
0da34b6d
BG		 3979#ifdef CONFIG_MTRR
3980 if (mgp->mtrr >= 0)
3981 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3982#endif
b10c0668
BG		 3983 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3984 mgp->cmd, mgp->cmd_bus);
0da34b6d 3985
e3fd5534
BG		 3986abort_with_enabled:
3987 pci_disable_device(pdev);
0da34b6d 3988
e3fd5534 3989abort_with_netdev:
0da34b6d
BG		 3990 free_netdev(netdev);
3991 return status;
3992}
3993
3994/*
3995 * myri10ge_remove
3996 *
3997 * Does what is necessary to shutdown one Myrinet device. Called
3998 * once for each Myrinet card by the kernel when a module is
3999 * unloaded.
4000 */
4001static void myri10ge_remove(struct pci_dev *pdev)
4002{
4003 struct myri10ge_priv *mgp;
4004 struct net_device *netdev;
0da34b6d
BG		 4005
4006 mgp = pci_get_drvdata(pdev);
4007 if (mgp == NULL)
4008 return;
4009
4010 flush_scheduled_work();
4011 netdev = mgp->dev;
4012 unregister_netdev(netdev);
0da34b6d 4013
5dd2d332 4014#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4015 myri10ge_teardown_dca(mgp);
4016#endif
0da34b6d
BG		 4017 myri10ge_dummy_rdma(mgp, 0);
4018
7adda30c 4019 /* avoid a memory leak */
83f6e152 4020 pci_restore_state(pdev);
7adda30c 4021
0da34b6d
BG		 4022 iounmap(mgp->sram);
4023
4024#ifdef CONFIG_MTRR
4025 if (mgp->mtrr >= 0)
4026 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4027#endif
0dcffac1
BG		 4028 myri10ge_free_slices(mgp);
4029 if (mgp->msix_vectors != NULL)
4030 kfree(mgp->msix_vectors);
b10c0668
BG		 4031 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4032 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 4033
4034 free_netdev(netdev);
e3fd5534 4035 pci_disable_device(pdev);
0da34b6d
BG		 4036 pci_set_drvdata(pdev, NULL);
4037}
4038
b10c0668 4039#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 4040#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 4041
4042static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 4043 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 4044 {PCI_DEVICE
4045 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 4046 {0},
4047};
4048
97131079
BG		 4049MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4050
0da34b6d
BG		 4051static struct pci_driver myri10ge_driver = {
4052 .name = "myri10ge",
4053 .probe = myri10ge_probe,
4054 .remove = myri10ge_remove,
4055 .id_table = myri10ge_pci_tbl,
4056#ifdef CONFIG_PM
4057 .suspend = myri10ge_suspend,
4058 .resume = myri10ge_resume,
4059#endif
4060};
4061
5dd2d332 4062#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4063static int
4064myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4065{
4066 int err = driver_for_each_device(&myri10ge_driver.driver,
4067 NULL, &event,
4068 myri10ge_notify_dca_device);
4069
4070 if (err)
4071 return NOTIFY_BAD;
4072 return NOTIFY_DONE;
4073}
4074
4075static struct notifier_block myri10ge_dca_notifier = {
4076 .notifier_call = myri10ge_notify_dca,
4077 .next = NULL,
4078 .priority = 0,
4079};
4ee2ac51 4080#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4081
0da34b6d
BG		 4082static __init int myri10ge_init_module(void)
4083{
4084 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
4085 MYRI10GE_VERSION_STR);
0dcffac1 4086
236bb5e6 4087 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
0dcffac1
BG		 4088 printk(KERN_ERR
4089 "%s: Illegal rssh hash type %d, defaulting to source port\n",
4090 myri10ge_driver.name, myri10ge_rss_hash);
4091 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4092 }
5dd2d332 4093#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4094 dca_register_notify(&myri10ge_dca_notifier);
4095#endif
236bb5e6
BG		 4096 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4097 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4098
0da34b6d
BG		 4099 return pci_register_driver(&myri10ge_driver);
4100}
4101
4102module_init(myri10ge_init_module);
4103
4104static __exit void myri10ge_cleanup_module(void)
4105{
5dd2d332 4106#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4107 dca_unregister_notify(&myri10ge_dca_notifier);
4108#endif
0da34b6d
BG		 4109 pci_unregister_driver(&myri10ge_driver);
4110}
4111
4112module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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