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[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4a2e612a 4 * Copyright (C) 2005 - 2007 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41#include <linux/tcp.h>
42#include <linux/netdevice.h>
43#include <linux/skbuff.h>
44#include <linux/string.h>
45#include <linux/module.h>
46#include <linux/pci.h>
b10c0668 47#include <linux/dma-mapping.h>
0da34b6d
BG		 48#include <linux/etherdevice.h>
49#include <linux/if_ether.h>
50#include <linux/if_vlan.h>
1e6e9342 51#include <linux/inet_lro.h>
0da34b6d
BG		 52#include <linux/ip.h>
53#include <linux/inet.h>
54#include <linux/in.h>
55#include <linux/ethtool.h>
56#include <linux/firmware.h>
57#include <linux/delay.h>
58#include <linux/version.h>
59#include <linux/timer.h>
60#include <linux/vmalloc.h>
61#include <linux/crc32.h>
62#include <linux/moduleparam.h>
63#include <linux/io.h>
199126a2 64#include <linux/log2.h>
0da34b6d 65#include <net/checksum.h>
1e6e9342
AG		 66#include <net/ip.h>
67#include <net/tcp.h>
0da34b6d
BG		 68#include <asm/byteorder.h>
69#include <asm/io.h>
0da34b6d
BG		 70#include <asm/processor.h>
71#ifdef CONFIG_MTRR
72#include <asm/mtrr.h>
73#endif
74
75#include "myri10ge_mcp.h"
76#include "myri10ge_mcp_gen_header.h"
77
29728637 78#define MYRI10GE_VERSION_STR "1.3.2-1.269"
0da34b6d
BG		 79
80MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81MODULE_AUTHOR("Maintainer: help@myri.com");
82MODULE_VERSION(MYRI10GE_VERSION_STR);
83MODULE_LICENSE("Dual BSD/GPL");
84
85#define MYRI10GE_MAX_ETHER_MTU 9014
86
87#define MYRI10GE_ETH_STOPPED 0
88#define MYRI10GE_ETH_STOPPING 1
89#define MYRI10GE_ETH_STARTING 2
90#define MYRI10GE_ETH_RUNNING 3
91#define MYRI10GE_ETH_OPEN_FAILED 4
92
93#define MYRI10GE_EEPROM_STRINGS_SIZE 256
94#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
1e6e9342
AG		 95#define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96#define MYRI10GE_LRO_MAX_PKTS 64
0da34b6d 97
40f6cff5 98#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 99#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
dd50f336
BG		 101#define MYRI10GE_ALLOC_ORDER 0
102#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
0da34b6d 105struct myri10ge_rx_buffer_state {
dd50f336
BG		 106 struct page *page;
107 int page_offset;
0da34b6d
BG		 108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110};
111
112struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117};
118
119struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123};
124
125struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 130 struct page *page;
131 dma_addr_t bus;
132 int page_offset;
0da34b6d 133 int cnt;
dd50f336 134 int fill_cnt;
0da34b6d
BG		 135 int alloc_fail;
136 int mask; /* number of rx slots -1 */
dd50f336 137 int watchdog_needed;
0da34b6d
BG		 138};
139
140struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
144 char *req_bytes;
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
147 int boundary; /* boundary transmits cannot cross */
148 int req ____cacheline_aligned; /* transmit slots submitted */
149 int pkt_start; /* packets started */
150 int done ____cacheline_aligned; /* transmit slots completed */
151 int pkt_done; /* packets completed */
152};
153
154struct myri10ge_rx_done {
155 struct mcp_slot *entry;
156 dma_addr_t bus;
157 int cnt;
158 int idx;
1e6e9342
AG		 159 struct net_lro_mgr lro_mgr;
160 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
0da34b6d
BG		 161};
162
163struct myri10ge_priv {
164 int running; /* running? */
165 int csum_flag; /* rx_csums? */
166 struct myri10ge_tx_buf tx; /* transmit ring */
167 struct myri10ge_rx_buf rx_small;
168 struct myri10ge_rx_buf rx_big;
169 struct myri10ge_rx_done rx_done;
170 int small_bytes;
dd50f336 171 int big_bytes;
0da34b6d 172 struct net_device *dev;
bea3348e 173 struct napi_struct napi;
0da34b6d
BG		 174 struct net_device_stats stats;
175 u8 __iomem *sram;
176 int sram_size;
177 unsigned long board_span;
178 unsigned long iomem_base;
40f6cff5
AV		 179 __be32 __iomem *irq_claim;
180 __be32 __iomem *irq_deassert;
0da34b6d
BG		 181 char *mac_addr_string;
182 struct mcp_cmd_response *cmd;
183 dma_addr_t cmd_bus;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 struct pci_dev *pdev;
187 int msi_enabled;
40f6cff5 188 __be32 link_state;
0da34b6d
BG		 189 unsigned int rdma_tags_available;
190 int intr_coal_delay;
40f6cff5 191 __be32 __iomem *intr_coal_delay_ptr;
0da34b6d 192 int mtrr;
276e26c3 193 int wc_enabled;
0da34b6d
BG		 194 int wake_queue;
195 int stop_queue;
196 int down_cnt;
197 wait_queue_head_t down_wq;
198 struct work_struct watchdog_work;
199 struct timer_list watchdog_timer;
200 int watchdog_tx_done;
c54772e7 201 int watchdog_tx_req;
626fda94 202 int watchdog_pause;
0da34b6d
BG		 203 int watchdog_resets;
204 int tx_linearized;
205 int pause;
206 char *fw_name;
207 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
208 char fw_version[128];
9dc6f0e7
BG		 209 int fw_ver_major;
210 int fw_ver_minor;
211 int fw_ver_tiny;
212 int adopted_rx_filter_bug;
0da34b6d
BG		 213 u8 mac_addr[6]; /* eeprom mac address */
214 unsigned long serial_number;
215 int vendor_specific_offset;
85a7ea1b 216 int fw_multicast_support;
0da34b6d
BG		 217 u32 read_dma;
218 u32 write_dma;
219 u32 read_write_dma;
c58ac5ca
BG		 220 u32 link_changes;
221 u32 msg_enable;
0da34b6d
BG		 222};
223
224static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
225static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
226
227static char *myri10ge_fw_name = NULL;
228module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
229MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
230
231static int myri10ge_ecrc_enable = 1;
232module_param(myri10ge_ecrc_enable, int, S_IRUGO);
233MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
234
235static int myri10ge_max_intr_slots = 1024;
236module_param(myri10ge_max_intr_slots, int, S_IRUGO);
237MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
238
239static int myri10ge_small_bytes = -1; /* -1 == auto */
240module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
241MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
242
243static int myri10ge_msi = 1; /* enable msi by default */
3621cec5 244module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
0da34b6d
BG		 245MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
246
f761fae1 247static int myri10ge_intr_coal_delay = 75;
0da34b6d
BG		 248module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
249MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
250
251static int myri10ge_flow_control = 1;
252module_param(myri10ge_flow_control, int, S_IRUGO);
253MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
254
255static int myri10ge_deassert_wait = 1;
256module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
257MODULE_PARM_DESC(myri10ge_deassert_wait,
258 "Wait when deasserting legacy interrupts\n");
259
260static int myri10ge_force_firmware = 0;
261module_param(myri10ge_force_firmware, int, S_IRUGO);
262MODULE_PARM_DESC(myri10ge_force_firmware,
263 "Force firmware to assume aligned completions\n");
264
0da34b6d
BG		 265static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
266module_param(myri10ge_initial_mtu, int, S_IRUGO);
267MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
268
269static int myri10ge_napi_weight = 64;
270module_param(myri10ge_napi_weight, int, S_IRUGO);
271MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
272
273static int myri10ge_watchdog_timeout = 1;
274module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
275MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
276
277static int myri10ge_max_irq_loops = 1048576;
278module_param(myri10ge_max_irq_loops, int, S_IRUGO);
279MODULE_PARM_DESC(myri10ge_max_irq_loops,
280 "Set stuck legacy IRQ detection threshold\n");
281
c58ac5ca
BG		 282#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
283
284static int myri10ge_debug = -1; /* defaults above */
285module_param(myri10ge_debug, int, 0);
286MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
287
1e6e9342
AG		 288static int myri10ge_lro = 1;
289module_param(myri10ge_lro, int, S_IRUGO);
290MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload\n");
291
292static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
293module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
294MODULE_PARM_DESC(myri10ge_lro, "Number of LRO packets to be aggregated\n");
295
dd50f336
BG		 296static int myri10ge_fill_thresh = 256;
297module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
298MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
299
f181137f
BG		 300static int myri10ge_reset_recover = 1;
301
f761fae1 302static int myri10ge_wcfifo = 0;
6ebc087a
BG		 303module_param(myri10ge_wcfifo, int, S_IRUGO);
304MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
305
0da34b6d
BG		 306#define MYRI10GE_FW_OFFSET 1024*1024
307#define MYRI10GE_HIGHPART_TO_U32(X) \
308(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
309#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
310
311#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
312
2f76216f
BG		 313static void myri10ge_set_multicast_list(struct net_device *dev);
314
6250223e 315static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 316{
6250223e 317 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 318}
319
0da34b6d
BG		 320static int
321myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
322 struct myri10ge_cmd *data, int atomic)
323{
324 struct mcp_cmd *buf;
325 char buf_bytes[sizeof(*buf) + 8];
326 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 327 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 328 u32 dma_low, dma_high, result, value;
329 int sleep_total = 0;
330
331 /* ensure buf is aligned to 8 bytes */
332 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
333
334 buf->data0 = htonl(data->data0);
335 buf->data1 = htonl(data->data1);
336 buf->data2 = htonl(data->data2);
337 buf->cmd = htonl(cmd);
338 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
339 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
340
341 buf->response_addr.low = htonl(dma_low);
342 buf->response_addr.high = htonl(dma_high);
40f6cff5 343 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 344 mb();
345 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
346
347 /* wait up to 15ms. Longest command is the DMA benchmark,
348 * which is capped at 5ms, but runs from a timeout handler
349 * that runs every 7.8ms. So a 15ms timeout leaves us with
350 * a 2.2ms margin
351 */
352 if (atomic) {
353 /* if atomic is set, do not sleep,
354 * and try to get the completion quickly
355 * (1ms will be enough for those commands) */
356 for (sleep_total = 0;
357 sleep_total < 1000
40f6cff5 358 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 359 sleep_total += 10)
360 udelay(10);
361 } else {
362 /* use msleep for most command */
363 for (sleep_total = 0;
364 sleep_total < 15
40f6cff5 365 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 366 sleep_total++)
367 msleep(1);
368 }
369
370 result = ntohl(response->result);
371 value = ntohl(response->data);
372 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
373 if (result == 0) {
374 data->data0 = value;
375 return 0;
85a7ea1b
BG		 376 } else if (result == MXGEFW_CMD_UNKNOWN) {
377 return -ENOSYS;
5443e9ea
BG		 378 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
379 return -E2BIG;
0da34b6d
BG		 380 } else {
381 dev_err(&mgp->pdev->dev,
382 "command %d failed, result = %d\n",
383 cmd, result);
384 return -ENXIO;
385 }
386 }
387
388 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
389 cmd, result);
390 return -EAGAIN;
391}
392
393/*
394 * The eeprom strings on the lanaiX have the format
395 * SN=x\0
396 * MAC=x:x:x:x:x:x\0
397 * PT:ddd mmm xx xx:xx:xx xx\0
398 * PV:ddd mmm xx xx:xx:xx xx\0
399 */
400static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
401{
402 char *ptr, *limit;
403 int i;
404
405 ptr = mgp->eeprom_strings;
406 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
407
408 while (*ptr != '\0' && ptr < limit) {
409 if (memcmp(ptr, "MAC=", 4) == 0) {
410 ptr += 4;
411 mgp->mac_addr_string = ptr;
412 for (i = 0; i < 6; i++) {
413 if ((ptr + 2) > limit)
414 goto abort;
415 mgp->mac_addr[i] =
416 simple_strtoul(ptr, &ptr, 16);
417 ptr += 1;
418 }
419 }
420 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
421 ptr += 3;
422 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
423 }
424 while (ptr < limit && *ptr++) ;
425 }
426
427 return 0;
428
429abort:
430 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
431 return -ENXIO;
432}
433
434/*
435 * Enable or disable periodic RDMAs from the host to make certain
436 * chipsets resend dropped PCIe messages
437 */
438
439static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
440{
441 char __iomem *submit;
40f6cff5 442 __be32 buf[16];
0da34b6d
BG		 443 u32 dma_low, dma_high;
444 int i;
445
446 /* clear confirmation addr */
447 mgp->cmd->data = 0;
448 mb();
449
450 /* send a rdma command to the PCIe engine, and wait for the
451 * response in the confirmation address. The firmware should
452 * write a -1 there to indicate it is alive and well
453 */
454 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
455 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
456
457 buf[0] = htonl(dma_high); /* confirm addr MSW */
458 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 459 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 460 buf[3] = htonl(dma_high); /* dummy addr MSW */
461 buf[4] = htonl(dma_low); /* dummy addr LSW */
462 buf[5] = htonl(enable); /* enable? */
463
e700f9f4 464 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 465
466 myri10ge_pio_copy(submit, &buf, sizeof(buf));
467 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
468 msleep(1);
469 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
470 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
471 (enable ? "enable" : "disable"));
472}
473
474static int
475myri10ge_validate_firmware(struct myri10ge_priv *mgp,
476 struct mcp_gen_header *hdr)
477{
478 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 479
480 /* check firmware type */
481 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
482 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
483 return -EINVAL;
484 }
485
486 /* save firmware version for ethtool */
487 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
488
9dc6f0e7
BG		 489 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
490 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 491
9dc6f0e7
BG		 492 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
493 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 494 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
495 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
496 MXGEFW_VERSION_MINOR);
497 return -EINVAL;
498 }
499 return 0;
500}
501
502static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
503{
504 unsigned crc, reread_crc;
505 const struct firmware *fw;
506 struct device *dev = &mgp->pdev->dev;
507 struct mcp_gen_header *hdr;
508 size_t hdr_offset;
509 int status;
e454358a 510 unsigned i;
0da34b6d
BG		 511
512 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
513 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
514 mgp->fw_name);
515 status = -EINVAL;
516 goto abort_with_nothing;
517 }
518
519 /* check size */
520
521 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
522 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
523 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
524 status = -EINVAL;
525 goto abort_with_fw;
526 }
527
528 /* check id */
40f6cff5 529 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 530 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
531 dev_err(dev, "Bad firmware file\n");
532 status = -EINVAL;
533 goto abort_with_fw;
534 }
535 hdr = (void *)(fw->data + hdr_offset);
536
537 status = myri10ge_validate_firmware(mgp, hdr);
538 if (status != 0)
539 goto abort_with_fw;
540
541 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 542 for (i = 0; i < fw->size; i += 256) {
543 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
544 fw->data + i,
545 min(256U, (unsigned)(fw->size - i)));
546 mb();
547 readb(mgp->sram);
b10c0668 548 }
0da34b6d
BG		 549 /* corruption checking is good for parity recovery and buggy chipset */
550 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
551 reread_crc = crc32(~0, fw->data, fw->size);
552 if (crc != reread_crc) {
553 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
554 (unsigned)fw->size, reread_crc, crc);
555 status = -EIO;
556 goto abort_with_fw;
557 }
558 *size = (u32) fw->size;
559
560abort_with_fw:
561 release_firmware(fw);
562
563abort_with_nothing:
564 return status;
565}
566
567static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
568{
569 struct mcp_gen_header *hdr;
570 struct device *dev = &mgp->pdev->dev;
571 const size_t bytes = sizeof(struct mcp_gen_header);
572 size_t hdr_offset;
573 int status;
574
575 /* find running firmware header */
576 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
577
578 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
579 dev_err(dev, "Running firmware has bad header offset (%d)\n",
580 (int)hdr_offset);
581 return -EIO;
582 }
583
584 /* copy header of running firmware from SRAM to host memory to
585 * validate firmware */
586 hdr = kmalloc(bytes, GFP_KERNEL);
587 if (hdr == NULL) {
588 dev_err(dev, "could not malloc firmware hdr\n");
589 return -ENOMEM;
590 }
591 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
592 status = myri10ge_validate_firmware(mgp, hdr);
593 kfree(hdr);
9dc6f0e7
BG		 594
595 /* check to see if adopted firmware has bug where adopting
596 * it will cause broadcasts to be filtered unless the NIC
597 * is kept in ALLMULTI mode */
598 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
599 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
600 mgp->adopted_rx_filter_bug = 1;
601 dev_warn(dev, "Adopting fw %d.%d.%d: "
602 "working around rx filter bug\n",
603 mgp->fw_ver_major, mgp->fw_ver_minor,
604 mgp->fw_ver_tiny);
605 }
0da34b6d
BG		 606 return status;
607}
608
609static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
610{
611 char __iomem *submit;
40f6cff5 612 __be32 buf[16];
0da34b6d
BG		 613 u32 dma_low, dma_high, size;
614 int status, i;
615
b10c0668 616 size = 0;
0da34b6d
BG		 617 status = myri10ge_load_hotplug_firmware(mgp, &size);
618 if (status) {
619 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
620
621 /* Do not attempt to adopt firmware if there
622 * was a bad crc */
623 if (status == -EIO)
624 return status;
625
626 status = myri10ge_adopt_running_firmware(mgp);
627 if (status != 0) {
628 dev_err(&mgp->pdev->dev,
629 "failed to adopt running firmware\n");
630 return status;
631 }
632 dev_info(&mgp->pdev->dev,
633 "Successfully adopted running firmware\n");
634 if (mgp->tx.boundary == 4096) {
635 dev_warn(&mgp->pdev->dev,
636 "Using firmware currently running on NIC"
637 ". For optimal\n");
638 dev_warn(&mgp->pdev->dev,
639 "performance consider loading optimized "
640 "firmware\n");
641 dev_warn(&mgp->pdev->dev, "via hotplug\n");
642 }
643
644 mgp->fw_name = "adopted";
645 mgp->tx.boundary = 2048;
646 return status;
647 }
648
649 /* clear confirmation addr */
650 mgp->cmd->data = 0;
651 mb();
652
653 /* send a reload command to the bootstrap MCP, and wait for the
654 * response in the confirmation address. The firmware should
655 * write a -1 there to indicate it is alive and well
656 */
657 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
658 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
659
660 buf[0] = htonl(dma_high); /* confirm addr MSW */
661 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 662 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 663
664 /* FIX: All newest firmware should un-protect the bottom of
665 * the sram before handoff. However, the very first interfaces
666 * do not. Therefore the handoff copy must skip the first 8 bytes
667 */
668 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
669 buf[4] = htonl(size - 8); /* length of code */
670 buf[5] = htonl(8); /* where to copy to */
671 buf[6] = htonl(0); /* where to jump to */
672
e700f9f4 673 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 674
675 myri10ge_pio_copy(submit, &buf, sizeof(buf));
676 mb();
677 msleep(1);
678 mb();
679 i = 0;
680 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
681 msleep(1);
682 i++;
683 }
684 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
685 dev_err(&mgp->pdev->dev, "handoff failed\n");
686 return -ENXIO;
687 }
688 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
9a71db72 689 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 690
691 return 0;
692}
693
694static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
695{
696 struct myri10ge_cmd cmd;
697 int status;
698
699 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
700 | (addr[2] << 8) | addr[3]);
701
702 cmd.data1 = ((addr[4] << 8) | (addr[5]));
703
704 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
705 return status;
706}
707
708static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
709{
710 struct myri10ge_cmd cmd;
711 int status, ctl;
712
713 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
714 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
715
716 if (status) {
717 printk(KERN_ERR
718 "myri10ge: %s: Failed to set flow control mode\n",
719 mgp->dev->name);
720 return status;
721 }
722 mgp->pause = pause;
723 return 0;
724}
725
726static void
727myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
728{
729 struct myri10ge_cmd cmd;
730 int status, ctl;
731
732 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
733 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
734 if (status)
735 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
736 mgp->dev->name);
737}
738
0d6ac257 739static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 740{
741 struct myri10ge_cmd cmd;
742 int status;
0da34b6d 743 u32 len;
34fdccea
BG		 744 struct page *dmatest_page;
745 dma_addr_t dmatest_bus;
0d6ac257
BG		 746 char *test = " ";
747
748 dmatest_page = alloc_page(GFP_KERNEL);
749 if (!dmatest_page)
750 return -ENOMEM;
751 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
752 DMA_BIDIRECTIONAL);
753
754 /* Run a small DMA test.
755 * The magic multipliers to the length tell the firmware
756 * to do DMA read, write, or read+write tests. The
757 * results are returned in cmd.data0. The upper 16
758 * bits or the return is the number of transfers completed.
759 * The lower 16 bits is the time in 0.5us ticks that the
760 * transfers took to complete.
761 */
762
763 len = mgp->tx.boundary;
764
765 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
766 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
767 cmd.data2 = len * 0x10000;
768 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
769 if (status != 0) {
770 test = "read";
771 goto abort;
772 }
773 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
774 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
775 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
776 cmd.data2 = len * 0x1;
777 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
778 if (status != 0) {
779 test = "write";
780 goto abort;
781 }
782 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
783
784 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
785 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
786 cmd.data2 = len * 0x10001;
787 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
788 if (status != 0) {
789 test = "read/write";
790 goto abort;
791 }
792 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
793 (cmd.data0 & 0xffff);
794
795abort:
796 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
797 put_page(dmatest_page);
798
799 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
800 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
801 test, status);
802
803 return status;
804}
805
806static int myri10ge_reset(struct myri10ge_priv *mgp)
807{
808 struct myri10ge_cmd cmd;
809 int status;
810 size_t bytes;
0da34b6d
BG		 811
812 /* try to send a reset command to the card to see if it
813 * is alive */
814 memset(&cmd, 0, sizeof(cmd));
815 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
816 if (status != 0) {
817 dev_err(&mgp->pdev->dev, "failed reset\n");
818 return -ENXIO;
819 }
0d6ac257
BG		 820
821 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0da34b6d
BG		 822
823 /* Now exchange information about interrupts */
824
825 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
826 memset(mgp->rx_done.entry, 0, bytes);
827 cmd.data0 = (u32) bytes;
828 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
829 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
830 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
831 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
832
833 status |=
834 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
40f6cff5 835 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
df30a740
BG		 836 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
837 &cmd, 0);
838 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 839
0da34b6d
BG		 840 status |= myri10ge_send_cmd
841 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 842 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 843 if (status != 0) {
844 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
845 return status;
846 }
40f6cff5 847 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 848
0da34b6d
BG		 849 memset(mgp->rx_done.entry, 0, bytes);
850
851 /* reset mcp/driver shared state back to 0 */
852 mgp->tx.req = 0;
853 mgp->tx.done = 0;
854 mgp->tx.pkt_start = 0;
855 mgp->tx.pkt_done = 0;
856 mgp->rx_big.cnt = 0;
857 mgp->rx_small.cnt = 0;
858 mgp->rx_done.idx = 0;
859 mgp->rx_done.cnt = 0;
c58ac5ca 860 mgp->link_changes = 0;
0da34b6d 861 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 862 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 863 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 864 return status;
865}
866
867static inline void
868myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
869 struct mcp_kreq_ether_recv *src)
870{
40f6cff5 871 __be32 low;
0da34b6d
BG		 872
873 low = src->addr_low;
40f6cff5 874 src->addr_low = htonl(DMA_32BIT_MASK);
e67bda55
BG		 875 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
876 mb();
877 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 878 mb();
879 src->addr_low = low;
40f6cff5 880 put_be32(low, &dst->addr_low);
0da34b6d
BG		 881 mb();
882}
883
40f6cff5 884static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 885{
886 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
887
40f6cff5 888 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 889 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
890 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
891 skb->csum = hw_csum;
84fa7933 892 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 893 }
894}
895
dd50f336
BG		 896static inline void
897myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
898 struct skb_frag_struct *rx_frags, int len, int hlen)
899{
900 struct skb_frag_struct *skb_frags;
901
902 skb->len = skb->data_len = len;
903 skb->truesize = len + sizeof(struct sk_buff);
904 /* attach the page(s) */
905
906 skb_frags = skb_shinfo(skb)->frags;
907 while (len > 0) {
908 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
909 len -= rx_frags->size;
910 skb_frags++;
911 rx_frags++;
912 skb_shinfo(skb)->nr_frags++;
913 }
914
915 /* pskb_may_pull is not available in irq context, but
916 * skb_pull() (for ether_pad and eth_type_trans()) requires
917 * the beginning of the packet in skb_headlen(), move it
918 * manually */
27d7ff46 919 skb_copy_to_linear_data(skb, va, hlen);
dd50f336
BG		 920 skb_shinfo(skb)->frags[0].page_offset += hlen;
921 skb_shinfo(skb)->frags[0].size -= hlen;
922 skb->data_len -= hlen;
923 skb->tail += hlen;
924 skb_pull(skb, MXGEFW_PAD);
925}
926
927static void
928myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
929 int bytes, int watchdog)
930{
931 struct page *page;
932 int idx;
933
934 if (unlikely(rx->watchdog_needed && !watchdog))
935 return;
936
937 /* try to refill entire ring */
938 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
939 idx = rx->fill_cnt & rx->mask;
ae8509b1 940 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 941 /* we can use part of previous page */
942 get_page(rx->page);
943 } else {
944 /* we need a new page */
945 page =
946 alloc_pages(GFP_ATOMIC | __GFP_COMP,
947 MYRI10GE_ALLOC_ORDER);
948 if (unlikely(page == NULL)) {
949 if (rx->fill_cnt - rx->cnt < 16)
950 rx->watchdog_needed = 1;
951 return;
952 }
953 rx->page = page;
954 rx->page_offset = 0;
955 rx->bus = pci_map_page(mgp->pdev, page, 0,
956 MYRI10GE_ALLOC_SIZE,
957 PCI_DMA_FROMDEVICE);
958 }
959 rx->info[idx].page = rx->page;
960 rx->info[idx].page_offset = rx->page_offset;
961 /* note that this is the address of the start of the
962 * page */
963 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
964 rx->shadow[idx].addr_low =
965 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
966 rx->shadow[idx].addr_high =
967 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
968
969 /* start next packet on a cacheline boundary */
970 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 971
972#if MYRI10GE_ALLOC_SIZE > 4096
973 /* don't cross a 4KB boundary */
974 if ((rx->page_offset >> 12) !=
975 ((rx->page_offset + bytes - 1) >> 12))
976 rx->page_offset = (rx->page_offset + 4096) & ~4095;
977#endif
dd50f336
BG		 978 rx->fill_cnt++;
979
980 /* copy 8 descriptors to the firmware at a time */
981 if ((idx & 7) == 7) {
982 if (rx->wc_fifo == NULL)
983 myri10ge_submit_8rx(&rx->lanai[idx - 7],
984 &rx->shadow[idx - 7]);
985 else {
986 mb();
987 myri10ge_pio_copy(rx->wc_fifo,
988 &rx->shadow[idx - 7], 64);
989 }
990 }
991 }
992}
993
994static inline void
995myri10ge_unmap_rx_page(struct pci_dev *pdev,
996 struct myri10ge_rx_buffer_state *info, int bytes)
997{
998 /* unmap the recvd page if we're the only or last user of it */
999 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1000 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1001 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1002 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1003 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1004 }
1005}
1006
1007#define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1008 * page into an skb */
1009
1010static inline int
52ea6fb3
BG		 1011myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1012 int bytes, int len, __wsum csum)
dd50f336
BG		 1013{
1014 struct sk_buff *skb;
1015 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1016 int i, idx, hlen, remainder;
1017 struct pci_dev *pdev = mgp->pdev;
1018 struct net_device *dev = mgp->dev;
1019 u8 *va;
1020
1021 len += MXGEFW_PAD;
1022 idx = rx->cnt & rx->mask;
1023 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1024 prefetch(va);
1025 /* Fill skb_frag_struct(s) with data from our receive */
1026 for (i = 0, remainder = len; remainder > 0; i++) {
1027 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1028 rx_frags[i].page = rx->info[idx].page;
1029 rx_frags[i].page_offset = rx->info[idx].page_offset;
1030 if (remainder < MYRI10GE_ALLOC_SIZE)
1031 rx_frags[i].size = remainder;
1032 else
1033 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1034 rx->cnt++;
1035 idx = rx->cnt & rx->mask;
1036 remainder -= MYRI10GE_ALLOC_SIZE;
1037 }
1038
1e6e9342
AG		 1039 if (mgp->csum_flag && myri10ge_lro) {
1040 rx_frags[0].page_offset += MXGEFW_PAD;
1041 rx_frags[0].size -= MXGEFW_PAD;
1042 len -= MXGEFW_PAD;
1043 lro_receive_frags(&mgp->rx_done.lro_mgr, rx_frags,
1044 len, len, (void *)(unsigned long)csum, csum);
1045 return 1;
1046 }
1047
dd50f336
BG		 1048 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1049
e636b2ea
BG		 1050 /* allocate an skb to attach the page(s) to. This is done
1051 * after trying LRO, so as to avoid skb allocation overheads */
dd50f336
BG		 1052
1053 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1054 if (unlikely(skb == NULL)) {
1055 mgp->stats.rx_dropped++;
1056 do {
1057 i--;
1058 put_page(rx_frags[i].page);
1059 } while (i != 0);
1060 return 0;
1061 }
1062
1063 /* Attach the pages to the skb, and trim off any padding */
1064 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1065 if (skb_shinfo(skb)->frags[0].size <= 0) {
1066 put_page(skb_shinfo(skb)->frags[0].page);
1067 skb_shinfo(skb)->nr_frags = 0;
1068 }
1069 skb->protocol = eth_type_trans(skb, dev);
dd50f336
BG		 1070
1071 if (mgp->csum_flag) {
1072 if ((skb->protocol == htons(ETH_P_IP)) ||
1073 (skb->protocol == htons(ETH_P_IPV6))) {
1074 skb->csum = csum;
1075 skb->ip_summed = CHECKSUM_COMPLETE;
1076 } else
1077 myri10ge_vlan_ip_csum(skb, csum);
1078 }
1079 netif_receive_skb(skb);
1080 dev->last_rx = jiffies;
1081 return 1;
1082}
1083
0da34b6d
BG		 1084static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1085{
1086 struct pci_dev *pdev = mgp->pdev;
1087 struct myri10ge_tx_buf *tx = &mgp->tx;
1088 struct sk_buff *skb;
1089 int idx, len;
0da34b6d
BG		 1090
1091 while (tx->pkt_done != mcp_index) {
1092 idx = tx->done & tx->mask;
1093 skb = tx->info[idx].skb;
1094
1095 /* Mark as free */
1096 tx->info[idx].skb = NULL;
1097 if (tx->info[idx].last) {
1098 tx->pkt_done++;
1099 tx->info[idx].last = 0;
1100 }
1101 tx->done++;
1102 len = pci_unmap_len(&tx->info[idx], len);
1103 pci_unmap_len_set(&tx->info[idx], len, 0);
1104 if (skb) {
1105 mgp->stats.tx_bytes += skb->len;
1106 mgp->stats.tx_packets++;
1107 dev_kfree_skb_irq(skb);
1108 if (len)
1109 pci_unmap_single(pdev,
1110 pci_unmap_addr(&tx->info[idx],
1111 bus), len,
1112 PCI_DMA_TODEVICE);
1113 } else {
1114 if (len)
1115 pci_unmap_page(pdev,
1116 pci_unmap_addr(&tx->info[idx],
1117 bus), len,
1118 PCI_DMA_TODEVICE);
1119 }
0da34b6d
BG		 1120 }
1121 /* start the queue if we've stopped it */
1122 if (netif_queue_stopped(mgp->dev)
1123 && tx->req - tx->done < (tx->mask >> 1)) {
1124 mgp->wake_queue++;
1125 netif_wake_queue(mgp->dev);
1126 }
1127}
1128
bea3348e 1129static inline int myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int budget)
0da34b6d
BG		 1130{
1131 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1132 unsigned long rx_bytes = 0;
1133 unsigned long rx_packets = 0;
1134 unsigned long rx_ok;
1135
1136 int idx = rx_done->idx;
1137 int cnt = rx_done->cnt;
bea3348e 1138 int work_done = 0;
0da34b6d 1139 u16 length;
40f6cff5 1140 __wsum checksum;
0da34b6d 1141
bea3348e 1142 while (rx_done->entry[idx].length != 0 && work_done++ < budget) {
0da34b6d
BG		 1143 length = ntohs(rx_done->entry[idx].length);
1144 rx_done->entry[idx].length = 0;
40f6cff5 1145 checksum = csum_unfold(rx_done->entry[idx].checksum);
0da34b6d 1146 if (length <= mgp->small_bytes)
52ea6fb3
BG		 1147 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1148 mgp->small_bytes,
1149 length, checksum);
0da34b6d 1150 else
52ea6fb3
BG		 1151 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1152 mgp->big_bytes,
1153 length, checksum);
0da34b6d
BG		 1154 rx_packets += rx_ok;
1155 rx_bytes += rx_ok * (unsigned long)length;
1156 cnt++;
1157 idx = cnt & (myri10ge_max_intr_slots - 1);
0da34b6d
BG		 1158 }
1159 rx_done->idx = idx;
1160 rx_done->cnt = cnt;
1161 mgp->stats.rx_packets += rx_packets;
1162 mgp->stats.rx_bytes += rx_bytes;
c7dab99b 1163
1e6e9342
AG		 1164 if (myri10ge_lro)
1165 lro_flush_all(&rx_done->lro_mgr);
1166
c7dab99b
BG		 1167 /* restock receive rings if needed */
1168 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1169 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1170 mgp->small_bytes + MXGEFW_PAD, 0);
1171 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1172 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1173
bea3348e 1174 return work_done;
0da34b6d
BG		 1175}
1176
1177static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1178{
1179 struct mcp_irq_data *stats = mgp->fw_stats;
1180
1181 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1182 unsigned link_up = ntohl(stats->link_up);
1183 if (mgp->link_state != link_up) {
1184 mgp->link_state = link_up;
1185
1186 if (mgp->link_state == MXGEFW_LINK_UP) {
c58ac5ca
BG		 1187 if (netif_msg_link(mgp))
1188 printk(KERN_INFO
1189 "myri10ge: %s: link up\n",
1190 mgp->dev->name);
0da34b6d 1191 netif_carrier_on(mgp->dev);
c58ac5ca 1192 mgp->link_changes++;
0da34b6d 1193 } else {
c58ac5ca
BG		 1194 if (netif_msg_link(mgp))
1195 printk(KERN_INFO
798a95db
BG		 1196 "myri10ge: %s: link %s\n",
1197 mgp->dev->name,
1198 (link_up == MXGEFW_LINK_MYRINET ?
1199 "mismatch (Myrinet detected)" :
1200 "down"));
0da34b6d 1201 netif_carrier_off(mgp->dev);
c58ac5ca 1202 mgp->link_changes++;
0da34b6d
BG		 1203 }
1204 }
1205 if (mgp->rdma_tags_available !=
1206 ntohl(mgp->fw_stats->rdma_tags_available)) {
1207 mgp->rdma_tags_available =
1208 ntohl(mgp->fw_stats->rdma_tags_available);
1209 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1210 "%d tags left\n", mgp->dev->name,
1211 mgp->rdma_tags_available);
1212 }
1213 mgp->down_cnt += stats->link_down;
1214 if (stats->link_down)
1215 wake_up(&mgp->down_wq);
1216 }
1217}
1218
bea3348e 1219static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1220{
e636b2ea
BG		 1221 struct myri10ge_priv *mgp =
1222 container_of(napi, struct myri10ge_priv, napi);
bea3348e 1223 struct net_device *netdev = mgp->dev;
0da34b6d 1224 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
bea3348e 1225 int work_done;
0da34b6d
BG		 1226
1227 /* process as many rx events as NAPI will allow */
bea3348e 1228 work_done = myri10ge_clean_rx_done(mgp, budget);
0da34b6d
BG		 1229
1230 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
bea3348e 1231 netif_rx_complete(netdev, napi);
40f6cff5 1232 put_be32(htonl(3), mgp->irq_claim);
0da34b6d 1233 }
bea3348e 1234 return work_done;
0da34b6d
BG		 1235}
1236
7d12e780 1237static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d
BG		 1238{
1239 struct myri10ge_priv *mgp = arg;
1240 struct mcp_irq_data *stats = mgp->fw_stats;
1241 struct myri10ge_tx_buf *tx = &mgp->tx;
1242 u32 send_done_count;
1243 int i;
1244
1245 /* make sure it is our IRQ, and that the DMA has finished */
1246 if (unlikely(!stats->valid))
1247 return (IRQ_NONE);
1248
1249 /* low bit indicates receives are present, so schedule
1250 * napi poll handler */
1251 if (stats->valid & 1)
bea3348e 1252 netif_rx_schedule(mgp->dev, &mgp->napi);
0da34b6d
BG		 1253
1254 if (!mgp->msi_enabled) {
40f6cff5 1255 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1256 if (!myri10ge_deassert_wait)
1257 stats->valid = 0;
1258 mb();
1259 } else
1260 stats->valid = 0;
1261
1262 /* Wait for IRQ line to go low, if using INTx */
1263 i = 0;
1264 while (1) {
1265 i++;
1266 /* check for transmit completes and receives */
1267 send_done_count = ntohl(stats->send_done_count);
1268 if (send_done_count != tx->pkt_done)
1269 myri10ge_tx_done(mgp, (int)send_done_count);
1270 if (unlikely(i > myri10ge_max_irq_loops)) {
1271 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1272 mgp->dev->name);
1273 stats->valid = 0;
1274 schedule_work(&mgp->watchdog_work);
1275 }
1276 if (likely(stats->valid == 0))
1277 break;
1278 cpu_relax();
1279 barrier();
1280 }
1281
1282 myri10ge_check_statblock(mgp);
1283
40f6cff5 1284 put_be32(htonl(3), mgp->irq_claim + 1);
0da34b6d
BG		 1285 return (IRQ_HANDLED);
1286}
1287
1288static int
1289myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1290{
1291 cmd->autoneg = AUTONEG_DISABLE;
1292 cmd->speed = SPEED_10000;
1293 cmd->duplex = DUPLEX_FULL;
1294 return 0;
1295}
1296
1297static void
1298myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1299{
1300 struct myri10ge_priv *mgp = netdev_priv(netdev);
1301
1302 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1303 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1304 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1305 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1306}
1307
1308static int
1309myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1310{
1311 struct myri10ge_priv *mgp = netdev_priv(netdev);
1312 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1313 return 0;
1314}
1315
1316static int
1317myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1318{
1319 struct myri10ge_priv *mgp = netdev_priv(netdev);
1320
1321 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1322 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1323 return 0;
1324}
1325
1326static void
1327myri10ge_get_pauseparam(struct net_device *netdev,
1328 struct ethtool_pauseparam *pause)
1329{
1330 struct myri10ge_priv *mgp = netdev_priv(netdev);
1331
1332 pause->autoneg = 0;
1333 pause->rx_pause = mgp->pause;
1334 pause->tx_pause = mgp->pause;
1335}
1336
1337static int
1338myri10ge_set_pauseparam(struct net_device *netdev,
1339 struct ethtool_pauseparam *pause)
1340{
1341 struct myri10ge_priv *mgp = netdev_priv(netdev);
1342
1343 if (pause->tx_pause != mgp->pause)
1344 return myri10ge_change_pause(mgp, pause->tx_pause);
1345 if (pause->rx_pause != mgp->pause)
1346 return myri10ge_change_pause(mgp, pause->tx_pause);
1347 if (pause->autoneg != 0)
1348 return -EINVAL;
1349 return 0;
1350}
1351
1352static void
1353myri10ge_get_ringparam(struct net_device *netdev,
1354 struct ethtool_ringparam *ring)
1355{
1356 struct myri10ge_priv *mgp = netdev_priv(netdev);
1357
1358 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1359 ring->rx_max_pending = mgp->rx_big.mask + 1;
1360 ring->rx_jumbo_max_pending = 0;
1361 ring->tx_max_pending = mgp->rx_small.mask + 1;
1362 ring->rx_mini_pending = ring->rx_mini_max_pending;
1363 ring->rx_pending = ring->rx_max_pending;
1364 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1365 ring->tx_pending = ring->tx_max_pending;
1366}
1367
1368static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1369{
1370 struct myri10ge_priv *mgp = netdev_priv(netdev);
1371 if (mgp->csum_flag)
1372 return 1;
1373 else
1374 return 0;
1375}
1376
1377static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1378{
1379 struct myri10ge_priv *mgp = netdev_priv(netdev);
1380 if (csum_enabled)
1381 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1382 else
1383 mgp->csum_flag = 0;
1384 return 0;
1385}
1386
1387static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1388 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1389 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1390 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1391 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1392 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1393 "tx_heartbeat_errors", "tx_window_errors",
1394 /* device-specific stats */
2c1a1088 1395 "tx_boundary", "WC", "irq", "MSI",
0da34b6d
BG		 1396 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1397 "serial_number", "tx_pkt_start", "tx_pkt_done",
1398 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1399 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
c58ac5ca 1400 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1401 "dropped_link_error_or_filtered",
1402 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1403 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1404 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1e6e9342
AG		 1405 "dropped_no_big_buffer", "LRO aggregated", "LRO flushed",
1406 "LRO avg aggr", "LRO no_desc"
0da34b6d
BG		 1407};
1408
1409#define MYRI10GE_NET_STATS_LEN 21
1410#define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1411
1412static void
1413myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1414{
1415 switch (stringset) {
1416 case ETH_SS_STATS:
1417 memcpy(data, *myri10ge_gstrings_stats,
1418 sizeof(myri10ge_gstrings_stats));
1419 break;
1420 }
1421}
1422
b9f2c044 1423static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1424{
b9f2c044
JG		 1425 switch (sset) {
1426 case ETH_SS_STATS:
1427 return MYRI10GE_STATS_LEN;
1428 default:
1429 return -EOPNOTSUPP;
1430 }
0da34b6d
BG		 1431}
1432
1433static void
1434myri10ge_get_ethtool_stats(struct net_device *netdev,
1435 struct ethtool_stats *stats, u64 * data)
1436{
1437 struct myri10ge_priv *mgp = netdev_priv(netdev);
1438 int i;
1439
1440 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1441 data[i] = ((unsigned long *)&mgp->stats)[i];
1442
2c1a1088 1443 data[i++] = (unsigned int)mgp->tx.boundary;
276e26c3 1444 data[i++] = (unsigned int)mgp->wc_enabled;
2c1a1088
BG		 1445 data[i++] = (unsigned int)mgp->pdev->irq;
1446 data[i++] = (unsigned int)mgp->msi_enabled;
0da34b6d
BG		 1447 data[i++] = (unsigned int)mgp->read_dma;
1448 data[i++] = (unsigned int)mgp->write_dma;
1449 data[i++] = (unsigned int)mgp->read_write_dma;
1450 data[i++] = (unsigned int)mgp->serial_number;
1451 data[i++] = (unsigned int)mgp->tx.pkt_start;
1452 data[i++] = (unsigned int)mgp->tx.pkt_done;
1453 data[i++] = (unsigned int)mgp->tx.req;
1454 data[i++] = (unsigned int)mgp->tx.done;
1455 data[i++] = (unsigned int)mgp->rx_small.cnt;
1456 data[i++] = (unsigned int)mgp->rx_big.cnt;
1457 data[i++] = (unsigned int)mgp->wake_queue;
1458 data[i++] = (unsigned int)mgp->stop_queue;
1459 data[i++] = (unsigned int)mgp->watchdog_resets;
1460 data[i++] = (unsigned int)mgp->tx_linearized;
c58ac5ca 1461 data[i++] = (unsigned int)mgp->link_changes;
0da34b6d
BG		 1462 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1463 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1464 data[i++] =
1465 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
cee505db
BG		 1466 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_pause);
1467 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_phy);
1468 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_bad_crc32);
1469 data[i++] =
1470 (unsigned int)ntohl(mgp->fw_stats->dropped_unicast_filtered);
85a7ea1b
BG		 1471 data[i++] =
1472 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
0da34b6d
BG		 1473 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1474 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1475 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1476 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1e6e9342
AG		 1477 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated;
1478 data[i++] = mgp->rx_done.lro_mgr.stats.flushed;
1479 if (mgp->rx_done.lro_mgr.stats.flushed)
1480 data[i++] = mgp->rx_done.lro_mgr.stats.aggregated /
1481 mgp->rx_done.lro_mgr.stats.flushed;
1482 else
1483 data[i++] = 0;
1484 data[i++] = mgp->rx_done.lro_mgr.stats.no_desc;
0da34b6d
BG		 1485}
1486
c58ac5ca
BG		 1487static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1488{
1489 struct myri10ge_priv *mgp = netdev_priv(netdev);
1490 mgp->msg_enable = value;
1491}
1492
1493static u32 myri10ge_get_msglevel(struct net_device *netdev)
1494{
1495 struct myri10ge_priv *mgp = netdev_priv(netdev);
1496 return mgp->msg_enable;
1497}
1498
7282d491 1499static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1500 .get_settings = myri10ge_get_settings,
1501 .get_drvinfo = myri10ge_get_drvinfo,
1502 .get_coalesce = myri10ge_get_coalesce,
1503 .set_coalesce = myri10ge_set_coalesce,
1504 .get_pauseparam = myri10ge_get_pauseparam,
1505 .set_pauseparam = myri10ge_set_pauseparam,
1506 .get_ringparam = myri10ge_get_ringparam,
1507 .get_rx_csum = myri10ge_get_rx_csum,
1508 .set_rx_csum = myri10ge_set_rx_csum,
b10c0668 1509 .set_tx_csum = ethtool_op_set_tx_hw_csum,
0da34b6d 1510 .set_sg = ethtool_op_set_sg,
0da34b6d 1511 .set_tso = ethtool_op_set_tso,
6ffdd071 1512 .get_link = ethtool_op_get_link,
0da34b6d 1513 .get_strings = myri10ge_get_strings,
b9f2c044 1514 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1515 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1516 .set_msglevel = myri10ge_set_msglevel,
1517 .get_msglevel = myri10ge_get_msglevel
0da34b6d
BG		 1518};
1519
1520static int myri10ge_allocate_rings(struct net_device *dev)
1521{
1522 struct myri10ge_priv *mgp;
1523 struct myri10ge_cmd cmd;
1524 int tx_ring_size, rx_ring_size;
1525 int tx_ring_entries, rx_ring_entries;
1526 int i, status;
1527 size_t bytes;
1528
1529 mgp = netdev_priv(dev);
1530
1531 /* get ring sizes */
1532
1533 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1534 tx_ring_size = cmd.data0;
1535 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1536 if (status != 0)
1537 return status;
0da34b6d
BG		 1538 rx_ring_size = cmd.data0;
1539
1540 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1541 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1542 mgp->tx.mask = tx_ring_entries - 1;
1543 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1544
355c7265
BG		 1545 status = -ENOMEM;
1546
0da34b6d
BG		 1547 /* allocate the host shadow rings */
1548
1549 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1550 * sizeof(*mgp->tx.req_list);
1551 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1552 if (mgp->tx.req_bytes == NULL)
1553 goto abort_with_nothing;
1554
1555 /* ensure req_list entries are aligned to 8 bytes */
1556 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1557 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1558
1559 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1560 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1561 if (mgp->rx_small.shadow == NULL)
1562 goto abort_with_tx_req_bytes;
1563
1564 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1565 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1566 if (mgp->rx_big.shadow == NULL)
1567 goto abort_with_rx_small_shadow;
1568
1569 /* allocate the host info rings */
1570
1571 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1572 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1573 if (mgp->tx.info == NULL)
1574 goto abort_with_rx_big_shadow;
1575
1576 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1577 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1578 if (mgp->rx_small.info == NULL)
1579 goto abort_with_tx_info;
1580
1581 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1582 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1583 if (mgp->rx_big.info == NULL)
1584 goto abort_with_rx_small_info;
1585
1586 /* Fill the receive rings */
c7dab99b
BG		 1587 mgp->rx_big.cnt = 0;
1588 mgp->rx_small.cnt = 0;
1589 mgp->rx_big.fill_cnt = 0;
1590 mgp->rx_small.fill_cnt = 0;
1591 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1592 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1593 mgp->rx_small.watchdog_needed = 0;
1594 mgp->rx_big.watchdog_needed = 0;
1595 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1596 mgp->small_bytes + MXGEFW_PAD, 0);
0da34b6d 1597
c7dab99b
BG		 1598 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1599 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1600 dev->name, mgp->rx_small.fill_cnt);
1601 goto abort_with_rx_small_ring;
0da34b6d
BG		 1602 }
1603
c7dab99b
BG		 1604 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1605 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1606 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1607 dev->name, mgp->rx_big.fill_cnt);
1608 goto abort_with_rx_big_ring;
0da34b6d
BG		 1609 }
1610
1611 return 0;
1612
1613abort_with_rx_big_ring:
c7dab99b
BG		 1614 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1615 int idx = i & mgp->rx_big.mask;
1616 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1617 mgp->big_bytes);
1618 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1619 }
1620
1621abort_with_rx_small_ring:
c7dab99b
BG		 1622 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1623 int idx = i & mgp->rx_small.mask;
1624 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1625 mgp->small_bytes + MXGEFW_PAD);
1626 put_page(mgp->rx_small.info[idx].page);
0da34b6d 1627 }
c7dab99b 1628
0da34b6d
BG		 1629 kfree(mgp->rx_big.info);
1630
1631abort_with_rx_small_info:
1632 kfree(mgp->rx_small.info);
1633
1634abort_with_tx_info:
1635 kfree(mgp->tx.info);
1636
1637abort_with_rx_big_shadow:
1638 kfree(mgp->rx_big.shadow);
1639
1640abort_with_rx_small_shadow:
1641 kfree(mgp->rx_small.shadow);
1642
1643abort_with_tx_req_bytes:
1644 kfree(mgp->tx.req_bytes);
1645 mgp->tx.req_bytes = NULL;
1646 mgp->tx.req_list = NULL;
1647
1648abort_with_nothing:
1649 return status;
1650}
1651
1652static void myri10ge_free_rings(struct net_device *dev)
1653{
1654 struct myri10ge_priv *mgp;
1655 struct sk_buff *skb;
1656 struct myri10ge_tx_buf *tx;
1657 int i, len, idx;
1658
1659 mgp = netdev_priv(dev);
1660
c7dab99b
BG		 1661 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1662 idx = i & mgp->rx_big.mask;
1663 if (i == mgp->rx_big.fill_cnt - 1)
1664 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1665 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1666 mgp->big_bytes);
1667 put_page(mgp->rx_big.info[idx].page);
0da34b6d
BG		 1668 }
1669
c7dab99b
BG		 1670 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1671 idx = i & mgp->rx_small.mask;
1672 if (i == mgp->rx_small.fill_cnt - 1)
1673 mgp->rx_small.info[idx].page_offset =
1674 MYRI10GE_ALLOC_SIZE;
1675 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1676 mgp->small_bytes + MXGEFW_PAD);
1677 put_page(mgp->rx_small.info[idx].page);
1678 }
0da34b6d
BG		 1679 tx = &mgp->tx;
1680 while (tx->done != tx->req) {
1681 idx = tx->done & tx->mask;
1682 skb = tx->info[idx].skb;
1683
1684 /* Mark as free */
1685 tx->info[idx].skb = NULL;
1686 tx->done++;
1687 len = pci_unmap_len(&tx->info[idx], len);
1688 pci_unmap_len_set(&tx->info[idx], len, 0);
1689 if (skb) {
1690 mgp->stats.tx_dropped++;
1691 dev_kfree_skb_any(skb);
1692 if (len)
1693 pci_unmap_single(mgp->pdev,
1694 pci_unmap_addr(&tx->info[idx],
1695 bus), len,
1696 PCI_DMA_TODEVICE);
1697 } else {
1698 if (len)
1699 pci_unmap_page(mgp->pdev,
1700 pci_unmap_addr(&tx->info[idx],
1701 bus), len,
1702 PCI_DMA_TODEVICE);
1703 }
1704 }
1705 kfree(mgp->rx_big.info);
1706
1707 kfree(mgp->rx_small.info);
1708
1709 kfree(mgp->tx.info);
1710
1711 kfree(mgp->rx_big.shadow);
1712
1713 kfree(mgp->rx_small.shadow);
1714
1715 kfree(mgp->tx.req_bytes);
1716 mgp->tx.req_bytes = NULL;
1717 mgp->tx.req_list = NULL;
1718}
1719
df30a740
BG		 1720static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1721{
1722 struct pci_dev *pdev = mgp->pdev;
1723 int status;
1724
1725 if (myri10ge_msi) {
1726 status = pci_enable_msi(pdev);
1727 if (status != 0)
1728 dev_err(&pdev->dev,
1729 "Error %d setting up MSI; falling back to xPIC\n",
1730 status);
1731 else
1732 mgp->msi_enabled = 1;
1733 } else {
1734 mgp->msi_enabled = 0;
1735 }
1736 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1737 mgp->dev->name, mgp);
1738 if (status != 0) {
1739 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1740 if (mgp->msi_enabled)
1741 pci_disable_msi(pdev);
1742 }
1743 return status;
1744}
1745
1746static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1747{
1748 struct pci_dev *pdev = mgp->pdev;
1749
1750 free_irq(pdev->irq, mgp);
1751 if (mgp->msi_enabled)
1752 pci_disable_msi(pdev);
1753}
1754
1e6e9342
AG		 1755static int
1756myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1757 void **ip_hdr, void **tcpudp_hdr,
1758 u64 * hdr_flags, void *priv)
1759{
1760 struct ethhdr *eh;
1761 struct vlan_ethhdr *veh;
1762 struct iphdr *iph;
1763 u8 *va = page_address(frag->page) + frag->page_offset;
1764 unsigned long ll_hlen;
1765 __wsum csum = (__wsum) (unsigned long)priv;
1766
1767 /* find the mac header, aborting if not IPv4 */
1768
1769 eh = (struct ethhdr *)va;
1770 *mac_hdr = eh;
1771 ll_hlen = ETH_HLEN;
1772 if (eh->h_proto != htons(ETH_P_IP)) {
1773 if (eh->h_proto == htons(ETH_P_8021Q)) {
1774 veh = (struct vlan_ethhdr *)va;
1775 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1776 return -1;
1777
1778 ll_hlen += VLAN_HLEN;
1779
1780 /*
1781 * HW checksum starts ETH_HLEN bytes into
1782 * frame, so we must subtract off the VLAN
1783 * header's checksum before csum can be used
1784 */
1785 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1786 VLAN_HLEN, 0));
1787 } else {
1788 return -1;
1789 }
1790 }
1791 *hdr_flags = LRO_IPV4;
1792
1793 iph = (struct iphdr *)(va + ll_hlen);
1794 *ip_hdr = iph;
1795 if (iph->protocol != IPPROTO_TCP)
1796 return -1;
1797 *hdr_flags |= LRO_TCP;
1798 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1799
1800 /* verify the IP checksum */
1801 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1802 return -1;
1803
1804 /* verify the checksum */
1805 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1806 ntohs(iph->tot_len) - (iph->ihl << 2),
1807 IPPROTO_TCP, csum)))
1808 return -1;
1809
1810 return 0;
1811}
1812
0da34b6d
BG		 1813static int myri10ge_open(struct net_device *dev)
1814{
1815 struct myri10ge_priv *mgp;
1816 struct myri10ge_cmd cmd;
1e6e9342 1817 struct net_lro_mgr *lro_mgr;
0da34b6d
BG		 1818 int status, big_pow2;
1819
1820 mgp = netdev_priv(dev);
1821
1822 if (mgp->running != MYRI10GE_ETH_STOPPED)
1823 return -EBUSY;
1824
1825 mgp->running = MYRI10GE_ETH_STARTING;
1826 status = myri10ge_reset(mgp);
1827 if (status != 0) {
1828 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
df30a740 1829 goto abort_with_nothing;
0da34b6d
BG		 1830 }
1831
df30a740
BG		 1832 status = myri10ge_request_irq(mgp);
1833 if (status != 0)
1834 goto abort_with_nothing;
1835
0da34b6d
BG		 1836 /* decide what small buffer size to use. For good TCP rx
1837 * performance, it is important to not receive 1514 byte
1838 * frames into jumbo buffers, as it confuses the socket buffer
1839 * accounting code, leading to drops and erratic performance.
1840 */
1841
1842 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 1843 /* enough for a TCP header */
1844 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1845 ? (128 - MXGEFW_PAD)
1846 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 1847 else
de3c4507
BG		 1848 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1849 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 1850
1851 /* Override the small buffer size? */
1852 if (myri10ge_small_bytes > 0)
1853 mgp->small_bytes = myri10ge_small_bytes;
1854
0da34b6d
BG		 1855 /* get the lanai pointers to the send and receive rings */
1856
1857 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1858 mgp->tx.lanai =
1859 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1860
1861 status |=
1862 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1863 mgp->rx_small.lanai =
1864 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1865
1866 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1867 mgp->rx_big.lanai =
1868 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1869
1870 if (status != 0) {
1871 printk(KERN_ERR
1872 "myri10ge: %s: failed to get ring sizes or locations\n",
1873 dev->name);
1874 mgp->running = MYRI10GE_ETH_STOPPED;
df30a740 1875 goto abort_with_irq;
0da34b6d
BG		 1876 }
1877
276e26c3 1878 if (myri10ge_wcfifo && mgp->wc_enabled) {
e700f9f4
BG		 1879 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1880 mgp->rx_small.wc_fifo =
1881 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1882 mgp->rx_big.wc_fifo =
1883 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
0da34b6d
BG		 1884 } else {
1885 mgp->tx.wc_fifo = NULL;
1886 mgp->rx_small.wc_fifo = NULL;
1887 mgp->rx_big.wc_fifo = NULL;
1888 }
1889
0da34b6d
BG		 1890 /* Firmware needs the big buff size as a power of 2. Lie and
1891 * tell him the buffer is larger, because we only use 1
1892 * buffer/pkt, and the mtu will prevent overruns.
1893 */
13348bee 1894 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 1895 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 1896 while (!is_power_of_2(big_pow2))
c7dab99b 1897 big_pow2++;
13348bee 1898 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 1899 } else {
1900 big_pow2 = MYRI10GE_ALLOC_SIZE;
1901 mgp->big_bytes = big_pow2;
1902 }
1903
1904 status = myri10ge_allocate_rings(dev);
1905 if (status != 0)
df30a740 1906 goto abort_with_irq;
0da34b6d
BG		 1907
1908 /* now give firmware buffers sizes, and MTU */
1909 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1910 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1911 cmd.data0 = mgp->small_bytes;
1912 status |=
1913 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1914 cmd.data0 = big_pow2;
1915 status |=
1916 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1917 if (status) {
1918 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1919 dev->name);
1920 goto abort_with_rings;
1921 }
1922
1923 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1924 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
85a7ea1b
BG		 1925 cmd.data2 = sizeof(struct mcp_irq_data);
1926 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1927 if (status == -ENOSYS) {
1928 dma_addr_t bus = mgp->fw_stats_bus;
1929 bus += offsetof(struct mcp_irq_data, send_done_count);
1930 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1931 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1932 status = myri10ge_send_cmd(mgp,
1933 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1934 &cmd, 0);
1935 /* Firmware cannot support multicast without STATS_DMA_V2 */
1936 mgp->fw_multicast_support = 0;
1937 } else {
1938 mgp->fw_multicast_support = 1;
1939 }
0da34b6d
BG		 1940 if (status) {
1941 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1942 dev->name);
1943 goto abort_with_rings;
1944 }
1945
40f6cff5 1946 mgp->link_state = htonl(~0U);
0da34b6d
BG		 1947 mgp->rdma_tags_available = 15;
1948
1e6e9342
AG		 1949 lro_mgr = &mgp->rx_done.lro_mgr;
1950 lro_mgr->dev = dev;
1951 lro_mgr->features = LRO_F_NAPI;
1952 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
1953 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
1954 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
1955 lro_mgr->lro_arr = mgp->rx_done.lro_desc;
1956 lro_mgr->get_frag_header = myri10ge_get_frag_header;
1957 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
1958 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
1959 lro_mgr->max_aggr = MAX_SKB_FRAGS;
1960
bea3348e 1961 napi_enable(&mgp->napi); /* must happen prior to any irq */
0da34b6d
BG		 1962
1963 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1964 if (status) {
1965 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1966 dev->name);
1967 goto abort_with_rings;
1968 }
1969
1970 mgp->wake_queue = 0;
1971 mgp->stop_queue = 0;
1972 mgp->running = MYRI10GE_ETH_RUNNING;
1973 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1974 add_timer(&mgp->watchdog_timer);
1975 netif_wake_queue(dev);
1976 return 0;
1977
1978abort_with_rings:
1979 myri10ge_free_rings(dev);
1980
df30a740
BG		 1981abort_with_irq:
1982 myri10ge_free_irq(mgp);
1983
0da34b6d
BG		 1984abort_with_nothing:
1985 mgp->running = MYRI10GE_ETH_STOPPED;
1986 return -ENOMEM;
1987}
1988
1989static int myri10ge_close(struct net_device *dev)
1990{
1991 struct myri10ge_priv *mgp;
1992 struct myri10ge_cmd cmd;
1993 int status, old_down_cnt;
1994
1995 mgp = netdev_priv(dev);
1996
1997 if (mgp->running != MYRI10GE_ETH_RUNNING)
1998 return 0;
1999
2000 if (mgp->tx.req_bytes == NULL)
2001 return 0;
2002
2003 del_timer_sync(&mgp->watchdog_timer);
2004 mgp->running = MYRI10GE_ETH_STOPPING;
bea3348e 2005 napi_disable(&mgp->napi);
0da34b6d
BG		 2006 netif_carrier_off(dev);
2007 netif_stop_queue(dev);
2008 old_down_cnt = mgp->down_cnt;
2009 mb();
2010 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2011 if (status)
2012 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2013 dev->name);
2014
2015 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2016 if (old_down_cnt == mgp->down_cnt)
2017 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2018
2019 netif_tx_disable(dev);
df30a740 2020 myri10ge_free_irq(mgp);
0da34b6d
BG		 2021 myri10ge_free_rings(dev);
2022
2023 mgp->running = MYRI10GE_ETH_STOPPED;
2024 return 0;
2025}
2026
2027/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2028 * backwards one at a time and handle ring wraps */
2029
2030static inline void
2031myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2032 struct mcp_kreq_ether_send *src, int cnt)
2033{
2034 int idx, starting_slot;
2035 starting_slot = tx->req;
2036 while (cnt > 1) {
2037 cnt--;
2038 idx = (starting_slot + cnt) & tx->mask;
2039 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2040 mb();
2041 }
2042}
2043
2044/*
2045 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2046 * at most 32 bytes at a time, so as to avoid involving the software
2047 * pio handler in the nic. We re-write the first segment's flags
2048 * to mark them valid only after writing the entire chain.
2049 */
2050
2051static inline void
2052myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2053 int cnt)
2054{
2055 int idx, i;
2056 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2057 struct mcp_kreq_ether_send *srcp;
2058 u8 last_flags;
2059
2060 idx = tx->req & tx->mask;
2061
2062 last_flags = src->flags;
2063 src->flags = 0;
2064 mb();
2065 dst = dstp = &tx->lanai[idx];
2066 srcp = src;
2067
2068 if ((idx + cnt) < tx->mask) {
2069 for (i = 0; i < (cnt - 1); i += 2) {
2070 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2071 mb(); /* force write every 32 bytes */
2072 srcp += 2;
2073 dstp += 2;
2074 }
2075 } else {
2076 /* submit all but the first request, and ensure
2077 * that it is submitted below */
2078 myri10ge_submit_req_backwards(tx, src, cnt);
2079 i = 0;
2080 }
2081 if (i < cnt) {
2082 /* submit the first request */
2083 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2084 mb(); /* barrier before setting valid flag */
2085 }
2086
2087 /* re-write the last 32-bits with the valid flags */
2088 src->flags = last_flags;
40f6cff5 2089 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2090 tx->req += cnt;
2091 mb();
2092}
2093
2094static inline void
2095myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2096 struct mcp_kreq_ether_send *src, int cnt)
2097{
2098 tx->req += cnt;
2099 mb();
2100 while (cnt >= 4) {
2101 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2102 mb();
2103 src += 4;
2104 cnt -= 4;
2105 }
2106 if (cnt > 0) {
2107 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2108 * needs to be so that we don't overrun it */
e700f9f4
BG		 2109 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2110 src, 64);
0da34b6d
BG		 2111 mb();
2112 }
2113}
2114
2115/*
2116 * Transmit a packet. We need to split the packet so that a single
2117 * segment does not cross myri10ge->tx.boundary, so this makes segment
2118 * counting tricky. So rather than try to count segments up front, we
2119 * just give up if there are too few segments to hold a reasonably
2120 * fragmented packet currently available. If we run
2121 * out of segments while preparing a packet for DMA, we just linearize
2122 * it and try again.
2123 */
2124
2125static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2126{
2127 struct myri10ge_priv *mgp = netdev_priv(dev);
2128 struct mcp_kreq_ether_send *req;
2129 struct myri10ge_tx_buf *tx = &mgp->tx;
2130 struct skb_frag_struct *frag;
2131 dma_addr_t bus;
40f6cff5
AV		 2132 u32 low;
2133 __be32 high_swapped;
0da34b6d
BG		 2134 unsigned int len;
2135 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2136 u16 pseudo_hdr_offset, cksum_offset;
2137 int cum_len, seglen, boundary, rdma_count;
2138 u8 flags, odd_flag;
2139
2140again:
2141 req = tx->req_list;
2142 avail = tx->mask - 1 - (tx->req - tx->done);
2143
2144 mss = 0;
2145 max_segments = MXGEFW_MAX_SEND_DESC;
2146
917690cd 2147 if (skb_is_gso(skb)) {
7967168c 2148 mss = skb_shinfo(skb)->gso_size;
917690cd 2149 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2150 }
0da34b6d
BG		 2151
2152 if ((unlikely(avail < max_segments))) {
2153 /* we are out of transmit resources */
2154 mgp->stop_queue++;
2155 netif_stop_queue(dev);
2156 return 1;
2157 }
2158
2159 /* Setup checksum offloading, if needed */
2160 cksum_offset = 0;
2161 pseudo_hdr_offset = 0;
2162 odd_flag = 0;
2163 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2164 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2165 cksum_offset = skb_transport_offset(skb);
ff1dcadb 2166 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2167 /* If the headers are excessively large, then we must
2168 * fall back to a software checksum */
2169 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
84fa7933 2170 if (skb_checksum_help(skb))
0da34b6d
BG		 2171 goto drop;
2172 cksum_offset = 0;
2173 pseudo_hdr_offset = 0;
2174 } else {
0da34b6d
BG		 2175 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2176 flags |= MXGEFW_FLAGS_CKSUM;
2177 }
2178 }
2179
2180 cum_len = 0;
2181
0da34b6d
BG		 2182 if (mss) { /* TSO */
2183 /* this removes any CKSUM flag from before */
2184 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2185
2186 /* negative cum_len signifies to the
2187 * send loop that we are still in the
2188 * header portion of the TSO packet.
2189 * TSO header must be at most 134 bytes long */
ab6a5bb6 2190 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d
BG		 2191
2192 /* for TSO, pseudo_hdr_offset holds mss.
2193 * The firmware figures out where to put
2194 * the checksum by parsing the header. */
40f6cff5 2195 pseudo_hdr_offset = mss;
0da34b6d 2196 } else
0da34b6d
BG		 2197 /* Mark small packets, and pad out tiny packets */
2198 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2199 flags |= MXGEFW_FLAGS_SMALL;
2200
2201 /* pad frames to at least ETH_ZLEN bytes */
2202 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 2203 if (skb_padto(skb, ETH_ZLEN)) {
0da34b6d
BG		 2204 /* The packet is gone, so we must
2205 * return 0 */
2206 mgp->stats.tx_dropped += 1;
2207 return 0;
2208 }
2209 /* adjust the len to account for the zero pad
2210 * so that the nic can know how long it is */
2211 skb->len = ETH_ZLEN;
2212 }
2213 }
2214
2215 /* map the skb for DMA */
2216 len = skb->len - skb->data_len;
2217 idx = tx->req & tx->mask;
2218 tx->info[idx].skb = skb;
2219 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2220 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2221 pci_unmap_len_set(&tx->info[idx], len, len);
2222
2223 frag_cnt = skb_shinfo(skb)->nr_frags;
2224 frag_idx = 0;
2225 count = 0;
2226 rdma_count = 0;
2227
2228 /* "rdma_count" is the number of RDMAs belonging to the
2229 * current packet BEFORE the current send request. For
2230 * non-TSO packets, this is equal to "count".
2231 * For TSO packets, rdma_count needs to be reset
2232 * to 0 after a segment cut.
2233 *
2234 * The rdma_count field of the send request is
2235 * the number of RDMAs of the packet starting at
2236 * that request. For TSO send requests with one ore more cuts
2237 * in the middle, this is the number of RDMAs starting
2238 * after the last cut in the request. All previous
2239 * segments before the last cut implicitly have 1 RDMA.
2240 *
2241 * Since the number of RDMAs is not known beforehand,
2242 * it must be filled-in retroactively - after each
2243 * segmentation cut or at the end of the entire packet.
2244 */
2245
2246 while (1) {
2247 /* Break the SKB or Fragment up into pieces which
2248 * do not cross mgp->tx.boundary */
2249 low = MYRI10GE_LOWPART_TO_U32(bus);
2250 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2251 while (len) {
2252 u8 flags_next;
2253 int cum_len_next;
2254
2255 if (unlikely(count == max_segments))
2256 goto abort_linearize;
2257
2258 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2259 seglen = boundary - low;
2260 if (seglen > len)
2261 seglen = len;
2262 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2263 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2264 if (mss) { /* TSO */
2265 (req - rdma_count)->rdma_count = rdma_count + 1;
2266
2267 if (likely(cum_len >= 0)) { /* payload */
2268 int next_is_first, chop;
2269
2270 chop = (cum_len_next > mss);
2271 cum_len_next = cum_len_next % mss;
2272 next_is_first = (cum_len_next == 0);
2273 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2274 flags_next |= next_is_first *
2275 MXGEFW_FLAGS_FIRST;
2276 rdma_count |= -(chop | next_is_first);
2277 rdma_count += chop & !next_is_first;
2278 } else if (likely(cum_len_next >= 0)) { /* header ends */
2279 int small;
2280
2281 rdma_count = -1;
2282 cum_len_next = 0;
2283 seglen = -cum_len;
2284 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2285 flags_next = MXGEFW_FLAGS_TSO_PLD |
2286 MXGEFW_FLAGS_FIRST |
2287 (small * MXGEFW_FLAGS_SMALL);
2288 }
2289 }
0da34b6d
BG		 2290 req->addr_high = high_swapped;
2291 req->addr_low = htonl(low);
40f6cff5 2292 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2293 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2294 req->rdma_count = 1;
2295 req->length = htons(seglen);
2296 req->cksum_offset = cksum_offset;
2297 req->flags = flags | ((cum_len & 1) * odd_flag);
2298
2299 low += seglen;
2300 len -= seglen;
2301 cum_len = cum_len_next;
2302 flags = flags_next;
2303 req++;
2304 count++;
2305 rdma_count++;
2306 if (unlikely(cksum_offset > seglen))
2307 cksum_offset -= seglen;
2308 else
2309 cksum_offset = 0;
2310 }
2311 if (frag_idx == frag_cnt)
2312 break;
2313
2314 /* map next fragment for DMA */
2315 idx = (count + tx->req) & tx->mask;
2316 frag = &skb_shinfo(skb)->frags[frag_idx];
2317 frag_idx++;
2318 len = frag->size;
2319 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2320 len, PCI_DMA_TODEVICE);
2321 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2322 pci_unmap_len_set(&tx->info[idx], len, len);
2323 }
2324
2325 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2326 if (mss)
2327 do {
2328 req--;
2329 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2330 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2331 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2332 idx = ((count - 1) + tx->req) & tx->mask;
2333 tx->info[idx].last = 1;
2334 if (tx->wc_fifo == NULL)
2335 myri10ge_submit_req(tx, tx->req_list, count);
2336 else
2337 myri10ge_submit_req_wc(tx, tx->req_list, count);
2338 tx->pkt_start++;
2339 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2340 mgp->stop_queue++;
2341 netif_stop_queue(dev);
2342 }
2343 dev->trans_start = jiffies;
2344 return 0;
2345
2346abort_linearize:
2347 /* Free any DMA resources we've alloced and clear out the skb
2348 * slot so as to not trip up assertions, and to avoid a
2349 * double-free if linearizing fails */
2350
2351 last_idx = (idx + 1) & tx->mask;
2352 idx = tx->req & tx->mask;
2353 tx->info[idx].skb = NULL;
2354 do {
2355 len = pci_unmap_len(&tx->info[idx], len);
2356 if (len) {
2357 if (tx->info[idx].skb != NULL)
2358 pci_unmap_single(mgp->pdev,
2359 pci_unmap_addr(&tx->info[idx],
2360 bus), len,
2361 PCI_DMA_TODEVICE);
2362 else
2363 pci_unmap_page(mgp->pdev,
2364 pci_unmap_addr(&tx->info[idx],
2365 bus), len,
2366 PCI_DMA_TODEVICE);
2367 pci_unmap_len_set(&tx->info[idx], len, 0);
2368 tx->info[idx].skb = NULL;
2369 }
2370 idx = (idx + 1) & tx->mask;
2371 } while (idx != last_idx);
89114afd 2372 if (skb_is_gso(skb)) {
0da34b6d
BG		 2373 printk(KERN_ERR
2374 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2375 mgp->dev->name);
2376 goto drop;
2377 }
2378
bec0e859 2379 if (skb_linearize(skb))
0da34b6d
BG		 2380 goto drop;
2381
2382 mgp->tx_linearized++;
2383 goto again;
2384
2385drop:
2386 dev_kfree_skb_any(skb);
2387 mgp->stats.tx_dropped += 1;
2388 return 0;
2389
2390}
2391
2392static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2393{
2394 struct myri10ge_priv *mgp = netdev_priv(dev);
2395 return &mgp->stats;
2396}
2397
2398static void myri10ge_set_multicast_list(struct net_device *dev)
2399{
85a7ea1b
BG		 2400 struct myri10ge_cmd cmd;
2401 struct myri10ge_priv *mgp;
2402 struct dev_mc_list *mc_list;
6250223e 2403 __be32 data[2] = { 0, 0 };
85a7ea1b 2404 int err;
0795af57 2405 DECLARE_MAC_BUF(mac);
85a7ea1b
BG		 2406
2407 mgp = netdev_priv(dev);
0da34b6d
BG		 2408 /* can be called from atomic contexts,
2409 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2410 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2411
2412 /* This firmware is known to not support multicast */
2f76216f 2413 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2414 return;
2415
2416 /* Disable multicast filtering */
2417
2418 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2419 if (err != 0) {
2420 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2421 " error status: %d\n", dev->name, err);
2422 goto abort;
2423 }
2424
2f76216f 2425 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2426 /* request to disable multicast filtering, so quit here */
2427 return;
2428 }
2429
2430 /* Flush the filters */
2431
2432 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2433 &cmd, 1);
2434 if (err != 0) {
2435 printk(KERN_ERR
2436 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2437 ", error status: %d\n", dev->name, err);
2438 goto abort;
2439 }
2440
2441 /* Walk the multicast list, and add each address */
2442 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
40f6cff5
AV		 2443 memcpy(data, &mc_list->dmi_addr, 6);
2444 cmd.data0 = ntohl(data[0]);
2445 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2446 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2447 &cmd, 1);
2448
2449 if (err != 0) {
2450 printk(KERN_ERR "myri10ge: %s: Failed "
2451 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2452 "%d\t", dev->name, err);
0795af57
JP		 2453 printk(KERN_ERR "MAC %s\n",
2454 print_mac(mac, mc_list->dmi_addr));
85a7ea1b
BG		 2455 goto abort;
2456 }
2457 }
2458 /* Enable multicast filtering */
2459 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2460 if (err != 0) {
2461 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2462 "error status: %d\n", dev->name, err);
2463 goto abort;
2464 }
2465
2466 return;
2467
2468abort:
2469 return;
0da34b6d
BG		 2470}
2471
2472static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2473{
2474 struct sockaddr *sa = addr;
2475 struct myri10ge_priv *mgp = netdev_priv(dev);
2476 int status;
2477
2478 if (!is_valid_ether_addr(sa->sa_data))
2479 return -EADDRNOTAVAIL;
2480
2481 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2482 if (status != 0) {
2483 printk(KERN_ERR
2484 "myri10ge: %s: changing mac address failed with %d\n",
2485 dev->name, status);
2486 return status;
2487 }
2488
2489 /* change the dev structure */
2490 memcpy(dev->dev_addr, sa->sa_data, 6);
2491 return 0;
2492}
2493
2494static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2495{
2496 struct myri10ge_priv *mgp = netdev_priv(dev);
2497 int error = 0;
2498
2499 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2500 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2501 dev->name, new_mtu);
2502 return -EINVAL;
2503 }
2504 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2505 dev->name, dev->mtu, new_mtu);
2506 if (mgp->running) {
2507 /* if we change the mtu on an active device, we must
2508 * reset the device so the firmware sees the change */
2509 myri10ge_close(dev);
2510 dev->mtu = new_mtu;
2511 myri10ge_open(dev);
2512 } else
2513 dev->mtu = new_mtu;
2514
2515 return error;
2516}
2517
2518/*
2519 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2520 * Only do it if the bridge is a root port since we don't want to disturb
2521 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2522 */
2523
0da34b6d
BG		 2524static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2525{
2526 struct pci_dev *bridge = mgp->pdev->bus->self;
2527 struct device *dev = &mgp->pdev->dev;
2528 unsigned cap;
2529 unsigned err_cap;
2530 u16 val;
2531 u8 ext_type;
2532 int ret;
2533
2534 if (!myri10ge_ecrc_enable || !bridge)
2535 return;
2536
2537 /* check that the bridge is a root port */
2538 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2539 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2540 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2541 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2542 if (myri10ge_ecrc_enable > 1) {
2543 struct pci_dev *old_bridge = bridge;
2544
2545 /* Walk the hierarchy up to the root port
2546 * where ECRC has to be enabled */
2547 do {
2548 bridge = bridge->bus->self;
2549 if (!bridge) {
2550 dev_err(dev,
2551 "Failed to find root port"
2552 " to force ECRC\n");
2553 return;
2554 }
2555 cap =
2556 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2557 pci_read_config_word(bridge,
2558 cap + PCI_CAP_FLAGS, &val);
2559 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2560 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2561
2562 dev_info(dev,
2563 "Forcing ECRC on non-root port %s"
2564 " (enabling on root port %s)\n",
2565 pci_name(old_bridge), pci_name(bridge));
2566 } else {
2567 dev_err(dev,
2568 "Not enabling ECRC on non-root port %s\n",
2569 pci_name(bridge));
2570 return;
2571 }
2572 }
2573
2574 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 2575 if (!cap)
2576 return;
2577
2578 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2579 if (ret) {
2580 dev_err(dev, "failed reading ext-conf-space of %s\n",
2581 pci_name(bridge));
2582 dev_err(dev, "\t pci=nommconf in use? "
2583 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2584 return;
2585 }
2586 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2587 return;
2588
2589 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2590 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2591 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 2592}
2593
2594/*
2595 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2596 * when the PCI-E Completion packets are aligned on an 8-byte
2597 * boundary. Some PCI-E chip sets always align Completion packets; on
2598 * the ones that do not, the alignment can be enforced by enabling
2599 * ECRC generation (if supported).
2600 *
2601 * When PCI-E Completion packets are not aligned, it is actually more
2602 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2603 *
2604 * If the driver can neither enable ECRC nor verify that it has
2605 * already been enabled, then it must use a firmware image which works
2606 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2607 * should also ensure that it never gives the device a Read-DMA which is
2608 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2609 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2610 * firmware image, and set tx.boundary to 4KB.
2611 */
2612
5443e9ea 2613static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 2614{
5443e9ea
BG		 2615 struct pci_dev *pdev = mgp->pdev;
2616 struct device *dev = &pdev->dev;
302d242c 2617 int status;
0da34b6d 2618
5443e9ea
BG		 2619 mgp->tx.boundary = 4096;
2620 /*
2621 * Verify the max read request size was set to 4KB
2622 * before trying the test with 4KB.
2623 */
302d242c
BG		 2624 status = pcie_get_readrq(pdev);
2625 if (status < 0) {
5443e9ea
BG		 2626 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2627 goto abort;
2628 }
302d242c
BG		 2629 if (status != 4096) {
2630 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
5443e9ea
BG		 2631 mgp->tx.boundary = 2048;
2632 }
2633 /*
2634 * load the optimized firmware (which assumes aligned PCIe
2635 * completions) in order to see if it works on this host.
2636 */
2637 mgp->fw_name = myri10ge_fw_aligned;
2638 status = myri10ge_load_firmware(mgp);
2639 if (status != 0) {
2640 goto abort;
2641 }
2642
2643 /*
2644 * Enable ECRC if possible
2645 */
2646 myri10ge_enable_ecrc(mgp);
2647
2648 /*
2649 * Run a DMA test which watches for unaligned completions and
2650 * aborts on the first one seen.
2651 */
2652
2653 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2654 if (status == 0)
2655 return; /* keep the aligned firmware */
2656
2657 if (status != -E2BIG)
2658 dev_warn(dev, "DMA test failed: %d\n", status);
2659 if (status == -ENOSYS)
2660 dev_warn(dev, "Falling back to ethp! "
2661 "Please install up to date fw\n");
2662abort:
2663 /* fall back to using the unaligned firmware */
0da34b6d
BG		 2664 mgp->tx.boundary = 2048;
2665 mgp->fw_name = myri10ge_fw_unaligned;
2666
5443e9ea
BG		 2667}
2668
2669static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2670{
0da34b6d 2671 if (myri10ge_force_firmware == 0) {
ce7f9368
BG		 2672 int link_width, exp_cap;
2673 u16 lnk;
2674
2675 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2676 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2677 link_width = (lnk >> 4) & 0x3f;
2678
ce7f9368
BG		 2679 /* Check to see if Link is less than 8 or if the
2680 * upstream bridge is known to provide aligned
2681 * completions */
2682 if (link_width < 8) {
2683 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2684 link_width);
2685 mgp->tx.boundary = 4096;
2686 mgp->fw_name = myri10ge_fw_aligned;
5443e9ea
BG		 2687 } else {
2688 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 2689 }
2690 } else {
2691 if (myri10ge_force_firmware == 1) {
2692 dev_info(&mgp->pdev->dev,
2693 "Assuming aligned completions (forced)\n");
2694 mgp->tx.boundary = 4096;
2695 mgp->fw_name = myri10ge_fw_aligned;
2696 } else {
2697 dev_info(&mgp->pdev->dev,
2698 "Assuming unaligned completions (forced)\n");
2699 mgp->tx.boundary = 2048;
2700 mgp->fw_name = myri10ge_fw_unaligned;
2701 }
2702 }
2703 if (myri10ge_fw_name != NULL) {
2704 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2705 myri10ge_fw_name);
2706 mgp->fw_name = myri10ge_fw_name;
2707 }
2708}
2709
0da34b6d 2710#ifdef CONFIG_PM
0da34b6d
BG		 2711static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2712{
2713 struct myri10ge_priv *mgp;
2714 struct net_device *netdev;
2715
2716 mgp = pci_get_drvdata(pdev);
2717 if (mgp == NULL)
2718 return -EINVAL;
2719 netdev = mgp->dev;
2720
2721 netif_device_detach(netdev);
2722 if (netif_running(netdev)) {
2723 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2724 rtnl_lock();
2725 myri10ge_close(netdev);
2726 rtnl_unlock();
2727 }
2728 myri10ge_dummy_rdma(mgp, 0);
83f6e152 2729 pci_save_state(pdev);
0da34b6d 2730 pci_disable_device(pdev);
1a63e846
BG		 2731
2732 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 2733}
2734
2735static int myri10ge_resume(struct pci_dev *pdev)
2736{
2737 struct myri10ge_priv *mgp;
2738 struct net_device *netdev;
2739 int status;
2740 u16 vendor;
2741
2742 mgp = pci_get_drvdata(pdev);
2743 if (mgp == NULL)
2744 return -EINVAL;
2745 netdev = mgp->dev;
2746 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2747 msleep(5); /* give card time to respond */
2748 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2749 if (vendor == 0xffff) {
2750 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2751 mgp->dev->name);
2752 return -EIO;
2753 }
83f6e152 2754
1a63e846
BG		 2755 status = pci_restore_state(pdev);
2756 if (status)
2757 return status;
4c2248cc
BG		 2758
2759 status = pci_enable_device(pdev);
1a63e846 2760 if (status) {
4c2248cc 2761 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 2762 return status;
4c2248cc
BG		 2763 }
2764
0da34b6d
BG		 2765 pci_set_master(pdev);
2766
0da34b6d 2767 myri10ge_reset(mgp);
013b68bf 2768 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 2769
2770 /* Save configuration space to be restored if the
2771 * nic resets due to a parity error */
83f6e152 2772 pci_save_state(pdev);
0da34b6d
BG		 2773
2774 if (netif_running(netdev)) {
2775 rtnl_lock();
df30a740 2776 status = myri10ge_open(netdev);
0da34b6d 2777 rtnl_unlock();
df30a740
BG		 2778 if (status != 0)
2779 goto abort_with_enabled;
2780
0da34b6d
BG		 2781 }
2782 netif_device_attach(netdev);
2783
2784 return 0;
2785
4c2248cc
BG		 2786abort_with_enabled:
2787 pci_disable_device(pdev);
0da34b6d
BG		 2788 return -EIO;
2789
2790}
0da34b6d
BG		 2791#endif /* CONFIG_PM */
2792
2793static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2794{
2795 struct pci_dev *pdev = mgp->pdev;
2796 int vs = mgp->vendor_specific_offset;
2797 u32 reboot;
2798
2799 /*enter read32 mode */
2800 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2801
2802 /*read REBOOT_STATUS (0xfffffff0) */
2803 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2804 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2805 return reboot;
2806}
2807
2808/*
2809 * This watchdog is used to check whether the board has suffered
2810 * from a parity error and needs to be recovered.
2811 */
c4028958 2812static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 2813{
c4028958 2814 struct myri10ge_priv *mgp =
6250223e 2815 container_of(work, struct myri10ge_priv, watchdog_work);
0da34b6d
BG		 2816 u32 reboot;
2817 int status;
2818 u16 cmd, vendor;
2819
2820 mgp->watchdog_resets++;
2821 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2822 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2823 /* Bus master DMA disabled? Check to see
2824 * if the card rebooted due to a parity error
2825 * For now, just report it */
2826 reboot = myri10ge_read_reboot(mgp);
2827 printk(KERN_ERR
f181137f
BG		 2828 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
2829 mgp->dev->name, reboot,
2830 myri10ge_reset_recover ? " " : " not");
2831 if (myri10ge_reset_recover == 0)
2832 return;
2833
2834 myri10ge_reset_recover--;
2835
0da34b6d
BG		 2836 /*
2837 * A rebooted nic will come back with config space as
2838 * it was after power was applied to PCIe bus.
2839 * Attempt to restore config space which was saved
2840 * when the driver was loaded, or the last time the
2841 * nic was resumed from power saving mode.
2842 */
83f6e152 2843 pci_restore_state(mgp->pdev);
7adda30c
BG		 2844
2845 /* save state again for accounting reasons */
83f6e152 2846 pci_save_state(mgp->pdev);
7adda30c 2847
0da34b6d
BG		 2848 } else {
2849 /* if we get back -1's from our slot, perhaps somebody
2850 * powered off our card. Don't try to reset it in
2851 * this case */
2852 if (cmd == 0xffff) {
2853 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2854 if (vendor == 0xffff) {
2855 printk(KERN_ERR
2856 "myri10ge: %s: device disappeared!\n",
2857 mgp->dev->name);
2858 return;
2859 }
2860 }
2861 /* Perhaps it is a software error. Try to reset */
2862
2863 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2864 mgp->dev->name);
2865 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2866 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2867 mgp->tx.pkt_start, mgp->tx.pkt_done,
2868 (int)ntohl(mgp->fw_stats->send_done_count));
2869 msleep(2000);
2870 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2871 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2872 mgp->tx.pkt_start, mgp->tx.pkt_done,
2873 (int)ntohl(mgp->fw_stats->send_done_count));
2874 }
2875 rtnl_lock();
2876 myri10ge_close(mgp->dev);
2877 status = myri10ge_load_firmware(mgp);
2878 if (status != 0)
2879 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2880 mgp->dev->name);
2881 else
2882 myri10ge_open(mgp->dev);
2883 rtnl_unlock();
2884}
2885
2886/*
2887 * We use our own timer routine rather than relying upon
2888 * netdev->tx_timeout because we have a very large hardware transmit
2889 * queue. Due to the large queue, the netdev->tx_timeout function
2890 * cannot detect a NIC with a parity error in a timely fashion if the
2891 * NIC is lightly loaded.
2892 */
2893static void myri10ge_watchdog_timer(unsigned long arg)
2894{
2895 struct myri10ge_priv *mgp;
626fda94 2896 u32 rx_pause_cnt;
0da34b6d
BG		 2897
2898 mgp = (struct myri10ge_priv *)arg;
c7dab99b
BG		 2899
2900 if (mgp->rx_small.watchdog_needed) {
2901 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2902 mgp->small_bytes + MXGEFW_PAD, 1);
2903 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2904 myri10ge_fill_thresh)
2905 mgp->rx_small.watchdog_needed = 0;
2906 }
2907 if (mgp->rx_big.watchdog_needed) {
2908 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2909 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2910 myri10ge_fill_thresh)
2911 mgp->rx_big.watchdog_needed = 0;
2912 }
626fda94 2913 rx_pause_cnt = ntohl(mgp->fw_stats->dropped_pause);
c7dab99b 2914
0da34b6d 2915 if (mgp->tx.req != mgp->tx.done &&
c54772e7 2916 mgp->tx.done == mgp->watchdog_tx_done &&
626fda94 2917 mgp->watchdog_tx_req != mgp->watchdog_tx_done) {
0da34b6d 2918 /* nic seems like it might be stuck.. */
626fda94
BG		 2919 if (rx_pause_cnt != mgp->watchdog_pause) {
2920 if (net_ratelimit())
2921 printk(KERN_WARNING "myri10ge %s:"
2922 "TX paused, check link partner\n",
2923 mgp->dev->name);
2924 } else {
2925 schedule_work(&mgp->watchdog_work);
2926 return;
2927 }
2928 }
2929 /* rearm timer */
2930 mod_timer(&mgp->watchdog_timer,
2931 jiffies + myri10ge_watchdog_timeout * HZ);
0da34b6d 2932 mgp->watchdog_tx_done = mgp->tx.done;
c54772e7 2933 mgp->watchdog_tx_req = mgp->tx.req;
626fda94 2934 mgp->watchdog_pause = rx_pause_cnt;
0da34b6d
BG		 2935}
2936
2937static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2938{
2939 struct net_device *netdev;
2940 struct myri10ge_priv *mgp;
2941 struct device *dev = &pdev->dev;
2942 size_t bytes;
2943 int i;
2944 int status = -ENXIO;
0da34b6d 2945 int dac_enabled;
0da34b6d
BG		 2946
2947 netdev = alloc_etherdev(sizeof(*mgp));
2948 if (netdev == NULL) {
2949 dev_err(dev, "Could not allocate ethernet device\n");
2950 return -ENOMEM;
2951 }
2952
b245fb67
MH		 2953 SET_NETDEV_DEV(netdev, &pdev->dev);
2954
0da34b6d 2955 mgp = netdev_priv(netdev);
0da34b6d 2956 mgp->dev = netdev;
e636b2ea 2957 netif_napi_add(netdev, &mgp->napi, myri10ge_poll, myri10ge_napi_weight);
0da34b6d
BG		 2958 mgp->pdev = pdev;
2959 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2960 mgp->pause = myri10ge_flow_control;
2961 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 2962 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
0da34b6d
BG		 2963 init_waitqueue_head(&mgp->down_wq);
2964
2965 if (pci_enable_device(pdev)) {
2966 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2967 status = -ENODEV;
2968 goto abort_with_netdev;
2969 }
0da34b6d
BG		 2970
2971 /* Find the vendor-specific cap so we can check
2972 * the reboot register later on */
2973 mgp->vendor_specific_offset
2974 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2975
2976 /* Set our max read request to 4KB */
302d242c 2977 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 2978 if (status != 0) {
2979 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2980 status);
2981 goto abort_with_netdev;
2982 }
2983
2984 pci_set_master(pdev);
2985 dac_enabled = 1;
2986 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2987 if (status != 0) {
2988 dac_enabled = 0;
2989 dev_err(&pdev->dev,
2990 "64-bit pci address mask was refused, trying 32-bit");
2991 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2992 }
2993 if (status != 0) {
2994 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2995 goto abort_with_netdev;
2996 }
b10c0668
BG		 2997 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2998 &mgp->cmd_bus, GFP_KERNEL);
0da34b6d
BG		 2999 if (mgp->cmd == NULL)
3000 goto abort_with_netdev;
3001
b10c0668
BG		 3002 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3003 &mgp->fw_stats_bus, GFP_KERNEL);
0da34b6d
BG		 3004 if (mgp->fw_stats == NULL)
3005 goto abort_with_cmd;
3006
3007 mgp->board_span = pci_resource_len(pdev, 0);
3008 mgp->iomem_base = pci_resource_start(pdev, 0);
3009 mgp->mtrr = -1;
276e26c3 3010 mgp->wc_enabled = 0;
0da34b6d
BG		 3011#ifdef CONFIG_MTRR
3012 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3013 MTRR_TYPE_WRCOMB, 1);
276e26c3
BG		 3014 if (mgp->mtrr >= 0)
3015 mgp->wc_enabled = 1;
0da34b6d
BG		 3016#endif
3017 /* Hack. need to get rid of these magic numbers */
3018 mgp->sram_size =
3019 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3020 if (mgp->sram_size > mgp->board_span) {
3021 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3022 mgp->board_span);
3023 goto abort_with_wc;
3024 }
3025 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3026 if (mgp->sram == NULL) {
3027 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3028 mgp->board_span, mgp->iomem_base);
3029 status = -ENXIO;
3030 goto abort_with_wc;
3031 }
3032 memcpy_fromio(mgp->eeprom_strings,
3033 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3034 MYRI10GE_EEPROM_STRINGS_SIZE);
3035 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3036 status = myri10ge_read_mac_addr(mgp);
3037 if (status)
3038 goto abort_with_ioremap;
3039
3040 for (i = 0; i < ETH_ALEN; i++)
3041 netdev->dev_addr[i] = mgp->mac_addr[i];
3042
3043 /* allocate rx done ring */
3044 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3045 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3046 &mgp->rx_done.bus, GFP_KERNEL);
0da34b6d
BG		 3047 if (mgp->rx_done.entry == NULL)
3048 goto abort_with_ioremap;
3049 memset(mgp->rx_done.entry, 0, bytes);
3050
5443e9ea
BG		 3051 myri10ge_select_firmware(mgp);
3052
0da34b6d
BG		 3053 status = myri10ge_load_firmware(mgp);
3054 if (status != 0) {
3055 dev_err(&pdev->dev, "failed to load firmware\n");
3056 goto abort_with_rx_done;
3057 }
3058
3059 status = myri10ge_reset(mgp);
3060 if (status != 0) {
3061 dev_err(&pdev->dev, "failed reset\n");
3062 goto abort_with_firmware;
3063 }
3064
0da34b6d
BG		 3065 pci_set_drvdata(pdev, mgp);
3066 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3067 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3068 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3069 myri10ge_initial_mtu = 68;
3070 netdev->mtu = myri10ge_initial_mtu;
3071 netdev->open = myri10ge_open;
3072 netdev->stop = myri10ge_close;
3073 netdev->hard_start_xmit = myri10ge_xmit;
3074 netdev->get_stats = myri10ge_get_stats;
3075 netdev->base_addr = mgp->iomem_base;
0da34b6d
BG		 3076 netdev->change_mtu = myri10ge_change_mtu;
3077 netdev->set_multicast_list = myri10ge_set_multicast_list;
3078 netdev->set_mac_address = myri10ge_set_mac_address;
3079 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
3080 if (dac_enabled)
3081 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3082
21d05db1
BG		 3083 /* make sure we can get an irq, and that MSI can be
3084 * setup (if available). Also ensure netdev->irq
3085 * is set to correct value if MSI is enabled */
3086 status = myri10ge_request_irq(mgp);
3087 if (status != 0)
3088 goto abort_with_firmware;
3089 netdev->irq = pdev->irq;
3090 myri10ge_free_irq(mgp);
3091
0da34b6d
BG		 3092 /* Save configuration space to be restored if the
3093 * nic resets due to a parity error */
83f6e152 3094 pci_save_state(pdev);
0da34b6d
BG		 3095
3096 /* Setup the watchdog timer */
3097 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3098 (unsigned long)mgp);
3099
3100 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
c4028958 3101 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3102 status = register_netdev(netdev);
3103 if (status != 0) {
3104 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3105 goto abort_with_state;
0da34b6d 3106 }
21d05db1
BG		 3107 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3108 (mgp->msi_enabled ? "MSI" : "xPIC"),
3109 netdev->irq, mgp->tx.boundary, mgp->fw_name,
276e26c3 3110 (mgp->wc_enabled ? "Enabled" : "Disabled"));
0da34b6d
BG		 3111
3112 return 0;
3113
7adda30c 3114abort_with_state:
83f6e152 3115 pci_restore_state(pdev);
0da34b6d
BG		 3116
3117abort_with_firmware:
3118 myri10ge_dummy_rdma(mgp, 0);
3119
3120abort_with_rx_done:
3121 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3122 dma_free_coherent(&pdev->dev, bytes,
3123 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3124
3125abort_with_ioremap:
3126 iounmap(mgp->sram);
3127
3128abort_with_wc:
3129#ifdef CONFIG_MTRR
3130 if (mgp->mtrr >= 0)
3131 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3132#endif
b10c0668
BG		 3133 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3134 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d
BG		 3135
3136abort_with_cmd:
b10c0668
BG		 3137 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3138 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3139
3140abort_with_netdev:
3141
3142 free_netdev(netdev);
3143 return status;
3144}
3145
3146/*
3147 * myri10ge_remove
3148 *
3149 * Does what is necessary to shutdown one Myrinet device. Called
3150 * once for each Myrinet card by the kernel when a module is
3151 * unloaded.
3152 */
3153static void myri10ge_remove(struct pci_dev *pdev)
3154{
3155 struct myri10ge_priv *mgp;
3156 struct net_device *netdev;
3157 size_t bytes;
3158
3159 mgp = pci_get_drvdata(pdev);
3160 if (mgp == NULL)
3161 return;
3162
3163 flush_scheduled_work();
3164 netdev = mgp->dev;
3165 unregister_netdev(netdev);
0da34b6d
BG		 3166
3167 myri10ge_dummy_rdma(mgp, 0);
3168
7adda30c 3169 /* avoid a memory leak */
83f6e152 3170 pci_restore_state(pdev);
7adda30c 3171
0da34b6d 3172 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
b10c0668
BG		 3173 dma_free_coherent(&pdev->dev, bytes,
3174 mgp->rx_done.entry, mgp->rx_done.bus);
0da34b6d
BG		 3175
3176 iounmap(mgp->sram);
3177
3178#ifdef CONFIG_MTRR
3179 if (mgp->mtrr >= 0)
3180 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3181#endif
b10c0668
BG		 3182 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3183 mgp->fw_stats, mgp->fw_stats_bus);
0da34b6d 3184
b10c0668
BG		 3185 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3186 mgp->cmd, mgp->cmd_bus);
0da34b6d
BG		 3187
3188 free_netdev(netdev);
3189 pci_set_drvdata(pdev, NULL);
3190}
3191
b10c0668 3192#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 3193#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d
BG		 3194
3195static struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 3196 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 3197 {PCI_DEVICE
3198 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 3199 {0},
3200};
3201
3202static struct pci_driver myri10ge_driver = {
3203 .name = "myri10ge",
3204 .probe = myri10ge_probe,
3205 .remove = myri10ge_remove,
3206 .id_table = myri10ge_pci_tbl,
3207#ifdef CONFIG_PM
3208 .suspend = myri10ge_suspend,
3209 .resume = myri10ge_resume,
3210#endif
3211};
3212
3213static __init int myri10ge_init_module(void)
3214{
3215 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3216 MYRI10GE_VERSION_STR);
3217 return pci_register_driver(&myri10ge_driver);
3218}
3219
3220module_init(myri10ge_init_module);
3221
3222static __exit void myri10ge_cleanup_module(void)
3223{
3224 pci_unregister_driver(&myri10ge_driver);
3225}
3226
3227module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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