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1da177e4 LT |
1 | /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */ |
2 | /* | |
3 | Written/copyright 1999-2001 by Donald Becker. | |
4 | Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com) | |
5 | Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com) | |
b27a16b7 | 6 | Portions copyright 2004 Harald Welte <laforge@gnumonks.org> |
1da177e4 LT |
7 | |
8 | This software may be used and distributed according to the terms of | |
9 | the GNU General Public License (GPL), incorporated herein by reference. | |
10 | Drivers based on or derived from this code fall under the GPL and must | |
11 | retain the authorship, copyright and license notice. This file is not | |
12 | a complete program and may only be used when the entire operating | |
13 | system is licensed under the GPL. License for under other terms may be | |
14 | available. Contact the original author for details. | |
15 | ||
16 | The original author may be reached as becker@scyld.com, or at | |
17 | Scyld Computing Corporation | |
18 | 410 Severn Ave., Suite 210 | |
19 | Annapolis MD 21403 | |
20 | ||
21 | Support information and updates available at | |
22 | http://www.scyld.com/network/netsemi.html | |
03a8c661 | 23 | [link no longer provides useful info -jgarzik] |
1da177e4 LT |
24 | |
25 | ||
1da177e4 LT |
26 | TODO: |
27 | * big endian support with CFG:BEM instead of cpu_to_le32 | |
1da177e4 LT |
28 | */ |
29 | ||
1da177e4 LT |
30 | #include <linux/module.h> |
31 | #include <linux/kernel.h> | |
32 | #include <linux/string.h> | |
33 | #include <linux/timer.h> | |
34 | #include <linux/errno.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/slab.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/netdevice.h> | |
40 | #include <linux/etherdevice.h> | |
41 | #include <linux/skbuff.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/spinlock.h> | |
44 | #include <linux/ethtool.h> | |
45 | #include <linux/delay.h> | |
46 | #include <linux/rtnetlink.h> | |
47 | #include <linux/mii.h> | |
48 | #include <linux/crc32.h> | |
49 | #include <linux/bitops.h> | |
b27a16b7 | 50 | #include <linux/prefetch.h> |
1da177e4 LT |
51 | #include <asm/processor.h> /* Processor type for cache alignment. */ |
52 | #include <asm/io.h> | |
53 | #include <asm/irq.h> | |
54 | #include <asm/uaccess.h> | |
55 | ||
56 | #define DRV_NAME "natsemi" | |
d5b20697 AG |
57 | #define DRV_VERSION "2.1" |
58 | #define DRV_RELDATE "Sept 11, 2006" | |
1da177e4 LT |
59 | |
60 | #define RX_OFFSET 2 | |
61 | ||
62 | /* Updated to recommendations in pci-skeleton v2.03. */ | |
63 | ||
64 | /* The user-configurable values. | |
65 | These may be modified when a driver module is loaded.*/ | |
66 | ||
67 | #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \ | |
68 | NETIF_MSG_LINK | \ | |
69 | NETIF_MSG_WOL | \ | |
70 | NETIF_MSG_RX_ERR | \ | |
71 | NETIF_MSG_TX_ERR) | |
72 | static int debug = -1; | |
73 | ||
1da177e4 LT |
74 | static int mtu; |
75 | ||
76 | /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). | |
77 | This chip uses a 512 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 78 | static const int multicast_filter_limit = 100; |
1da177e4 LT |
79 | |
80 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
81 | Setting to > 1518 effectively disables this feature. */ | |
82 | static int rx_copybreak; | |
83 | ||
1a147809 MB |
84 | static int dspcfg_workaround = 1; |
85 | ||
1da177e4 LT |
86 | /* Used to pass the media type, etc. |
87 | Both 'options[]' and 'full_duplex[]' should exist for driver | |
88 | interoperability. | |
89 | The media type is usually passed in 'options[]'. | |
90 | */ | |
91 | #define MAX_UNITS 8 /* More are supported, limit only on options */ | |
92 | static int options[MAX_UNITS]; | |
93 | static int full_duplex[MAX_UNITS]; | |
94 | ||
95 | /* Operational parameters that are set at compile time. */ | |
96 | ||
97 | /* Keep the ring sizes a power of two for compile efficiency. | |
98 | The compiler will convert <unsigned>'%'<2^N> into a bit mask. | |
99 | Making the Tx ring too large decreases the effectiveness of channel | |
100 | bonding and packet priority. | |
101 | There are no ill effects from too-large receive rings. */ | |
102 | #define TX_RING_SIZE 16 | |
103 | #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */ | |
104 | #define RX_RING_SIZE 32 | |
105 | ||
106 | /* Operational parameters that usually are not changed. */ | |
107 | /* Time in jiffies before concluding the transmitter is hung. */ | |
108 | #define TX_TIMEOUT (2*HZ) | |
109 | ||
110 | #define NATSEMI_HW_TIMEOUT 400 | |
f2cade13 | 111 | #define NATSEMI_TIMER_FREQ 5*HZ |
1da177e4 LT |
112 | #define NATSEMI_PG0_NREGS 64 |
113 | #define NATSEMI_RFDR_NREGS 8 | |
114 | #define NATSEMI_PG1_NREGS 4 | |
115 | #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \ | |
116 | NATSEMI_PG1_NREGS) | |
117 | #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */ | |
118 | #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32)) | |
1da177e4 LT |
119 | |
120 | /* Buffer sizes: | |
121 | * The nic writes 32-bit values, even if the upper bytes of | |
122 | * a 32-bit value are beyond the end of the buffer. | |
123 | */ | |
124 | #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */ | |
125 | #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */ | |
126 | #define NATSEMI_LONGPKT 1518 /* limit for normal packets */ | |
127 | #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */ | |
128 | ||
129 | /* These identify the driver base version and may not be removed. */ | |
aa738adf | 130 | static char version[] __devinitdata = |
1da177e4 LT |
131 | KERN_INFO DRV_NAME " dp8381x driver, version " |
132 | DRV_VERSION ", " DRV_RELDATE "\n" | |
133 | KERN_INFO " originally by Donald Becker <becker@scyld.com>\n" | |
1da177e4 LT |
134 | KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n"; |
135 | ||
136 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
137 | MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver"); | |
138 | MODULE_LICENSE("GPL"); | |
139 | ||
1da177e4 LT |
140 | module_param(mtu, int, 0); |
141 | module_param(debug, int, 0); | |
142 | module_param(rx_copybreak, int, 0); | |
1a147809 | 143 | module_param(dspcfg_workaround, int, 1); |
1da177e4 LT |
144 | module_param_array(options, int, NULL, 0); |
145 | module_param_array(full_duplex, int, NULL, 0); | |
1da177e4 LT |
146 | MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)"); |
147 | MODULE_PARM_DESC(debug, "DP8381x default debug level"); | |
6aa20a22 | 148 | MODULE_PARM_DESC(rx_copybreak, |
1da177e4 | 149 | "DP8381x copy breakpoint for copy-only-tiny-frames"); |
1a147809 | 150 | MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround"); |
6aa20a22 | 151 | MODULE_PARM_DESC(options, |
1da177e4 LT |
152 | "DP8381x: Bits 0-3: media type, bit 17: full duplex"); |
153 | MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)"); | |
154 | ||
155 | /* | |
156 | Theory of Operation | |
157 | ||
158 | I. Board Compatibility | |
159 | ||
160 | This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC. | |
161 | It also works with other chips in in the DP83810 series. | |
162 | ||
163 | II. Board-specific settings | |
164 | ||
165 | This driver requires the PCI interrupt line to be valid. | |
166 | It honors the EEPROM-set values. | |
167 | ||
168 | III. Driver operation | |
169 | ||
170 | IIIa. Ring buffers | |
171 | ||
172 | This driver uses two statically allocated fixed-size descriptor lists | |
173 | formed into rings by a branch from the final descriptor to the beginning of | |
174 | the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. | |
175 | The NatSemi design uses a 'next descriptor' pointer that the driver forms | |
176 | into a list. | |
177 | ||
178 | IIIb/c. Transmit/Receive Structure | |
179 | ||
180 | This driver uses a zero-copy receive and transmit scheme. | |
181 | The driver allocates full frame size skbuffs for the Rx ring buffers at | |
182 | open() time and passes the skb->data field to the chip as receive data | |
183 | buffers. When an incoming frame is less than RX_COPYBREAK bytes long, | |
184 | a fresh skbuff is allocated and the frame is copied to the new skbuff. | |
185 | When the incoming frame is larger, the skbuff is passed directly up the | |
186 | protocol stack. Buffers consumed this way are replaced by newly allocated | |
187 | skbuffs in a later phase of receives. | |
188 | ||
189 | The RX_COPYBREAK value is chosen to trade-off the memory wasted by | |
190 | using a full-sized skbuff for small frames vs. the copying costs of larger | |
191 | frames. New boards are typically used in generously configured machines | |
192 | and the underfilled buffers have negligible impact compared to the benefit of | |
193 | a single allocation size, so the default value of zero results in never | |
194 | copying packets. When copying is done, the cost is usually mitigated by using | |
195 | a combined copy/checksum routine. Copying also preloads the cache, which is | |
196 | most useful with small frames. | |
197 | ||
198 | A subtle aspect of the operation is that unaligned buffers are not permitted | |
199 | by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't | |
200 | longword aligned for further processing. On copies frames are put into the | |
201 | skbuff at an offset of "+2", 16-byte aligning the IP header. | |
202 | ||
203 | IIId. Synchronization | |
204 | ||
205 | Most operations are synchronized on the np->lock irq spinlock, except the | |
6344f052 MB |
206 | recieve and transmit paths which are synchronised using a combination of |
207 | hardware descriptor ownership, disabling interrupts and NAPI poll scheduling. | |
1da177e4 LT |
208 | |
209 | IVb. References | |
210 | ||
211 | http://www.scyld.com/expert/100mbps.html | |
212 | http://www.scyld.com/expert/NWay.html | |
213 | Datasheet is available from: | |
214 | http://www.national.com/pf/DP/DP83815.html | |
215 | ||
216 | IVc. Errata | |
217 | ||
218 | None characterised. | |
219 | */ | |
220 | ||
221 | ||
222 | ||
1da177e4 LT |
223 | /* |
224 | * Support for fibre connections on Am79C874: | |
225 | * This phy needs a special setup when connected to a fibre cable. | |
226 | * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf | |
227 | */ | |
228 | #define PHYID_AM79C874 0x0022561b | |
229 | ||
a2b524b2 JG |
230 | enum { |
231 | MII_MCTRL = 0x15, /* mode control register */ | |
232 | MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */ | |
233 | MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */ | |
234 | }; | |
1da177e4 | 235 | |
6aab4447 MB |
236 | enum { |
237 | NATSEMI_FLAG_IGNORE_PHY = 0x1, | |
238 | }; | |
6aa20a22 | 239 | |
1da177e4 | 240 | /* array of board data directly indexed by pci_tbl[x].driver_data */ |
aa738adf | 241 | static struct { |
1da177e4 LT |
242 | const char *name; |
243 | unsigned long flags; | |
a2b524b2 | 244 | unsigned int eeprom_size; |
1da177e4 | 245 | } natsemi_pci_info[] __devinitdata = { |
6aab4447 | 246 | { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 }, |
a2b524b2 | 247 | { "NatSemi DP8381[56]", 0, 24 }, |
1da177e4 LT |
248 | }; |
249 | ||
aa738adf | 250 | static struct pci_device_id natsemi_pci_tbl[] __devinitdata = { |
6aab4447 | 251 | { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 }, |
36c843d5 | 252 | { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, |
a2b524b2 | 253 | { } /* terminate list */ |
1da177e4 LT |
254 | }; |
255 | MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl); | |
256 | ||
257 | /* Offsets to the device registers. | |
258 | Unlike software-only systems, device drivers interact with complex hardware. | |
259 | It's not useful to define symbolic names for every register bit in the | |
260 | device. | |
261 | */ | |
262 | enum register_offsets { | |
263 | ChipCmd = 0x00, | |
264 | ChipConfig = 0x04, | |
265 | EECtrl = 0x08, | |
266 | PCIBusCfg = 0x0C, | |
267 | IntrStatus = 0x10, | |
268 | IntrMask = 0x14, | |
269 | IntrEnable = 0x18, | |
270 | IntrHoldoff = 0x1C, /* DP83816 only */ | |
271 | TxRingPtr = 0x20, | |
272 | TxConfig = 0x24, | |
273 | RxRingPtr = 0x30, | |
274 | RxConfig = 0x34, | |
275 | ClkRun = 0x3C, | |
276 | WOLCmd = 0x40, | |
277 | PauseCmd = 0x44, | |
278 | RxFilterAddr = 0x48, | |
279 | RxFilterData = 0x4C, | |
280 | BootRomAddr = 0x50, | |
281 | BootRomData = 0x54, | |
282 | SiliconRev = 0x58, | |
283 | StatsCtrl = 0x5C, | |
284 | StatsData = 0x60, | |
285 | RxPktErrs = 0x60, | |
286 | RxMissed = 0x68, | |
287 | RxCRCErrs = 0x64, | |
288 | BasicControl = 0x80, | |
289 | BasicStatus = 0x84, | |
290 | AnegAdv = 0x90, | |
291 | AnegPeer = 0x94, | |
292 | PhyStatus = 0xC0, | |
293 | MIntrCtrl = 0xC4, | |
294 | MIntrStatus = 0xC8, | |
295 | PhyCtrl = 0xE4, | |
296 | ||
297 | /* These are from the spec, around page 78... on a separate table. | |
298 | * The meaning of these registers depend on the value of PGSEL. */ | |
299 | PGSEL = 0xCC, | |
300 | PMDCSR = 0xE4, | |
301 | TSTDAT = 0xFC, | |
302 | DSPCFG = 0xF4, | |
303 | SDCFG = 0xF8 | |
304 | }; | |
305 | /* the values for the 'magic' registers above (PGSEL=1) */ | |
306 | #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */ | |
307 | #define TSTDAT_VAL 0x0 | |
308 | #define DSPCFG_VAL 0x5040 | |
309 | #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */ | |
310 | #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */ | |
311 | #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */ | |
312 | #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */ | |
313 | ||
314 | /* misc PCI space registers */ | |
315 | enum pci_register_offsets { | |
316 | PCIPM = 0x44, | |
317 | }; | |
318 | ||
319 | enum ChipCmd_bits { | |
320 | ChipReset = 0x100, | |
321 | RxReset = 0x20, | |
322 | TxReset = 0x10, | |
323 | RxOff = 0x08, | |
324 | RxOn = 0x04, | |
325 | TxOff = 0x02, | |
326 | TxOn = 0x01, | |
327 | }; | |
328 | ||
329 | enum ChipConfig_bits { | |
330 | CfgPhyDis = 0x200, | |
331 | CfgPhyRst = 0x400, | |
332 | CfgExtPhy = 0x1000, | |
333 | CfgAnegEnable = 0x2000, | |
334 | CfgAneg100 = 0x4000, | |
335 | CfgAnegFull = 0x8000, | |
336 | CfgAnegDone = 0x8000000, | |
337 | CfgFullDuplex = 0x20000000, | |
338 | CfgSpeed100 = 0x40000000, | |
339 | CfgLink = 0x80000000, | |
340 | }; | |
341 | ||
342 | enum EECtrl_bits { | |
343 | EE_ShiftClk = 0x04, | |
344 | EE_DataIn = 0x01, | |
345 | EE_ChipSelect = 0x08, | |
346 | EE_DataOut = 0x02, | |
347 | MII_Data = 0x10, | |
348 | MII_Write = 0x20, | |
349 | MII_ShiftClk = 0x40, | |
350 | }; | |
351 | ||
352 | enum PCIBusCfg_bits { | |
353 | EepromReload = 0x4, | |
354 | }; | |
355 | ||
356 | /* Bits in the interrupt status/mask registers. */ | |
357 | enum IntrStatus_bits { | |
358 | IntrRxDone = 0x0001, | |
359 | IntrRxIntr = 0x0002, | |
360 | IntrRxErr = 0x0004, | |
361 | IntrRxEarly = 0x0008, | |
362 | IntrRxIdle = 0x0010, | |
363 | IntrRxOverrun = 0x0020, | |
364 | IntrTxDone = 0x0040, | |
365 | IntrTxIntr = 0x0080, | |
366 | IntrTxErr = 0x0100, | |
367 | IntrTxIdle = 0x0200, | |
368 | IntrTxUnderrun = 0x0400, | |
369 | StatsMax = 0x0800, | |
370 | SWInt = 0x1000, | |
371 | WOLPkt = 0x2000, | |
372 | LinkChange = 0x4000, | |
373 | IntrHighBits = 0x8000, | |
374 | RxStatusFIFOOver = 0x10000, | |
375 | IntrPCIErr = 0xf00000, | |
376 | RxResetDone = 0x1000000, | |
377 | TxResetDone = 0x2000000, | |
378 | IntrAbnormalSummary = 0xCD20, | |
379 | }; | |
380 | ||
381 | /* | |
382 | * Default Interrupts: | |
383 | * Rx OK, Rx Packet Error, Rx Overrun, | |
384 | * Tx OK, Tx Packet Error, Tx Underrun, | |
385 | * MIB Service, Phy Interrupt, High Bits, | |
386 | * Rx Status FIFO overrun, | |
387 | * Received Target Abort, Received Master Abort, | |
388 | * Signalled System Error, Received Parity Error | |
389 | */ | |
390 | #define DEFAULT_INTR 0x00f1cd65 | |
391 | ||
392 | enum TxConfig_bits { | |
393 | TxDrthMask = 0x3f, | |
394 | TxFlthMask = 0x3f00, | |
395 | TxMxdmaMask = 0x700000, | |
396 | TxMxdma_512 = 0x0, | |
397 | TxMxdma_4 = 0x100000, | |
398 | TxMxdma_8 = 0x200000, | |
399 | TxMxdma_16 = 0x300000, | |
400 | TxMxdma_32 = 0x400000, | |
401 | TxMxdma_64 = 0x500000, | |
402 | TxMxdma_128 = 0x600000, | |
403 | TxMxdma_256 = 0x700000, | |
404 | TxCollRetry = 0x800000, | |
405 | TxAutoPad = 0x10000000, | |
406 | TxMacLoop = 0x20000000, | |
407 | TxHeartIgn = 0x40000000, | |
408 | TxCarrierIgn = 0x80000000 | |
409 | }; | |
410 | ||
6aa20a22 | 411 | /* |
1da177e4 LT |
412 | * Tx Configuration: |
413 | * - 256 byte DMA burst length | |
414 | * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free) | |
415 | * - 64 bytes initial drain threshold (i.e. begin actual transmission | |
416 | * when 64 byte are in the fifo) | |
417 | * - on tx underruns, increase drain threshold by 64. | |
418 | * - at most use a drain threshold of 1472 bytes: The sum of the fill | |
419 | * threshold and the drain threshold must be less than 2016 bytes. | |
420 | * | |
421 | */ | |
422 | #define TX_FLTH_VAL ((512/32) << 8) | |
423 | #define TX_DRTH_VAL_START (64/32) | |
424 | #define TX_DRTH_VAL_INC 2 | |
425 | #define TX_DRTH_VAL_LIMIT (1472/32) | |
426 | ||
427 | enum RxConfig_bits { | |
428 | RxDrthMask = 0x3e, | |
429 | RxMxdmaMask = 0x700000, | |
430 | RxMxdma_512 = 0x0, | |
431 | RxMxdma_4 = 0x100000, | |
432 | RxMxdma_8 = 0x200000, | |
433 | RxMxdma_16 = 0x300000, | |
434 | RxMxdma_32 = 0x400000, | |
435 | RxMxdma_64 = 0x500000, | |
436 | RxMxdma_128 = 0x600000, | |
437 | RxMxdma_256 = 0x700000, | |
438 | RxAcceptLong = 0x8000000, | |
439 | RxAcceptTx = 0x10000000, | |
440 | RxAcceptRunt = 0x40000000, | |
441 | RxAcceptErr = 0x80000000 | |
442 | }; | |
443 | #define RX_DRTH_VAL (128/8) | |
444 | ||
445 | enum ClkRun_bits { | |
446 | PMEEnable = 0x100, | |
447 | PMEStatus = 0x8000, | |
448 | }; | |
449 | ||
450 | enum WolCmd_bits { | |
451 | WakePhy = 0x1, | |
452 | WakeUnicast = 0x2, | |
453 | WakeMulticast = 0x4, | |
454 | WakeBroadcast = 0x8, | |
455 | WakeArp = 0x10, | |
456 | WakePMatch0 = 0x20, | |
457 | WakePMatch1 = 0x40, | |
458 | WakePMatch2 = 0x80, | |
459 | WakePMatch3 = 0x100, | |
460 | WakeMagic = 0x200, | |
461 | WakeMagicSecure = 0x400, | |
462 | SecureHack = 0x100000, | |
463 | WokePhy = 0x400000, | |
464 | WokeUnicast = 0x800000, | |
465 | WokeMulticast = 0x1000000, | |
466 | WokeBroadcast = 0x2000000, | |
467 | WokeArp = 0x4000000, | |
468 | WokePMatch0 = 0x8000000, | |
469 | WokePMatch1 = 0x10000000, | |
470 | WokePMatch2 = 0x20000000, | |
471 | WokePMatch3 = 0x40000000, | |
472 | WokeMagic = 0x80000000, | |
473 | WakeOptsSummary = 0x7ff | |
474 | }; | |
475 | ||
476 | enum RxFilterAddr_bits { | |
477 | RFCRAddressMask = 0x3ff, | |
478 | AcceptMulticast = 0x00200000, | |
479 | AcceptMyPhys = 0x08000000, | |
480 | AcceptAllPhys = 0x10000000, | |
481 | AcceptAllMulticast = 0x20000000, | |
482 | AcceptBroadcast = 0x40000000, | |
483 | RxFilterEnable = 0x80000000 | |
484 | }; | |
485 | ||
486 | enum StatsCtrl_bits { | |
487 | StatsWarn = 0x1, | |
488 | StatsFreeze = 0x2, | |
489 | StatsClear = 0x4, | |
490 | StatsStrobe = 0x8, | |
491 | }; | |
492 | ||
493 | enum MIntrCtrl_bits { | |
494 | MICRIntEn = 0x2, | |
495 | }; | |
496 | ||
497 | enum PhyCtrl_bits { | |
498 | PhyAddrMask = 0x1f, | |
499 | }; | |
500 | ||
501 | #define PHY_ADDR_NONE 32 | |
502 | #define PHY_ADDR_INTERNAL 1 | |
503 | ||
504 | /* values we might find in the silicon revision register */ | |
505 | #define SRR_DP83815_C 0x0302 | |
506 | #define SRR_DP83815_D 0x0403 | |
507 | #define SRR_DP83816_A4 0x0504 | |
508 | #define SRR_DP83816_A5 0x0505 | |
509 | ||
510 | /* The Rx and Tx buffer descriptors. */ | |
511 | /* Note that using only 32 bit fields simplifies conversion to big-endian | |
512 | architectures. */ | |
513 | struct netdev_desc { | |
eca1ad82 AV |
514 | __le32 next_desc; |
515 | __le32 cmd_status; | |
516 | __le32 addr; | |
517 | __le32 software_use; | |
1da177e4 LT |
518 | }; |
519 | ||
520 | /* Bits in network_desc.status */ | |
521 | enum desc_status_bits { | |
522 | DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000, | |
523 | DescNoCRC=0x10000000, DescPktOK=0x08000000, | |
524 | DescSizeMask=0xfff, | |
525 | ||
526 | DescTxAbort=0x04000000, DescTxFIFO=0x02000000, | |
527 | DescTxCarrier=0x01000000, DescTxDefer=0x00800000, | |
528 | DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000, | |
529 | DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000, | |
530 | ||
531 | DescRxAbort=0x04000000, DescRxOver=0x02000000, | |
532 | DescRxDest=0x01800000, DescRxLong=0x00400000, | |
533 | DescRxRunt=0x00200000, DescRxInvalid=0x00100000, | |
534 | DescRxCRC=0x00080000, DescRxAlign=0x00040000, | |
535 | DescRxLoop=0x00020000, DesRxColl=0x00010000, | |
536 | }; | |
537 | ||
538 | struct netdev_private { | |
539 | /* Descriptor rings first for alignment */ | |
540 | dma_addr_t ring_dma; | |
541 | struct netdev_desc *rx_ring; | |
542 | struct netdev_desc *tx_ring; | |
543 | /* The addresses of receive-in-place skbuffs */ | |
544 | struct sk_buff *rx_skbuff[RX_RING_SIZE]; | |
545 | dma_addr_t rx_dma[RX_RING_SIZE]; | |
546 | /* address of a sent-in-place packet/buffer, for later free() */ | |
547 | struct sk_buff *tx_skbuff[TX_RING_SIZE]; | |
548 | dma_addr_t tx_dma[TX_RING_SIZE]; | |
bea3348e SH |
549 | struct net_device *dev; |
550 | struct napi_struct napi; | |
1da177e4 LT |
551 | struct net_device_stats stats; |
552 | /* Media monitoring timer */ | |
553 | struct timer_list timer; | |
554 | /* Frequently used values: keep some adjacent for cache effect */ | |
555 | struct pci_dev *pci_dev; | |
556 | struct netdev_desc *rx_head_desc; | |
557 | /* Producer/consumer ring indices */ | |
558 | unsigned int cur_rx, dirty_rx; | |
559 | unsigned int cur_tx, dirty_tx; | |
560 | /* Based on MTU+slack. */ | |
561 | unsigned int rx_buf_sz; | |
562 | int oom; | |
b27a16b7 MB |
563 | /* Interrupt status */ |
564 | u32 intr_status; | |
1da177e4 LT |
565 | /* Do not touch the nic registers */ |
566 | int hands_off; | |
68c90166 MB |
567 | /* Don't pay attention to the reported link state. */ |
568 | int ignore_phy; | |
1da177e4 LT |
569 | /* external phy that is used: only valid if dev->if_port != PORT_TP */ |
570 | int mii; | |
571 | int phy_addr_external; | |
572 | unsigned int full_duplex; | |
573 | /* Rx filter */ | |
574 | u32 cur_rx_mode; | |
575 | u32 rx_filter[16]; | |
576 | /* FIFO and PCI burst thresholds */ | |
577 | u32 tx_config, rx_config; | |
578 | /* original contents of ClkRun register */ | |
579 | u32 SavedClkRun; | |
580 | /* silicon revision */ | |
581 | u32 srr; | |
582 | /* expected DSPCFG value */ | |
583 | u16 dspcfg; | |
1a147809 | 584 | int dspcfg_workaround; |
1da177e4 LT |
585 | /* parms saved in ethtool format */ |
586 | u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */ | |
587 | u8 duplex; /* Duplex, half or full */ | |
588 | u8 autoneg; /* Autonegotiation enabled */ | |
589 | /* MII transceiver section */ | |
590 | u16 advertising; | |
591 | unsigned int iosize; | |
592 | spinlock_t lock; | |
593 | u32 msg_enable; | |
a8b4cf42 MB |
594 | /* EEPROM data */ |
595 | int eeprom_size; | |
1da177e4 LT |
596 | }; |
597 | ||
598 | static void move_int_phy(struct net_device *dev, int addr); | |
599 | static int eeprom_read(void __iomem *ioaddr, int location); | |
600 | static int mdio_read(struct net_device *dev, int reg); | |
601 | static void mdio_write(struct net_device *dev, int reg, u16 data); | |
602 | static void init_phy_fixup(struct net_device *dev); | |
603 | static int miiport_read(struct net_device *dev, int phy_id, int reg); | |
604 | static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data); | |
605 | static int find_mii(struct net_device *dev); | |
606 | static void natsemi_reset(struct net_device *dev); | |
607 | static void natsemi_reload_eeprom(struct net_device *dev); | |
608 | static void natsemi_stop_rxtx(struct net_device *dev); | |
609 | static int netdev_open(struct net_device *dev); | |
610 | static void do_cable_magic(struct net_device *dev); | |
611 | static void undo_cable_magic(struct net_device *dev); | |
612 | static void check_link(struct net_device *dev); | |
613 | static void netdev_timer(unsigned long data); | |
614 | static void dump_ring(struct net_device *dev); | |
ed4cb133 | 615 | static void ns_tx_timeout(struct net_device *dev); |
1da177e4 LT |
616 | static int alloc_ring(struct net_device *dev); |
617 | static void refill_rx(struct net_device *dev); | |
618 | static void init_ring(struct net_device *dev); | |
619 | static void drain_tx(struct net_device *dev); | |
620 | static void drain_ring(struct net_device *dev); | |
621 | static void free_ring(struct net_device *dev); | |
622 | static void reinit_ring(struct net_device *dev); | |
623 | static void init_registers(struct net_device *dev); | |
624 | static int start_tx(struct sk_buff *skb, struct net_device *dev); | |
7d12e780 | 625 | static irqreturn_t intr_handler(int irq, void *dev_instance); |
1da177e4 | 626 | static void netdev_error(struct net_device *dev, int intr_status); |
bea3348e | 627 | static int natsemi_poll(struct napi_struct *napi, int budget); |
b27a16b7 | 628 | static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do); |
1da177e4 LT |
629 | static void netdev_tx_done(struct net_device *dev); |
630 | static int natsemi_change_mtu(struct net_device *dev, int new_mtu); | |
631 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
632 | static void natsemi_poll_controller(struct net_device *dev); | |
633 | #endif | |
634 | static void __set_rx_mode(struct net_device *dev); | |
635 | static void set_rx_mode(struct net_device *dev); | |
636 | static void __get_stats(struct net_device *dev); | |
637 | static struct net_device_stats *get_stats(struct net_device *dev); | |
638 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
639 | static int netdev_set_wol(struct net_device *dev, u32 newval); | |
640 | static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur); | |
641 | static int netdev_set_sopass(struct net_device *dev, u8 *newval); | |
642 | static int netdev_get_sopass(struct net_device *dev, u8 *data); | |
643 | static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd); | |
644 | static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd); | |
645 | static void enable_wol_mode(struct net_device *dev, int enable_intr); | |
646 | static int netdev_close(struct net_device *dev); | |
647 | static int netdev_get_regs(struct net_device *dev, u8 *buf); | |
648 | static int netdev_get_eeprom(struct net_device *dev, u8 *buf); | |
7282d491 | 649 | static const struct ethtool_ops ethtool_ops; |
1da177e4 | 650 | |
1a147809 MB |
651 | #define NATSEMI_ATTR(_name) \ |
652 | static ssize_t natsemi_show_##_name(struct device *dev, \ | |
653 | struct device_attribute *attr, char *buf); \ | |
654 | static ssize_t natsemi_set_##_name(struct device *dev, \ | |
655 | struct device_attribute *attr, \ | |
656 | const char *buf, size_t count); \ | |
657 | static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name) | |
658 | ||
659 | #define NATSEMI_CREATE_FILE(_dev, _name) \ | |
660 | device_create_file(&_dev->dev, &dev_attr_##_name) | |
661 | #define NATSEMI_REMOVE_FILE(_dev, _name) \ | |
f6c42865 | 662 | device_remove_file(&_dev->dev, &dev_attr_##_name) |
1a147809 MB |
663 | |
664 | NATSEMI_ATTR(dspcfg_workaround); | |
665 | ||
666 | static ssize_t natsemi_show_dspcfg_workaround(struct device *dev, | |
7d2e3cb7 | 667 | struct device_attribute *attr, |
1a147809 MB |
668 | char *buf) |
669 | { | |
670 | struct netdev_private *np = netdev_priv(to_net_dev(dev)); | |
671 | ||
672 | return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off"); | |
673 | } | |
674 | ||
675 | static ssize_t natsemi_set_dspcfg_workaround(struct device *dev, | |
676 | struct device_attribute *attr, | |
677 | const char *buf, size_t count) | |
678 | { | |
679 | struct netdev_private *np = netdev_priv(to_net_dev(dev)); | |
680 | int new_setting; | |
d41f2d17 | 681 | unsigned long flags; |
1a147809 MB |
682 | |
683 | /* Find out the new setting */ | |
684 | if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1)) | |
685 | new_setting = 1; | |
686 | else if (!strncmp("off", buf, count - 1) | |
687 | || !strncmp("0", buf, count - 1)) | |
688 | new_setting = 0; | |
689 | else | |
7d2e3cb7 | 690 | return count; |
1a147809 MB |
691 | |
692 | spin_lock_irqsave(&np->lock, flags); | |
693 | ||
694 | np->dspcfg_workaround = new_setting; | |
695 | ||
696 | spin_unlock_irqrestore(&np->lock, flags); | |
697 | ||
698 | return count; | |
699 | } | |
700 | ||
1da177e4 LT |
701 | static inline void __iomem *ns_ioaddr(struct net_device *dev) |
702 | { | |
703 | return (void __iomem *) dev->base_addr; | |
704 | } | |
705 | ||
b27a16b7 MB |
706 | static inline void natsemi_irq_enable(struct net_device *dev) |
707 | { | |
708 | writel(1, ns_ioaddr(dev) + IntrEnable); | |
709 | readl(ns_ioaddr(dev) + IntrEnable); | |
710 | } | |
711 | ||
712 | static inline void natsemi_irq_disable(struct net_device *dev) | |
713 | { | |
714 | writel(0, ns_ioaddr(dev) + IntrEnable); | |
715 | readl(ns_ioaddr(dev) + IntrEnable); | |
716 | } | |
717 | ||
1da177e4 LT |
718 | static void move_int_phy(struct net_device *dev, int addr) |
719 | { | |
720 | struct netdev_private *np = netdev_priv(dev); | |
721 | void __iomem *ioaddr = ns_ioaddr(dev); | |
722 | int target = 31; | |
723 | ||
6aa20a22 | 724 | /* |
1da177e4 LT |
725 | * The internal phy is visible on the external mii bus. Therefore we must |
726 | * move it away before we can send commands to an external phy. | |
727 | * There are two addresses we must avoid: | |
728 | * - the address on the external phy that is used for transmission. | |
729 | * - the address that we want to access. User space can access phys | |
730 | * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the | |
731 | * phy that is used for transmission. | |
732 | */ | |
733 | ||
734 | if (target == addr) | |
735 | target--; | |
736 | if (target == np->phy_addr_external) | |
737 | target--; | |
738 | writew(target, ioaddr + PhyCtrl); | |
739 | readw(ioaddr + PhyCtrl); | |
740 | udelay(1); | |
741 | } | |
742 | ||
5a40f09b JG |
743 | static void __devinit natsemi_init_media (struct net_device *dev) |
744 | { | |
745 | struct netdev_private *np = netdev_priv(dev); | |
746 | u32 tmp; | |
747 | ||
68c90166 MB |
748 | if (np->ignore_phy) |
749 | netif_carrier_on(dev); | |
750 | else | |
751 | netif_carrier_off(dev); | |
5a40f09b JG |
752 | |
753 | /* get the initial settings from hardware */ | |
754 | tmp = mdio_read(dev, MII_BMCR); | |
755 | np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10; | |
756 | np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF; | |
757 | np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE; | |
758 | np->advertising= mdio_read(dev, MII_ADVERTISE); | |
759 | ||
760 | if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL | |
761 | && netif_msg_probe(np)) { | |
762 | printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s " | |
763 | "10%s %s duplex.\n", | |
764 | pci_name(np->pci_dev), | |
765 | (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)? | |
766 | "enabled, advertise" : "disabled, force", | |
767 | (np->advertising & | |
768 | (ADVERTISE_100FULL|ADVERTISE_100HALF))? | |
769 | "0" : "", | |
770 | (np->advertising & | |
771 | (ADVERTISE_100FULL|ADVERTISE_10FULL))? | |
772 | "full" : "half"); | |
773 | } | |
774 | if (netif_msg_probe(np)) | |
775 | printk(KERN_INFO | |
776 | "natsemi %s: Transceiver status %#04x advertising %#04x.\n", | |
777 | pci_name(np->pci_dev), mdio_read(dev, MII_BMSR), | |
778 | np->advertising); | |
779 | ||
780 | } | |
781 | ||
1da177e4 LT |
782 | static int __devinit natsemi_probe1 (struct pci_dev *pdev, |
783 | const struct pci_device_id *ent) | |
784 | { | |
785 | struct net_device *dev; | |
786 | struct netdev_private *np; | |
787 | int i, option, irq, chip_idx = ent->driver_data; | |
788 | static int find_cnt = -1; | |
703bb99c SS |
789 | resource_size_t iostart; |
790 | unsigned long iosize; | |
1da177e4 LT |
791 | void __iomem *ioaddr; |
792 | const int pcibar = 1; /* PCI base address register */ | |
793 | int prev_eedata; | |
794 | u32 tmp; | |
795 | ||
796 | /* when built into the kernel, we only print version if device is found */ | |
797 | #ifndef MODULE | |
798 | static int printed_version; | |
799 | if (!printed_version++) | |
800 | printk(version); | |
801 | #endif | |
802 | ||
803 | i = pci_enable_device(pdev); | |
804 | if (i) return i; | |
805 | ||
806 | /* natsemi has a non-standard PM control register | |
807 | * in PCI config space. Some boards apparently need | |
808 | * to be brought to D0 in this manner. | |
809 | */ | |
810 | pci_read_config_dword(pdev, PCIPM, &tmp); | |
811 | if (tmp & PCI_PM_CTRL_STATE_MASK) { | |
812 | /* D0 state, disable PME assertion */ | |
813 | u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK; | |
814 | pci_write_config_dword(pdev, PCIPM, newtmp); | |
815 | } | |
816 | ||
817 | find_cnt++; | |
818 | iostart = pci_resource_start(pdev, pcibar); | |
819 | iosize = pci_resource_len(pdev, pcibar); | |
820 | irq = pdev->irq; | |
821 | ||
a2b524b2 | 822 | pci_set_master(pdev); |
1da177e4 LT |
823 | |
824 | dev = alloc_etherdev(sizeof (struct netdev_private)); | |
825 | if (!dev) | |
826 | return -ENOMEM; | |
1da177e4 LT |
827 | SET_NETDEV_DEV(dev, &pdev->dev); |
828 | ||
829 | i = pci_request_regions(pdev, DRV_NAME); | |
830 | if (i) | |
831 | goto err_pci_request_regions; | |
832 | ||
833 | ioaddr = ioremap(iostart, iosize); | |
834 | if (!ioaddr) { | |
835 | i = -ENOMEM; | |
836 | goto err_ioremap; | |
837 | } | |
838 | ||
839 | /* Work around the dropped serial bit. */ | |
840 | prev_eedata = eeprom_read(ioaddr, 6); | |
841 | for (i = 0; i < 3; i++) { | |
842 | int eedata = eeprom_read(ioaddr, i + 7); | |
843 | dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15); | |
844 | dev->dev_addr[i*2+1] = eedata >> 7; | |
845 | prev_eedata = eedata; | |
846 | } | |
847 | ||
848 | dev->base_addr = (unsigned long __force) ioaddr; | |
849 | dev->irq = irq; | |
850 | ||
851 | np = netdev_priv(dev); | |
bea3348e | 852 | netif_napi_add(dev, &np->napi, natsemi_poll, 64); |
bbbab5ca | 853 | np->dev = dev; |
1da177e4 LT |
854 | |
855 | np->pci_dev = pdev; | |
856 | pci_set_drvdata(pdev, dev); | |
857 | np->iosize = iosize; | |
858 | spin_lock_init(&np->lock); | |
859 | np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG; | |
860 | np->hands_off = 0; | |
b27a16b7 | 861 | np->intr_status = 0; |
a2b524b2 | 862 | np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size; |
6aab4447 MB |
863 | if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY) |
864 | np->ignore_phy = 1; | |
865 | else | |
866 | np->ignore_phy = 0; | |
1a147809 | 867 | np->dspcfg_workaround = dspcfg_workaround; |
1da177e4 LT |
868 | |
869 | /* Initial port: | |
68c90166 | 870 | * - If configured to ignore the PHY set up for external. |
1da177e4 LT |
871 | * - If the nic was configured to use an external phy and if find_mii |
872 | * finds a phy: use external port, first phy that replies. | |
873 | * - Otherwise: internal port. | |
874 | * Note that the phy address for the internal phy doesn't matter: | |
875 | * The address would be used to access a phy over the mii bus, but | |
876 | * the internal phy is accessed through mapped registers. | |
877 | */ | |
68c90166 | 878 | if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy) |
1da177e4 LT |
879 | dev->if_port = PORT_MII; |
880 | else | |
881 | dev->if_port = PORT_TP; | |
882 | /* Reset the chip to erase previous misconfiguration. */ | |
883 | natsemi_reload_eeprom(dev); | |
884 | natsemi_reset(dev); | |
885 | ||
886 | if (dev->if_port != PORT_TP) { | |
887 | np->phy_addr_external = find_mii(dev); | |
68c90166 MB |
888 | /* If we're ignoring the PHY it doesn't matter if we can't |
889 | * find one. */ | |
890 | if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) { | |
1da177e4 LT |
891 | dev->if_port = PORT_TP; |
892 | np->phy_addr_external = PHY_ADDR_INTERNAL; | |
893 | } | |
894 | } else { | |
895 | np->phy_addr_external = PHY_ADDR_INTERNAL; | |
896 | } | |
897 | ||
898 | option = find_cnt < MAX_UNITS ? options[find_cnt] : 0; | |
899 | if (dev->mem_start) | |
900 | option = dev->mem_start; | |
901 | ||
902 | /* The lower four bits are the media type. */ | |
903 | if (option) { | |
904 | if (option & 0x200) | |
905 | np->full_duplex = 1; | |
906 | if (option & 15) | |
907 | printk(KERN_INFO | |
908 | "natsemi %s: ignoring user supplied media type %d", | |
909 | pci_name(np->pci_dev), option & 15); | |
910 | } | |
911 | if (find_cnt < MAX_UNITS && full_duplex[find_cnt]) | |
912 | np->full_duplex = 1; | |
913 | ||
914 | /* The chip-specific entries in the device structure. */ | |
915 | dev->open = &netdev_open; | |
916 | dev->hard_start_xmit = &start_tx; | |
917 | dev->stop = &netdev_close; | |
918 | dev->get_stats = &get_stats; | |
919 | dev->set_multicast_list = &set_rx_mode; | |
920 | dev->change_mtu = &natsemi_change_mtu; | |
921 | dev->do_ioctl = &netdev_ioctl; | |
ed4cb133 | 922 | dev->tx_timeout = &ns_tx_timeout; |
1da177e4 | 923 | dev->watchdog_timeo = TX_TIMEOUT; |
b27a16b7 | 924 | |
1da177e4 LT |
925 | #ifdef CONFIG_NET_POLL_CONTROLLER |
926 | dev->poll_controller = &natsemi_poll_controller; | |
927 | #endif | |
928 | SET_ETHTOOL_OPS(dev, ðtool_ops); | |
929 | ||
930 | if (mtu) | |
931 | dev->mtu = mtu; | |
932 | ||
5a40f09b | 933 | natsemi_init_media(dev); |
1da177e4 LT |
934 | |
935 | /* save the silicon revision for later querying */ | |
936 | np->srr = readl(ioaddr + SiliconRev); | |
937 | if (netif_msg_hw(np)) | |
938 | printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n", | |
939 | pci_name(np->pci_dev), np->srr); | |
940 | ||
941 | i = register_netdev(dev); | |
942 | if (i) | |
943 | goto err_register_netdev; | |
944 | ||
1a147809 MB |
945 | if (NATSEMI_CREATE_FILE(pdev, dspcfg_workaround)) |
946 | goto err_create_file; | |
947 | ||
1da177e4 | 948 | if (netif_msg_drv(np)) { |
703bb99c | 949 | printk(KERN_INFO "natsemi %s: %s at %#08llx " |
e174961c | 950 | "(%s), %pM, IRQ %d", |
703bb99c SS |
951 | dev->name, natsemi_pci_info[chip_idx].name, |
952 | (unsigned long long)iostart, pci_name(np->pci_dev), | |
e174961c | 953 | dev->dev_addr, irq); |
1da177e4 LT |
954 | if (dev->if_port == PORT_TP) |
955 | printk(", port TP.\n"); | |
68c90166 MB |
956 | else if (np->ignore_phy) |
957 | printk(", port MII, ignoring PHY\n"); | |
1da177e4 LT |
958 | else |
959 | printk(", port MII, phy ad %d.\n", np->phy_addr_external); | |
960 | } | |
961 | return 0; | |
962 | ||
1a147809 MB |
963 | err_create_file: |
964 | unregister_netdev(dev); | |
965 | ||
1da177e4 LT |
966 | err_register_netdev: |
967 | iounmap(ioaddr); | |
968 | ||
969 | err_ioremap: | |
970 | pci_release_regions(pdev); | |
971 | pci_set_drvdata(pdev, NULL); | |
972 | ||
973 | err_pci_request_regions: | |
974 | free_netdev(dev); | |
975 | return i; | |
976 | } | |
977 | ||
978 | ||
979 | /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. | |
980 | The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */ | |
981 | ||
982 | /* Delay between EEPROM clock transitions. | |
983 | No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need | |
984 | a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that | |
985 | made udelay() unreliable. | |
986 | The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is | |
405bbe9f | 987 | deprecated. |
1da177e4 LT |
988 | */ |
989 | #define eeprom_delay(ee_addr) readl(ee_addr) | |
990 | ||
991 | #define EE_Write0 (EE_ChipSelect) | |
992 | #define EE_Write1 (EE_ChipSelect | EE_DataIn) | |
993 | ||
994 | /* The EEPROM commands include the alway-set leading bit. */ | |
995 | enum EEPROM_Cmds { | |
996 | EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6), | |
997 | }; | |
998 | ||
999 | static int eeprom_read(void __iomem *addr, int location) | |
1000 | { | |
1001 | int i; | |
1002 | int retval = 0; | |
1003 | void __iomem *ee_addr = addr + EECtrl; | |
1004 | int read_cmd = location | EE_ReadCmd; | |
1005 | ||
1006 | writel(EE_Write0, ee_addr); | |
1007 | ||
1008 | /* Shift the read command bits out. */ | |
1009 | for (i = 10; i >= 0; i--) { | |
1010 | short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0; | |
1011 | writel(dataval, ee_addr); | |
1012 | eeprom_delay(ee_addr); | |
1013 | writel(dataval | EE_ShiftClk, ee_addr); | |
1014 | eeprom_delay(ee_addr); | |
1015 | } | |
1016 | writel(EE_ChipSelect, ee_addr); | |
1017 | eeprom_delay(ee_addr); | |
1018 | ||
1019 | for (i = 0; i < 16; i++) { | |
1020 | writel(EE_ChipSelect | EE_ShiftClk, ee_addr); | |
1021 | eeprom_delay(ee_addr); | |
1022 | retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0; | |
1023 | writel(EE_ChipSelect, ee_addr); | |
1024 | eeprom_delay(ee_addr); | |
1025 | } | |
1026 | ||
1027 | /* Terminate the EEPROM access. */ | |
1028 | writel(EE_Write0, ee_addr); | |
1029 | writel(0, ee_addr); | |
1030 | return retval; | |
1031 | } | |
1032 | ||
1033 | /* MII transceiver control section. | |
1034 | * The 83815 series has an internal transceiver, and we present the | |
1035 | * internal management registers as if they were MII connected. | |
1036 | * External Phy registers are referenced through the MII interface. | |
1037 | */ | |
1038 | ||
1039 | /* clock transitions >= 20ns (25MHz) | |
1040 | * One readl should be good to PCI @ 100MHz | |
1041 | */ | |
1042 | #define mii_delay(ioaddr) readl(ioaddr + EECtrl) | |
1043 | ||
1044 | static int mii_getbit (struct net_device *dev) | |
1045 | { | |
1046 | int data; | |
1047 | void __iomem *ioaddr = ns_ioaddr(dev); | |
1048 | ||
1049 | writel(MII_ShiftClk, ioaddr + EECtrl); | |
1050 | data = readl(ioaddr + EECtrl); | |
1051 | writel(0, ioaddr + EECtrl); | |
1052 | mii_delay(ioaddr); | |
1053 | return (data & MII_Data)? 1 : 0; | |
1054 | } | |
1055 | ||
1056 | static void mii_send_bits (struct net_device *dev, u32 data, int len) | |
1057 | { | |
1058 | u32 i; | |
1059 | void __iomem *ioaddr = ns_ioaddr(dev); | |
1060 | ||
1061 | for (i = (1 << (len-1)); i; i >>= 1) | |
1062 | { | |
1063 | u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0); | |
1064 | writel(mdio_val, ioaddr + EECtrl); | |
1065 | mii_delay(ioaddr); | |
1066 | writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl); | |
1067 | mii_delay(ioaddr); | |
1068 | } | |
1069 | writel(0, ioaddr + EECtrl); | |
1070 | mii_delay(ioaddr); | |
1071 | } | |
1072 | ||
1073 | static int miiport_read(struct net_device *dev, int phy_id, int reg) | |
1074 | { | |
1075 | u32 cmd; | |
1076 | int i; | |
1077 | u32 retval = 0; | |
1078 | ||
1079 | /* Ensure sync */ | |
1080 | mii_send_bits (dev, 0xffffffff, 32); | |
1081 | /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ | |
1082 | /* ST,OP = 0110'b for read operation */ | |
1083 | cmd = (0x06 << 10) | (phy_id << 5) | reg; | |
1084 | mii_send_bits (dev, cmd, 14); | |
1085 | /* Turnaround */ | |
1086 | if (mii_getbit (dev)) | |
1087 | return 0; | |
1088 | /* Read data */ | |
1089 | for (i = 0; i < 16; i++) { | |
1090 | retval <<= 1; | |
1091 | retval |= mii_getbit (dev); | |
1092 | } | |
1093 | /* End cycle */ | |
1094 | mii_getbit (dev); | |
1095 | return retval; | |
1096 | } | |
1097 | ||
1098 | static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data) | |
1099 | { | |
1100 | u32 cmd; | |
1101 | ||
1102 | /* Ensure sync */ | |
1103 | mii_send_bits (dev, 0xffffffff, 32); | |
1104 | /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ | |
1105 | /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */ | |
1106 | cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data; | |
1107 | mii_send_bits (dev, cmd, 32); | |
1108 | /* End cycle */ | |
1109 | mii_getbit (dev); | |
1110 | } | |
1111 | ||
1112 | static int mdio_read(struct net_device *dev, int reg) | |
1113 | { | |
1114 | struct netdev_private *np = netdev_priv(dev); | |
1115 | void __iomem *ioaddr = ns_ioaddr(dev); | |
1116 | ||
1117 | /* The 83815 series has two ports: | |
1118 | * - an internal transceiver | |
1119 | * - an external mii bus | |
1120 | */ | |
1121 | if (dev->if_port == PORT_TP) | |
1122 | return readw(ioaddr+BasicControl+(reg<<2)); | |
1123 | else | |
1124 | return miiport_read(dev, np->phy_addr_external, reg); | |
1125 | } | |
1126 | ||
1127 | static void mdio_write(struct net_device *dev, int reg, u16 data) | |
1128 | { | |
1129 | struct netdev_private *np = netdev_priv(dev); | |
1130 | void __iomem *ioaddr = ns_ioaddr(dev); | |
1131 | ||
1132 | /* The 83815 series has an internal transceiver; handle separately */ | |
1133 | if (dev->if_port == PORT_TP) | |
1134 | writew(data, ioaddr+BasicControl+(reg<<2)); | |
1135 | else | |
1136 | miiport_write(dev, np->phy_addr_external, reg, data); | |
1137 | } | |
1138 | ||
1139 | static void init_phy_fixup(struct net_device *dev) | |
1140 | { | |
1141 | struct netdev_private *np = netdev_priv(dev); | |
1142 | void __iomem *ioaddr = ns_ioaddr(dev); | |
1143 | int i; | |
1144 | u32 cfg; | |
1145 | u16 tmp; | |
1146 | ||
1147 | /* restore stuff lost when power was out */ | |
1148 | tmp = mdio_read(dev, MII_BMCR); | |
1149 | if (np->autoneg == AUTONEG_ENABLE) { | |
1150 | /* renegotiate if something changed */ | |
1151 | if ((tmp & BMCR_ANENABLE) == 0 | |
1152 | || np->advertising != mdio_read(dev, MII_ADVERTISE)) | |
1153 | { | |
1154 | /* turn on autonegotiation and force negotiation */ | |
1155 | tmp |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
1156 | mdio_write(dev, MII_ADVERTISE, np->advertising); | |
1157 | } | |
1158 | } else { | |
1159 | /* turn off auto negotiation, set speed and duplexity */ | |
1160 | tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX); | |
1161 | if (np->speed == SPEED_100) | |
1162 | tmp |= BMCR_SPEED100; | |
1163 | if (np->duplex == DUPLEX_FULL) | |
1164 | tmp |= BMCR_FULLDPLX; | |
6aa20a22 | 1165 | /* |
1da177e4 LT |
1166 | * Note: there is no good way to inform the link partner |
1167 | * that our capabilities changed. The user has to unplug | |
1168 | * and replug the network cable after some changes, e.g. | |
1169 | * after switching from 10HD, autoneg off to 100 HD, | |
1170 | * autoneg off. | |
1171 | */ | |
1172 | } | |
1173 | mdio_write(dev, MII_BMCR, tmp); | |
1174 | readl(ioaddr + ChipConfig); | |
1175 | udelay(1); | |
1176 | ||
1177 | /* find out what phy this is */ | |
1178 | np->mii = (mdio_read(dev, MII_PHYSID1) << 16) | |
1179 | + mdio_read(dev, MII_PHYSID2); | |
1180 | ||
1181 | /* handle external phys here */ | |
1182 | switch (np->mii) { | |
1183 | case PHYID_AM79C874: | |
1184 | /* phy specific configuration for fibre/tp operation */ | |
1185 | tmp = mdio_read(dev, MII_MCTRL); | |
1186 | tmp &= ~(MII_FX_SEL | MII_EN_SCRM); | |
1187 | if (dev->if_port == PORT_FIBRE) | |
1188 | tmp |= MII_FX_SEL; | |
1189 | else | |
1190 | tmp |= MII_EN_SCRM; | |
1191 | mdio_write(dev, MII_MCTRL, tmp); | |
1192 | break; | |
1193 | default: | |
1194 | break; | |
1195 | } | |
1196 | cfg = readl(ioaddr + ChipConfig); | |
1197 | if (cfg & CfgExtPhy) | |
1198 | return; | |
1199 | ||
1200 | /* On page 78 of the spec, they recommend some settings for "optimum | |
1201 | performance" to be done in sequence. These settings optimize some | |
1202 | of the 100Mbit autodetection circuitry. They say we only want to | |
1203 | do this for rev C of the chip, but engineers at NSC (Bradley | |
1204 | Kennedy) recommends always setting them. If you don't, you get | |
1205 | errors on some autonegotiations that make the device unusable. | |
1206 | ||
1207 | It seems that the DSP needs a few usec to reinitialize after | |
1208 | the start of the phy. Just retry writing these values until they | |
1209 | stick. | |
1210 | */ | |
1211 | for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { | |
1212 | ||
1213 | int dspcfg; | |
1214 | writew(1, ioaddr + PGSEL); | |
1215 | writew(PMDCSR_VAL, ioaddr + PMDCSR); | |
1216 | writew(TSTDAT_VAL, ioaddr + TSTDAT); | |
1217 | np->dspcfg = (np->srr <= SRR_DP83815_C)? | |
1218 | DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG)); | |
1219 | writew(np->dspcfg, ioaddr + DSPCFG); | |
1220 | writew(SDCFG_VAL, ioaddr + SDCFG); | |
1221 | writew(0, ioaddr + PGSEL); | |
1222 | readl(ioaddr + ChipConfig); | |
1223 | udelay(10); | |
1224 | ||
1225 | writew(1, ioaddr + PGSEL); | |
1226 | dspcfg = readw(ioaddr + DSPCFG); | |
1227 | writew(0, ioaddr + PGSEL); | |
1228 | if (np->dspcfg == dspcfg) | |
1229 | break; | |
1230 | } | |
1231 | ||
1232 | if (netif_msg_link(np)) { | |
1233 | if (i==NATSEMI_HW_TIMEOUT) { | |
1234 | printk(KERN_INFO | |
1235 | "%s: DSPCFG mismatch after retrying for %d usec.\n", | |
1236 | dev->name, i*10); | |
1237 | } else { | |
1238 | printk(KERN_INFO | |
1239 | "%s: DSPCFG accepted after %d usec.\n", | |
1240 | dev->name, i*10); | |
1241 | } | |
1242 | } | |
1243 | /* | |
1244 | * Enable PHY Specific event based interrupts. Link state change | |
1245 | * and Auto-Negotiation Completion are among the affected. | |
1246 | * Read the intr status to clear it (needed for wake events). | |
1247 | */ | |
1248 | readw(ioaddr + MIntrStatus); | |
1249 | writew(MICRIntEn, ioaddr + MIntrCtrl); | |
1250 | } | |
1251 | ||
1252 | static int switch_port_external(struct net_device *dev) | |
1253 | { | |
1254 | struct netdev_private *np = netdev_priv(dev); | |
1255 | void __iomem *ioaddr = ns_ioaddr(dev); | |
1256 | u32 cfg; | |
1257 | ||
1258 | cfg = readl(ioaddr + ChipConfig); | |
1259 | if (cfg & CfgExtPhy) | |
1260 | return 0; | |
1261 | ||
1262 | if (netif_msg_link(np)) { | |
1263 | printk(KERN_INFO "%s: switching to external transceiver.\n", | |
1264 | dev->name); | |
1265 | } | |
1266 | ||
1267 | /* 1) switch back to external phy */ | |
1268 | writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig); | |
1269 | readl(ioaddr + ChipConfig); | |
1270 | udelay(1); | |
1271 | ||
1272 | /* 2) reset the external phy: */ | |
1273 | /* resetting the external PHY has been known to cause a hub supplying | |
1274 | * power over Ethernet to kill the power. We don't want to kill | |
1275 | * power to this computer, so we avoid resetting the phy. | |
1276 | */ | |
1277 | ||
1278 | /* 3) reinit the phy fixup, it got lost during power down. */ | |
1279 | move_int_phy(dev, np->phy_addr_external); | |
1280 | init_phy_fixup(dev); | |
1281 | ||
1282 | return 1; | |
1283 | } | |
1284 | ||
1285 | static int switch_port_internal(struct net_device *dev) | |
1286 | { | |
1287 | struct netdev_private *np = netdev_priv(dev); | |
1288 | void __iomem *ioaddr = ns_ioaddr(dev); | |
1289 | int i; | |
1290 | u32 cfg; | |
1291 | u16 bmcr; | |
1292 | ||
1293 | cfg = readl(ioaddr + ChipConfig); | |
1294 | if (!(cfg &CfgExtPhy)) | |
1295 | return 0; | |
1296 | ||
1297 | if (netif_msg_link(np)) { | |
1298 | printk(KERN_INFO "%s: switching to internal transceiver.\n", | |
1299 | dev->name); | |
1300 | } | |
1301 | /* 1) switch back to internal phy: */ | |
1302 | cfg = cfg & ~(CfgExtPhy | CfgPhyDis); | |
1303 | writel(cfg, ioaddr + ChipConfig); | |
1304 | readl(ioaddr + ChipConfig); | |
1305 | udelay(1); | |
6aa20a22 | 1306 | |
1da177e4 LT |
1307 | /* 2) reset the internal phy: */ |
1308 | bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2)); | |
1309 | writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2)); | |
1310 | readl(ioaddr + ChipConfig); | |
1311 | udelay(10); | |
1312 | for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { | |
1313 | bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2)); | |
1314 | if (!(bmcr & BMCR_RESET)) | |
1315 | break; | |
1316 | udelay(10); | |
1317 | } | |
1318 | if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) { | |
1319 | printk(KERN_INFO | |
1320 | "%s: phy reset did not complete in %d usec.\n", | |
1321 | dev->name, i*10); | |
1322 | } | |
1323 | /* 3) reinit the phy fixup, it got lost during power down. */ | |
1324 | init_phy_fixup(dev); | |
1325 | ||
1326 | return 1; | |
1327 | } | |
1328 | ||
1329 | /* Scan for a PHY on the external mii bus. | |
1330 | * There are two tricky points: | |
1331 | * - Do not scan while the internal phy is enabled. The internal phy will | |
1332 | * crash: e.g. reads from the DSPCFG register will return odd values and | |
1333 | * the nasty random phy reset code will reset the nic every few seconds. | |
1334 | * - The internal phy must be moved around, an external phy could | |
1335 | * have the same address as the internal phy. | |
1336 | */ | |
1337 | static int find_mii(struct net_device *dev) | |
1338 | { | |
1339 | struct netdev_private *np = netdev_priv(dev); | |
1340 | int tmp; | |
1341 | int i; | |
1342 | int did_switch; | |
1343 | ||
1344 | /* Switch to external phy */ | |
1345 | did_switch = switch_port_external(dev); | |
6aa20a22 | 1346 | |
1da177e4 LT |
1347 | /* Scan the possible phy addresses: |
1348 | * | |
1349 | * PHY address 0 means that the phy is in isolate mode. Not yet | |
1350 | * supported due to lack of test hardware. User space should | |
1351 | * handle it through ethtool. | |
1352 | */ | |
1353 | for (i = 1; i <= 31; i++) { | |
1354 | move_int_phy(dev, i); | |
1355 | tmp = miiport_read(dev, i, MII_BMSR); | |
1356 | if (tmp != 0xffff && tmp != 0x0000) { | |
1357 | /* found something! */ | |
1358 | np->mii = (mdio_read(dev, MII_PHYSID1) << 16) | |
1359 | + mdio_read(dev, MII_PHYSID2); | |
1360 | if (netif_msg_probe(np)) { | |
1361 | printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n", | |
1362 | pci_name(np->pci_dev), np->mii, i); | |
1363 | } | |
1364 | break; | |
1365 | } | |
1366 | } | |
1367 | /* And switch back to internal phy: */ | |
1368 | if (did_switch) | |
1369 | switch_port_internal(dev); | |
1370 | return i; | |
1371 | } | |
1372 | ||
1373 | /* CFG bits [13:16] [18:23] */ | |
1374 | #define CFG_RESET_SAVE 0xfde000 | |
1375 | /* WCSR bits [0:4] [9:10] */ | |
1376 | #define WCSR_RESET_SAVE 0x61f | |
1377 | /* RFCR bits [20] [22] [27:31] */ | |
1378 | #define RFCR_RESET_SAVE 0xf8500000; | |
1379 | ||
1380 | static void natsemi_reset(struct net_device *dev) | |
1381 | { | |
1382 | int i; | |
1383 | u32 cfg; | |
1384 | u32 wcsr; | |
1385 | u32 rfcr; | |
1386 | u16 pmatch[3]; | |
1387 | u16 sopass[3]; | |
1388 | struct netdev_private *np = netdev_priv(dev); | |
1389 | void __iomem *ioaddr = ns_ioaddr(dev); | |
1390 | ||
1391 | /* | |
1392 | * Resetting the chip causes some registers to be lost. | |
1393 | * Natsemi suggests NOT reloading the EEPROM while live, so instead | |
1394 | * we save the state that would have been loaded from EEPROM | |
1395 | * on a normal power-up (see the spec EEPROM map). This assumes | |
1396 | * whoever calls this will follow up with init_registers() eventually. | |
1397 | */ | |
1398 | ||
1399 | /* CFG */ | |
1400 | cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE; | |
1401 | /* WCSR */ | |
1402 | wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE; | |
1403 | /* RFCR */ | |
1404 | rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE; | |
1405 | /* PMATCH */ | |
1406 | for (i = 0; i < 3; i++) { | |
1407 | writel(i*2, ioaddr + RxFilterAddr); | |
1408 | pmatch[i] = readw(ioaddr + RxFilterData); | |
1409 | } | |
1410 | /* SOPAS */ | |
1411 | for (i = 0; i < 3; i++) { | |
1412 | writel(0xa+(i*2), ioaddr + RxFilterAddr); | |
1413 | sopass[i] = readw(ioaddr + RxFilterData); | |
1414 | } | |
1415 | ||
1416 | /* now whack the chip */ | |
1417 | writel(ChipReset, ioaddr + ChipCmd); | |
1418 | for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { | |
1419 | if (!(readl(ioaddr + ChipCmd) & ChipReset)) | |
1420 | break; | |
1421 | udelay(5); | |
1422 | } | |
1423 | if (i==NATSEMI_HW_TIMEOUT) { | |
1424 | printk(KERN_WARNING "%s: reset did not complete in %d usec.\n", | |
1425 | dev->name, i*5); | |
1426 | } else if (netif_msg_hw(np)) { | |
1427 | printk(KERN_DEBUG "%s: reset completed in %d usec.\n", | |
1428 | dev->name, i*5); | |
1429 | } | |
1430 | ||
1431 | /* restore CFG */ | |
1432 | cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE; | |
1433 | /* turn on external phy if it was selected */ | |
1434 | if (dev->if_port == PORT_TP) | |
1435 | cfg &= ~(CfgExtPhy | CfgPhyDis); | |
1436 | else | |
1437 | cfg |= (CfgExtPhy | CfgPhyDis); | |
1438 | writel(cfg, ioaddr + ChipConfig); | |
1439 | /* restore WCSR */ | |
1440 | wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE; | |
1441 | writel(wcsr, ioaddr + WOLCmd); | |
1442 | /* read RFCR */ | |
1443 | rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE; | |
1444 | /* restore PMATCH */ | |
1445 | for (i = 0; i < 3; i++) { | |
1446 | writel(i*2, ioaddr + RxFilterAddr); | |
1447 | writew(pmatch[i], ioaddr + RxFilterData); | |
1448 | } | |
1449 | for (i = 0; i < 3; i++) { | |
1450 | writel(0xa+(i*2), ioaddr + RxFilterAddr); | |
1451 | writew(sopass[i], ioaddr + RxFilterData); | |
1452 | } | |
1453 | /* restore RFCR */ | |
1454 | writel(rfcr, ioaddr + RxFilterAddr); | |
1455 | } | |
1456 | ||
e72fd96e MB |
1457 | static void reset_rx(struct net_device *dev) |
1458 | { | |
1459 | int i; | |
1460 | struct netdev_private *np = netdev_priv(dev); | |
1461 | void __iomem *ioaddr = ns_ioaddr(dev); | |
1462 | ||
1463 | np->intr_status &= ~RxResetDone; | |
1464 | ||
1465 | writel(RxReset, ioaddr + ChipCmd); | |
1466 | ||
1467 | for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { | |
1468 | np->intr_status |= readl(ioaddr + IntrStatus); | |
1469 | if (np->intr_status & RxResetDone) | |
1470 | break; | |
1471 | udelay(15); | |
1472 | } | |
1473 | if (i==NATSEMI_HW_TIMEOUT) { | |
1474 | printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n", | |
1475 | dev->name, i*15); | |
1476 | } else if (netif_msg_hw(np)) { | |
1477 | printk(KERN_WARNING "%s: RX reset took %d usec.\n", | |
1478 | dev->name, i*15); | |
1479 | } | |
1480 | } | |
1481 | ||
1da177e4 LT |
1482 | static void natsemi_reload_eeprom(struct net_device *dev) |
1483 | { | |
1484 | struct netdev_private *np = netdev_priv(dev); | |
1485 | void __iomem *ioaddr = ns_ioaddr(dev); | |
1486 | int i; | |
1487 | ||
1488 | writel(EepromReload, ioaddr + PCIBusCfg); | |
1489 | for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { | |
1490 | udelay(50); | |
1491 | if (!(readl(ioaddr + PCIBusCfg) & EepromReload)) | |
1492 | break; | |
1493 | } | |
1494 | if (i==NATSEMI_HW_TIMEOUT) { | |
1495 | printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n", | |
1496 | pci_name(np->pci_dev), i*50); | |
1497 | } else if (netif_msg_hw(np)) { | |
1498 | printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n", | |
1499 | pci_name(np->pci_dev), i*50); | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | static void natsemi_stop_rxtx(struct net_device *dev) | |
1504 | { | |
1505 | void __iomem * ioaddr = ns_ioaddr(dev); | |
1506 | struct netdev_private *np = netdev_priv(dev); | |
1507 | int i; | |
1508 | ||
1509 | writel(RxOff | TxOff, ioaddr + ChipCmd); | |
1510 | for(i=0;i< NATSEMI_HW_TIMEOUT;i++) { | |
1511 | if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0) | |
1512 | break; | |
1513 | udelay(5); | |
1514 | } | |
1515 | if (i==NATSEMI_HW_TIMEOUT) { | |
1516 | printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n", | |
1517 | dev->name, i*5); | |
1518 | } else if (netif_msg_hw(np)) { | |
1519 | printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n", | |
1520 | dev->name, i*5); | |
1521 | } | |
1522 | } | |
1523 | ||
1524 | static int netdev_open(struct net_device *dev) | |
1525 | { | |
1526 | struct netdev_private *np = netdev_priv(dev); | |
1527 | void __iomem * ioaddr = ns_ioaddr(dev); | |
1528 | int i; | |
1529 | ||
1530 | /* Reset the chip, just in case. */ | |
1531 | natsemi_reset(dev); | |
1532 | ||
1fb9df5d | 1533 | i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev); |
1da177e4 LT |
1534 | if (i) return i; |
1535 | ||
1536 | if (netif_msg_ifup(np)) | |
1537 | printk(KERN_DEBUG "%s: netdev_open() irq %d.\n", | |
1538 | dev->name, dev->irq); | |
1539 | i = alloc_ring(dev); | |
1540 | if (i < 0) { | |
1541 | free_irq(dev->irq, dev); | |
1542 | return i; | |
1543 | } | |
bea3348e SH |
1544 | napi_enable(&np->napi); |
1545 | ||
1da177e4 LT |
1546 | init_ring(dev); |
1547 | spin_lock_irq(&np->lock); | |
1548 | init_registers(dev); | |
1549 | /* now set the MAC address according to dev->dev_addr */ | |
1550 | for (i = 0; i < 3; i++) { | |
1551 | u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i]; | |
1552 | ||
1553 | writel(i*2, ioaddr + RxFilterAddr); | |
1554 | writew(mac, ioaddr + RxFilterData); | |
1555 | } | |
1556 | writel(np->cur_rx_mode, ioaddr + RxFilterAddr); | |
1557 | spin_unlock_irq(&np->lock); | |
1558 | ||
1559 | netif_start_queue(dev); | |
1560 | ||
1561 | if (netif_msg_ifup(np)) | |
1562 | printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n", | |
1563 | dev->name, (int)readl(ioaddr + ChipCmd)); | |
1564 | ||
1565 | /* Set the timer to check for link beat. */ | |
1566 | init_timer(&np->timer); | |
0e5d5442 | 1567 | np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ); |
1da177e4 LT |
1568 | np->timer.data = (unsigned long)dev; |
1569 | np->timer.function = &netdev_timer; /* timer handler */ | |
1570 | add_timer(&np->timer); | |
1571 | ||
1572 | return 0; | |
1573 | } | |
1574 | ||
1575 | static void do_cable_magic(struct net_device *dev) | |
1576 | { | |
1577 | struct netdev_private *np = netdev_priv(dev); | |
1578 | void __iomem *ioaddr = ns_ioaddr(dev); | |
1579 | ||
1580 | if (dev->if_port != PORT_TP) | |
1581 | return; | |
1582 | ||
1583 | if (np->srr >= SRR_DP83816_A5) | |
1584 | return; | |
1585 | ||
1586 | /* | |
1587 | * 100 MBit links with short cables can trip an issue with the chip. | |
1588 | * The problem manifests as lots of CRC errors and/or flickering | |
1589 | * activity LED while idle. This process is based on instructions | |
1590 | * from engineers at National. | |
1591 | */ | |
1592 | if (readl(ioaddr + ChipConfig) & CfgSpeed100) { | |
1593 | u16 data; | |
1594 | ||
1595 | writew(1, ioaddr + PGSEL); | |
1596 | /* | |
1597 | * coefficient visibility should already be enabled via | |
1598 | * DSPCFG | 0x1000 | |
1599 | */ | |
1600 | data = readw(ioaddr + TSTDAT) & 0xff; | |
1601 | /* | |
1602 | * the value must be negative, and within certain values | |
1603 | * (these values all come from National) | |
1604 | */ | |
1605 | if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) { | |
ddfce6bb | 1606 | np = netdev_priv(dev); |
1da177e4 LT |
1607 | |
1608 | /* the bug has been triggered - fix the coefficient */ | |
1609 | writew(TSTDAT_FIXED, ioaddr + TSTDAT); | |
1610 | /* lock the value */ | |
1611 | data = readw(ioaddr + DSPCFG); | |
1612 | np->dspcfg = data | DSPCFG_LOCK; | |
1613 | writew(np->dspcfg, ioaddr + DSPCFG); | |
1614 | } | |
1615 | writew(0, ioaddr + PGSEL); | |
1616 | } | |
1617 | } | |
1618 | ||
1619 | static void undo_cable_magic(struct net_device *dev) | |
1620 | { | |
1621 | u16 data; | |
1622 | struct netdev_private *np = netdev_priv(dev); | |
1623 | void __iomem * ioaddr = ns_ioaddr(dev); | |
1624 | ||
1625 | if (dev->if_port != PORT_TP) | |
1626 | return; | |
1627 | ||
1628 | if (np->srr >= SRR_DP83816_A5) | |
1629 | return; | |
1630 | ||
1631 | writew(1, ioaddr + PGSEL); | |
1632 | /* make sure the lock bit is clear */ | |
1633 | data = readw(ioaddr + DSPCFG); | |
1634 | np->dspcfg = data & ~DSPCFG_LOCK; | |
1635 | writew(np->dspcfg, ioaddr + DSPCFG); | |
1636 | writew(0, ioaddr + PGSEL); | |
1637 | } | |
1638 | ||
1639 | static void check_link(struct net_device *dev) | |
1640 | { | |
1641 | struct netdev_private *np = netdev_priv(dev); | |
1642 | void __iomem * ioaddr = ns_ioaddr(dev); | |
68c90166 | 1643 | int duplex = np->duplex; |
1da177e4 | 1644 | u16 bmsr; |
6aa20a22 | 1645 | |
68c90166 MB |
1646 | /* If we are ignoring the PHY then don't try reading it. */ |
1647 | if (np->ignore_phy) | |
1648 | goto propagate_state; | |
1649 | ||
1da177e4 LT |
1650 | /* The link status field is latched: it remains low after a temporary |
1651 | * link failure until it's read. We need the current link status, | |
1652 | * thus read twice. | |
1653 | */ | |
1654 | mdio_read(dev, MII_BMSR); | |
1655 | bmsr = mdio_read(dev, MII_BMSR); | |
1656 | ||
1657 | if (!(bmsr & BMSR_LSTATUS)) { | |
1658 | if (netif_carrier_ok(dev)) { | |
1659 | if (netif_msg_link(np)) | |
1660 | printk(KERN_NOTICE "%s: link down.\n", | |
68c90166 | 1661 | dev->name); |
1da177e4 LT |
1662 | netif_carrier_off(dev); |
1663 | undo_cable_magic(dev); | |
1664 | } | |
1665 | return; | |
1666 | } | |
1667 | if (!netif_carrier_ok(dev)) { | |
1668 | if (netif_msg_link(np)) | |
1669 | printk(KERN_NOTICE "%s: link up.\n", dev->name); | |
1670 | netif_carrier_on(dev); | |
1671 | do_cable_magic(dev); | |
1672 | } | |
1673 | ||
1674 | duplex = np->full_duplex; | |
1675 | if (!duplex) { | |
1676 | if (bmsr & BMSR_ANEGCOMPLETE) { | |
1677 | int tmp = mii_nway_result( | |
1678 | np->advertising & mdio_read(dev, MII_LPA)); | |
1679 | if (tmp == LPA_100FULL || tmp == LPA_10FULL) | |
1680 | duplex = 1; | |
1681 | } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX) | |
1682 | duplex = 1; | |
1683 | } | |
1684 | ||
68c90166 | 1685 | propagate_state: |
1da177e4 LT |
1686 | /* if duplex is set then bit 28 must be set, too */ |
1687 | if (duplex ^ !!(np->rx_config & RxAcceptTx)) { | |
1688 | if (netif_msg_link(np)) | |
1689 | printk(KERN_INFO | |
1690 | "%s: Setting %s-duplex based on negotiated " | |
1691 | "link capability.\n", dev->name, | |
1692 | duplex ? "full" : "half"); | |
1693 | if (duplex) { | |
1694 | np->rx_config |= RxAcceptTx; | |
1695 | np->tx_config |= TxCarrierIgn | TxHeartIgn; | |
1696 | } else { | |
1697 | np->rx_config &= ~RxAcceptTx; | |
1698 | np->tx_config &= ~(TxCarrierIgn | TxHeartIgn); | |
1699 | } | |
1700 | writel(np->tx_config, ioaddr + TxConfig); | |
1701 | writel(np->rx_config, ioaddr + RxConfig); | |
1702 | } | |
1703 | } | |
1704 | ||
1705 | static void init_registers(struct net_device *dev) | |
1706 | { | |
1707 | struct netdev_private *np = netdev_priv(dev); | |
1708 | void __iomem * ioaddr = ns_ioaddr(dev); | |
1709 | ||
1710 | init_phy_fixup(dev); | |
1711 | ||
1712 | /* clear any interrupts that are pending, such as wake events */ | |
1713 | readl(ioaddr + IntrStatus); | |
1714 | ||
1715 | writel(np->ring_dma, ioaddr + RxRingPtr); | |
1716 | writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc), | |
1717 | ioaddr + TxRingPtr); | |
1718 | ||
1719 | /* Initialize other registers. | |
1720 | * Configure the PCI bus bursts and FIFO thresholds. | |
1721 | * Configure for standard, in-spec Ethernet. | |
1722 | * Start with half-duplex. check_link will update | |
1723 | * to the correct settings. | |
1724 | */ | |
1725 | ||
1726 | /* DRTH: 2: start tx if 64 bytes are in the fifo | |
1727 | * FLTH: 0x10: refill with next packet if 512 bytes are free | |
1728 | * MXDMA: 0: up to 256 byte bursts. | |
1729 | * MXDMA must be <= FLTH | |
1730 | * ECRETRY=1 | |
1731 | * ATP=1 | |
1732 | */ | |
1733 | np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | | |
1734 | TX_FLTH_VAL | TX_DRTH_VAL_START; | |
1735 | writel(np->tx_config, ioaddr + TxConfig); | |
1736 | ||
1737 | /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo | |
1738 | * MXDMA 0: up to 256 byte bursts | |
1739 | */ | |
1740 | np->rx_config = RxMxdma_256 | RX_DRTH_VAL; | |
1741 | /* if receive ring now has bigger buffers than normal, enable jumbo */ | |
1742 | if (np->rx_buf_sz > NATSEMI_LONGPKT) | |
1743 | np->rx_config |= RxAcceptLong; | |
1744 | ||
1745 | writel(np->rx_config, ioaddr + RxConfig); | |
1746 | ||
1747 | /* Disable PME: | |
1748 | * The PME bit is initialized from the EEPROM contents. | |
1749 | * PCI cards probably have PME disabled, but motherboard | |
1750 | * implementations may have PME set to enable WakeOnLan. | |
1751 | * With PME set the chip will scan incoming packets but | |
1752 | * nothing will be written to memory. */ | |
1753 | np->SavedClkRun = readl(ioaddr + ClkRun); | |
1754 | writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun); | |
1755 | if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) { | |
1756 | printk(KERN_NOTICE "%s: Wake-up event %#08x\n", | |
1757 | dev->name, readl(ioaddr + WOLCmd)); | |
1758 | } | |
1759 | ||
1760 | check_link(dev); | |
1761 | __set_rx_mode(dev); | |
1762 | ||
1763 | /* Enable interrupts by setting the interrupt mask. */ | |
1764 | writel(DEFAULT_INTR, ioaddr + IntrMask); | |
14fdd90e | 1765 | natsemi_irq_enable(dev); |
1da177e4 LT |
1766 | |
1767 | writel(RxOn | TxOn, ioaddr + ChipCmd); | |
1768 | writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */ | |
1769 | } | |
1770 | ||
1771 | /* | |
1772 | * netdev_timer: | |
1773 | * Purpose: | |
1774 | * 1) check for link changes. Usually they are handled by the MII interrupt | |
1775 | * but it doesn't hurt to check twice. | |
1776 | * 2) check for sudden death of the NIC: | |
1777 | * It seems that a reference set for this chip went out with incorrect info, | |
1778 | * and there exist boards that aren't quite right. An unexpected voltage | |
1779 | * drop can cause the PHY to get itself in a weird state (basically reset). | |
1a147809 MB |
1780 | * NOTE: this only seems to affect revC chips. The user can disable |
1781 | * this check via dspcfg_workaround sysfs option. | |
1da177e4 LT |
1782 | * 3) check of death of the RX path due to OOM |
1783 | */ | |
1784 | static void netdev_timer(unsigned long data) | |
1785 | { | |
1786 | struct net_device *dev = (struct net_device *)data; | |
1787 | struct netdev_private *np = netdev_priv(dev); | |
1788 | void __iomem * ioaddr = ns_ioaddr(dev); | |
f2cade13 | 1789 | int next_tick = NATSEMI_TIMER_FREQ; |
1da177e4 LT |
1790 | |
1791 | if (netif_msg_timer(np)) { | |
1792 | /* DO NOT read the IntrStatus register, | |
1793 | * a read clears any pending interrupts. | |
1794 | */ | |
1795 | printk(KERN_DEBUG "%s: Media selection timer tick.\n", | |
1796 | dev->name); | |
1797 | } | |
1798 | ||
1799 | if (dev->if_port == PORT_TP) { | |
1800 | u16 dspcfg; | |
1801 | ||
1802 | spin_lock_irq(&np->lock); | |
1803 | /* check for a nasty random phy-reset - use dspcfg as a flag */ | |
1804 | writew(1, ioaddr+PGSEL); | |
1805 | dspcfg = readw(ioaddr+DSPCFG); | |
1806 | writew(0, ioaddr+PGSEL); | |
1a147809 | 1807 | if (np->dspcfg_workaround && dspcfg != np->dspcfg) { |
1da177e4 LT |
1808 | if (!netif_queue_stopped(dev)) { |
1809 | spin_unlock_irq(&np->lock); | |
d0ed4864 | 1810 | if (netif_msg_drv(np)) |
1da177e4 LT |
1811 | printk(KERN_NOTICE "%s: possible phy reset: " |
1812 | "re-initializing\n", dev->name); | |
1813 | disable_irq(dev->irq); | |
1814 | spin_lock_irq(&np->lock); | |
1815 | natsemi_stop_rxtx(dev); | |
1816 | dump_ring(dev); | |
1817 | reinit_ring(dev); | |
1818 | init_registers(dev); | |
1819 | spin_unlock_irq(&np->lock); | |
1820 | enable_irq(dev->irq); | |
1821 | } else { | |
1822 | /* hurry back */ | |
1823 | next_tick = HZ; | |
1824 | spin_unlock_irq(&np->lock); | |
1825 | } | |
1826 | } else { | |
1827 | /* init_registers() calls check_link() for the above case */ | |
1828 | check_link(dev); | |
1829 | spin_unlock_irq(&np->lock); | |
1830 | } | |
1831 | } else { | |
1832 | spin_lock_irq(&np->lock); | |
1833 | check_link(dev); | |
1834 | spin_unlock_irq(&np->lock); | |
1835 | } | |
1836 | if (np->oom) { | |
1837 | disable_irq(dev->irq); | |
1838 | np->oom = 0; | |
1839 | refill_rx(dev); | |
1840 | enable_irq(dev->irq); | |
1841 | if (!np->oom) { | |
1842 | writel(RxOn, ioaddr + ChipCmd); | |
1843 | } else { | |
1844 | next_tick = 1; | |
1845 | } | |
1846 | } | |
0e5d5442 MB |
1847 | |
1848 | if (next_tick > 1) | |
1849 | mod_timer(&np->timer, round_jiffies(jiffies + next_tick)); | |
1850 | else | |
1851 | mod_timer(&np->timer, jiffies + next_tick); | |
1da177e4 LT |
1852 | } |
1853 | ||
1854 | static void dump_ring(struct net_device *dev) | |
1855 | { | |
1856 | struct netdev_private *np = netdev_priv(dev); | |
1857 | ||
1858 | if (netif_msg_pktdata(np)) { | |
1859 | int i; | |
1860 | printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring); | |
1861 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1862 | printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n", | |
1863 | i, np->tx_ring[i].next_desc, | |
1864 | np->tx_ring[i].cmd_status, | |
1865 | np->tx_ring[i].addr); | |
1866 | } | |
1867 | printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring); | |
1868 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1869 | printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n", | |
1870 | i, np->rx_ring[i].next_desc, | |
1871 | np->rx_ring[i].cmd_status, | |
1872 | np->rx_ring[i].addr); | |
1873 | } | |
1874 | } | |
1875 | } | |
1876 | ||
ed4cb133 | 1877 | static void ns_tx_timeout(struct net_device *dev) |
1da177e4 LT |
1878 | { |
1879 | struct netdev_private *np = netdev_priv(dev); | |
1880 | void __iomem * ioaddr = ns_ioaddr(dev); | |
1881 | ||
1882 | disable_irq(dev->irq); | |
1883 | spin_lock_irq(&np->lock); | |
1884 | if (!np->hands_off) { | |
1885 | if (netif_msg_tx_err(np)) | |
1886 | printk(KERN_WARNING | |
1887 | "%s: Transmit timed out, status %#08x," | |
1888 | " resetting...\n", | |
1889 | dev->name, readl(ioaddr + IntrStatus)); | |
1890 | dump_ring(dev); | |
1891 | ||
1892 | natsemi_reset(dev); | |
1893 | reinit_ring(dev); | |
1894 | init_registers(dev); | |
1895 | } else { | |
1896 | printk(KERN_WARNING | |
1897 | "%s: tx_timeout while in hands_off state?\n", | |
1898 | dev->name); | |
1899 | } | |
1900 | spin_unlock_irq(&np->lock); | |
1901 | enable_irq(dev->irq); | |
1902 | ||
1903 | dev->trans_start = jiffies; | |
1904 | np->stats.tx_errors++; | |
1905 | netif_wake_queue(dev); | |
1906 | } | |
1907 | ||
1908 | static int alloc_ring(struct net_device *dev) | |
1909 | { | |
1910 | struct netdev_private *np = netdev_priv(dev); | |
1911 | np->rx_ring = pci_alloc_consistent(np->pci_dev, | |
1912 | sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE), | |
1913 | &np->ring_dma); | |
1914 | if (!np->rx_ring) | |
1915 | return -ENOMEM; | |
1916 | np->tx_ring = &np->rx_ring[RX_RING_SIZE]; | |
1917 | return 0; | |
1918 | } | |
1919 | ||
1920 | static void refill_rx(struct net_device *dev) | |
1921 | { | |
1922 | struct netdev_private *np = netdev_priv(dev); | |
1923 | ||
1924 | /* Refill the Rx ring buffers. */ | |
1925 | for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) { | |
1926 | struct sk_buff *skb; | |
1927 | int entry = np->dirty_rx % RX_RING_SIZE; | |
1928 | if (np->rx_skbuff[entry] == NULL) { | |
1929 | unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING; | |
1930 | skb = dev_alloc_skb(buflen); | |
1931 | np->rx_skbuff[entry] = skb; | |
1932 | if (skb == NULL) | |
1933 | break; /* Better luck next round. */ | |
1934 | skb->dev = dev; /* Mark as being used by this device. */ | |
1935 | np->rx_dma[entry] = pci_map_single(np->pci_dev, | |
689be439 | 1936 | skb->data, buflen, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
1937 | np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]); |
1938 | } | |
1939 | np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz); | |
1940 | } | |
1941 | if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) { | |
1942 | if (netif_msg_rx_err(np)) | |
1943 | printk(KERN_WARNING "%s: going OOM.\n", dev->name); | |
1944 | np->oom = 1; | |
1945 | } | |
1946 | } | |
1947 | ||
1948 | static void set_bufsize(struct net_device *dev) | |
1949 | { | |
1950 | struct netdev_private *np = netdev_priv(dev); | |
1951 | if (dev->mtu <= ETH_DATA_LEN) | |
1952 | np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS; | |
1953 | else | |
1954 | np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS; | |
1955 | } | |
1956 | ||
1957 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
1958 | static void init_ring(struct net_device *dev) | |
1959 | { | |
1960 | struct netdev_private *np = netdev_priv(dev); | |
1961 | int i; | |
1962 | ||
1963 | /* 1) TX ring */ | |
1964 | np->dirty_tx = np->cur_tx = 0; | |
1965 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1966 | np->tx_skbuff[i] = NULL; | |
1967 | np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma | |
1968 | +sizeof(struct netdev_desc) | |
1969 | *((i+1)%TX_RING_SIZE+RX_RING_SIZE)); | |
1970 | np->tx_ring[i].cmd_status = 0; | |
1971 | } | |
1972 | ||
1973 | /* 2) RX ring */ | |
1974 | np->dirty_rx = 0; | |
1975 | np->cur_rx = RX_RING_SIZE; | |
1976 | np->oom = 0; | |
1977 | set_bufsize(dev); | |
1978 | ||
1979 | np->rx_head_desc = &np->rx_ring[0]; | |
1980 | ||
1981 | /* Please be carefull before changing this loop - at least gcc-2.95.1 | |
1982 | * miscompiles it otherwise. | |
1983 | */ | |
1984 | /* Initialize all Rx descriptors. */ | |
1985 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1986 | np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma | |
1987 | +sizeof(struct netdev_desc) | |
1988 | *((i+1)%RX_RING_SIZE)); | |
1989 | np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn); | |
1990 | np->rx_skbuff[i] = NULL; | |
1991 | } | |
1992 | refill_rx(dev); | |
1993 | dump_ring(dev); | |
1994 | } | |
1995 | ||
1996 | static void drain_tx(struct net_device *dev) | |
1997 | { | |
1998 | struct netdev_private *np = netdev_priv(dev); | |
1999 | int i; | |
2000 | ||
2001 | for (i = 0; i < TX_RING_SIZE; i++) { | |
2002 | if (np->tx_skbuff[i]) { | |
2003 | pci_unmap_single(np->pci_dev, | |
2004 | np->tx_dma[i], np->tx_skbuff[i]->len, | |
2005 | PCI_DMA_TODEVICE); | |
2006 | dev_kfree_skb(np->tx_skbuff[i]); | |
2007 | np->stats.tx_dropped++; | |
2008 | } | |
2009 | np->tx_skbuff[i] = NULL; | |
2010 | } | |
2011 | } | |
2012 | ||
2013 | static void drain_rx(struct net_device *dev) | |
2014 | { | |
2015 | struct netdev_private *np = netdev_priv(dev); | |
2016 | unsigned int buflen = np->rx_buf_sz; | |
2017 | int i; | |
2018 | ||
2019 | /* Free all the skbuffs in the Rx queue. */ | |
2020 | for (i = 0; i < RX_RING_SIZE; i++) { | |
2021 | np->rx_ring[i].cmd_status = 0; | |
eca1ad82 | 2022 | np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ |
1da177e4 LT |
2023 | if (np->rx_skbuff[i]) { |
2024 | pci_unmap_single(np->pci_dev, | |
2025 | np->rx_dma[i], buflen, | |
2026 | PCI_DMA_FROMDEVICE); | |
2027 | dev_kfree_skb(np->rx_skbuff[i]); | |
2028 | } | |
2029 | np->rx_skbuff[i] = NULL; | |
2030 | } | |
2031 | } | |
2032 | ||
2033 | static void drain_ring(struct net_device *dev) | |
2034 | { | |
2035 | drain_rx(dev); | |
2036 | drain_tx(dev); | |
2037 | } | |
2038 | ||
2039 | static void free_ring(struct net_device *dev) | |
2040 | { | |
2041 | struct netdev_private *np = netdev_priv(dev); | |
2042 | pci_free_consistent(np->pci_dev, | |
2043 | sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE), | |
2044 | np->rx_ring, np->ring_dma); | |
2045 | } | |
2046 | ||
2047 | static void reinit_rx(struct net_device *dev) | |
2048 | { | |
2049 | struct netdev_private *np = netdev_priv(dev); | |
2050 | int i; | |
2051 | ||
2052 | /* RX Ring */ | |
2053 | np->dirty_rx = 0; | |
2054 | np->cur_rx = RX_RING_SIZE; | |
2055 | np->rx_head_desc = &np->rx_ring[0]; | |
2056 | /* Initialize all Rx descriptors. */ | |
2057 | for (i = 0; i < RX_RING_SIZE; i++) | |
2058 | np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn); | |
2059 | ||
2060 | refill_rx(dev); | |
2061 | } | |
2062 | ||
2063 | static void reinit_ring(struct net_device *dev) | |
2064 | { | |
2065 | struct netdev_private *np = netdev_priv(dev); | |
2066 | int i; | |
2067 | ||
2068 | /* drain TX ring */ | |
2069 | drain_tx(dev); | |
2070 | np->dirty_tx = np->cur_tx = 0; | |
2071 | for (i=0;i<TX_RING_SIZE;i++) | |
2072 | np->tx_ring[i].cmd_status = 0; | |
2073 | ||
2074 | reinit_rx(dev); | |
2075 | } | |
2076 | ||
2077 | static int start_tx(struct sk_buff *skb, struct net_device *dev) | |
2078 | { | |
2079 | struct netdev_private *np = netdev_priv(dev); | |
2080 | void __iomem * ioaddr = ns_ioaddr(dev); | |
2081 | unsigned entry; | |
6006f7f5 | 2082 | unsigned long flags; |
1da177e4 LT |
2083 | |
2084 | /* Note: Ordering is important here, set the field with the | |
2085 | "ownership" bit last, and only then increment cur_tx. */ | |
2086 | ||
2087 | /* Calculate the next Tx descriptor entry. */ | |
2088 | entry = np->cur_tx % TX_RING_SIZE; | |
2089 | ||
2090 | np->tx_skbuff[entry] = skb; | |
2091 | np->tx_dma[entry] = pci_map_single(np->pci_dev, | |
2092 | skb->data,skb->len, PCI_DMA_TODEVICE); | |
2093 | ||
2094 | np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]); | |
2095 | ||
6006f7f5 | 2096 | spin_lock_irqsave(&np->lock, flags); |
1da177e4 LT |
2097 | |
2098 | if (!np->hands_off) { | |
2099 | np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len); | |
2100 | /* StrongARM: Explicitly cache flush np->tx_ring and | |
2101 | * skb->data,skb->len. */ | |
2102 | wmb(); | |
2103 | np->cur_tx++; | |
2104 | if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) { | |
2105 | netdev_tx_done(dev); | |
2106 | if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) | |
2107 | netif_stop_queue(dev); | |
2108 | } | |
2109 | /* Wake the potentially-idle transmit channel. */ | |
2110 | writel(TxOn, ioaddr + ChipCmd); | |
2111 | } else { | |
2112 | dev_kfree_skb_irq(skb); | |
2113 | np->stats.tx_dropped++; | |
2114 | } | |
6006f7f5 | 2115 | spin_unlock_irqrestore(&np->lock, flags); |
1da177e4 LT |
2116 | |
2117 | dev->trans_start = jiffies; | |
2118 | ||
2119 | if (netif_msg_tx_queued(np)) { | |
2120 | printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n", | |
2121 | dev->name, np->cur_tx, entry); | |
2122 | } | |
2123 | return 0; | |
2124 | } | |
2125 | ||
2126 | static void netdev_tx_done(struct net_device *dev) | |
2127 | { | |
2128 | struct netdev_private *np = netdev_priv(dev); | |
2129 | ||
2130 | for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) { | |
2131 | int entry = np->dirty_tx % TX_RING_SIZE; | |
2132 | if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn)) | |
2133 | break; | |
2134 | if (netif_msg_tx_done(np)) | |
2135 | printk(KERN_DEBUG | |
2136 | "%s: tx frame #%d finished, status %#08x.\n", | |
2137 | dev->name, np->dirty_tx, | |
2138 | le32_to_cpu(np->tx_ring[entry].cmd_status)); | |
2139 | if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) { | |
2140 | np->stats.tx_packets++; | |
2141 | np->stats.tx_bytes += np->tx_skbuff[entry]->len; | |
2142 | } else { /* Various Tx errors */ | |
2143 | int tx_status = | |
2144 | le32_to_cpu(np->tx_ring[entry].cmd_status); | |
2145 | if (tx_status & (DescTxAbort|DescTxExcColl)) | |
2146 | np->stats.tx_aborted_errors++; | |
2147 | if (tx_status & DescTxFIFO) | |
2148 | np->stats.tx_fifo_errors++; | |
2149 | if (tx_status & DescTxCarrier) | |
2150 | np->stats.tx_carrier_errors++; | |
2151 | if (tx_status & DescTxOOWCol) | |
2152 | np->stats.tx_window_errors++; | |
2153 | np->stats.tx_errors++; | |
2154 | } | |
2155 | pci_unmap_single(np->pci_dev,np->tx_dma[entry], | |
2156 | np->tx_skbuff[entry]->len, | |
2157 | PCI_DMA_TODEVICE); | |
2158 | /* Free the original skb. */ | |
2159 | dev_kfree_skb_irq(np->tx_skbuff[entry]); | |
2160 | np->tx_skbuff[entry] = NULL; | |
2161 | } | |
2162 | if (netif_queue_stopped(dev) | |
2163 | && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) { | |
2164 | /* The ring is no longer full, wake queue. */ | |
2165 | netif_wake_queue(dev); | |
2166 | } | |
2167 | } | |
2168 | ||
b27a16b7 MB |
2169 | /* The interrupt handler doesn't actually handle interrupts itself, it |
2170 | * schedules a NAPI poll if there is anything to do. */ | |
7d12e780 | 2171 | static irqreturn_t intr_handler(int irq, void *dev_instance) |
1da177e4 LT |
2172 | { |
2173 | struct net_device *dev = dev_instance; | |
2174 | struct netdev_private *np = netdev_priv(dev); | |
2175 | void __iomem * ioaddr = ns_ioaddr(dev); | |
1da177e4 | 2176 | |
069f8256 | 2177 | /* Reading IntrStatus automatically acknowledges so don't do |
2178 | * that while interrupts are disabled, (for example, while a | |
2179 | * poll is scheduled). */ | |
2180 | if (np->hands_off || !readl(ioaddr + IntrEnable)) | |
1da177e4 | 2181 | return IRQ_NONE; |
6aa20a22 | 2182 | |
b27a16b7 | 2183 | np->intr_status = readl(ioaddr + IntrStatus); |
1da177e4 | 2184 | |
069f8256 | 2185 | if (!np->intr_status) |
2186 | return IRQ_NONE; | |
2187 | ||
b27a16b7 MB |
2188 | if (netif_msg_intr(np)) |
2189 | printk(KERN_DEBUG | |
2190 | "%s: Interrupt, status %#08x, mask %#08x.\n", | |
2191 | dev->name, np->intr_status, | |
2192 | readl(ioaddr + IntrMask)); | |
1da177e4 | 2193 | |
b27a16b7 MB |
2194 | prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]); |
2195 | ||
bea3348e | 2196 | if (netif_rx_schedule_prep(dev, &np->napi)) { |
b27a16b7 MB |
2197 | /* Disable interrupts and register for poll */ |
2198 | natsemi_irq_disable(dev); | |
bea3348e | 2199 | __netif_rx_schedule(dev, &np->napi); |
069f8256 | 2200 | } else |
2201 | printk(KERN_WARNING | |
2202 | "%s: Ignoring interrupt, status %#08x, mask %#08x.\n", | |
2203 | dev->name, np->intr_status, | |
2204 | readl(ioaddr + IntrMask)); | |
2205 | ||
b27a16b7 MB |
2206 | return IRQ_HANDLED; |
2207 | } | |
2208 | ||
2209 | /* This is the NAPI poll routine. As well as the standard RX handling | |
2210 | * it also handles all other interrupts that the chip might raise. | |
2211 | */ | |
bea3348e | 2212 | static int natsemi_poll(struct napi_struct *napi, int budget) |
b27a16b7 | 2213 | { |
bea3348e SH |
2214 | struct netdev_private *np = container_of(napi, struct netdev_private, napi); |
2215 | struct net_device *dev = np->dev; | |
b27a16b7 | 2216 | void __iomem * ioaddr = ns_ioaddr(dev); |
b27a16b7 MB |
2217 | int work_done = 0; |
2218 | ||
2219 | do { | |
069f8256 | 2220 | if (netif_msg_intr(np)) |
2221 | printk(KERN_DEBUG | |
2222 | "%s: Poll, status %#08x, mask %#08x.\n", | |
2223 | dev->name, np->intr_status, | |
2224 | readl(ioaddr + IntrMask)); | |
2225 | ||
d2a90036 | 2226 | /* netdev_rx() may read IntrStatus again if the RX state |
2227 | * machine falls over so do it first. */ | |
2228 | if (np->intr_status & | |
2229 | (IntrRxDone | IntrRxIntr | RxStatusFIFOOver | | |
2230 | IntrRxErr | IntrRxOverrun)) { | |
bea3348e | 2231 | netdev_rx(dev, &work_done, budget); |
d2a90036 | 2232 | } |
2233 | ||
b27a16b7 MB |
2234 | if (np->intr_status & |
2235 | (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) { | |
1da177e4 LT |
2236 | spin_lock(&np->lock); |
2237 | netdev_tx_done(dev); | |
2238 | spin_unlock(&np->lock); | |
2239 | } | |
2240 | ||
2241 | /* Abnormal error summary/uncommon events handlers. */ | |
b27a16b7 MB |
2242 | if (np->intr_status & IntrAbnormalSummary) |
2243 | netdev_error(dev, np->intr_status); | |
6aa20a22 | 2244 | |
bea3348e SH |
2245 | if (work_done >= budget) |
2246 | return work_done; | |
b27a16b7 MB |
2247 | |
2248 | np->intr_status = readl(ioaddr + IntrStatus); | |
2249 | } while (np->intr_status); | |
1da177e4 | 2250 | |
bea3348e | 2251 | netif_rx_complete(dev, napi); |
b27a16b7 MB |
2252 | |
2253 | /* Reenable interrupts providing nothing is trying to shut | |
2254 | * the chip down. */ | |
2255 | spin_lock(&np->lock); | |
4ec24119 | 2256 | if (!np->hands_off) |
b27a16b7 MB |
2257 | natsemi_irq_enable(dev); |
2258 | spin_unlock(&np->lock); | |
2259 | ||
bea3348e | 2260 | return work_done; |
1da177e4 LT |
2261 | } |
2262 | ||
2263 | /* This routine is logically part of the interrupt handler, but separated | |
2264 | for clarity and better register allocation. */ | |
b27a16b7 | 2265 | static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do) |
1da177e4 LT |
2266 | { |
2267 | struct netdev_private *np = netdev_priv(dev); | |
2268 | int entry = np->cur_rx % RX_RING_SIZE; | |
2269 | int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx; | |
2270 | s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status); | |
2271 | unsigned int buflen = np->rx_buf_sz; | |
2272 | void __iomem * ioaddr = ns_ioaddr(dev); | |
2273 | ||
2274 | /* If the driver owns the next entry it's a new packet. Send it up. */ | |
2275 | while (desc_status < 0) { /* e.g. & DescOwn */ | |
2276 | int pkt_len; | |
2277 | if (netif_msg_rx_status(np)) | |
2278 | printk(KERN_DEBUG | |
2279 | " netdev_rx() entry %d status was %#08x.\n", | |
2280 | entry, desc_status); | |
2281 | if (--boguscnt < 0) | |
2282 | break; | |
b27a16b7 MB |
2283 | |
2284 | if (*work_done >= work_to_do) | |
2285 | break; | |
2286 | ||
2287 | (*work_done)++; | |
2288 | ||
1da177e4 LT |
2289 | pkt_len = (desc_status & DescSizeMask) - 4; |
2290 | if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){ | |
2291 | if (desc_status & DescMore) { | |
6006f7f5 SS |
2292 | unsigned long flags; |
2293 | ||
1da177e4 LT |
2294 | if (netif_msg_rx_err(np)) |
2295 | printk(KERN_WARNING | |
2296 | "%s: Oversized(?) Ethernet " | |
2297 | "frame spanned multiple " | |
2298 | "buffers, entry %#08x " | |
2299 | "status %#08x.\n", dev->name, | |
2300 | np->cur_rx, desc_status); | |
2301 | np->stats.rx_length_errors++; | |
e72fd96e MB |
2302 | |
2303 | /* The RX state machine has probably | |
2304 | * locked up beneath us. Follow the | |
2305 | * reset procedure documented in | |
2306 | * AN-1287. */ | |
2307 | ||
6006f7f5 | 2308 | spin_lock_irqsave(&np->lock, flags); |
e72fd96e MB |
2309 | reset_rx(dev); |
2310 | reinit_rx(dev); | |
2311 | writel(np->ring_dma, ioaddr + RxRingPtr); | |
2312 | check_link(dev); | |
6006f7f5 | 2313 | spin_unlock_irqrestore(&np->lock, flags); |
e72fd96e MB |
2314 | |
2315 | /* We'll enable RX on exit from this | |
2316 | * function. */ | |
2317 | break; | |
2318 | ||
1da177e4 LT |
2319 | } else { |
2320 | /* There was an error. */ | |
2321 | np->stats.rx_errors++; | |
2322 | if (desc_status & (DescRxAbort|DescRxOver)) | |
2323 | np->stats.rx_over_errors++; | |
2324 | if (desc_status & (DescRxLong|DescRxRunt)) | |
2325 | np->stats.rx_length_errors++; | |
2326 | if (desc_status & (DescRxInvalid|DescRxAlign)) | |
2327 | np->stats.rx_frame_errors++; | |
2328 | if (desc_status & DescRxCRC) | |
2329 | np->stats.rx_crc_errors++; | |
2330 | } | |
2331 | } else if (pkt_len > np->rx_buf_sz) { | |
2332 | /* if this is the tail of a double buffer | |
2333 | * packet, we've already counted the error | |
2334 | * on the first part. Ignore the second half. | |
2335 | */ | |
2336 | } else { | |
2337 | struct sk_buff *skb; | |
2338 | /* Omit CRC size. */ | |
2339 | /* Check if the packet is long enough to accept | |
2340 | * without copying to a minimally-sized skbuff. */ | |
2341 | if (pkt_len < rx_copybreak | |
2342 | && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) { | |
1da177e4 LT |
2343 | /* 16 byte align the IP header */ |
2344 | skb_reserve(skb, RX_OFFSET); | |
2345 | pci_dma_sync_single_for_cpu(np->pci_dev, | |
2346 | np->rx_dma[entry], | |
2347 | buflen, | |
2348 | PCI_DMA_FROMDEVICE); | |
8c7b7faa DM |
2349 | skb_copy_to_linear_data(skb, |
2350 | np->rx_skbuff[entry]->data, pkt_len); | |
1da177e4 LT |
2351 | skb_put(skb, pkt_len); |
2352 | pci_dma_sync_single_for_device(np->pci_dev, | |
2353 | np->rx_dma[entry], | |
2354 | buflen, | |
2355 | PCI_DMA_FROMDEVICE); | |
2356 | } else { | |
2357 | pci_unmap_single(np->pci_dev, np->rx_dma[entry], | |
2358 | buflen, PCI_DMA_FROMDEVICE); | |
2359 | skb_put(skb = np->rx_skbuff[entry], pkt_len); | |
2360 | np->rx_skbuff[entry] = NULL; | |
2361 | } | |
2362 | skb->protocol = eth_type_trans(skb, dev); | |
b27a16b7 | 2363 | netif_receive_skb(skb); |
1da177e4 LT |
2364 | np->stats.rx_packets++; |
2365 | np->stats.rx_bytes += pkt_len; | |
2366 | } | |
2367 | entry = (++np->cur_rx) % RX_RING_SIZE; | |
2368 | np->rx_head_desc = &np->rx_ring[entry]; | |
2369 | desc_status = le32_to_cpu(np->rx_head_desc->cmd_status); | |
2370 | } | |
2371 | refill_rx(dev); | |
2372 | ||
2373 | /* Restart Rx engine if stopped. */ | |
2374 | if (np->oom) | |
2375 | mod_timer(&np->timer, jiffies + 1); | |
2376 | else | |
2377 | writel(RxOn, ioaddr + ChipCmd); | |
2378 | } | |
2379 | ||
2380 | static void netdev_error(struct net_device *dev, int intr_status) | |
2381 | { | |
2382 | struct netdev_private *np = netdev_priv(dev); | |
2383 | void __iomem * ioaddr = ns_ioaddr(dev); | |
2384 | ||
2385 | spin_lock(&np->lock); | |
2386 | if (intr_status & LinkChange) { | |
2387 | u16 lpa = mdio_read(dev, MII_LPA); | |
2388 | if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE | |
2389 | && netif_msg_link(np)) { | |
2390 | printk(KERN_INFO | |
2391 | "%s: Autonegotiation advertising" | |
2392 | " %#04x partner %#04x.\n", dev->name, | |
2393 | np->advertising, lpa); | |
2394 | } | |
2395 | ||
2396 | /* read MII int status to clear the flag */ | |
2397 | readw(ioaddr + MIntrStatus); | |
2398 | check_link(dev); | |
2399 | } | |
2400 | if (intr_status & StatsMax) { | |
2401 | __get_stats(dev); | |
2402 | } | |
2403 | if (intr_status & IntrTxUnderrun) { | |
2404 | if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) { | |
2405 | np->tx_config += TX_DRTH_VAL_INC; | |
2406 | if (netif_msg_tx_err(np)) | |
2407 | printk(KERN_NOTICE | |
2408 | "%s: increased tx threshold, txcfg %#08x.\n", | |
2409 | dev->name, np->tx_config); | |
2410 | } else { | |
2411 | if (netif_msg_tx_err(np)) | |
2412 | printk(KERN_NOTICE | |
2413 | "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n", | |
2414 | dev->name, np->tx_config); | |
2415 | } | |
2416 | writel(np->tx_config, ioaddr + TxConfig); | |
2417 | } | |
2418 | if (intr_status & WOLPkt && netif_msg_wol(np)) { | |
2419 | int wol_status = readl(ioaddr + WOLCmd); | |
2420 | printk(KERN_NOTICE "%s: Link wake-up event %#08x\n", | |
2421 | dev->name, wol_status); | |
2422 | } | |
2423 | if (intr_status & RxStatusFIFOOver) { | |
2424 | if (netif_msg_rx_err(np) && netif_msg_intr(np)) { | |
2425 | printk(KERN_NOTICE "%s: Rx status FIFO overrun\n", | |
2426 | dev->name); | |
2427 | } | |
2428 | np->stats.rx_fifo_errors++; | |
c76720cf | 2429 | np->stats.rx_errors++; |
1da177e4 LT |
2430 | } |
2431 | /* Hmmmmm, it's not clear how to recover from PCI faults. */ | |
2432 | if (intr_status & IntrPCIErr) { | |
2433 | printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name, | |
2434 | intr_status & IntrPCIErr); | |
2435 | np->stats.tx_fifo_errors++; | |
c76720cf | 2436 | np->stats.tx_errors++; |
1da177e4 | 2437 | np->stats.rx_fifo_errors++; |
c76720cf | 2438 | np->stats.rx_errors++; |
1da177e4 LT |
2439 | } |
2440 | spin_unlock(&np->lock); | |
2441 | } | |
2442 | ||
2443 | static void __get_stats(struct net_device *dev) | |
2444 | { | |
2445 | void __iomem * ioaddr = ns_ioaddr(dev); | |
2446 | struct netdev_private *np = netdev_priv(dev); | |
2447 | ||
2448 | /* The chip only need report frame silently dropped. */ | |
2449 | np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs); | |
2450 | np->stats.rx_missed_errors += readl(ioaddr + RxMissed); | |
2451 | } | |
2452 | ||
2453 | static struct net_device_stats *get_stats(struct net_device *dev) | |
2454 | { | |
2455 | struct netdev_private *np = netdev_priv(dev); | |
2456 | ||
2457 | /* The chip only need report frame silently dropped. */ | |
2458 | spin_lock_irq(&np->lock); | |
2459 | if (netif_running(dev) && !np->hands_off) | |
2460 | __get_stats(dev); | |
2461 | spin_unlock_irq(&np->lock); | |
2462 | ||
2463 | return &np->stats; | |
2464 | } | |
2465 | ||
2466 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2467 | static void natsemi_poll_controller(struct net_device *dev) | |
2468 | { | |
2469 | disable_irq(dev->irq); | |
069f8256 | 2470 | intr_handler(dev->irq, dev); |
1da177e4 LT |
2471 | enable_irq(dev->irq); |
2472 | } | |
2473 | #endif | |
2474 | ||
2475 | #define HASH_TABLE 0x200 | |
2476 | static void __set_rx_mode(struct net_device *dev) | |
2477 | { | |
2478 | void __iomem * ioaddr = ns_ioaddr(dev); | |
2479 | struct netdev_private *np = netdev_priv(dev); | |
2480 | u8 mc_filter[64]; /* Multicast hash filter */ | |
2481 | u32 rx_mode; | |
2482 | ||
2483 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1da177e4 LT |
2484 | rx_mode = RxFilterEnable | AcceptBroadcast |
2485 | | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys; | |
2486 | } else if ((dev->mc_count > multicast_filter_limit) | |
2487 | || (dev->flags & IFF_ALLMULTI)) { | |
2488 | rx_mode = RxFilterEnable | AcceptBroadcast | |
2489 | | AcceptAllMulticast | AcceptMyPhys; | |
2490 | } else { | |
2491 | struct dev_mc_list *mclist; | |
2492 | int i; | |
2493 | memset(mc_filter, 0, sizeof(mc_filter)); | |
2494 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
2495 | i++, mclist = mclist->next) { | |
ddfce6bb SH |
2496 | int b = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff; |
2497 | mc_filter[b/8] |= (1 << (b & 0x07)); | |
1da177e4 LT |
2498 | } |
2499 | rx_mode = RxFilterEnable | AcceptBroadcast | |
2500 | | AcceptMulticast | AcceptMyPhys; | |
2501 | for (i = 0; i < 64; i += 2) { | |
760f86d7 HX |
2502 | writel(HASH_TABLE + i, ioaddr + RxFilterAddr); |
2503 | writel((mc_filter[i + 1] << 8) + mc_filter[i], | |
2504 | ioaddr + RxFilterData); | |
1da177e4 LT |
2505 | } |
2506 | } | |
2507 | writel(rx_mode, ioaddr + RxFilterAddr); | |
2508 | np->cur_rx_mode = rx_mode; | |
2509 | } | |
2510 | ||
2511 | static int natsemi_change_mtu(struct net_device *dev, int new_mtu) | |
2512 | { | |
2513 | if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS) | |
2514 | return -EINVAL; | |
2515 | ||
2516 | dev->mtu = new_mtu; | |
2517 | ||
2518 | /* synchronized against open : rtnl_lock() held by caller */ | |
2519 | if (netif_running(dev)) { | |
2520 | struct netdev_private *np = netdev_priv(dev); | |
2521 | void __iomem * ioaddr = ns_ioaddr(dev); | |
2522 | ||
2523 | disable_irq(dev->irq); | |
2524 | spin_lock(&np->lock); | |
2525 | /* stop engines */ | |
2526 | natsemi_stop_rxtx(dev); | |
2527 | /* drain rx queue */ | |
2528 | drain_rx(dev); | |
2529 | /* change buffers */ | |
2530 | set_bufsize(dev); | |
2531 | reinit_rx(dev); | |
2532 | writel(np->ring_dma, ioaddr + RxRingPtr); | |
2533 | /* restart engines */ | |
2534 | writel(RxOn | TxOn, ioaddr + ChipCmd); | |
2535 | spin_unlock(&np->lock); | |
2536 | enable_irq(dev->irq); | |
2537 | } | |
2538 | return 0; | |
2539 | } | |
2540 | ||
2541 | static void set_rx_mode(struct net_device *dev) | |
2542 | { | |
2543 | struct netdev_private *np = netdev_priv(dev); | |
2544 | spin_lock_irq(&np->lock); | |
2545 | if (!np->hands_off) | |
2546 | __set_rx_mode(dev); | |
2547 | spin_unlock_irq(&np->lock); | |
2548 | } | |
2549 | ||
2550 | static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
2551 | { | |
2552 | struct netdev_private *np = netdev_priv(dev); | |
2553 | strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN); | |
2554 | strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN); | |
2555 | strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN); | |
2556 | } | |
2557 | ||
2558 | static int get_regs_len(struct net_device *dev) | |
2559 | { | |
2560 | return NATSEMI_REGS_SIZE; | |
2561 | } | |
2562 | ||
2563 | static int get_eeprom_len(struct net_device *dev) | |
2564 | { | |
a8b4cf42 MB |
2565 | struct netdev_private *np = netdev_priv(dev); |
2566 | return np->eeprom_size; | |
1da177e4 LT |
2567 | } |
2568 | ||
2569 | static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2570 | { | |
2571 | struct netdev_private *np = netdev_priv(dev); | |
2572 | spin_lock_irq(&np->lock); | |
2573 | netdev_get_ecmd(dev, ecmd); | |
2574 | spin_unlock_irq(&np->lock); | |
2575 | return 0; | |
2576 | } | |
2577 | ||
2578 | static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2579 | { | |
2580 | struct netdev_private *np = netdev_priv(dev); | |
2581 | int res; | |
2582 | spin_lock_irq(&np->lock); | |
2583 | res = netdev_set_ecmd(dev, ecmd); | |
2584 | spin_unlock_irq(&np->lock); | |
2585 | return res; | |
2586 | } | |
2587 | ||
2588 | static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2589 | { | |
2590 | struct netdev_private *np = netdev_priv(dev); | |
2591 | spin_lock_irq(&np->lock); | |
2592 | netdev_get_wol(dev, &wol->supported, &wol->wolopts); | |
2593 | netdev_get_sopass(dev, wol->sopass); | |
2594 | spin_unlock_irq(&np->lock); | |
2595 | } | |
2596 | ||
2597 | static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2598 | { | |
2599 | struct netdev_private *np = netdev_priv(dev); | |
2600 | int res; | |
2601 | spin_lock_irq(&np->lock); | |
2602 | netdev_set_wol(dev, wol->wolopts); | |
2603 | res = netdev_set_sopass(dev, wol->sopass); | |
2604 | spin_unlock_irq(&np->lock); | |
2605 | return res; | |
2606 | } | |
2607 | ||
2608 | static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | |
2609 | { | |
2610 | struct netdev_private *np = netdev_priv(dev); | |
2611 | regs->version = NATSEMI_REGS_VER; | |
2612 | spin_lock_irq(&np->lock); | |
2613 | netdev_get_regs(dev, buf); | |
2614 | spin_unlock_irq(&np->lock); | |
2615 | } | |
2616 | ||
2617 | static u32 get_msglevel(struct net_device *dev) | |
2618 | { | |
2619 | struct netdev_private *np = netdev_priv(dev); | |
2620 | return np->msg_enable; | |
2621 | } | |
2622 | ||
2623 | static void set_msglevel(struct net_device *dev, u32 val) | |
2624 | { | |
2625 | struct netdev_private *np = netdev_priv(dev); | |
2626 | np->msg_enable = val; | |
2627 | } | |
2628 | ||
2629 | static int nway_reset(struct net_device *dev) | |
2630 | { | |
2631 | int tmp; | |
2632 | int r = -EINVAL; | |
2633 | /* if autoneg is off, it's an error */ | |
2634 | tmp = mdio_read(dev, MII_BMCR); | |
2635 | if (tmp & BMCR_ANENABLE) { | |
2636 | tmp |= (BMCR_ANRESTART); | |
2637 | mdio_write(dev, MII_BMCR, tmp); | |
2638 | r = 0; | |
2639 | } | |
2640 | return r; | |
2641 | } | |
2642 | ||
2643 | static u32 get_link(struct net_device *dev) | |
2644 | { | |
2645 | /* LSTATUS is latched low until a read - so read twice */ | |
2646 | mdio_read(dev, MII_BMSR); | |
2647 | return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0; | |
2648 | } | |
2649 | ||
2650 | static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
2651 | { | |
2652 | struct netdev_private *np = netdev_priv(dev); | |
a8b4cf42 | 2653 | u8 *eebuf; |
1da177e4 LT |
2654 | int res; |
2655 | ||
a8b4cf42 MB |
2656 | eebuf = kmalloc(np->eeprom_size, GFP_KERNEL); |
2657 | if (!eebuf) | |
2658 | return -ENOMEM; | |
2659 | ||
1da177e4 LT |
2660 | eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16); |
2661 | spin_lock_irq(&np->lock); | |
2662 | res = netdev_get_eeprom(dev, eebuf); | |
2663 | spin_unlock_irq(&np->lock); | |
2664 | if (!res) | |
2665 | memcpy(data, eebuf+eeprom->offset, eeprom->len); | |
a8b4cf42 | 2666 | kfree(eebuf); |
1da177e4 LT |
2667 | return res; |
2668 | } | |
2669 | ||
7282d491 | 2670 | static const struct ethtool_ops ethtool_ops = { |
1da177e4 LT |
2671 | .get_drvinfo = get_drvinfo, |
2672 | .get_regs_len = get_regs_len, | |
2673 | .get_eeprom_len = get_eeprom_len, | |
2674 | .get_settings = get_settings, | |
2675 | .set_settings = set_settings, | |
2676 | .get_wol = get_wol, | |
2677 | .set_wol = set_wol, | |
2678 | .get_regs = get_regs, | |
2679 | .get_msglevel = get_msglevel, | |
2680 | .set_msglevel = set_msglevel, | |
2681 | .nway_reset = nway_reset, | |
2682 | .get_link = get_link, | |
2683 | .get_eeprom = get_eeprom, | |
2684 | }; | |
2685 | ||
2686 | static int netdev_set_wol(struct net_device *dev, u32 newval) | |
2687 | { | |
2688 | struct netdev_private *np = netdev_priv(dev); | |
2689 | void __iomem * ioaddr = ns_ioaddr(dev); | |
2690 | u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary; | |
2691 | ||
2692 | /* translate to bitmasks this chip understands */ | |
2693 | if (newval & WAKE_PHY) | |
2694 | data |= WakePhy; | |
2695 | if (newval & WAKE_UCAST) | |
2696 | data |= WakeUnicast; | |
2697 | if (newval & WAKE_MCAST) | |
2698 | data |= WakeMulticast; | |
2699 | if (newval & WAKE_BCAST) | |
2700 | data |= WakeBroadcast; | |
2701 | if (newval & WAKE_ARP) | |
2702 | data |= WakeArp; | |
2703 | if (newval & WAKE_MAGIC) | |
2704 | data |= WakeMagic; | |
2705 | if (np->srr >= SRR_DP83815_D) { | |
2706 | if (newval & WAKE_MAGICSECURE) { | |
2707 | data |= WakeMagicSecure; | |
2708 | } | |
2709 | } | |
2710 | ||
2711 | writel(data, ioaddr + WOLCmd); | |
2712 | ||
2713 | return 0; | |
2714 | } | |
2715 | ||
2716 | static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur) | |
2717 | { | |
2718 | struct netdev_private *np = netdev_priv(dev); | |
2719 | void __iomem * ioaddr = ns_ioaddr(dev); | |
2720 | u32 regval = readl(ioaddr + WOLCmd); | |
2721 | ||
2722 | *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | |
2723 | | WAKE_ARP | WAKE_MAGIC); | |
2724 | ||
2725 | if (np->srr >= SRR_DP83815_D) { | |
2726 | /* SOPASS works on revD and higher */ | |
2727 | *supported |= WAKE_MAGICSECURE; | |
2728 | } | |
2729 | *cur = 0; | |
2730 | ||
2731 | /* translate from chip bitmasks */ | |
2732 | if (regval & WakePhy) | |
2733 | *cur |= WAKE_PHY; | |
2734 | if (regval & WakeUnicast) | |
2735 | *cur |= WAKE_UCAST; | |
2736 | if (regval & WakeMulticast) | |
2737 | *cur |= WAKE_MCAST; | |
2738 | if (regval & WakeBroadcast) | |
2739 | *cur |= WAKE_BCAST; | |
2740 | if (regval & WakeArp) | |
2741 | *cur |= WAKE_ARP; | |
2742 | if (regval & WakeMagic) | |
2743 | *cur |= WAKE_MAGIC; | |
2744 | if (regval & WakeMagicSecure) { | |
2745 | /* this can be on in revC, but it's broken */ | |
2746 | *cur |= WAKE_MAGICSECURE; | |
2747 | } | |
2748 | ||
2749 | return 0; | |
2750 | } | |
2751 | ||
2752 | static int netdev_set_sopass(struct net_device *dev, u8 *newval) | |
2753 | { | |
2754 | struct netdev_private *np = netdev_priv(dev); | |
2755 | void __iomem * ioaddr = ns_ioaddr(dev); | |
2756 | u16 *sval = (u16 *)newval; | |
2757 | u32 addr; | |
2758 | ||
2759 | if (np->srr < SRR_DP83815_D) { | |
2760 | return 0; | |
2761 | } | |
2762 | ||
2763 | /* enable writing to these registers by disabling the RX filter */ | |
2764 | addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask; | |
2765 | addr &= ~RxFilterEnable; | |
2766 | writel(addr, ioaddr + RxFilterAddr); | |
2767 | ||
2768 | /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */ | |
2769 | writel(addr | 0xa, ioaddr + RxFilterAddr); | |
2770 | writew(sval[0], ioaddr + RxFilterData); | |
2771 | ||
2772 | writel(addr | 0xc, ioaddr + RxFilterAddr); | |
2773 | writew(sval[1], ioaddr + RxFilterData); | |
2774 | ||
2775 | writel(addr | 0xe, ioaddr + RxFilterAddr); | |
2776 | writew(sval[2], ioaddr + RxFilterData); | |
2777 | ||
2778 | /* re-enable the RX filter */ | |
2779 | writel(addr | RxFilterEnable, ioaddr + RxFilterAddr); | |
2780 | ||
2781 | return 0; | |
2782 | } | |
2783 | ||
2784 | static int netdev_get_sopass(struct net_device *dev, u8 *data) | |
2785 | { | |
2786 | struct netdev_private *np = netdev_priv(dev); | |
2787 | void __iomem * ioaddr = ns_ioaddr(dev); | |
2788 | u16 *sval = (u16 *)data; | |
2789 | u32 addr; | |
2790 | ||
2791 | if (np->srr < SRR_DP83815_D) { | |
2792 | sval[0] = sval[1] = sval[2] = 0; | |
2793 | return 0; | |
2794 | } | |
2795 | ||
2796 | /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */ | |
2797 | addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask; | |
2798 | ||
2799 | writel(addr | 0xa, ioaddr + RxFilterAddr); | |
2800 | sval[0] = readw(ioaddr + RxFilterData); | |
2801 | ||
2802 | writel(addr | 0xc, ioaddr + RxFilterAddr); | |
2803 | sval[1] = readw(ioaddr + RxFilterData); | |
2804 | ||
2805 | writel(addr | 0xe, ioaddr + RxFilterAddr); | |
2806 | sval[2] = readw(ioaddr + RxFilterData); | |
2807 | ||
2808 | writel(addr, ioaddr + RxFilterAddr); | |
2809 | ||
2810 | return 0; | |
2811 | } | |
2812 | ||
2813 | static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2814 | { | |
2815 | struct netdev_private *np = netdev_priv(dev); | |
2816 | u32 tmp; | |
2817 | ||
2818 | ecmd->port = dev->if_port; | |
2819 | ecmd->speed = np->speed; | |
2820 | ecmd->duplex = np->duplex; | |
2821 | ecmd->autoneg = np->autoneg; | |
2822 | ecmd->advertising = 0; | |
2823 | if (np->advertising & ADVERTISE_10HALF) | |
2824 | ecmd->advertising |= ADVERTISED_10baseT_Half; | |
2825 | if (np->advertising & ADVERTISE_10FULL) | |
2826 | ecmd->advertising |= ADVERTISED_10baseT_Full; | |
2827 | if (np->advertising & ADVERTISE_100HALF) | |
2828 | ecmd->advertising |= ADVERTISED_100baseT_Half; | |
2829 | if (np->advertising & ADVERTISE_100FULL) | |
2830 | ecmd->advertising |= ADVERTISED_100baseT_Full; | |
2831 | ecmd->supported = (SUPPORTED_Autoneg | | |
2832 | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | | |
2833 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
2834 | SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE); | |
2835 | ecmd->phy_address = np->phy_addr_external; | |
2836 | /* | |
2837 | * We intentionally report the phy address of the external | |
2838 | * phy, even if the internal phy is used. This is necessary | |
2839 | * to work around a deficiency of the ethtool interface: | |
2840 | * It's only possible to query the settings of the active | |
6aa20a22 | 2841 | * port. Therefore |
1da177e4 LT |
2842 | * # ethtool -s ethX port mii |
2843 | * actually sends an ioctl to switch to port mii with the | |
2844 | * settings that are used for the current active port. | |
2845 | * If we would report a different phy address in this | |
2846 | * command, then | |
2847 | * # ethtool -s ethX port tp;ethtool -s ethX port mii | |
2848 | * would unintentionally change the phy address. | |
2849 | * | |
2850 | * Fortunately the phy address doesn't matter with the | |
2851 | * internal phy... | |
2852 | */ | |
2853 | ||
2854 | /* set information based on active port type */ | |
2855 | switch (ecmd->port) { | |
2856 | default: | |
2857 | case PORT_TP: | |
2858 | ecmd->advertising |= ADVERTISED_TP; | |
2859 | ecmd->transceiver = XCVR_INTERNAL; | |
2860 | break; | |
2861 | case PORT_MII: | |
2862 | ecmd->advertising |= ADVERTISED_MII; | |
2863 | ecmd->transceiver = XCVR_EXTERNAL; | |
2864 | break; | |
2865 | case PORT_FIBRE: | |
2866 | ecmd->advertising |= ADVERTISED_FIBRE; | |
2867 | ecmd->transceiver = XCVR_EXTERNAL; | |
2868 | break; | |
2869 | } | |
2870 | ||
2871 | /* if autonegotiation is on, try to return the active speed/duplex */ | |
2872 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2873 | ecmd->advertising |= ADVERTISED_Autoneg; | |
2874 | tmp = mii_nway_result( | |
2875 | np->advertising & mdio_read(dev, MII_LPA)); | |
2876 | if (tmp == LPA_100FULL || tmp == LPA_100HALF) | |
2877 | ecmd->speed = SPEED_100; | |
2878 | else | |
2879 | ecmd->speed = SPEED_10; | |
2880 | if (tmp == LPA_100FULL || tmp == LPA_10FULL) | |
2881 | ecmd->duplex = DUPLEX_FULL; | |
2882 | else | |
2883 | ecmd->duplex = DUPLEX_HALF; | |
2884 | } | |
2885 | ||
2886 | /* ignore maxtxpkt, maxrxpkt for now */ | |
2887 | ||
2888 | return 0; | |
2889 | } | |
2890 | ||
2891 | static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2892 | { | |
2893 | struct netdev_private *np = netdev_priv(dev); | |
2894 | ||
2895 | if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE) | |
2896 | return -EINVAL; | |
2897 | if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL) | |
2898 | return -EINVAL; | |
2899 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2900 | if ((ecmd->advertising & (ADVERTISED_10baseT_Half | | |
2901 | ADVERTISED_10baseT_Full | | |
2902 | ADVERTISED_100baseT_Half | | |
2903 | ADVERTISED_100baseT_Full)) == 0) { | |
2904 | return -EINVAL; | |
2905 | } | |
2906 | } else if (ecmd->autoneg == AUTONEG_DISABLE) { | |
2907 | if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100) | |
2908 | return -EINVAL; | |
2909 | if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) | |
2910 | return -EINVAL; | |
2911 | } else { | |
2912 | return -EINVAL; | |
2913 | } | |
2914 | ||
68c90166 MB |
2915 | /* |
2916 | * If we're ignoring the PHY then autoneg and the internal | |
2917 | * transciever are really not going to work so don't let the | |
2918 | * user select them. | |
2919 | */ | |
2920 | if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE || | |
2921 | ecmd->port == PORT_TP)) | |
2922 | return -EINVAL; | |
2923 | ||
1da177e4 LT |
2924 | /* |
2925 | * maxtxpkt, maxrxpkt: ignored for now. | |
2926 | * | |
2927 | * transceiver: | |
2928 | * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always | |
2929 | * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and | |
2930 | * selects based on ecmd->port. | |
2931 | * | |
2932 | * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre | |
2933 | * phys that are connected to the mii bus. It's used to apply fibre | |
2934 | * specific updates. | |
2935 | */ | |
2936 | ||
2937 | /* WHEW! now lets bang some bits */ | |
2938 | ||
2939 | /* save the parms */ | |
2940 | dev->if_port = ecmd->port; | |
2941 | np->autoneg = ecmd->autoneg; | |
2942 | np->phy_addr_external = ecmd->phy_address & PhyAddrMask; | |
2943 | if (np->autoneg == AUTONEG_ENABLE) { | |
2944 | /* advertise only what has been requested */ | |
2945 | np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); | |
2946 | if (ecmd->advertising & ADVERTISED_10baseT_Half) | |
2947 | np->advertising |= ADVERTISE_10HALF; | |
2948 | if (ecmd->advertising & ADVERTISED_10baseT_Full) | |
2949 | np->advertising |= ADVERTISE_10FULL; | |
2950 | if (ecmd->advertising & ADVERTISED_100baseT_Half) | |
2951 | np->advertising |= ADVERTISE_100HALF; | |
2952 | if (ecmd->advertising & ADVERTISED_100baseT_Full) | |
2953 | np->advertising |= ADVERTISE_100FULL; | |
2954 | } else { | |
2955 | np->speed = ecmd->speed; | |
2956 | np->duplex = ecmd->duplex; | |
2957 | /* user overriding the initial full duplex parm? */ | |
2958 | if (np->duplex == DUPLEX_HALF) | |
2959 | np->full_duplex = 0; | |
2960 | } | |
2961 | ||
2962 | /* get the right phy enabled */ | |
2963 | if (ecmd->port == PORT_TP) | |
2964 | switch_port_internal(dev); | |
2965 | else | |
2966 | switch_port_external(dev); | |
2967 | ||
2968 | /* set parms and see how this affected our link status */ | |
2969 | init_phy_fixup(dev); | |
2970 | check_link(dev); | |
2971 | return 0; | |
2972 | } | |
2973 | ||
2974 | static int netdev_get_regs(struct net_device *dev, u8 *buf) | |
2975 | { | |
2976 | int i; | |
2977 | int j; | |
2978 | u32 rfcr; | |
2979 | u32 *rbuf = (u32 *)buf; | |
2980 | void __iomem * ioaddr = ns_ioaddr(dev); | |
2981 | ||
2982 | /* read non-mii page 0 of registers */ | |
2983 | for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) { | |
2984 | rbuf[i] = readl(ioaddr + i*4); | |
2985 | } | |
2986 | ||
2987 | /* read current mii registers */ | |
2988 | for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++) | |
2989 | rbuf[i] = mdio_read(dev, i & 0x1f); | |
2990 | ||
2991 | /* read only the 'magic' registers from page 1 */ | |
2992 | writew(1, ioaddr + PGSEL); | |
2993 | rbuf[i++] = readw(ioaddr + PMDCSR); | |
2994 | rbuf[i++] = readw(ioaddr + TSTDAT); | |
2995 | rbuf[i++] = readw(ioaddr + DSPCFG); | |
2996 | rbuf[i++] = readw(ioaddr + SDCFG); | |
2997 | writew(0, ioaddr + PGSEL); | |
2998 | ||
2999 | /* read RFCR indexed registers */ | |
3000 | rfcr = readl(ioaddr + RxFilterAddr); | |
3001 | for (j = 0; j < NATSEMI_RFDR_NREGS; j++) { | |
3002 | writel(j*2, ioaddr + RxFilterAddr); | |
3003 | rbuf[i++] = readw(ioaddr + RxFilterData); | |
3004 | } | |
3005 | writel(rfcr, ioaddr + RxFilterAddr); | |
3006 | ||
3007 | /* the interrupt status is clear-on-read - see if we missed any */ | |
3008 | if (rbuf[4] & rbuf[5]) { | |
3009 | printk(KERN_WARNING | |
3010 | "%s: shoot, we dropped an interrupt (%#08x)\n", | |
3011 | dev->name, rbuf[4] & rbuf[5]); | |
3012 | } | |
3013 | ||
3014 | return 0; | |
3015 | } | |
3016 | ||
3017 | #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \ | |
3018 | | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \ | |
3019 | | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \ | |
3020 | | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \ | |
3021 | | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \ | |
3022 | | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \ | |
3023 | | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \ | |
3024 | | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) ) | |
3025 | ||
3026 | static int netdev_get_eeprom(struct net_device *dev, u8 *buf) | |
3027 | { | |
3028 | int i; | |
3029 | u16 *ebuf = (u16 *)buf; | |
3030 | void __iomem * ioaddr = ns_ioaddr(dev); | |
a8b4cf42 | 3031 | struct netdev_private *np = netdev_priv(dev); |
1da177e4 LT |
3032 | |
3033 | /* eeprom_read reads 16 bits, and indexes by 16 bits */ | |
a8b4cf42 | 3034 | for (i = 0; i < np->eeprom_size/2; i++) { |
1da177e4 LT |
3035 | ebuf[i] = eeprom_read(ioaddr, i); |
3036 | /* The EEPROM itself stores data bit-swapped, but eeprom_read | |
3037 | * reads it back "sanely". So we swap it back here in order to | |
3038 | * present it to userland as it is stored. */ | |
3039 | ebuf[i] = SWAP_BITS(ebuf[i]); | |
3040 | } | |
3041 | return 0; | |
3042 | } | |
3043 | ||
3044 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
3045 | { | |
3046 | struct mii_ioctl_data *data = if_mii(rq); | |
3047 | struct netdev_private *np = netdev_priv(dev); | |
3048 | ||
3049 | switch(cmd) { | |
3050 | case SIOCGMIIPHY: /* Get address of MII PHY in use. */ | |
3051 | case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */ | |
3052 | data->phy_id = np->phy_addr_external; | |
3053 | /* Fall Through */ | |
3054 | ||
3055 | case SIOCGMIIREG: /* Read MII PHY register. */ | |
3056 | case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */ | |
3057 | /* The phy_id is not enough to uniquely identify | |
3058 | * the intended target. Therefore the command is sent to | |
3059 | * the given mii on the current port. | |
3060 | */ | |
3061 | if (dev->if_port == PORT_TP) { | |
3062 | if ((data->phy_id & 0x1f) == np->phy_addr_external) | |
3063 | data->val_out = mdio_read(dev, | |
3064 | data->reg_num & 0x1f); | |
3065 | else | |
3066 | data->val_out = 0; | |
3067 | } else { | |
3068 | move_int_phy(dev, data->phy_id & 0x1f); | |
3069 | data->val_out = miiport_read(dev, data->phy_id & 0x1f, | |
3070 | data->reg_num & 0x1f); | |
3071 | } | |
3072 | return 0; | |
3073 | ||
3074 | case SIOCSMIIREG: /* Write MII PHY register. */ | |
3075 | case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */ | |
3076 | if (!capable(CAP_NET_ADMIN)) | |
3077 | return -EPERM; | |
3078 | if (dev->if_port == PORT_TP) { | |
3079 | if ((data->phy_id & 0x1f) == np->phy_addr_external) { | |
3080 | if ((data->reg_num & 0x1f) == MII_ADVERTISE) | |
3081 | np->advertising = data->val_in; | |
3082 | mdio_write(dev, data->reg_num & 0x1f, | |
3083 | data->val_in); | |
3084 | } | |
3085 | } else { | |
3086 | if ((data->phy_id & 0x1f) == np->phy_addr_external) { | |
3087 | if ((data->reg_num & 0x1f) == MII_ADVERTISE) | |
3088 | np->advertising = data->val_in; | |
3089 | } | |
3090 | move_int_phy(dev, data->phy_id & 0x1f); | |
3091 | miiport_write(dev, data->phy_id & 0x1f, | |
3092 | data->reg_num & 0x1f, | |
3093 | data->val_in); | |
3094 | } | |
3095 | return 0; | |
3096 | default: | |
3097 | return -EOPNOTSUPP; | |
3098 | } | |
3099 | } | |
3100 | ||
3101 | static void enable_wol_mode(struct net_device *dev, int enable_intr) | |
3102 | { | |
3103 | void __iomem * ioaddr = ns_ioaddr(dev); | |
3104 | struct netdev_private *np = netdev_priv(dev); | |
3105 | ||
3106 | if (netif_msg_wol(np)) | |
3107 | printk(KERN_INFO "%s: remaining active for wake-on-lan\n", | |
3108 | dev->name); | |
3109 | ||
3110 | /* For WOL we must restart the rx process in silent mode. | |
3111 | * Write NULL to the RxRingPtr. Only possible if | |
3112 | * rx process is stopped | |
3113 | */ | |
3114 | writel(0, ioaddr + RxRingPtr); | |
3115 | ||
3116 | /* read WoL status to clear */ | |
3117 | readl(ioaddr + WOLCmd); | |
3118 | ||
3119 | /* PME on, clear status */ | |
3120 | writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun); | |
3121 | ||
3122 | /* and restart the rx process */ | |
3123 | writel(RxOn, ioaddr + ChipCmd); | |
3124 | ||
3125 | if (enable_intr) { | |
3126 | /* enable the WOL interrupt. | |
3127 | * Could be used to send a netlink message. | |
3128 | */ | |
3129 | writel(WOLPkt | LinkChange, ioaddr + IntrMask); | |
14fdd90e | 3130 | natsemi_irq_enable(dev); |
1da177e4 LT |
3131 | } |
3132 | } | |
3133 | ||
3134 | static int netdev_close(struct net_device *dev) | |
3135 | { | |
3136 | void __iomem * ioaddr = ns_ioaddr(dev); | |
3137 | struct netdev_private *np = netdev_priv(dev); | |
3138 | ||
3139 | if (netif_msg_ifdown(np)) | |
3140 | printk(KERN_DEBUG | |
3141 | "%s: Shutting down ethercard, status was %#04x.\n", | |
3142 | dev->name, (int)readl(ioaddr + ChipCmd)); | |
3143 | if (netif_msg_pktdata(np)) | |
3144 | printk(KERN_DEBUG | |
3145 | "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", | |
3146 | dev->name, np->cur_tx, np->dirty_tx, | |
3147 | np->cur_rx, np->dirty_rx); | |
3148 | ||
bea3348e SH |
3149 | napi_disable(&np->napi); |
3150 | ||
1da177e4 LT |
3151 | /* |
3152 | * FIXME: what if someone tries to close a device | |
3153 | * that is suspended? | |
3154 | * Should we reenable the nic to switch to | |
3155 | * the final WOL settings? | |
3156 | */ | |
3157 | ||
3158 | del_timer_sync(&np->timer); | |
3159 | disable_irq(dev->irq); | |
3160 | spin_lock_irq(&np->lock); | |
b27a16b7 | 3161 | natsemi_irq_disable(dev); |
1da177e4 LT |
3162 | np->hands_off = 1; |
3163 | spin_unlock_irq(&np->lock); | |
3164 | enable_irq(dev->irq); | |
3165 | ||
3166 | free_irq(dev->irq, dev); | |
3167 | ||
3168 | /* Interrupt disabled, interrupt handler released, | |
3169 | * queue stopped, timer deleted, rtnl_lock held | |
3170 | * All async codepaths that access the driver are disabled. | |
3171 | */ | |
3172 | spin_lock_irq(&np->lock); | |
3173 | np->hands_off = 0; | |
3174 | readl(ioaddr + IntrMask); | |
3175 | readw(ioaddr + MIntrStatus); | |
3176 | ||
3177 | /* Freeze Stats */ | |
3178 | writel(StatsFreeze, ioaddr + StatsCtrl); | |
3179 | ||
3180 | /* Stop the chip's Tx and Rx processes. */ | |
3181 | natsemi_stop_rxtx(dev); | |
3182 | ||
3183 | __get_stats(dev); | |
3184 | spin_unlock_irq(&np->lock); | |
3185 | ||
3186 | /* clear the carrier last - an interrupt could reenable it otherwise */ | |
3187 | netif_carrier_off(dev); | |
3188 | netif_stop_queue(dev); | |
3189 | ||
3190 | dump_ring(dev); | |
3191 | drain_ring(dev); | |
3192 | free_ring(dev); | |
3193 | ||
3194 | { | |
3195 | u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary; | |
3196 | if (wol) { | |
3197 | /* restart the NIC in WOL mode. | |
3198 | * The nic must be stopped for this. | |
3199 | */ | |
3200 | enable_wol_mode(dev, 0); | |
3201 | } else { | |
3202 | /* Restore PME enable bit unmolested */ | |
3203 | writel(np->SavedClkRun, ioaddr + ClkRun); | |
3204 | } | |
3205 | } | |
3206 | return 0; | |
3207 | } | |
3208 | ||
3209 | ||
3210 | static void __devexit natsemi_remove1 (struct pci_dev *pdev) | |
3211 | { | |
3212 | struct net_device *dev = pci_get_drvdata(pdev); | |
3213 | void __iomem * ioaddr = ns_ioaddr(dev); | |
3214 | ||
1a147809 | 3215 | NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround); |
1da177e4 LT |
3216 | unregister_netdev (dev); |
3217 | pci_release_regions (pdev); | |
3218 | iounmap(ioaddr); | |
3219 | free_netdev (dev); | |
3220 | pci_set_drvdata(pdev, NULL); | |
3221 | } | |
3222 | ||
3223 | #ifdef CONFIG_PM | |
3224 | ||
3225 | /* | |
3226 | * The ns83815 chip doesn't have explicit RxStop bits. | |
3227 | * Kicking the Rx or Tx process for a new packet reenables the Rx process | |
3228 | * of the nic, thus this function must be very careful: | |
3229 | * | |
3230 | * suspend/resume synchronization: | |
3231 | * entry points: | |
3232 | * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler, | |
ed4cb133 | 3233 | * start_tx, ns_tx_timeout |
1da177e4 LT |
3234 | * |
3235 | * No function accesses the hardware without checking np->hands_off. | |
3236 | * the check occurs under spin_lock_irq(&np->lock); | |
3237 | * exceptions: | |
3238 | * * netdev_ioctl: noncritical access. | |
3239 | * * netdev_open: cannot happen due to the device_detach | |
3240 | * * netdev_close: doesn't hurt. | |
3241 | * * netdev_timer: timer stopped by natsemi_suspend. | |
3242 | * * intr_handler: doesn't acquire the spinlock. suspend calls | |
3243 | * disable_irq() to enforce synchronization. | |
b27a16b7 MB |
3244 | * * natsemi_poll: checks before reenabling interrupts. suspend |
3245 | * sets hands_off, disables interrupts and then waits with | |
bea3348e | 3246 | * napi_disable(). |
1da177e4 LT |
3247 | * |
3248 | * Interrupts must be disabled, otherwise hands_off can cause irq storms. | |
3249 | */ | |
3250 | ||
3251 | static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state) | |
3252 | { | |
3253 | struct net_device *dev = pci_get_drvdata (pdev); | |
3254 | struct netdev_private *np = netdev_priv(dev); | |
3255 | void __iomem * ioaddr = ns_ioaddr(dev); | |
3256 | ||
3257 | rtnl_lock(); | |
3258 | if (netif_running (dev)) { | |
3259 | del_timer_sync(&np->timer); | |
3260 | ||
3261 | disable_irq(dev->irq); | |
3262 | spin_lock_irq(&np->lock); | |
3263 | ||
14fdd90e | 3264 | natsemi_irq_disable(dev); |
1da177e4 LT |
3265 | np->hands_off = 1; |
3266 | natsemi_stop_rxtx(dev); | |
3267 | netif_stop_queue(dev); | |
3268 | ||
3269 | spin_unlock_irq(&np->lock); | |
3270 | enable_irq(dev->irq); | |
3271 | ||
bea3348e | 3272 | napi_disable(&np->napi); |
b27a16b7 | 3273 | |
1da177e4 LT |
3274 | /* Update the error counts. */ |
3275 | __get_stats(dev); | |
3276 | ||
3277 | /* pci_power_off(pdev, -1); */ | |
3278 | drain_ring(dev); | |
3279 | { | |
3280 | u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary; | |
3281 | /* Restore PME enable bit */ | |
3282 | if (wol) { | |
3283 | /* restart the NIC in WOL mode. | |
3284 | * The nic must be stopped for this. | |
3285 | * FIXME: use the WOL interrupt | |
3286 | */ | |
3287 | enable_wol_mode(dev, 0); | |
3288 | } else { | |
3289 | /* Restore PME enable bit unmolested */ | |
3290 | writel(np->SavedClkRun, ioaddr + ClkRun); | |
3291 | } | |
3292 | } | |
3293 | } | |
3294 | netif_device_detach(dev); | |
3295 | rtnl_unlock(); | |
3296 | return 0; | |
3297 | } | |
3298 | ||
3299 | ||
3300 | static int natsemi_resume (struct pci_dev *pdev) | |
3301 | { | |
3302 | struct net_device *dev = pci_get_drvdata (pdev); | |
3303 | struct netdev_private *np = netdev_priv(dev); | |
a8a935da | 3304 | int ret = 0; |
1da177e4 LT |
3305 | |
3306 | rtnl_lock(); | |
3307 | if (netif_device_present(dev)) | |
3308 | goto out; | |
3309 | if (netif_running(dev)) { | |
3310 | BUG_ON(!np->hands_off); | |
a8a935da MB |
3311 | ret = pci_enable_device(pdev); |
3312 | if (ret < 0) { | |
3313 | dev_err(&pdev->dev, | |
3314 | "pci_enable_device() failed: %d\n", ret); | |
3315 | goto out; | |
3316 | } | |
1da177e4 LT |
3317 | /* pci_power_on(pdev); */ |
3318 | ||
bea3348e SH |
3319 | napi_enable(&np->napi); |
3320 | ||
1da177e4 LT |
3321 | natsemi_reset(dev); |
3322 | init_ring(dev); | |
3323 | disable_irq(dev->irq); | |
3324 | spin_lock_irq(&np->lock); | |
3325 | np->hands_off = 0; | |
3326 | init_registers(dev); | |
3327 | netif_device_attach(dev); | |
3328 | spin_unlock_irq(&np->lock); | |
3329 | enable_irq(dev->irq); | |
3330 | ||
0e5d5442 | 3331 | mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ)); |
1da177e4 LT |
3332 | } |
3333 | netif_device_attach(dev); | |
3334 | out: | |
3335 | rtnl_unlock(); | |
a8a935da | 3336 | return ret; |
1da177e4 LT |
3337 | } |
3338 | ||
3339 | #endif /* CONFIG_PM */ | |
3340 | ||
3341 | static struct pci_driver natsemi_driver = { | |
3342 | .name = DRV_NAME, | |
3343 | .id_table = natsemi_pci_tbl, | |
3344 | .probe = natsemi_probe1, | |
3345 | .remove = __devexit_p(natsemi_remove1), | |
3346 | #ifdef CONFIG_PM | |
3347 | .suspend = natsemi_suspend, | |
3348 | .resume = natsemi_resume, | |
3349 | #endif | |
3350 | }; | |
3351 | ||
3352 | static int __init natsemi_init_mod (void) | |
3353 | { | |
3354 | /* when a module, this is printed whether or not devices are found in probe */ | |
3355 | #ifdef MODULE | |
3356 | printk(version); | |
3357 | #endif | |
3358 | ||
29917620 | 3359 | return pci_register_driver(&natsemi_driver); |
1da177e4 LT |
3360 | } |
3361 | ||
3362 | static void __exit natsemi_exit_mod (void) | |
3363 | { | |
3364 | pci_unregister_driver (&natsemi_driver); | |
3365 | } | |
3366 | ||
3367 | module_init(natsemi_init_mod); | |
3368 | module_exit(natsemi_exit_mod); | |
3369 |