projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
netxen: cleanup unused variables/functions
[deliverable/linux.git] / drivers / net / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1
AK		 1/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
80922fbc 4 *
3d396eb1
AK		 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
cb8011ad 9 *
3d396eb1
AK		 10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
cb8011ad 14 *
3d396eb1
AK		 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
80922fbc 19 *
3d396eb1
AK		 20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
80922fbc 22 *
3d396eb1
AK		 23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34#include "netxen_nic.h"
35#include "netxen_nic_hw.h"
36#include "netxen_nic_phan_reg.h"
37
3176ff3e 38
c9bdd4b5
ACM		 39#include <net/ip.h>
40
3176ff3e
MT		 41struct netxen_recv_crb recv_crb_registers[] = {
42 /*
43 * Instance 0.
44 */
45 {
7830b22c
DP		 46 /* crb_rcv_producer: */
47 {
48 NETXEN_NIC_REG(0x100),
49 /* Jumbo frames */
50 NETXEN_NIC_REG(0x110),
51 /* LRO */
52 NETXEN_NIC_REG(0x120)
53 },
54 /* crb_sts_consumer: */
55 NETXEN_NIC_REG(0x138),
56 },
3176ff3e
MT		 57 /*
58 * Instance 1,
59 */
60 {
7830b22c
DP		 61 /* crb_rcv_producer: */
62 {
63 NETXEN_NIC_REG(0x144),
64 /* Jumbo frames */
65 NETXEN_NIC_REG(0x154),
66 /* LRO */
67 NETXEN_NIC_REG(0x164)
68 },
69 /* crb_sts_consumer: */
70 NETXEN_NIC_REG(0x17c),
71 },
595e3fb8 72 /*
6c80b18d 73 * Instance 2,
595e3fb8
MT		 74 */
75 {
7830b22c
DP		 76 /* crb_rcv_producer: */
77 {
78 NETXEN_NIC_REG(0x1d8),
79 /* Jumbo frames */
80 NETXEN_NIC_REG(0x1f8),
81 /* LRO */
82 NETXEN_NIC_REG(0x208)
83 },
84 /* crb_sts_consumer: */
85 NETXEN_NIC_REG(0x220),
595e3fb8
MT		 86 },
87 /*
6c80b18d 88 * Instance 3,
595e3fb8
MT		 89 */
90 {
7830b22c
DP		 91 /* crb_rcv_producer: */
92 {
93 NETXEN_NIC_REG(0x22c),
94 /* Jumbo frames */
95 NETXEN_NIC_REG(0x23c),
96 /* LRO */
97 NETXEN_NIC_REG(0x24c)
98 },
99 /* crb_sts_consumer: */
100 NETXEN_NIC_REG(0x264),
595e3fb8 101 },
3176ff3e
MT		 102};
103
993fb90c 104static u64 ctx_addr_sig_regs[][3] = {
3176ff3e
MT		 105 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
106 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
107 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
108 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
109};
993fb90c
AB		 110#define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
111#define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
112#define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
3176ff3e
MT		 113
114
3d396eb1
AK		 115/* PCI Windowing for DDR regions. */
116
117#define ADDR_IN_RANGE(addr, low, high) \
118 (((addr) <= (high)) && ((addr) >= (low)))
119
0d04761d 120#define NETXEN_FLASH_BASE (NETXEN_BOOTLD_START)
3d396eb1 121#define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
ed25ffa1 122#define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
cb8011ad 123#define NETXEN_MIN_MTU 64
3d396eb1
AK		 124#define NETXEN_ETH_FCS_SIZE 4
125#define NETXEN_ENET_HEADER_SIZE 14
cb8011ad 126#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1
AK		 127#define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
128#define NETXEN_NIU_HDRSIZE (0x1 << 6)
129#define NETXEN_NIU_TLRSIZE (0x1 << 5)
130
cb8011ad
AK		 131#define lower32(x) ((u32)((x) & 0xffffffff))
132#define upper32(x) \
133 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
134
135#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
136#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
137#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
138#define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
139
140#define NETXEN_NIC_WINDOW_MARGIN 0x100000
141
993fb90c
AB		 142static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
143 unsigned long long addr);
3d396eb1
AK		 144void netxen_free_hw_resources(struct netxen_adapter *adapter);
145
146int netxen_nic_set_mac(struct net_device *netdev, void *p)
147{
3176ff3e 148 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1
AK		 149 struct sockaddr *addr = p;
150
151 if (netif_running(netdev))
152 return -EBUSY;
153
154 if (!is_valid_ether_addr(addr->sa_data))
155 return -EADDRNOTAVAIL;
156
157 DPRINTK(INFO, "valid ether addr\n");
158 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
159
80922fbc 160 if (adapter->macaddr_set)
3176ff3e 161 adapter->macaddr_set(adapter, addr->sa_data);
3d396eb1
AK		 162
163 return 0;
164}
165
166/*
167 * netxen_nic_set_multi - Multicast
168 */
169void netxen_nic_set_multi(struct net_device *netdev)
170{
3176ff3e 171 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1 172 struct dev_mc_list *mc_ptr;
3d396eb1
AK		 173
174 mc_ptr = netdev->mc_list;
175 if (netdev->flags & IFF_PROMISC) {
80922fbc
AK		 176 if (adapter->set_promisc)
177 adapter->set_promisc(adapter,
80922fbc 178 NETXEN_NIU_PROMISC_MODE);
3d396eb1 179 } else {
6c80b18d 180 if (adapter->unset_promisc)
80922fbc 181 adapter->unset_promisc(adapter,
80922fbc 182 NETXEN_NIU_NON_PROMISC_MODE);
3d396eb1 183 }
3d396eb1
AK		 184}
185
186/*
187 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
188 * @returns 0 on success, negative on failure
189 */
190int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
191{
3176ff3e 192 struct netxen_adapter *adapter = netdev_priv(netdev);
3d396eb1
AK		 193 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
194
195 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
196 printk(KERN_ERR "%s: %s %d is not supported.\n",
197 netxen_nic_driver_name, netdev->name, mtu);
198 return -EINVAL;
199 }
200
80922fbc 201 if (adapter->set_mtu)
3176ff3e 202 adapter->set_mtu(adapter, mtu);
3d396eb1
AK		 203 netdev->mtu = mtu;
204
205 return 0;
206}
207
208/*
209 * check if the firmware has been downloaded and ready to run and
210 * setup the address for the descriptors in the adapter
211 */
212int netxen_nic_hw_resources(struct netxen_adapter *adapter)
213{
214 struct netxen_hardware_context *hw = &adapter->ahw;
3d396eb1
AK		 215 u32 state = 0;
216 void *addr;
217 int loops = 0, err = 0;
218 int ctx, ring;
3d396eb1
AK		 219 struct netxen_recv_context *recv_ctx;
220 struct netxen_rcv_desc_ctx *rcv_desc;
595e3fb8 221 int func_id = adapter->portnum;
3d396eb1 222
80922fbc 223 DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
cb8011ad 224 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
80922fbc 225 DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
cb8011ad 226 pci_base_offset(adapter, NETXEN_CRB_CAM));
80922fbc 227 DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
cb8011ad 228 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
3d396eb1 229
3d396eb1
AK		 230
231 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
232 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
233 loops = 0;
234 state = 0;
235 /* Window 1 call */
7830b22c 236 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_RCVPEG_STATE));
3d396eb1 237 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
96acb6eb 238 msleep(1);
3d396eb1
AK		 239 /* Window 1 call */
240 state = readl(NETXEN_CRB_NORMALIZE(adapter,
7830b22c 241 CRB_RCVPEG_STATE));
3d396eb1
AK		 242 loops++;
243 }
244 if (loops >= 20) {
245 printk(KERN_ERR "Rcv Peg initialization not complete:"
246 "%x.\n", state);
247 err = -EIO;
248 return err;
249 }
250 }
2d1a3bbd 251 adapter->intr_scheme = readl(
252 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW));
443be796
DP		 253 adapter->msi_mode = readl(
254 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW));
3d396eb1 255
7830b22c
DP		 256 addr = pci_alloc_consistent(adapter->pdev,
257 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
258 &adapter->ctx_desc_phys_addr);
cb8011ad 259
3d396eb1
AK		 260 if (addr == NULL) {
261 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
ed25ffa1
AK		 262 err = -ENOMEM;
263 return err;
cb8011ad 264 }
ed25ffa1
AK		 265 memset(addr, 0, sizeof(struct netxen_ring_ctx));
266 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
6c80b18d 267 adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
a608ab9c
AV		 268 adapter->ctx_desc->cmd_consumer_offset =
269 cpu_to_le64(adapter->ctx_desc_phys_addr +
270 sizeof(struct netxen_ring_ctx));
f305f789 271 adapter->cmd_consumer = (__le32 *) (((char *)addr) +
ed25ffa1
AK		 272 sizeof(struct netxen_ring_ctx));
273
7830b22c 274 addr = pci_alloc_consistent(adapter->pdev,
9de06610
AK		 275 sizeof(struct cmd_desc_type0) *
276 adapter->max_tx_desc_count,
7830b22c 277 &hw->cmd_desc_phys_addr);
cb8011ad 278
ed25ffa1
AK		 279 if (addr == NULL) {
280 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
281 netxen_free_hw_resources(adapter);
cb8011ad 282 return -ENOMEM;
3d396eb1
AK		 283 }
284
a608ab9c
AV		 285 adapter->ctx_desc->cmd_ring_addr =
286 cpu_to_le64(hw->cmd_desc_phys_addr);
287 adapter->ctx_desc->cmd_ring_size =
288 cpu_to_le32(adapter->max_tx_desc_count);
3d396eb1
AK		 289
290 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
291
292 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
293 recv_ctx = &adapter->recv_ctx[ctx];
294
295 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
296 rcv_desc = &recv_ctx->rcv_desc[ring];
7830b22c 297 addr = pci_alloc_consistent(adapter->pdev,
cb8011ad 298 RCV_DESC_RINGSIZE,
7830b22c 299 &rcv_desc->phys_addr);
3d396eb1
AK		 300 if (addr == NULL) {
301 DPRINTK(ERR, "bad return from "
302 "pci_alloc_consistent\n");
303 netxen_free_hw_resources(adapter);
304 err = -ENOMEM;
305 return err;
306 }
307 rcv_desc->desc_head = (struct rcv_desc *)addr;
a608ab9c
AV		 308 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
309 cpu_to_le64(rcv_desc->phys_addr);
ed25ffa1 310 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
a608ab9c 311 cpu_to_le32(rcv_desc->max_rx_desc_count);
7830b22c
DP		 312 rcv_desc->crb_rcv_producer =
313 recv_crb_registers[adapter->portnum].
314 crb_rcv_producer[ring];
3d396eb1
AK		 315 }
316
7830b22c
DP		 317 addr = pci_alloc_consistent(adapter->pdev, STATUS_DESC_RINGSIZE,
318 &recv_ctx->rcv_status_desc_phys_addr);
3d396eb1
AK		 319 if (addr == NULL) {
320 DPRINTK(ERR, "bad return from"
321 " pci_alloc_consistent\n");
322 netxen_free_hw_resources(adapter);
323 err = -ENOMEM;
324 return err;
325 }
326 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
a608ab9c
AV		 327 adapter->ctx_desc->sts_ring_addr =
328 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
329 adapter->ctx_desc->sts_ring_size =
330 cpu_to_le32(adapter->max_rx_desc_count);
7830b22c
DP		 331 recv_ctx->crb_sts_consumer =
332 recv_crb_registers[adapter->portnum].crb_sts_consumer;
3d396eb1 333
3d396eb1
AK		 334 }
335 /* Window = 1 */
ed25ffa1
AK		 336
337 writel(lower32(adapter->ctx_desc_phys_addr),
595e3fb8 338 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id)));
ed25ffa1 339 writel(upper32(adapter->ctx_desc_phys_addr),
595e3fb8
MT		 340 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id)));
341 writel(NETXEN_CTX_SIGNATURE | func_id,
342 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id)));
3d396eb1
AK		 343 return err;
344}
345
346void netxen_free_hw_resources(struct netxen_adapter *adapter)
347{
348 struct netxen_recv_context *recv_ctx;
349 struct netxen_rcv_desc_ctx *rcv_desc;
350 int ctx, ring;
351
ed25ffa1 352 if (adapter->ctx_desc != NULL) {
7830b22c 353 pci_free_consistent(adapter->pdev,
ed25ffa1
AK		 354 sizeof(struct netxen_ring_ctx) +
355 sizeof(uint32_t),
356 adapter->ctx_desc,
357 adapter->ctx_desc_phys_addr);
358 adapter->ctx_desc = NULL;
359 }
360
3d396eb1 361 if (adapter->ahw.cmd_desc_head != NULL) {
7830b22c 362 pci_free_consistent(adapter->pdev,
3d396eb1
AK		 363 sizeof(struct cmd_desc_type0) *
364 adapter->max_tx_desc_count,
365 adapter->ahw.cmd_desc_head,
366 adapter->ahw.cmd_desc_phys_addr);
367 adapter->ahw.cmd_desc_head = NULL;
368 }
369
370 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
371 recv_ctx = &adapter->recv_ctx[ctx];
372 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
373 rcv_desc = &recv_ctx->rcv_desc[ring];
374
375 if (rcv_desc->desc_head != NULL) {
7830b22c 376 pci_free_consistent(adapter->pdev,
3d396eb1
AK		 377 RCV_DESC_RINGSIZE,
378 rcv_desc->desc_head,
379 rcv_desc->phys_addr);
380 rcv_desc->desc_head = NULL;
381 }
382 }
383
384 if (recv_ctx->rcv_status_desc_head != NULL) {
7830b22c 385 pci_free_consistent(adapter->pdev,
3d396eb1
AK		 386 STATUS_DESC_RINGSIZE,
387 recv_ctx->rcv_status_desc_head,
388 recv_ctx->
389 rcv_status_desc_phys_addr);
390 recv_ctx->rcv_status_desc_head = NULL;
391 }
392 }
393}
394
395void netxen_tso_check(struct netxen_adapter *adapter,
396 struct cmd_desc_type0 *desc, struct sk_buff *skb)
397{
398 if (desc->mss) {
c9bdd4b5 399 desc->total_hdr_length = (sizeof(struct ethhdr) +
ab6a5bb6 400 ip_hdrlen(skb) + tcp_hdrlen(skb));
ed25ffa1 401 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
c75e86b4 402 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 403 if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
ed25ffa1 404 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
eddc9ec5 405 } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
ed25ffa1 406 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
3d396eb1
AK		 407 } else {
408 return;
409 }
410 }
ea2ae17d 411 desc->tcp_hdr_offset = skb_transport_offset(skb);
bbe735e4 412 desc->ip_hdr_offset = skb_network_offset(skb);
3d396eb1
AK		 413}
414
415int netxen_is_flash_supported(struct netxen_adapter *adapter)
416{
417 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
418 int addr, val01, val02, i, j;
419
420 /* if the flash size less than 4Mb, make huge war cry and die */
421 for (j = 1; j < 4; j++) {
cb8011ad 422 addr = j * NETXEN_NIC_WINDOW_MARGIN;
ff8ac609 423 for (i = 0; i < ARRAY_SIZE(locs); i++) {
3d396eb1
AK		 424 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
425 && netxen_rom_fast_read(adapter, (addr + locs[i]),
426 &val02) == 0) {
427 if (val01 == val02)
428 return -1;
429 } else
430 return -1;
431 }
432 }
433
434 return 0;
435}
436
437static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 438 int size, __le32 * buf)
3d396eb1
AK		 439{
440 int i, addr;
f305f789
AV		 441 __le32 *ptr32;
442 u32 v;
3d396eb1
AK		 443
444 addr = base;
445 ptr32 = buf;
446 for (i = 0; i < size / sizeof(u32); i++) {
f305f789 447 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 448 return -1;
f305f789 449 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 450 ptr32++;
451 addr += sizeof(u32);
452 }
453 if ((char *)buf + size > (char *)ptr32) {
f305f789
AV		 454 __le32 local;
455 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
3d396eb1 456 return -1;
f305f789 457 local = cpu_to_le32(v);
3d396eb1
AK		 458 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
459 }
460
461 return 0;
462}
463
f305f789 464int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
3d396eb1 465{
f305f789 466 __le32 *pmac = (__le32 *) & mac[0];
3d396eb1
AK		 467
468 if (netxen_get_flash_block(adapter,
0d04761d 469 NETXEN_USER_START +
3d396eb1
AK		 470 offsetof(struct netxen_new_user_info,
471 mac_addr),
472 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
473 return -1;
474 }
f305f789 475 if (*mac == cpu_to_le64(~0ULL)) {
3d396eb1 476 if (netxen_get_flash_block(adapter,
0d04761d 477 NETXEN_USER_START_OLD +
3d396eb1
AK		 478 offsetof(struct netxen_user_old_info,
479 mac_addr),
480 FLASH_NUM_PORTS * sizeof(u64),
481 pmac) == -1)
482 return -1;
f305f789 483 if (*mac == cpu_to_le64(~0ULL))
3d396eb1
AK		 484 return -1;
485 }
486 return 0;
487}
488
489/*
490 * Changes the CRB window to the specified window.
491 */
492void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
493{
494 void __iomem *offset;
495 u32 tmp;
496 int count = 0;
497
498 if (adapter->curr_window == wndw)
499 return;
13ba9c77 500 switch(adapter->ahw.pci_func) {
3176ff3e
MT		 501 case 0:
502 offset = PCI_OFFSET_SECOND_RANGE(adapter,
503 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
504 break;
505 case 1:
506 offset = PCI_OFFSET_SECOND_RANGE(adapter,
507 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1));
508 break;
509 case 2:
510 offset = PCI_OFFSET_SECOND_RANGE(adapter,
511 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2));
512 break;
513 case 3:
514 offset = PCI_OFFSET_SECOND_RANGE(adapter,
515 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3));
516 break;
517 default:
5bc51424 518 printk(KERN_INFO "Changing the window for PCI function "
13ba9c77 519 "%d\n", adapter->ahw.pci_func);
3176ff3e
MT		 520 offset = PCI_OFFSET_SECOND_RANGE(adapter,
521 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
522 break;
523 }
3d396eb1
AK		 524 /*
525 * Move the CRB window.
526 * We need to write to the "direct access" region of PCI
527 * to avoid a race condition where the window register has
528 * not been successfully written across CRB before the target
529 * register address is received by PCI. The direct region bypasses
530 * the CRB bus.
531 */
3d396eb1
AK		 532
533 if (wndw & 0x1)
534 wndw = NETXEN_WINDOW_ONE;
535
536 writel(wndw, offset);
537
538 /* MUST make sure window is set before we forge on... */
539 while ((tmp = readl(offset)) != wndw) {
540 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
541 "registered properly: 0x%08x.\n",
542 netxen_nic_driver_name, __FUNCTION__, tmp);
543 mdelay(1);
544 if (count >= 10)
545 break;
546 count++;
547 }
548
6c80b18d
MT		 549 if (wndw == NETXEN_WINDOW_ONE)
550 adapter->curr_window = 1;
551 else
552 adapter->curr_window = 0;
3d396eb1
AK		 553}
554
96acb6eb 555int netxen_load_firmware(struct netxen_adapter *adapter)
3d396eb1
AK		 556{
557 int i;
e0e20a1a
LCMT		 558 u32 data, size = 0;
559 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
3d396eb1
AK		 560 u64 off;
561 void __iomem *addr;
562
563 size = NETXEN_FIRMWARE_LEN;
564 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
565
566 for (i = 0; i < size; i++) {
96acb6eb
DP		 567 int retries = 10;
568 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
569 return -EIO;
570
cb8011ad
AK		 571 off = netxen_nic_pci_set_window(adapter, memaddr);
572 addr = pci_base_offset(adapter, off);
3d396eb1 573 writel(data, addr);
96acb6eb
DP		 574 do {
575 if (readl(addr) == data)
576 break;
577 msleep(100);
578 writel(data, addr);
579 } while (--retries);
580 if (!retries) {
581 printk(KERN_ERR "%s: firmware load aborted, write failed at 0x%x\n",
582 netxen_nic_driver_name, memaddr);
583 return -EIO;
584 }
3d396eb1
AK		 585 flashaddr += 4;
586 memaddr += 4;
587 }
588 udelay(100);
589 /* make sure Casper is powered on */
590 writel(0x3fff,
591 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
592 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
593
96acb6eb 594 return 0;
3d396eb1
AK		 595}
596
597int
598netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
599 int len)
600{
601 void __iomem *addr;
602
603 if (ADDR_IN_WINDOW1(off)) {
604 addr = NETXEN_CRB_NORMALIZE(adapter, off);
605 } else { /* Window 0 */
cb8011ad 606 addr = pci_base_offset(adapter, off);
3d396eb1
AK		 607 netxen_nic_pci_change_crbwindow(adapter, 0);
608 }
609
610 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
611 " data %llx len %d\n",
cb8011ad 612 pci_base(adapter, off), off, addr,
3d396eb1 613 *(unsigned long long *)data, len);
cb8011ad
AK		 614 if (!addr) {
615 netxen_nic_pci_change_crbwindow(adapter, 1);
616 return 1;
617 }
618
3d396eb1
AK		 619 switch (len) {
620 case 1:
621 writeb(*(u8 *) data, addr);
622 break;
623 case 2:
624 writew(*(u16 *) data, addr);
625 break;
626 case 4:
627 writel(*(u32 *) data, addr);
628 break;
629 case 8:
630 writeq(*(u64 *) data, addr);
631 break;
632 default:
633 DPRINTK(INFO,
634 "writing data %lx to offset %llx, num words=%d\n",
635 *(unsigned long *)data, off, (len >> 3));
636
637 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
638 (len >> 3));
639 break;
640 }
641 if (!ADDR_IN_WINDOW1(off))
642 netxen_nic_pci_change_crbwindow(adapter, 1);
643
644 return 0;
645}
646
647int
648netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
649 int len)
650{
651 void __iomem *addr;
652
653 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
654 addr = NETXEN_CRB_NORMALIZE(adapter, off);
655 } else { /* Window 0 */
cb8011ad 656 addr = pci_base_offset(adapter, off);
3d396eb1
AK		 657 netxen_nic_pci_change_crbwindow(adapter, 0);
658 }
659
660 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
cb8011ad
AK		 661 pci_base(adapter, off), off, addr);
662 if (!addr) {
663 netxen_nic_pci_change_crbwindow(adapter, 1);
664 return 1;
665 }
3d396eb1
AK		 666 switch (len) {
667 case 1:
668 *(u8 *) data = readb(addr);
669 break;
670 case 2:
671 *(u16 *) data = readw(addr);
672 break;
673 case 4:
674 *(u32 *) data = readl(addr);
675 break;
676 case 8:
677 *(u64 *) data = readq(addr);
678 break;
679 default:
680 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
681 (len >> 3));
682 break;
683 }
684 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
685
686 if (!ADDR_IN_WINDOW1(off))
687 netxen_nic_pci_change_crbwindow(adapter, 1);
688
689 return 0;
690}
691
692void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
693{ /* Only for window 1 */
694 void __iomem *addr;
695
696 addr = NETXEN_CRB_NORMALIZE(adapter, off);
697 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
80922fbc 698 pci_base(adapter, off), off, addr, val);
3d396eb1
AK		 699 writel(val, addr);
700
701}
702
703int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
704{ /* Only for window 1 */
705 void __iomem *addr;
706 int val;
707
708 addr = NETXEN_CRB_NORMALIZE(adapter, off);
709 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
80922fbc 710 pci_base(adapter, off), off, addr);
3d396eb1
AK		 711 val = readl(addr);
712 writel(val, addr);
713
714 return val;
715}
716
717/* Change the window to 0, write and change back to window 1. */
718void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
719{
720 void __iomem *addr;
721
722 netxen_nic_pci_change_crbwindow(adapter, 0);
71bd7877 723 addr = pci_base_offset(adapter, index);
3d396eb1
AK		 724 writel(value, addr);
725 netxen_nic_pci_change_crbwindow(adapter, 1);
726}
727
728/* Change the window to 0, read and change back to window 1. */
729void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
730{
731 void __iomem *addr;
732
71bd7877 733 addr = pci_base_offset(adapter, index);
3d396eb1
AK		 734
735 netxen_nic_pci_change_crbwindow(adapter, 0);
736 *value = readl(addr);
737 netxen_nic_pci_change_crbwindow(adapter, 1);
738}
739
4790654c 740static int netxen_pci_set_window_warning_count;
3d396eb1 741
993fb90c
AB		 742static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
743 unsigned long long addr)
3d396eb1
AK		 744{
745 static int ddr_mn_window = -1;
746 static int qdr_sn_window = -1;
747 int window;
748
749 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
750 /* DDR network side */
751 addr -= NETXEN_ADDR_DDR_NET;
752 window = (addr >> 25) & 0x3ff;
753 if (ddr_mn_window != window) {
754 ddr_mn_window = window;
cb8011ad
AK		 755 writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
756 NETXEN_PCIX_PH_REG
3052246c 757 (PCIX_MN_WINDOW(adapter->ahw.pci_func))));
3d396eb1 758 /* MUST make sure window is set before we forge on... */
cb8011ad
AK		 759 readl(PCI_OFFSET_SECOND_RANGE(adapter,
760 NETXEN_PCIX_PH_REG
3052246c 761 (PCIX_MN_WINDOW(adapter->ahw.pci_func))));
3d396eb1 762 }
cb8011ad 763 addr -= (window * NETXEN_WINDOW_ONE);
3d396eb1
AK		 764 addr += NETXEN_PCI_DDR_NET;
765 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
766 addr -= NETXEN_ADDR_OCM0;
767 addr += NETXEN_PCI_OCM0;
768 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
769 addr -= NETXEN_ADDR_OCM1;
770 addr += NETXEN_PCI_OCM1;
771 } else
772 if (ADDR_IN_RANGE
773 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
774 /* QDR network side */
775 addr -= NETXEN_ADDR_QDR_NET;
776 window = (addr >> 22) & 0x3f;
777 if (qdr_sn_window != window) {
778 qdr_sn_window = window;
cb8011ad
AK		 779 writel((window << 22),
780 PCI_OFFSET_SECOND_RANGE(adapter,
781 NETXEN_PCIX_PH_REG
3052246c 782 (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
3d396eb1 783 /* MUST make sure window is set before we forge on... */
cb8011ad
AK		 784 readl(PCI_OFFSET_SECOND_RANGE(adapter,
785 NETXEN_PCIX_PH_REG
3052246c 786 (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
3d396eb1
AK		 787 }
788 addr -= (window * 0x400000);
789 addr += NETXEN_PCI_QDR_NET;
790 } else {
791 /*
792 * peg gdb frequently accesses memory that doesn't exist,
793 * this limits the chit chat so debugging isn't slowed down.
794 */
795 if ((netxen_pci_set_window_warning_count++ < 8)
796 || (netxen_pci_set_window_warning_count % 64 == 0))
797 printk("%s: Warning:netxen_nic_pci_set_window()"
798 " Unknown address range!\n",
799 netxen_nic_driver_name);
800
801 }
802 return addr;
803}
804
993fb90c 805#if 0
13ba9c77
MT		 806int
807netxen_nic_erase_pxe(struct netxen_adapter *adapter)
808{
0d04761d 809 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
4790654c 810 printk(KERN_ERR "%s: erase pxe failed\n",
13ba9c77
MT		 811 netxen_nic_driver_name);
812 return -1;
813 }
814 return 0;
815}
993fb90c 816#endif /* 0 */
13ba9c77 817
3d396eb1
AK		 818int netxen_nic_get_board_info(struct netxen_adapter *adapter)
819{
820 int rv = 0;
0d04761d 821 int addr = NETXEN_BRDCFG_START;
3d396eb1
AK		 822 struct netxen_board_info *boardinfo;
823 int index;
824 u32 *ptr32;
825
826 boardinfo = &adapter->ahw.boardcfg;
827 ptr32 = (u32 *) boardinfo;
828
829 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
830 index++) {
831 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
832 return -EIO;
833 }
834 ptr32++;
835 addr += sizeof(u32);
836 }
837 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
838 printk("%s: ERROR reading %s board config."
839 " Read %x, expected %x\n", netxen_nic_driver_name,
840 netxen_nic_driver_name,
841 boardinfo->magic, NETXEN_BDINFO_MAGIC);
842 rv = -1;
843 }
844 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
845 printk("%s: Unknown board config version."
846 " Read %x, expected %x\n", netxen_nic_driver_name,
847 boardinfo->header_version, NETXEN_BDINFO_VERSION);
848 rv = -1;
849 }
850
851 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
852 switch ((netxen_brdtype_t) boardinfo->board_type) {
853 case NETXEN_BRDTYPE_P2_SB35_4G:
854 adapter->ahw.board_type = NETXEN_NIC_GBE;
855 break;
856 case NETXEN_BRDTYPE_P2_SB31_10G:
857 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
858 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
859 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
860 adapter->ahw.board_type = NETXEN_NIC_XGBE;
861 break;
862 case NETXEN_BRDTYPE_P1_BD:
863 case NETXEN_BRDTYPE_P1_SB:
864 case NETXEN_BRDTYPE_P1_SMAX:
865 case NETXEN_BRDTYPE_P1_SOCK:
866 adapter->ahw.board_type = NETXEN_NIC_GBE;
867 break;
868 default:
869 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
870 boardinfo->board_type);
871 break;
872 }
873
874 return rv;
875}
876
877/* NIU access sections */
878
3176ff3e 879int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 880{
3d396eb1 881 netxen_nic_write_w0(adapter,
3276fbad
DP		 882 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
883 new_mtu);
3d396eb1
AK		 884 return 0;
885}
886
3176ff3e 887int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 888{
3d396eb1 889 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
3276fbad 890 if (adapter->physical_port == 0)
4790654c 891 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
595e3fb8 892 new_mtu);
4790654c 893 else
595e3fb8
MT		 894 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
895 new_mtu);
3d396eb1
AK		 896 return 0;
897}
898
899void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
900{
3276fbad 901 netxen_niu_gbe_init_port(adapter, adapter->physical_port);
3d396eb1
AK		 902}
903
904void
905netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
906 int data)
907{
908 void __iomem *addr;
909
910 if (ADDR_IN_WINDOW1(off)) {
911 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
912 } else {
913 netxen_nic_pci_change_crbwindow(adapter, 0);
71bd7877 914 addr = pci_base_offset(adapter, off);
3d396eb1
AK		 915 writel(data, addr);
916 netxen_nic_pci_change_crbwindow(adapter, 1);
917 }
918}
919
3176ff3e 920void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 921{
a608ab9c
AV		 922 __u32 status;
923 __u32 autoneg;
924 __u32 mode;
3d396eb1
AK		 925
926 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
927 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
80922fbc
AK		 928 if (adapter->phy_read
929 && adapter->
13ba9c77 930 phy_read(adapter,
3d396eb1
AK		 931 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
932 &status) == 0) {
933 if (netxen_get_phy_link(status)) {
934 switch (netxen_get_phy_speed(status)) {
935 case 0:
3176ff3e 936 adapter->link_speed = SPEED_10;
3d396eb1
AK		 937 break;
938 case 1:
3176ff3e 939 adapter->link_speed = SPEED_100;
3d396eb1
AK		 940 break;
941 case 2:
3176ff3e 942 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 943 break;
944 default:
3176ff3e 945 adapter->link_speed = -1;
3d396eb1
AK		 946 break;
947 }
948 switch (netxen_get_phy_duplex(status)) {
949 case 0:
3176ff3e 950 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 951 break;
952 case 1:
3176ff3e 953 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 954 break;
955 default:
3176ff3e 956 adapter->link_duplex = -1;
3d396eb1
AK		 957 break;
958 }
80922fbc
AK		 959 if (adapter->phy_read
960 && adapter->
13ba9c77 961 phy_read(adapter,
3d396eb1 962 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
ed25ffa1 963 &autoneg) != 0)
3176ff3e 964 adapter->link_autoneg = autoneg;
3d396eb1
AK		 965 } else
966 goto link_down;
967 } else {
968 link_down:
3176ff3e
MT		 969 adapter->link_speed = -1;
970 adapter->link_duplex = -1;
3d396eb1
AK		 971 }
972 }
973}
974
975void netxen_nic_flash_print(struct netxen_adapter *adapter)
976{
3d396eb1
AK		 977 u32 fw_major = 0;
978 u32 fw_minor = 0;
979 u32 fw_build = 0;
cb8011ad 980 char brd_name[NETXEN_MAX_SHORT_NAME];
8d74849b
HH		 981 char serial_num[32];
982 int i, addr;
6d1495f2 983 __le32 *ptr32;
3d396eb1
AK		 984
985 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
dcd56fdb
DP		 986
987 adapter->driver_mismatch = 0;
988
989 ptr32 = (u32 *)&serial_num;
990 addr = NETXEN_USER_START +
991 offsetof(struct netxen_new_user_info, serial_num);
992 for (i = 0; i < 8; i++) {
993 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
994 printk("%s: ERROR reading %s board userarea.\n",
995 netxen_nic_driver_name,
996 netxen_nic_driver_name);
997 adapter->driver_mismatch = 1;
998 return;
cb8011ad 999 }
dcd56fdb
DP		 1000 ptr32++;
1001 addr += sizeof(u32);
1002 }
1003
1004 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
1005 NETXEN_FW_VERSION_MAJOR));
1006 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
1007 NETXEN_FW_VERSION_MINOR));
1008 fw_build =
1009 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
8d74849b 1010
dcd56fdb 1011 if (adapter->portnum == 0) {
cb8011ad
AK		 1012 get_brd_name_by_type(board_info->board_type, brd_name);
1013
1014 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
dcd56fdb
DP		 1015 brd_name, serial_num, board_info->chip_id);
1016 printk("NetXen Firmware version %d.%d.%d\n", fw_major,
1017 fw_minor, fw_build);
3d396eb1 1018 }
dcd56fdb 1019
3d396eb1 1020 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
3d396eb1
AK		 1021 adapter->driver_mismatch = 1;
1022 }
90f8b1d2
AK		 1023 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
1024 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
3d396eb1
AK		 1025 adapter->driver_mismatch = 1;
1026 }
dcd56fdb
DP		 1027 if (adapter->driver_mismatch) {
1028 printk(KERN_ERR "%s: driver and firmware version mismatch\n",
1029 adapter->netdev->name);
1030 return;
1031 }
1032
1033 switch (adapter->ahw.board_type) {
1034 case NETXEN_NIC_GBE:
1035 dev_info(&adapter->pdev->dev, "%s: GbE port initialized\n",
1036 adapter->netdev->name);
1037 break;
1038 case NETXEN_NIC_XGBE:
1039 dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
1040 adapter->netdev->name);
1041 break;
1042 }
3d396eb1
AK		 1043}
1044
Linux kernel - Deliverables
This page took 0.6739 seconds and 5 git commands to generate.