Commit | Line | Data |
---|---|---|
3d396eb1 | 1 | /* |
5d242f1c | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
13af7a6e | 3 | * Copyright (C) 2009 - QLogic Corporation. |
3d396eb1 | 4 | * All rights reserved. |
80922fbc | 5 | * |
3d396eb1 AK |
6 | * This program is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
80922fbc | 10 | * |
3d396eb1 AK |
11 | * This program is distributed in the hope that it will be useful, but |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
80922fbc | 15 | * |
3d396eb1 AK |
16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
19 | * MA 02111-1307, USA. | |
80922fbc | 20 | * |
3d396eb1 | 21 | * The full GNU General Public License is included in this distribution |
4d21fef4 | 22 | * in the file called "COPYING". |
80922fbc | 23 | * |
3d396eb1 AK |
24 | */ |
25 | ||
26 | #include <linux/netdevice.h> | |
27 | #include <linux/delay.h> | |
28 | #include "netxen_nic.h" | |
29 | #include "netxen_nic_hw.h" | |
3d396eb1 AK |
30 | |
31 | struct crb_addr_pair { | |
e0e20a1a LCMT |
32 | u32 addr; |
33 | u32 data; | |
3d396eb1 AK |
34 | }; |
35 | ||
36 | #define NETXEN_MAX_CRB_XFORM 60 | |
37 | static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM]; | |
e0e20a1a | 38 | #define NETXEN_ADDR_ERROR (0xffffffff) |
3d396eb1 AK |
39 | |
40 | #define crb_addr_transform(name) \ | |
41 | crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \ | |
42 | NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20 | |
43 | ||
cb8011ad AK |
44 | #define NETXEN_NIC_XDMA_RESET 0x8000ff |
45 | ||
becf46a0 | 46 | static void |
d8b100c5 DP |
47 | netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
48 | struct nx_host_rds_ring *rds_ring); | |
f50330f9 | 49 | static int netxen_p3_has_mn(struct netxen_adapter *adapter); |
993fb90c | 50 | |
3d396eb1 AK |
51 | static void crb_addr_transform_setup(void) |
52 | { | |
53 | crb_addr_transform(XDMA); | |
54 | crb_addr_transform(TIMR); | |
55 | crb_addr_transform(SRE); | |
56 | crb_addr_transform(SQN3); | |
57 | crb_addr_transform(SQN2); | |
58 | crb_addr_transform(SQN1); | |
59 | crb_addr_transform(SQN0); | |
60 | crb_addr_transform(SQS3); | |
61 | crb_addr_transform(SQS2); | |
62 | crb_addr_transform(SQS1); | |
63 | crb_addr_transform(SQS0); | |
64 | crb_addr_transform(RPMX7); | |
65 | crb_addr_transform(RPMX6); | |
66 | crb_addr_transform(RPMX5); | |
67 | crb_addr_transform(RPMX4); | |
68 | crb_addr_transform(RPMX3); | |
69 | crb_addr_transform(RPMX2); | |
70 | crb_addr_transform(RPMX1); | |
71 | crb_addr_transform(RPMX0); | |
72 | crb_addr_transform(ROMUSB); | |
73 | crb_addr_transform(SN); | |
74 | crb_addr_transform(QMN); | |
75 | crb_addr_transform(QMS); | |
76 | crb_addr_transform(PGNI); | |
77 | crb_addr_transform(PGND); | |
78 | crb_addr_transform(PGN3); | |
79 | crb_addr_transform(PGN2); | |
80 | crb_addr_transform(PGN1); | |
81 | crb_addr_transform(PGN0); | |
82 | crb_addr_transform(PGSI); | |
83 | crb_addr_transform(PGSD); | |
84 | crb_addr_transform(PGS3); | |
85 | crb_addr_transform(PGS2); | |
86 | crb_addr_transform(PGS1); | |
87 | crb_addr_transform(PGS0); | |
88 | crb_addr_transform(PS); | |
89 | crb_addr_transform(PH); | |
90 | crb_addr_transform(NIU); | |
91 | crb_addr_transform(I2Q); | |
92 | crb_addr_transform(EG); | |
93 | crb_addr_transform(MN); | |
94 | crb_addr_transform(MS); | |
95 | crb_addr_transform(CAS2); | |
96 | crb_addr_transform(CAS1); | |
97 | crb_addr_transform(CAS0); | |
98 | crb_addr_transform(CAM); | |
99 | crb_addr_transform(C2C1); | |
100 | crb_addr_transform(C2C0); | |
1fcca1a5 | 101 | crb_addr_transform(SMB); |
e4c93c81 DP |
102 | crb_addr_transform(OCM0); |
103 | crb_addr_transform(I2C0); | |
3d396eb1 AK |
104 | } |
105 | ||
2956640d | 106 | void netxen_release_rx_buffers(struct netxen_adapter *adapter) |
3d396eb1 | 107 | { |
2956640d | 108 | struct netxen_recv_context *recv_ctx; |
48bfd1e0 | 109 | struct nx_host_rds_ring *rds_ring; |
2956640d | 110 | struct netxen_rx_buffer *rx_buf; |
becf46a0 DP |
111 | int i, ring; |
112 | ||
113 | recv_ctx = &adapter->recv_ctx; | |
114 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
115 | rds_ring = &recv_ctx->rds_rings[ring]; | |
438627c7 | 116 | for (i = 0; i < rds_ring->num_desc; ++i) { |
becf46a0 DP |
117 | rx_buf = &(rds_ring->rx_buf_arr[i]); |
118 | if (rx_buf->state == NETXEN_BUFFER_FREE) | |
119 | continue; | |
120 | pci_unmap_single(adapter->pdev, | |
121 | rx_buf->dma, | |
122 | rds_ring->dma_size, | |
123 | PCI_DMA_FROMDEVICE); | |
124 | if (rx_buf->skb != NULL) | |
125 | dev_kfree_skb_any(rx_buf->skb); | |
2956640d DP |
126 | } |
127 | } | |
128 | } | |
129 | ||
130 | void netxen_release_tx_buffers(struct netxen_adapter *adapter) | |
131 | { | |
132 | struct netxen_cmd_buffer *cmd_buf; | |
133 | struct netxen_skb_frag *buffrag; | |
134 | int i, j; | |
4ea528a1 | 135 | struct nx_host_tx_ring *tx_ring = adapter->tx_ring; |
2956640d | 136 | |
d877f1e3 DP |
137 | cmd_buf = tx_ring->cmd_buf_arr; |
138 | for (i = 0; i < tx_ring->num_desc; i++) { | |
2956640d DP |
139 | buffrag = cmd_buf->frag_array; |
140 | if (buffrag->dma) { | |
141 | pci_unmap_single(adapter->pdev, buffrag->dma, | |
142 | buffrag->length, PCI_DMA_TODEVICE); | |
143 | buffrag->dma = 0ULL; | |
144 | } | |
145 | for (j = 0; j < cmd_buf->frag_count; j++) { | |
146 | buffrag++; | |
147 | if (buffrag->dma) { | |
148 | pci_unmap_page(adapter->pdev, buffrag->dma, | |
149 | buffrag->length, | |
150 | PCI_DMA_TODEVICE); | |
151 | buffrag->dma = 0ULL; | |
152 | } | |
153 | } | |
2956640d DP |
154 | if (cmd_buf->skb) { |
155 | dev_kfree_skb_any(cmd_buf->skb); | |
156 | cmd_buf->skb = NULL; | |
157 | } | |
158 | cmd_buf++; | |
159 | } | |
160 | } | |
161 | ||
162 | void netxen_free_sw_resources(struct netxen_adapter *adapter) | |
163 | { | |
164 | struct netxen_recv_context *recv_ctx; | |
48bfd1e0 | 165 | struct nx_host_rds_ring *rds_ring; |
d877f1e3 | 166 | struct nx_host_tx_ring *tx_ring; |
becf46a0 DP |
167 | int ring; |
168 | ||
169 | recv_ctx = &adapter->recv_ctx; | |
4ea528a1 DP |
170 | |
171 | if (recv_ctx->rds_rings == NULL) | |
172 | goto skip_rds; | |
173 | ||
becf46a0 DP |
174 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
175 | rds_ring = &recv_ctx->rds_rings[ring]; | |
f2333a01 F |
176 | vfree(rds_ring->rx_buf_arr); |
177 | rds_ring->rx_buf_arr = NULL; | |
2956640d | 178 | } |
4ea528a1 DP |
179 | kfree(recv_ctx->rds_rings); |
180 | ||
181 | skip_rds: | |
182 | if (adapter->tx_ring == NULL) | |
183 | return; | |
becf46a0 | 184 | |
4ea528a1 | 185 | tx_ring = adapter->tx_ring; |
f2333a01 | 186 | vfree(tx_ring->cmd_buf_arr); |
011f4ea0 AKS |
187 | kfree(tx_ring); |
188 | adapter->tx_ring = NULL; | |
2956640d DP |
189 | } |
190 | ||
191 | int netxen_alloc_sw_resources(struct netxen_adapter *adapter) | |
192 | { | |
193 | struct netxen_recv_context *recv_ctx; | |
48bfd1e0 | 194 | struct nx_host_rds_ring *rds_ring; |
d8b100c5 | 195 | struct nx_host_sds_ring *sds_ring; |
4ea528a1 | 196 | struct nx_host_tx_ring *tx_ring; |
2956640d | 197 | struct netxen_rx_buffer *rx_buf; |
4ea528a1 | 198 | int ring, i, size; |
2956640d DP |
199 | |
200 | struct netxen_cmd_buffer *cmd_buf_arr; | |
201 | struct net_device *netdev = adapter->netdev; | |
d877f1e3 | 202 | struct pci_dev *pdev = adapter->pdev; |
2956640d | 203 | |
4ea528a1 DP |
204 | size = sizeof(struct nx_host_tx_ring); |
205 | tx_ring = kzalloc(size, GFP_KERNEL); | |
206 | if (tx_ring == NULL) { | |
207 | dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n", | |
208 | netdev->name); | |
209 | return -ENOMEM; | |
210 | } | |
211 | adapter->tx_ring = tx_ring; | |
212 | ||
d877f1e3 | 213 | tx_ring->num_desc = adapter->num_txd; |
b2af9cb0 | 214 | tx_ring->txq = netdev_get_tx_queue(netdev, 0); |
4ea528a1 DP |
215 | |
216 | cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring)); | |
2956640d | 217 | if (cmd_buf_arr == NULL) { |
d877f1e3 | 218 | dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n", |
2956640d DP |
219 | netdev->name); |
220 | return -ENOMEM; | |
221 | } | |
d877f1e3 DP |
222 | memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring)); |
223 | tx_ring->cmd_buf_arr = cmd_buf_arr; | |
2956640d | 224 | |
becf46a0 | 225 | recv_ctx = &adapter->recv_ctx; |
4ea528a1 DP |
226 | |
227 | size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring); | |
228 | rds_ring = kzalloc(size, GFP_KERNEL); | |
229 | if (rds_ring == NULL) { | |
230 | dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n", | |
231 | netdev->name); | |
232 | return -ENOMEM; | |
233 | } | |
234 | recv_ctx->rds_rings = rds_ring; | |
235 | ||
becf46a0 DP |
236 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
237 | rds_ring = &recv_ctx->rds_rings[ring]; | |
438627c7 DP |
238 | switch (ring) { |
239 | case RCV_RING_NORMAL: | |
240 | rds_ring->num_desc = adapter->num_rxd; | |
becf46a0 DP |
241 | if (adapter->ahw.cut_through) { |
242 | rds_ring->dma_size = | |
243 | NX_CT_DEFAULT_RX_BUF_LEN; | |
48bfd1e0 | 244 | rds_ring->skb_size = |
becf46a0 DP |
245 | NX_CT_DEFAULT_RX_BUF_LEN; |
246 | } else { | |
9b08beba DP |
247 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
248 | rds_ring->dma_size = | |
249 | NX_P3_RX_BUF_MAX_LEN; | |
250 | else | |
251 | rds_ring->dma_size = | |
252 | NX_P2_RX_BUF_MAX_LEN; | |
becf46a0 | 253 | rds_ring->skb_size = |
9b08beba | 254 | rds_ring->dma_size + NET_IP_ALIGN; |
becf46a0 DP |
255 | } |
256 | break; | |
2956640d | 257 | |
438627c7 DP |
258 | case RCV_RING_JUMBO: |
259 | rds_ring->num_desc = adapter->num_jumbo_rxd; | |
becf46a0 DP |
260 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
261 | rds_ring->dma_size = | |
262 | NX_P3_RX_JUMBO_BUF_MAX_LEN; | |
263 | else | |
264 | rds_ring->dma_size = | |
265 | NX_P2_RX_JUMBO_BUF_MAX_LEN; | |
bc75e5bf DP |
266 | |
267 | if (adapter->capabilities & NX_CAP0_HW_LRO) | |
268 | rds_ring->dma_size += NX_LRO_BUFFER_EXTRA; | |
269 | ||
becf46a0 DP |
270 | rds_ring->skb_size = |
271 | rds_ring->dma_size + NET_IP_ALIGN; | |
272 | break; | |
2956640d | 273 | |
becf46a0 | 274 | case RCV_RING_LRO: |
438627c7 | 275 | rds_ring->num_desc = adapter->num_lro_rxd; |
9b08beba DP |
276 | rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH; |
277 | rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN; | |
becf46a0 DP |
278 | break; |
279 | ||
280 | } | |
281 | rds_ring->rx_buf_arr = (struct netxen_rx_buffer *) | |
d8b100c5 | 282 | vmalloc(RCV_BUFF_RINGSIZE(rds_ring)); |
becf46a0 DP |
283 | if (rds_ring->rx_buf_arr == NULL) { |
284 | printk(KERN_ERR "%s: Failed to allocate " | |
285 | "rx buffer ring %d\n", | |
286 | netdev->name, ring); | |
287 | /* free whatever was already allocated */ | |
288 | goto err_out; | |
289 | } | |
d8b100c5 | 290 | memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring)); |
becf46a0 DP |
291 | INIT_LIST_HEAD(&rds_ring->free_list); |
292 | /* | |
293 | * Now go through all of them, set reference handles | |
294 | * and put them in the queues. | |
295 | */ | |
becf46a0 | 296 | rx_buf = rds_ring->rx_buf_arr; |
4ea528a1 | 297 | for (i = 0; i < rds_ring->num_desc; i++) { |
becf46a0 DP |
298 | list_add_tail(&rx_buf->list, |
299 | &rds_ring->free_list); | |
300 | rx_buf->ref_handle = i; | |
301 | rx_buf->state = NETXEN_BUFFER_FREE; | |
302 | rx_buf++; | |
3d396eb1 | 303 | } |
d8b100c5 DP |
304 | spin_lock_init(&rds_ring->lock); |
305 | } | |
306 | ||
307 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { | |
308 | sds_ring = &recv_ctx->sds_rings[ring]; | |
309 | sds_ring->irq = adapter->msix_entries[ring].vector; | |
d8b100c5 DP |
310 | sds_ring->adapter = adapter; |
311 | sds_ring->num_desc = adapter->num_rxd; | |
312 | ||
313 | for (i = 0; i < NUM_RCV_DESC_RINGS; i++) | |
314 | INIT_LIST_HEAD(&sds_ring->free_list[i]); | |
3d396eb1 | 315 | } |
2956640d DP |
316 | |
317 | return 0; | |
318 | ||
319 | err_out: | |
320 | netxen_free_sw_resources(adapter); | |
321 | return -ENOMEM; | |
3d396eb1 AK |
322 | } |
323 | ||
3d396eb1 AK |
324 | /* |
325 | * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB | |
326 | * address to external PCI CRB address. | |
327 | */ | |
993fb90c | 328 | static u32 netxen_decode_crb_addr(u32 addr) |
3d396eb1 AK |
329 | { |
330 | int i; | |
e0e20a1a | 331 | u32 base_addr, offset, pci_base; |
3d396eb1 AK |
332 | |
333 | crb_addr_transform_setup(); | |
334 | ||
335 | pci_base = NETXEN_ADDR_ERROR; | |
336 | base_addr = addr & 0xfff00000; | |
337 | offset = addr & 0x000fffff; | |
338 | ||
339 | for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) { | |
340 | if (crb_addr_xform[i] == base_addr) { | |
341 | pci_base = i << 20; | |
342 | break; | |
343 | } | |
344 | } | |
345 | if (pci_base == NETXEN_ADDR_ERROR) | |
346 | return pci_base; | |
347 | else | |
348 | return (pci_base + offset); | |
349 | } | |
350 | ||
c9517e58 | 351 | #define NETXEN_MAX_ROM_WAIT_USEC 100 |
3d396eb1 | 352 | |
993fb90c | 353 | static int netxen_wait_rom_done(struct netxen_adapter *adapter) |
3d396eb1 AK |
354 | { |
355 | long timeout = 0; | |
356 | long done = 0; | |
357 | ||
27c915a4 DP |
358 | cond_resched(); |
359 | ||
3d396eb1 | 360 | while (done == 0) { |
f98a9f69 | 361 | done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS); |
3d396eb1 | 362 | done &= 2; |
c9517e58 DP |
363 | if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) { |
364 | dev_err(&adapter->pdev->dev, | |
365 | "Timeout reached waiting for rom done"); | |
3d396eb1 AK |
366 | return -EIO; |
367 | } | |
c9517e58 | 368 | udelay(1); |
3d396eb1 AK |
369 | } |
370 | return 0; | |
371 | } | |
372 | ||
993fb90c AB |
373 | static int do_rom_fast_read(struct netxen_adapter *adapter, |
374 | int addr, int *valp) | |
3d396eb1 | 375 | { |
f98a9f69 DP |
376 | NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); |
377 | NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); | |
378 | NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
379 | NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb); | |
3d396eb1 AK |
380 | if (netxen_wait_rom_done(adapter)) { |
381 | printk("Error waiting for rom done\n"); | |
382 | return -EIO; | |
383 | } | |
384 | /* reset abyte_cnt and dummy_byte_cnt */ | |
f98a9f69 | 385 | NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); |
27c915a4 | 386 | udelay(10); |
f98a9f69 | 387 | NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
3d396eb1 | 388 | |
f98a9f69 | 389 | *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA); |
3d396eb1 AK |
390 | return 0; |
391 | } | |
392 | ||
993fb90c AB |
393 | static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
394 | u8 *bytes, size_t size) | |
27d2ab54 AK |
395 | { |
396 | int addridx; | |
397 | int ret = 0; | |
398 | ||
399 | for (addridx = addr; addridx < (addr + size); addridx += 4) { | |
f305f789 AV |
400 | int v; |
401 | ret = do_rom_fast_read(adapter, addridx, &v); | |
27d2ab54 AK |
402 | if (ret != 0) |
403 | break; | |
f305f789 | 404 | *(__le32 *)bytes = cpu_to_le32(v); |
27d2ab54 AK |
405 | bytes += 4; |
406 | } | |
407 | ||
408 | return ret; | |
409 | } | |
410 | ||
411 | int | |
4790654c | 412 | netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
413 | u8 *bytes, size_t size) |
414 | { | |
415 | int ret; | |
416 | ||
c9517e58 | 417 | ret = netxen_rom_lock(adapter); |
27d2ab54 AK |
418 | if (ret < 0) |
419 | return ret; | |
420 | ||
421 | ret = do_rom_fast_read_words(adapter, addr, bytes, size); | |
422 | ||
423 | netxen_rom_unlock(adapter); | |
424 | return ret; | |
425 | } | |
426 | ||
3d396eb1 AK |
427 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp) |
428 | { | |
429 | int ret; | |
430 | ||
c9517e58 | 431 | if (netxen_rom_lock(adapter) != 0) |
3d396eb1 AK |
432 | return -EIO; |
433 | ||
434 | ret = do_rom_fast_read(adapter, addr, valp); | |
cb8011ad AK |
435 | netxen_rom_unlock(adapter); |
436 | return ret; | |
437 | } | |
438 | ||
3d396eb1 AK |
439 | #define NETXEN_BOARDTYPE 0x4008 |
440 | #define NETXEN_BOARDNUM 0x400c | |
441 | #define NETXEN_CHIPNUM 0x4010 | |
3d396eb1 | 442 | |
0be367bd | 443 | int netxen_pinit_from_rom(struct netxen_adapter *adapter) |
3d396eb1 | 444 | { |
dcd56fdb | 445 | int addr, val; |
27c915a4 | 446 | int i, n, init_delay = 0; |
3d396eb1 | 447 | struct crb_addr_pair *buf; |
27c915a4 | 448 | unsigned offset; |
e0e20a1a | 449 | u32 off; |
3d396eb1 AK |
450 | |
451 | /* resetall */ | |
c9517e58 | 452 | netxen_rom_lock(adapter); |
f98a9f69 | 453 | NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff); |
27c915a4 | 454 | netxen_rom_unlock(adapter); |
3d396eb1 | 455 | |
2956640d DP |
456 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
457 | if (netxen_rom_fast_read(adapter, 0, &n) != 0 || | |
27c915a4 | 458 | (n != 0xcafecafe) || |
2956640d DP |
459 | netxen_rom_fast_read(adapter, 4, &n) != 0) { |
460 | printk(KERN_ERR "%s: ERROR Reading crb_init area: " | |
461 | "n: %08x\n", netxen_nic_driver_name, n); | |
3d396eb1 AK |
462 | return -EIO; |
463 | } | |
2956640d DP |
464 | offset = n & 0xffffU; |
465 | n = (n >> 16) & 0xffffU; | |
466 | } else { | |
467 | if (netxen_rom_fast_read(adapter, 0, &n) != 0 || | |
468 | !(n & 0x80000000)) { | |
469 | printk(KERN_ERR "%s: ERROR Reading crb_init area: " | |
470 | "n: %08x\n", netxen_nic_driver_name, n); | |
471 | return -EIO; | |
3d396eb1 | 472 | } |
2956640d DP |
473 | offset = 1; |
474 | n &= ~0x80000000; | |
475 | } | |
476 | ||
0be367bd | 477 | if (n >= 1024) { |
2956640d DP |
478 | printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not" |
479 | " initialized.\n", __func__, n); | |
480 | return -EIO; | |
481 | } | |
3d396eb1 | 482 | |
2956640d DP |
483 | buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL); |
484 | if (buf == NULL) { | |
485 | printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n", | |
486 | netxen_nic_driver_name); | |
487 | return -ENOMEM; | |
488 | } | |
0be367bd | 489 | |
2956640d DP |
490 | for (i = 0; i < n; i++) { |
491 | if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 || | |
584dbe94 DM |
492 | netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) { |
493 | kfree(buf); | |
2956640d | 494 | return -EIO; |
584dbe94 | 495 | } |
2956640d DP |
496 | |
497 | buf[i].addr = addr; | |
498 | buf[i].data = val; | |
499 | ||
2956640d | 500 | } |
0be367bd | 501 | |
2956640d DP |
502 | for (i = 0; i < n; i++) { |
503 | ||
504 | off = netxen_decode_crb_addr(buf[i].addr); | |
505 | if (off == NETXEN_ADDR_ERROR) { | |
506 | printk(KERN_ERR"CRB init value out of range %x\n", | |
1fcca1a5 | 507 | buf[i].addr); |
2956640d DP |
508 | continue; |
509 | } | |
510 | off += NETXEN_PCI_CRBSPACE; | |
0be367bd AKS |
511 | |
512 | if (off & 1) | |
513 | continue; | |
514 | ||
2956640d DP |
515 | /* skipping cold reboot MAGIC */ |
516 | if (off == NETXEN_CAM_RAM(0x1fc)) | |
517 | continue; | |
518 | ||
519 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | |
8bee0a91 DP |
520 | if (off == (NETXEN_CRB_I2C0 + 0x1c)) |
521 | continue; | |
2956640d DP |
522 | /* do not reset PCI */ |
523 | if (off == (ROMUSB_GLB + 0xbc)) | |
1fcca1a5 | 524 | continue; |
27c915a4 DP |
525 | if (off == (ROMUSB_GLB + 0xa8)) |
526 | continue; | |
527 | if (off == (ROMUSB_GLB + 0xc8)) /* core clock */ | |
528 | continue; | |
529 | if (off == (ROMUSB_GLB + 0x24)) /* MN clock */ | |
530 | continue; | |
531 | if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */ | |
532 | continue; | |
e7473f12 AKS |
533 | if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET) |
534 | continue; | |
0be367bd AKS |
535 | if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) && |
536 | !NX_IS_REVISION_P3P(adapter->ahw.revision_id)) | |
2956640d DP |
537 | buf[i].data = 0x1020; |
538 | /* skip the function enable register */ | |
539 | if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION)) | |
3d396eb1 | 540 | continue; |
2956640d DP |
541 | if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2)) |
542 | continue; | |
543 | if ((off & 0x0ff00000) == NETXEN_CRB_SMB) | |
544 | continue; | |
545 | } | |
3d396eb1 | 546 | |
27c915a4 | 547 | init_delay = 1; |
2956640d DP |
548 | /* After writing this register, HW needs time for CRB */ |
549 | /* to quiet down (else crb_window returns 0xffffffff) */ | |
550 | if (off == NETXEN_ROMUSB_GLB_SW_RESET) { | |
27c915a4 | 551 | init_delay = 1000; |
2956640d | 552 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
3d396eb1 | 553 | /* hold xdma in reset also */ |
cb8011ad | 554 | buf[i].data = NETXEN_NIC_XDMA_RESET; |
27c915a4 | 555 | buf[i].data = 0x8000ff; |
3d396eb1 | 556 | } |
2956640d | 557 | } |
3d396eb1 | 558 | |
f98a9f69 | 559 | NXWR32(adapter, off, buf[i].data); |
3d396eb1 | 560 | |
27c915a4 | 561 | msleep(init_delay); |
2956640d DP |
562 | } |
563 | kfree(buf); | |
3d396eb1 | 564 | |
2956640d | 565 | /* disable_peg_cache_all */ |
3d396eb1 | 566 | |
2956640d DP |
567 | /* unreset_net_cache */ |
568 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
f98a9f69 DP |
569 | val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET); |
570 | NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f)); | |
3d396eb1 | 571 | } |
2956640d DP |
572 | |
573 | /* p2dn replyCount */ | |
f98a9f69 | 574 | NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e); |
2956640d | 575 | /* disable_peg_cache 0 */ |
f98a9f69 | 576 | NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8); |
2956640d | 577 | /* disable_peg_cache 1 */ |
f98a9f69 | 578 | NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8); |
2956640d DP |
579 | |
580 | /* peg_clr_all */ | |
581 | ||
582 | /* peg_clr 0 */ | |
f98a9f69 DP |
583 | NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0); |
584 | NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0); | |
2956640d | 585 | /* peg_clr 1 */ |
f98a9f69 DP |
586 | NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0); |
587 | NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0); | |
2956640d | 588 | /* peg_clr 2 */ |
f98a9f69 DP |
589 | NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0); |
590 | NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0); | |
2956640d | 591 | /* peg_clr 3 */ |
f98a9f69 DP |
592 | NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0); |
593 | NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0); | |
3d396eb1 AK |
594 | return 0; |
595 | } | |
596 | ||
f50330f9 AKS |
597 | static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section) |
598 | { | |
599 | uint32_t i; | |
600 | struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0]; | |
601 | __le32 entries = cpu_to_le32(directory->num_entries); | |
602 | ||
603 | for (i = 0; i < entries; i++) { | |
604 | ||
605 | __le32 offs = cpu_to_le32(directory->findex) + | |
606 | (i * cpu_to_le32(directory->entry_size)); | |
607 | __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8)); | |
608 | ||
609 | if (tab_type == section) | |
610 | return (struct uni_table_desc *) &unirom[offs]; | |
611 | } | |
612 | ||
613 | return NULL; | |
614 | } | |
615 | ||
616 | static int | |
617 | nx_set_product_offs(struct netxen_adapter *adapter) | |
618 | { | |
619 | struct uni_table_desc *ptab_descr; | |
620 | const u8 *unirom = adapter->fw->data; | |
621 | uint32_t i; | |
622 | __le32 entries; | |
623 | ||
634d7df8 DP |
624 | int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ? |
625 | 1 : netxen_p3_has_mn(adapter); | |
626 | ||
f50330f9 AKS |
627 | ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL); |
628 | if (ptab_descr == NULL) | |
629 | return -1; | |
630 | ||
631 | entries = cpu_to_le32(ptab_descr->num_entries); | |
632 | ||
634d7df8 | 633 | nomn: |
f50330f9 AKS |
634 | for (i = 0; i < entries; i++) { |
635 | ||
636 | __le32 flags, file_chiprev, offs; | |
637 | u8 chiprev = adapter->ahw.revision_id; | |
f50330f9 AKS |
638 | uint32_t flagbit; |
639 | ||
640 | offs = cpu_to_le32(ptab_descr->findex) + | |
641 | (i * cpu_to_le32(ptab_descr->entry_size)); | |
642 | flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF)); | |
643 | file_chiprev = cpu_to_le32(*((int *)&unirom[offs] + | |
644 | NX_UNI_CHIP_REV_OFF)); | |
645 | ||
646 | flagbit = mn_present ? 1 : 2; | |
647 | ||
648 | if ((chiprev == file_chiprev) && | |
649 | ((1ULL << flagbit) & flags)) { | |
650 | adapter->file_prd_off = offs; | |
651 | return 0; | |
652 | } | |
653 | } | |
654 | ||
634d7df8 DP |
655 | if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
656 | mn_present = 0; | |
657 | goto nomn; | |
658 | } | |
659 | ||
f50330f9 AKS |
660 | return -1; |
661 | } | |
662 | ||
663 | ||
664 | static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter, | |
665 | u32 section, u32 idx_offset) | |
666 | { | |
667 | const u8 *unirom = adapter->fw->data; | |
668 | int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] + | |
669 | idx_offset)); | |
670 | struct uni_table_desc *tab_desc; | |
671 | __le32 offs; | |
672 | ||
673 | tab_desc = nx_get_table_desc(unirom, section); | |
674 | ||
675 | if (tab_desc == NULL) | |
676 | return NULL; | |
677 | ||
678 | offs = cpu_to_le32(tab_desc->findex) + | |
679 | (cpu_to_le32(tab_desc->entry_size) * idx); | |
680 | ||
681 | return (struct uni_data_desc *)&unirom[offs]; | |
682 | } | |
683 | ||
684 | static u8 * | |
685 | nx_get_bootld_offs(struct netxen_adapter *adapter) | |
686 | { | |
687 | u32 offs = NETXEN_BOOTLD_START; | |
688 | ||
689 | if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) | |
690 | offs = cpu_to_le32((nx_get_data_desc(adapter, | |
691 | NX_UNI_DIR_SECT_BOOTLD, | |
692 | NX_UNI_BOOTLD_IDX_OFF))->findex); | |
693 | ||
694 | return (u8 *)&adapter->fw->data[offs]; | |
695 | } | |
696 | ||
697 | static u8 * | |
698 | nx_get_fw_offs(struct netxen_adapter *adapter) | |
699 | { | |
700 | u32 offs = NETXEN_IMAGE_START; | |
701 | ||
702 | if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) | |
703 | offs = cpu_to_le32((nx_get_data_desc(adapter, | |
704 | NX_UNI_DIR_SECT_FW, | |
705 | NX_UNI_FIRMWARE_IDX_OFF))->findex); | |
706 | ||
707 | return (u8 *)&adapter->fw->data[offs]; | |
708 | } | |
709 | ||
710 | static __le32 | |
711 | nx_get_fw_size(struct netxen_adapter *adapter) | |
712 | { | |
713 | if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) | |
714 | return cpu_to_le32((nx_get_data_desc(adapter, | |
715 | NX_UNI_DIR_SECT_FW, | |
716 | NX_UNI_FIRMWARE_IDX_OFF))->size); | |
717 | else | |
718 | return cpu_to_le32( | |
719 | *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]); | |
720 | } | |
721 | ||
722 | static __le32 | |
723 | nx_get_fw_version(struct netxen_adapter *adapter) | |
724 | { | |
725 | struct uni_data_desc *fw_data_desc; | |
726 | const struct firmware *fw = adapter->fw; | |
727 | __le32 major, minor, sub; | |
728 | const u8 *ver_str; | |
729 | int i, ret = 0; | |
730 | ||
731 | if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) { | |
732 | ||
733 | fw_data_desc = nx_get_data_desc(adapter, | |
734 | NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF); | |
735 | ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) + | |
736 | cpu_to_le32(fw_data_desc->size) - 17; | |
737 | ||
738 | for (i = 0; i < 12; i++) { | |
739 | if (!strncmp(&ver_str[i], "REV=", 4)) { | |
740 | ret = sscanf(&ver_str[i+4], "%u.%u.%u ", | |
741 | &major, &minor, &sub); | |
742 | break; | |
743 | } | |
744 | } | |
745 | ||
746 | if (ret != 3) | |
747 | return 0; | |
748 | ||
749 | return major + (minor << 8) + (sub << 16); | |
750 | ||
751 | } else | |
752 | return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]); | |
753 | } | |
754 | ||
755 | static __le32 | |
756 | nx_get_bios_version(struct netxen_adapter *adapter) | |
757 | { | |
758 | const struct firmware *fw = adapter->fw; | |
759 | __le32 bios_ver, prd_off = adapter->file_prd_off; | |
760 | ||
761 | if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) { | |
762 | bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off]) | |
763 | + NX_UNI_BIOS_VERSION_OFF)); | |
764 | return (bios_ver << 24) + ((bios_ver >> 8) & 0xff00) + | |
765 | (bios_ver >> 24); | |
766 | } else | |
767 | return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]); | |
768 | ||
769 | } | |
770 | ||
67c38fc6 DP |
771 | int |
772 | netxen_need_fw_reset(struct netxen_adapter *adapter) | |
773 | { | |
774 | u32 count, old_count; | |
775 | u32 val, version, major, minor, build; | |
776 | int i, timeout; | |
777 | u8 fw_type; | |
778 | ||
779 | /* NX2031 firmware doesn't support heartbit */ | |
780 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
781 | return 1; | |
782 | ||
6a808c6c AKS |
783 | if (adapter->need_fw_reset) |
784 | return 1; | |
785 | ||
67c38fc6 DP |
786 | /* last attempt had failed */ |
787 | if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED) | |
788 | return 1; | |
789 | ||
581e8ae4 | 790 | old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER); |
67c38fc6 DP |
791 | |
792 | for (i = 0; i < 10; i++) { | |
793 | ||
794 | timeout = msleep_interruptible(200); | |
795 | if (timeout) { | |
796 | NXWR32(adapter, CRB_CMDPEG_STATE, | |
797 | PHAN_INITIALIZE_FAILED); | |
798 | return -EINTR; | |
799 | } | |
800 | ||
801 | count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER); | |
802 | if (count != old_count) | |
803 | break; | |
804 | } | |
805 | ||
806 | /* firmware is dead */ | |
807 | if (count == old_count) | |
808 | return 1; | |
809 | ||
810 | /* check if we have got newer or different file firmware */ | |
811 | if (adapter->fw) { | |
812 | ||
f50330f9 | 813 | val = nx_get_fw_version(adapter); |
67c38fc6 | 814 | |
67c38fc6 DP |
815 | version = NETXEN_DECODE_VERSION(val); |
816 | ||
817 | major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR); | |
818 | minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR); | |
819 | build = NXRD32(adapter, NETXEN_FW_VERSION_SUB); | |
820 | ||
821 | if (version > NETXEN_VERSION_CODE(major, minor, build)) | |
822 | return 1; | |
823 | ||
f50330f9 AKS |
824 | if (version == NETXEN_VERSION_CODE(major, minor, build) && |
825 | adapter->fw_type != NX_UNIFIED_ROMIMAGE) { | |
67c38fc6 DP |
826 | |
827 | val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL); | |
828 | fw_type = (val & 0x4) ? | |
829 | NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE; | |
830 | ||
831 | if (adapter->fw_type != fw_type) | |
832 | return 1; | |
833 | } | |
834 | } | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
839 | static char *fw_name[] = { | |
7e8e5d97 DP |
840 | NX_P2_MN_ROMIMAGE_NAME, |
841 | NX_P3_CT_ROMIMAGE_NAME, | |
842 | NX_P3_MN_ROMIMAGE_NAME, | |
843 | NX_UNIFIED_ROMIMAGE_NAME, | |
844 | NX_FLASH_ROMIMAGE_NAME, | |
67c38fc6 DP |
845 | }; |
846 | ||
f7185c71 DP |
847 | int |
848 | netxen_load_firmware(struct netxen_adapter *adapter) | |
849 | { | |
850 | u64 *ptr64; | |
851 | u32 i, flashaddr, size; | |
852 | const struct firmware *fw = adapter->fw; | |
67c38fc6 DP |
853 | struct pci_dev *pdev = adapter->pdev; |
854 | ||
855 | dev_info(&pdev->dev, "loading firmware from %s\n", | |
856 | fw_name[adapter->fw_type]); | |
f7185c71 DP |
857 | |
858 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
859 | NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1); | |
860 | ||
861 | if (fw) { | |
862 | __le64 data; | |
863 | ||
864 | size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8; | |
865 | ||
f50330f9 | 866 | ptr64 = (u64 *)nx_get_bootld_offs(adapter); |
f7185c71 DP |
867 | flashaddr = NETXEN_BOOTLD_START; |
868 | ||
869 | for (i = 0; i < size; i++) { | |
870 | data = cpu_to_le64(ptr64[i]); | |
f50330f9 AKS |
871 | |
872 | if (adapter->pci_mem_write(adapter, flashaddr, data)) | |
1f5e055d AKS |
873 | return -EIO; |
874 | ||
f7185c71 DP |
875 | flashaddr += 8; |
876 | } | |
877 | ||
f50330f9 | 878 | size = (__force u32)nx_get_fw_size(adapter) / 8; |
f7185c71 | 879 | |
f50330f9 | 880 | ptr64 = (u64 *)nx_get_fw_offs(adapter); |
f7185c71 DP |
881 | flashaddr = NETXEN_IMAGE_START; |
882 | ||
883 | for (i = 0; i < size; i++) { | |
884 | data = cpu_to_le64(ptr64[i]); | |
885 | ||
886 | if (adapter->pci_mem_write(adapter, | |
1f5e055d | 887 | flashaddr, data)) |
f7185c71 DP |
888 | return -EIO; |
889 | ||
890 | flashaddr += 8; | |
891 | } | |
892 | } else { | |
f78c0850 AKS |
893 | u64 data; |
894 | u32 hi, lo; | |
f7185c71 | 895 | |
f78c0850 | 896 | size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8; |
f7185c71 DP |
897 | flashaddr = NETXEN_BOOTLD_START; |
898 | ||
899 | for (i = 0; i < size; i++) { | |
900 | if (netxen_rom_fast_read(adapter, | |
1f5e055d | 901 | flashaddr, (int *)&lo) != 0) |
f78c0850 AKS |
902 | return -EIO; |
903 | if (netxen_rom_fast_read(adapter, | |
1f5e055d | 904 | flashaddr + 4, (int *)&hi) != 0) |
f7185c71 DP |
905 | return -EIO; |
906 | ||
f78c0850 AKS |
907 | /* hi, lo are already in host endian byteorder */ |
908 | data = (((u64)hi << 32) | lo); | |
909 | ||
f7185c71 | 910 | if (adapter->pci_mem_write(adapter, |
1f5e055d | 911 | flashaddr, data)) |
f7185c71 DP |
912 | return -EIO; |
913 | ||
f78c0850 | 914 | flashaddr += 8; |
f7185c71 DP |
915 | } |
916 | } | |
917 | msleep(1); | |
918 | ||
0be367bd AKS |
919 | if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) { |
920 | NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020); | |
921 | NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e); | |
922 | } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | |
f7185c71 DP |
923 | NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d); |
924 | else { | |
925 | NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff); | |
926 | NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0); | |
927 | } | |
928 | ||
929 | return 0; | |
930 | } | |
931 | ||
932 | static int | |
f50330f9 | 933 | netxen_validate_firmware(struct netxen_adapter *adapter) |
f7185c71 DP |
934 | { |
935 | __le32 val; | |
f50330f9 | 936 | u32 ver, min_ver, bios, min_size; |
f7185c71 DP |
937 | struct pci_dev *pdev = adapter->pdev; |
938 | const struct firmware *fw = adapter->fw; | |
f50330f9 | 939 | u8 fw_type = adapter->fw_type; |
f7185c71 | 940 | |
f50330f9 AKS |
941 | if (fw_type == NX_UNIFIED_ROMIMAGE) { |
942 | if (nx_set_product_offs(adapter)) | |
943 | return -EINVAL; | |
944 | ||
945 | min_size = NX_UNI_FW_MIN_SIZE; | |
946 | } else { | |
947 | val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]); | |
948 | if ((__force u32)val != NETXEN_BDINFO_MAGIC) | |
949 | return -EINVAL; | |
f7185c71 | 950 | |
f50330f9 AKS |
951 | min_size = NX_FW_MIN_SIZE; |
952 | } | |
953 | ||
954 | if (fw->size < min_size) | |
f7185c71 DP |
955 | return -EINVAL; |
956 | ||
f50330f9 | 957 | val = nx_get_fw_version(adapter); |
f7185c71 DP |
958 | |
959 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) | |
960 | min_ver = NETXEN_VERSION_CODE(4, 0, 216); | |
961 | else | |
962 | min_ver = NETXEN_VERSION_CODE(3, 4, 216); | |
963 | ||
98e31bb0 | 964 | ver = NETXEN_DECODE_VERSION(val); |
f7185c71 | 965 | |
98e31bb0 | 966 | if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) { |
f7185c71 DP |
967 | dev_err(&pdev->dev, |
968 | "%s: firmware version %d.%d.%d unsupported\n", | |
f50330f9 | 969 | fw_name[fw_type], _major(ver), _minor(ver), _build(ver)); |
f7185c71 DP |
970 | return -EINVAL; |
971 | } | |
972 | ||
f50330f9 | 973 | val = nx_get_bios_version(adapter); |
f7185c71 DP |
974 | netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios); |
975 | if ((__force u32)val != bios) { | |
976 | dev_err(&pdev->dev, "%s: firmware bios is incompatible\n", | |
f50330f9 | 977 | fw_name[fw_type]); |
f7185c71 DP |
978 | return -EINVAL; |
979 | } | |
980 | ||
981 | /* check if flashed firmware is newer */ | |
982 | if (netxen_rom_fast_read(adapter, | |
983 | NX_FW_VERSION_OFFSET, (int *)&val)) | |
984 | return -EIO; | |
98e31bb0 DP |
985 | val = NETXEN_DECODE_VERSION(val); |
986 | if (val > ver) { | |
987 | dev_info(&pdev->dev, "%s: firmware is older than flash\n", | |
f50330f9 | 988 | fw_name[fw_type]); |
f7185c71 | 989 | return -EINVAL; |
98e31bb0 | 990 | } |
f7185c71 DP |
991 | |
992 | NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC); | |
993 | return 0; | |
994 | } | |
995 | ||
f50330f9 AKS |
996 | static void |
997 | nx_get_next_fwtype(struct netxen_adapter *adapter) | |
998 | { | |
999 | u8 fw_type; | |
1000 | ||
1001 | switch (adapter->fw_type) { | |
1002 | case NX_UNKNOWN_ROMIMAGE: | |
1003 | fw_type = NX_UNIFIED_ROMIMAGE; | |
1004 | break; | |
1005 | ||
1006 | case NX_UNIFIED_ROMIMAGE: | |
1007 | if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) | |
1008 | fw_type = NX_FLASH_ROMIMAGE; | |
1009 | else if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
1010 | fw_type = NX_P2_MN_ROMIMAGE; | |
1011 | else if (netxen_p3_has_mn(adapter)) | |
1012 | fw_type = NX_P3_MN_ROMIMAGE; | |
1013 | else | |
1014 | fw_type = NX_P3_CT_ROMIMAGE; | |
1015 | break; | |
1016 | ||
1017 | case NX_P3_MN_ROMIMAGE: | |
1018 | fw_type = NX_P3_CT_ROMIMAGE; | |
1019 | break; | |
1020 | ||
1021 | case NX_P2_MN_ROMIMAGE: | |
1022 | case NX_P3_CT_ROMIMAGE: | |
1023 | default: | |
1024 | fw_type = NX_FLASH_ROMIMAGE; | |
1025 | break; | |
1026 | } | |
1027 | ||
1028 | adapter->fw_type = fw_type; | |
1029 | } | |
1030 | ||
6598b169 DP |
1031 | static int |
1032 | netxen_p3_has_mn(struct netxen_adapter *adapter) | |
f7185c71 DP |
1033 | { |
1034 | u32 capability, flashed_ver; | |
f7185c71 DP |
1035 | capability = 0; |
1036 | ||
634d7df8 DP |
1037 | /* NX2031 always had MN */ |
1038 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
1039 | return 1; | |
1040 | ||
f7185c71 DP |
1041 | netxen_rom_fast_read(adapter, |
1042 | NX_FW_VERSION_OFFSET, (int *)&flashed_ver); | |
98e31bb0 DP |
1043 | flashed_ver = NETXEN_DECODE_VERSION(flashed_ver); |
1044 | ||
f7185c71 | 1045 | if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) { |
6598b169 | 1046 | |
f7185c71 | 1047 | capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY); |
6598b169 DP |
1048 | if (capability & NX_PEG_TUNE_MN_PRESENT) |
1049 | return 1; | |
1050 | } | |
1051 | return 0; | |
1052 | } | |
1053 | ||
1054 | void netxen_request_firmware(struct netxen_adapter *adapter) | |
1055 | { | |
6598b169 DP |
1056 | struct pci_dev *pdev = adapter->pdev; |
1057 | int rc = 0; | |
1058 | ||
f50330f9 | 1059 | adapter->fw_type = NX_UNKNOWN_ROMIMAGE; |
f7185c71 | 1060 | |
f50330f9 AKS |
1061 | next: |
1062 | nx_get_next_fwtype(adapter); | |
f7185c71 | 1063 | |
f50330f9 | 1064 | if (adapter->fw_type == NX_FLASH_ROMIMAGE) { |
f7185c71 | 1065 | adapter->fw = NULL; |
f50330f9 AKS |
1066 | } else { |
1067 | rc = request_firmware(&adapter->fw, | |
1068 | fw_name[adapter->fw_type], &pdev->dev); | |
1069 | if (rc != 0) | |
1070 | goto next; | |
1071 | ||
1072 | rc = netxen_validate_firmware(adapter); | |
1073 | if (rc != 0) { | |
1074 | release_firmware(adapter->fw); | |
f7185c71 | 1075 | msleep(1); |
f50330f9 | 1076 | goto next; |
f7185c71 | 1077 | } |
f7185c71 | 1078 | } |
f7185c71 DP |
1079 | } |
1080 | ||
1081 | ||
1082 | void | |
1083 | netxen_release_firmware(struct netxen_adapter *adapter) | |
1084 | { | |
1085 | if (adapter->fw) | |
1086 | release_firmware(adapter->fw); | |
db4cfd8a | 1087 | adapter->fw = NULL; |
f7185c71 DP |
1088 | } |
1089 | ||
83ac51fa | 1090 | int netxen_init_dummy_dma(struct netxen_adapter *adapter) |
ed25ffa1 | 1091 | { |
83ac51fa DP |
1092 | u64 addr; |
1093 | u32 hi, lo; | |
ed25ffa1 | 1094 | |
83ac51fa DP |
1095 | if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) |
1096 | return 0; | |
1097 | ||
1098 | adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev, | |
ed25ffa1 AK |
1099 | NETXEN_HOST_DUMMY_DMA_SIZE, |
1100 | &adapter->dummy_dma.phys_addr); | |
1101 | if (adapter->dummy_dma.addr == NULL) { | |
83ac51fa DP |
1102 | dev_err(&adapter->pdev->dev, |
1103 | "ERROR: Could not allocate dummy DMA memory\n"); | |
ed25ffa1 AK |
1104 | return -ENOMEM; |
1105 | } | |
1106 | ||
1107 | addr = (uint64_t) adapter->dummy_dma.phys_addr; | |
1108 | hi = (addr >> 32) & 0xffffffff; | |
1109 | lo = addr & 0xffffffff; | |
1110 | ||
f98a9f69 DP |
1111 | NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi); |
1112 | NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo); | |
ed25ffa1 AK |
1113 | |
1114 | return 0; | |
1115 | } | |
1116 | ||
83ac51fa DP |
1117 | /* |
1118 | * NetXen DMA watchdog control: | |
1119 | * | |
1120 | * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive | |
1121 | * Bit 1 : disable_request => 1 req disable dma watchdog | |
1122 | * Bit 2 : enable_request => 1 req enable dma watchdog | |
1123 | * Bit 3-31 : unused | |
1124 | */ | |
1125 | void netxen_free_dummy_dma(struct netxen_adapter *adapter) | |
ed25ffa1 | 1126 | { |
15eef1e1 | 1127 | int i = 100; |
83ac51fa DP |
1128 | u32 ctrl; |
1129 | ||
1130 | if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) | |
1131 | return; | |
15eef1e1 DP |
1132 | |
1133 | if (!adapter->dummy_dma.addr) | |
1134 | return; | |
439b454e | 1135 | |
83ac51fa DP |
1136 | ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL); |
1137 | if ((ctrl & 0x1) != 0) { | |
1138 | NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2)); | |
1139 | ||
1140 | while ((ctrl & 0x1) != 0) { | |
1141 | ||
439b454e | 1142 | msleep(50); |
83ac51fa DP |
1143 | |
1144 | ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL); | |
1145 | ||
1146 | if (--i == 0) | |
439b454e | 1147 | break; |
83ac51fa | 1148 | }; |
15eef1e1 | 1149 | } |
439b454e | 1150 | |
15eef1e1 DP |
1151 | if (i) { |
1152 | pci_free_consistent(adapter->pdev, | |
1153 | NETXEN_HOST_DUMMY_DMA_SIZE, | |
1154 | adapter->dummy_dma.addr, | |
1155 | adapter->dummy_dma.phys_addr); | |
1156 | adapter->dummy_dma.addr = NULL; | |
83ac51fa DP |
1157 | } else |
1158 | dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n"); | |
ed25ffa1 AK |
1159 | } |
1160 | ||
96acb6eb | 1161 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val) |
3d396eb1 AK |
1162 | { |
1163 | u32 val = 0; | |
2956640d | 1164 | int retries = 60; |
3d396eb1 | 1165 | |
96f2ebd2 DP |
1166 | if (pegtune_val) |
1167 | return 0; | |
1168 | ||
1169 | do { | |
1170 | val = NXRD32(adapter, CRB_CMDPEG_STATE); | |
96acb6eb | 1171 | |
96f2ebd2 DP |
1172 | switch (val) { |
1173 | case PHAN_INITIALIZE_COMPLETE: | |
1174 | case PHAN_INITIALIZE_ACK: | |
1175 | return 0; | |
1176 | case PHAN_INITIALIZE_FAILED: | |
1177 | goto out_err; | |
1178 | default: | |
1179 | break; | |
1180 | } | |
96acb6eb | 1181 | |
96f2ebd2 | 1182 | msleep(500); |
2956640d | 1183 | |
96f2ebd2 | 1184 | } while (--retries); |
2956640d | 1185 | |
96f2ebd2 | 1186 | NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); |
96acb6eb | 1187 | |
96f2ebd2 DP |
1188 | out_err: |
1189 | dev_warn(&adapter->pdev->dev, "firmware init failed\n"); | |
1190 | return -EIO; | |
3d396eb1 AK |
1191 | } |
1192 | ||
56a00787 DP |
1193 | static int |
1194 | netxen_receive_peg_ready(struct netxen_adapter *adapter) | |
2956640d DP |
1195 | { |
1196 | u32 val = 0; | |
1197 | int retries = 2000; | |
1198 | ||
1199 | do { | |
f98a9f69 | 1200 | val = NXRD32(adapter, CRB_RCVPEG_STATE); |
2956640d DP |
1201 | |
1202 | if (val == PHAN_PEG_RCV_INITIALIZED) | |
1203 | return 0; | |
1204 | ||
1205 | msleep(10); | |
1206 | ||
1207 | } while (--retries); | |
1208 | ||
1209 | if (!retries) { | |
1210 | printk(KERN_ERR "Receive Peg initialization not " | |
1211 | "complete, state: 0x%x.\n", val); | |
1212 | return -EIO; | |
1213 | } | |
1214 | ||
1215 | return 0; | |
1216 | } | |
1217 | ||
56a00787 DP |
1218 | int netxen_init_firmware(struct netxen_adapter *adapter) |
1219 | { | |
1220 | int err; | |
1221 | ||
1222 | err = netxen_receive_peg_ready(adapter); | |
1223 | if (err) | |
1224 | return err; | |
1225 | ||
f98a9f69 DP |
1226 | NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT); |
1227 | NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC); | |
1228 | NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE); | |
1229 | NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK); | |
56a00787 DP |
1230 | |
1231 | return err; | |
1232 | } | |
1233 | ||
3bf26ce3 DP |
1234 | static void |
1235 | netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg) | |
1236 | { | |
1237 | u32 cable_OUI; | |
1238 | u16 cable_len; | |
1239 | u16 link_speed; | |
1240 | u8 link_status, module, duplex, autoneg; | |
1241 | struct net_device *netdev = adapter->netdev; | |
1242 | ||
1243 | adapter->has_link_events = 1; | |
1244 | ||
1245 | cable_OUI = msg->body[1] & 0xffffffff; | |
1246 | cable_len = (msg->body[1] >> 32) & 0xffff; | |
1247 | link_speed = (msg->body[1] >> 48) & 0xffff; | |
1248 | ||
1249 | link_status = msg->body[2] & 0xff; | |
1250 | duplex = (msg->body[2] >> 16) & 0xff; | |
1251 | autoneg = (msg->body[2] >> 24) & 0xff; | |
1252 | ||
1253 | module = (msg->body[2] >> 8) & 0xff; | |
1254 | if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) { | |
1255 | printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n", | |
1256 | netdev->name, cable_OUI, cable_len); | |
1257 | } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) { | |
1258 | printk(KERN_INFO "%s: unsupported cable length %d\n", | |
1259 | netdev->name, cable_len); | |
1260 | } | |
1261 | ||
1262 | netxen_advert_link_change(adapter, link_status); | |
1263 | ||
1264 | /* update link parameters */ | |
1265 | if (duplex == LINKEVENT_FULL_DUPLEX) | |
1266 | adapter->link_duplex = DUPLEX_FULL; | |
1267 | else | |
1268 | adapter->link_duplex = DUPLEX_HALF; | |
1269 | adapter->module_type = module; | |
1270 | adapter->link_autoneg = autoneg; | |
1271 | adapter->link_speed = link_speed; | |
1272 | } | |
1273 | ||
1274 | static void | |
1275 | netxen_handle_fw_message(int desc_cnt, int index, | |
1276 | struct nx_host_sds_ring *sds_ring) | |
1277 | { | |
1278 | nx_fw_msg_t msg; | |
1279 | struct status_desc *desc; | |
1280 | int i = 0, opcode; | |
1281 | ||
1282 | while (desc_cnt > 0 && i < 8) { | |
1283 | desc = &sds_ring->desc_head[index]; | |
1284 | msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]); | |
1285 | msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]); | |
1286 | ||
1287 | index = get_next_index(index, sds_ring->num_desc); | |
1288 | desc_cnt--; | |
1289 | } | |
1290 | ||
1291 | opcode = netxen_get_nic_msg_opcode(msg.body[0]); | |
1292 | switch (opcode) { | |
1293 | case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE: | |
1294 | netxen_handle_linkevent(sds_ring->adapter, &msg); | |
1295 | break; | |
1296 | default: | |
1297 | break; | |
1298 | } | |
1299 | } | |
1300 | ||
d8b100c5 DP |
1301 | static int |
1302 | netxen_alloc_rx_skb(struct netxen_adapter *adapter, | |
1303 | struct nx_host_rds_ring *rds_ring, | |
1304 | struct netxen_rx_buffer *buffer) | |
1305 | { | |
1306 | struct sk_buff *skb; | |
1307 | dma_addr_t dma; | |
1308 | struct pci_dev *pdev = adapter->pdev; | |
1309 | ||
1310 | buffer->skb = dev_alloc_skb(rds_ring->skb_size); | |
1311 | if (!buffer->skb) | |
1312 | return 1; | |
1313 | ||
1314 | skb = buffer->skb; | |
1315 | ||
1316 | if (!adapter->ahw.cut_through) | |
1317 | skb_reserve(skb, 2); | |
1318 | ||
1319 | dma = pci_map_single(pdev, skb->data, | |
1320 | rds_ring->dma_size, PCI_DMA_FROMDEVICE); | |
1321 | ||
1322 | if (pci_dma_mapping_error(pdev, dma)) { | |
1323 | dev_kfree_skb_any(skb); | |
1324 | buffer->skb = NULL; | |
1325 | return 1; | |
1326 | } | |
1327 | ||
1328 | buffer->skb = skb; | |
1329 | buffer->dma = dma; | |
1330 | buffer->state = NETXEN_BUFFER_BUSY; | |
1331 | ||
1332 | return 0; | |
1333 | } | |
1334 | ||
d9e651bc DP |
1335 | static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter, |
1336 | struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum) | |
1337 | { | |
1338 | struct netxen_rx_buffer *buffer; | |
1339 | struct sk_buff *skb; | |
1340 | ||
1341 | buffer = &rds_ring->rx_buf_arr[index]; | |
1342 | ||
1343 | pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size, | |
1344 | PCI_DMA_FROMDEVICE); | |
1345 | ||
1346 | skb = buffer->skb; | |
1347 | if (!skb) | |
1348 | goto no_skb; | |
1349 | ||
1350 | if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) { | |
1351 | adapter->stats.csummed++; | |
1352 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1353 | } else | |
1354 | skb->ip_summed = CHECKSUM_NONE; | |
1355 | ||
1356 | skb->dev = adapter->netdev; | |
1357 | ||
1358 | buffer->skb = NULL; | |
d9e651bc DP |
1359 | no_skb: |
1360 | buffer->state = NETXEN_BUFFER_FREE; | |
d9e651bc DP |
1361 | return skb; |
1362 | } | |
1363 | ||
d8b100c5 | 1364 | static struct netxen_rx_buffer * |
9b3ef55c | 1365 | netxen_process_rcv(struct netxen_adapter *adapter, |
c1c00ab8 DP |
1366 | struct nx_host_sds_ring *sds_ring, |
1367 | int ring, u64 sts_data0) | |
3d396eb1 | 1368 | { |
3176ff3e | 1369 | struct net_device *netdev = adapter->netdev; |
becf46a0 | 1370 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; |
3d396eb1 AK |
1371 | struct netxen_rx_buffer *buffer; |
1372 | struct sk_buff *skb; | |
c1c00ab8 DP |
1373 | struct nx_host_rds_ring *rds_ring; |
1374 | int index, length, cksum, pkt_offset; | |
3d396eb1 | 1375 | |
c1c00ab8 DP |
1376 | if (unlikely(ring >= adapter->max_rds_rings)) |
1377 | return NULL; | |
1378 | ||
1379 | rds_ring = &recv_ctx->rds_rings[ring]; | |
1380 | ||
1381 | index = netxen_get_sts_refhandle(sts_data0); | |
1382 | if (unlikely(index >= rds_ring->num_desc)) | |
d8b100c5 | 1383 | return NULL; |
438627c7 | 1384 | |
48bfd1e0 | 1385 | buffer = &rds_ring->rx_buf_arr[index]; |
3d396eb1 | 1386 | |
c1c00ab8 DP |
1387 | length = netxen_get_sts_totallength(sts_data0); |
1388 | cksum = netxen_get_sts_status(sts_data0); | |
1389 | pkt_offset = netxen_get_sts_pkt_offset(sts_data0); | |
1390 | ||
d9e651bc DP |
1391 | skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum); |
1392 | if (!skb) | |
d8b100c5 | 1393 | return buffer; |
200eef20 | 1394 | |
9b3ef55c DP |
1395 | if (length > rds_ring->skb_size) |
1396 | skb_put(skb, rds_ring->skb_size); | |
1397 | else | |
1398 | skb_put(skb, length); | |
d9e651bc | 1399 | |
9b3ef55c DP |
1400 | |
1401 | if (pkt_offset) | |
1402 | skb_pull(skb, pkt_offset); | |
ed25ffa1 | 1403 | |
bc75e5bf | 1404 | skb->truesize = skb->len + sizeof(struct sk_buff); |
3d396eb1 AK |
1405 | skb->protocol = eth_type_trans(skb, netdev); |
1406 | ||
a92e9e65 | 1407 | napi_gro_receive(&sds_ring->napi, skb); |
d9e651bc | 1408 | |
1bb482f8 | 1409 | adapter->stats.rx_pkts++; |
0ddc110c | 1410 | adapter->stats.rxbytes += length; |
d8b100c5 DP |
1411 | |
1412 | return buffer; | |
3d396eb1 AK |
1413 | } |
1414 | ||
c1c00ab8 DP |
1415 | #define TCP_HDR_SIZE 20 |
1416 | #define TCP_TS_OPTION_SIZE 12 | |
1417 | #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE) | |
1418 | ||
1419 | static struct netxen_rx_buffer * | |
1420 | netxen_process_lro(struct netxen_adapter *adapter, | |
1421 | struct nx_host_sds_ring *sds_ring, | |
1422 | int ring, u64 sts_data0, u64 sts_data1) | |
1423 | { | |
1424 | struct net_device *netdev = adapter->netdev; | |
1425 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; | |
1426 | struct netxen_rx_buffer *buffer; | |
1427 | struct sk_buff *skb; | |
1428 | struct nx_host_rds_ring *rds_ring; | |
1429 | struct iphdr *iph; | |
1430 | struct tcphdr *th; | |
1431 | bool push, timestamp; | |
1432 | int l2_hdr_offset, l4_hdr_offset; | |
1433 | int index; | |
1434 | u16 lro_length, length, data_offset; | |
1435 | u32 seq_number; | |
1436 | ||
1437 | if (unlikely(ring > adapter->max_rds_rings)) | |
1438 | return NULL; | |
1439 | ||
1440 | rds_ring = &recv_ctx->rds_rings[ring]; | |
1441 | ||
1442 | index = netxen_get_lro_sts_refhandle(sts_data0); | |
1443 | if (unlikely(index > rds_ring->num_desc)) | |
1444 | return NULL; | |
1445 | ||
1446 | buffer = &rds_ring->rx_buf_arr[index]; | |
1447 | ||
1448 | timestamp = netxen_get_lro_sts_timestamp(sts_data0); | |
1449 | lro_length = netxen_get_lro_sts_length(sts_data0); | |
1450 | l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0); | |
1451 | l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0); | |
1452 | push = netxen_get_lro_sts_push_flag(sts_data0); | |
1453 | seq_number = netxen_get_lro_sts_seq_number(sts_data1); | |
1454 | ||
1455 | skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK); | |
1456 | if (!skb) | |
1457 | return buffer; | |
1458 | ||
1459 | if (timestamp) | |
1460 | data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE; | |
1461 | else | |
1462 | data_offset = l4_hdr_offset + TCP_HDR_SIZE; | |
1463 | ||
1464 | skb_put(skb, lro_length + data_offset); | |
1465 | ||
bc75e5bf | 1466 | skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb); |
c1c00ab8 DP |
1467 | |
1468 | skb_pull(skb, l2_hdr_offset); | |
1469 | skb->protocol = eth_type_trans(skb, netdev); | |
1470 | ||
1471 | iph = (struct iphdr *)skb->data; | |
1472 | th = (struct tcphdr *)(skb->data + (iph->ihl << 2)); | |
1473 | ||
1474 | length = (iph->ihl << 2) + (th->doff << 2) + lro_length; | |
1475 | iph->tot_len = htons(length); | |
1476 | iph->check = 0; | |
1477 | iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); | |
1478 | th->psh = push; | |
1479 | th->seq = htonl(seq_number); | |
1480 | ||
1bb482f8 NK |
1481 | length = skb->len; |
1482 | ||
c1c00ab8 DP |
1483 | netif_receive_skb(skb); |
1484 | ||
1bb482f8 NK |
1485 | adapter->stats.lro_pkts++; |
1486 | adapter->stats.rxbytes += length; | |
1487 | ||
c1c00ab8 DP |
1488 | return buffer; |
1489 | } | |
1490 | ||
d8b100c5 DP |
1491 | #define netxen_merge_rx_buffers(list, head) \ |
1492 | do { list_splice_tail_init(list, head); } while (0); | |
1493 | ||
becf46a0 | 1494 | int |
d8b100c5 | 1495 | netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max) |
3d396eb1 | 1496 | { |
d8b100c5 DP |
1497 | struct netxen_adapter *adapter = sds_ring->adapter; |
1498 | ||
1499 | struct list_head *cur; | |
1500 | ||
0ddc110c | 1501 | struct status_desc *desc; |
d8b100c5 DP |
1502 | struct netxen_rx_buffer *rxbuf; |
1503 | ||
1504 | u32 consumer = sds_ring->consumer; | |
1505 | ||
9b3ef55c | 1506 | int count = 0; |
c1c00ab8 DP |
1507 | u64 sts_data0, sts_data1; |
1508 | int opcode, ring = 0, desc_cnt; | |
3d396eb1 | 1509 | |
3d396eb1 | 1510 | while (count < max) { |
d8b100c5 | 1511 | desc = &sds_ring->desc_head[consumer]; |
c1c00ab8 | 1512 | sts_data0 = le64_to_cpu(desc->status_desc_data[0]); |
0ddc110c | 1513 | |
c1c00ab8 | 1514 | if (!(sts_data0 & STATUS_OWNER_HOST)) |
3d396eb1 | 1515 | break; |
d9e651bc | 1516 | |
c1c00ab8 | 1517 | desc_cnt = netxen_get_sts_desc_cnt(sts_data0); |
3bf26ce3 | 1518 | |
c1c00ab8 | 1519 | opcode = netxen_get_sts_opcode(sts_data0); |
d9e651bc | 1520 | |
3bf26ce3 DP |
1521 | switch (opcode) { |
1522 | case NETXEN_NIC_RXPKT_DESC: | |
1523 | case NETXEN_OLD_RXPKT_DESC: | |
6598b169 | 1524 | case NETXEN_NIC_SYN_OFFLOAD: |
c1c00ab8 DP |
1525 | ring = netxen_get_sts_type(sts_data0); |
1526 | rxbuf = netxen_process_rcv(adapter, sds_ring, | |
1527 | ring, sts_data0); | |
1528 | break; | |
1529 | case NETXEN_NIC_LRO_DESC: | |
1530 | ring = netxen_get_lro_sts_type(sts_data0); | |
1531 | sts_data1 = le64_to_cpu(desc->status_desc_data[1]); | |
1532 | rxbuf = netxen_process_lro(adapter, sds_ring, | |
1533 | ring, sts_data0, sts_data1); | |
3bf26ce3 DP |
1534 | break; |
1535 | case NETXEN_NIC_RESPONSE_DESC: | |
1536 | netxen_handle_fw_message(desc_cnt, consumer, sds_ring); | |
1537 | default: | |
1538 | goto skip; | |
1539 | } | |
1540 | ||
1541 | WARN_ON(desc_cnt > 1); | |
1542 | ||
d8b100c5 DP |
1543 | if (rxbuf) |
1544 | list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]); | |
1545 | ||
3bf26ce3 DP |
1546 | skip: |
1547 | for (; desc_cnt > 0; desc_cnt--) { | |
1548 | desc = &sds_ring->desc_head[consumer]; | |
1549 | desc->status_desc_data[0] = | |
1550 | cpu_to_le64(STATUS_OWNER_PHANTOM); | |
1551 | consumer = get_next_index(consumer, sds_ring->num_desc); | |
1552 | } | |
3d396eb1 AK |
1553 | count++; |
1554 | } | |
0ddc110c | 1555 | |
d8b100c5 DP |
1556 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
1557 | struct nx_host_rds_ring *rds_ring = | |
1558 | &adapter->recv_ctx.rds_rings[ring]; | |
1559 | ||
1560 | if (!list_empty(&sds_ring->free_list[ring])) { | |
1561 | list_for_each(cur, &sds_ring->free_list[ring]) { | |
1562 | rxbuf = list_entry(cur, | |
1563 | struct netxen_rx_buffer, list); | |
1564 | netxen_alloc_rx_skb(adapter, rds_ring, rxbuf); | |
1565 | } | |
1566 | spin_lock(&rds_ring->lock); | |
1567 | netxen_merge_rx_buffers(&sds_ring->free_list[ring], | |
1568 | &rds_ring->free_list); | |
1569 | spin_unlock(&rds_ring->lock); | |
1570 | } | |
1571 | ||
1572 | netxen_post_rx_buffers_nodb(adapter, rds_ring); | |
1573 | } | |
3d396eb1 | 1574 | |
3d396eb1 | 1575 | if (count) { |
d8b100c5 | 1576 | sds_ring->consumer = consumer; |
195c5f98 | 1577 | NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer); |
3d396eb1 AK |
1578 | } |
1579 | ||
1580 | return count; | |
1581 | } | |
1582 | ||
1583 | /* Process Command status ring */ | |
05aaa02d | 1584 | int netxen_process_cmd_ring(struct netxen_adapter *adapter) |
3d396eb1 | 1585 | { |
d877f1e3 | 1586 | u32 sw_consumer, hw_consumer; |
ba53e6b4 | 1587 | int count = 0, i; |
3d396eb1 | 1588 | struct netxen_cmd_buffer *buffer; |
ba53e6b4 DP |
1589 | struct pci_dev *pdev = adapter->pdev; |
1590 | struct net_device *netdev = adapter->netdev; | |
3d396eb1 | 1591 | struct netxen_skb_frag *frag; |
ba53e6b4 | 1592 | int done = 0; |
4ea528a1 | 1593 | struct nx_host_tx_ring *tx_ring = adapter->tx_ring; |
3d396eb1 | 1594 | |
d8b100c5 DP |
1595 | if (!spin_trylock(&adapter->tx_clean_lock)) |
1596 | return 1; | |
1597 | ||
d877f1e3 | 1598 | sw_consumer = tx_ring->sw_consumer; |
d877f1e3 | 1599 | hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer)); |
3d396eb1 | 1600 | |
d877f1e3 DP |
1601 | while (sw_consumer != hw_consumer) { |
1602 | buffer = &tx_ring->cmd_buf_arr[sw_consumer]; | |
53a01e00 | 1603 | if (buffer->skb) { |
1604 | frag = &buffer->frag_array[0]; | |
3d396eb1 AK |
1605 | pci_unmap_single(pdev, frag->dma, frag->length, |
1606 | PCI_DMA_TODEVICE); | |
96acb6eb | 1607 | frag->dma = 0ULL; |
3d396eb1 | 1608 | for (i = 1; i < buffer->frag_count; i++) { |
3d396eb1 AK |
1609 | frag++; /* Get the next frag */ |
1610 | pci_unmap_page(pdev, frag->dma, frag->length, | |
1611 | PCI_DMA_TODEVICE); | |
96acb6eb | 1612 | frag->dma = 0ULL; |
3d396eb1 AK |
1613 | } |
1614 | ||
ba53e6b4 | 1615 | adapter->stats.xmitfinished++; |
53a01e00 | 1616 | dev_kfree_skb_any(buffer->skb); |
1617 | buffer->skb = NULL; | |
3d396eb1 AK |
1618 | } |
1619 | ||
d877f1e3 | 1620 | sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc); |
ba53e6b4 DP |
1621 | if (++count >= MAX_STATUS_HANDLE) |
1622 | break; | |
3d396eb1 | 1623 | } |
3d396eb1 | 1624 | |
22527864 | 1625 | if (count && netif_running(netdev)) { |
cb2107be DP |
1626 | tx_ring->sw_consumer = sw_consumer; |
1627 | ||
ba53e6b4 | 1628 | smp_mb(); |
cb2107be | 1629 | |
22527864 | 1630 | if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) { |
b2af9cb0 | 1631 | __netif_tx_lock(tx_ring->txq, smp_processor_id()); |
74c520da | 1632 | if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH) { |
cb2107be | 1633 | netif_wake_queue(netdev); |
74c520da AKS |
1634 | adapter->tx_timeo_cnt = 0; |
1635 | } | |
b2af9cb0 | 1636 | __netif_tx_unlock(tx_ring->txq); |
3d396eb1 AK |
1637 | } |
1638 | } | |
ed25ffa1 AK |
1639 | /* |
1640 | * If everything is freed up to consumer then check if the ring is full | |
1641 | * If the ring is full then check if more needs to be freed and | |
1642 | * schedule the call back again. | |
1643 | * | |
1644 | * This happens when there are 2 CPUs. One could be freeing and the | |
1645 | * other filling it. If the ring is full when we get out of here and | |
1646 | * the card has already interrupted the host then the host can miss the | |
1647 | * interrupt. | |
1648 | * | |
1649 | * There is still a possible race condition and the host could miss an | |
1650 | * interrupt. The card has to take care of this. | |
1651 | */ | |
d877f1e3 DP |
1652 | hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer)); |
1653 | done = (sw_consumer == hw_consumer); | |
d8b100c5 | 1654 | spin_unlock(&adapter->tx_clean_lock); |
3d396eb1 | 1655 | |
ed25ffa1 | 1656 | return (done); |
3d396eb1 AK |
1657 | } |
1658 | ||
becf46a0 | 1659 | void |
d8b100c5 DP |
1660 | netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid, |
1661 | struct nx_host_rds_ring *rds_ring) | |
3d396eb1 | 1662 | { |
3d396eb1 AK |
1663 | struct rcv_desc *pdesc; |
1664 | struct netxen_rx_buffer *buffer; | |
d8b100c5 | 1665 | int producer, count = 0; |
ed25ffa1 | 1666 | netxen_ctx_msg msg = 0; |
d9e651bc | 1667 | struct list_head *head; |
3d396eb1 | 1668 | |
48bfd1e0 | 1669 | producer = rds_ring->producer; |
d9e651bc | 1670 | |
d8b100c5 DP |
1671 | spin_lock(&rds_ring->lock); |
1672 | head = &rds_ring->free_list; | |
d9e651bc DP |
1673 | while (!list_empty(head)) { |
1674 | ||
d8b100c5 | 1675 | buffer = list_entry(head->next, struct netxen_rx_buffer, list); |
6f703406 | 1676 | |
d8b100c5 DP |
1677 | if (!buffer->skb) { |
1678 | if (netxen_alloc_rx_skb(adapter, rds_ring, buffer)) | |
1679 | break; | |
6f703406 DP |
1680 | } |
1681 | ||
1682 | count++; | |
d9e651bc DP |
1683 | list_del(&buffer->list); |
1684 | ||
ed25ffa1 | 1685 | /* make a rcv descriptor */ |
6f703406 | 1686 | pdesc = &rds_ring->desc_head[producer]; |
d8b100c5 | 1687 | pdesc->addr_buffer = cpu_to_le64(buffer->dma); |
ed33ebe4 | 1688 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
48bfd1e0 | 1689 | pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); |
6f703406 | 1690 | |
438627c7 | 1691 | producer = get_next_index(producer, rds_ring->num_desc); |
ed25ffa1 | 1692 | } |
d8b100c5 | 1693 | spin_unlock(&rds_ring->lock); |
9b3ef55c | 1694 | |
ed25ffa1 | 1695 | if (count) { |
48bfd1e0 | 1696 | rds_ring->producer = producer; |
195c5f98 | 1697 | NXWRIO(adapter, rds_ring->crb_rcv_producer, |
438627c7 | 1698 | (producer-1) & (rds_ring->num_desc-1)); |
48bfd1e0 | 1699 | |
4f96b988 | 1700 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
ed25ffa1 AK |
1701 | /* |
1702 | * Write a doorbell msg to tell phanmon of change in | |
1703 | * receive ring producer | |
48bfd1e0 | 1704 | * Only for firmware version < 4.0.0 |
ed25ffa1 AK |
1705 | */ |
1706 | netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID); | |
1707 | netxen_set_msg_privid(msg); | |
1708 | netxen_set_msg_count(msg, | |
438627c7 DP |
1709 | ((producer - 1) & |
1710 | (rds_ring->num_desc - 1))); | |
3176ff3e | 1711 | netxen_set_msg_ctxid(msg, adapter->portnum); |
ed25ffa1 | 1712 | netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid)); |
f03b0ebd DP |
1713 | NXWRIO(adapter, DB_NORMALIZE(adapter, |
1714 | NETXEN_RCV_PRODUCER_OFFSET), msg); | |
48bfd1e0 | 1715 | } |
ed25ffa1 AK |
1716 | } |
1717 | } | |
1718 | ||
becf46a0 | 1719 | static void |
d8b100c5 DP |
1720 | netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
1721 | struct nx_host_rds_ring *rds_ring) | |
ed25ffa1 | 1722 | { |
ed25ffa1 AK |
1723 | struct rcv_desc *pdesc; |
1724 | struct netxen_rx_buffer *buffer; | |
d8b100c5 | 1725 | int producer, count = 0; |
d9e651bc | 1726 | struct list_head *head; |
ed25ffa1 | 1727 | |
48bfd1e0 | 1728 | producer = rds_ring->producer; |
d8b100c5 DP |
1729 | if (!spin_trylock(&rds_ring->lock)) |
1730 | return; | |
1731 | ||
d9e651bc | 1732 | head = &rds_ring->free_list; |
d9e651bc DP |
1733 | while (!list_empty(head)) { |
1734 | ||
d8b100c5 | 1735 | buffer = list_entry(head->next, struct netxen_rx_buffer, list); |
6f703406 | 1736 | |
d8b100c5 DP |
1737 | if (!buffer->skb) { |
1738 | if (netxen_alloc_rx_skb(adapter, rds_ring, buffer)) | |
1739 | break; | |
6f703406 DP |
1740 | } |
1741 | ||
1742 | count++; | |
d9e651bc DP |
1743 | list_del(&buffer->list); |
1744 | ||
3d396eb1 | 1745 | /* make a rcv descriptor */ |
6f703406 | 1746 | pdesc = &rds_ring->desc_head[producer]; |
ed33ebe4 | 1747 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
48bfd1e0 | 1748 | pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); |
3d396eb1 | 1749 | pdesc->addr_buffer = cpu_to_le64(buffer->dma); |
6f703406 | 1750 | |
438627c7 | 1751 | producer = get_next_index(producer, rds_ring->num_desc); |
3d396eb1 AK |
1752 | } |
1753 | ||
3d396eb1 | 1754 | if (count) { |
48bfd1e0 | 1755 | rds_ring->producer = producer; |
195c5f98 | 1756 | NXWRIO(adapter, rds_ring->crb_rcv_producer, |
438627c7 | 1757 | (producer - 1) & (rds_ring->num_desc - 1)); |
3d396eb1 | 1758 | } |
d8b100c5 | 1759 | spin_unlock(&rds_ring->lock); |
3d396eb1 AK |
1760 | } |
1761 | ||
3d396eb1 AK |
1762 | void netxen_nic_clear_stats(struct netxen_adapter *adapter) |
1763 | { | |
3d396eb1 | 1764 | memset(&adapter->stats, 0, sizeof(adapter->stats)); |
3176ff3e | 1765 | return; |
3d396eb1 AK |
1766 | } |
1767 |