Commit | Line | Data |
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3d396eb1 AK |
1 | /* |
2 | * Copyright (C) 2003 - 2006 NetXen, Inc. | |
3 | * All rights reserved. | |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
25 | * NetXen, | |
26 | * 3965 Freedom Circle, Fourth floor, | |
27 | * Santa Clara, CA 95054 | |
28 | * | |
29 | * | |
30 | * Source file for NIC routines to initialize the Phantom Hardware | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/netdevice.h> | |
35 | #include <linux/delay.h> | |
36 | #include "netxen_nic.h" | |
37 | #include "netxen_nic_hw.h" | |
3d396eb1 AK |
38 | #include "netxen_nic_phan_reg.h" |
39 | ||
40 | struct crb_addr_pair { | |
e0e20a1a LCMT |
41 | u32 addr; |
42 | u32 data; | |
3d396eb1 AK |
43 | }; |
44 | ||
45 | #define NETXEN_MAX_CRB_XFORM 60 | |
46 | static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM]; | |
e0e20a1a | 47 | #define NETXEN_ADDR_ERROR (0xffffffff) |
3d396eb1 AK |
48 | |
49 | #define crb_addr_transform(name) \ | |
50 | crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \ | |
51 | NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20 | |
52 | ||
cb8011ad AK |
53 | #define NETXEN_NIC_XDMA_RESET 0x8000ff |
54 | ||
993fb90c AB |
55 | static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
56 | uint32_t ctx, uint32_t ringid); | |
57 | ||
58 | #if 0 | |
59 | static void netxen_nic_locked_write_reg(struct netxen_adapter *adapter, | |
60 | unsigned long off, int *data) | |
3d396eb1 | 61 | { |
cb8011ad | 62 | void __iomem *addr = pci_base_offset(adapter, off); |
3d396eb1 AK |
63 | writel(*data, addr); |
64 | } | |
993fb90c | 65 | #endif /* 0 */ |
3d396eb1 AK |
66 | |
67 | static void crb_addr_transform_setup(void) | |
68 | { | |
69 | crb_addr_transform(XDMA); | |
70 | crb_addr_transform(TIMR); | |
71 | crb_addr_transform(SRE); | |
72 | crb_addr_transform(SQN3); | |
73 | crb_addr_transform(SQN2); | |
74 | crb_addr_transform(SQN1); | |
75 | crb_addr_transform(SQN0); | |
76 | crb_addr_transform(SQS3); | |
77 | crb_addr_transform(SQS2); | |
78 | crb_addr_transform(SQS1); | |
79 | crb_addr_transform(SQS0); | |
80 | crb_addr_transform(RPMX7); | |
81 | crb_addr_transform(RPMX6); | |
82 | crb_addr_transform(RPMX5); | |
83 | crb_addr_transform(RPMX4); | |
84 | crb_addr_transform(RPMX3); | |
85 | crb_addr_transform(RPMX2); | |
86 | crb_addr_transform(RPMX1); | |
87 | crb_addr_transform(RPMX0); | |
88 | crb_addr_transform(ROMUSB); | |
89 | crb_addr_transform(SN); | |
90 | crb_addr_transform(QMN); | |
91 | crb_addr_transform(QMS); | |
92 | crb_addr_transform(PGNI); | |
93 | crb_addr_transform(PGND); | |
94 | crb_addr_transform(PGN3); | |
95 | crb_addr_transform(PGN2); | |
96 | crb_addr_transform(PGN1); | |
97 | crb_addr_transform(PGN0); | |
98 | crb_addr_transform(PGSI); | |
99 | crb_addr_transform(PGSD); | |
100 | crb_addr_transform(PGS3); | |
101 | crb_addr_transform(PGS2); | |
102 | crb_addr_transform(PGS1); | |
103 | crb_addr_transform(PGS0); | |
104 | crb_addr_transform(PS); | |
105 | crb_addr_transform(PH); | |
106 | crb_addr_transform(NIU); | |
107 | crb_addr_transform(I2Q); | |
108 | crb_addr_transform(EG); | |
109 | crb_addr_transform(MN); | |
110 | crb_addr_transform(MS); | |
111 | crb_addr_transform(CAS2); | |
112 | crb_addr_transform(CAS1); | |
113 | crb_addr_transform(CAS0); | |
114 | crb_addr_transform(CAM); | |
115 | crb_addr_transform(C2C1); | |
116 | crb_addr_transform(C2C0); | |
1fcca1a5 | 117 | crb_addr_transform(SMB); |
e4c93c81 DP |
118 | crb_addr_transform(OCM0); |
119 | crb_addr_transform(I2C0); | |
3d396eb1 AK |
120 | } |
121 | ||
122 | int netxen_init_firmware(struct netxen_adapter *adapter) | |
123 | { | |
124 | u32 state = 0, loops = 0, err = 0; | |
125 | ||
126 | /* Window 1 call */ | |
3ce06a32 | 127 | state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE); |
3d396eb1 AK |
128 | |
129 | if (state == PHAN_INITIALIZE_ACK) | |
130 | return 0; | |
131 | ||
132 | while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) { | |
2956640d | 133 | msleep(1); |
3d396eb1 | 134 | /* Window 1 call */ |
3ce06a32 | 135 | state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE); |
3d396eb1 AK |
136 | |
137 | loops++; | |
138 | } | |
139 | if (loops >= 2000) { | |
140 | printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n", | |
141 | state); | |
142 | err = -EIO; | |
143 | return err; | |
144 | } | |
145 | /* Window 1 call */ | |
3ce06a32 DP |
146 | adapter->pci_write_normalize(adapter, |
147 | CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT); | |
148 | adapter->pci_write_normalize(adapter, | |
149 | CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC); | |
150 | adapter->pci_write_normalize(adapter, | |
151 | CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE); | |
152 | adapter->pci_write_normalize(adapter, | |
153 | CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK); | |
3d396eb1 AK |
154 | |
155 | return err; | |
156 | } | |
157 | ||
2956640d | 158 | void netxen_release_rx_buffers(struct netxen_adapter *adapter) |
3d396eb1 | 159 | { |
2956640d | 160 | struct netxen_recv_context *recv_ctx; |
48bfd1e0 | 161 | struct nx_host_rds_ring *rds_ring; |
2956640d DP |
162 | struct netxen_rx_buffer *rx_buf; |
163 | int i, ctxid, ring; | |
3d396eb1 | 164 | |
3d396eb1 | 165 | for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) { |
2956640d | 166 | recv_ctx = &adapter->recv_ctx[ctxid]; |
48bfd1e0 DP |
167 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
168 | rds_ring = &recv_ctx->rds_rings[ring]; | |
169 | for (i = 0; i < rds_ring->max_rx_desc_count; ++i) { | |
170 | rx_buf = &(rds_ring->rx_buf_arr[i]); | |
2956640d DP |
171 | if (rx_buf->state == NETXEN_BUFFER_FREE) |
172 | continue; | |
173 | pci_unmap_single(adapter->pdev, | |
174 | rx_buf->dma, | |
48bfd1e0 | 175 | rds_ring->dma_size, |
2956640d DP |
176 | PCI_DMA_FROMDEVICE); |
177 | if (rx_buf->skb != NULL) | |
178 | dev_kfree_skb_any(rx_buf->skb); | |
179 | } | |
180 | } | |
181 | } | |
182 | } | |
183 | ||
184 | void netxen_release_tx_buffers(struct netxen_adapter *adapter) | |
185 | { | |
186 | struct netxen_cmd_buffer *cmd_buf; | |
187 | struct netxen_skb_frag *buffrag; | |
188 | int i, j; | |
189 | ||
190 | cmd_buf = adapter->cmd_buf_arr; | |
191 | for (i = 0; i < adapter->max_tx_desc_count; i++) { | |
192 | buffrag = cmd_buf->frag_array; | |
193 | if (buffrag->dma) { | |
194 | pci_unmap_single(adapter->pdev, buffrag->dma, | |
195 | buffrag->length, PCI_DMA_TODEVICE); | |
196 | buffrag->dma = 0ULL; | |
197 | } | |
198 | for (j = 0; j < cmd_buf->frag_count; j++) { | |
199 | buffrag++; | |
200 | if (buffrag->dma) { | |
201 | pci_unmap_page(adapter->pdev, buffrag->dma, | |
202 | buffrag->length, | |
203 | PCI_DMA_TODEVICE); | |
204 | buffrag->dma = 0ULL; | |
205 | } | |
206 | } | |
207 | /* Free the skb we received in netxen_nic_xmit_frame */ | |
208 | if (cmd_buf->skb) { | |
209 | dev_kfree_skb_any(cmd_buf->skb); | |
210 | cmd_buf->skb = NULL; | |
211 | } | |
212 | cmd_buf++; | |
213 | } | |
214 | } | |
215 | ||
216 | void netxen_free_sw_resources(struct netxen_adapter *adapter) | |
217 | { | |
218 | struct netxen_recv_context *recv_ctx; | |
48bfd1e0 | 219 | struct nx_host_rds_ring *rds_ring; |
2956640d DP |
220 | int ctx, ring; |
221 | ||
222 | for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) { | |
223 | recv_ctx = &adapter->recv_ctx[ctx]; | |
48bfd1e0 DP |
224 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
225 | rds_ring = &recv_ctx->rds_rings[ring]; | |
226 | if (rds_ring->rx_buf_arr) { | |
227 | vfree(rds_ring->rx_buf_arr); | |
228 | rds_ring->rx_buf_arr = NULL; | |
2956640d DP |
229 | } |
230 | } | |
231 | } | |
232 | if (adapter->cmd_buf_arr) | |
233 | vfree(adapter->cmd_buf_arr); | |
234 | return; | |
235 | } | |
236 | ||
237 | int netxen_alloc_sw_resources(struct netxen_adapter *adapter) | |
238 | { | |
239 | struct netxen_recv_context *recv_ctx; | |
48bfd1e0 | 240 | struct nx_host_rds_ring *rds_ring; |
2956640d DP |
241 | struct netxen_rx_buffer *rx_buf; |
242 | int ctx, ring, i, num_rx_bufs; | |
243 | ||
244 | struct netxen_cmd_buffer *cmd_buf_arr; | |
245 | struct net_device *netdev = adapter->netdev; | |
246 | ||
247 | cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE); | |
248 | if (cmd_buf_arr == NULL) { | |
249 | printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n", | |
250 | netdev->name); | |
251 | return -ENOMEM; | |
252 | } | |
253 | memset(cmd_buf_arr, 0, TX_RINGSIZE); | |
254 | adapter->cmd_buf_arr = cmd_buf_arr; | |
255 | ||
256 | for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) { | |
257 | recv_ctx = &adapter->recv_ctx[ctx]; | |
48bfd1e0 DP |
258 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
259 | rds_ring = &recv_ctx->rds_rings[ring]; | |
2956640d DP |
260 | switch (RCV_DESC_TYPE(ring)) { |
261 | case RCV_DESC_NORMAL: | |
48bfd1e0 | 262 | rds_ring->max_rx_desc_count = |
2956640d | 263 | adapter->max_rx_desc_count; |
48bfd1e0 DP |
264 | rds_ring->flags = RCV_DESC_NORMAL; |
265 | rds_ring->dma_size = RX_DMA_MAP_LEN; | |
266 | rds_ring->skb_size = MAX_RX_BUFFER_LENGTH; | |
2956640d DP |
267 | break; |
268 | ||
269 | case RCV_DESC_JUMBO: | |
48bfd1e0 | 270 | rds_ring->max_rx_desc_count = |
2956640d | 271 | adapter->max_jumbo_rx_desc_count; |
48bfd1e0 DP |
272 | rds_ring->flags = RCV_DESC_JUMBO; |
273 | rds_ring->dma_size = RX_JUMBO_DMA_MAP_LEN; | |
274 | rds_ring->skb_size = | |
2956640d DP |
275 | MAX_RX_JUMBO_BUFFER_LENGTH; |
276 | break; | |
277 | ||
278 | case RCV_RING_LRO: | |
48bfd1e0 | 279 | rds_ring->max_rx_desc_count = |
2956640d | 280 | adapter->max_lro_rx_desc_count; |
48bfd1e0 DP |
281 | rds_ring->flags = RCV_DESC_LRO; |
282 | rds_ring->dma_size = RX_LRO_DMA_MAP_LEN; | |
283 | rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH; | |
2956640d DP |
284 | break; |
285 | ||
286 | } | |
48bfd1e0 | 287 | rds_ring->rx_buf_arr = (struct netxen_rx_buffer *) |
2956640d | 288 | vmalloc(RCV_BUFFSIZE); |
48bfd1e0 | 289 | if (rds_ring->rx_buf_arr == NULL) { |
2956640d DP |
290 | printk(KERN_ERR "%s: Failed to allocate " |
291 | "rx buffer ring %d\n", | |
292 | netdev->name, ring); | |
293 | /* free whatever was already allocated */ | |
294 | goto err_out; | |
295 | } | |
48bfd1e0 DP |
296 | memset(rds_ring->rx_buf_arr, 0, RCV_BUFFSIZE); |
297 | rds_ring->begin_alloc = 0; | |
3d396eb1 AK |
298 | /* |
299 | * Now go through all of them, set reference handles | |
300 | * and put them in the queues. | |
301 | */ | |
48bfd1e0 DP |
302 | num_rx_bufs = rds_ring->max_rx_desc_count; |
303 | rx_buf = rds_ring->rx_buf_arr; | |
3d396eb1 AK |
304 | for (i = 0; i < num_rx_bufs; i++) { |
305 | rx_buf->ref_handle = i; | |
306 | rx_buf->state = NETXEN_BUFFER_FREE; | |
3d396eb1 AK |
307 | rx_buf++; |
308 | } | |
309 | } | |
310 | } | |
2956640d DP |
311 | |
312 | return 0; | |
313 | ||
314 | err_out: | |
315 | netxen_free_sw_resources(adapter); | |
316 | return -ENOMEM; | |
3d396eb1 AK |
317 | } |
318 | ||
3d396eb1 AK |
319 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter) |
320 | { | |
3d396eb1 AK |
321 | switch (adapter->ahw.board_type) { |
322 | case NETXEN_NIC_GBE: | |
80922fbc | 323 | adapter->enable_phy_interrupts = |
3d396eb1 | 324 | netxen_niu_gbe_enable_phy_interrupts; |
80922fbc | 325 | adapter->disable_phy_interrupts = |
3d396eb1 | 326 | netxen_niu_gbe_disable_phy_interrupts; |
80922fbc AK |
327 | adapter->macaddr_set = netxen_niu_macaddr_set; |
328 | adapter->set_mtu = netxen_nic_set_mtu_gb; | |
329 | adapter->set_promisc = netxen_niu_set_promiscuous_mode; | |
80922fbc AK |
330 | adapter->phy_read = netxen_niu_gbe_phy_read; |
331 | adapter->phy_write = netxen_niu_gbe_phy_write; | |
c9fc891f | 332 | adapter->init_port = netxen_niu_gbe_init_port; |
80922fbc | 333 | adapter->stop_port = netxen_niu_disable_gbe_port; |
3d396eb1 AK |
334 | break; |
335 | ||
336 | case NETXEN_NIC_XGBE: | |
80922fbc | 337 | adapter->enable_phy_interrupts = |
3d396eb1 | 338 | netxen_niu_xgbe_enable_phy_interrupts; |
80922fbc | 339 | adapter->disable_phy_interrupts = |
3d396eb1 | 340 | netxen_niu_xgbe_disable_phy_interrupts; |
80922fbc AK |
341 | adapter->macaddr_set = netxen_niu_xg_macaddr_set; |
342 | adapter->set_mtu = netxen_nic_set_mtu_xgb; | |
343 | adapter->init_port = netxen_niu_xg_init_port; | |
344 | adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode; | |
80922fbc | 345 | adapter->stop_port = netxen_niu_disable_xg_port; |
3d396eb1 AK |
346 | break; |
347 | ||
348 | default: | |
349 | break; | |
350 | } | |
351 | } | |
352 | ||
353 | /* | |
354 | * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB | |
355 | * address to external PCI CRB address. | |
356 | */ | |
993fb90c | 357 | static u32 netxen_decode_crb_addr(u32 addr) |
3d396eb1 AK |
358 | { |
359 | int i; | |
e0e20a1a | 360 | u32 base_addr, offset, pci_base; |
3d396eb1 AK |
361 | |
362 | crb_addr_transform_setup(); | |
363 | ||
364 | pci_base = NETXEN_ADDR_ERROR; | |
365 | base_addr = addr & 0xfff00000; | |
366 | offset = addr & 0x000fffff; | |
367 | ||
368 | for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) { | |
369 | if (crb_addr_xform[i] == base_addr) { | |
370 | pci_base = i << 20; | |
371 | break; | |
372 | } | |
373 | } | |
374 | if (pci_base == NETXEN_ADDR_ERROR) | |
375 | return pci_base; | |
376 | else | |
377 | return (pci_base + offset); | |
378 | } | |
379 | ||
13ba9c77 MT |
380 | static long rom_max_timeout = 100; |
381 | static long rom_lock_timeout = 10000; | |
7830b22c | 382 | #if 0 |
27d2ab54 | 383 | static long rom_write_timeout = 700; |
7830b22c | 384 | #endif |
3d396eb1 | 385 | |
993fb90c | 386 | static int rom_lock(struct netxen_adapter *adapter) |
3d396eb1 AK |
387 | { |
388 | int iter; | |
389 | u32 done = 0; | |
390 | int timeout = 0; | |
391 | ||
392 | while (!done) { | |
393 | /* acquire semaphore2 from PCI HW block */ | |
394 | netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK), | |
395 | &done); | |
396 | if (done == 1) | |
397 | break; | |
398 | if (timeout >= rom_lock_timeout) | |
399 | return -EIO; | |
400 | ||
401 | timeout++; | |
402 | /* | |
403 | * Yield CPU | |
404 | */ | |
405 | if (!in_atomic()) | |
406 | schedule(); | |
407 | else { | |
408 | for (iter = 0; iter < 20; iter++) | |
409 | cpu_relax(); /*This a nop instr on i386 */ | |
410 | } | |
411 | } | |
412 | netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER); | |
413 | return 0; | |
414 | } | |
415 | ||
993fb90c | 416 | static int netxen_wait_rom_done(struct netxen_adapter *adapter) |
3d396eb1 AK |
417 | { |
418 | long timeout = 0; | |
419 | long done = 0; | |
420 | ||
421 | while (done == 0) { | |
422 | done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS); | |
423 | done &= 2; | |
424 | timeout++; | |
425 | if (timeout >= rom_max_timeout) { | |
426 | printk("Timeout reached waiting for rom done"); | |
427 | return -EIO; | |
428 | } | |
429 | } | |
430 | return 0; | |
431 | } | |
432 | ||
7830b22c | 433 | #if 0 |
993fb90c | 434 | static int netxen_rom_wren(struct netxen_adapter *adapter) |
cb8011ad AK |
435 | { |
436 | /* Set write enable latch in ROM status register */ | |
437 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
438 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
439 | M25P_INSTR_WREN); | |
440 | if (netxen_wait_rom_done(adapter)) { | |
441 | return -1; | |
442 | } | |
443 | return 0; | |
444 | } | |
445 | ||
993fb90c AB |
446 | static unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter, |
447 | unsigned int addr) | |
cb8011ad AK |
448 | { |
449 | unsigned int data = 0xdeaddead; | |
450 | data = netxen_nic_reg_read(adapter, addr); | |
451 | return data; | |
452 | } | |
453 | ||
993fb90c | 454 | static int netxen_do_rom_rdsr(struct netxen_adapter *adapter) |
cb8011ad AK |
455 | { |
456 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
457 | M25P_INSTR_RDSR); | |
458 | if (netxen_wait_rom_done(adapter)) { | |
459 | return -1; | |
460 | } | |
461 | return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA); | |
462 | } | |
7830b22c | 463 | #endif |
cb8011ad | 464 | |
993fb90c | 465 | static void netxen_rom_unlock(struct netxen_adapter *adapter) |
cb8011ad AK |
466 | { |
467 | u32 val; | |
468 | ||
469 | /* release semaphore2 */ | |
470 | netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val); | |
471 | ||
472 | } | |
473 | ||
7830b22c | 474 | #if 0 |
993fb90c | 475 | static int netxen_rom_wip_poll(struct netxen_adapter *adapter) |
cb8011ad AK |
476 | { |
477 | long timeout = 0; | |
478 | long wip = 1; | |
479 | int val; | |
480 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
481 | while (wip != 0) { | |
482 | val = netxen_do_rom_rdsr(adapter); | |
483 | wip = val & 1; | |
484 | timeout++; | |
485 | if (timeout > rom_max_timeout) { | |
486 | return -1; | |
487 | } | |
488 | } | |
489 | return 0; | |
490 | } | |
491 | ||
993fb90c AB |
492 | static int do_rom_fast_write(struct netxen_adapter *adapter, int addr, |
493 | int data) | |
cb8011ad AK |
494 | { |
495 | if (netxen_rom_wren(adapter)) { | |
496 | return -1; | |
497 | } | |
498 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data); | |
499 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); | |
500 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
501 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
502 | M25P_INSTR_PP); | |
503 | if (netxen_wait_rom_done(adapter)) { | |
504 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
505 | return -1; | |
506 | } | |
507 | ||
508 | return netxen_rom_wip_poll(adapter); | |
509 | } | |
7830b22c | 510 | #endif |
cb8011ad | 511 | |
993fb90c AB |
512 | static int do_rom_fast_read(struct netxen_adapter *adapter, |
513 | int addr, int *valp) | |
3d396eb1 | 514 | { |
96acb6eb | 515 | cond_resched(); |
b58ecad8 | 516 | |
3d396eb1 AK |
517 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); |
518 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
b58ecad8 | 519 | udelay(100); /* prevent bursting on CRB */ |
3d396eb1 AK |
520 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
521 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb); | |
522 | if (netxen_wait_rom_done(adapter)) { | |
523 | printk("Error waiting for rom done\n"); | |
524 | return -EIO; | |
525 | } | |
526 | /* reset abyte_cnt and dummy_byte_cnt */ | |
527 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
b58ecad8 | 528 | udelay(100); /* prevent bursting on CRB */ |
3d396eb1 AK |
529 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
530 | ||
531 | *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA); | |
532 | return 0; | |
533 | } | |
534 | ||
993fb90c AB |
535 | static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
536 | u8 *bytes, size_t size) | |
27d2ab54 AK |
537 | { |
538 | int addridx; | |
539 | int ret = 0; | |
540 | ||
541 | for (addridx = addr; addridx < (addr + size); addridx += 4) { | |
f305f789 AV |
542 | int v; |
543 | ret = do_rom_fast_read(adapter, addridx, &v); | |
27d2ab54 AK |
544 | if (ret != 0) |
545 | break; | |
f305f789 | 546 | *(__le32 *)bytes = cpu_to_le32(v); |
27d2ab54 AK |
547 | bytes += 4; |
548 | } | |
549 | ||
550 | return ret; | |
551 | } | |
552 | ||
553 | int | |
4790654c | 554 | netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
555 | u8 *bytes, size_t size) |
556 | { | |
557 | int ret; | |
558 | ||
559 | ret = rom_lock(adapter); | |
560 | if (ret < 0) | |
561 | return ret; | |
562 | ||
563 | ret = do_rom_fast_read_words(adapter, addr, bytes, size); | |
564 | ||
565 | netxen_rom_unlock(adapter); | |
566 | return ret; | |
567 | } | |
568 | ||
3d396eb1 AK |
569 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp) |
570 | { | |
571 | int ret; | |
572 | ||
573 | if (rom_lock(adapter) != 0) | |
574 | return -EIO; | |
575 | ||
576 | ret = do_rom_fast_read(adapter, addr, valp); | |
cb8011ad AK |
577 | netxen_rom_unlock(adapter); |
578 | return ret; | |
579 | } | |
580 | ||
993fb90c | 581 | #if 0 |
cb8011ad AK |
582 | int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data) |
583 | { | |
584 | int ret = 0; | |
585 | ||
586 | if (rom_lock(adapter) != 0) { | |
587 | return -1; | |
588 | } | |
589 | ret = do_rom_fast_write(adapter, addr, data); | |
590 | netxen_rom_unlock(adapter); | |
591 | return ret; | |
592 | } | |
27d2ab54 | 593 | |
4790654c | 594 | static int do_rom_fast_write_words(struct netxen_adapter *adapter, |
993fb90c | 595 | int addr, u8 *bytes, size_t size) |
27d2ab54 AK |
596 | { |
597 | int addridx = addr; | |
598 | int ret = 0; | |
599 | ||
600 | while (addridx < (addr + size)) { | |
601 | int last_attempt = 0; | |
602 | int timeout = 0; | |
603 | int data; | |
604 | ||
f305f789 | 605 | data = le32_to_cpu((*(__le32*)bytes)); |
27d2ab54 AK |
606 | ret = do_rom_fast_write(adapter, addridx, data); |
607 | if (ret < 0) | |
608 | return ret; | |
4790654c | 609 | |
27d2ab54 AK |
610 | while(1) { |
611 | int data1; | |
612 | ||
f8dfdd5c SH |
613 | ret = do_rom_fast_read(adapter, addridx, &data1); |
614 | if (ret < 0) | |
615 | return ret; | |
616 | ||
27d2ab54 AK |
617 | if (data1 == data) |
618 | break; | |
619 | ||
620 | if (timeout++ >= rom_write_timeout) { | |
621 | if (last_attempt++ < 4) { | |
4790654c | 622 | ret = do_rom_fast_write(adapter, |
27d2ab54 AK |
623 | addridx, data); |
624 | if (ret < 0) | |
625 | return ret; | |
626 | } | |
627 | else { | |
628 | printk(KERN_INFO "Data write did not " | |
629 | "succeed at address 0x%x\n", addridx); | |
630 | break; | |
631 | } | |
632 | } | |
633 | } | |
634 | ||
635 | bytes += 4; | |
636 | addridx += 4; | |
637 | } | |
638 | ||
639 | return ret; | |
640 | } | |
641 | ||
4790654c | 642 | int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
643 | u8 *bytes, size_t size) |
644 | { | |
645 | int ret = 0; | |
646 | ||
647 | ret = rom_lock(adapter); | |
648 | if (ret < 0) | |
649 | return ret; | |
650 | ||
651 | ret = do_rom_fast_write_words(adapter, addr, bytes, size); | |
652 | netxen_rom_unlock(adapter); | |
653 | ||
654 | return ret; | |
655 | } | |
656 | ||
993fb90c | 657 | static int netxen_rom_wrsr(struct netxen_adapter *adapter, int data) |
27d2ab54 AK |
658 | { |
659 | int ret; | |
660 | ||
661 | ret = netxen_rom_wren(adapter); | |
662 | if (ret < 0) | |
663 | return ret; | |
664 | ||
665 | netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data); | |
4790654c | 666 | netxen_crb_writelit_adapter(adapter, |
27d2ab54 AK |
667 | NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1); |
668 | ||
669 | ret = netxen_wait_rom_done(adapter); | |
670 | if (ret < 0) | |
671 | return ret; | |
672 | ||
673 | return netxen_rom_wip_poll(adapter); | |
674 | } | |
675 | ||
993fb90c | 676 | static int netxen_rom_rdsr(struct netxen_adapter *adapter) |
27d2ab54 AK |
677 | { |
678 | int ret; | |
679 | ||
680 | ret = rom_lock(adapter); | |
681 | if (ret < 0) | |
682 | return ret; | |
683 | ||
684 | ret = netxen_do_rom_rdsr(adapter); | |
685 | netxen_rom_unlock(adapter); | |
686 | return ret; | |
687 | } | |
688 | ||
689 | int netxen_backup_crbinit(struct netxen_adapter *adapter) | |
690 | { | |
691 | int ret = FLASH_SUCCESS; | |
692 | int val; | |
0d04761d | 693 | char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL); |
27d2ab54 AK |
694 | |
695 | if (!buffer) | |
4790654c | 696 | return -ENOMEM; |
27d2ab54 AK |
697 | /* unlock sector 63 */ |
698 | val = netxen_rom_rdsr(adapter); | |
699 | val = val & 0xe3; | |
700 | ret = netxen_rom_wrsr(adapter, val); | |
701 | if (ret != FLASH_SUCCESS) | |
702 | goto out_kfree; | |
703 | ||
704 | ret = netxen_rom_wip_poll(adapter); | |
705 | if (ret != FLASH_SUCCESS) | |
706 | goto out_kfree; | |
707 | ||
708 | /* copy sector 0 to sector 63 */ | |
4790654c | 709 | ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START, |
0d04761d | 710 | buffer, NETXEN_FLASH_SECTOR_SIZE); |
27d2ab54 AK |
711 | if (ret != FLASH_SUCCESS) |
712 | goto out_kfree; | |
713 | ||
4790654c | 714 | ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START, |
0d04761d | 715 | buffer, NETXEN_FLASH_SECTOR_SIZE); |
27d2ab54 AK |
716 | if (ret != FLASH_SUCCESS) |
717 | goto out_kfree; | |
718 | ||
719 | /* lock sector 63 */ | |
720 | val = netxen_rom_rdsr(adapter); | |
721 | if (!(val & 0x8)) { | |
722 | val |= (0x1 << 2); | |
723 | /* lock sector 63 */ | |
724 | if (netxen_rom_wrsr(adapter, val) == 0) { | |
725 | ret = netxen_rom_wip_poll(adapter); | |
726 | if (ret != FLASH_SUCCESS) | |
727 | goto out_kfree; | |
728 | ||
729 | /* lock SR writes */ | |
730 | ret = netxen_rom_wip_poll(adapter); | |
731 | if (ret != FLASH_SUCCESS) | |
732 | goto out_kfree; | |
733 | } | |
734 | } | |
735 | ||
736 | out_kfree: | |
737 | kfree(buffer); | |
738 | return ret; | |
739 | } | |
740 | ||
993fb90c | 741 | static int netxen_do_rom_se(struct netxen_adapter *adapter, int addr) |
cb8011ad AK |
742 | { |
743 | netxen_rom_wren(adapter); | |
744 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); | |
745 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); | |
746 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, | |
747 | M25P_INSTR_SE); | |
748 | if (netxen_wait_rom_done(adapter)) { | |
749 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
750 | return -1; | |
751 | } | |
752 | return netxen_rom_wip_poll(adapter); | |
753 | } | |
754 | ||
993fb90c | 755 | static void check_erased_flash(struct netxen_adapter *adapter, int addr) |
27d2ab54 AK |
756 | { |
757 | int i; | |
758 | int val; | |
759 | int count = 0, erased_errors = 0; | |
760 | int range; | |
761 | ||
4790654c | 762 | range = (addr == NETXEN_USER_START) ? |
0d04761d | 763 | NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE; |
4790654c | 764 | |
27d2ab54 AK |
765 | for (i = addr; i < range; i += 4) { |
766 | netxen_rom_fast_read(adapter, i, &val); | |
767 | if (val != 0xffffffff) | |
768 | erased_errors++; | |
769 | count++; | |
770 | } | |
771 | ||
772 | if (erased_errors) | |
773 | printk(KERN_INFO "0x%x out of 0x%x words fail to be erased " | |
774 | "for sector address: %x\n", erased_errors, count, addr); | |
775 | } | |
776 | ||
cb8011ad AK |
777 | int netxen_rom_se(struct netxen_adapter *adapter, int addr) |
778 | { | |
779 | int ret = 0; | |
780 | if (rom_lock(adapter) != 0) { | |
781 | return -1; | |
782 | } | |
783 | ret = netxen_do_rom_se(adapter, addr); | |
784 | netxen_rom_unlock(adapter); | |
27d2ab54 AK |
785 | msleep(30); |
786 | check_erased_flash(adapter, addr); | |
787 | ||
788 | return ret; | |
789 | } | |
790 | ||
993fb90c AB |
791 | static int netxen_flash_erase_sections(struct netxen_adapter *adapter, |
792 | int start, int end) | |
27d2ab54 AK |
793 | { |
794 | int ret = FLASH_SUCCESS; | |
795 | int i; | |
796 | ||
797 | for (i = start; i < end; i++) { | |
0d04761d | 798 | ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE); |
27d2ab54 AK |
799 | if (ret) |
800 | break; | |
801 | ret = netxen_rom_wip_poll(adapter); | |
802 | if (ret < 0) | |
803 | return ret; | |
804 | } | |
805 | ||
806 | return ret; | |
807 | } | |
808 | ||
809 | int | |
810 | netxen_flash_erase_secondary(struct netxen_adapter *adapter) | |
811 | { | |
812 | int ret = FLASH_SUCCESS; | |
813 | int start, end; | |
814 | ||
0d04761d MT |
815 | start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE; |
816 | end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE; | |
27d2ab54 AK |
817 | ret = netxen_flash_erase_sections(adapter, start, end); |
818 | ||
819 | return ret; | |
820 | } | |
821 | ||
822 | int | |
823 | netxen_flash_erase_primary(struct netxen_adapter *adapter) | |
824 | { | |
825 | int ret = FLASH_SUCCESS; | |
826 | int start, end; | |
827 | ||
0d04761d MT |
828 | start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE; |
829 | end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE; | |
27d2ab54 AK |
830 | ret = netxen_flash_erase_sections(adapter, start, end); |
831 | ||
832 | return ret; | |
833 | } | |
834 | ||
e45d9ab4 AK |
835 | void netxen_halt_pegs(struct netxen_adapter *adapter) |
836 | { | |
837 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1); | |
838 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1); | |
839 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1); | |
840 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1); | |
841 | } | |
842 | ||
27d2ab54 AK |
843 | int netxen_flash_unlock(struct netxen_adapter *adapter) |
844 | { | |
845 | int ret = 0; | |
846 | ||
847 | ret = netxen_rom_wrsr(adapter, 0); | |
848 | if (ret < 0) | |
849 | return ret; | |
850 | ||
851 | ret = netxen_rom_wren(adapter); | |
852 | if (ret < 0) | |
853 | return ret; | |
854 | ||
3d396eb1 AK |
855 | return ret; |
856 | } | |
7830b22c | 857 | #endif /* 0 */ |
3d396eb1 AK |
858 | |
859 | #define NETXEN_BOARDTYPE 0x4008 | |
860 | #define NETXEN_BOARDNUM 0x400c | |
861 | #define NETXEN_CHIPNUM 0x4010 | |
3d396eb1 AK |
862 | |
863 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose) | |
864 | { | |
dcd56fdb | 865 | int addr, val; |
2956640d | 866 | int i, init_delay = 0; |
3d396eb1 | 867 | struct crb_addr_pair *buf; |
2956640d | 868 | unsigned offset, n; |
e0e20a1a | 869 | u32 off; |
3d396eb1 AK |
870 | |
871 | /* resetall */ | |
3d396eb1 | 872 | netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET, |
2956640d | 873 | 0xffffffff); |
3d396eb1 AK |
874 | |
875 | if (verbose) { | |
3d396eb1 AK |
876 | if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0) |
877 | printk("P2 ROM board type: 0x%08x\n", val); | |
878 | else | |
879 | printk("Could not read board type\n"); | |
880 | if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0) | |
881 | printk("P2 ROM board num: 0x%08x\n", val); | |
882 | else | |
883 | printk("Could not read board number\n"); | |
884 | if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0) | |
885 | printk("P2 ROM chip num: 0x%08x\n", val); | |
886 | else | |
887 | printk("Could not read chip number\n"); | |
888 | } | |
889 | ||
2956640d DP |
890 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
891 | if (netxen_rom_fast_read(adapter, 0, &n) != 0 || | |
892 | (n != 0xcafecafeUL) || | |
893 | netxen_rom_fast_read(adapter, 4, &n) != 0) { | |
894 | printk(KERN_ERR "%s: ERROR Reading crb_init area: " | |
895 | "n: %08x\n", netxen_nic_driver_name, n); | |
3d396eb1 AK |
896 | return -EIO; |
897 | } | |
2956640d DP |
898 | offset = n & 0xffffU; |
899 | n = (n >> 16) & 0xffffU; | |
900 | } else { | |
901 | if (netxen_rom_fast_read(adapter, 0, &n) != 0 || | |
902 | !(n & 0x80000000)) { | |
903 | printk(KERN_ERR "%s: ERROR Reading crb_init area: " | |
904 | "n: %08x\n", netxen_nic_driver_name, n); | |
905 | return -EIO; | |
3d396eb1 | 906 | } |
2956640d DP |
907 | offset = 1; |
908 | n &= ~0x80000000; | |
909 | } | |
910 | ||
911 | if (n < 1024) { | |
912 | if (verbose) | |
913 | printk(KERN_DEBUG "%s: %d CRB init values found" | |
914 | " in ROM.\n", netxen_nic_driver_name, n); | |
915 | } else { | |
916 | printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not" | |
917 | " initialized.\n", __func__, n); | |
918 | return -EIO; | |
919 | } | |
3d396eb1 | 920 | |
2956640d DP |
921 | buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL); |
922 | if (buf == NULL) { | |
923 | printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n", | |
924 | netxen_nic_driver_name); | |
925 | return -ENOMEM; | |
926 | } | |
927 | for (i = 0; i < n; i++) { | |
928 | if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 || | |
929 | netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) | |
930 | return -EIO; | |
931 | ||
932 | buf[i].addr = addr; | |
933 | buf[i].data = val; | |
934 | ||
935 | if (verbose) | |
936 | printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n", | |
937 | netxen_nic_driver_name, | |
938 | (u32)netxen_decode_crb_addr(addr), val); | |
939 | } | |
940 | for (i = 0; i < n; i++) { | |
941 | ||
942 | off = netxen_decode_crb_addr(buf[i].addr); | |
943 | if (off == NETXEN_ADDR_ERROR) { | |
944 | printk(KERN_ERR"CRB init value out of range %x\n", | |
1fcca1a5 | 945 | buf[i].addr); |
2956640d DP |
946 | continue; |
947 | } | |
948 | off += NETXEN_PCI_CRBSPACE; | |
949 | /* skipping cold reboot MAGIC */ | |
950 | if (off == NETXEN_CAM_RAM(0x1fc)) | |
951 | continue; | |
952 | ||
953 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | |
954 | /* do not reset PCI */ | |
955 | if (off == (ROMUSB_GLB + 0xbc)) | |
1fcca1a5 | 956 | continue; |
2956640d DP |
957 | if (off == (NETXEN_CRB_PEG_NET_1 + 0x18)) |
958 | buf[i].data = 0x1020; | |
959 | /* skip the function enable register */ | |
960 | if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION)) | |
3d396eb1 | 961 | continue; |
2956640d DP |
962 | if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2)) |
963 | continue; | |
964 | if ((off & 0x0ff00000) == NETXEN_CRB_SMB) | |
965 | continue; | |
966 | } | |
3d396eb1 | 967 | |
2956640d DP |
968 | if (off == NETXEN_ADDR_ERROR) { |
969 | printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n", | |
970 | netxen_nic_driver_name, buf[i].addr); | |
971 | continue; | |
972 | } | |
973 | ||
974 | /* After writing this register, HW needs time for CRB */ | |
975 | /* to quiet down (else crb_window returns 0xffffffff) */ | |
976 | if (off == NETXEN_ROMUSB_GLB_SW_RESET) { | |
977 | init_delay = 1; | |
978 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
3d396eb1 | 979 | /* hold xdma in reset also */ |
cb8011ad | 980 | buf[i].data = NETXEN_NIC_XDMA_RESET; |
3d396eb1 | 981 | } |
2956640d | 982 | } |
3d396eb1 | 983 | |
2956640d | 984 | adapter->hw_write_wx(adapter, off, &buf[i].data, 4); |
3d396eb1 | 985 | |
2956640d DP |
986 | if (init_delay == 1) { |
987 | msleep(1000); | |
988 | init_delay = 0; | |
3d396eb1 | 989 | } |
2956640d DP |
990 | msleep(1); |
991 | } | |
992 | kfree(buf); | |
3d396eb1 | 993 | |
2956640d | 994 | /* disable_peg_cache_all */ |
3d396eb1 | 995 | |
2956640d DP |
996 | /* unreset_net_cache */ |
997 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
998 | adapter->hw_read_wx(adapter, | |
999 | NETXEN_ROMUSB_GLB_SW_RESET, &val, 4); | |
3d396eb1 | 1000 | netxen_crb_writelit_adapter(adapter, |
2956640d | 1001 | NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f)); |
3d396eb1 | 1002 | } |
2956640d DP |
1003 | |
1004 | /* p2dn replyCount */ | |
1005 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e); | |
1006 | /* disable_peg_cache 0 */ | |
1007 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8); | |
1008 | /* disable_peg_cache 1 */ | |
1009 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8); | |
1010 | ||
1011 | /* peg_clr_all */ | |
1012 | ||
1013 | /* peg_clr 0 */ | |
1014 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0); | |
1015 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0); | |
1016 | /* peg_clr 1 */ | |
1017 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0); | |
1018 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0); | |
1019 | /* peg_clr 2 */ | |
1020 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0); | |
1021 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0); | |
1022 | /* peg_clr 3 */ | |
1023 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0); | |
1024 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0); | |
3d396eb1 AK |
1025 | return 0; |
1026 | } | |
1027 | ||
ed25ffa1 AK |
1028 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter) |
1029 | { | |
1030 | uint64_t addr; | |
1031 | uint32_t hi; | |
1032 | uint32_t lo; | |
1033 | ||
1034 | adapter->dummy_dma.addr = | |
7830b22c | 1035 | pci_alloc_consistent(adapter->pdev, |
ed25ffa1 AK |
1036 | NETXEN_HOST_DUMMY_DMA_SIZE, |
1037 | &adapter->dummy_dma.phys_addr); | |
1038 | if (adapter->dummy_dma.addr == NULL) { | |
1039 | printk("%s: ERROR: Could not allocate dummy DMA memory\n", | |
2956640d | 1040 | __func__); |
ed25ffa1 AK |
1041 | return -ENOMEM; |
1042 | } | |
1043 | ||
1044 | addr = (uint64_t) adapter->dummy_dma.phys_addr; | |
1045 | hi = (addr >> 32) & 0xffffffff; | |
1046 | lo = addr & 0xffffffff; | |
1047 | ||
3ce06a32 DP |
1048 | adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi); |
1049 | adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo); | |
ed25ffa1 | 1050 | |
2956640d DP |
1051 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
1052 | uint32_t temp = 0; | |
1053 | adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4); | |
1054 | } | |
1055 | ||
ed25ffa1 AK |
1056 | return 0; |
1057 | } | |
1058 | ||
1059 | void netxen_free_adapter_offload(struct netxen_adapter *adapter) | |
1060 | { | |
439b454e DP |
1061 | int i; |
1062 | ||
ed25ffa1 | 1063 | if (adapter->dummy_dma.addr) { |
439b454e DP |
1064 | i = 100; |
1065 | do { | |
1066 | if (dma_watchdog_shutdown_request(adapter) == 1) | |
1067 | break; | |
1068 | msleep(50); | |
1069 | if (dma_watchdog_shutdown_poll_result(adapter) == 1) | |
1070 | break; | |
1071 | } while (--i); | |
1072 | ||
1073 | if (i) { | |
7830b22c | 1074 | pci_free_consistent(adapter->pdev, |
ed25ffa1 AK |
1075 | NETXEN_HOST_DUMMY_DMA_SIZE, |
1076 | adapter->dummy_dma.addr, | |
1077 | adapter->dummy_dma.phys_addr); | |
439b454e DP |
1078 | adapter->dummy_dma.addr = NULL; |
1079 | } else { | |
1080 | printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n", | |
1081 | adapter->netdev->name); | |
1082 | } | |
ed25ffa1 AK |
1083 | } |
1084 | } | |
1085 | ||
96acb6eb | 1086 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val) |
3d396eb1 AK |
1087 | { |
1088 | u32 val = 0; | |
2956640d | 1089 | int retries = 60; |
3d396eb1 | 1090 | |
cb8011ad | 1091 | if (!pegtune_val) { |
96acb6eb | 1092 | do { |
3ce06a32 DP |
1093 | val = adapter->pci_read_normalize(adapter, |
1094 | CRB_CMDPEG_STATE); | |
96acb6eb DP |
1095 | |
1096 | if (val == PHAN_INITIALIZE_COMPLETE || | |
1097 | val == PHAN_INITIALIZE_ACK) | |
1098 | return 0; | |
1099 | ||
2956640d DP |
1100 | msleep(500); |
1101 | ||
96acb6eb | 1102 | } while (--retries); |
2956640d | 1103 | |
96acb6eb | 1104 | if (!retries) { |
2956640d DP |
1105 | pegtune_val = adapter->pci_read_normalize(adapter, |
1106 | NETXEN_ROMUSB_GLB_PEGTUNE_DONE); | |
96acb6eb DP |
1107 | printk(KERN_WARNING "netxen_phantom_init: init failed, " |
1108 | "pegtune_val=%x\n", pegtune_val); | |
1109 | return -1; | |
3d396eb1 | 1110 | } |
3d396eb1 | 1111 | } |
96acb6eb DP |
1112 | |
1113 | return 0; | |
3d396eb1 AK |
1114 | } |
1115 | ||
2956640d DP |
1116 | int netxen_receive_peg_ready(struct netxen_adapter *adapter) |
1117 | { | |
1118 | u32 val = 0; | |
1119 | int retries = 2000; | |
1120 | ||
1121 | do { | |
1122 | val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE); | |
1123 | ||
1124 | if (val == PHAN_PEG_RCV_INITIALIZED) | |
1125 | return 0; | |
1126 | ||
1127 | msleep(10); | |
1128 | ||
1129 | } while (--retries); | |
1130 | ||
1131 | if (!retries) { | |
1132 | printk(KERN_ERR "Receive Peg initialization not " | |
1133 | "complete, state: 0x%x.\n", val); | |
1134 | return -EIO; | |
1135 | } | |
1136 | ||
1137 | return 0; | |
1138 | } | |
1139 | ||
3d396eb1 AK |
1140 | /* |
1141 | * netxen_process_rcv() send the received packet to the protocol stack. | |
1142 | * and if the number of receives exceeds RX_BUFFERS_REFILL, then we | |
1143 | * invoke the routine to send more rx buffers to the Phantom... | |
1144 | */ | |
993fb90c AB |
1145 | static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid, |
1146 | struct status_desc *desc) | |
3d396eb1 | 1147 | { |
3176ff3e MT |
1148 | struct pci_dev *pdev = adapter->pdev; |
1149 | struct net_device *netdev = adapter->netdev; | |
5dc16268 DP |
1150 | u64 sts_data = le64_to_cpu(desc->status_desc_data); |
1151 | int index = netxen_get_sts_refhandle(sts_data); | |
3d396eb1 AK |
1152 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]); |
1153 | struct netxen_rx_buffer *buffer; | |
1154 | struct sk_buff *skb; | |
5dc16268 | 1155 | u32 length = netxen_get_sts_totallength(sts_data); |
3d396eb1 | 1156 | u32 desc_ctx; |
48bfd1e0 | 1157 | struct nx_host_rds_ring *rds_ring; |
3d396eb1 AK |
1158 | int ret; |
1159 | ||
5dc16268 | 1160 | desc_ctx = netxen_get_sts_type(sts_data); |
3d396eb1 AK |
1161 | if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) { |
1162 | printk("%s: %s Bad Rcv descriptor ring\n", | |
1163 | netxen_nic_driver_name, netdev->name); | |
1164 | return; | |
1165 | } | |
1166 | ||
48bfd1e0 DP |
1167 | rds_ring = &recv_ctx->rds_rings[desc_ctx]; |
1168 | if (unlikely(index > rds_ring->max_rx_desc_count)) { | |
ed25ffa1 | 1169 | DPRINTK(ERR, "Got a buffer index:%x Max is %x\n", |
48bfd1e0 | 1170 | index, rds_ring->max_rx_desc_count); |
ed25ffa1 AK |
1171 | return; |
1172 | } | |
48bfd1e0 | 1173 | buffer = &rds_ring->rx_buf_arr[index]; |
ed25ffa1 AK |
1174 | if (desc_ctx == RCV_DESC_LRO_CTXID) { |
1175 | buffer->lro_current_frags++; | |
1176 | if (netxen_get_sts_desc_lro_last_frag(desc)) { | |
1177 | buffer->lro_expected_frags = | |
1178 | netxen_get_sts_desc_lro_cnt(desc); | |
1179 | buffer->lro_length = length; | |
1180 | } | |
1181 | if (buffer->lro_current_frags != buffer->lro_expected_frags) { | |
1182 | if (buffer->lro_expected_frags != 0) { | |
5bc51424 JP |
1183 | printk("LRO: (refhandle:%x) recv frag. " |
1184 | "wait for last. flags: %x expected:%d " | |
ed25ffa1 AK |
1185 | "have:%d\n", index, |
1186 | netxen_get_sts_desc_lro_last_frag(desc), | |
1187 | buffer->lro_expected_frags, | |
1188 | buffer->lro_current_frags); | |
1189 | } | |
1190 | return; | |
1191 | } | |
1192 | } | |
3d396eb1 | 1193 | |
48bfd1e0 | 1194 | pci_unmap_single(pdev, buffer->dma, rds_ring->dma_size, |
3d396eb1 AK |
1195 | PCI_DMA_FROMDEVICE); |
1196 | ||
1197 | skb = (struct sk_buff *)buffer->skb; | |
1198 | ||
200eef20 | 1199 | if (likely(adapter->rx_csum && |
d1847a72 | 1200 | netxen_get_sts_status(sts_data) == STATUS_CKSUM_OK)) { |
3176ff3e | 1201 | adapter->stats.csummed++; |
3d396eb1 | 1202 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
200eef20 DP |
1203 | } else |
1204 | skb->ip_summed = CHECKSUM_NONE; | |
1205 | ||
96acb6eb | 1206 | skb->dev = netdev; |
ed25ffa1 AK |
1207 | if (desc_ctx == RCV_DESC_LRO_CTXID) { |
1208 | /* True length was only available on the last pkt */ | |
1209 | skb_put(skb, buffer->lro_length); | |
1210 | } else { | |
1211 | skb_put(skb, length); | |
1212 | } | |
1213 | ||
3d396eb1 AK |
1214 | skb->protocol = eth_type_trans(skb, netdev); |
1215 | ||
1216 | ret = netif_receive_skb(skb); | |
3d396eb1 AK |
1217 | netdev->last_rx = jiffies; |
1218 | ||
3d396eb1 AK |
1219 | /* |
1220 | * We just consumed one buffer so post a buffer. | |
1221 | */ | |
3d396eb1 AK |
1222 | buffer->skb = NULL; |
1223 | buffer->state = NETXEN_BUFFER_FREE; | |
ed25ffa1 AK |
1224 | buffer->lro_current_frags = 0; |
1225 | buffer->lro_expected_frags = 0; | |
3d396eb1 | 1226 | |
3176ff3e MT |
1227 | adapter->stats.no_rcv++; |
1228 | adapter->stats.rxbytes += length; | |
3d396eb1 AK |
1229 | } |
1230 | ||
1231 | /* Process Receive status ring */ | |
1232 | u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max) | |
1233 | { | |
1234 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]); | |
1235 | struct status_desc *desc_head = recv_ctx->rcv_status_desc_head; | |
1236 | struct status_desc *desc; /* used to read status desc here */ | |
1237 | u32 consumer = recv_ctx->status_rx_consumer; | |
1238 | int count = 0, ring; | |
1239 | ||
3d396eb1 AK |
1240 | while (count < max) { |
1241 | desc = &desc_head[consumer]; | |
a608ab9c | 1242 | if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) { |
ed25ffa1 AK |
1243 | DPRINTK(ERR, "desc %p ownedby %x\n", desc, |
1244 | netxen_get_sts_owner(desc)); | |
3d396eb1 AK |
1245 | break; |
1246 | } | |
1247 | netxen_process_rcv(adapter, ctxid, desc); | |
a608ab9c | 1248 | netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM); |
3d396eb1 AK |
1249 | consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1); |
1250 | count++; | |
1251 | } | |
48bfd1e0 | 1252 | for (ring = 0; ring < adapter->max_rds_rings; ring++) |
05aaa02d | 1253 | netxen_post_rx_buffers_nodb(adapter, ctxid, ring); |
3d396eb1 AK |
1254 | |
1255 | /* update the consumer index in phantom */ | |
1256 | if (count) { | |
3d396eb1 AK |
1257 | recv_ctx->status_rx_consumer = consumer; |
1258 | ||
1259 | /* Window = 1 */ | |
3ce06a32 DP |
1260 | adapter->pci_write_normalize(adapter, |
1261 | recv_ctx->crb_sts_consumer, consumer); | |
3d396eb1 AK |
1262 | } |
1263 | ||
1264 | return count; | |
1265 | } | |
1266 | ||
1267 | /* Process Command status ring */ | |
05aaa02d | 1268 | int netxen_process_cmd_ring(struct netxen_adapter *adapter) |
3d396eb1 | 1269 | { |
ba53e6b4 DP |
1270 | u32 last_consumer, consumer; |
1271 | int count = 0, i; | |
3d396eb1 | 1272 | struct netxen_cmd_buffer *buffer; |
ba53e6b4 DP |
1273 | struct pci_dev *pdev = adapter->pdev; |
1274 | struct net_device *netdev = adapter->netdev; | |
3d396eb1 | 1275 | struct netxen_skb_frag *frag; |
ba53e6b4 | 1276 | int done = 0; |
3d396eb1 | 1277 | |
3d396eb1 | 1278 | last_consumer = adapter->last_cmd_consumer; |
9b410117 | 1279 | consumer = le32_to_cpu(*(adapter->cmd_consumer)); |
3d396eb1 | 1280 | |
ba53e6b4 | 1281 | while (last_consumer != consumer) { |
3d396eb1 | 1282 | buffer = &adapter->cmd_buf_arr[last_consumer]; |
53a01e00 | 1283 | if (buffer->skb) { |
1284 | frag = &buffer->frag_array[0]; | |
3d396eb1 AK |
1285 | pci_unmap_single(pdev, frag->dma, frag->length, |
1286 | PCI_DMA_TODEVICE); | |
96acb6eb | 1287 | frag->dma = 0ULL; |
3d396eb1 | 1288 | for (i = 1; i < buffer->frag_count; i++) { |
3d396eb1 AK |
1289 | frag++; /* Get the next frag */ |
1290 | pci_unmap_page(pdev, frag->dma, frag->length, | |
1291 | PCI_DMA_TODEVICE); | |
96acb6eb | 1292 | frag->dma = 0ULL; |
3d396eb1 AK |
1293 | } |
1294 | ||
ba53e6b4 | 1295 | adapter->stats.xmitfinished++; |
53a01e00 | 1296 | dev_kfree_skb_any(buffer->skb); |
1297 | buffer->skb = NULL; | |
3d396eb1 AK |
1298 | } |
1299 | ||
1300 | last_consumer = get_next_index(last_consumer, | |
1301 | adapter->max_tx_desc_count); | |
ba53e6b4 DP |
1302 | if (++count >= MAX_STATUS_HANDLE) |
1303 | break; | |
3d396eb1 | 1304 | } |
3d396eb1 | 1305 | |
ba53e6b4 | 1306 | if (count) { |
3d396eb1 | 1307 | adapter->last_cmd_consumer = last_consumer; |
ba53e6b4 DP |
1308 | smp_mb(); |
1309 | if (netif_queue_stopped(netdev) && netif_running(netdev)) { | |
1310 | netif_tx_lock(netdev); | |
1311 | netif_wake_queue(netdev); | |
1312 | smp_mb(); | |
1313 | netif_tx_unlock(netdev); | |
3d396eb1 AK |
1314 | } |
1315 | } | |
ed25ffa1 AK |
1316 | /* |
1317 | * If everything is freed up to consumer then check if the ring is full | |
1318 | * If the ring is full then check if more needs to be freed and | |
1319 | * schedule the call back again. | |
1320 | * | |
1321 | * This happens when there are 2 CPUs. One could be freeing and the | |
1322 | * other filling it. If the ring is full when we get out of here and | |
1323 | * the card has already interrupted the host then the host can miss the | |
1324 | * interrupt. | |
1325 | * | |
1326 | * There is still a possible race condition and the host could miss an | |
1327 | * interrupt. The card has to take care of this. | |
1328 | */ | |
ba53e6b4 DP |
1329 | consumer = le32_to_cpu(*(adapter->cmd_consumer)); |
1330 | done = (last_consumer == consumer); | |
3d396eb1 | 1331 | |
ed25ffa1 | 1332 | return (done); |
3d396eb1 AK |
1333 | } |
1334 | ||
1335 | /* | |
1336 | * netxen_post_rx_buffers puts buffer in the Phantom memory | |
1337 | */ | |
1338 | void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid) | |
1339 | { | |
7830b22c | 1340 | struct pci_dev *pdev = adapter->pdev; |
3d396eb1 AK |
1341 | struct sk_buff *skb; |
1342 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]); | |
48bfd1e0 | 1343 | struct nx_host_rds_ring *rds_ring = NULL; |
ed25ffa1 | 1344 | uint producer; |
3d396eb1 AK |
1345 | struct rcv_desc *pdesc; |
1346 | struct netxen_rx_buffer *buffer; | |
1347 | int count = 0; | |
1348 | int index = 0; | |
ed25ffa1 AK |
1349 | netxen_ctx_msg msg = 0; |
1350 | dma_addr_t dma; | |
3d396eb1 | 1351 | |
48bfd1e0 | 1352 | rds_ring = &recv_ctx->rds_rings[ringid]; |
3d396eb1 | 1353 | |
48bfd1e0 DP |
1354 | producer = rds_ring->producer; |
1355 | index = rds_ring->begin_alloc; | |
1356 | buffer = &rds_ring->rx_buf_arr[index]; | |
3d396eb1 AK |
1357 | /* We can start writing rx descriptors into the phantom memory. */ |
1358 | while (buffer->state == NETXEN_BUFFER_FREE) { | |
48bfd1e0 | 1359 | skb = dev_alloc_skb(rds_ring->skb_size); |
3d396eb1 AK |
1360 | if (unlikely(!skb)) { |
1361 | /* | |
ed25ffa1 | 1362 | * TODO |
3d396eb1 AK |
1363 | * We need to schedule the posting of buffers to the pegs. |
1364 | */ | |
48bfd1e0 | 1365 | rds_ring->begin_alloc = index; |
cb8011ad | 1366 | DPRINTK(ERR, "netxen_post_rx_buffers: " |
3d396eb1 AK |
1367 | " allocated only %d buffers\n", count); |
1368 | break; | |
1369 | } | |
ed25ffa1 AK |
1370 | |
1371 | count++; /* now there should be no failure */ | |
48bfd1e0 | 1372 | pdesc = &rds_ring->desc_head[producer]; |
ed25ffa1 AK |
1373 | |
1374 | #if defined(XGB_DEBUG) | |
1375 | *(unsigned long *)(skb->head) = 0xc0debabe; | |
1376 | if (skb_is_nonlinear(skb)) { | |
1377 | printk("Allocated SKB @%p is nonlinear\n"); | |
1378 | } | |
1379 | #endif | |
1380 | skb_reserve(skb, 2); | |
1381 | /* This will be setup when we receive the | |
1382 | * buffer after it has been filled FSL TBD TBD | |
1383 | * skb->dev = netdev; | |
1384 | */ | |
48bfd1e0 | 1385 | dma = pci_map_single(pdev, skb->data, rds_ring->dma_size, |
ed25ffa1 | 1386 | PCI_DMA_FROMDEVICE); |
ed33ebe4 | 1387 | pdesc->addr_buffer = cpu_to_le64(dma); |
ed25ffa1 AK |
1388 | buffer->skb = skb; |
1389 | buffer->state = NETXEN_BUFFER_BUSY; | |
1390 | buffer->dma = dma; | |
1391 | /* make a rcv descriptor */ | |
ed33ebe4 | 1392 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
48bfd1e0 | 1393 | pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); |
ed25ffa1 AK |
1394 | DPRINTK(INFO, "done writing descripter\n"); |
1395 | producer = | |
48bfd1e0 DP |
1396 | get_next_index(producer, rds_ring->max_rx_desc_count); |
1397 | index = get_next_index(index, rds_ring->max_rx_desc_count); | |
1398 | buffer = &rds_ring->rx_buf_arr[index]; | |
ed25ffa1 AK |
1399 | } |
1400 | /* if we did allocate buffers, then write the count to Phantom */ | |
1401 | if (count) { | |
48bfd1e0 DP |
1402 | rds_ring->begin_alloc = index; |
1403 | rds_ring->producer = producer; | |
ed25ffa1 | 1404 | /* Window = 1 */ |
3ce06a32 | 1405 | adapter->pci_write_normalize(adapter, |
48bfd1e0 DP |
1406 | rds_ring->crb_rcv_producer, |
1407 | (producer-1) & (rds_ring->max_rx_desc_count-1)); | |
1408 | ||
1409 | if (adapter->fw_major < 4) { | |
ed25ffa1 AK |
1410 | /* |
1411 | * Write a doorbell msg to tell phanmon of change in | |
1412 | * receive ring producer | |
48bfd1e0 | 1413 | * Only for firmware version < 4.0.0 |
ed25ffa1 AK |
1414 | */ |
1415 | netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID); | |
1416 | netxen_set_msg_privid(msg); | |
1417 | netxen_set_msg_count(msg, | |
1418 | ((producer - | |
48bfd1e0 | 1419 | 1) & (rds_ring-> |
ed25ffa1 | 1420 | max_rx_desc_count - 1))); |
3176ff3e | 1421 | netxen_set_msg_ctxid(msg, adapter->portnum); |
ed25ffa1 AK |
1422 | netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid)); |
1423 | writel(msg, | |
1424 | DB_NORMALIZE(adapter, | |
1425 | NETXEN_RCV_PRODUCER_OFFSET)); | |
48bfd1e0 | 1426 | } |
ed25ffa1 AK |
1427 | } |
1428 | } | |
1429 | ||
993fb90c AB |
1430 | static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
1431 | uint32_t ctx, uint32_t ringid) | |
ed25ffa1 | 1432 | { |
7830b22c | 1433 | struct pci_dev *pdev = adapter->pdev; |
ed25ffa1 AK |
1434 | struct sk_buff *skb; |
1435 | struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]); | |
48bfd1e0 | 1436 | struct nx_host_rds_ring *rds_ring = NULL; |
ed25ffa1 AK |
1437 | u32 producer; |
1438 | struct rcv_desc *pdesc; | |
1439 | struct netxen_rx_buffer *buffer; | |
1440 | int count = 0; | |
1441 | int index = 0; | |
1442 | ||
48bfd1e0 | 1443 | rds_ring = &recv_ctx->rds_rings[ringid]; |
ed25ffa1 | 1444 | |
48bfd1e0 DP |
1445 | producer = rds_ring->producer; |
1446 | index = rds_ring->begin_alloc; | |
1447 | buffer = &rds_ring->rx_buf_arr[index]; | |
ed25ffa1 AK |
1448 | /* We can start writing rx descriptors into the phantom memory. */ |
1449 | while (buffer->state == NETXEN_BUFFER_FREE) { | |
48bfd1e0 | 1450 | skb = dev_alloc_skb(rds_ring->skb_size); |
ed25ffa1 AK |
1451 | if (unlikely(!skb)) { |
1452 | /* | |
1453 | * We need to schedule the posting of buffers to the pegs. | |
1454 | */ | |
48bfd1e0 | 1455 | rds_ring->begin_alloc = index; |
ed25ffa1 AK |
1456 | DPRINTK(ERR, "netxen_post_rx_buffers_nodb: " |
1457 | " allocated only %d buffers\n", count); | |
1458 | break; | |
1459 | } | |
3d396eb1 | 1460 | count++; /* now there should be no failure */ |
48bfd1e0 | 1461 | pdesc = &rds_ring->desc_head[producer]; |
ed25ffa1 | 1462 | skb_reserve(skb, 2); |
4790654c | 1463 | /* |
3d396eb1 AK |
1464 | * This will be setup when we receive the |
1465 | * buffer after it has been filled | |
1466 | * skb->dev = netdev; | |
1467 | */ | |
1468 | buffer->skb = skb; | |
1469 | buffer->state = NETXEN_BUFFER_BUSY; | |
1470 | buffer->dma = pci_map_single(pdev, skb->data, | |
48bfd1e0 | 1471 | rds_ring->dma_size, |
3d396eb1 | 1472 | PCI_DMA_FROMDEVICE); |
ed25ffa1 | 1473 | |
3d396eb1 | 1474 | /* make a rcv descriptor */ |
ed33ebe4 | 1475 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
48bfd1e0 | 1476 | pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); |
3d396eb1 | 1477 | pdesc->addr_buffer = cpu_to_le64(buffer->dma); |
3d396eb1 | 1478 | producer = |
48bfd1e0 DP |
1479 | get_next_index(producer, rds_ring->max_rx_desc_count); |
1480 | index = get_next_index(index, rds_ring->max_rx_desc_count); | |
1481 | buffer = &rds_ring->rx_buf_arr[index]; | |
3d396eb1 AK |
1482 | } |
1483 | ||
1484 | /* if we did allocate buffers, then write the count to Phantom */ | |
1485 | if (count) { | |
48bfd1e0 DP |
1486 | rds_ring->begin_alloc = index; |
1487 | rds_ring->producer = producer; | |
3d396eb1 | 1488 | /* Window = 1 */ |
3ce06a32 | 1489 | adapter->pci_write_normalize(adapter, |
48bfd1e0 DP |
1490 | rds_ring->crb_rcv_producer, |
1491 | (producer-1) & (rds_ring->max_rx_desc_count-1)); | |
3d396eb1 | 1492 | wmb(); |
3d396eb1 AK |
1493 | } |
1494 | } | |
1495 | ||
3d396eb1 AK |
1496 | void netxen_nic_clear_stats(struct netxen_adapter *adapter) |
1497 | { | |
3d396eb1 | 1498 | memset(&adapter->stats, 0, sizeof(adapter->stats)); |
3176ff3e | 1499 | return; |
3d396eb1 AK |
1500 | } |
1501 |