Commit | Line | Data |
---|---|---|
3d396eb1 | 1 | /* |
5d242f1c | 2 | * Copyright (C) 2003 - 2009 NetXen, Inc. |
3d396eb1 | 3 | * All rights reserved. |
80922fbc | 4 | * |
3d396eb1 AK |
5 | * This program is free software; you can redistribute it and/or |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
80922fbc | 9 | * |
3d396eb1 AK |
10 | * This program is distributed in the hope that it will be useful, but |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
80922fbc | 14 | * |
3d396eb1 AK |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
80922fbc | 19 | * |
3d396eb1 AK |
20 | * The full GNU General Public License is included in this distribution |
21 | * in the file called LICENSE. | |
80922fbc | 22 | * |
3d396eb1 AK |
23 | * Contact Information: |
24 | * info@netxen.com | |
5d242f1c DP |
25 | * NetXen Inc, |
26 | * 18922 Forge Drive | |
27 | * Cupertino, CA 95014-0701 | |
3d396eb1 AK |
28 | * |
29 | */ | |
30 | ||
31 | #include <linux/netdevice.h> | |
32 | #include <linux/delay.h> | |
33 | #include "netxen_nic.h" | |
34 | #include "netxen_nic_hw.h" | |
3d396eb1 AK |
35 | #include "netxen_nic_phan_reg.h" |
36 | ||
37 | struct crb_addr_pair { | |
e0e20a1a LCMT |
38 | u32 addr; |
39 | u32 data; | |
3d396eb1 AK |
40 | }; |
41 | ||
42 | #define NETXEN_MAX_CRB_XFORM 60 | |
43 | static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM]; | |
e0e20a1a | 44 | #define NETXEN_ADDR_ERROR (0xffffffff) |
3d396eb1 AK |
45 | |
46 | #define crb_addr_transform(name) \ | |
47 | crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \ | |
48 | NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20 | |
49 | ||
cb8011ad AK |
50 | #define NETXEN_NIC_XDMA_RESET 0x8000ff |
51 | ||
becf46a0 | 52 | static void |
d8b100c5 DP |
53 | netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
54 | struct nx_host_rds_ring *rds_ring); | |
993fb90c | 55 | |
3d396eb1 AK |
56 | static void crb_addr_transform_setup(void) |
57 | { | |
58 | crb_addr_transform(XDMA); | |
59 | crb_addr_transform(TIMR); | |
60 | crb_addr_transform(SRE); | |
61 | crb_addr_transform(SQN3); | |
62 | crb_addr_transform(SQN2); | |
63 | crb_addr_transform(SQN1); | |
64 | crb_addr_transform(SQN0); | |
65 | crb_addr_transform(SQS3); | |
66 | crb_addr_transform(SQS2); | |
67 | crb_addr_transform(SQS1); | |
68 | crb_addr_transform(SQS0); | |
69 | crb_addr_transform(RPMX7); | |
70 | crb_addr_transform(RPMX6); | |
71 | crb_addr_transform(RPMX5); | |
72 | crb_addr_transform(RPMX4); | |
73 | crb_addr_transform(RPMX3); | |
74 | crb_addr_transform(RPMX2); | |
75 | crb_addr_transform(RPMX1); | |
76 | crb_addr_transform(RPMX0); | |
77 | crb_addr_transform(ROMUSB); | |
78 | crb_addr_transform(SN); | |
79 | crb_addr_transform(QMN); | |
80 | crb_addr_transform(QMS); | |
81 | crb_addr_transform(PGNI); | |
82 | crb_addr_transform(PGND); | |
83 | crb_addr_transform(PGN3); | |
84 | crb_addr_transform(PGN2); | |
85 | crb_addr_transform(PGN1); | |
86 | crb_addr_transform(PGN0); | |
87 | crb_addr_transform(PGSI); | |
88 | crb_addr_transform(PGSD); | |
89 | crb_addr_transform(PGS3); | |
90 | crb_addr_transform(PGS2); | |
91 | crb_addr_transform(PGS1); | |
92 | crb_addr_transform(PGS0); | |
93 | crb_addr_transform(PS); | |
94 | crb_addr_transform(PH); | |
95 | crb_addr_transform(NIU); | |
96 | crb_addr_transform(I2Q); | |
97 | crb_addr_transform(EG); | |
98 | crb_addr_transform(MN); | |
99 | crb_addr_transform(MS); | |
100 | crb_addr_transform(CAS2); | |
101 | crb_addr_transform(CAS1); | |
102 | crb_addr_transform(CAS0); | |
103 | crb_addr_transform(CAM); | |
104 | crb_addr_transform(C2C1); | |
105 | crb_addr_transform(C2C0); | |
1fcca1a5 | 106 | crb_addr_transform(SMB); |
e4c93c81 DP |
107 | crb_addr_transform(OCM0); |
108 | crb_addr_transform(I2C0); | |
3d396eb1 AK |
109 | } |
110 | ||
111 | int netxen_init_firmware(struct netxen_adapter *adapter) | |
112 | { | |
113 | u32 state = 0, loops = 0, err = 0; | |
114 | ||
115 | /* Window 1 call */ | |
3ce06a32 | 116 | state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE); |
3d396eb1 AK |
117 | |
118 | if (state == PHAN_INITIALIZE_ACK) | |
119 | return 0; | |
120 | ||
121 | while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) { | |
2956640d | 122 | msleep(1); |
3d396eb1 | 123 | /* Window 1 call */ |
3ce06a32 | 124 | state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE); |
3d396eb1 AK |
125 | |
126 | loops++; | |
127 | } | |
128 | if (loops >= 2000) { | |
129 | printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n", | |
130 | state); | |
131 | err = -EIO; | |
132 | return err; | |
133 | } | |
134 | /* Window 1 call */ | |
3ce06a32 DP |
135 | adapter->pci_write_normalize(adapter, |
136 | CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT); | |
137 | adapter->pci_write_normalize(adapter, | |
138 | CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC); | |
139 | adapter->pci_write_normalize(adapter, | |
140 | CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE); | |
141 | adapter->pci_write_normalize(adapter, | |
142 | CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK); | |
3d396eb1 AK |
143 | |
144 | return err; | |
145 | } | |
146 | ||
2956640d | 147 | void netxen_release_rx_buffers(struct netxen_adapter *adapter) |
3d396eb1 | 148 | { |
2956640d | 149 | struct netxen_recv_context *recv_ctx; |
48bfd1e0 | 150 | struct nx_host_rds_ring *rds_ring; |
2956640d | 151 | struct netxen_rx_buffer *rx_buf; |
becf46a0 DP |
152 | int i, ring; |
153 | ||
154 | recv_ctx = &adapter->recv_ctx; | |
155 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
156 | rds_ring = &recv_ctx->rds_rings[ring]; | |
438627c7 | 157 | for (i = 0; i < rds_ring->num_desc; ++i) { |
becf46a0 DP |
158 | rx_buf = &(rds_ring->rx_buf_arr[i]); |
159 | if (rx_buf->state == NETXEN_BUFFER_FREE) | |
160 | continue; | |
161 | pci_unmap_single(adapter->pdev, | |
162 | rx_buf->dma, | |
163 | rds_ring->dma_size, | |
164 | PCI_DMA_FROMDEVICE); | |
165 | if (rx_buf->skb != NULL) | |
166 | dev_kfree_skb_any(rx_buf->skb); | |
2956640d DP |
167 | } |
168 | } | |
169 | } | |
170 | ||
171 | void netxen_release_tx_buffers(struct netxen_adapter *adapter) | |
172 | { | |
173 | struct netxen_cmd_buffer *cmd_buf; | |
174 | struct netxen_skb_frag *buffrag; | |
175 | int i, j; | |
d877f1e3 | 176 | struct nx_host_tx_ring *tx_ring = &adapter->tx_ring; |
2956640d | 177 | |
d877f1e3 DP |
178 | cmd_buf = tx_ring->cmd_buf_arr; |
179 | for (i = 0; i < tx_ring->num_desc; i++) { | |
2956640d DP |
180 | buffrag = cmd_buf->frag_array; |
181 | if (buffrag->dma) { | |
182 | pci_unmap_single(adapter->pdev, buffrag->dma, | |
183 | buffrag->length, PCI_DMA_TODEVICE); | |
184 | buffrag->dma = 0ULL; | |
185 | } | |
186 | for (j = 0; j < cmd_buf->frag_count; j++) { | |
187 | buffrag++; | |
188 | if (buffrag->dma) { | |
189 | pci_unmap_page(adapter->pdev, buffrag->dma, | |
190 | buffrag->length, | |
191 | PCI_DMA_TODEVICE); | |
192 | buffrag->dma = 0ULL; | |
193 | } | |
194 | } | |
2956640d DP |
195 | if (cmd_buf->skb) { |
196 | dev_kfree_skb_any(cmd_buf->skb); | |
197 | cmd_buf->skb = NULL; | |
198 | } | |
199 | cmd_buf++; | |
200 | } | |
201 | } | |
202 | ||
203 | void netxen_free_sw_resources(struct netxen_adapter *adapter) | |
204 | { | |
205 | struct netxen_recv_context *recv_ctx; | |
48bfd1e0 | 206 | struct nx_host_rds_ring *rds_ring; |
d877f1e3 | 207 | struct nx_host_tx_ring *tx_ring; |
becf46a0 DP |
208 | int ring; |
209 | ||
210 | recv_ctx = &adapter->recv_ctx; | |
211 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
212 | rds_ring = &recv_ctx->rds_rings[ring]; | |
213 | if (rds_ring->rx_buf_arr) { | |
214 | vfree(rds_ring->rx_buf_arr); | |
215 | rds_ring->rx_buf_arr = NULL; | |
2956640d DP |
216 | } |
217 | } | |
becf46a0 | 218 | |
d877f1e3 DP |
219 | tx_ring = &adapter->tx_ring; |
220 | if (tx_ring->cmd_buf_arr) | |
221 | vfree(tx_ring->cmd_buf_arr); | |
2956640d DP |
222 | return; |
223 | } | |
224 | ||
225 | int netxen_alloc_sw_resources(struct netxen_adapter *adapter) | |
226 | { | |
227 | struct netxen_recv_context *recv_ctx; | |
48bfd1e0 | 228 | struct nx_host_rds_ring *rds_ring; |
d8b100c5 | 229 | struct nx_host_sds_ring *sds_ring; |
d877f1e3 | 230 | struct nx_host_tx_ring *tx_ring = &adapter->tx_ring; |
2956640d | 231 | struct netxen_rx_buffer *rx_buf; |
becf46a0 | 232 | int ring, i, num_rx_bufs; |
2956640d DP |
233 | |
234 | struct netxen_cmd_buffer *cmd_buf_arr; | |
235 | struct net_device *netdev = adapter->netdev; | |
d877f1e3 | 236 | struct pci_dev *pdev = adapter->pdev; |
2956640d | 237 | |
d877f1e3 | 238 | tx_ring->num_desc = adapter->num_txd; |
d8b100c5 | 239 | cmd_buf_arr = |
d877f1e3 | 240 | (struct netxen_cmd_buffer *)vmalloc(TX_BUFF_RINGSIZE(tx_ring)); |
2956640d | 241 | if (cmd_buf_arr == NULL) { |
d877f1e3 | 242 | dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n", |
2956640d DP |
243 | netdev->name); |
244 | return -ENOMEM; | |
245 | } | |
d877f1e3 DP |
246 | memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring)); |
247 | tx_ring->cmd_buf_arr = cmd_buf_arr; | |
2956640d | 248 | |
becf46a0 DP |
249 | recv_ctx = &adapter->recv_ctx; |
250 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
251 | rds_ring = &recv_ctx->rds_rings[ring]; | |
438627c7 DP |
252 | switch (ring) { |
253 | case RCV_RING_NORMAL: | |
254 | rds_ring->num_desc = adapter->num_rxd; | |
becf46a0 DP |
255 | if (adapter->ahw.cut_through) { |
256 | rds_ring->dma_size = | |
257 | NX_CT_DEFAULT_RX_BUF_LEN; | |
48bfd1e0 | 258 | rds_ring->skb_size = |
becf46a0 DP |
259 | NX_CT_DEFAULT_RX_BUF_LEN; |
260 | } else { | |
261 | rds_ring->dma_size = RX_DMA_MAP_LEN; | |
262 | rds_ring->skb_size = | |
263 | MAX_RX_BUFFER_LENGTH; | |
264 | } | |
265 | break; | |
2956640d | 266 | |
438627c7 DP |
267 | case RCV_RING_JUMBO: |
268 | rds_ring->num_desc = adapter->num_jumbo_rxd; | |
becf46a0 DP |
269 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) |
270 | rds_ring->dma_size = | |
271 | NX_P3_RX_JUMBO_BUF_MAX_LEN; | |
272 | else | |
273 | rds_ring->dma_size = | |
274 | NX_P2_RX_JUMBO_BUF_MAX_LEN; | |
275 | rds_ring->skb_size = | |
276 | rds_ring->dma_size + NET_IP_ALIGN; | |
277 | break; | |
2956640d | 278 | |
becf46a0 | 279 | case RCV_RING_LRO: |
438627c7 | 280 | rds_ring->num_desc = adapter->num_lro_rxd; |
becf46a0 DP |
281 | rds_ring->dma_size = RX_LRO_DMA_MAP_LEN; |
282 | rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH; | |
283 | break; | |
284 | ||
285 | } | |
286 | rds_ring->rx_buf_arr = (struct netxen_rx_buffer *) | |
d8b100c5 | 287 | vmalloc(RCV_BUFF_RINGSIZE(rds_ring)); |
becf46a0 DP |
288 | if (rds_ring->rx_buf_arr == NULL) { |
289 | printk(KERN_ERR "%s: Failed to allocate " | |
290 | "rx buffer ring %d\n", | |
291 | netdev->name, ring); | |
292 | /* free whatever was already allocated */ | |
293 | goto err_out; | |
294 | } | |
d8b100c5 | 295 | memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring)); |
becf46a0 DP |
296 | INIT_LIST_HEAD(&rds_ring->free_list); |
297 | /* | |
298 | * Now go through all of them, set reference handles | |
299 | * and put them in the queues. | |
300 | */ | |
438627c7 | 301 | num_rx_bufs = rds_ring->num_desc; |
becf46a0 DP |
302 | rx_buf = rds_ring->rx_buf_arr; |
303 | for (i = 0; i < num_rx_bufs; i++) { | |
304 | list_add_tail(&rx_buf->list, | |
305 | &rds_ring->free_list); | |
306 | rx_buf->ref_handle = i; | |
307 | rx_buf->state = NETXEN_BUFFER_FREE; | |
308 | rx_buf++; | |
3d396eb1 | 309 | } |
d8b100c5 DP |
310 | spin_lock_init(&rds_ring->lock); |
311 | } | |
312 | ||
313 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { | |
314 | sds_ring = &recv_ctx->sds_rings[ring]; | |
315 | sds_ring->irq = adapter->msix_entries[ring].vector; | |
d8b100c5 DP |
316 | sds_ring->adapter = adapter; |
317 | sds_ring->num_desc = adapter->num_rxd; | |
318 | ||
319 | for (i = 0; i < NUM_RCV_DESC_RINGS; i++) | |
320 | INIT_LIST_HEAD(&sds_ring->free_list[i]); | |
3d396eb1 | 321 | } |
2956640d DP |
322 | |
323 | return 0; | |
324 | ||
325 | err_out: | |
326 | netxen_free_sw_resources(adapter); | |
327 | return -ENOMEM; | |
3d396eb1 AK |
328 | } |
329 | ||
3d396eb1 AK |
330 | void netxen_initialize_adapter_ops(struct netxen_adapter *adapter) |
331 | { | |
1e2d0059 | 332 | switch (adapter->ahw.port_type) { |
3d396eb1 | 333 | case NETXEN_NIC_GBE: |
80922fbc | 334 | adapter->enable_phy_interrupts = |
3d396eb1 | 335 | netxen_niu_gbe_enable_phy_interrupts; |
80922fbc | 336 | adapter->disable_phy_interrupts = |
3d396eb1 | 337 | netxen_niu_gbe_disable_phy_interrupts; |
80922fbc AK |
338 | adapter->macaddr_set = netxen_niu_macaddr_set; |
339 | adapter->set_mtu = netxen_nic_set_mtu_gb; | |
340 | adapter->set_promisc = netxen_niu_set_promiscuous_mode; | |
80922fbc AK |
341 | adapter->phy_read = netxen_niu_gbe_phy_read; |
342 | adapter->phy_write = netxen_niu_gbe_phy_write; | |
c9fc891f | 343 | adapter->init_port = netxen_niu_gbe_init_port; |
80922fbc | 344 | adapter->stop_port = netxen_niu_disable_gbe_port; |
3d396eb1 AK |
345 | break; |
346 | ||
347 | case NETXEN_NIC_XGBE: | |
80922fbc | 348 | adapter->enable_phy_interrupts = |
3d396eb1 | 349 | netxen_niu_xgbe_enable_phy_interrupts; |
80922fbc | 350 | adapter->disable_phy_interrupts = |
3d396eb1 | 351 | netxen_niu_xgbe_disable_phy_interrupts; |
80922fbc AK |
352 | adapter->macaddr_set = netxen_niu_xg_macaddr_set; |
353 | adapter->set_mtu = netxen_nic_set_mtu_xgb; | |
354 | adapter->init_port = netxen_niu_xg_init_port; | |
355 | adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode; | |
80922fbc | 356 | adapter->stop_port = netxen_niu_disable_xg_port; |
3d396eb1 AK |
357 | break; |
358 | ||
359 | default: | |
360 | break; | |
361 | } | |
9ad27643 DP |
362 | |
363 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | |
364 | adapter->set_mtu = nx_fw_cmd_set_mtu; | |
365 | adapter->set_promisc = netxen_p3_nic_set_promisc; | |
366 | } | |
3d396eb1 AK |
367 | } |
368 | ||
369 | /* | |
370 | * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB | |
371 | * address to external PCI CRB address. | |
372 | */ | |
993fb90c | 373 | static u32 netxen_decode_crb_addr(u32 addr) |
3d396eb1 AK |
374 | { |
375 | int i; | |
e0e20a1a | 376 | u32 base_addr, offset, pci_base; |
3d396eb1 AK |
377 | |
378 | crb_addr_transform_setup(); | |
379 | ||
380 | pci_base = NETXEN_ADDR_ERROR; | |
381 | base_addr = addr & 0xfff00000; | |
382 | offset = addr & 0x000fffff; | |
383 | ||
384 | for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) { | |
385 | if (crb_addr_xform[i] == base_addr) { | |
386 | pci_base = i << 20; | |
387 | break; | |
388 | } | |
389 | } | |
390 | if (pci_base == NETXEN_ADDR_ERROR) | |
391 | return pci_base; | |
392 | else | |
393 | return (pci_base + offset); | |
394 | } | |
395 | ||
13ba9c77 MT |
396 | static long rom_max_timeout = 100; |
397 | static long rom_lock_timeout = 10000; | |
3d396eb1 | 398 | |
993fb90c | 399 | static int rom_lock(struct netxen_adapter *adapter) |
3d396eb1 AK |
400 | { |
401 | int iter; | |
402 | u32 done = 0; | |
403 | int timeout = 0; | |
404 | ||
405 | while (!done) { | |
406 | /* acquire semaphore2 from PCI HW block */ | |
407 | netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK), | |
408 | &done); | |
409 | if (done == 1) | |
410 | break; | |
411 | if (timeout >= rom_lock_timeout) | |
412 | return -EIO; | |
413 | ||
414 | timeout++; | |
415 | /* | |
416 | * Yield CPU | |
417 | */ | |
418 | if (!in_atomic()) | |
419 | schedule(); | |
420 | else { | |
421 | for (iter = 0; iter < 20; iter++) | |
422 | cpu_relax(); /*This a nop instr on i386 */ | |
423 | } | |
424 | } | |
425 | netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER); | |
426 | return 0; | |
427 | } | |
428 | ||
993fb90c | 429 | static int netxen_wait_rom_done(struct netxen_adapter *adapter) |
3d396eb1 AK |
430 | { |
431 | long timeout = 0; | |
432 | long done = 0; | |
433 | ||
27c915a4 DP |
434 | cond_resched(); |
435 | ||
3d396eb1 AK |
436 | while (done == 0) { |
437 | done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS); | |
438 | done &= 2; | |
439 | timeout++; | |
440 | if (timeout >= rom_max_timeout) { | |
441 | printk("Timeout reached waiting for rom done"); | |
442 | return -EIO; | |
443 | } | |
444 | } | |
445 | return 0; | |
446 | } | |
447 | ||
993fb90c | 448 | static void netxen_rom_unlock(struct netxen_adapter *adapter) |
cb8011ad AK |
449 | { |
450 | u32 val; | |
451 | ||
452 | /* release semaphore2 */ | |
453 | netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val); | |
454 | ||
455 | } | |
456 | ||
993fb90c AB |
457 | static int do_rom_fast_read(struct netxen_adapter *adapter, |
458 | int addr, int *valp) | |
3d396eb1 AK |
459 | { |
460 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); | |
3d396eb1 | 461 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
27c915a4 | 462 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); |
3d396eb1 AK |
463 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb); |
464 | if (netxen_wait_rom_done(adapter)) { | |
465 | printk("Error waiting for rom done\n"); | |
466 | return -EIO; | |
467 | } | |
468 | /* reset abyte_cnt and dummy_byte_cnt */ | |
469 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); | |
27c915a4 | 470 | udelay(10); |
3d396eb1 AK |
471 | netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); |
472 | ||
473 | *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA); | |
474 | return 0; | |
475 | } | |
476 | ||
993fb90c AB |
477 | static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
478 | u8 *bytes, size_t size) | |
27d2ab54 AK |
479 | { |
480 | int addridx; | |
481 | int ret = 0; | |
482 | ||
483 | for (addridx = addr; addridx < (addr + size); addridx += 4) { | |
f305f789 AV |
484 | int v; |
485 | ret = do_rom_fast_read(adapter, addridx, &v); | |
27d2ab54 AK |
486 | if (ret != 0) |
487 | break; | |
f305f789 | 488 | *(__le32 *)bytes = cpu_to_le32(v); |
27d2ab54 AK |
489 | bytes += 4; |
490 | } | |
491 | ||
492 | return ret; | |
493 | } | |
494 | ||
495 | int | |
4790654c | 496 | netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, |
27d2ab54 AK |
497 | u8 *bytes, size_t size) |
498 | { | |
499 | int ret; | |
500 | ||
501 | ret = rom_lock(adapter); | |
502 | if (ret < 0) | |
503 | return ret; | |
504 | ||
505 | ret = do_rom_fast_read_words(adapter, addr, bytes, size); | |
506 | ||
507 | netxen_rom_unlock(adapter); | |
508 | return ret; | |
509 | } | |
510 | ||
3d396eb1 AK |
511 | int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp) |
512 | { | |
513 | int ret; | |
514 | ||
515 | if (rom_lock(adapter) != 0) | |
516 | return -EIO; | |
517 | ||
518 | ret = do_rom_fast_read(adapter, addr, valp); | |
cb8011ad AK |
519 | netxen_rom_unlock(adapter); |
520 | return ret; | |
521 | } | |
522 | ||
3d396eb1 AK |
523 | #define NETXEN_BOARDTYPE 0x4008 |
524 | #define NETXEN_BOARDNUM 0x400c | |
525 | #define NETXEN_CHIPNUM 0x4010 | |
3d396eb1 AK |
526 | |
527 | int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose) | |
528 | { | |
dcd56fdb | 529 | int addr, val; |
27c915a4 | 530 | int i, n, init_delay = 0; |
3d396eb1 | 531 | struct crb_addr_pair *buf; |
27c915a4 | 532 | unsigned offset; |
e0e20a1a | 533 | u32 off; |
3d396eb1 AK |
534 | |
535 | /* resetall */ | |
27c915a4 | 536 | rom_lock(adapter); |
3d396eb1 | 537 | netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET, |
2956640d | 538 | 0xffffffff); |
27c915a4 | 539 | netxen_rom_unlock(adapter); |
3d396eb1 AK |
540 | |
541 | if (verbose) { | |
3d396eb1 AK |
542 | if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0) |
543 | printk("P2 ROM board type: 0x%08x\n", val); | |
544 | else | |
545 | printk("Could not read board type\n"); | |
546 | if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0) | |
547 | printk("P2 ROM board num: 0x%08x\n", val); | |
548 | else | |
549 | printk("Could not read board number\n"); | |
550 | if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0) | |
551 | printk("P2 ROM chip num: 0x%08x\n", val); | |
552 | else | |
553 | printk("Could not read chip number\n"); | |
554 | } | |
555 | ||
2956640d DP |
556 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
557 | if (netxen_rom_fast_read(adapter, 0, &n) != 0 || | |
27c915a4 | 558 | (n != 0xcafecafe) || |
2956640d DP |
559 | netxen_rom_fast_read(adapter, 4, &n) != 0) { |
560 | printk(KERN_ERR "%s: ERROR Reading crb_init area: " | |
561 | "n: %08x\n", netxen_nic_driver_name, n); | |
3d396eb1 AK |
562 | return -EIO; |
563 | } | |
2956640d DP |
564 | offset = n & 0xffffU; |
565 | n = (n >> 16) & 0xffffU; | |
566 | } else { | |
567 | if (netxen_rom_fast_read(adapter, 0, &n) != 0 || | |
568 | !(n & 0x80000000)) { | |
569 | printk(KERN_ERR "%s: ERROR Reading crb_init area: " | |
570 | "n: %08x\n", netxen_nic_driver_name, n); | |
571 | return -EIO; | |
3d396eb1 | 572 | } |
2956640d DP |
573 | offset = 1; |
574 | n &= ~0x80000000; | |
575 | } | |
576 | ||
577 | if (n < 1024) { | |
578 | if (verbose) | |
579 | printk(KERN_DEBUG "%s: %d CRB init values found" | |
580 | " in ROM.\n", netxen_nic_driver_name, n); | |
581 | } else { | |
582 | printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not" | |
583 | " initialized.\n", __func__, n); | |
584 | return -EIO; | |
585 | } | |
3d396eb1 | 586 | |
2956640d DP |
587 | buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL); |
588 | if (buf == NULL) { | |
589 | printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n", | |
590 | netxen_nic_driver_name); | |
591 | return -ENOMEM; | |
592 | } | |
593 | for (i = 0; i < n; i++) { | |
594 | if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 || | |
584dbe94 DM |
595 | netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) { |
596 | kfree(buf); | |
2956640d | 597 | return -EIO; |
584dbe94 | 598 | } |
2956640d DP |
599 | |
600 | buf[i].addr = addr; | |
601 | buf[i].data = val; | |
602 | ||
603 | if (verbose) | |
604 | printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n", | |
605 | netxen_nic_driver_name, | |
606 | (u32)netxen_decode_crb_addr(addr), val); | |
607 | } | |
608 | for (i = 0; i < n; i++) { | |
609 | ||
610 | off = netxen_decode_crb_addr(buf[i].addr); | |
611 | if (off == NETXEN_ADDR_ERROR) { | |
612 | printk(KERN_ERR"CRB init value out of range %x\n", | |
1fcca1a5 | 613 | buf[i].addr); |
2956640d DP |
614 | continue; |
615 | } | |
616 | off += NETXEN_PCI_CRBSPACE; | |
617 | /* skipping cold reboot MAGIC */ | |
618 | if (off == NETXEN_CAM_RAM(0x1fc)) | |
619 | continue; | |
620 | ||
621 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | |
622 | /* do not reset PCI */ | |
623 | if (off == (ROMUSB_GLB + 0xbc)) | |
1fcca1a5 | 624 | continue; |
27c915a4 DP |
625 | if (off == (ROMUSB_GLB + 0xa8)) |
626 | continue; | |
627 | if (off == (ROMUSB_GLB + 0xc8)) /* core clock */ | |
628 | continue; | |
629 | if (off == (ROMUSB_GLB + 0x24)) /* MN clock */ | |
630 | continue; | |
631 | if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */ | |
632 | continue; | |
2956640d DP |
633 | if (off == (NETXEN_CRB_PEG_NET_1 + 0x18)) |
634 | buf[i].data = 0x1020; | |
635 | /* skip the function enable register */ | |
636 | if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION)) | |
3d396eb1 | 637 | continue; |
2956640d DP |
638 | if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2)) |
639 | continue; | |
640 | if ((off & 0x0ff00000) == NETXEN_CRB_SMB) | |
641 | continue; | |
642 | } | |
3d396eb1 | 643 | |
2956640d DP |
644 | if (off == NETXEN_ADDR_ERROR) { |
645 | printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n", | |
646 | netxen_nic_driver_name, buf[i].addr); | |
647 | continue; | |
648 | } | |
649 | ||
27c915a4 | 650 | init_delay = 1; |
2956640d DP |
651 | /* After writing this register, HW needs time for CRB */ |
652 | /* to quiet down (else crb_window returns 0xffffffff) */ | |
653 | if (off == NETXEN_ROMUSB_GLB_SW_RESET) { | |
27c915a4 | 654 | init_delay = 1000; |
2956640d | 655 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
3d396eb1 | 656 | /* hold xdma in reset also */ |
cb8011ad | 657 | buf[i].data = NETXEN_NIC_XDMA_RESET; |
27c915a4 | 658 | buf[i].data = 0x8000ff; |
3d396eb1 | 659 | } |
2956640d | 660 | } |
3d396eb1 | 661 | |
2956640d | 662 | adapter->hw_write_wx(adapter, off, &buf[i].data, 4); |
3d396eb1 | 663 | |
27c915a4 | 664 | msleep(init_delay); |
2956640d DP |
665 | } |
666 | kfree(buf); | |
3d396eb1 | 667 | |
2956640d | 668 | /* disable_peg_cache_all */ |
3d396eb1 | 669 | |
2956640d DP |
670 | /* unreset_net_cache */ |
671 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { | |
672 | adapter->hw_read_wx(adapter, | |
673 | NETXEN_ROMUSB_GLB_SW_RESET, &val, 4); | |
3d396eb1 | 674 | netxen_crb_writelit_adapter(adapter, |
2956640d | 675 | NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f)); |
3d396eb1 | 676 | } |
2956640d DP |
677 | |
678 | /* p2dn replyCount */ | |
679 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e); | |
680 | /* disable_peg_cache 0 */ | |
681 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8); | |
682 | /* disable_peg_cache 1 */ | |
683 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8); | |
684 | ||
685 | /* peg_clr_all */ | |
686 | ||
687 | /* peg_clr 0 */ | |
688 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0); | |
689 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0); | |
690 | /* peg_clr 1 */ | |
691 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0); | |
692 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0); | |
693 | /* peg_clr 2 */ | |
694 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0); | |
695 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0); | |
696 | /* peg_clr 3 */ | |
697 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0); | |
698 | netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0); | |
3d396eb1 AK |
699 | return 0; |
700 | } | |
701 | ||
ed25ffa1 AK |
702 | int netxen_initialize_adapter_offload(struct netxen_adapter *adapter) |
703 | { | |
704 | uint64_t addr; | |
705 | uint32_t hi; | |
706 | uint32_t lo; | |
707 | ||
708 | adapter->dummy_dma.addr = | |
7830b22c | 709 | pci_alloc_consistent(adapter->pdev, |
ed25ffa1 AK |
710 | NETXEN_HOST_DUMMY_DMA_SIZE, |
711 | &adapter->dummy_dma.phys_addr); | |
712 | if (adapter->dummy_dma.addr == NULL) { | |
713 | printk("%s: ERROR: Could not allocate dummy DMA memory\n", | |
2956640d | 714 | __func__); |
ed25ffa1 AK |
715 | return -ENOMEM; |
716 | } | |
717 | ||
718 | addr = (uint64_t) adapter->dummy_dma.phys_addr; | |
719 | hi = (addr >> 32) & 0xffffffff; | |
720 | lo = addr & 0xffffffff; | |
721 | ||
3ce06a32 DP |
722 | adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi); |
723 | adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo); | |
ed25ffa1 | 724 | |
2956640d DP |
725 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
726 | uint32_t temp = 0; | |
727 | adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4); | |
728 | } | |
729 | ||
ed25ffa1 AK |
730 | return 0; |
731 | } | |
732 | ||
733 | void netxen_free_adapter_offload(struct netxen_adapter *adapter) | |
734 | { | |
15eef1e1 DP |
735 | int i = 100; |
736 | ||
737 | if (!adapter->dummy_dma.addr) | |
738 | return; | |
439b454e | 739 | |
15eef1e1 | 740 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
439b454e DP |
741 | do { |
742 | if (dma_watchdog_shutdown_request(adapter) == 1) | |
743 | break; | |
744 | msleep(50); | |
745 | if (dma_watchdog_shutdown_poll_result(adapter) == 1) | |
746 | break; | |
747 | } while (--i); | |
15eef1e1 | 748 | } |
439b454e | 749 | |
15eef1e1 DP |
750 | if (i) { |
751 | pci_free_consistent(adapter->pdev, | |
752 | NETXEN_HOST_DUMMY_DMA_SIZE, | |
753 | adapter->dummy_dma.addr, | |
754 | adapter->dummy_dma.phys_addr); | |
755 | adapter->dummy_dma.addr = NULL; | |
756 | } else { | |
757 | printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n", | |
758 | adapter->netdev->name); | |
ed25ffa1 AK |
759 | } |
760 | } | |
761 | ||
96acb6eb | 762 | int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val) |
3d396eb1 AK |
763 | { |
764 | u32 val = 0; | |
2956640d | 765 | int retries = 60; |
3d396eb1 | 766 | |
cb8011ad | 767 | if (!pegtune_val) { |
96acb6eb | 768 | do { |
3ce06a32 DP |
769 | val = adapter->pci_read_normalize(adapter, |
770 | CRB_CMDPEG_STATE); | |
96acb6eb DP |
771 | |
772 | if (val == PHAN_INITIALIZE_COMPLETE || | |
773 | val == PHAN_INITIALIZE_ACK) | |
774 | return 0; | |
775 | ||
2956640d DP |
776 | msleep(500); |
777 | ||
96acb6eb | 778 | } while (--retries); |
2956640d | 779 | |
96acb6eb | 780 | if (!retries) { |
2956640d DP |
781 | pegtune_val = adapter->pci_read_normalize(adapter, |
782 | NETXEN_ROMUSB_GLB_PEGTUNE_DONE); | |
96acb6eb DP |
783 | printk(KERN_WARNING "netxen_phantom_init: init failed, " |
784 | "pegtune_val=%x\n", pegtune_val); | |
785 | return -1; | |
3d396eb1 | 786 | } |
3d396eb1 | 787 | } |
96acb6eb DP |
788 | |
789 | return 0; | |
3d396eb1 AK |
790 | } |
791 | ||
2956640d DP |
792 | int netxen_receive_peg_ready(struct netxen_adapter *adapter) |
793 | { | |
794 | u32 val = 0; | |
795 | int retries = 2000; | |
796 | ||
797 | do { | |
798 | val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE); | |
799 | ||
800 | if (val == PHAN_PEG_RCV_INITIALIZED) | |
801 | return 0; | |
802 | ||
803 | msleep(10); | |
804 | ||
805 | } while (--retries); | |
806 | ||
807 | if (!retries) { | |
808 | printk(KERN_ERR "Receive Peg initialization not " | |
809 | "complete, state: 0x%x.\n", val); | |
810 | return -EIO; | |
811 | } | |
812 | ||
813 | return 0; | |
814 | } | |
815 | ||
d8b100c5 DP |
816 | static int |
817 | netxen_alloc_rx_skb(struct netxen_adapter *adapter, | |
818 | struct nx_host_rds_ring *rds_ring, | |
819 | struct netxen_rx_buffer *buffer) | |
820 | { | |
821 | struct sk_buff *skb; | |
822 | dma_addr_t dma; | |
823 | struct pci_dev *pdev = adapter->pdev; | |
824 | ||
825 | buffer->skb = dev_alloc_skb(rds_ring->skb_size); | |
826 | if (!buffer->skb) | |
827 | return 1; | |
828 | ||
829 | skb = buffer->skb; | |
830 | ||
831 | if (!adapter->ahw.cut_through) | |
832 | skb_reserve(skb, 2); | |
833 | ||
834 | dma = pci_map_single(pdev, skb->data, | |
835 | rds_ring->dma_size, PCI_DMA_FROMDEVICE); | |
836 | ||
837 | if (pci_dma_mapping_error(pdev, dma)) { | |
838 | dev_kfree_skb_any(skb); | |
839 | buffer->skb = NULL; | |
840 | return 1; | |
841 | } | |
842 | ||
843 | buffer->skb = skb; | |
844 | buffer->dma = dma; | |
845 | buffer->state = NETXEN_BUFFER_BUSY; | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
d9e651bc DP |
850 | static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter, |
851 | struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum) | |
852 | { | |
853 | struct netxen_rx_buffer *buffer; | |
854 | struct sk_buff *skb; | |
855 | ||
856 | buffer = &rds_ring->rx_buf_arr[index]; | |
857 | ||
858 | pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size, | |
859 | PCI_DMA_FROMDEVICE); | |
860 | ||
861 | skb = buffer->skb; | |
862 | if (!skb) | |
863 | goto no_skb; | |
864 | ||
865 | if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) { | |
866 | adapter->stats.csummed++; | |
867 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
868 | } else | |
869 | skb->ip_summed = CHECKSUM_NONE; | |
870 | ||
871 | skb->dev = adapter->netdev; | |
872 | ||
873 | buffer->skb = NULL; | |
d9e651bc DP |
874 | no_skb: |
875 | buffer->state = NETXEN_BUFFER_FREE; | |
d9e651bc DP |
876 | return skb; |
877 | } | |
878 | ||
d8b100c5 | 879 | static struct netxen_rx_buffer * |
9b3ef55c DP |
880 | netxen_process_rcv(struct netxen_adapter *adapter, |
881 | int ring, int index, int length, int cksum, int pkt_offset) | |
3d396eb1 | 882 | { |
3176ff3e | 883 | struct net_device *netdev = adapter->netdev; |
becf46a0 | 884 | struct netxen_recv_context *recv_ctx = &adapter->recv_ctx; |
3d396eb1 AK |
885 | struct netxen_rx_buffer *buffer; |
886 | struct sk_buff *skb; | |
9b3ef55c | 887 | struct nx_host_rds_ring *rds_ring = &recv_ctx->rds_rings[ring]; |
3d396eb1 | 888 | |
438627c7 | 889 | if (unlikely(index > rds_ring->num_desc)) |
d8b100c5 | 890 | return NULL; |
438627c7 | 891 | |
48bfd1e0 | 892 | buffer = &rds_ring->rx_buf_arr[index]; |
3d396eb1 | 893 | |
d9e651bc DP |
894 | skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum); |
895 | if (!skb) | |
d8b100c5 | 896 | return buffer; |
200eef20 | 897 | |
9b3ef55c DP |
898 | if (length > rds_ring->skb_size) |
899 | skb_put(skb, rds_ring->skb_size); | |
900 | else | |
901 | skb_put(skb, length); | |
d9e651bc | 902 | |
9b3ef55c DP |
903 | |
904 | if (pkt_offset) | |
905 | skb_pull(skb, pkt_offset); | |
ed25ffa1 | 906 | |
3d396eb1 AK |
907 | skb->protocol = eth_type_trans(skb, netdev); |
908 | ||
0ddc110c | 909 | netif_receive_skb(skb); |
d9e651bc | 910 | |
0ddc110c DP |
911 | adapter->stats.no_rcv++; |
912 | adapter->stats.rxbytes += length; | |
d8b100c5 DP |
913 | |
914 | return buffer; | |
3d396eb1 AK |
915 | } |
916 | ||
d8b100c5 DP |
917 | #define netxen_merge_rx_buffers(list, head) \ |
918 | do { list_splice_tail_init(list, head); } while (0); | |
919 | ||
becf46a0 | 920 | int |
d8b100c5 | 921 | netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max) |
3d396eb1 | 922 | { |
d8b100c5 DP |
923 | struct netxen_adapter *adapter = sds_ring->adapter; |
924 | ||
925 | struct list_head *cur; | |
926 | ||
0ddc110c | 927 | struct status_desc *desc; |
d8b100c5 DP |
928 | struct netxen_rx_buffer *rxbuf; |
929 | ||
930 | u32 consumer = sds_ring->consumer; | |
931 | ||
9b3ef55c | 932 | int count = 0; |
d9e651bc | 933 | u64 sts_data; |
9b3ef55c | 934 | int opcode, ring, index, length, cksum, pkt_offset; |
3d396eb1 | 935 | |
3d396eb1 | 936 | while (count < max) { |
d8b100c5 | 937 | desc = &sds_ring->desc_head[consumer]; |
0ddc110c DP |
938 | sts_data = le64_to_cpu(desc->status_desc_data); |
939 | ||
940 | if (!(sts_data & STATUS_OWNER_HOST)) | |
3d396eb1 | 941 | break; |
d9e651bc | 942 | |
9b3ef55c DP |
943 | ring = netxen_get_sts_type(sts_data); |
944 | if (ring > RCV_RING_JUMBO) | |
945 | continue; | |
946 | ||
d9e651bc | 947 | opcode = netxen_get_sts_opcode(sts_data); |
d9e651bc | 948 | |
9b3ef55c DP |
949 | index = netxen_get_sts_refhandle(sts_data); |
950 | length = netxen_get_sts_totallength(sts_data); | |
951 | cksum = netxen_get_sts_status(sts_data); | |
952 | pkt_offset = netxen_get_sts_pkt_offset(sts_data); | |
953 | ||
d8b100c5 | 954 | rxbuf = netxen_process_rcv(adapter, ring, index, |
9b3ef55c | 955 | length, cksum, pkt_offset); |
d9e651bc | 956 | |
d8b100c5 DP |
957 | if (rxbuf) |
958 | list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]); | |
959 | ||
0ddc110c | 960 | desc->status_desc_data = cpu_to_le64(STATUS_OWNER_PHANTOM); |
d9e651bc | 961 | |
d8b100c5 | 962 | consumer = get_next_index(consumer, sds_ring->num_desc); |
3d396eb1 AK |
963 | count++; |
964 | } | |
0ddc110c | 965 | |
d8b100c5 DP |
966 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { |
967 | struct nx_host_rds_ring *rds_ring = | |
968 | &adapter->recv_ctx.rds_rings[ring]; | |
969 | ||
970 | if (!list_empty(&sds_ring->free_list[ring])) { | |
971 | list_for_each(cur, &sds_ring->free_list[ring]) { | |
972 | rxbuf = list_entry(cur, | |
973 | struct netxen_rx_buffer, list); | |
974 | netxen_alloc_rx_skb(adapter, rds_ring, rxbuf); | |
975 | } | |
976 | spin_lock(&rds_ring->lock); | |
977 | netxen_merge_rx_buffers(&sds_ring->free_list[ring], | |
978 | &rds_ring->free_list); | |
979 | spin_unlock(&rds_ring->lock); | |
980 | } | |
981 | ||
982 | netxen_post_rx_buffers_nodb(adapter, rds_ring); | |
983 | } | |
3d396eb1 | 984 | |
3d396eb1 | 985 | if (count) { |
d8b100c5 | 986 | sds_ring->consumer = consumer; |
3ce06a32 | 987 | adapter->pci_write_normalize(adapter, |
d8b100c5 | 988 | sds_ring->crb_sts_consumer, consumer); |
3d396eb1 AK |
989 | } |
990 | ||
991 | return count; | |
992 | } | |
993 | ||
994 | /* Process Command status ring */ | |
05aaa02d | 995 | int netxen_process_cmd_ring(struct netxen_adapter *adapter) |
3d396eb1 | 996 | { |
d877f1e3 | 997 | u32 sw_consumer, hw_consumer; |
ba53e6b4 | 998 | int count = 0, i; |
3d396eb1 | 999 | struct netxen_cmd_buffer *buffer; |
ba53e6b4 DP |
1000 | struct pci_dev *pdev = adapter->pdev; |
1001 | struct net_device *netdev = adapter->netdev; | |
3d396eb1 | 1002 | struct netxen_skb_frag *frag; |
ba53e6b4 | 1003 | int done = 0; |
d877f1e3 | 1004 | struct nx_host_tx_ring *tx_ring = &adapter->tx_ring; |
3d396eb1 | 1005 | |
d8b100c5 DP |
1006 | if (!spin_trylock(&adapter->tx_clean_lock)) |
1007 | return 1; | |
1008 | ||
d877f1e3 DP |
1009 | sw_consumer = tx_ring->sw_consumer; |
1010 | barrier(); /* hw_consumer can change underneath */ | |
1011 | hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer)); | |
3d396eb1 | 1012 | |
d877f1e3 DP |
1013 | while (sw_consumer != hw_consumer) { |
1014 | buffer = &tx_ring->cmd_buf_arr[sw_consumer]; | |
53a01e00 | 1015 | if (buffer->skb) { |
1016 | frag = &buffer->frag_array[0]; | |
3d396eb1 AK |
1017 | pci_unmap_single(pdev, frag->dma, frag->length, |
1018 | PCI_DMA_TODEVICE); | |
96acb6eb | 1019 | frag->dma = 0ULL; |
3d396eb1 | 1020 | for (i = 1; i < buffer->frag_count; i++) { |
3d396eb1 AK |
1021 | frag++; /* Get the next frag */ |
1022 | pci_unmap_page(pdev, frag->dma, frag->length, | |
1023 | PCI_DMA_TODEVICE); | |
96acb6eb | 1024 | frag->dma = 0ULL; |
3d396eb1 AK |
1025 | } |
1026 | ||
ba53e6b4 | 1027 | adapter->stats.xmitfinished++; |
53a01e00 | 1028 | dev_kfree_skb_any(buffer->skb); |
1029 | buffer->skb = NULL; | |
3d396eb1 AK |
1030 | } |
1031 | ||
d877f1e3 | 1032 | sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc); |
ba53e6b4 DP |
1033 | if (++count >= MAX_STATUS_HANDLE) |
1034 | break; | |
3d396eb1 | 1035 | } |
3d396eb1 | 1036 | |
ba53e6b4 | 1037 | if (count) { |
d877f1e3 | 1038 | tx_ring->sw_consumer = sw_consumer; |
ba53e6b4 DP |
1039 | smp_mb(); |
1040 | if (netif_queue_stopped(netdev) && netif_running(netdev)) { | |
1041 | netif_tx_lock(netdev); | |
1042 | netif_wake_queue(netdev); | |
1043 | smp_mb(); | |
1044 | netif_tx_unlock(netdev); | |
3d396eb1 AK |
1045 | } |
1046 | } | |
ed25ffa1 AK |
1047 | /* |
1048 | * If everything is freed up to consumer then check if the ring is full | |
1049 | * If the ring is full then check if more needs to be freed and | |
1050 | * schedule the call back again. | |
1051 | * | |
1052 | * This happens when there are 2 CPUs. One could be freeing and the | |
1053 | * other filling it. If the ring is full when we get out of here and | |
1054 | * the card has already interrupted the host then the host can miss the | |
1055 | * interrupt. | |
1056 | * | |
1057 | * There is still a possible race condition and the host could miss an | |
1058 | * interrupt. The card has to take care of this. | |
1059 | */ | |
d877f1e3 DP |
1060 | barrier(); /* hw_consumer can change underneath */ |
1061 | hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer)); | |
1062 | done = (sw_consumer == hw_consumer); | |
d8b100c5 | 1063 | spin_unlock(&adapter->tx_clean_lock); |
3d396eb1 | 1064 | |
ed25ffa1 | 1065 | return (done); |
3d396eb1 AK |
1066 | } |
1067 | ||
becf46a0 | 1068 | void |
d8b100c5 DP |
1069 | netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid, |
1070 | struct nx_host_rds_ring *rds_ring) | |
3d396eb1 | 1071 | { |
3d396eb1 AK |
1072 | struct rcv_desc *pdesc; |
1073 | struct netxen_rx_buffer *buffer; | |
d8b100c5 | 1074 | int producer, count = 0; |
ed25ffa1 | 1075 | netxen_ctx_msg msg = 0; |
d9e651bc | 1076 | struct list_head *head; |
3d396eb1 | 1077 | |
48bfd1e0 | 1078 | producer = rds_ring->producer; |
d9e651bc | 1079 | |
d8b100c5 DP |
1080 | spin_lock(&rds_ring->lock); |
1081 | head = &rds_ring->free_list; | |
d9e651bc DP |
1082 | while (!list_empty(head)) { |
1083 | ||
d8b100c5 | 1084 | buffer = list_entry(head->next, struct netxen_rx_buffer, list); |
6f703406 | 1085 | |
d8b100c5 DP |
1086 | if (!buffer->skb) { |
1087 | if (netxen_alloc_rx_skb(adapter, rds_ring, buffer)) | |
1088 | break; | |
6f703406 DP |
1089 | } |
1090 | ||
1091 | count++; | |
d9e651bc DP |
1092 | list_del(&buffer->list); |
1093 | ||
ed25ffa1 | 1094 | /* make a rcv descriptor */ |
6f703406 | 1095 | pdesc = &rds_ring->desc_head[producer]; |
d8b100c5 | 1096 | pdesc->addr_buffer = cpu_to_le64(buffer->dma); |
ed33ebe4 | 1097 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
48bfd1e0 | 1098 | pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); |
6f703406 | 1099 | |
438627c7 | 1100 | producer = get_next_index(producer, rds_ring->num_desc); |
ed25ffa1 | 1101 | } |
d8b100c5 | 1102 | spin_unlock(&rds_ring->lock); |
9b3ef55c | 1103 | |
ed25ffa1 | 1104 | if (count) { |
48bfd1e0 | 1105 | rds_ring->producer = producer; |
3ce06a32 | 1106 | adapter->pci_write_normalize(adapter, |
48bfd1e0 | 1107 | rds_ring->crb_rcv_producer, |
438627c7 | 1108 | (producer-1) & (rds_ring->num_desc-1)); |
48bfd1e0 DP |
1109 | |
1110 | if (adapter->fw_major < 4) { | |
ed25ffa1 AK |
1111 | /* |
1112 | * Write a doorbell msg to tell phanmon of change in | |
1113 | * receive ring producer | |
48bfd1e0 | 1114 | * Only for firmware version < 4.0.0 |
ed25ffa1 AK |
1115 | */ |
1116 | netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID); | |
1117 | netxen_set_msg_privid(msg); | |
1118 | netxen_set_msg_count(msg, | |
438627c7 DP |
1119 | ((producer - 1) & |
1120 | (rds_ring->num_desc - 1))); | |
3176ff3e | 1121 | netxen_set_msg_ctxid(msg, adapter->portnum); |
ed25ffa1 AK |
1122 | netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid)); |
1123 | writel(msg, | |
1124 | DB_NORMALIZE(adapter, | |
1125 | NETXEN_RCV_PRODUCER_OFFSET)); | |
48bfd1e0 | 1126 | } |
ed25ffa1 AK |
1127 | } |
1128 | } | |
1129 | ||
becf46a0 | 1130 | static void |
d8b100c5 DP |
1131 | netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, |
1132 | struct nx_host_rds_ring *rds_ring) | |
ed25ffa1 | 1133 | { |
ed25ffa1 AK |
1134 | struct rcv_desc *pdesc; |
1135 | struct netxen_rx_buffer *buffer; | |
d8b100c5 | 1136 | int producer, count = 0; |
d9e651bc | 1137 | struct list_head *head; |
ed25ffa1 | 1138 | |
48bfd1e0 | 1139 | producer = rds_ring->producer; |
d8b100c5 DP |
1140 | if (!spin_trylock(&rds_ring->lock)) |
1141 | return; | |
1142 | ||
d9e651bc | 1143 | head = &rds_ring->free_list; |
d9e651bc DP |
1144 | while (!list_empty(head)) { |
1145 | ||
d8b100c5 | 1146 | buffer = list_entry(head->next, struct netxen_rx_buffer, list); |
6f703406 | 1147 | |
d8b100c5 DP |
1148 | if (!buffer->skb) { |
1149 | if (netxen_alloc_rx_skb(adapter, rds_ring, buffer)) | |
1150 | break; | |
6f703406 DP |
1151 | } |
1152 | ||
1153 | count++; | |
d9e651bc DP |
1154 | list_del(&buffer->list); |
1155 | ||
3d396eb1 | 1156 | /* make a rcv descriptor */ |
6f703406 | 1157 | pdesc = &rds_ring->desc_head[producer]; |
ed33ebe4 | 1158 | pdesc->reference_handle = cpu_to_le16(buffer->ref_handle); |
48bfd1e0 | 1159 | pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size); |
3d396eb1 | 1160 | pdesc->addr_buffer = cpu_to_le64(buffer->dma); |
6f703406 | 1161 | |
438627c7 | 1162 | producer = get_next_index(producer, rds_ring->num_desc); |
3d396eb1 AK |
1163 | } |
1164 | ||
3d396eb1 | 1165 | if (count) { |
48bfd1e0 | 1166 | rds_ring->producer = producer; |
3ce06a32 | 1167 | adapter->pci_write_normalize(adapter, |
48bfd1e0 | 1168 | rds_ring->crb_rcv_producer, |
438627c7 | 1169 | (producer - 1) & (rds_ring->num_desc - 1)); |
3d396eb1 | 1170 | wmb(); |
3d396eb1 | 1171 | } |
d8b100c5 | 1172 | spin_unlock(&rds_ring->lock); |
3d396eb1 AK |
1173 | } |
1174 | ||
3d396eb1 AK |
1175 | void netxen_nic_clear_stats(struct netxen_adapter *adapter) |
1176 | { | |
3d396eb1 | 1177 | memset(&adapter->stats, 0, sizeof(adapter->stats)); |
3176ff3e | 1178 | return; |
3d396eb1 AK |
1179 | } |
1180 |