projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
s2io: fix warning in drivers/net/s2io.c
[deliverable/linux.git] / drivers / net / niu.c
CommitLineData
a3138df9
DM		 1/* niu.c: Neptune ethernet driver.
2 *
be0c007a 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
a3138df9
DM		 4 */
5
6#include <linux/module.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/dma-mapping.h>
10#include <linux/netdevice.h>
11#include <linux/ethtool.h>
12#include <linux/etherdevice.h>
13#include <linux/platform_device.h>
14#include <linux/delay.h>
15#include <linux/bitops.h>
16#include <linux/mii.h>
17#include <linux/if_ether.h>
18#include <linux/if_vlan.h>
19#include <linux/ip.h>
20#include <linux/in.h>
21#include <linux/ipv6.h>
22#include <linux/log2.h>
23#include <linux/jiffies.h>
24#include <linux/crc32.h>
25
26#include <linux/io.h>
27
28#ifdef CONFIG_SPARC64
29#include <linux/of_device.h>
30#endif
31
32#include "niu.h"
33
34#define DRV_MODULE_NAME "niu"
35#define PFX DRV_MODULE_NAME ": "
d8c3e23d
DM		 36#define DRV_MODULE_VERSION "1.0"
37#define DRV_MODULE_RELDATE "Nov 14, 2008"
a3138df9
DM		 38
39static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43MODULE_DESCRIPTION("NIU ethernet driver");
44MODULE_LICENSE("GPL");
45MODULE_VERSION(DRV_MODULE_VERSION);
46
47#ifndef DMA_44BIT_MASK
48#define DMA_44BIT_MASK 0x00000fffffffffffULL
49#endif
50
51#ifndef readq
52static u64 readq(void __iomem *reg)
53{
e23a59e1 54 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
a3138df9
DM		 55}
56
57static void writeq(u64 val, void __iomem *reg)
58{
59 writel(val & 0xffffffff, reg);
60 writel(val >> 32, reg + 0x4UL);
61}
62#endif
63
64static struct pci_device_id niu_pci_tbl[] = {
65 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
66 {}
67};
68
69MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
70
71#define NIU_TX_TIMEOUT (5 * HZ)
72
73#define nr64(reg) readq(np->regs + (reg))
74#define nw64(reg, val) writeq((val), np->regs + (reg))
75
76#define nr64_mac(reg) readq(np->mac_regs + (reg))
77#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
78
79#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
80#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
81
82#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
83#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
84
85#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
86#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
87
88#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
89
90static int niu_debug;
91static int debug = -1;
92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "NIU debug level");
94
95#define niudbg(TYPE, f, a...) \
96do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
97 printk(KERN_DEBUG PFX f, ## a); \
98} while (0)
99
100#define niuinfo(TYPE, f, a...) \
101do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
102 printk(KERN_INFO PFX f, ## a); \
103} while (0)
104
105#define niuwarn(TYPE, f, a...) \
106do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
107 printk(KERN_WARNING PFX f, ## a); \
108} while (0)
109
110#define niu_lock_parent(np, flags) \
111 spin_lock_irqsave(&np->parent->lock, flags)
112#define niu_unlock_parent(np, flags) \
113 spin_unlock_irqrestore(&np->parent->lock, flags)
114
5fbd7e24
MW		 115static int serdes_init_10g_serdes(struct niu *np);
116
a3138df9
DM		 117static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
118 u64 bits, int limit, int delay)
119{
120 while (--limit >= 0) {
121 u64 val = nr64_mac(reg);
122
123 if (!(val & bits))
124 break;
125 udelay(delay);
126 }
127 if (limit < 0)
128 return -ENODEV;
129 return 0;
130}
131
132static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
133 u64 bits, int limit, int delay,
134 const char *reg_name)
135{
136 int err;
137
138 nw64_mac(reg, bits);
139 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
140 if (err)
141 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
142 "would not clear, val[%llx]\n",
143 np->dev->name, (unsigned long long) bits, reg_name,
144 (unsigned long long) nr64_mac(reg));
145 return err;
146}
147
148#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
149({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
150 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
151})
152
153static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
154 u64 bits, int limit, int delay)
155{
156 while (--limit >= 0) {
157 u64 val = nr64_ipp(reg);
158
159 if (!(val & bits))
160 break;
161 udelay(delay);
162 }
163 if (limit < 0)
164 return -ENODEV;
165 return 0;
166}
167
168static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
169 u64 bits, int limit, int delay,
170 const char *reg_name)
171{
172 int err;
173 u64 val;
174
175 val = nr64_ipp(reg);
176 val |= bits;
177 nw64_ipp(reg, val);
178
179 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
180 if (err)
181 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
182 "would not clear, val[%llx]\n",
183 np->dev->name, (unsigned long long) bits, reg_name,
184 (unsigned long long) nr64_ipp(reg));
185 return err;
186}
187
188#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
189({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
190 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
191})
192
193static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
194 u64 bits, int limit, int delay)
195{
196 while (--limit >= 0) {
197 u64 val = nr64(reg);
198
199 if (!(val & bits))
200 break;
201 udelay(delay);
202 }
203 if (limit < 0)
204 return -ENODEV;
205 return 0;
206}
207
208#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
209({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
210 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
211})
212
213static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
214 u64 bits, int limit, int delay,
215 const char *reg_name)
216{
217 int err;
218
219 nw64(reg, bits);
220 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
221 if (err)
222 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
223 "would not clear, val[%llx]\n",
224 np->dev->name, (unsigned long long) bits, reg_name,
225 (unsigned long long) nr64(reg));
226 return err;
227}
228
229#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
230({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
231 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
232})
233
234static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
235{
236 u64 val = (u64) lp->timer;
237
238 if (on)
239 val |= LDG_IMGMT_ARM;
240
241 nw64(LDG_IMGMT(lp->ldg_num), val);
242}
243
244static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
245{
246 unsigned long mask_reg, bits;
247 u64 val;
248
249 if (ldn < 0 || ldn > LDN_MAX)
250 return -EINVAL;
251
252 if (ldn < 64) {
253 mask_reg = LD_IM0(ldn);
254 bits = LD_IM0_MASK;
255 } else {
256 mask_reg = LD_IM1(ldn - 64);
257 bits = LD_IM1_MASK;
258 }
259
260 val = nr64(mask_reg);
261 if (on)
262 val &= ~bits;
263 else
264 val |= bits;
265 nw64(mask_reg, val);
266
267 return 0;
268}
269
270static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
271{
272 struct niu_parent *parent = np->parent;
273 int i;
274
275 for (i = 0; i <= LDN_MAX; i++) {
276 int err;
277
278 if (parent->ldg_map[i] != lp->ldg_num)
279 continue;
280
281 err = niu_ldn_irq_enable(np, i, on);
282 if (err)
283 return err;
284 }
285 return 0;
286}
287
288static int niu_enable_interrupts(struct niu *np, int on)
289{
290 int i;
291
292 for (i = 0; i < np->num_ldg; i++) {
293 struct niu_ldg *lp = &np->ldg[i];
294 int err;
295
296 err = niu_enable_ldn_in_ldg(np, lp, on);
297 if (err)
298 return err;
299 }
300 for (i = 0; i < np->num_ldg; i++)
301 niu_ldg_rearm(np, &np->ldg[i], on);
302
303 return 0;
304}
305
306static u32 phy_encode(u32 type, int port)
307{
308 return (type << (port * 2));
309}
310
311static u32 phy_decode(u32 val, int port)
312{
313 return (val >> (port * 2)) & PORT_TYPE_MASK;
314}
315
316static int mdio_wait(struct niu *np)
317{
318 int limit = 1000;
319 u64 val;
320
321 while (--limit > 0) {
322 val = nr64(MIF_FRAME_OUTPUT);
323 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
324 return val & MIF_FRAME_OUTPUT_DATA;
325
326 udelay(10);
327 }
328
329 return -ENODEV;
330}
331
332static int mdio_read(struct niu *np, int port, int dev, int reg)
333{
334 int err;
335
336 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
337 err = mdio_wait(np);
338 if (err < 0)
339 return err;
340
341 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
342 return mdio_wait(np);
343}
344
345static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
346{
347 int err;
348
349 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
350 err = mdio_wait(np);
351 if (err < 0)
352 return err;
353
354 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
355 err = mdio_wait(np);
356 if (err < 0)
357 return err;
358
359 return 0;
360}
361
362static int mii_read(struct niu *np, int port, int reg)
363{
364 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
365 return mdio_wait(np);
366}
367
368static int mii_write(struct niu *np, int port, int reg, int data)
369{
370 int err;
371
372 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
373 err = mdio_wait(np);
374 if (err < 0)
375 return err;
376
377 return 0;
378}
379
380static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
381{
382 int err;
383
384 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
385 ESR2_TI_PLL_TX_CFG_L(channel),
386 val & 0xffff);
387 if (!err)
388 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
389 ESR2_TI_PLL_TX_CFG_H(channel),
390 val >> 16);
391 return err;
392}
393
394static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
395{
396 int err;
397
398 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
399 ESR2_TI_PLL_RX_CFG_L(channel),
400 val & 0xffff);
401 if (!err)
402 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
403 ESR2_TI_PLL_RX_CFG_H(channel),
404 val >> 16);
405 return err;
406}
407
408/* Mode is always 10G fiber. */
e3e081e1 409static int serdes_init_niu_10g_fiber(struct niu *np)
a3138df9
DM		 410{
411 struct niu_link_config *lp = &np->link_config;
412 u32 tx_cfg, rx_cfg;
413 unsigned long i;
414
415 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
416 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
417 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
418 PLL_RX_CFG_EQ_LP_ADAPTIVE);
419
420 if (lp->loopback_mode == LOOPBACK_PHY) {
421 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
422
423 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
424 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
425
426 tx_cfg |= PLL_TX_CFG_ENTEST;
427 rx_cfg |= PLL_RX_CFG_ENTEST;
428 }
429
430 /* Initialize all 4 lanes of the SERDES. */
431 for (i = 0; i < 4; i++) {
432 int err = esr2_set_tx_cfg(np, i, tx_cfg);
433 if (err)
434 return err;
435 }
436
437 for (i = 0; i < 4; i++) {
438 int err = esr2_set_rx_cfg(np, i, rx_cfg);
439 if (err)
440 return err;
441 }
442
443 return 0;
444}
445
e3e081e1
SB		 446static int serdes_init_niu_1g_serdes(struct niu *np)
447{
448 struct niu_link_config *lp = &np->link_config;
449 u16 pll_cfg, pll_sts;
450 int max_retry = 100;
451 u64 sig, mask, val;
452 u32 tx_cfg, rx_cfg;
453 unsigned long i;
454 int err;
455
456 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
457 PLL_TX_CFG_RATE_HALF);
458 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
459 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
460 PLL_RX_CFG_RATE_HALF);
461
462 if (np->port == 0)
463 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
464
465 if (lp->loopback_mode == LOOPBACK_PHY) {
466 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
467
468 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
469 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
470
471 tx_cfg |= PLL_TX_CFG_ENTEST;
472 rx_cfg |= PLL_RX_CFG_ENTEST;
473 }
474
475 /* Initialize PLL for 1G */
476 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
477
478 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
479 ESR2_TI_PLL_CFG_L, pll_cfg);
480 if (err) {
481 dev_err(np->device, PFX "NIU Port %d "
482 "serdes_init_niu_1g_serdes: "
483 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
484 return err;
485 }
486
487 pll_sts = PLL_CFG_ENPLL;
488
489 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
490 ESR2_TI_PLL_STS_L, pll_sts);
491 if (err) {
492 dev_err(np->device, PFX "NIU Port %d "
493 "serdes_init_niu_1g_serdes: "
494 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
495 return err;
496 }
497
498 udelay(200);
499
500 /* Initialize all 4 lanes of the SERDES. */
501 for (i = 0; i < 4; i++) {
502 err = esr2_set_tx_cfg(np, i, tx_cfg);
503 if (err)
504 return err;
505 }
506
507 for (i = 0; i < 4; i++) {
508 err = esr2_set_rx_cfg(np, i, rx_cfg);
509 if (err)
510 return err;
511 }
512
513 switch (np->port) {
514 case 0:
515 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
516 mask = val;
517 break;
518
519 case 1:
520 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
521 mask = val;
522 break;
523
524 default:
525 return -EINVAL;
526 }
527
528 while (max_retry--) {
529 sig = nr64(ESR_INT_SIGNALS);
530 if ((sig & mask) == val)
531 break;
532
533 mdelay(500);
534 }
535
536 if ((sig & mask) != val) {
537 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
538 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
539 return -ENODEV;
540 }
541
542 return 0;
543}
544
545static int serdes_init_niu_10g_serdes(struct niu *np)
546{
547 struct niu_link_config *lp = &np->link_config;
548 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
549 int max_retry = 100;
550 u64 sig, mask, val;
551 unsigned long i;
552 int err;
553
554 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
555 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
556 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
557 PLL_RX_CFG_EQ_LP_ADAPTIVE);
558
559 if (lp->loopback_mode == LOOPBACK_PHY) {
560 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
561
562 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
563 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
564
565 tx_cfg |= PLL_TX_CFG_ENTEST;
566 rx_cfg |= PLL_RX_CFG_ENTEST;
567 }
568
569 /* Initialize PLL for 10G */
570 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
571
572 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
573 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
574 if (err) {
575 dev_err(np->device, PFX "NIU Port %d "
576 "serdes_init_niu_10g_serdes: "
577 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
578 return err;
579 }
580
581 pll_sts = PLL_CFG_ENPLL;
582
583 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
584 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
585 if (err) {
586 dev_err(np->device, PFX "NIU Port %d "
587 "serdes_init_niu_10g_serdes: "
588 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
589 return err;
590 }
591
592 udelay(200);
593
594 /* Initialize all 4 lanes of the SERDES. */
595 for (i = 0; i < 4; i++) {
596 err = esr2_set_tx_cfg(np, i, tx_cfg);
597 if (err)
598 return err;
599 }
600
601 for (i = 0; i < 4; i++) {
602 err = esr2_set_rx_cfg(np, i, rx_cfg);
603 if (err)
604 return err;
605 }
606
607 /* check if serdes is ready */
608
609 switch (np->port) {
610 case 0:
611 mask = ESR_INT_SIGNALS_P0_BITS;
612 val = (ESR_INT_SRDY0_P0 |
613 ESR_INT_DET0_P0 |
614 ESR_INT_XSRDY_P0 |
615 ESR_INT_XDP_P0_CH3 |
616 ESR_INT_XDP_P0_CH2 |
617 ESR_INT_XDP_P0_CH1 |
618 ESR_INT_XDP_P0_CH0);
619 break;
620
621 case 1:
622 mask = ESR_INT_SIGNALS_P1_BITS;
623 val = (ESR_INT_SRDY0_P1 |
624 ESR_INT_DET0_P1 |
625 ESR_INT_XSRDY_P1 |
626 ESR_INT_XDP_P1_CH3 |
627 ESR_INT_XDP_P1_CH2 |
628 ESR_INT_XDP_P1_CH1 |
629 ESR_INT_XDP_P1_CH0);
630 break;
631
632 default:
633 return -EINVAL;
634 }
635
636 while (max_retry--) {
637 sig = nr64(ESR_INT_SIGNALS);
638 if ((sig & mask) == val)
639 break;
640
641 mdelay(500);
642 }
643
644 if ((sig & mask) != val) {
645 pr_info(PFX "NIU Port %u signal bits [%08x] are not "
646 "[%08x] for 10G...trying 1G\n",
647 np->port, (int) (sig & mask), (int) val);
648
649 /* 10G failed, try initializing at 1G */
650 err = serdes_init_niu_1g_serdes(np);
651 if (!err) {
652 np->flags &= ~NIU_FLAGS_10G;
653 np->mac_xcvr = MAC_XCVR_PCS;
654 } else {
655 dev_err(np->device, PFX "Port %u 10G/1G SERDES "
656 "Link Failed \n", np->port);
657 return -ENODEV;
658 }
659 }
660 return 0;
661}
662
a3138df9
DM		 663static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
664{
665 int err;
666
667 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
668 if (err >= 0) {
669 *val = (err & 0xffff);
670 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
671 ESR_RXTX_CTRL_H(chan));
672 if (err >= 0)
673 *val |= ((err & 0xffff) << 16);
674 err = 0;
675 }
676 return err;
677}
678
679static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
680{
681 int err;
682
683 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
684 ESR_GLUE_CTRL0_L(chan));
685 if (err >= 0) {
686 *val = (err & 0xffff);
687 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
688 ESR_GLUE_CTRL0_H(chan));
689 if (err >= 0) {
690 *val |= ((err & 0xffff) << 16);
691 err = 0;
692 }
693 }
694 return err;
695}
696
697static int esr_read_reset(struct niu *np, u32 *val)
698{
699 int err;
700
701 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
702 ESR_RXTX_RESET_CTRL_L);
703 if (err >= 0) {
704 *val = (err & 0xffff);
705 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
706 ESR_RXTX_RESET_CTRL_H);
707 if (err >= 0) {
708 *val |= ((err & 0xffff) << 16);
709 err = 0;
710 }
711 }
712 return err;
713}
714
715static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
716{
717 int err;
718
719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720 ESR_RXTX_CTRL_L(chan), val & 0xffff);
721 if (!err)
722 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
723 ESR_RXTX_CTRL_H(chan), (val >> 16));
724 return err;
725}
726
727static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
728{
729 int err;
730
731 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
732 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
733 if (!err)
734 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
735 ESR_GLUE_CTRL0_H(chan), (val >> 16));
736 return err;
737}
738
739static int esr_reset(struct niu *np)
740{
741 u32 reset;
742 int err;
743
744 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
745 ESR_RXTX_RESET_CTRL_L, 0x0000);
746 if (err)
747 return err;
748 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
749 ESR_RXTX_RESET_CTRL_H, 0xffff);
750 if (err)
751 return err;
752 udelay(200);
753
754 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
755 ESR_RXTX_RESET_CTRL_L, 0xffff);
756 if (err)
757 return err;
758 udelay(200);
759
760 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
761 ESR_RXTX_RESET_CTRL_H, 0x0000);
762 if (err)
763 return err;
764 udelay(200);
765
766 err = esr_read_reset(np, &reset);
767 if (err)
768 return err;
769 if (reset != 0) {
770 dev_err(np->device, PFX "Port %u ESR_RESET "
771 "did not clear [%08x]\n",
772 np->port, reset);
773 return -ENODEV;
774 }
775
776 return 0;
777}
778
779static int serdes_init_10g(struct niu *np)
780{
781 struct niu_link_config *lp = &np->link_config;
782 unsigned long ctrl_reg, test_cfg_reg, i;
783 u64 ctrl_val, test_cfg_val, sig, mask, val;
784 int err;
785
786 switch (np->port) {
787 case 0:
788 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
789 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
790 break;
791 case 1:
792 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
793 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
794 break;
795
796 default:
797 return -EINVAL;
798 }
799 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
800 ENET_SERDES_CTRL_SDET_1 |
801 ENET_SERDES_CTRL_SDET_2 |
802 ENET_SERDES_CTRL_SDET_3 |
803 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
804 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
805 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
806 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
807 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
808 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
809 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
810 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
811 test_cfg_val = 0;
812
813 if (lp->loopback_mode == LOOPBACK_PHY) {
814 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
815 ENET_SERDES_TEST_MD_0_SHIFT) |
816 (ENET_TEST_MD_PAD_LOOPBACK <<
817 ENET_SERDES_TEST_MD_1_SHIFT) |
818 (ENET_TEST_MD_PAD_LOOPBACK <<
819 ENET_SERDES_TEST_MD_2_SHIFT) |
820 (ENET_TEST_MD_PAD_LOOPBACK <<
821 ENET_SERDES_TEST_MD_3_SHIFT));
822 }
823
824 nw64(ctrl_reg, ctrl_val);
825 nw64(test_cfg_reg, test_cfg_val);
826
827 /* Initialize all 4 lanes of the SERDES. */
828 for (i = 0; i < 4; i++) {
829 u32 rxtx_ctrl, glue0;
830
831 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
832 if (err)
833 return err;
834 err = esr_read_glue0(np, i, &glue0);
835 if (err)
836 return err;
837
838 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
839 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
840 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
841
842 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
843 ESR_GLUE_CTRL0_THCNT |
844 ESR_GLUE_CTRL0_BLTIME);
845 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
846 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
847 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
848 (BLTIME_300_CYCLES <<
849 ESR_GLUE_CTRL0_BLTIME_SHIFT));
850
851 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
852 if (err)
853 return err;
854 err = esr_write_glue0(np, i, glue0);
855 if (err)
856 return err;
857 }
858
859 err = esr_reset(np);
860 if (err)
861 return err;
862
863 sig = nr64(ESR_INT_SIGNALS);
864 switch (np->port) {
865 case 0:
866 mask = ESR_INT_SIGNALS_P0_BITS;
867 val = (ESR_INT_SRDY0_P0 |
868 ESR_INT_DET0_P0 |
869 ESR_INT_XSRDY_P0 |
870 ESR_INT_XDP_P0_CH3 |
871 ESR_INT_XDP_P0_CH2 |
872 ESR_INT_XDP_P0_CH1 |
873 ESR_INT_XDP_P0_CH0);
874 break;
875
876 case 1:
877 mask = ESR_INT_SIGNALS_P1_BITS;
878 val = (ESR_INT_SRDY0_P1 |
879 ESR_INT_DET0_P1 |
880 ESR_INT_XSRDY_P1 |
881 ESR_INT_XDP_P1_CH3 |
882 ESR_INT_XDP_P1_CH2 |
883 ESR_INT_XDP_P1_CH1 |
884 ESR_INT_XDP_P1_CH0);
885 break;
886
887 default:
888 return -EINVAL;
889 }
890
891 if ((sig & mask) != val) {
a5d6ab56
MW		 892 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
893 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
894 return 0;
895 }
a3138df9
DM		 896 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
897 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
898 return -ENODEV;
899 }
a5d6ab56
MW		 900 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
901 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
a3138df9
DM		 902 return 0;
903}
904
905static int serdes_init_1g(struct niu *np)
906{
907 u64 val;
908
909 val = nr64(ENET_SERDES_1_PLL_CFG);
910 val &= ~ENET_SERDES_PLL_FBDIV2;
911 switch (np->port) {
912 case 0:
913 val |= ENET_SERDES_PLL_HRATE0;
914 break;
915 case 1:
916 val |= ENET_SERDES_PLL_HRATE1;
917 break;
918 case 2:
919 val |= ENET_SERDES_PLL_HRATE2;
920 break;
921 case 3:
922 val |= ENET_SERDES_PLL_HRATE3;
923 break;
924 default:
925 return -EINVAL;
926 }
927 nw64(ENET_SERDES_1_PLL_CFG, val);
928
929 return 0;
930}
931
5fbd7e24
MW		 932static int serdes_init_1g_serdes(struct niu *np)
933{
934 struct niu_link_config *lp = &np->link_config;
935 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
936 u64 ctrl_val, test_cfg_val, sig, mask, val;
937 int err;
938 u64 reset_val, val_rd;
939
940 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
941 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
942 ENET_SERDES_PLL_FBDIV0;
943 switch (np->port) {
944 case 0:
945 reset_val = ENET_SERDES_RESET_0;
946 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
947 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
948 pll_cfg = ENET_SERDES_0_PLL_CFG;
949 break;
950 case 1:
951 reset_val = ENET_SERDES_RESET_1;
952 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
953 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
954 pll_cfg = ENET_SERDES_1_PLL_CFG;
955 break;
956
957 default:
958 return -EINVAL;
959 }
960 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
961 ENET_SERDES_CTRL_SDET_1 |
962 ENET_SERDES_CTRL_SDET_2 |
963 ENET_SERDES_CTRL_SDET_3 |
964 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
965 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
966 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
967 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
968 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
969 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
970 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
971 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
972 test_cfg_val = 0;
973
974 if (lp->loopback_mode == LOOPBACK_PHY) {
975 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
976 ENET_SERDES_TEST_MD_0_SHIFT) |
977 (ENET_TEST_MD_PAD_LOOPBACK <<
978 ENET_SERDES_TEST_MD_1_SHIFT) |
979 (ENET_TEST_MD_PAD_LOOPBACK <<
980 ENET_SERDES_TEST_MD_2_SHIFT) |
981 (ENET_TEST_MD_PAD_LOOPBACK <<
982 ENET_SERDES_TEST_MD_3_SHIFT));
983 }
984
985 nw64(ENET_SERDES_RESET, reset_val);
986 mdelay(20);
987 val_rd = nr64(ENET_SERDES_RESET);
988 val_rd &= ~reset_val;
989 nw64(pll_cfg, val);
990 nw64(ctrl_reg, ctrl_val);
991 nw64(test_cfg_reg, test_cfg_val);
992 nw64(ENET_SERDES_RESET, val_rd);
993 mdelay(2000);
994
995 /* Initialize all 4 lanes of the SERDES. */
996 for (i = 0; i < 4; i++) {
997 u32 rxtx_ctrl, glue0;
998
999 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1000 if (err)
1001 return err;
1002 err = esr_read_glue0(np, i, &glue0);
1003 if (err)
1004 return err;
1005
1006 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1007 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1008 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1009
1010 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1011 ESR_GLUE_CTRL0_THCNT |
1012 ESR_GLUE_CTRL0_BLTIME);
1013 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1014 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1015 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1016 (BLTIME_300_CYCLES <<
1017 ESR_GLUE_CTRL0_BLTIME_SHIFT));
1018
1019 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1020 if (err)
1021 return err;
1022 err = esr_write_glue0(np, i, glue0);
1023 if (err)
1024 return err;
1025 }
1026
1027
1028 sig = nr64(ESR_INT_SIGNALS);
1029 switch (np->port) {
1030 case 0:
1031 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1032 mask = val;
1033 break;
1034
1035 case 1:
1036 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1037 mask = val;
1038 break;
1039
1040 default:
1041 return -EINVAL;
1042 }
1043
1044 if ((sig & mask) != val) {
1045 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
1046 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
1047 return -ENODEV;
1048 }
1049
1050 return 0;
1051}
1052
1053static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1054{
1055 struct niu_link_config *lp = &np->link_config;
1056 int link_up;
1057 u64 val;
1058 u16 current_speed;
1059 unsigned long flags;
1060 u8 current_duplex;
1061
1062 link_up = 0;
1063 current_speed = SPEED_INVALID;
1064 current_duplex = DUPLEX_INVALID;
1065
1066 spin_lock_irqsave(&np->lock, flags);
1067
1068 val = nr64_pcs(PCS_MII_STAT);
1069
1070 if (val & PCS_MII_STAT_LINK_STATUS) {
1071 link_up = 1;
1072 current_speed = SPEED_1000;
1073 current_duplex = DUPLEX_FULL;
1074 }
1075
1076 lp->active_speed = current_speed;
1077 lp->active_duplex = current_duplex;
1078 spin_unlock_irqrestore(&np->lock, flags);
1079
1080 *link_up_p = link_up;
1081 return 0;
1082}
1083
5fbd7e24
MW		 1084static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1085{
1086 unsigned long flags;
1087 struct niu_link_config *lp = &np->link_config;
1088 int link_up = 0;
1089 int link_ok = 1;
1090 u64 val, val2;
1091 u16 current_speed;
1092 u8 current_duplex;
1093
1094 if (!(np->flags & NIU_FLAGS_10G))
1095 return link_status_1g_serdes(np, link_up_p);
1096
1097 current_speed = SPEED_INVALID;
1098 current_duplex = DUPLEX_INVALID;
1099 spin_lock_irqsave(&np->lock, flags);
1100
1101 val = nr64_xpcs(XPCS_STATUS(0));
1102 val2 = nr64_mac(XMAC_INTER2);
1103 if (val2 & 0x01000000)
1104 link_ok = 0;
1105
1106 if ((val & 0x1000ULL) && link_ok) {
1107 link_up = 1;
1108 current_speed = SPEED_10000;
1109 current_duplex = DUPLEX_FULL;
1110 }
1111 lp->active_speed = current_speed;
1112 lp->active_duplex = current_duplex;
1113 spin_unlock_irqrestore(&np->lock, flags);
1114 *link_up_p = link_up;
1115 return 0;
1116}
1117
5fbd7e24
MW		 1118static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1119{
1120 struct niu_link_config *lp = &np->link_config;
1121 u16 current_speed, bmsr;
1122 unsigned long flags;
1123 u8 current_duplex;
1124 int err, link_up;
1125
1126 link_up = 0;
1127 current_speed = SPEED_INVALID;
1128 current_duplex = DUPLEX_INVALID;
1129
1130 spin_lock_irqsave(&np->lock, flags);
1131
1132 err = -EINVAL;
1133
1134 err = mii_read(np, np->phy_addr, MII_BMSR);
1135 if (err < 0)
1136 goto out;
1137
1138 bmsr = err;
1139 if (bmsr & BMSR_LSTATUS) {
1140 u16 adv, lpa, common, estat;
1141
1142 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1143 if (err < 0)
1144 goto out;
1145 adv = err;
1146
1147 err = mii_read(np, np->phy_addr, MII_LPA);
1148 if (err < 0)
1149 goto out;
1150 lpa = err;
1151
1152 common = adv & lpa;
1153
1154 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1155 if (err < 0)
1156 goto out;
1157 estat = err;
1158 link_up = 1;
1159 current_speed = SPEED_1000;
1160 current_duplex = DUPLEX_FULL;
1161
1162 }
1163 lp->active_speed = current_speed;
1164 lp->active_duplex = current_duplex;
1165 err = 0;
1166
1167out:
1168 spin_unlock_irqrestore(&np->lock, flags);
1169
1170 *link_up_p = link_up;
1171 return err;
1172}
1173
a3138df9
DM		 1174static int bcm8704_reset(struct niu *np)
1175{
1176 int err, limit;
1177
1178 err = mdio_read(np, np->phy_addr,
1179 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1180 if (err < 0)
1181 return err;
1182 err |= BMCR_RESET;
1183 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1184 MII_BMCR, err);
1185 if (err)
1186 return err;
1187
1188 limit = 1000;
1189 while (--limit >= 0) {
1190 err = mdio_read(np, np->phy_addr,
1191 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1192 if (err < 0)
1193 return err;
1194 if (!(err & BMCR_RESET))
1195 break;
1196 }
1197 if (limit < 0) {
1198 dev_err(np->device, PFX "Port %u PHY will not reset "
1199 "(bmcr=%04x)\n", np->port, (err & 0xffff));
1200 return -ENODEV;
1201 }
1202 return 0;
1203}
1204
1205/* When written, certain PHY registers need to be read back twice
1206 * in order for the bits to settle properly.
1207 */
1208static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1209{
1210 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1211 if (err < 0)
1212 return err;
1213 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1214 if (err < 0)
1215 return err;
1216 return 0;
1217}
1218
a5d6ab56
MW		 1219static int bcm8706_init_user_dev3(struct niu *np)
1220{
1221 int err;
1222
1223
1224 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1225 BCM8704_USER_OPT_DIGITAL_CTRL);
1226 if (err < 0)
1227 return err;
1228 err &= ~USER_ODIG_CTRL_GPIOS;
1229 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1230 err |= USER_ODIG_CTRL_RESV2;
1231 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1232 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1233 if (err)
1234 return err;
1235
1236 mdelay(1000);
1237
1238 return 0;
1239}
1240
a3138df9
DM		 1241static int bcm8704_init_user_dev3(struct niu *np)
1242{
1243 int err;
1244
1245 err = mdio_write(np, np->phy_addr,
1246 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1247 (USER_CONTROL_OPTXRST_LVL |
1248 USER_CONTROL_OPBIASFLT_LVL |
1249 USER_CONTROL_OBTMPFLT_LVL |
1250 USER_CONTROL_OPPRFLT_LVL |
1251 USER_CONTROL_OPTXFLT_LVL |
1252 USER_CONTROL_OPRXLOS_LVL |
1253 USER_CONTROL_OPRXFLT_LVL |
1254 USER_CONTROL_OPTXON_LVL |
1255 (0x3f << USER_CONTROL_RES1_SHIFT)));
1256 if (err)
1257 return err;
1258
1259 err = mdio_write(np, np->phy_addr,
1260 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1261 (USER_PMD_TX_CTL_XFP_CLKEN |
1262 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1263 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1264 USER_PMD_TX_CTL_TSCK_LPWREN));
1265 if (err)
1266 return err;
1267
1268 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1269 if (err)
1270 return err;
1271 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1272 if (err)
1273 return err;
1274
1275 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1276 BCM8704_USER_OPT_DIGITAL_CTRL);
1277 if (err < 0)
1278 return err;
1279 err &= ~USER_ODIG_CTRL_GPIOS;
1280 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1281 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1282 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1283 if (err)
1284 return err;
1285
1286 mdelay(1000);
1287
1288 return 0;
1289}
1290
b0de8e40
ML		 1291static int mrvl88x2011_act_led(struct niu *np, int val)
1292{
1293 int err;
1294
1295 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1296 MRVL88X2011_LED_8_TO_11_CTL);
1297 if (err < 0)
1298 return err;
1299
1300 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1301 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1302
1303 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1304 MRVL88X2011_LED_8_TO_11_CTL, err);
1305}
1306
1307static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1308{
1309 int err;
1310
1311 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1312 MRVL88X2011_LED_BLINK_CTL);
1313 if (err >= 0) {
1314 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1315 err |= (rate << 4);
1316
1317 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1318 MRVL88X2011_LED_BLINK_CTL, err);
1319 }
1320
1321 return err;
1322}
1323
1324static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1325{
1326 int err;
1327
1328 /* Set LED functions */
1329 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1330 if (err)
1331 return err;
1332
1333 /* led activity */
1334 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1335 if (err)
1336 return err;
1337
1338 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1339 MRVL88X2011_GENERAL_CTL);
1340 if (err < 0)
1341 return err;
1342
1343 err |= MRVL88X2011_ENA_XFPREFCLK;
1344
1345 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1346 MRVL88X2011_GENERAL_CTL, err);
1347 if (err < 0)
1348 return err;
1349
1350 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1351 MRVL88X2011_PMA_PMD_CTL_1);
1352 if (err < 0)
1353 return err;
1354
1355 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1356 err |= MRVL88X2011_LOOPBACK;
1357 else
1358 err &= ~MRVL88X2011_LOOPBACK;
1359
1360 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1361 MRVL88X2011_PMA_PMD_CTL_1, err);
1362 if (err < 0)
1363 return err;
1364
1365 /* Enable PMD */
1366 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1367 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1368}
1369
a5d6ab56
MW		 1370
1371static int xcvr_diag_bcm870x(struct niu *np)
a3138df9 1372{
a3138df9 1373 u16 analog_stat0, tx_alarm_status;
a5d6ab56 1374 int err = 0;
a3138df9
DM		 1375
1376#if 1
1377 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1378 MII_STAT1000);
1379 if (err < 0)
1380 return err;
1381 pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1382 np->port, err);
1383
1384 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1385 if (err < 0)
1386 return err;
1387 pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1388 np->port, err);
1389
1390 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1391 MII_NWAYTEST);
1392 if (err < 0)
1393 return err;
1394 pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1395 np->port, err);
1396#endif
1397
1398 /* XXX dig this out it might not be so useful XXX */
1399 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1400 BCM8704_USER_ANALOG_STATUS0);
1401 if (err < 0)
1402 return err;
1403 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1404 BCM8704_USER_ANALOG_STATUS0);
1405 if (err < 0)
1406 return err;
1407 analog_stat0 = err;
1408
1409 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1410 BCM8704_USER_TX_ALARM_STATUS);
1411 if (err < 0)
1412 return err;
1413 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1414 BCM8704_USER_TX_ALARM_STATUS);
1415 if (err < 0)
1416 return err;
1417 tx_alarm_status = err;
1418
1419 if (analog_stat0 != 0x03fc) {
1420 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1421 pr_info(PFX "Port %u cable not connected "
1422 "or bad cable.\n", np->port);
1423 } else if (analog_stat0 == 0x639c) {
1424 pr_info(PFX "Port %u optical module is bad "
1425 "or missing.\n", np->port);
1426 }
1427 }
1428
1429 return 0;
1430}
1431
a5d6ab56
MW		 1432static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1433{
1434 struct niu_link_config *lp = &np->link_config;
1435 int err;
1436
1437 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1438 MII_BMCR);
1439 if (err < 0)
1440 return err;
1441
1442 err &= ~BMCR_LOOPBACK;
1443
1444 if (lp->loopback_mode == LOOPBACK_MAC)
1445 err |= BMCR_LOOPBACK;
1446
1447 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1448 MII_BMCR, err);
1449 if (err)
1450 return err;
1451
1452 return 0;
1453}
1454
1455static int xcvr_init_10g_bcm8706(struct niu *np)
1456{
1457 int err = 0;
1458 u64 val;
1459
1460 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1461 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1462 return err;
1463
1464 val = nr64_mac(XMAC_CONFIG);
1465 val &= ~XMAC_CONFIG_LED_POLARITY;
1466 val |= XMAC_CONFIG_FORCE_LED_ON;
1467 nw64_mac(XMAC_CONFIG, val);
1468
1469 val = nr64(MIF_CONFIG);
1470 val |= MIF_CONFIG_INDIRECT_MODE;
1471 nw64(MIF_CONFIG, val);
1472
1473 err = bcm8704_reset(np);
1474 if (err)
1475 return err;
1476
1477 err = xcvr_10g_set_lb_bcm870x(np);
1478 if (err)
1479 return err;
1480
1481 err = bcm8706_init_user_dev3(np);
1482 if (err)
1483 return err;
1484
1485 err = xcvr_diag_bcm870x(np);
1486 if (err)
1487 return err;
1488
1489 return 0;
1490}
1491
1492static int xcvr_init_10g_bcm8704(struct niu *np)
1493{
1494 int err;
1495
1496 err = bcm8704_reset(np);
1497 if (err)
1498 return err;
1499
1500 err = bcm8704_init_user_dev3(np);
1501 if (err)
1502 return err;
1503
1504 err = xcvr_10g_set_lb_bcm870x(np);
1505 if (err)
1506 return err;
1507
1508 err = xcvr_diag_bcm870x(np);
1509 if (err)
1510 return err;
1511
1512 return 0;
1513}
1514
b0de8e40
ML		 1515static int xcvr_init_10g(struct niu *np)
1516{
1517 int phy_id, err;
1518 u64 val;
1519
1520 val = nr64_mac(XMAC_CONFIG);
1521 val &= ~XMAC_CONFIG_LED_POLARITY;
1522 val |= XMAC_CONFIG_FORCE_LED_ON;
1523 nw64_mac(XMAC_CONFIG, val);
1524
1525 /* XXX shared resource, lock parent XXX */
1526 val = nr64(MIF_CONFIG);
1527 val |= MIF_CONFIG_INDIRECT_MODE;
1528 nw64(MIF_CONFIG, val);
1529
1530 phy_id = phy_decode(np->parent->port_phy, np->port);
1531 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1532
1533 /* handle different phy types */
1534 switch (phy_id & NIU_PHY_ID_MASK) {
1535 case NIU_PHY_ID_MRVL88X2011:
1536 err = xcvr_init_10g_mrvl88x2011(np);
1537 break;
1538
1539 default: /* bcom 8704 */
1540 err = xcvr_init_10g_bcm8704(np);
1541 break;
1542 }
1543
1544 return 0;
1545}
1546
a3138df9
DM		 1547static int mii_reset(struct niu *np)
1548{
1549 int limit, err;
1550
1551 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1552 if (err)
1553 return err;
1554
1555 limit = 1000;
1556 while (--limit >= 0) {
1557 udelay(500);
1558 err = mii_read(np, np->phy_addr, MII_BMCR);
1559 if (err < 0)
1560 return err;
1561 if (!(err & BMCR_RESET))
1562 break;
1563 }
1564 if (limit < 0) {
1565 dev_err(np->device, PFX "Port %u MII would not reset, "
1566 "bmcr[%04x]\n", np->port, err);
1567 return -ENODEV;
1568 }
1569
1570 return 0;
1571}
1572
5fbd7e24
MW		 1573static int xcvr_init_1g_rgmii(struct niu *np)
1574{
1575 int err;
1576 u64 val;
1577 u16 bmcr, bmsr, estat;
1578
1579 val = nr64(MIF_CONFIG);
1580 val &= ~MIF_CONFIG_INDIRECT_MODE;
1581 nw64(MIF_CONFIG, val);
1582
1583 err = mii_reset(np);
1584 if (err)
1585 return err;
1586
1587 err = mii_read(np, np->phy_addr, MII_BMSR);
1588 if (err < 0)
1589 return err;
1590 bmsr = err;
1591
1592 estat = 0;
1593 if (bmsr & BMSR_ESTATEN) {
1594 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1595 if (err < 0)
1596 return err;
1597 estat = err;
1598 }
1599
1600 bmcr = 0;
1601 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1602 if (err)
1603 return err;
1604
1605 if (bmsr & BMSR_ESTATEN) {
1606 u16 ctrl1000 = 0;
1607
1608 if (estat & ESTATUS_1000_TFULL)
1609 ctrl1000 |= ADVERTISE_1000FULL;
1610 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1611 if (err)
1612 return err;
1613 }
1614
1615 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1616
1617 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1618 if (err)
1619 return err;
1620
1621 err = mii_read(np, np->phy_addr, MII_BMCR);
1622 if (err < 0)
1623 return err;
1624 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1625
1626 err = mii_read(np, np->phy_addr, MII_BMSR);
1627 if (err < 0)
1628 return err;
1629
1630 return 0;
1631}
1632
a3138df9
DM		 1633static int mii_init_common(struct niu *np)
1634{
1635 struct niu_link_config *lp = &np->link_config;
1636 u16 bmcr, bmsr, adv, estat;
1637 int err;
1638
1639 err = mii_reset(np);
1640 if (err)
1641 return err;
1642
1643 err = mii_read(np, np->phy_addr, MII_BMSR);
1644 if (err < 0)
1645 return err;
1646 bmsr = err;
1647
1648 estat = 0;
1649 if (bmsr & BMSR_ESTATEN) {
1650 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1651 if (err < 0)
1652 return err;
1653 estat = err;
1654 }
1655
1656 bmcr = 0;
1657 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1658 if (err)
1659 return err;
1660
1661 if (lp->loopback_mode == LOOPBACK_MAC) {
1662 bmcr |= BMCR_LOOPBACK;
1663 if (lp->active_speed == SPEED_1000)
1664 bmcr |= BMCR_SPEED1000;
1665 if (lp->active_duplex == DUPLEX_FULL)
1666 bmcr |= BMCR_FULLDPLX;
1667 }
1668
1669 if (lp->loopback_mode == LOOPBACK_PHY) {
1670 u16 aux;
1671
1672 aux = (BCM5464R_AUX_CTL_EXT_LB |
1673 BCM5464R_AUX_CTL_WRITE_1);
1674 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1675 if (err)
1676 return err;
1677 }
1678
1679 /* XXX configurable XXX */
1680 /* XXX for now don't advertise half-duplex or asym pause... XXX */
1681 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1682 if (bmsr & BMSR_10FULL)
1683 adv |= ADVERTISE_10FULL;
1684 if (bmsr & BMSR_100FULL)
1685 adv |= ADVERTISE_100FULL;
1686 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1687 if (err)
1688 return err;
1689
1690 if (bmsr & BMSR_ESTATEN) {
1691 u16 ctrl1000 = 0;
1692
1693 if (estat & ESTATUS_1000_TFULL)
1694 ctrl1000 |= ADVERTISE_1000FULL;
1695 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1696 if (err)
1697 return err;
1698 }
1699 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1700
1701 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1702 if (err)
1703 return err;
1704
1705 err = mii_read(np, np->phy_addr, MII_BMCR);
1706 if (err < 0)
1707 return err;
1708 err = mii_read(np, np->phy_addr, MII_BMSR);
1709 if (err < 0)
1710 return err;
1711#if 0
1712 pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1713 np->port, bmcr, bmsr);
1714#endif
1715
1716 return 0;
1717}
1718
1719static int xcvr_init_1g(struct niu *np)
1720{
1721 u64 val;
1722
1723 /* XXX shared resource, lock parent XXX */
1724 val = nr64(MIF_CONFIG);
1725 val &= ~MIF_CONFIG_INDIRECT_MODE;
1726 nw64(MIF_CONFIG, val);
1727
1728 return mii_init_common(np);
1729}
1730
1731static int niu_xcvr_init(struct niu *np)
1732{
1733 const struct niu_phy_ops *ops = np->phy_ops;
1734 int err;
1735
1736 err = 0;
1737 if (ops->xcvr_init)
1738 err = ops->xcvr_init(np);
1739
1740 return err;
1741}
1742
1743static int niu_serdes_init(struct niu *np)
1744{
1745 const struct niu_phy_ops *ops = np->phy_ops;
1746 int err;
1747
1748 err = 0;
1749 if (ops->serdes_init)
1750 err = ops->serdes_init(np);
1751
1752 return err;
1753}
1754
1755static void niu_init_xif(struct niu *);
0c3b091b 1756static void niu_handle_led(struct niu *, int status);
a3138df9
DM		 1757
1758static int niu_link_status_common(struct niu *np, int link_up)
1759{
1760 struct niu_link_config *lp = &np->link_config;
1761 struct net_device *dev = np->dev;
1762 unsigned long flags;
1763
1764 if (!netif_carrier_ok(dev) && link_up) {
1765 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1766 dev->name,
1767 (lp->active_speed == SPEED_10000 ?
1768 "10Gb/sec" :
1769 (lp->active_speed == SPEED_1000 ?
1770 "1Gb/sec" :
1771 (lp->active_speed == SPEED_100 ?
1772 "100Mbit/sec" : "10Mbit/sec"))),
1773 (lp->active_duplex == DUPLEX_FULL ?
1774 "full" : "half"));
1775
1776 spin_lock_irqsave(&np->lock, flags);
1777 niu_init_xif(np);
0c3b091b 1778 niu_handle_led(np, 1);
a3138df9
DM		 1779 spin_unlock_irqrestore(&np->lock, flags);
1780
1781 netif_carrier_on(dev);
1782 } else if (netif_carrier_ok(dev) && !link_up) {
1783 niuwarn(LINK, "%s: Link is down\n", dev->name);
0c3b091b
ML		 1784 spin_lock_irqsave(&np->lock, flags);
1785 niu_handle_led(np, 0);
1786 spin_unlock_irqrestore(&np->lock, flags);
a3138df9
DM		 1787 netif_carrier_off(dev);
1788 }
1789
1790 return 0;
1791}
1792
b0de8e40 1793static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
a3138df9 1794{
b0de8e40 1795 int err, link_up, pma_status, pcs_status;
a3138df9
DM		 1796
1797 link_up = 0;
1798
b0de8e40
ML		 1799 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1800 MRVL88X2011_10G_PMD_STATUS_2);
1801 if (err < 0)
1802 goto out;
a3138df9 1803
b0de8e40
ML		 1804 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1805 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1806 MRVL88X2011_PMA_PMD_STATUS_1);
1807 if (err < 0)
1808 goto out;
1809
1810 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1811
1812 /* Check PMC Register : 3.0001.2 == 1: read twice */
1813 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1814 MRVL88X2011_PMA_PMD_STATUS_1);
1815 if (err < 0)
1816 goto out;
1817
1818 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1819 MRVL88X2011_PMA_PMD_STATUS_1);
1820 if (err < 0)
1821 goto out;
1822
1823 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1824
1825 /* Check XGXS Register : 4.0018.[0-3,12] */
1826 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1827 MRVL88X2011_10G_XGXS_LANE_STAT);
1828 if (err < 0)
a3138df9
DM		 1829 goto out;
1830
b0de8e40
ML		 1831 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1832 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1833 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1834 0x800))
1835 link_up = (pma_status && pcs_status) ? 1 : 0;
1836
1837 np->link_config.active_speed = SPEED_10000;
1838 np->link_config.active_duplex = DUPLEX_FULL;
1839 err = 0;
1840out:
1841 mrvl88x2011_act_led(np, (link_up ?
1842 MRVL88X2011_LED_CTL_PCS_ACT :
1843 MRVL88X2011_LED_CTL_OFF));
1844
1845 *link_up_p = link_up;
1846 return err;
1847}
1848
a5d6ab56
MW		 1849static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1850{
1851 int err, link_up;
1852 link_up = 0;
1853
1854 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1855 BCM8704_PMD_RCV_SIGDET);
1856 if (err < 0)
1857 goto out;
1858 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1859 err = 0;
1860 goto out;
1861 }
1862
1863 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1864 BCM8704_PCS_10G_R_STATUS);
1865 if (err < 0)
1866 goto out;
1867
1868 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1869 err = 0;
1870 goto out;
1871 }
1872
1873 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1874 BCM8704_PHYXS_XGXS_LANE_STAT);
1875 if (err < 0)
1876 goto out;
1877 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1878 PHYXS_XGXS_LANE_STAT_MAGIC |
1879 PHYXS_XGXS_LANE_STAT_PATTEST |
1880 PHYXS_XGXS_LANE_STAT_LANE3 |
1881 PHYXS_XGXS_LANE_STAT_LANE2 |
1882 PHYXS_XGXS_LANE_STAT_LANE1 |
1883 PHYXS_XGXS_LANE_STAT_LANE0)) {
1884 err = 0;
1885 np->link_config.active_speed = SPEED_INVALID;
1886 np->link_config.active_duplex = DUPLEX_INVALID;
1887 goto out;
1888 }
1889
1890 link_up = 1;
1891 np->link_config.active_speed = SPEED_10000;
1892 np->link_config.active_duplex = DUPLEX_FULL;
1893 err = 0;
1894
1895out:
1896 *link_up_p = link_up;
1897 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
1898 err = 0;
1899 return err;
1900}
1901
b0de8e40
ML		 1902static int link_status_10g_bcom(struct niu *np, int *link_up_p)
1903{
1904 int err, link_up;
1905
1906 link_up = 0;
1907
a3138df9
DM		 1908 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1909 BCM8704_PMD_RCV_SIGDET);
1910 if (err < 0)
1911 goto out;
1912 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1913 err = 0;
1914 goto out;
1915 }
1916
1917 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1918 BCM8704_PCS_10G_R_STATUS);
1919 if (err < 0)
1920 goto out;
1921 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1922 err = 0;
1923 goto out;
1924 }
1925
1926 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1927 BCM8704_PHYXS_XGXS_LANE_STAT);
1928 if (err < 0)
1929 goto out;
1930
1931 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1932 PHYXS_XGXS_LANE_STAT_MAGIC |
1933 PHYXS_XGXS_LANE_STAT_LANE3 |
1934 PHYXS_XGXS_LANE_STAT_LANE2 |
1935 PHYXS_XGXS_LANE_STAT_LANE1 |
1936 PHYXS_XGXS_LANE_STAT_LANE0)) {
1937 err = 0;
1938 goto out;
1939 }
1940
1941 link_up = 1;
1942 np->link_config.active_speed = SPEED_10000;
1943 np->link_config.active_duplex = DUPLEX_FULL;
1944 err = 0;
1945
1946out:
b0de8e40
ML		 1947 *link_up_p = link_up;
1948 return err;
1949}
1950
1951static int link_status_10g(struct niu *np, int *link_up_p)
1952{
1953 unsigned long flags;
1954 int err = -EINVAL;
1955
1956 spin_lock_irqsave(&np->lock, flags);
1957
1958 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
1959 int phy_id;
1960
1961 phy_id = phy_decode(np->parent->port_phy, np->port);
1962 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1963
1964 /* handle different phy types */
1965 switch (phy_id & NIU_PHY_ID_MASK) {
1966 case NIU_PHY_ID_MRVL88X2011:
1967 err = link_status_10g_mrvl(np, link_up_p);
1968 break;
1969
1970 default: /* bcom 8704 */
1971 err = link_status_10g_bcom(np, link_up_p);
1972 break;
1973 }
1974 }
1975
a3138df9
DM		 1976 spin_unlock_irqrestore(&np->lock, flags);
1977
a3138df9
DM		 1978 return err;
1979}
1980
a5d6ab56
MW		 1981static int niu_10g_phy_present(struct niu *np)
1982{
1983 u64 sig, mask, val;
1984
1985 sig = nr64(ESR_INT_SIGNALS);
1986 switch (np->port) {
1987 case 0:
1988 mask = ESR_INT_SIGNALS_P0_BITS;
1989 val = (ESR_INT_SRDY0_P0 |
1990 ESR_INT_DET0_P0 |
1991 ESR_INT_XSRDY_P0 |
1992 ESR_INT_XDP_P0_CH3 |
1993 ESR_INT_XDP_P0_CH2 |
1994 ESR_INT_XDP_P0_CH1 |
1995 ESR_INT_XDP_P0_CH0);
1996 break;
1997
1998 case 1:
1999 mask = ESR_INT_SIGNALS_P1_BITS;
2000 val = (ESR_INT_SRDY0_P1 |
2001 ESR_INT_DET0_P1 |
2002 ESR_INT_XSRDY_P1 |
2003 ESR_INT_XDP_P1_CH3 |
2004 ESR_INT_XDP_P1_CH2 |
2005 ESR_INT_XDP_P1_CH1 |
2006 ESR_INT_XDP_P1_CH0);
2007 break;
2008
2009 default:
2010 return 0;
2011 }
2012
2013 if ((sig & mask) != val)
2014 return 0;
2015 return 1;
2016}
2017
2018static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2019{
2020 unsigned long flags;
2021 int err = 0;
2022 int phy_present;
2023 int phy_present_prev;
2024
2025 spin_lock_irqsave(&np->lock, flags);
2026
2027 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2028 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2029 1 : 0;
2030 phy_present = niu_10g_phy_present(np);
2031 if (phy_present != phy_present_prev) {
2032 /* state change */
2033 if (phy_present) {
2034 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2035 if (np->phy_ops->xcvr_init)
2036 err = np->phy_ops->xcvr_init(np);
2037 if (err) {
2038 /* debounce */
2039 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2040 }
2041 } else {
2042 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2043 *link_up_p = 0;
2044 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
2045 np->dev->name);
2046 }
2047 }
2048 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT)
2049 err = link_status_10g_bcm8706(np, link_up_p);
2050 }
2051
2052 spin_unlock_irqrestore(&np->lock, flags);
2053
2054 return err;
2055}
2056
a3138df9
DM		 2057static int link_status_1g(struct niu *np, int *link_up_p)
2058{
e415e6ea 2059 struct niu_link_config *lp = &np->link_config;
a3138df9
DM		 2060 u16 current_speed, bmsr;
2061 unsigned long flags;
2062 u8 current_duplex;
2063 int err, link_up;
2064
2065 link_up = 0;
2066 current_speed = SPEED_INVALID;
2067 current_duplex = DUPLEX_INVALID;
2068
2069 spin_lock_irqsave(&np->lock, flags);
2070
2071 err = -EINVAL;
2072 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
2073 goto out;
2074
2075 err = mii_read(np, np->phy_addr, MII_BMSR);
2076 if (err < 0)
2077 goto out;
2078
2079 bmsr = err;
2080 if (bmsr & BMSR_LSTATUS) {
2081 u16 adv, lpa, common, estat;
2082
2083 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
2084 if (err < 0)
2085 goto out;
2086 adv = err;
2087
2088 err = mii_read(np, np->phy_addr, MII_LPA);
2089 if (err < 0)
2090 goto out;
2091 lpa = err;
2092
2093 common = adv & lpa;
2094
2095 err = mii_read(np, np->phy_addr, MII_ESTATUS);
2096 if (err < 0)
2097 goto out;
2098 estat = err;
2099
2100 link_up = 1;
2101 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
2102 current_speed = SPEED_1000;
2103 if (estat & ESTATUS_1000_TFULL)
2104 current_duplex = DUPLEX_FULL;
2105 else
2106 current_duplex = DUPLEX_HALF;
2107 } else {
2108 if (common & ADVERTISE_100BASE4) {
2109 current_speed = SPEED_100;
2110 current_duplex = DUPLEX_HALF;
2111 } else if (common & ADVERTISE_100FULL) {
2112 current_speed = SPEED_100;
2113 current_duplex = DUPLEX_FULL;
2114 } else if (common & ADVERTISE_100HALF) {
2115 current_speed = SPEED_100;
2116 current_duplex = DUPLEX_HALF;
2117 } else if (common & ADVERTISE_10FULL) {
2118 current_speed = SPEED_10;
2119 current_duplex = DUPLEX_FULL;
2120 } else if (common & ADVERTISE_10HALF) {
2121 current_speed = SPEED_10;
2122 current_duplex = DUPLEX_HALF;
2123 } else
2124 link_up = 0;
2125 }
2126 }
e415e6ea
DM		 2127 lp->active_speed = current_speed;
2128 lp->active_duplex = current_duplex;
a3138df9
DM		 2129 err = 0;
2130
2131out:
2132 spin_unlock_irqrestore(&np->lock, flags);
2133
2134 *link_up_p = link_up;
2135 return err;
2136}
2137
2138static int niu_link_status(struct niu *np, int *link_up_p)
2139{
2140 const struct niu_phy_ops *ops = np->phy_ops;
2141 int err;
2142
2143 err = 0;
2144 if (ops->link_status)
2145 err = ops->link_status(np, link_up_p);
2146
2147 return err;
2148}
2149
2150static void niu_timer(unsigned long __opaque)
2151{
2152 struct niu *np = (struct niu *) __opaque;
2153 unsigned long off;
2154 int err, link_up;
2155
2156 err = niu_link_status(np, &link_up);
2157 if (!err)
2158 niu_link_status_common(np, link_up);
2159
2160 if (netif_carrier_ok(np->dev))
2161 off = 5 * HZ;
2162 else
2163 off = 1 * HZ;
2164 np->timer.expires = jiffies + off;
2165
2166 add_timer(&np->timer);
2167}
2168
5fbd7e24
MW		 2169static const struct niu_phy_ops phy_ops_10g_serdes = {
2170 .serdes_init = serdes_init_10g_serdes,
2171 .link_status = link_status_10g_serdes,
2172};
2173
e3e081e1
SB		 2174static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2175 .serdes_init = serdes_init_niu_10g_serdes,
2176 .link_status = link_status_10g_serdes,
2177};
2178
2179static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2180 .serdes_init = serdes_init_niu_1g_serdes,
2181 .link_status = link_status_1g_serdes,
2182};
2183
5fbd7e24
MW		 2184static const struct niu_phy_ops phy_ops_1g_rgmii = {
2185 .xcvr_init = xcvr_init_1g_rgmii,
2186 .link_status = link_status_1g_rgmii,
2187};
2188
a3138df9 2189static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
e3e081e1 2190 .serdes_init = serdes_init_niu_10g_fiber,
a3138df9
DM		 2191 .xcvr_init = xcvr_init_10g,
2192 .link_status = link_status_10g,
2193};
2194
2195static const struct niu_phy_ops phy_ops_10g_fiber = {
2196 .serdes_init = serdes_init_10g,
2197 .xcvr_init = xcvr_init_10g,
2198 .link_status = link_status_10g,
2199};
2200
a5d6ab56
MW		 2201static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2202 .serdes_init = serdes_init_10g,
2203 .xcvr_init = xcvr_init_10g_bcm8706,
2204 .link_status = link_status_10g_hotplug,
2205};
2206
a3138df9
DM		 2207static const struct niu_phy_ops phy_ops_10g_copper = {
2208 .serdes_init = serdes_init_10g,
2209 .link_status = link_status_10g, /* XXX */
2210};
2211
2212static const struct niu_phy_ops phy_ops_1g_fiber = {
2213 .serdes_init = serdes_init_1g,
2214 .xcvr_init = xcvr_init_1g,
2215 .link_status = link_status_1g,
2216};
2217
2218static const struct niu_phy_ops phy_ops_1g_copper = {
2219 .xcvr_init = xcvr_init_1g,
2220 .link_status = link_status_1g,
2221};
2222
2223struct niu_phy_template {
2224 const struct niu_phy_ops *ops;
2225 u32 phy_addr_base;
2226};
2227
e3e081e1 2228static const struct niu_phy_template phy_template_niu_10g_fiber = {
a3138df9
DM		 2229 .ops = &phy_ops_10g_fiber_niu,
2230 .phy_addr_base = 16,
2231};
2232
e3e081e1
SB		 2233static const struct niu_phy_template phy_template_niu_10g_serdes = {
2234 .ops = &phy_ops_10g_serdes_niu,
2235 .phy_addr_base = 0,
2236};
2237
2238static const struct niu_phy_template phy_template_niu_1g_serdes = {
2239 .ops = &phy_ops_1g_serdes_niu,
2240 .phy_addr_base = 0,
2241};
2242
a3138df9
DM		 2243static const struct niu_phy_template phy_template_10g_fiber = {
2244 .ops = &phy_ops_10g_fiber,
2245 .phy_addr_base = 8,
2246};
2247
a5d6ab56
MW		 2248static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2249 .ops = &phy_ops_10g_fiber_hotplug,
2250 .phy_addr_base = 8,
2251};
2252
a3138df9
DM		 2253static const struct niu_phy_template phy_template_10g_copper = {
2254 .ops = &phy_ops_10g_copper,
2255 .phy_addr_base = 10,
2256};
2257
2258static const struct niu_phy_template phy_template_1g_fiber = {
2259 .ops = &phy_ops_1g_fiber,
2260 .phy_addr_base = 0,
2261};
2262
2263static const struct niu_phy_template phy_template_1g_copper = {
2264 .ops = &phy_ops_1g_copper,
2265 .phy_addr_base = 0,
2266};
2267
5fbd7e24
MW		 2268static const struct niu_phy_template phy_template_1g_rgmii = {
2269 .ops = &phy_ops_1g_rgmii,
2270 .phy_addr_base = 0,
2271};
2272
2273static const struct niu_phy_template phy_template_10g_serdes = {
2274 .ops = &phy_ops_10g_serdes,
2275 .phy_addr_base = 0,
2276};
2277
2278static int niu_atca_port_num[4] = {
2279 0, 0, 11, 10
2280};
2281
2282static int serdes_init_10g_serdes(struct niu *np)
2283{
2284 struct niu_link_config *lp = &np->link_config;
2285 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2286 u64 ctrl_val, test_cfg_val, sig, mask, val;
2287 int err;
2288 u64 reset_val;
2289
2290 switch (np->port) {
2291 case 0:
2292 reset_val = ENET_SERDES_RESET_0;
2293 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2294 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2295 pll_cfg = ENET_SERDES_0_PLL_CFG;
2296 break;
2297 case 1:
2298 reset_val = ENET_SERDES_RESET_1;
2299 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2300 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2301 pll_cfg = ENET_SERDES_1_PLL_CFG;
2302 break;
2303
2304 default:
2305 return -EINVAL;
2306 }
2307 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2308 ENET_SERDES_CTRL_SDET_1 |
2309 ENET_SERDES_CTRL_SDET_2 |
2310 ENET_SERDES_CTRL_SDET_3 |
2311 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2312 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2313 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2314 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2315 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2316 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2317 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2318 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2319 test_cfg_val = 0;
2320
2321 if (lp->loopback_mode == LOOPBACK_PHY) {
2322 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2323 ENET_SERDES_TEST_MD_0_SHIFT) |
2324 (ENET_TEST_MD_PAD_LOOPBACK <<
2325 ENET_SERDES_TEST_MD_1_SHIFT) |
2326 (ENET_TEST_MD_PAD_LOOPBACK <<
2327 ENET_SERDES_TEST_MD_2_SHIFT) |
2328 (ENET_TEST_MD_PAD_LOOPBACK <<
2329 ENET_SERDES_TEST_MD_3_SHIFT));
2330 }
2331
2332 esr_reset(np);
2333 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2334 nw64(ctrl_reg, ctrl_val);
2335 nw64(test_cfg_reg, test_cfg_val);
2336
2337 /* Initialize all 4 lanes of the SERDES. */
2338 for (i = 0; i < 4; i++) {
2339 u32 rxtx_ctrl, glue0;
2340
2341 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2342 if (err)
2343 return err;
2344 err = esr_read_glue0(np, i, &glue0);
2345 if (err)
2346 return err;
2347
2348 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2349 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2350 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2351
2352 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2353 ESR_GLUE_CTRL0_THCNT |
2354 ESR_GLUE_CTRL0_BLTIME);
2355 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2356 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2357 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2358 (BLTIME_300_CYCLES <<
2359 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2360
2361 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2362 if (err)
2363 return err;
2364 err = esr_write_glue0(np, i, glue0);
2365 if (err)
2366 return err;
2367 }
2368
2369
2370 sig = nr64(ESR_INT_SIGNALS);
2371 switch (np->port) {
2372 case 0:
2373 mask = ESR_INT_SIGNALS_P0_BITS;
2374 val = (ESR_INT_SRDY0_P0 |
2375 ESR_INT_DET0_P0 |
2376 ESR_INT_XSRDY_P0 |
2377 ESR_INT_XDP_P0_CH3 |
2378 ESR_INT_XDP_P0_CH2 |
2379 ESR_INT_XDP_P0_CH1 |
2380 ESR_INT_XDP_P0_CH0);
2381 break;
2382
2383 case 1:
2384 mask = ESR_INT_SIGNALS_P1_BITS;
2385 val = (ESR_INT_SRDY0_P1 |
2386 ESR_INT_DET0_P1 |
2387 ESR_INT_XSRDY_P1 |
2388 ESR_INT_XDP_P1_CH3 |
2389 ESR_INT_XDP_P1_CH2 |
2390 ESR_INT_XDP_P1_CH1 |
2391 ESR_INT_XDP_P1_CH0);
2392 break;
2393
2394 default:
2395 return -EINVAL;
2396 }
2397
2398 if ((sig & mask) != val) {
2399 int err;
2400 err = serdes_init_1g_serdes(np);
2401 if (!err) {
2402 np->flags &= ~NIU_FLAGS_10G;
2403 np->mac_xcvr = MAC_XCVR_PCS;
2404 } else {
2405 dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2406 np->port);
2407 return -ENODEV;
2408 }
2409 }
2410
2411 return 0;
2412}
2413
a3138df9
DM		 2414static int niu_determine_phy_disposition(struct niu *np)
2415{
2416 struct niu_parent *parent = np->parent;
2417 u8 plat_type = parent->plat_type;
2418 const struct niu_phy_template *tp;
2419 u32 phy_addr_off = 0;
2420
2421 if (plat_type == PLAT_TYPE_NIU) {
e3e081e1
SB		 2422 switch (np->flags &
2423 (NIU_FLAGS_10G |
2424 NIU_FLAGS_FIBER |
2425 NIU_FLAGS_XCVR_SERDES)) {
2426 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2427 /* 10G Serdes */
2428 tp = &phy_template_niu_10g_serdes;
2429 break;
2430 case NIU_FLAGS_XCVR_SERDES:
2431 /* 1G Serdes */
2432 tp = &phy_template_niu_1g_serdes;
2433 break;
2434 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2435 /* 10G Fiber */
2436 default:
2437 tp = &phy_template_niu_10g_fiber;
2438 phy_addr_off += np->port;
2439 break;
2440 }
a3138df9 2441 } else {
5fbd7e24
MW		 2442 switch (np->flags &
2443 (NIU_FLAGS_10G |
2444 NIU_FLAGS_FIBER |
2445 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 2446 case 0:
2447 /* 1G copper */
2448 tp = &phy_template_1g_copper;
2449 if (plat_type == PLAT_TYPE_VF_P0)
2450 phy_addr_off = 10;
2451 else if (plat_type == PLAT_TYPE_VF_P1)
2452 phy_addr_off = 26;
2453
2454 phy_addr_off += (np->port ^ 0x3);
2455 break;
2456
2457 case NIU_FLAGS_10G:
2458 /* 10G copper */
2459 tp = &phy_template_1g_copper;
2460 break;
2461
2462 case NIU_FLAGS_FIBER:
2463 /* 1G fiber */
2464 tp = &phy_template_1g_fiber;
2465 break;
2466
2467 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2468 /* 10G fiber */
2469 tp = &phy_template_10g_fiber;
2470 if (plat_type == PLAT_TYPE_VF_P0 ||
2471 plat_type == PLAT_TYPE_VF_P1)
2472 phy_addr_off = 8;
2473 phy_addr_off += np->port;
a5d6ab56
MW		 2474 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2475 tp = &phy_template_10g_fiber_hotplug;
2476 if (np->port == 0)
2477 phy_addr_off = 8;
2478 if (np->port == 1)
2479 phy_addr_off = 12;
2480 }
a3138df9
DM		 2481 break;
2482
5fbd7e24
MW		 2483 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2484 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2485 case NIU_FLAGS_XCVR_SERDES:
2486 switch(np->port) {
2487 case 0:
2488 case 1:
2489 tp = &phy_template_10g_serdes;
2490 break;
2491 case 2:
2492 case 3:
2493 tp = &phy_template_1g_rgmii;
2494 break;
2495 default:
2496 return -EINVAL;
2497 break;
2498 }
2499 phy_addr_off = niu_atca_port_num[np->port];
2500 break;
2501
a3138df9
DM		 2502 default:
2503 return -EINVAL;
2504 }
2505 }
2506
2507 np->phy_ops = tp->ops;
2508 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2509
2510 return 0;
2511}
2512
2513static int niu_init_link(struct niu *np)
2514{
2515 struct niu_parent *parent = np->parent;
2516 int err, ignore;
2517
2518 if (parent->plat_type == PLAT_TYPE_NIU) {
2519 err = niu_xcvr_init(np);
2520 if (err)
2521 return err;
2522 msleep(200);
2523 }
2524 err = niu_serdes_init(np);
2525 if (err)
2526 return err;
2527 msleep(200);
2528 err = niu_xcvr_init(np);
2529 if (!err)
2530 niu_link_status(np, &ignore);
2531 return 0;
2532}
2533
2534static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2535{
2536 u16 reg0 = addr[4] << 8 | addr[5];
2537 u16 reg1 = addr[2] << 8 | addr[3];
2538 u16 reg2 = addr[0] << 8 | addr[1];
2539
2540 if (np->flags & NIU_FLAGS_XMAC) {
2541 nw64_mac(XMAC_ADDR0, reg0);
2542 nw64_mac(XMAC_ADDR1, reg1);
2543 nw64_mac(XMAC_ADDR2, reg2);
2544 } else {
2545 nw64_mac(BMAC_ADDR0, reg0);
2546 nw64_mac(BMAC_ADDR1, reg1);
2547 nw64_mac(BMAC_ADDR2, reg2);
2548 }
2549}
2550
2551static int niu_num_alt_addr(struct niu *np)
2552{
2553 if (np->flags & NIU_FLAGS_XMAC)
2554 return XMAC_NUM_ALT_ADDR;
2555 else
2556 return BMAC_NUM_ALT_ADDR;
2557}
2558
2559static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2560{
2561 u16 reg0 = addr[4] << 8 | addr[5];
2562 u16 reg1 = addr[2] << 8 | addr[3];
2563 u16 reg2 = addr[0] << 8 | addr[1];
2564
2565 if (index >= niu_num_alt_addr(np))
2566 return -EINVAL;
2567
2568 if (np->flags & NIU_FLAGS_XMAC) {
2569 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2570 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2571 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2572 } else {
2573 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2574 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2575 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2576 }
2577
2578 return 0;
2579}
2580
2581static int niu_enable_alt_mac(struct niu *np, int index, int on)
2582{
2583 unsigned long reg;
2584 u64 val, mask;
2585
2586 if (index >= niu_num_alt_addr(np))
2587 return -EINVAL;
2588
fa907895 2589 if (np->flags & NIU_FLAGS_XMAC) {
a3138df9 2590 reg = XMAC_ADDR_CMPEN;
fa907895
MW		 2591 mask = 1 << index;
2592 } else {
a3138df9 2593 reg = BMAC_ADDR_CMPEN;
fa907895
MW		 2594 mask = 1 << (index + 1);
2595 }
a3138df9
DM		 2596
2597 val = nr64_mac(reg);
2598 if (on)
2599 val |= mask;
2600 else
2601 val &= ~mask;
2602 nw64_mac(reg, val);
2603
2604 return 0;
2605}
2606
2607static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2608 int num, int mac_pref)
2609{
2610 u64 val = nr64_mac(reg);
2611 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2612 val |= num;
2613 if (mac_pref)
2614 val |= HOST_INFO_MPR;
2615 nw64_mac(reg, val);
2616}
2617
2618static int __set_rdc_table_num(struct niu *np,
2619 int xmac_index, int bmac_index,
2620 int rdc_table_num, int mac_pref)
2621{
2622 unsigned long reg;
2623
2624 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2625 return -EINVAL;
2626 if (np->flags & NIU_FLAGS_XMAC)
2627 reg = XMAC_HOST_INFO(xmac_index);
2628 else
2629 reg = BMAC_HOST_INFO(bmac_index);
2630 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2631 return 0;
2632}
2633
2634static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2635 int mac_pref)
2636{
2637 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2638}
2639
2640static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2641 int mac_pref)
2642{
2643 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2644}
2645
2646static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2647 int table_num, int mac_pref)
2648{
2649 if (idx >= niu_num_alt_addr(np))
2650 return -EINVAL;
2651 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2652}
2653
2654static u64 vlan_entry_set_parity(u64 reg_val)
2655{
2656 u64 port01_mask;
2657 u64 port23_mask;
2658
2659 port01_mask = 0x00ff;
2660 port23_mask = 0xff00;
2661
2662 if (hweight64(reg_val & port01_mask) & 1)
2663 reg_val |= ENET_VLAN_TBL_PARITY0;
2664 else
2665 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2666
2667 if (hweight64(reg_val & port23_mask) & 1)
2668 reg_val |= ENET_VLAN_TBL_PARITY1;
2669 else
2670 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2671
2672 return reg_val;
2673}
2674
2675static void vlan_tbl_write(struct niu *np, unsigned long index,
2676 int port, int vpr, int rdc_table)
2677{
2678 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2679
2680 reg_val &= ~((ENET_VLAN_TBL_VPR |
2681 ENET_VLAN_TBL_VLANRDCTBLN) <<
2682 ENET_VLAN_TBL_SHIFT(port));
2683 if (vpr)
2684 reg_val |= (ENET_VLAN_TBL_VPR <<
2685 ENET_VLAN_TBL_SHIFT(port));
2686 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2687
2688 reg_val = vlan_entry_set_parity(reg_val);
2689
2690 nw64(ENET_VLAN_TBL(index), reg_val);
2691}
2692
2693static void vlan_tbl_clear(struct niu *np)
2694{
2695 int i;
2696
2697 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2698 nw64(ENET_VLAN_TBL(i), 0);
2699}
2700
2701static int tcam_wait_bit(struct niu *np, u64 bit)
2702{
2703 int limit = 1000;
2704
2705 while (--limit > 0) {
2706 if (nr64(TCAM_CTL) & bit)
2707 break;
2708 udelay(1);
2709 }
2710 if (limit < 0)
2711 return -ENODEV;
2712
2713 return 0;
2714}
2715
2716static int tcam_flush(struct niu *np, int index)
2717{
2718 nw64(TCAM_KEY_0, 0x00);
2719 nw64(TCAM_KEY_MASK_0, 0xff);
2720 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2721
2722 return tcam_wait_bit(np, TCAM_CTL_STAT);
2723}
2724
2725#if 0
2726static int tcam_read(struct niu *np, int index,
2727 u64 *key, u64 *mask)
2728{
2729 int err;
2730
2731 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2732 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2733 if (!err) {
2734 key[0] = nr64(TCAM_KEY_0);
2735 key[1] = nr64(TCAM_KEY_1);
2736 key[2] = nr64(TCAM_KEY_2);
2737 key[3] = nr64(TCAM_KEY_3);
2738 mask[0] = nr64(TCAM_KEY_MASK_0);
2739 mask[1] = nr64(TCAM_KEY_MASK_1);
2740 mask[2] = nr64(TCAM_KEY_MASK_2);
2741 mask[3] = nr64(TCAM_KEY_MASK_3);
2742 }
2743 return err;
2744}
2745#endif
2746
2747static int tcam_write(struct niu *np, int index,
2748 u64 *key, u64 *mask)
2749{
2750 nw64(TCAM_KEY_0, key[0]);
2751 nw64(TCAM_KEY_1, key[1]);
2752 nw64(TCAM_KEY_2, key[2]);
2753 nw64(TCAM_KEY_3, key[3]);
2754 nw64(TCAM_KEY_MASK_0, mask[0]);
2755 nw64(TCAM_KEY_MASK_1, mask[1]);
2756 nw64(TCAM_KEY_MASK_2, mask[2]);
2757 nw64(TCAM_KEY_MASK_3, mask[3]);
2758 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2759
2760 return tcam_wait_bit(np, TCAM_CTL_STAT);
2761}
2762
2763#if 0
2764static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2765{
2766 int err;
2767
2768 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2769 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2770 if (!err)
2771 *data = nr64(TCAM_KEY_1);
2772
2773 return err;
2774}
2775#endif
2776
2777static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2778{
2779 nw64(TCAM_KEY_1, assoc_data);
2780 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2781
2782 return tcam_wait_bit(np, TCAM_CTL_STAT);
2783}
2784
2785static void tcam_enable(struct niu *np, int on)
2786{
2787 u64 val = nr64(FFLP_CFG_1);
2788
2789 if (on)
2790 val &= ~FFLP_CFG_1_TCAM_DIS;
2791 else
2792 val |= FFLP_CFG_1_TCAM_DIS;
2793 nw64(FFLP_CFG_1, val);
2794}
2795
2796static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2797{
2798 u64 val = nr64(FFLP_CFG_1);
2799
2800 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2801 FFLP_CFG_1_CAMLAT |
2802 FFLP_CFG_1_CAMRATIO);
2803 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2804 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2805 nw64(FFLP_CFG_1, val);
2806
2807 val = nr64(FFLP_CFG_1);
2808 val |= FFLP_CFG_1_FFLPINITDONE;
2809 nw64(FFLP_CFG_1, val);
2810}
2811
2812static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2813 int on)
2814{
2815 unsigned long reg;
2816 u64 val;
2817
2818 if (class < CLASS_CODE_ETHERTYPE1 ||
2819 class > CLASS_CODE_ETHERTYPE2)
2820 return -EINVAL;
2821
2822 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2823 val = nr64(reg);
2824 if (on)
2825 val |= L2_CLS_VLD;
2826 else
2827 val &= ~L2_CLS_VLD;
2828 nw64(reg, val);
2829
2830 return 0;
2831}
2832
2833#if 0
2834static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2835 u64 ether_type)
2836{
2837 unsigned long reg;
2838 u64 val;
2839
2840 if (class < CLASS_CODE_ETHERTYPE1 ||
2841 class > CLASS_CODE_ETHERTYPE2 ||
2842 (ether_type & ~(u64)0xffff) != 0)
2843 return -EINVAL;
2844
2845 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2846 val = nr64(reg);
2847 val &= ~L2_CLS_ETYPE;
2848 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2849 nw64(reg, val);
2850
2851 return 0;
2852}
2853#endif
2854
2855static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2856 int on)
2857{
2858 unsigned long reg;
2859 u64 val;
2860
2861 if (class < CLASS_CODE_USER_PROG1 ||
2862 class > CLASS_CODE_USER_PROG4)
2863 return -EINVAL;
2864
2865 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2866 val = nr64(reg);
2867 if (on)
2868 val |= L3_CLS_VALID;
2869 else
2870 val &= ~L3_CLS_VALID;
2871 nw64(reg, val);
2872
2873 return 0;
2874}
2875
2876#if 0
2877static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2878 int ipv6, u64 protocol_id,
2879 u64 tos_mask, u64 tos_val)
2880{
2881 unsigned long reg;
2882 u64 val;
2883
2884 if (class < CLASS_CODE_USER_PROG1 ||
2885 class > CLASS_CODE_USER_PROG4 ||
2886 (protocol_id & ~(u64)0xff) != 0 ||
2887 (tos_mask & ~(u64)0xff) != 0 ||
2888 (tos_val & ~(u64)0xff) != 0)
2889 return -EINVAL;
2890
2891 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2892 val = nr64(reg);
2893 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2894 L3_CLS_TOSMASK | L3_CLS_TOS);
2895 if (ipv6)
2896 val |= L3_CLS_IPVER;
2897 val |= (protocol_id << L3_CLS_PID_SHIFT);
2898 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2899 val |= (tos_val << L3_CLS_TOS_SHIFT);
2900 nw64(reg, val);
2901
2902 return 0;
2903}
2904#endif
2905
2906static int tcam_early_init(struct niu *np)
2907{
2908 unsigned long i;
2909 int err;
2910
2911 tcam_enable(np, 0);
2912 tcam_set_lat_and_ratio(np,
2913 DEFAULT_TCAM_LATENCY,
2914 DEFAULT_TCAM_ACCESS_RATIO);
2915 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
2916 err = tcam_user_eth_class_enable(np, i, 0);
2917 if (err)
2918 return err;
2919 }
2920 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
2921 err = tcam_user_ip_class_enable(np, i, 0);
2922 if (err)
2923 return err;
2924 }
2925
2926 return 0;
2927}
2928
2929static int tcam_flush_all(struct niu *np)
2930{
2931 unsigned long i;
2932
2933 for (i = 0; i < np->parent->tcam_num_entries; i++) {
2934 int err = tcam_flush(np, i);
2935 if (err)
2936 return err;
2937 }
2938 return 0;
2939}
2940
2941static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
2942{
2943 return ((u64)index | (num_entries == 1 ?
2944 HASH_TBL_ADDR_AUTOINC : 0));
2945}
2946
2947#if 0
2948static int hash_read(struct niu *np, unsigned long partition,
2949 unsigned long index, unsigned long num_entries,
2950 u64 *data)
2951{
2952 u64 val = hash_addr_regval(index, num_entries);
2953 unsigned long i;
2954
2955 if (partition >= FCRAM_NUM_PARTITIONS ||
2956 index + num_entries > FCRAM_SIZE)
2957 return -EINVAL;
2958
2959 nw64(HASH_TBL_ADDR(partition), val);
2960 for (i = 0; i < num_entries; i++)
2961 data[i] = nr64(HASH_TBL_DATA(partition));
2962
2963 return 0;
2964}
2965#endif
2966
2967static int hash_write(struct niu *np, unsigned long partition,
2968 unsigned long index, unsigned long num_entries,
2969 u64 *data)
2970{
2971 u64 val = hash_addr_regval(index, num_entries);
2972 unsigned long i;
2973
2974 if (partition >= FCRAM_NUM_PARTITIONS ||
2975 index + (num_entries * 8) > FCRAM_SIZE)
2976 return -EINVAL;
2977
2978 nw64(HASH_TBL_ADDR(partition), val);
2979 for (i = 0; i < num_entries; i++)
2980 nw64(HASH_TBL_DATA(partition), data[i]);
2981
2982 return 0;
2983}
2984
2985static void fflp_reset(struct niu *np)
2986{
2987 u64 val;
2988
2989 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
2990 udelay(10);
2991 nw64(FFLP_CFG_1, 0);
2992
2993 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
2994 nw64(FFLP_CFG_1, val);
2995}
2996
2997static void fflp_set_timings(struct niu *np)
2998{
2999 u64 val = nr64(FFLP_CFG_1);
3000
3001 val &= ~FFLP_CFG_1_FFLPINITDONE;
3002 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3003 nw64(FFLP_CFG_1, val);
3004
3005 val = nr64(FFLP_CFG_1);
3006 val |= FFLP_CFG_1_FFLPINITDONE;
3007 nw64(FFLP_CFG_1, val);
3008
3009 val = nr64(FCRAM_REF_TMR);
3010 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3011 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3012 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3013 nw64(FCRAM_REF_TMR, val);
3014}
3015
3016static int fflp_set_partition(struct niu *np, u64 partition,
3017 u64 mask, u64 base, int enable)
3018{
3019 unsigned long reg;
3020 u64 val;
3021
3022 if (partition >= FCRAM_NUM_PARTITIONS ||
3023 (mask & ~(u64)0x1f) != 0 ||
3024 (base & ~(u64)0x1f) != 0)
3025 return -EINVAL;
3026
3027 reg = FLW_PRT_SEL(partition);
3028
3029 val = nr64(reg);
3030 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3031 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3032 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3033 if (enable)
3034 val |= FLW_PRT_SEL_EXT;
3035 nw64(reg, val);
3036
3037 return 0;
3038}
3039
3040static int fflp_disable_all_partitions(struct niu *np)
3041{
3042 unsigned long i;
3043
3044 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3045 int err = fflp_set_partition(np, 0, 0, 0, 0);
3046 if (err)
3047 return err;
3048 }
3049 return 0;
3050}
3051
3052static void fflp_llcsnap_enable(struct niu *np, int on)
3053{
3054 u64 val = nr64(FFLP_CFG_1);
3055
3056 if (on)
3057 val |= FFLP_CFG_1_LLCSNAP;
3058 else
3059 val &= ~FFLP_CFG_1_LLCSNAP;
3060 nw64(FFLP_CFG_1, val);
3061}
3062
3063static void fflp_errors_enable(struct niu *np, int on)
3064{
3065 u64 val = nr64(FFLP_CFG_1);
3066
3067 if (on)
3068 val &= ~FFLP_CFG_1_ERRORDIS;
3069 else
3070 val |= FFLP_CFG_1_ERRORDIS;
3071 nw64(FFLP_CFG_1, val);
3072}
3073
3074static int fflp_hash_clear(struct niu *np)
3075{
3076 struct fcram_hash_ipv4 ent;
3077 unsigned long i;
3078
3079 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3080 memset(&ent, 0, sizeof(ent));
3081 ent.header = HASH_HEADER_EXT;
3082
3083 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3084 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3085 if (err)
3086 return err;
3087 }
3088 return 0;
3089}
3090
3091static int fflp_early_init(struct niu *np)
3092{
3093 struct niu_parent *parent;
3094 unsigned long flags;
3095 int err;
3096
3097 niu_lock_parent(np, flags);
3098
3099 parent = np->parent;
3100 err = 0;
3101 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3102 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
3103 np->port);
3104 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3105 fflp_reset(np);
3106 fflp_set_timings(np);
3107 err = fflp_disable_all_partitions(np);
3108 if (err) {
3109 niudbg(PROBE, "fflp_disable_all_partitions "
3110 "failed, err=%d\n", err);
3111 goto out;
3112 }
3113 }
3114
3115 err = tcam_early_init(np);
3116 if (err) {
3117 niudbg(PROBE, "tcam_early_init failed, err=%d\n",
3118 err);
3119 goto out;
3120 }
3121 fflp_llcsnap_enable(np, 1);
3122 fflp_errors_enable(np, 0);
3123 nw64(H1POLY, 0);
3124 nw64(H2POLY, 0);
3125
3126 err = tcam_flush_all(np);
3127 if (err) {
3128 niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
3129 err);
3130 goto out;
3131 }
3132 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3133 err = fflp_hash_clear(np);
3134 if (err) {
3135 niudbg(PROBE, "fflp_hash_clear failed, "
3136 "err=%d\n", err);
3137 goto out;
3138 }
3139 }
3140
3141 vlan_tbl_clear(np);
3142
3143 niudbg(PROBE, "fflp_early_init: Success\n");
3144 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3145 }
3146out:
3147 niu_unlock_parent(np, flags);
3148 return err;
3149}
3150
3151static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3152{
3153 if (class_code < CLASS_CODE_USER_PROG1 ||
3154 class_code > CLASS_CODE_SCTP_IPV6)
3155 return -EINVAL;
3156
3157 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3158 return 0;
3159}
3160
3161static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3162{
3163 if (class_code < CLASS_CODE_USER_PROG1 ||
3164 class_code > CLASS_CODE_SCTP_IPV6)
3165 return -EINVAL;
3166
3167 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3168 return 0;
3169}
3170
3171static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3172 u32 offset, u32 size)
3173{
3174 int i = skb_shinfo(skb)->nr_frags;
3175 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3176
3177 frag->page = page;
3178 frag->page_offset = offset;
3179 frag->size = size;
3180
3181 skb->len += size;
3182 skb->data_len += size;
3183 skb->truesize += size;
3184
3185 skb_shinfo(skb)->nr_frags = i + 1;
3186}
3187
3188static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3189{
3190 a >>= PAGE_SHIFT;
3191 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3192
3193 return (a & (MAX_RBR_RING_SIZE - 1));
3194}
3195
3196static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3197 struct page ***link)
3198{
3199 unsigned int h = niu_hash_rxaddr(rp, addr);
3200 struct page *p, **pp;
3201
3202 addr &= PAGE_MASK;
3203 pp = &rp->rxhash[h];
3204 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3205 if (p->index == addr) {
3206 *link = pp;
3207 break;
3208 }
3209 }
3210
3211 return p;
3212}
3213
3214static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3215{
3216 unsigned int h = niu_hash_rxaddr(rp, base);
3217
3218 page->index = base;
3219 page->mapping = (struct address_space *) rp->rxhash[h];
3220 rp->rxhash[h] = page;
3221}
3222
3223static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3224 gfp_t mask, int start_index)
3225{
3226 struct page *page;
3227 u64 addr;
3228 int i;
3229
3230 page = alloc_page(mask);
3231 if (!page)
3232 return -ENOMEM;
3233
3234 addr = np->ops->map_page(np->device, page, 0,
3235 PAGE_SIZE, DMA_FROM_DEVICE);
3236
3237 niu_hash_page(rp, page, addr);
3238 if (rp->rbr_blocks_per_page > 1)
3239 atomic_add(rp->rbr_blocks_per_page - 1,
3240 &compound_head(page)->_count);
3241
3242 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3243 __le32 *rbr = &rp->rbr[start_index + i];
3244
3245 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3246 addr += rp->rbr_block_size;
3247 }
3248
3249 return 0;
3250}
3251
3252static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3253{
3254 int index = rp->rbr_index;
3255
3256 rp->rbr_pending++;
3257 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3258 int err = niu_rbr_add_page(np, rp, mask, index);
3259
3260 if (unlikely(err)) {
3261 rp->rbr_pending--;
3262 return;
3263 }
3264
3265 rp->rbr_index += rp->rbr_blocks_per_page;
3266 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3267 if (rp->rbr_index == rp->rbr_table_size)
3268 rp->rbr_index = 0;
3269
3270 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3271 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3272 rp->rbr_pending = 0;
3273 }
3274 }
3275}
3276
3277static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3278{
3279 unsigned int index = rp->rcr_index;
3280 int num_rcr = 0;
3281
3282 rp->rx_dropped++;
3283 while (1) {
3284 struct page *page, **link;
3285 u64 addr, val;
3286 u32 rcr_size;
3287
3288 num_rcr++;
3289
3290 val = le64_to_cpup(&rp->rcr[index]);
3291 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3292 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3293 page = niu_find_rxpage(rp, addr, &link);
3294
3295 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3296 RCR_ENTRY_PKTBUFSZ_SHIFT];
3297 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3298 *link = (struct page *) page->mapping;
3299 np->ops->unmap_page(np->device, page->index,
3300 PAGE_SIZE, DMA_FROM_DEVICE);
3301 page->index = 0;
3302 page->mapping = NULL;
3303 __free_page(page);
3304 rp->rbr_refill_pending++;
3305 }
3306
3307 index = NEXT_RCR(rp, index);
3308 if (!(val & RCR_ENTRY_MULTI))
3309 break;
3310
3311 }
3312 rp->rcr_index = index;
3313
3314 return num_rcr;
3315}
3316
3317static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
3318{
3319 unsigned int index = rp->rcr_index;
3320 struct sk_buff *skb;
3321 int len, num_rcr;
3322
3323 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3324 if (unlikely(!skb))
3325 return niu_rx_pkt_ignore(np, rp);
3326
3327 num_rcr = 0;
3328 while (1) {
3329 struct page *page, **link;
3330 u32 rcr_size, append_size;
3331 u64 addr, val, off;
3332
3333 num_rcr++;
3334
3335 val = le64_to_cpup(&rp->rcr[index]);
3336
3337 len = (val & RCR_ENTRY_L2_LEN) >>
3338 RCR_ENTRY_L2_LEN_SHIFT;
3339 len -= ETH_FCS_LEN;
3340
3341 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3342 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3343 page = niu_find_rxpage(rp, addr, &link);
3344
3345 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3346 RCR_ENTRY_PKTBUFSZ_SHIFT];
3347
3348 off = addr & ~PAGE_MASK;
3349 append_size = rcr_size;
3350 if (num_rcr == 1) {
3351 int ptype;
3352
3353 off += 2;
3354 append_size -= 2;
3355
3356 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3357 if ((ptype == RCR_PKT_TYPE_TCP ||
3358 ptype == RCR_PKT_TYPE_UDP) &&
3359 !(val & (RCR_ENTRY_NOPORT |
3360 RCR_ENTRY_ERROR)))
3361 skb->ip_summed = CHECKSUM_UNNECESSARY;
3362 else
3363 skb->ip_summed = CHECKSUM_NONE;
3364 }
3365 if (!(val & RCR_ENTRY_MULTI))
3366 append_size = len - skb->len;
3367
3368 niu_rx_skb_append(skb, page, off, append_size);
3369 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3370 *link = (struct page *) page->mapping;
3371 np->ops->unmap_page(np->device, page->index,
3372 PAGE_SIZE, DMA_FROM_DEVICE);
3373 page->index = 0;
3374 page->mapping = NULL;
3375 rp->rbr_refill_pending++;
3376 } else
3377 get_page(page);
3378
3379 index = NEXT_RCR(rp, index);
3380 if (!(val & RCR_ENTRY_MULTI))
3381 break;
3382
3383 }
3384 rp->rcr_index = index;
3385
3386 skb_reserve(skb, NET_IP_ALIGN);
3387 __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3388
3389 rp->rx_packets++;
3390 rp->rx_bytes += skb->len;
3391
3392 skb->protocol = eth_type_trans(skb, np->dev);
3393 netif_receive_skb(skb);
3394
3395 return num_rcr;
3396}
3397
3398static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3399{
3400 int blocks_per_page = rp->rbr_blocks_per_page;
3401 int err, index = rp->rbr_index;
3402
3403 err = 0;
3404 while (index < (rp->rbr_table_size - blocks_per_page)) {
3405 err = niu_rbr_add_page(np, rp, mask, index);
3406 if (err)
3407 break;
3408
3409 index += blocks_per_page;
3410 }
3411
3412 rp->rbr_index = index;
3413 return err;
3414}
3415
3416static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3417{
3418 int i;
3419
3420 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3421 struct page *page;
3422
3423 page = rp->rxhash[i];
3424 while (page) {
3425 struct page *next = (struct page *) page->mapping;
3426 u64 base = page->index;
3427
3428 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3429 DMA_FROM_DEVICE);
3430 page->index = 0;
3431 page->mapping = NULL;
3432
3433 __free_page(page);
3434
3435 page = next;
3436 }
3437 }
3438
3439 for (i = 0; i < rp->rbr_table_size; i++)
3440 rp->rbr[i] = cpu_to_le32(0);
3441 rp->rbr_index = 0;
3442}
3443
3444static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3445{
3446 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3447 struct sk_buff *skb = tb->skb;
3448 struct tx_pkt_hdr *tp;
3449 u64 tx_flags;
3450 int i, len;
3451
3452 tp = (struct tx_pkt_hdr *) skb->data;
3453 tx_flags = le64_to_cpup(&tp->flags);
3454
3455 rp->tx_packets++;
3456 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3457 ((tx_flags & TXHDR_PAD) / 2));
3458
3459 len = skb_headlen(skb);
3460 np->ops->unmap_single(np->device, tb->mapping,
3461 len, DMA_TO_DEVICE);
3462
3463 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3464 rp->mark_pending--;
3465
3466 tb->skb = NULL;
3467 do {
3468 idx = NEXT_TX(rp, idx);
3469 len -= MAX_TX_DESC_LEN;
3470 } while (len > 0);
3471
3472 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3473 tb = &rp->tx_buffs[idx];
3474 BUG_ON(tb->skb != NULL);
3475 np->ops->unmap_page(np->device, tb->mapping,
3476 skb_shinfo(skb)->frags[i].size,
3477 DMA_TO_DEVICE);
3478 idx = NEXT_TX(rp, idx);
3479 }
3480
3481 dev_kfree_skb(skb);
3482
3483 return idx;
3484}
3485
3486#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3487
3488static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3489{
b4c21639 3490 struct netdev_queue *txq;
a3138df9 3491 u16 pkt_cnt, tmp;
b4c21639 3492 int cons, index;
a3138df9
DM		 3493 u64 cs;
3494
b4c21639
DM		 3495 index = (rp - np->tx_rings);
3496 txq = netdev_get_tx_queue(np->dev, index);
3497
a3138df9
DM		 3498 cs = rp->tx_cs;
3499 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3500 goto out;
3501
3502 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3503 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3504 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3505
3506 rp->last_pkt_cnt = tmp;
3507
3508 cons = rp->cons;
3509
3510 niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3511 np->dev->name, pkt_cnt, cons);
3512
3513 while (pkt_cnt--)
3514 cons = release_tx_packet(np, rp, cons);
3515
3516 rp->cons = cons;
3517 smp_mb();
3518
3519out:
b4c21639 3520 if (unlikely(netif_tx_queue_stopped(txq) &&
a3138df9 3521 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
b4c21639
DM		 3522 __netif_tx_lock(txq, smp_processor_id());
3523 if (netif_tx_queue_stopped(txq) &&
a3138df9 3524 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
b4c21639
DM		 3525 netif_tx_wake_queue(txq);
3526 __netif_tx_unlock(txq);
a3138df9
DM		 3527 }
3528}
3529
3530static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
3531{
3532 int qlen, rcr_done = 0, work_done = 0;
3533 struct rxdma_mailbox *mbox = rp->mbox;
3534 u64 stat;
3535
3536#if 1
3537 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3538 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3539#else
3540 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3541 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3542#endif
3543 mbox->rx_dma_ctl_stat = 0;
3544 mbox->rcrstat_a = 0;
3545
3546 niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3547 np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3548
3549 rcr_done = work_done = 0;
3550 qlen = min(qlen, budget);
3551 while (work_done < qlen) {
3552 rcr_done += niu_process_rx_pkt(np, rp);
3553 work_done++;
3554 }
3555
3556 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3557 unsigned int i;
3558
3559 for (i = 0; i < rp->rbr_refill_pending; i++)
3560 niu_rbr_refill(np, rp, GFP_ATOMIC);
3561 rp->rbr_refill_pending = 0;
3562 }
3563
3564 stat = (RX_DMA_CTL_STAT_MEX |
3565 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3566 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3567
3568 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3569
3570 return work_done;
3571}
3572
3573static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3574{
3575 u64 v0 = lp->v0;
3576 u32 tx_vec = (v0 >> 32);
3577 u32 rx_vec = (v0 & 0xffffffff);
3578 int i, work_done = 0;
3579
3580 niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3581 np->dev->name, (unsigned long long) v0);
3582
3583 for (i = 0; i < np->num_tx_rings; i++) {
3584 struct tx_ring_info *rp = &np->tx_rings[i];
3585 if (tx_vec & (1 << rp->tx_channel))
3586 niu_tx_work(np, rp);
3587 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3588 }
3589
3590 for (i = 0; i < np->num_rx_rings; i++) {
3591 struct rx_ring_info *rp = &np->rx_rings[i];
3592
3593 if (rx_vec & (1 << rp->rx_channel)) {
3594 int this_work_done;
3595
3596 this_work_done = niu_rx_work(np, rp,
3597 budget);
3598
3599 budget -= this_work_done;
3600 work_done += this_work_done;
3601 }
3602 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3603 }
3604
3605 return work_done;
3606}
3607
3608static int niu_poll(struct napi_struct *napi, int budget)
3609{
3610 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3611 struct niu *np = lp->np;
3612 int work_done;
3613
3614 work_done = niu_poll_core(np, lp, budget);
3615
3616 if (work_done < budget) {
3617 netif_rx_complete(np->dev, napi);
3618 niu_ldg_rearm(np, lp, 1);
3619 }
3620 return work_done;
3621}
3622
3623static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3624 u64 stat)
3625{
3626 dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3627 np->dev->name, rp->rx_channel);
3628
3629 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3630 printk("RBR_TMOUT ");
3631 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3632 printk("RSP_CNT ");
3633 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3634 printk("BYTE_EN_BUS ");
3635 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3636 printk("RSP_DAT ");
3637 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3638 printk("RCR_ACK ");
3639 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3640 printk("RCR_SHA_PAR ");
3641 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3642 printk("RBR_PRE_PAR ");
3643 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3644 printk("CONFIG ");
3645 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3646 printk("RCRINCON ");
3647 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3648 printk("RCRFULL ");
3649 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3650 printk("RBRFULL ");
3651 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3652 printk("RBRLOGPAGE ");
3653 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3654 printk("CFIGLOGPAGE ");
3655 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3656 printk("DC_FIDO ");
3657
3658 printk(")\n");
3659}
3660
3661static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3662{
3663 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3664 int err = 0;
3665
a3138df9
DM		 3666
3667 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3668 RX_DMA_CTL_STAT_PORT_FATAL))
3669 err = -EINVAL;
3670
406f353c
MW		 3671 if (err) {
3672 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3673 np->dev->name, rp->rx_channel,
3674 (unsigned long long) stat);
3675
3676 niu_log_rxchan_errors(np, rp, stat);
3677 }
3678
a3138df9
DM		 3679 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3680 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3681
3682 return err;
3683}
3684
3685static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3686 u64 cs)
3687{
3688 dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3689 np->dev->name, rp->tx_channel);
3690
3691 if (cs & TX_CS_MBOX_ERR)
3692 printk("MBOX ");
3693 if (cs & TX_CS_PKT_SIZE_ERR)
3694 printk("PKT_SIZE ");
3695 if (cs & TX_CS_TX_RING_OFLOW)
3696 printk("TX_RING_OFLOW ");
3697 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3698 printk("PREF_BUF_PAR ");
3699 if (cs & TX_CS_NACK_PREF)
3700 printk("NACK_PREF ");
3701 if (cs & TX_CS_NACK_PKT_RD)
3702 printk("NACK_PKT_RD ");
3703 if (cs & TX_CS_CONF_PART_ERR)
3704 printk("CONF_PART ");
3705 if (cs & TX_CS_PKT_PRT_ERR)
3706 printk("PKT_PTR ");
3707
3708 printk(")\n");
3709}
3710
3711static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3712{
3713 u64 cs, logh, logl;
3714
3715 cs = nr64(TX_CS(rp->tx_channel));
3716 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3717 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3718
3719 dev_err(np->device, PFX "%s: TX channel %u error, "
3720 "cs[%llx] logh[%llx] logl[%llx]\n",
3721 np->dev->name, rp->tx_channel,
3722 (unsigned long long) cs,
3723 (unsigned long long) logh,
3724 (unsigned long long) logl);
3725
3726 niu_log_txchan_errors(np, rp, cs);
3727
3728 return -ENODEV;
3729}
3730
3731static int niu_mif_interrupt(struct niu *np)
3732{
3733 u64 mif_status = nr64(MIF_STATUS);
3734 int phy_mdint = 0;
3735
3736 if (np->flags & NIU_FLAGS_XMAC) {
3737 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3738
3739 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3740 phy_mdint = 1;
3741 }
3742
3743 dev_err(np->device, PFX "%s: MIF interrupt, "
3744 "stat[%llx] phy_mdint(%d)\n",
3745 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3746
3747 return -ENODEV;
3748}
3749
3750static void niu_xmac_interrupt(struct niu *np)
3751{
3752 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3753 u64 val;
3754
3755 val = nr64_mac(XTXMAC_STATUS);
3756 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3757 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3758 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3759 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3760 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3761 mp->tx_fifo_errors++;
3762 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3763 mp->tx_overflow_errors++;
3764 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3765 mp->tx_max_pkt_size_errors++;
3766 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3767 mp->tx_underflow_errors++;
3768
3769 val = nr64_mac(XRXMAC_STATUS);
3770 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3771 mp->rx_local_faults++;
3772 if (val & XRXMAC_STATUS_RFLT_DET)
3773 mp->rx_remote_faults++;
3774 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3775 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3776 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3777 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3778 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3779 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3780 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3781 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3782 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3783 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3784 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3785 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3786 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3787 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3788 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3789 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3790 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3791 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3792 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3793 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3794 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3795 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3796 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3797 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3798 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3799 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3800 if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3801 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3802 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3803 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3804 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3805 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3806 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3807 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3808 if (val & XRXMAC_STATUS_RXUFLOW)
3809 mp->rx_underflows++;
3810 if (val & XRXMAC_STATUS_RXOFLOW)
3811 mp->rx_overflows++;
3812
3813 val = nr64_mac(XMAC_FC_STAT);
3814 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3815 mp->pause_off_state++;
3816 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3817 mp->pause_on_state++;
3818 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3819 mp->pause_received++;
3820}
3821
3822static void niu_bmac_interrupt(struct niu *np)
3823{
3824 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3825 u64 val;
3826
3827 val = nr64_mac(BTXMAC_STATUS);
3828 if (val & BTXMAC_STATUS_UNDERRUN)
3829 mp->tx_underflow_errors++;
3830 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3831 mp->tx_max_pkt_size_errors++;
3832 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3833 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3834 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3835 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
3836
3837 val = nr64_mac(BRXMAC_STATUS);
3838 if (val & BRXMAC_STATUS_OVERFLOW)
3839 mp->rx_overflows++;
3840 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
3841 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
3842 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
3843 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3844 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
3845 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3846 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
3847 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
3848
3849 val = nr64_mac(BMAC_CTRL_STATUS);
3850 if (val & BMAC_CTRL_STATUS_NOPAUSE)
3851 mp->pause_off_state++;
3852 if (val & BMAC_CTRL_STATUS_PAUSE)
3853 mp->pause_on_state++;
3854 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
3855 mp->pause_received++;
3856}
3857
3858static int niu_mac_interrupt(struct niu *np)
3859{
3860 if (np->flags & NIU_FLAGS_XMAC)
3861 niu_xmac_interrupt(np);
3862 else
3863 niu_bmac_interrupt(np);
3864
3865 return 0;
3866}
3867
3868static void niu_log_device_error(struct niu *np, u64 stat)
3869{
3870 dev_err(np->device, PFX "%s: Core device errors ( ",
3871 np->dev->name);
3872
3873 if (stat & SYS_ERR_MASK_META2)
3874 printk("META2 ");
3875 if (stat & SYS_ERR_MASK_META1)
3876 printk("META1 ");
3877 if (stat & SYS_ERR_MASK_PEU)
3878 printk("PEU ");
3879 if (stat & SYS_ERR_MASK_TXC)
3880 printk("TXC ");
3881 if (stat & SYS_ERR_MASK_RDMC)
3882 printk("RDMC ");
3883 if (stat & SYS_ERR_MASK_TDMC)
3884 printk("TDMC ");
3885 if (stat & SYS_ERR_MASK_ZCP)
3886 printk("ZCP ");
3887 if (stat & SYS_ERR_MASK_FFLP)
3888 printk("FFLP ");
3889 if (stat & SYS_ERR_MASK_IPP)
3890 printk("IPP ");
3891 if (stat & SYS_ERR_MASK_MAC)
3892 printk("MAC ");
3893 if (stat & SYS_ERR_MASK_SMX)
3894 printk("SMX ");
3895
3896 printk(")\n");
3897}
3898
3899static int niu_device_error(struct niu *np)
3900{
3901 u64 stat = nr64(SYS_ERR_STAT);
3902
3903 dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
3904 np->dev->name, (unsigned long long) stat);
3905
3906 niu_log_device_error(np, stat);
3907
3908 return -ENODEV;
3909}
3910
406f353c
MW		 3911static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
3912 u64 v0, u64 v1, u64 v2)
a3138df9 3913{
406f353c 3914
a3138df9
DM		 3915 int i, err = 0;
3916
406f353c
MW		 3917 lp->v0 = v0;
3918 lp->v1 = v1;
3919 lp->v2 = v2;
3920
a3138df9
DM		 3921 if (v1 & 0x00000000ffffffffULL) {
3922 u32 rx_vec = (v1 & 0xffffffff);
3923
3924 for (i = 0; i < np->num_rx_rings; i++) {
3925 struct rx_ring_info *rp = &np->rx_rings[i];
3926
3927 if (rx_vec & (1 << rp->rx_channel)) {
3928 int r = niu_rx_error(np, rp);
406f353c 3929 if (r) {
a3138df9 3930 err = r;
406f353c
MW		 3931 } else {
3932 if (!v0)
3933 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3934 RX_DMA_CTL_STAT_MEX);
3935 }
a3138df9
DM		 3936 }
3937 }
3938 }
3939 if (v1 & 0x7fffffff00000000ULL) {
3940 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
3941
3942 for (i = 0; i < np->num_tx_rings; i++) {
3943 struct tx_ring_info *rp = &np->tx_rings[i];
3944
3945 if (tx_vec & (1 << rp->tx_channel)) {
3946 int r = niu_tx_error(np, rp);
3947 if (r)
3948 err = r;
3949 }
3950 }
3951 }
3952 if ((v0 | v1) & 0x8000000000000000ULL) {
3953 int r = niu_mif_interrupt(np);
3954 if (r)
3955 err = r;
3956 }
3957 if (v2) {
3958 if (v2 & 0x01ef) {
3959 int r = niu_mac_interrupt(np);
3960 if (r)
3961 err = r;
3962 }
3963 if (v2 & 0x0210) {
3964 int r = niu_device_error(np);
3965 if (r)
3966 err = r;
3967 }
3968 }
3969
3970 if (err)
3971 niu_enable_interrupts(np, 0);
3972
406f353c 3973 return err;
a3138df9
DM		 3974}
3975
3976static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
3977 int ldn)
3978{
3979 struct rxdma_mailbox *mbox = rp->mbox;
3980 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3981
3982 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
3983 RX_DMA_CTL_STAT_RCRTO);
3984 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
3985
3986 niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
3987 np->dev->name, (unsigned long long) stat);
3988}
3989
3990static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
3991 int ldn)
3992{
3993 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
3994
3995 niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
3996 np->dev->name, (unsigned long long) rp->tx_cs);
3997}
3998
3999static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4000{
4001 struct niu_parent *parent = np->parent;
4002 u32 rx_vec, tx_vec;
4003 int i;
4004
4005 tx_vec = (v0 >> 32);
4006 rx_vec = (v0 & 0xffffffff);
4007
4008 for (i = 0; i < np->num_rx_rings; i++) {
4009 struct rx_ring_info *rp = &np->rx_rings[i];
4010 int ldn = LDN_RXDMA(rp->rx_channel);
4011
4012 if (parent->ldg_map[ldn] != ldg)
4013 continue;
4014
4015 nw64(LD_IM0(ldn), LD_IM0_MASK);
4016 if (rx_vec & (1 << rp->rx_channel))
4017 niu_rxchan_intr(np, rp, ldn);
4018 }
4019
4020 for (i = 0; i < np->num_tx_rings; i++) {
4021 struct tx_ring_info *rp = &np->tx_rings[i];
4022 int ldn = LDN_TXDMA(rp->tx_channel);
4023
4024 if (parent->ldg_map[ldn] != ldg)
4025 continue;
4026
4027 nw64(LD_IM0(ldn), LD_IM0_MASK);
4028 if (tx_vec & (1 << rp->tx_channel))
4029 niu_txchan_intr(np, rp, ldn);
4030 }
4031}
4032
4033static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4034 u64 v0, u64 v1, u64 v2)
4035{
4036 if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
4037 lp->v0 = v0;
4038 lp->v1 = v1;
4039 lp->v2 = v2;
4040 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4041 __netif_rx_schedule(np->dev, &lp->napi);
4042 }
4043}
4044
4045static irqreturn_t niu_interrupt(int irq, void *dev_id)
4046{
4047 struct niu_ldg *lp = dev_id;
4048 struct niu *np = lp->np;
4049 int ldg = lp->ldg_num;
4050 unsigned long flags;
4051 u64 v0, v1, v2;
4052
4053 if (netif_msg_intr(np))
4054 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
4055 lp, ldg);
4056
4057 spin_lock_irqsave(&np->lock, flags);
4058
4059 v0 = nr64(LDSV0(ldg));
4060 v1 = nr64(LDSV1(ldg));
4061 v2 = nr64(LDSV2(ldg));
4062
4063 if (netif_msg_intr(np))
4064 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4065 (unsigned long long) v0,
4066 (unsigned long long) v1,
4067 (unsigned long long) v2);
4068
4069 if (unlikely(!v0 && !v1 && !v2)) {
4070 spin_unlock_irqrestore(&np->lock, flags);
4071 return IRQ_NONE;
4072 }
4073
4074 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
406f353c 4075 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
a3138df9
DM		 4076 if (err)
4077 goto out;
4078 }
4079 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4080 niu_schedule_napi(np, lp, v0, v1, v2);
4081 else
4082 niu_ldg_rearm(np, lp, 1);
4083out:
4084 spin_unlock_irqrestore(&np->lock, flags);
4085
4086 return IRQ_HANDLED;
4087}
4088
4089static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4090{
4091 if (rp->mbox) {
4092 np->ops->free_coherent(np->device,
4093 sizeof(struct rxdma_mailbox),
4094 rp->mbox, rp->mbox_dma);
4095 rp->mbox = NULL;
4096 }
4097 if (rp->rcr) {
4098 np->ops->free_coherent(np->device,
4099 MAX_RCR_RING_SIZE * sizeof(__le64),
4100 rp->rcr, rp->rcr_dma);
4101 rp->rcr = NULL;
4102 rp->rcr_table_size = 0;
4103 rp->rcr_index = 0;
4104 }
4105 if (rp->rbr) {
4106 niu_rbr_free(np, rp);
4107
4108 np->ops->free_coherent(np->device,
4109 MAX_RBR_RING_SIZE * sizeof(__le32),
4110 rp->rbr, rp->rbr_dma);
4111 rp->rbr = NULL;
4112 rp->rbr_table_size = 0;
4113 rp->rbr_index = 0;
4114 }
4115 kfree(rp->rxhash);
4116 rp->rxhash = NULL;
4117}
4118
4119static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4120{
4121 if (rp->mbox) {
4122 np->ops->free_coherent(np->device,
4123 sizeof(struct txdma_mailbox),
4124 rp->mbox, rp->mbox_dma);
4125 rp->mbox = NULL;
4126 }
4127 if (rp->descr) {
4128 int i;
4129
4130 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4131 if (rp->tx_buffs[i].skb)
4132 (void) release_tx_packet(np, rp, i);
4133 }
4134
4135 np->ops->free_coherent(np->device,
4136 MAX_TX_RING_SIZE * sizeof(__le64),
4137 rp->descr, rp->descr_dma);
4138 rp->descr = NULL;
4139 rp->pending = 0;
4140 rp->prod = 0;
4141 rp->cons = 0;
4142 rp->wrap_bit = 0;
4143 }
4144}
4145
4146static void niu_free_channels(struct niu *np)
4147{
4148 int i;
4149
4150 if (np->rx_rings) {
4151 for (i = 0; i < np->num_rx_rings; i++) {
4152 struct rx_ring_info *rp = &np->rx_rings[i];
4153
4154 niu_free_rx_ring_info(np, rp);
4155 }
4156 kfree(np->rx_rings);
4157 np->rx_rings = NULL;
4158 np->num_rx_rings = 0;
4159 }
4160
4161 if (np->tx_rings) {
4162 for (i = 0; i < np->num_tx_rings; i++) {
4163 struct tx_ring_info *rp = &np->tx_rings[i];
4164
4165 niu_free_tx_ring_info(np, rp);
4166 }
4167 kfree(np->tx_rings);
4168 np->tx_rings = NULL;
4169 np->num_tx_rings = 0;
4170 }
4171}
4172
4173static int niu_alloc_rx_ring_info(struct niu *np,
4174 struct rx_ring_info *rp)
4175{
4176 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4177
4178 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4179 GFP_KERNEL);
4180 if (!rp->rxhash)
4181 return -ENOMEM;
4182
4183 rp->mbox = np->ops->alloc_coherent(np->device,
4184 sizeof(struct rxdma_mailbox),
4185 &rp->mbox_dma, GFP_KERNEL);
4186 if (!rp->mbox)
4187 return -ENOMEM;
4188 if ((unsigned long)rp->mbox & (64UL - 1)) {
4189 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4190 "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
4191 return -EINVAL;
4192 }
4193
4194 rp->rcr = np->ops->alloc_coherent(np->device,
4195 MAX_RCR_RING_SIZE * sizeof(__le64),
4196 &rp->rcr_dma, GFP_KERNEL);
4197 if (!rp->rcr)
4198 return -ENOMEM;
4199 if ((unsigned long)rp->rcr & (64UL - 1)) {
4200 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4201 "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
4202 return -EINVAL;
4203 }
4204 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4205 rp->rcr_index = 0;
4206
4207 rp->rbr = np->ops->alloc_coherent(np->device,
4208 MAX_RBR_RING_SIZE * sizeof(__le32),
4209 &rp->rbr_dma, GFP_KERNEL);
4210 if (!rp->rbr)
4211 return -ENOMEM;
4212 if ((unsigned long)rp->rbr & (64UL - 1)) {
4213 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4214 "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
4215 return -EINVAL;
4216 }
4217 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4218 rp->rbr_index = 0;
4219 rp->rbr_pending = 0;
4220
4221 return 0;
4222}
4223
4224static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4225{
4226 int mtu = np->dev->mtu;
4227
4228 /* These values are recommended by the HW designers for fair
4229 * utilization of DRR amongst the rings.
4230 */
4231 rp->max_burst = mtu + 32;
4232 if (rp->max_burst > 4096)
4233 rp->max_burst = 4096;
4234}
4235
4236static int niu_alloc_tx_ring_info(struct niu *np,
4237 struct tx_ring_info *rp)
4238{
4239 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4240
4241 rp->mbox = np->ops->alloc_coherent(np->device,
4242 sizeof(struct txdma_mailbox),
4243 &rp->mbox_dma, GFP_KERNEL);
4244 if (!rp->mbox)
4245 return -ENOMEM;
4246 if ((unsigned long)rp->mbox & (64UL - 1)) {
4247 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4248 "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
4249 return -EINVAL;
4250 }
4251
4252 rp->descr = np->ops->alloc_coherent(np->device,
4253 MAX_TX_RING_SIZE * sizeof(__le64),
4254 &rp->descr_dma, GFP_KERNEL);
4255 if (!rp->descr)
4256 return -ENOMEM;
4257 if ((unsigned long)rp->descr & (64UL - 1)) {
4258 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4259 "TXDMA descr table %p\n", np->dev->name, rp->descr);
4260 return -EINVAL;
4261 }
4262
4263 rp->pending = MAX_TX_RING_SIZE;
4264 rp->prod = 0;
4265 rp->cons = 0;
4266 rp->wrap_bit = 0;
4267
4268 /* XXX make these configurable... XXX */
4269 rp->mark_freq = rp->pending / 4;
4270
4271 niu_set_max_burst(np, rp);
4272
4273 return 0;
4274}
4275
4276static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4277{
81429973 4278 u16 bss;
a3138df9 4279
81429973 4280 bss = min(PAGE_SHIFT, 15);
a3138df9 4281
81429973
OJ		 4282 rp->rbr_block_size = 1 << bss;
4283 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
a3138df9
DM		 4284
4285 rp->rbr_sizes[0] = 256;
4286 rp->rbr_sizes[1] = 1024;
4287 if (np->dev->mtu > ETH_DATA_LEN) {
4288 switch (PAGE_SIZE) {
4289 case 4 * 1024:
4290 rp->rbr_sizes[2] = 4096;
4291 break;
4292
4293 default:
4294 rp->rbr_sizes[2] = 8192;
4295 break;
4296 }
4297 } else {
4298 rp->rbr_sizes[2] = 2048;
4299 }
4300 rp->rbr_sizes[3] = rp->rbr_block_size;
4301}
4302
4303static int niu_alloc_channels(struct niu *np)
4304{
4305 struct niu_parent *parent = np->parent;
4306 int first_rx_channel, first_tx_channel;
4307 int i, port, err;
4308
4309 port = np->port;
4310 first_rx_channel = first_tx_channel = 0;
4311 for (i = 0; i < port; i++) {
4312 first_rx_channel += parent->rxchan_per_port[i];
4313 first_tx_channel += parent->txchan_per_port[i];
4314 }
4315
4316 np->num_rx_rings = parent->rxchan_per_port[port];
4317 np->num_tx_rings = parent->txchan_per_port[port];
4318
b4c21639
DM		 4319 np->dev->real_num_tx_queues = np->num_tx_rings;
4320
a3138df9
DM		 4321 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4322 GFP_KERNEL);
4323 err = -ENOMEM;
4324 if (!np->rx_rings)
4325 goto out_err;
4326
4327 for (i = 0; i < np->num_rx_rings; i++) {
4328 struct rx_ring_info *rp = &np->rx_rings[i];
4329
4330 rp->np = np;
4331 rp->rx_channel = first_rx_channel + i;
4332
4333 err = niu_alloc_rx_ring_info(np, rp);
4334 if (err)
4335 goto out_err;
4336
4337 niu_size_rbr(np, rp);
4338
4339 /* XXX better defaults, configurable, etc... XXX */
4340 rp->nonsyn_window = 64;
4341 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4342 rp->syn_window = 64;
4343 rp->syn_threshold = rp->rcr_table_size - 64;
4344 rp->rcr_pkt_threshold = 16;
4345 rp->rcr_timeout = 8;
4346 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4347 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4348 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4349
4350 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4351 if (err)
4352 return err;
4353 }
4354
4355 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4356 GFP_KERNEL);
4357 err = -ENOMEM;
4358 if (!np->tx_rings)
4359 goto out_err;
4360
4361 for (i = 0; i < np->num_tx_rings; i++) {
4362 struct tx_ring_info *rp = &np->tx_rings[i];
4363
4364 rp->np = np;
4365 rp->tx_channel = first_tx_channel + i;
4366
4367 err = niu_alloc_tx_ring_info(np, rp);
4368 if (err)
4369 goto out_err;
4370 }
4371
4372 return 0;
4373
4374out_err:
4375 niu_free_channels(np);
4376 return err;
4377}
4378
4379static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4380{
4381 int limit = 1000;
4382
4383 while (--limit > 0) {
4384 u64 val = nr64(TX_CS(channel));
4385 if (val & TX_CS_SNG_STATE)
4386 return 0;
4387 }
4388 return -ENODEV;
4389}
4390
4391static int niu_tx_channel_stop(struct niu *np, int channel)
4392{
4393 u64 val = nr64(TX_CS(channel));
4394
4395 val |= TX_CS_STOP_N_GO;
4396 nw64(TX_CS(channel), val);
4397
4398 return niu_tx_cs_sng_poll(np, channel);
4399}
4400
4401static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4402{
4403 int limit = 1000;
4404
4405 while (--limit > 0) {
4406 u64 val = nr64(TX_CS(channel));
4407 if (!(val & TX_CS_RST))
4408 return 0;
4409 }
4410 return -ENODEV;
4411}
4412
4413static int niu_tx_channel_reset(struct niu *np, int channel)
4414{
4415 u64 val = nr64(TX_CS(channel));
4416 int err;
4417
4418 val |= TX_CS_RST;
4419 nw64(TX_CS(channel), val);
4420
4421 err = niu_tx_cs_reset_poll(np, channel);
4422 if (!err)
4423 nw64(TX_RING_KICK(channel), 0);
4424
4425 return err;
4426}
4427
4428static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4429{
4430 u64 val;
4431
4432 nw64(TX_LOG_MASK1(channel), 0);
4433 nw64(TX_LOG_VAL1(channel), 0);
4434 nw64(TX_LOG_MASK2(channel), 0);
4435 nw64(TX_LOG_VAL2(channel), 0);
4436 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4437 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4438 nw64(TX_LOG_PAGE_HDL(channel), 0);
4439
4440 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4441 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4442 nw64(TX_LOG_PAGE_VLD(channel), val);
4443
4444 /* XXX TXDMA 32bit mode? XXX */
4445
4446 return 0;
4447}
4448
4449static void niu_txc_enable_port(struct niu *np, int on)
4450{
4451 unsigned long flags;
4452 u64 val, mask;
4453
4454 niu_lock_parent(np, flags);
4455 val = nr64(TXC_CONTROL);
4456 mask = (u64)1 << np->port;
4457 if (on) {
4458 val |= TXC_CONTROL_ENABLE | mask;
4459 } else {
4460 val &= ~mask;
4461 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4462 val &= ~TXC_CONTROL_ENABLE;
4463 }
4464 nw64(TXC_CONTROL, val);
4465 niu_unlock_parent(np, flags);
4466}
4467
4468static void niu_txc_set_imask(struct niu *np, u64 imask)
4469{
4470 unsigned long flags;
4471 u64 val;
4472
4473 niu_lock_parent(np, flags);
4474 val = nr64(TXC_INT_MASK);
4475 val &= ~TXC_INT_MASK_VAL(np->port);
4476 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4477 niu_unlock_parent(np, flags);
4478}
4479
4480static void niu_txc_port_dma_enable(struct niu *np, int on)
4481{
4482 u64 val = 0;
4483
4484 if (on) {
4485 int i;
4486
4487 for (i = 0; i < np->num_tx_rings; i++)
4488 val |= (1 << np->tx_rings[i].tx_channel);
4489 }
4490 nw64(TXC_PORT_DMA(np->port), val);
4491}
4492
4493static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4494{
4495 int err, channel = rp->tx_channel;
4496 u64 val, ring_len;
4497
4498 err = niu_tx_channel_stop(np, channel);
4499 if (err)
4500 return err;
4501
4502 err = niu_tx_channel_reset(np, channel);
4503 if (err)
4504 return err;
4505
4506 err = niu_tx_channel_lpage_init(np, channel);
4507 if (err)
4508 return err;
4509
4510 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4511 nw64(TX_ENT_MSK(channel), 0);
4512
4513 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4514 TX_RNG_CFIG_STADDR)) {
4515 dev_err(np->device, PFX "%s: TX ring channel %d "
4516 "DMA addr (%llx) is not aligned.\n",
4517 np->dev->name, channel,
4518 (unsigned long long) rp->descr_dma);
4519 return -EINVAL;
4520 }
4521
4522 /* The length field in TX_RNG_CFIG is measured in 64-byte
4523 * blocks. rp->pending is the number of TX descriptors in
4524 * our ring, 8 bytes each, thus we divide by 8 bytes more
4525 * to get the proper value the chip wants.
4526 */
4527 ring_len = (rp->pending / 8);
4528
4529 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4530 rp->descr_dma);
4531 nw64(TX_RNG_CFIG(channel), val);
4532
4533 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4534 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4535 dev_err(np->device, PFX "%s: TX ring channel %d "
4536 "MBOX addr (%llx) is has illegal bits.\n",
4537 np->dev->name, channel,
4538 (unsigned long long) rp->mbox_dma);
4539 return -EINVAL;
4540 }
4541 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4542 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4543
4544 nw64(TX_CS(channel), 0);
4545
4546 rp->last_pkt_cnt = 0;
4547
4548 return 0;
4549}
4550
4551static void niu_init_rdc_groups(struct niu *np)
4552{
4553 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4554 int i, first_table_num = tp->first_table_num;
4555
4556 for (i = 0; i < tp->num_tables; i++) {
4557 struct rdc_table *tbl = &tp->tables[i];
4558 int this_table = first_table_num + i;
4559 int slot;
4560
4561 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4562 nw64(RDC_TBL(this_table, slot),
4563 tbl->rxdma_channel[slot]);
4564 }
4565
4566 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4567}
4568
4569static void niu_init_drr_weight(struct niu *np)
4570{
4571 int type = phy_decode(np->parent->port_phy, np->port);
4572 u64 val;
4573
4574 switch (type) {
4575 case PORT_TYPE_10G:
4576 val = PT_DRR_WEIGHT_DEFAULT_10G;
4577 break;
4578
4579 case PORT_TYPE_1G:
4580 default:
4581 val = PT_DRR_WEIGHT_DEFAULT_1G;
4582 break;
4583 }
4584 nw64(PT_DRR_WT(np->port), val);
4585}
4586
4587static int niu_init_hostinfo(struct niu *np)
4588{
4589 struct niu_parent *parent = np->parent;
4590 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4591 int i, err, num_alt = niu_num_alt_addr(np);
4592 int first_rdc_table = tp->first_table_num;
4593
4594 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4595 if (err)
4596 return err;
4597
4598 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4599 if (err)
4600 return err;
4601
4602 for (i = 0; i < num_alt; i++) {
4603 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4604 if (err)
4605 return err;
4606 }
4607
4608 return 0;
4609}
4610
4611static int niu_rx_channel_reset(struct niu *np, int channel)
4612{
4613 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4614 RXDMA_CFIG1_RST, 1000, 10,
4615 "RXDMA_CFIG1");
4616}
4617
4618static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4619{
4620 u64 val;
4621
4622 nw64(RX_LOG_MASK1(channel), 0);
4623 nw64(RX_LOG_VAL1(channel), 0);
4624 nw64(RX_LOG_MASK2(channel), 0);
4625 nw64(RX_LOG_VAL2(channel), 0);
4626 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4627 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4628 nw64(RX_LOG_PAGE_HDL(channel), 0);
4629
4630 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4631 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4632 nw64(RX_LOG_PAGE_VLD(channel), val);
4633
4634 return 0;
4635}
4636
4637static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4638{
4639 u64 val;
4640
4641 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4642 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4643 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4644 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4645 nw64(RDC_RED_PARA(rp->rx_channel), val);
4646}
4647
4648static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4649{
4650 u64 val = 0;
4651
4652 switch (rp->rbr_block_size) {
4653 case 4 * 1024:
4654 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4655 break;
4656 case 8 * 1024:
4657 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4658 break;
4659 case 16 * 1024:
4660 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4661 break;
4662 case 32 * 1024:
4663 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4664 break;
4665 default:
4666 return -EINVAL;
4667 }
4668 val |= RBR_CFIG_B_VLD2;
4669 switch (rp->rbr_sizes[2]) {
4670 case 2 * 1024:
4671 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4672 break;
4673 case 4 * 1024:
4674 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4675 break;
4676 case 8 * 1024:
4677 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4678 break;
4679 case 16 * 1024:
4680 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4681 break;
4682
4683 default:
4684 return -EINVAL;
4685 }
4686 val |= RBR_CFIG_B_VLD1;
4687 switch (rp->rbr_sizes[1]) {
4688 case 1 * 1024:
4689 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4690 break;
4691 case 2 * 1024:
4692 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4693 break;
4694 case 4 * 1024:
4695 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4696 break;
4697 case 8 * 1024:
4698 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4699 break;
4700
4701 default:
4702 return -EINVAL;
4703 }
4704 val |= RBR_CFIG_B_VLD0;
4705 switch (rp->rbr_sizes[0]) {
4706 case 256:
4707 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4708 break;
4709 case 512:
4710 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4711 break;
4712 case 1 * 1024:
4713 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4714 break;
4715 case 2 * 1024:
4716 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4717 break;
4718
4719 default:
4720 return -EINVAL;
4721 }
4722
4723 *ret = val;
4724 return 0;
4725}
4726
4727static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4728{
4729 u64 val = nr64(RXDMA_CFIG1(channel));
4730 int limit;
4731
4732 if (on)
4733 val |= RXDMA_CFIG1_EN;
4734 else
4735 val &= ~RXDMA_CFIG1_EN;
4736 nw64(RXDMA_CFIG1(channel), val);
4737
4738 limit = 1000;
4739 while (--limit > 0) {
4740 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4741 break;
4742 udelay(10);
4743 }
4744 if (limit <= 0)
4745 return -ENODEV;
4746 return 0;
4747}
4748
4749static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4750{
4751 int err, channel = rp->rx_channel;
4752 u64 val;
4753
4754 err = niu_rx_channel_reset(np, channel);
4755 if (err)
4756 return err;
4757
4758 err = niu_rx_channel_lpage_init(np, channel);
4759 if (err)
4760 return err;
4761
4762 niu_rx_channel_wred_init(np, rp);
4763
4764 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4765 nw64(RX_DMA_CTL_STAT(channel),
4766 (RX_DMA_CTL_STAT_MEX |
4767 RX_DMA_CTL_STAT_RCRTHRES |
4768 RX_DMA_CTL_STAT_RCRTO |
4769 RX_DMA_CTL_STAT_RBR_EMPTY));
4770 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4771 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4772 nw64(RBR_CFIG_A(channel),
4773 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4774 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4775 err = niu_compute_rbr_cfig_b(rp, &val);
4776 if (err)
4777 return err;
4778 nw64(RBR_CFIG_B(channel), val);
4779 nw64(RCRCFIG_A(channel),
4780 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4781 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4782 nw64(RCRCFIG_B(channel),
4783 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4784 RCRCFIG_B_ENTOUT |
4785 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4786
4787 err = niu_enable_rx_channel(np, channel, 1);
4788 if (err)
4789 return err;
4790
4791 nw64(RBR_KICK(channel), rp->rbr_index);
4792
4793 val = nr64(RX_DMA_CTL_STAT(channel));
4794 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4795 nw64(RX_DMA_CTL_STAT(channel), val);
4796
4797 return 0;
4798}
4799
4800static int niu_init_rx_channels(struct niu *np)
4801{
4802 unsigned long flags;
4803 u64 seed = jiffies_64;
4804 int err, i;
4805
4806 niu_lock_parent(np, flags);
4807 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4808 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4809 niu_unlock_parent(np, flags);
4810
4811 /* XXX RXDMA 32bit mode? XXX */
4812
4813 niu_init_rdc_groups(np);
4814 niu_init_drr_weight(np);
4815
4816 err = niu_init_hostinfo(np);
4817 if (err)
4818 return err;
4819
4820 for (i = 0; i < np->num_rx_rings; i++) {
4821 struct rx_ring_info *rp = &np->rx_rings[i];
4822
4823 err = niu_init_one_rx_channel(np, rp);
4824 if (err)
4825 return err;
4826 }
4827
4828 return 0;
4829}
4830
4831static int niu_set_ip_frag_rule(struct niu *np)
4832{
4833 struct niu_parent *parent = np->parent;
4834 struct niu_classifier *cp = &np->clas;
4835 struct niu_tcam_entry *tp;
4836 int index, err;
4837
4838 /* XXX fix this allocation scheme XXX */
4839 index = cp->tcam_index;
4840 tp = &parent->tcam[index];
4841
4842 /* Note that the noport bit is the same in both ipv4 and
4843 * ipv6 format TCAM entries.
4844 */
4845 memset(tp, 0, sizeof(*tp));
4846 tp->key[1] = TCAM_V4KEY1_NOPORT;
4847 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
4848 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
4849 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
4850 err = tcam_write(np, index, tp->key, tp->key_mask);
4851 if (err)
4852 return err;
4853 err = tcam_assoc_write(np, index, tp->assoc_data);
4854 if (err)
4855 return err;
4856
4857 return 0;
4858}
4859
4860static int niu_init_classifier_hw(struct niu *np)
4861{
4862 struct niu_parent *parent = np->parent;
4863 struct niu_classifier *cp = &np->clas;
4864 int i, err;
4865
4866 nw64(H1POLY, cp->h1_init);
4867 nw64(H2POLY, cp->h2_init);
4868
4869 err = niu_init_hostinfo(np);
4870 if (err)
4871 return err;
4872
4873 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
4874 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
4875
4876 vlan_tbl_write(np, i, np->port,
4877 vp->vlan_pref, vp->rdc_num);
4878 }
4879
4880 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
4881 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
4882
4883 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
4884 ap->rdc_num, ap->mac_pref);
4885 if (err)
4886 return err;
4887 }
4888
4889 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
4890 int index = i - CLASS_CODE_USER_PROG1;
4891
4892 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
4893 if (err)
4894 return err;
4895 err = niu_set_flow_key(np, i, parent->flow_key[index]);
4896 if (err)
4897 return err;
4898 }
4899
4900 err = niu_set_ip_frag_rule(np);
4901 if (err)
4902 return err;
4903
4904 tcam_enable(np, 1);
4905
4906 return 0;
4907}
4908
4909static int niu_zcp_write(struct niu *np, int index, u64 *data)
4910{
4911 nw64(ZCP_RAM_DATA0, data[0]);
4912 nw64(ZCP_RAM_DATA1, data[1]);
4913 nw64(ZCP_RAM_DATA2, data[2]);
4914 nw64(ZCP_RAM_DATA3, data[3]);
4915 nw64(ZCP_RAM_DATA4, data[4]);
4916 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
4917 nw64(ZCP_RAM_ACC,
4918 (ZCP_RAM_ACC_WRITE |
4919 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4920 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4921
4922 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4923 1000, 100);
4924}
4925
4926static int niu_zcp_read(struct niu *np, int index, u64 *data)
4927{
4928 int err;
4929
4930 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4931 1000, 100);
4932 if (err) {
4933 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
4934 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4935 (unsigned long long) nr64(ZCP_RAM_ACC));
4936 return err;
4937 }
4938
4939 nw64(ZCP_RAM_ACC,
4940 (ZCP_RAM_ACC_READ |
4941 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4942 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4943
4944 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4945 1000, 100);
4946 if (err) {
4947 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
4948 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4949 (unsigned long long) nr64(ZCP_RAM_ACC));
4950 return err;
4951 }
4952
4953 data[0] = nr64(ZCP_RAM_DATA0);
4954 data[1] = nr64(ZCP_RAM_DATA1);
4955 data[2] = nr64(ZCP_RAM_DATA2);
4956 data[3] = nr64(ZCP_RAM_DATA3);
4957 data[4] = nr64(ZCP_RAM_DATA4);
4958
4959 return 0;
4960}
4961
4962static void niu_zcp_cfifo_reset(struct niu *np)
4963{
4964 u64 val = nr64(RESET_CFIFO);
4965
4966 val |= RESET_CFIFO_RST(np->port);
4967 nw64(RESET_CFIFO, val);
4968 udelay(10);
4969
4970 val &= ~RESET_CFIFO_RST(np->port);
4971 nw64(RESET_CFIFO, val);
4972}
4973
4974static int niu_init_zcp(struct niu *np)
4975{
4976 u64 data[5], rbuf[5];
4977 int i, max, err;
4978
4979 if (np->parent->plat_type != PLAT_TYPE_NIU) {
4980 if (np->port == 0 || np->port == 1)
4981 max = ATLAS_P0_P1_CFIFO_ENTRIES;
4982 else
4983 max = ATLAS_P2_P3_CFIFO_ENTRIES;
4984 } else
4985 max = NIU_CFIFO_ENTRIES;
4986
4987 data[0] = 0;
4988 data[1] = 0;
4989 data[2] = 0;
4990 data[3] = 0;
4991 data[4] = 0;
4992
4993 for (i = 0; i < max; i++) {
4994 err = niu_zcp_write(np, i, data);
4995 if (err)
4996 return err;
4997 err = niu_zcp_read(np, i, rbuf);
4998 if (err)
4999 return err;
5000 }
5001
5002 niu_zcp_cfifo_reset(np);
5003 nw64(CFIFO_ECC(np->port), 0);
5004 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5005 (void) nr64(ZCP_INT_STAT);
5006 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5007
5008 return 0;
5009}
5010
5011static void niu_ipp_write(struct niu *np, int index, u64 *data)
5012{
5013 u64 val = nr64_ipp(IPP_CFIG);
5014
5015 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5016 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5017 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5018 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5019 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5020 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5021 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5022 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5023}
5024
5025static void niu_ipp_read(struct niu *np, int index, u64 *data)
5026{
5027 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5028 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5029 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5030 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5031 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5032 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5033}
5034
5035static int niu_ipp_reset(struct niu *np)
5036{
5037 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5038 1000, 100, "IPP_CFIG");
5039}
5040
5041static int niu_init_ipp(struct niu *np)
5042{
5043 u64 data[5], rbuf[5], val;
5044 int i, max, err;
5045
5046 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5047 if (np->port == 0 || np->port == 1)
5048 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5049 else
5050 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5051 } else
5052 max = NIU_DFIFO_ENTRIES;
5053
5054 data[0] = 0;
5055 data[1] = 0;
5056 data[2] = 0;
5057 data[3] = 0;
5058 data[4] = 0;
5059
5060 for (i = 0; i < max; i++) {
5061 niu_ipp_write(np, i, data);
5062 niu_ipp_read(np, i, rbuf);
5063 }
5064
5065 (void) nr64_ipp(IPP_INT_STAT);
5066 (void) nr64_ipp(IPP_INT_STAT);
5067
5068 err = niu_ipp_reset(np);
5069 if (err)
5070 return err;
5071
5072 (void) nr64_ipp(IPP_PKT_DIS);
5073 (void) nr64_ipp(IPP_BAD_CS_CNT);
5074 (void) nr64_ipp(IPP_ECC);
5075
5076 (void) nr64_ipp(IPP_INT_STAT);
5077
5078 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5079
5080 val = nr64_ipp(IPP_CFIG);
5081 val &= ~IPP_CFIG_IP_MAX_PKT;
5082 val |= (IPP_CFIG_IPP_ENABLE |
5083 IPP_CFIG_DFIFO_ECC_EN |
5084 IPP_CFIG_DROP_BAD_CRC |
5085 IPP_CFIG_CKSUM_EN |
5086 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5087 nw64_ipp(IPP_CFIG, val);
5088
5089 return 0;
5090}
5091
0c3b091b 5092static void niu_handle_led(struct niu *np, int status)
a3138df9 5093{
a3138df9 5094 u64 val;
a3138df9
DM		 5095 val = nr64_mac(XMAC_CONFIG);
5096
5097 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5098 (np->flags & NIU_FLAGS_FIBER) != 0) {
0c3b091b 5099 if (status) {
a3138df9
DM		 5100 val |= XMAC_CONFIG_LED_POLARITY;
5101 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5102 } else {
5103 val |= XMAC_CONFIG_FORCE_LED_ON;
5104 val &= ~XMAC_CONFIG_LED_POLARITY;
5105 }
5106 }
5107
0c3b091b
ML		 5108 nw64_mac(XMAC_CONFIG, val);
5109}
5110
5111static void niu_init_xif_xmac(struct niu *np)
5112{
5113 struct niu_link_config *lp = &np->link_config;
5114 u64 val;
5115
5fbd7e24
MW		 5116 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5117 val = nr64(MIF_CONFIG);
5118 val |= MIF_CONFIG_ATCA_GE;
5119 nw64(MIF_CONFIG, val);
5120 }
5121
0c3b091b 5122 val = nr64_mac(XMAC_CONFIG);
a3138df9
DM		 5123 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5124
5125 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5126
5127 if (lp->loopback_mode == LOOPBACK_MAC) {
5128 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5129 val |= XMAC_CONFIG_LOOPBACK;
5130 } else {
5131 val &= ~XMAC_CONFIG_LOOPBACK;
5132 }
5133
5134 if (np->flags & NIU_FLAGS_10G) {
5135 val &= ~XMAC_CONFIG_LFS_DISABLE;
5136 } else {
5137 val |= XMAC_CONFIG_LFS_DISABLE;
5fbd7e24
MW		 5138 if (!(np->flags & NIU_FLAGS_FIBER) &&
5139 !(np->flags & NIU_FLAGS_XCVR_SERDES))
a3138df9
DM		 5140 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5141 else
5142 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5143 }
5144
5145 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5146
5147 if (lp->active_speed == SPEED_100)
5148 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5149 else
5150 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5151
5152 nw64_mac(XMAC_CONFIG, val);
5153
5154 val = nr64_mac(XMAC_CONFIG);
5155 val &= ~XMAC_CONFIG_MODE_MASK;
5156 if (np->flags & NIU_FLAGS_10G) {
5157 val |= XMAC_CONFIG_MODE_XGMII;
5158 } else {
5159 if (lp->active_speed == SPEED_100)
5160 val |= XMAC_CONFIG_MODE_MII;
5161 else
5162 val |= XMAC_CONFIG_MODE_GMII;
5163 }
5164
5165 nw64_mac(XMAC_CONFIG, val);
5166}
5167
5168static void niu_init_xif_bmac(struct niu *np)
5169{
5170 struct niu_link_config *lp = &np->link_config;
5171 u64 val;
5172
5173 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5174
5175 if (lp->loopback_mode == LOOPBACK_MAC)
5176 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5177 else
5178 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5179
5180 if (lp->active_speed == SPEED_1000)
5181 val |= BMAC_XIF_CONFIG_GMII_MODE;
5182 else
5183 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5184
5185 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5186 BMAC_XIF_CONFIG_LED_POLARITY);
5187
5188 if (!(np->flags & NIU_FLAGS_10G) &&
5189 !(np->flags & NIU_FLAGS_FIBER) &&
5190 lp->active_speed == SPEED_100)
5191 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5192 else
5193 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5194
5195 nw64_mac(BMAC_XIF_CONFIG, val);
5196}
5197
5198static void niu_init_xif(struct niu *np)
5199{
5200 if (np->flags & NIU_FLAGS_XMAC)
5201 niu_init_xif_xmac(np);
5202 else
5203 niu_init_xif_bmac(np);
5204}
5205
5206static void niu_pcs_mii_reset(struct niu *np)
5207{
5fbd7e24 5208 int limit = 1000;
a3138df9
DM		 5209 u64 val = nr64_pcs(PCS_MII_CTL);
5210 val |= PCS_MII_CTL_RST;
5211 nw64_pcs(PCS_MII_CTL, val);
5fbd7e24
MW		 5212 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5213 udelay(100);
5214 val = nr64_pcs(PCS_MII_CTL);
5215 }
a3138df9
DM		 5216}
5217
5218static void niu_xpcs_reset(struct niu *np)
5219{
5fbd7e24 5220 int limit = 1000;
a3138df9
DM		 5221 u64 val = nr64_xpcs(XPCS_CONTROL1);
5222 val |= XPCS_CONTROL1_RESET;
5223 nw64_xpcs(XPCS_CONTROL1, val);
5fbd7e24
MW		 5224 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5225 udelay(100);
5226 val = nr64_xpcs(XPCS_CONTROL1);
5227 }
a3138df9
DM		 5228}
5229
5230static int niu_init_pcs(struct niu *np)
5231{
5232 struct niu_link_config *lp = &np->link_config;
5233 u64 val;
5234
5fbd7e24
MW		 5235 switch (np->flags & (NIU_FLAGS_10G |
5236 NIU_FLAGS_FIBER |
5237 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 5238 case NIU_FLAGS_FIBER:
5239 /* 1G fiber */
5240 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5241 nw64_pcs(PCS_DPATH_MODE, 0);
5242 niu_pcs_mii_reset(np);
5243 break;
5244
5245 case NIU_FLAGS_10G:
5246 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5fbd7e24
MW		 5247 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5248 /* 10G SERDES */
a3138df9
DM		 5249 if (!(np->flags & NIU_FLAGS_XMAC))
5250 return -EINVAL;
5251
5252 /* 10G copper or fiber */
5253 val = nr64_mac(XMAC_CONFIG);
5254 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5255 nw64_mac(XMAC_CONFIG, val);
5256
5257 niu_xpcs_reset(np);
5258
5259 val = nr64_xpcs(XPCS_CONTROL1);
5260 if (lp->loopback_mode == LOOPBACK_PHY)
5261 val |= XPCS_CONTROL1_LOOPBACK;
5262 else
5263 val &= ~XPCS_CONTROL1_LOOPBACK;
5264 nw64_xpcs(XPCS_CONTROL1, val);
5265
5266 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5267 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5268 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5269 break;
5270
5fbd7e24
MW		 5271
5272 case NIU_FLAGS_XCVR_SERDES:
5273 /* 1G SERDES */
5274 niu_pcs_mii_reset(np);
5275 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5276 nw64_pcs(PCS_DPATH_MODE, 0);
5277 break;
5278
a3138df9
DM		 5279 case 0:
5280 /* 1G copper */
5fbd7e24
MW		 5281 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5282 /* 1G RGMII FIBER */
a3138df9
DM		 5283 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5284 niu_pcs_mii_reset(np);
5285 break;
5286
5287 default:
5288 return -EINVAL;
5289 }
5290
5291 return 0;
5292}
5293
5294static int niu_reset_tx_xmac(struct niu *np)
5295{
5296 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5297 (XTXMAC_SW_RST_REG_RS |
5298 XTXMAC_SW_RST_SOFT_RST),
5299 1000, 100, "XTXMAC_SW_RST");
5300}
5301
5302static int niu_reset_tx_bmac(struct niu *np)
5303{
5304 int limit;
5305
5306 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5307 limit = 1000;
5308 while (--limit >= 0) {
5309 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5310 break;
5311 udelay(100);
5312 }
5313 if (limit < 0) {
5314 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5315 "BTXMAC_SW_RST[%llx]\n",
5316 np->port,
5317 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5318 return -ENODEV;
5319 }
5320
5321 return 0;
5322}
5323
5324static int niu_reset_tx_mac(struct niu *np)
5325{
5326 if (np->flags & NIU_FLAGS_XMAC)
5327 return niu_reset_tx_xmac(np);
5328 else
5329 return niu_reset_tx_bmac(np);
5330}
5331
5332static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5333{
5334 u64 val;
5335
5336 val = nr64_mac(XMAC_MIN);
5337 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5338 XMAC_MIN_RX_MIN_PKT_SIZE);
5339 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5340 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5341 nw64_mac(XMAC_MIN, val);
5342
5343 nw64_mac(XMAC_MAX, max);
5344
5345 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5346
5347 val = nr64_mac(XMAC_IPG);
5348 if (np->flags & NIU_FLAGS_10G) {
5349 val &= ~XMAC_IPG_IPG_XGMII;
5350 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5351 } else {
5352 val &= ~XMAC_IPG_IPG_MII_GMII;
5353 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5354 }
5355 nw64_mac(XMAC_IPG, val);
5356
5357 val = nr64_mac(XMAC_CONFIG);
5358 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5359 XMAC_CONFIG_STRETCH_MODE |
5360 XMAC_CONFIG_VAR_MIN_IPG_EN |
5361 XMAC_CONFIG_TX_ENABLE);
5362 nw64_mac(XMAC_CONFIG, val);
5363
5364 nw64_mac(TXMAC_FRM_CNT, 0);
5365 nw64_mac(TXMAC_BYTE_CNT, 0);
5366}
5367
5368static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5369{
5370 u64 val;
5371
5372 nw64_mac(BMAC_MIN_FRAME, min);
5373 nw64_mac(BMAC_MAX_FRAME, max);
5374
5375 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5376 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5377 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5378
5379 val = nr64_mac(BTXMAC_CONFIG);
5380 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5381 BTXMAC_CONFIG_ENABLE);
5382 nw64_mac(BTXMAC_CONFIG, val);
5383}
5384
5385static void niu_init_tx_mac(struct niu *np)
5386{
5387 u64 min, max;
5388
5389 min = 64;
5390 if (np->dev->mtu > ETH_DATA_LEN)
5391 max = 9216;
5392 else
5393 max = 1522;
5394
5395 /* The XMAC_MIN register only accepts values for TX min which
5396 * have the low 3 bits cleared.
5397 */
5398 BUILD_BUG_ON(min & 0x7);
5399
5400 if (np->flags & NIU_FLAGS_XMAC)
5401 niu_init_tx_xmac(np, min, max);
5402 else
5403 niu_init_tx_bmac(np, min, max);
5404}
5405
5406static int niu_reset_rx_xmac(struct niu *np)
5407{
5408 int limit;
5409
5410 nw64_mac(XRXMAC_SW_RST,
5411 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5412 limit = 1000;
5413 while (--limit >= 0) {
5414 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5415 XRXMAC_SW_RST_SOFT_RST)))
5416 break;
5417 udelay(100);
5418 }
5419 if (limit < 0) {
5420 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5421 "XRXMAC_SW_RST[%llx]\n",
5422 np->port,
5423 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5424 return -ENODEV;
5425 }
5426
5427 return 0;
5428}
5429
5430static int niu_reset_rx_bmac(struct niu *np)
5431{
5432 int limit;
5433
5434 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5435 limit = 1000;
5436 while (--limit >= 0) {
5437 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5438 break;
5439 udelay(100);
5440 }
5441 if (limit < 0) {
5442 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5443 "BRXMAC_SW_RST[%llx]\n",
5444 np->port,
5445 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5446 return -ENODEV;
5447 }
5448
5449 return 0;
5450}
5451
5452static int niu_reset_rx_mac(struct niu *np)
5453{
5454 if (np->flags & NIU_FLAGS_XMAC)
5455 return niu_reset_rx_xmac(np);
5456 else
5457 return niu_reset_rx_bmac(np);
5458}
5459
5460static void niu_init_rx_xmac(struct niu *np)
5461{
5462 struct niu_parent *parent = np->parent;
5463 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5464 int first_rdc_table = tp->first_table_num;
5465 unsigned long i;
5466 u64 val;
5467
5468 nw64_mac(XMAC_ADD_FILT0, 0);
5469 nw64_mac(XMAC_ADD_FILT1, 0);
5470 nw64_mac(XMAC_ADD_FILT2, 0);
5471 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5472 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5473 for (i = 0; i < MAC_NUM_HASH; i++)
5474 nw64_mac(XMAC_HASH_TBL(i), 0);
5475 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5476 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5477 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5478
5479 val = nr64_mac(XMAC_CONFIG);
5480 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5481 XMAC_CONFIG_PROMISCUOUS |
5482 XMAC_CONFIG_PROMISC_GROUP |
5483 XMAC_CONFIG_ERR_CHK_DIS |
5484 XMAC_CONFIG_RX_CRC_CHK_DIS |
5485 XMAC_CONFIG_RESERVED_MULTICAST |
5486 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5487 XMAC_CONFIG_ADDR_FILTER_EN |
5488 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5489 XMAC_CONFIG_STRIP_CRC |
5490 XMAC_CONFIG_PASS_FLOW_CTRL |
5491 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5492 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5493 nw64_mac(XMAC_CONFIG, val);
5494
5495 nw64_mac(RXMAC_BT_CNT, 0);
5496 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5497 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5498 nw64_mac(RXMAC_FRAG_CNT, 0);
5499 nw64_mac(RXMAC_HIST_CNT1, 0);
5500 nw64_mac(RXMAC_HIST_CNT2, 0);
5501 nw64_mac(RXMAC_HIST_CNT3, 0);
5502 nw64_mac(RXMAC_HIST_CNT4, 0);
5503 nw64_mac(RXMAC_HIST_CNT5, 0);
5504 nw64_mac(RXMAC_HIST_CNT6, 0);
5505 nw64_mac(RXMAC_HIST_CNT7, 0);
5506 nw64_mac(RXMAC_MPSZER_CNT, 0);
5507 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5508 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5509 nw64_mac(LINK_FAULT_CNT, 0);
5510}
5511
5512static void niu_init_rx_bmac(struct niu *np)
5513{
5514 struct niu_parent *parent = np->parent;
5515 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5516 int first_rdc_table = tp->first_table_num;
5517 unsigned long i;
5518 u64 val;
5519
5520 nw64_mac(BMAC_ADD_FILT0, 0);
5521 nw64_mac(BMAC_ADD_FILT1, 0);
5522 nw64_mac(BMAC_ADD_FILT2, 0);
5523 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5524 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5525 for (i = 0; i < MAC_NUM_HASH; i++)
5526 nw64_mac(BMAC_HASH_TBL(i), 0);
5527 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5528 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5529 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5530
5531 val = nr64_mac(BRXMAC_CONFIG);
5532 val &= ~(BRXMAC_CONFIG_ENABLE |
5533 BRXMAC_CONFIG_STRIP_PAD |
5534 BRXMAC_CONFIG_STRIP_FCS |
5535 BRXMAC_CONFIG_PROMISC |
5536 BRXMAC_CONFIG_PROMISC_GRP |
5537 BRXMAC_CONFIG_ADDR_FILT_EN |
5538 BRXMAC_CONFIG_DISCARD_DIS);
5539 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5540 nw64_mac(BRXMAC_CONFIG, val);
5541
5542 val = nr64_mac(BMAC_ADDR_CMPEN);
5543 val |= BMAC_ADDR_CMPEN_EN0;
5544 nw64_mac(BMAC_ADDR_CMPEN, val);
5545}
5546
5547static void niu_init_rx_mac(struct niu *np)
5548{
5549 niu_set_primary_mac(np, np->dev->dev_addr);
5550
5551 if (np->flags & NIU_FLAGS_XMAC)
5552 niu_init_rx_xmac(np);
5553 else
5554 niu_init_rx_bmac(np);
5555}
5556
5557static void niu_enable_tx_xmac(struct niu *np, int on)
5558{
5559 u64 val = nr64_mac(XMAC_CONFIG);
5560
5561 if (on)
5562 val |= XMAC_CONFIG_TX_ENABLE;
5563 else
5564 val &= ~XMAC_CONFIG_TX_ENABLE;
5565 nw64_mac(XMAC_CONFIG, val);
5566}
5567
5568static void niu_enable_tx_bmac(struct niu *np, int on)
5569{
5570 u64 val = nr64_mac(BTXMAC_CONFIG);
5571
5572 if (on)
5573 val |= BTXMAC_CONFIG_ENABLE;
5574 else
5575 val &= ~BTXMAC_CONFIG_ENABLE;
5576 nw64_mac(BTXMAC_CONFIG, val);
5577}
5578
5579static void niu_enable_tx_mac(struct niu *np, int on)
5580{
5581 if (np->flags & NIU_FLAGS_XMAC)
5582 niu_enable_tx_xmac(np, on);
5583 else
5584 niu_enable_tx_bmac(np, on);
5585}
5586
5587static void niu_enable_rx_xmac(struct niu *np, int on)
5588{
5589 u64 val = nr64_mac(XMAC_CONFIG);
5590
5591 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5592 XMAC_CONFIG_PROMISCUOUS);
5593
5594 if (np->flags & NIU_FLAGS_MCAST)
5595 val |= XMAC_CONFIG_HASH_FILTER_EN;
5596 if (np->flags & NIU_FLAGS_PROMISC)
5597 val |= XMAC_CONFIG_PROMISCUOUS;
5598
5599 if (on)
5600 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5601 else
5602 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5603 nw64_mac(XMAC_CONFIG, val);
5604}
5605
5606static void niu_enable_rx_bmac(struct niu *np, int on)
5607{
5608 u64 val = nr64_mac(BRXMAC_CONFIG);
5609
5610 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5611 BRXMAC_CONFIG_PROMISC);
5612
5613 if (np->flags & NIU_FLAGS_MCAST)
5614 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5615 if (np->flags & NIU_FLAGS_PROMISC)
5616 val |= BRXMAC_CONFIG_PROMISC;
5617
5618 if (on)
5619 val |= BRXMAC_CONFIG_ENABLE;
5620 else
5621 val &= ~BRXMAC_CONFIG_ENABLE;
5622 nw64_mac(BRXMAC_CONFIG, val);
5623}
5624
5625static void niu_enable_rx_mac(struct niu *np, int on)
5626{
5627 if (np->flags & NIU_FLAGS_XMAC)
5628 niu_enable_rx_xmac(np, on);
5629 else
5630 niu_enable_rx_bmac(np, on);
5631}
5632
5633static int niu_init_mac(struct niu *np)
5634{
5635 int err;
5636
5637 niu_init_xif(np);
5638 err = niu_init_pcs(np);
5639 if (err)
5640 return err;
5641
5642 err = niu_reset_tx_mac(np);
5643 if (err)
5644 return err;
5645 niu_init_tx_mac(np);
5646 err = niu_reset_rx_mac(np);
5647 if (err)
5648 return err;
5649 niu_init_rx_mac(np);
5650
5651 /* This looks hookey but the RX MAC reset we just did will
5652 * undo some of the state we setup in niu_init_tx_mac() so we
5653 * have to call it again. In particular, the RX MAC reset will
5654 * set the XMAC_MAX register back to it's default value.
5655 */
5656 niu_init_tx_mac(np);
5657 niu_enable_tx_mac(np, 1);
5658
5659 niu_enable_rx_mac(np, 1);
5660
5661 return 0;
5662}
5663
5664static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5665{
5666 (void) niu_tx_channel_stop(np, rp->tx_channel);
5667}
5668
5669static void niu_stop_tx_channels(struct niu *np)
5670{
5671 int i;
5672
5673 for (i = 0; i < np->num_tx_rings; i++) {
5674 struct tx_ring_info *rp = &np->tx_rings[i];
5675
5676 niu_stop_one_tx_channel(np, rp);
5677 }
5678}
5679
5680static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5681{
5682 (void) niu_tx_channel_reset(np, rp->tx_channel);
5683}
5684
5685static void niu_reset_tx_channels(struct niu *np)
5686{
5687 int i;
5688
5689 for (i = 0; i < np->num_tx_rings; i++) {
5690 struct tx_ring_info *rp = &np->tx_rings[i];
5691
5692 niu_reset_one_tx_channel(np, rp);
5693 }
5694}
5695
5696static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5697{
5698 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5699}
5700
5701static void niu_stop_rx_channels(struct niu *np)
5702{
5703 int i;
5704
5705 for (i = 0; i < np->num_rx_rings; i++) {
5706 struct rx_ring_info *rp = &np->rx_rings[i];
5707
5708 niu_stop_one_rx_channel(np, rp);
5709 }
5710}
5711
5712static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5713{
5714 int channel = rp->rx_channel;
5715
5716 (void) niu_rx_channel_reset(np, channel);
5717 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5718 nw64(RX_DMA_CTL_STAT(channel), 0);
5719 (void) niu_enable_rx_channel(np, channel, 0);
5720}
5721
5722static void niu_reset_rx_channels(struct niu *np)
5723{
5724 int i;
5725
5726 for (i = 0; i < np->num_rx_rings; i++) {
5727 struct rx_ring_info *rp = &np->rx_rings[i];
5728
5729 niu_reset_one_rx_channel(np, rp);
5730 }
5731}
5732
5733static void niu_disable_ipp(struct niu *np)
5734{
5735 u64 rd, wr, val;
5736 int limit;
5737
5738 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5739 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5740 limit = 100;
5741 while (--limit >= 0 && (rd != wr)) {
5742 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5743 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5744 }
5745 if (limit < 0 &&
5746 (rd != 0 && wr != 1)) {
5747 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5748 "rd_ptr[%llx] wr_ptr[%llx]\n",
5749 np->dev->name,
5750 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5751 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5752 }
5753
5754 val = nr64_ipp(IPP_CFIG);
5755 val &= ~(IPP_CFIG_IPP_ENABLE |
5756 IPP_CFIG_DFIFO_ECC_EN |
5757 IPP_CFIG_DROP_BAD_CRC |
5758 IPP_CFIG_CKSUM_EN);
5759 nw64_ipp(IPP_CFIG, val);
5760
5761 (void) niu_ipp_reset(np);
5762}
5763
5764static int niu_init_hw(struct niu *np)
5765{
5766 int i, err;
5767
5768 niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5769 niu_txc_enable_port(np, 1);
5770 niu_txc_port_dma_enable(np, 1);
5771 niu_txc_set_imask(np, 0);
5772
5773 niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5774 for (i = 0; i < np->num_tx_rings; i++) {
5775 struct tx_ring_info *rp = &np->tx_rings[i];
5776
5777 err = niu_init_one_tx_channel(np, rp);
5778 if (err)
5779 return err;
5780 }
5781
5782 niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5783 err = niu_init_rx_channels(np);
5784 if (err)
5785 goto out_uninit_tx_channels;
5786
5787 niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5788 err = niu_init_classifier_hw(np);
5789 if (err)
5790 goto out_uninit_rx_channels;
5791
5792 niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5793 err = niu_init_zcp(np);
5794 if (err)
5795 goto out_uninit_rx_channels;
5796
5797 niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5798 err = niu_init_ipp(np);
5799 if (err)
5800 goto out_uninit_rx_channels;
5801
5802 niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5803 err = niu_init_mac(np);
5804 if (err)
5805 goto out_uninit_ipp;
5806
5807 return 0;
5808
5809out_uninit_ipp:
5810 niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5811 niu_disable_ipp(np);
5812
5813out_uninit_rx_channels:
5814 niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
5815 niu_stop_rx_channels(np);
5816 niu_reset_rx_channels(np);
5817
5818out_uninit_tx_channels:
5819 niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
5820 niu_stop_tx_channels(np);
5821 niu_reset_tx_channels(np);
5822
5823 return err;
5824}
5825
5826static void niu_stop_hw(struct niu *np)
5827{
5828 niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
5829 niu_enable_interrupts(np, 0);
5830
5831 niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
5832 niu_enable_rx_mac(np, 0);
5833
5834 niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
5835 niu_disable_ipp(np);
5836
5837 niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
5838 niu_stop_tx_channels(np);
5839
5840 niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
5841 niu_stop_rx_channels(np);
5842
5843 niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
5844 niu_reset_tx_channels(np);
5845
5846 niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
5847 niu_reset_rx_channels(np);
5848}
5849
70340d72
RO		 5850static void niu_set_irq_name(struct niu *np)
5851{
5852 int port = np->port;
5853 int i, j = 1;
5854
5855 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
5856
5857 if (port == 0) {
5858 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
5859 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
5860 j = 3;
5861 }
5862
5863 for (i = 0; i < np->num_ldg - j; i++) {
5864 if (i < np->num_rx_rings)
5865 sprintf(np->irq_name[i+j], "%s-rx-%d",
5866 np->dev->name, i);
5867 else if (i < np->num_tx_rings + np->num_rx_rings)
5868 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
5869 i - np->num_rx_rings);
5870 }
5871}
5872
a3138df9
DM		 5873static int niu_request_irq(struct niu *np)
5874{
5875 int i, j, err;
5876
70340d72
RO		 5877 niu_set_irq_name(np);
5878
a3138df9
DM		 5879 err = 0;
5880 for (i = 0; i < np->num_ldg; i++) {
5881 struct niu_ldg *lp = &np->ldg[i];
5882
5883 err = request_irq(lp->irq, niu_interrupt,
5884 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
70340d72 5885 np->irq_name[i], lp);
a3138df9
DM		 5886 if (err)
5887 goto out_free_irqs;
5888
5889 }
5890
5891 return 0;
5892
5893out_free_irqs:
5894 for (j = 0; j < i; j++) {
5895 struct niu_ldg *lp = &np->ldg[j];
5896
5897 free_irq(lp->irq, lp);
5898 }
5899 return err;
5900}
5901
5902static void niu_free_irq(struct niu *np)
5903{
5904 int i;
5905
5906 for (i = 0; i < np->num_ldg; i++) {
5907 struct niu_ldg *lp = &np->ldg[i];
5908
5909 free_irq(lp->irq, lp);
5910 }
5911}
5912
5913static void niu_enable_napi(struct niu *np)
5914{
5915 int i;
5916
5917 for (i = 0; i < np->num_ldg; i++)
5918 napi_enable(&np->ldg[i].napi);
5919}
5920
5921static void niu_disable_napi(struct niu *np)
5922{
5923 int i;
5924
5925 for (i = 0; i < np->num_ldg; i++)
5926 napi_disable(&np->ldg[i].napi);
5927}
5928
5929static int niu_open(struct net_device *dev)
5930{
5931 struct niu *np = netdev_priv(dev);
5932 int err;
5933
5934 netif_carrier_off(dev);
5935
5936 err = niu_alloc_channels(np);
5937 if (err)
5938 goto out_err;
5939
5940 err = niu_enable_interrupts(np, 0);
5941 if (err)
5942 goto out_free_channels;
5943
5944 err = niu_request_irq(np);
5945 if (err)
5946 goto out_free_channels;
5947
5948 niu_enable_napi(np);
5949
5950 spin_lock_irq(&np->lock);
5951
5952 err = niu_init_hw(np);
5953 if (!err) {
5954 init_timer(&np->timer);
5955 np->timer.expires = jiffies + HZ;
5956 np->timer.data = (unsigned long) np;
5957 np->timer.function = niu_timer;
5958
5959 err = niu_enable_interrupts(np, 1);
5960 if (err)
5961 niu_stop_hw(np);
5962 }
5963
5964 spin_unlock_irq(&np->lock);
5965
5966 if (err) {
5967 niu_disable_napi(np);
5968 goto out_free_irq;
5969 }
5970
b4c21639 5971 netif_tx_start_all_queues(dev);
a3138df9
DM		 5972
5973 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
5974 netif_carrier_on(dev);
5975
5976 add_timer(&np->timer);
5977
5978 return 0;
5979
5980out_free_irq:
5981 niu_free_irq(np);
5982
5983out_free_channels:
5984 niu_free_channels(np);
5985
5986out_err:
5987 return err;
5988}
5989
5990static void niu_full_shutdown(struct niu *np, struct net_device *dev)
5991{
5992 cancel_work_sync(&np->reset_task);
5993
5994 niu_disable_napi(np);
b4c21639 5995 netif_tx_stop_all_queues(dev);
a3138df9
DM		 5996
5997 del_timer_sync(&np->timer);
5998
5999 spin_lock_irq(&np->lock);
6000
6001 niu_stop_hw(np);
6002
6003 spin_unlock_irq(&np->lock);
6004}
6005
6006static int niu_close(struct net_device *dev)
6007{
6008 struct niu *np = netdev_priv(dev);
6009
6010 niu_full_shutdown(np, dev);
6011
6012 niu_free_irq(np);
6013
6014 niu_free_channels(np);
6015
0c3b091b
ML		 6016 niu_handle_led(np, 0);
6017
a3138df9
DM		 6018 return 0;
6019}
6020
6021static void niu_sync_xmac_stats(struct niu *np)
6022{
6023 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6024
6025 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6026 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6027
6028 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6029 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6030 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6031 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6032 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6033 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6034 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6035 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6036 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6037 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6038 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6039 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6040 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6041 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6042 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6043 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6044}
6045
6046static void niu_sync_bmac_stats(struct niu *np)
6047{
6048 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6049
6050 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6051 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6052
6053 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6054 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6055 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6056 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6057}
6058
6059static void niu_sync_mac_stats(struct niu *np)
6060{
6061 if (np->flags & NIU_FLAGS_XMAC)
6062 niu_sync_xmac_stats(np);
6063 else
6064 niu_sync_bmac_stats(np);
6065}
6066
6067static void niu_get_rx_stats(struct niu *np)
6068{
6069 unsigned long pkts, dropped, errors, bytes;
6070 int i;
6071
6072 pkts = dropped = errors = bytes = 0;
6073 for (i = 0; i < np->num_rx_rings; i++) {
6074 struct rx_ring_info *rp = &np->rx_rings[i];
6075
6076 pkts += rp->rx_packets;
6077 bytes += rp->rx_bytes;
6078 dropped += rp->rx_dropped;
6079 errors += rp->rx_errors;
6080 }
6081 np->net_stats.rx_packets = pkts;
6082 np->net_stats.rx_bytes = bytes;
6083 np->net_stats.rx_dropped = dropped;
6084 np->net_stats.rx_errors = errors;
6085}
6086
6087static void niu_get_tx_stats(struct niu *np)
6088{
6089 unsigned long pkts, errors, bytes;
6090 int i;
6091
6092 pkts = errors = bytes = 0;
6093 for (i = 0; i < np->num_tx_rings; i++) {
6094 struct tx_ring_info *rp = &np->tx_rings[i];
6095
6096 pkts += rp->tx_packets;
6097 bytes += rp->tx_bytes;
6098 errors += rp->tx_errors;
6099 }
6100 np->net_stats.tx_packets = pkts;
6101 np->net_stats.tx_bytes = bytes;
6102 np->net_stats.tx_errors = errors;
6103}
6104
6105static struct net_device_stats *niu_get_stats(struct net_device *dev)
6106{
6107 struct niu *np = netdev_priv(dev);
6108
6109 niu_get_rx_stats(np);
6110 niu_get_tx_stats(np);
6111
6112 return &np->net_stats;
6113}
6114
6115static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6116{
6117 int i;
6118
6119 for (i = 0; i < 16; i++)
6120 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6121}
6122
6123static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6124{
6125 int i;
6126
6127 for (i = 0; i < 16; i++)
6128 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6129}
6130
6131static void niu_load_hash(struct niu *np, u16 *hash)
6132{
6133 if (np->flags & NIU_FLAGS_XMAC)
6134 niu_load_hash_xmac(np, hash);
6135 else
6136 niu_load_hash_bmac(np, hash);
6137}
6138
6139static void niu_set_rx_mode(struct net_device *dev)
6140{
6141 struct niu *np = netdev_priv(dev);
6142 int i, alt_cnt, err;
6143 struct dev_addr_list *addr;
6144 unsigned long flags;
6145 u16 hash[16] = { 0, };
6146
6147 spin_lock_irqsave(&np->lock, flags);
6148 niu_enable_rx_mac(np, 0);
6149
6150 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6151 if (dev->flags & IFF_PROMISC)
6152 np->flags |= NIU_FLAGS_PROMISC;
6153 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
6154 np->flags |= NIU_FLAGS_MCAST;
6155
6156 alt_cnt = dev->uc_count;
6157 if (alt_cnt > niu_num_alt_addr(np)) {
6158 alt_cnt = 0;
6159 np->flags |= NIU_FLAGS_PROMISC;
6160 }
6161
6162 if (alt_cnt) {
6163 int index = 0;
6164
6165 for (addr = dev->uc_list; addr; addr = addr->next) {
6166 err = niu_set_alt_mac(np, index,
6167 addr->da_addr);
6168 if (err)
6169 printk(KERN_WARNING PFX "%s: Error %d "
6170 "adding alt mac %d\n",
6171 dev->name, err, index);
6172 err = niu_enable_alt_mac(np, index, 1);
6173 if (err)
6174 printk(KERN_WARNING PFX "%s: Error %d "
6175 "enabling alt mac %d\n",
6176 dev->name, err, index);
6177
6178 index++;
6179 }
6180 } else {
3b5bcede
MW		 6181 int alt_start;
6182 if (np->flags & NIU_FLAGS_XMAC)
6183 alt_start = 0;
6184 else
6185 alt_start = 1;
6186 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
a3138df9
DM		 6187 err = niu_enable_alt_mac(np, i, 0);
6188 if (err)
6189 printk(KERN_WARNING PFX "%s: Error %d "
6190 "disabling alt mac %d\n",
6191 dev->name, err, i);
6192 }
6193 }
6194 if (dev->flags & IFF_ALLMULTI) {
6195 for (i = 0; i < 16; i++)
6196 hash[i] = 0xffff;
6197 } else if (dev->mc_count > 0) {
6198 for (addr = dev->mc_list; addr; addr = addr->next) {
6199 u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6200
6201 crc >>= 24;
6202 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6203 }
6204 }
6205
6206 if (np->flags & NIU_FLAGS_MCAST)
6207 niu_load_hash(np, hash);
6208
6209 niu_enable_rx_mac(np, 1);
6210 spin_unlock_irqrestore(&np->lock, flags);
6211}
6212
6213static int niu_set_mac_addr(struct net_device *dev, void *p)
6214{
6215 struct niu *np = netdev_priv(dev);
6216 struct sockaddr *addr = p;
6217 unsigned long flags;
6218
6219 if (!is_valid_ether_addr(addr->sa_data))
6220 return -EINVAL;
6221
6222 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6223
6224 if (!netif_running(dev))
6225 return 0;
6226
6227 spin_lock_irqsave(&np->lock, flags);
6228 niu_enable_rx_mac(np, 0);
6229 niu_set_primary_mac(np, dev->dev_addr);
6230 niu_enable_rx_mac(np, 1);
6231 spin_unlock_irqrestore(&np->lock, flags);
6232
6233 return 0;
6234}
6235
6236static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6237{
6238 return -EOPNOTSUPP;
6239}
6240
6241static void niu_netif_stop(struct niu *np)
6242{
6243 np->dev->trans_start = jiffies; /* prevent tx timeout */
6244
6245 niu_disable_napi(np);
6246
6247 netif_tx_disable(np->dev);
6248}
6249
6250static void niu_netif_start(struct niu *np)
6251{
6252 /* NOTE: unconditional netif_wake_queue is only appropriate
6253 * so long as all callers are assured to have free tx slots
6254 * (such as after niu_init_hw).
6255 */
b4c21639 6256 netif_tx_wake_all_queues(np->dev);
a3138df9
DM		 6257
6258 niu_enable_napi(np);
6259
6260 niu_enable_interrupts(np, 1);
6261}
6262
cff502a3
SB		 6263static void niu_reset_buffers(struct niu *np)
6264{
6265 int i, j, k, err;
6266
6267 if (np->rx_rings) {
6268 for (i = 0; i < np->num_rx_rings; i++) {
6269 struct rx_ring_info *rp = &np->rx_rings[i];
6270
6271 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6272 struct page *page;
6273
6274 page = rp->rxhash[j];
6275 while (page) {
6276 struct page *next =
6277 (struct page *) page->mapping;
6278 u64 base = page->index;
6279 base = base >> RBR_DESCR_ADDR_SHIFT;
6280 rp->rbr[k++] = cpu_to_le32(base);
6281 page = next;
6282 }
6283 }
6284 for (; k < MAX_RBR_RING_SIZE; k++) {
6285 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6286 if (unlikely(err))
6287 break;
6288 }
6289
6290 rp->rbr_index = rp->rbr_table_size - 1;
6291 rp->rcr_index = 0;
6292 rp->rbr_pending = 0;
6293 rp->rbr_refill_pending = 0;
6294 }
6295 }
6296 if (np->tx_rings) {
6297 for (i = 0; i < np->num_tx_rings; i++) {
6298 struct tx_ring_info *rp = &np->tx_rings[i];
6299
6300 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6301 if (rp->tx_buffs[j].skb)
6302 (void) release_tx_packet(np, rp, j);
6303 }
6304
6305 rp->pending = MAX_TX_RING_SIZE;
6306 rp->prod = 0;
6307 rp->cons = 0;
6308 rp->wrap_bit = 0;
6309 }
6310 }
6311}
6312
a3138df9
DM		 6313static void niu_reset_task(struct work_struct *work)
6314{
6315 struct niu *np = container_of(work, struct niu, reset_task);
6316 unsigned long flags;
6317 int err;
6318
6319 spin_lock_irqsave(&np->lock, flags);
6320 if (!netif_running(np->dev)) {
6321 spin_unlock_irqrestore(&np->lock, flags);
6322 return;
6323 }
6324
6325 spin_unlock_irqrestore(&np->lock, flags);
6326
6327 del_timer_sync(&np->timer);
6328
6329 niu_netif_stop(np);
6330
6331 spin_lock_irqsave(&np->lock, flags);
6332
6333 niu_stop_hw(np);
6334
cff502a3
SB		 6335 spin_unlock_irqrestore(&np->lock, flags);
6336
6337 niu_reset_buffers(np);
6338
6339 spin_lock_irqsave(&np->lock, flags);
6340
a3138df9
DM		 6341 err = niu_init_hw(np);
6342 if (!err) {
6343 np->timer.expires = jiffies + HZ;
6344 add_timer(&np->timer);
6345 niu_netif_start(np);
6346 }
6347
6348 spin_unlock_irqrestore(&np->lock, flags);
6349}
6350
6351static void niu_tx_timeout(struct net_device *dev)
6352{
6353 struct niu *np = netdev_priv(dev);
6354
6355 dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6356 dev->name);
6357
6358 schedule_work(&np->reset_task);
6359}
6360
6361static void niu_set_txd(struct tx_ring_info *rp, int index,
6362 u64 mapping, u64 len, u64 mark,
6363 u64 n_frags)
6364{
6365 __le64 *desc = &rp->descr[index];
6366
6367 *desc = cpu_to_le64(mark |
6368 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6369 (len << TX_DESC_TR_LEN_SHIFT) |
6370 (mapping & TX_DESC_SAD));
6371}
6372
6373static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6374 u64 pad_bytes, u64 len)
6375{
6376 u16 eth_proto, eth_proto_inner;
6377 u64 csum_bits, l3off, ihl, ret;
6378 u8 ip_proto;
6379 int ipv6;
6380
6381 eth_proto = be16_to_cpu(ehdr->h_proto);
6382 eth_proto_inner = eth_proto;
6383 if (eth_proto == ETH_P_8021Q) {
6384 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6385 __be16 val = vp->h_vlan_encapsulated_proto;
6386
6387 eth_proto_inner = be16_to_cpu(val);
6388 }
6389
6390 ipv6 = ihl = 0;
6391 switch (skb->protocol) {
6392 case __constant_htons(ETH_P_IP):
6393 ip_proto = ip_hdr(skb)->protocol;
6394 ihl = ip_hdr(skb)->ihl;
6395 break;
6396 case __constant_htons(ETH_P_IPV6):
6397 ip_proto = ipv6_hdr(skb)->nexthdr;
6398 ihl = (40 >> 2);
6399 ipv6 = 1;
6400 break;
6401 default:
6402 ip_proto = ihl = 0;
6403 break;
6404 }
6405
6406 csum_bits = TXHDR_CSUM_NONE;
6407 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6408 u64 start, stuff;
6409
6410 csum_bits = (ip_proto == IPPROTO_TCP ?
6411 TXHDR_CSUM_TCP :
6412 (ip_proto == IPPROTO_UDP ?
6413 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6414
6415 start = skb_transport_offset(skb) -
6416 (pad_bytes + sizeof(struct tx_pkt_hdr));
6417 stuff = start + skb->csum_offset;
6418
6419 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6420 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6421 }
6422
6423 l3off = skb_network_offset(skb) -
6424 (pad_bytes + sizeof(struct tx_pkt_hdr));
6425
6426 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6427 (len << TXHDR_LEN_SHIFT) |
6428 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6429 (ihl << TXHDR_IHL_SHIFT) |
6430 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6431 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6432 (ipv6 ? TXHDR_IP_VER : 0) |
6433 csum_bits);
6434
6435 return ret;
6436}
6437
a3138df9
DM		 6438static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6439{
6440 struct niu *np = netdev_priv(dev);
6441 unsigned long align, headroom;
b4c21639 6442 struct netdev_queue *txq;
a3138df9
DM		 6443 struct tx_ring_info *rp;
6444 struct tx_pkt_hdr *tp;
6445 unsigned int len, nfg;
6446 struct ethhdr *ehdr;
6447 int prod, i, tlen;
6448 u64 mapping, mrk;
6449
b4c21639
DM		 6450 i = skb_get_queue_mapping(skb);
6451 rp = &np->tx_rings[i];
6452 txq = netdev_get_tx_queue(dev, i);
a3138df9
DM		 6453
6454 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
b4c21639 6455 netif_tx_stop_queue(txq);
a3138df9
DM		 6456 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6457 "queue awake!\n", dev->name);
6458 rp->tx_errors++;
6459 return NETDEV_TX_BUSY;
6460 }
6461
6462 if (skb->len < ETH_ZLEN) {
6463 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6464
6465 if (skb_pad(skb, pad_bytes))
6466 goto out;
6467 skb_put(skb, pad_bytes);
6468 }
6469
6470 len = sizeof(struct tx_pkt_hdr) + 15;
6471 if (skb_headroom(skb) < len) {
6472 struct sk_buff *skb_new;
6473
6474 skb_new = skb_realloc_headroom(skb, len);
6475 if (!skb_new) {
6476 rp->tx_errors++;
6477 goto out_drop;
6478 }
6479 kfree_skb(skb);
6480 skb = skb_new;
3ebebccf
DM		 6481 } else
6482 skb_orphan(skb);
a3138df9
DM		 6483
6484 align = ((unsigned long) skb->data & (16 - 1));
6485 headroom = align + sizeof(struct tx_pkt_hdr);
6486
6487 ehdr = (struct ethhdr *) skb->data;
6488 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6489
6490 len = skb->len - sizeof(struct tx_pkt_hdr);
6491 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6492 tp->resv = 0;
6493
6494 len = skb_headlen(skb);
6495 mapping = np->ops->map_single(np->device, skb->data,
6496 len, DMA_TO_DEVICE);
6497
6498 prod = rp->prod;
6499
6500 rp->tx_buffs[prod].skb = skb;
6501 rp->tx_buffs[prod].mapping = mapping;
6502
6503 mrk = TX_DESC_SOP;
6504 if (++rp->mark_counter == rp->mark_freq) {
6505 rp->mark_counter = 0;
6506 mrk |= TX_DESC_MARK;
6507 rp->mark_pending++;
6508 }
6509
6510 tlen = len;
6511 nfg = skb_shinfo(skb)->nr_frags;
6512 while (tlen > 0) {
6513 tlen -= MAX_TX_DESC_LEN;
6514 nfg++;
6515 }
6516
6517 while (len > 0) {
6518 unsigned int this_len = len;
6519
6520 if (this_len > MAX_TX_DESC_LEN)
6521 this_len = MAX_TX_DESC_LEN;
6522
6523 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6524 mrk = nfg = 0;
6525
6526 prod = NEXT_TX(rp, prod);
6527 mapping += this_len;
6528 len -= this_len;
6529 }
6530
6531 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6532 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6533
6534 len = frag->size;
6535 mapping = np->ops->map_page(np->device, frag->page,
6536 frag->page_offset, len,
6537 DMA_TO_DEVICE);
6538
6539 rp->tx_buffs[prod].skb = NULL;
6540 rp->tx_buffs[prod].mapping = mapping;
6541
6542 niu_set_txd(rp, prod, mapping, len, 0, 0);
6543
6544 prod = NEXT_TX(rp, prod);
6545 }
6546
6547 if (prod < rp->prod)
6548 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6549 rp->prod = prod;
6550
6551 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6552
6553 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
b4c21639 6554 netif_tx_stop_queue(txq);
a3138df9 6555 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
b4c21639 6556 netif_tx_wake_queue(txq);
a3138df9
DM		 6557 }
6558
6559 dev->trans_start = jiffies;
6560
6561out:
6562 return NETDEV_TX_OK;
6563
6564out_drop:
6565 rp->tx_errors++;
6566 kfree_skb(skb);
6567 goto out;
6568}
6569
6570static int niu_change_mtu(struct net_device *dev, int new_mtu)
6571{
6572 struct niu *np = netdev_priv(dev);
6573 int err, orig_jumbo, new_jumbo;
6574
6575 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6576 return -EINVAL;
6577
6578 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6579 new_jumbo = (new_mtu > ETH_DATA_LEN);
6580
6581 dev->mtu = new_mtu;
6582
6583 if (!netif_running(dev) ||
6584 (orig_jumbo == new_jumbo))
6585 return 0;
6586
6587 niu_full_shutdown(np, dev);
6588
6589 niu_free_channels(np);
6590
6591 niu_enable_napi(np);
6592
6593 err = niu_alloc_channels(np);
6594 if (err)
6595 return err;
6596
6597 spin_lock_irq(&np->lock);
6598
6599 err = niu_init_hw(np);
6600 if (!err) {
6601 init_timer(&np->timer);
6602 np->timer.expires = jiffies + HZ;
6603 np->timer.data = (unsigned long) np;
6604 np->timer.function = niu_timer;
6605
6606 err = niu_enable_interrupts(np, 1);
6607 if (err)
6608 niu_stop_hw(np);
6609 }
6610
6611 spin_unlock_irq(&np->lock);
6612
6613 if (!err) {
b4c21639 6614 netif_tx_start_all_queues(dev);
a3138df9
DM		 6615 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6616 netif_carrier_on(dev);
6617
6618 add_timer(&np->timer);
6619 }
6620
6621 return err;
6622}
6623
6624static void niu_get_drvinfo(struct net_device *dev,
6625 struct ethtool_drvinfo *info)
6626{
6627 struct niu *np = netdev_priv(dev);
6628 struct niu_vpd *vpd = &np->vpd;
6629
6630 strcpy(info->driver, DRV_MODULE_NAME);
6631 strcpy(info->version, DRV_MODULE_VERSION);
6632 sprintf(info->fw_version, "%d.%d",
6633 vpd->fcode_major, vpd->fcode_minor);
6634 if (np->parent->plat_type != PLAT_TYPE_NIU)
6635 strcpy(info->bus_info, pci_name(np->pdev));
6636}
6637
6638static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6639{
6640 struct niu *np = netdev_priv(dev);
6641 struct niu_link_config *lp;
6642
6643 lp = &np->link_config;
6644
6645 memset(cmd, 0, sizeof(*cmd));
6646 cmd->phy_address = np->phy_addr;
6647 cmd->supported = lp->supported;
6648 cmd->advertising = lp->advertising;
6649 cmd->autoneg = lp->autoneg;
6650 cmd->speed = lp->active_speed;
6651 cmd->duplex = lp->active_duplex;
6652
6653 return 0;
6654}
6655
6656static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6657{
6658 return -EINVAL;
6659}
6660
6661static u32 niu_get_msglevel(struct net_device *dev)
6662{
6663 struct niu *np = netdev_priv(dev);
6664 return np->msg_enable;
6665}
6666
6667static void niu_set_msglevel(struct net_device *dev, u32 value)
6668{
6669 struct niu *np = netdev_priv(dev);
6670 np->msg_enable = value;
6671}
6672
6673static int niu_get_eeprom_len(struct net_device *dev)
6674{
6675 struct niu *np = netdev_priv(dev);
6676
6677 return np->eeprom_len;
6678}
6679
6680static int niu_get_eeprom(struct net_device *dev,
6681 struct ethtool_eeprom *eeprom, u8 *data)
6682{
6683 struct niu *np = netdev_priv(dev);
6684 u32 offset, len, val;
6685
6686 offset = eeprom->offset;
6687 len = eeprom->len;
6688
6689 if (offset + len < offset)
6690 return -EINVAL;
6691 if (offset >= np->eeprom_len)
6692 return -EINVAL;
6693 if (offset + len > np->eeprom_len)
6694 len = eeprom->len = np->eeprom_len - offset;
6695
6696 if (offset & 3) {
6697 u32 b_offset, b_count;
6698
6699 b_offset = offset & 3;
6700 b_count = 4 - b_offset;
6701 if (b_count > len)
6702 b_count = len;
6703
6704 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6705 memcpy(data, ((char *)&val) + b_offset, b_count);
6706 data += b_count;
6707 len -= b_count;
6708 offset += b_count;
6709 }
6710 while (len >= 4) {
6711 val = nr64(ESPC_NCR(offset / 4));
6712 memcpy(data, &val, 4);
6713 data += 4;
6714 len -= 4;
6715 offset += 4;
6716 }
6717 if (len) {
6718 val = nr64(ESPC_NCR(offset / 4));
6719 memcpy(data, &val, len);
6720 }
6721 return 0;
6722}
6723
b4653e99
SB		 6724static int niu_ethflow_to_class(int flow_type, u64 *class)
6725{
6726 switch (flow_type) {
6727 case TCP_V4_FLOW:
6728 *class = CLASS_CODE_TCP_IPV4;
6729 break;
6730 case UDP_V4_FLOW:
6731 *class = CLASS_CODE_UDP_IPV4;
6732 break;
6733 case AH_ESP_V4_FLOW:
6734 *class = CLASS_CODE_AH_ESP_IPV4;
6735 break;
6736 case SCTP_V4_FLOW:
6737 *class = CLASS_CODE_SCTP_IPV4;
6738 break;
6739 case TCP_V6_FLOW:
6740 *class = CLASS_CODE_TCP_IPV6;
6741 break;
6742 case UDP_V6_FLOW:
6743 *class = CLASS_CODE_UDP_IPV6;
6744 break;
6745 case AH_ESP_V6_FLOW:
6746 *class = CLASS_CODE_AH_ESP_IPV6;
6747 break;
6748 case SCTP_V6_FLOW:
6749 *class = CLASS_CODE_SCTP_IPV6;
6750 break;
6751 default:
38c080ff 6752 return 0;
b4653e99
SB		 6753 }
6754
6755 return 1;
6756}
6757
6758static u64 niu_flowkey_to_ethflow(u64 flow_key)
6759{
6760 u64 ethflow = 0;
6761
6762 if (flow_key & FLOW_KEY_PORT)
6763 ethflow |= RXH_DEV_PORT;
6764 if (flow_key & FLOW_KEY_L2DA)
6765 ethflow |= RXH_L2DA;
6766 if (flow_key & FLOW_KEY_VLAN)
6767 ethflow |= RXH_VLAN;
6768 if (flow_key & FLOW_KEY_IPSA)
6769 ethflow |= RXH_IP_SRC;
6770 if (flow_key & FLOW_KEY_IPDA)
6771 ethflow |= RXH_IP_DST;
6772 if (flow_key & FLOW_KEY_PROTO)
6773 ethflow |= RXH_L3_PROTO;
6774 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
6775 ethflow |= RXH_L4_B_0_1;
6776 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
6777 ethflow |= RXH_L4_B_2_3;
6778
6779 return ethflow;
6780
6781}
6782
6783static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
6784{
6785 u64 key = 0;
6786
6787 if (ethflow & RXH_DEV_PORT)
6788 key |= FLOW_KEY_PORT;
6789 if (ethflow & RXH_L2DA)
6790 key |= FLOW_KEY_L2DA;
6791 if (ethflow & RXH_VLAN)
6792 key |= FLOW_KEY_VLAN;
6793 if (ethflow & RXH_IP_SRC)
6794 key |= FLOW_KEY_IPSA;
6795 if (ethflow & RXH_IP_DST)
6796 key |= FLOW_KEY_IPDA;
6797 if (ethflow & RXH_L3_PROTO)
6798 key |= FLOW_KEY_PROTO;
6799 if (ethflow & RXH_L4_B_0_1)
6800 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
6801 if (ethflow & RXH_L4_B_2_3)
6802 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
6803
6804 *flow_key = key;
6805
6806 return 1;
6807
6808}
6809
6810static int niu_get_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6811{
6812 struct niu *np = netdev_priv(dev);
6813 u64 class;
6814
6815 cmd->data = 0;
6816
6817 if (!niu_ethflow_to_class(cmd->flow_type, &class))
6818 return -EINVAL;
6819
6820 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6821 TCAM_KEY_DISC)
6822 cmd->data = RXH_DISCARD;
6823 else
6824
6825 cmd->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
6826 CLASS_CODE_USER_PROG1]);
6827 return 0;
6828}
6829
6830static int niu_set_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6831{
6832 struct niu *np = netdev_priv(dev);
6833 u64 class;
6834 u64 flow_key = 0;
6835 unsigned long flags;
6836
6837 if (!niu_ethflow_to_class(cmd->flow_type, &class))
6838 return -EINVAL;
6839
6840 if (class < CLASS_CODE_USER_PROG1 ||
6841 class > CLASS_CODE_SCTP_IPV6)
6842 return -EINVAL;
6843
6844 if (cmd->data & RXH_DISCARD) {
6845 niu_lock_parent(np, flags);
6846 flow_key = np->parent->tcam_key[class -
6847 CLASS_CODE_USER_PROG1];
6848 flow_key |= TCAM_KEY_DISC;
6849 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6850 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6851 niu_unlock_parent(np, flags);
6852 return 0;
6853 } else {
6854 /* Discard was set before, but is not set now */
6855 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6856 TCAM_KEY_DISC) {
6857 niu_lock_parent(np, flags);
6858 flow_key = np->parent->tcam_key[class -
6859 CLASS_CODE_USER_PROG1];
6860 flow_key &= ~TCAM_KEY_DISC;
6861 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
6862 flow_key);
6863 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
6864 flow_key;
6865 niu_unlock_parent(np, flags);
6866 }
6867 }
6868
6869 if (!niu_ethflow_to_flowkey(cmd->data, &flow_key))
6870 return -EINVAL;
6871
6872 niu_lock_parent(np, flags);
6873 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6874 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6875 niu_unlock_parent(np, flags);
6876
6877 return 0;
6878}
6879
a3138df9
DM		 6880static const struct {
6881 const char string[ETH_GSTRING_LEN];
6882} niu_xmac_stat_keys[] = {
6883 { "tx_frames" },
6884 { "tx_bytes" },
6885 { "tx_fifo_errors" },
6886 { "tx_overflow_errors" },
6887 { "tx_max_pkt_size_errors" },
6888 { "tx_underflow_errors" },
6889 { "rx_local_faults" },
6890 { "rx_remote_faults" },
6891 { "rx_link_faults" },
6892 { "rx_align_errors" },
6893 { "rx_frags" },
6894 { "rx_mcasts" },
6895 { "rx_bcasts" },
6896 { "rx_hist_cnt1" },
6897 { "rx_hist_cnt2" },
6898 { "rx_hist_cnt3" },
6899 { "rx_hist_cnt4" },
6900 { "rx_hist_cnt5" },
6901 { "rx_hist_cnt6" },
6902 { "rx_hist_cnt7" },
6903 { "rx_octets" },
6904 { "rx_code_violations" },
6905 { "rx_len_errors" },
6906 { "rx_crc_errors" },
6907 { "rx_underflows" },
6908 { "rx_overflows" },
6909 { "pause_off_state" },
6910 { "pause_on_state" },
6911 { "pause_received" },
6912};
6913
6914#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
6915
6916static const struct {
6917 const char string[ETH_GSTRING_LEN];
6918} niu_bmac_stat_keys[] = {
6919 { "tx_underflow_errors" },
6920 { "tx_max_pkt_size_errors" },
6921 { "tx_bytes" },
6922 { "tx_frames" },
6923 { "rx_overflows" },
6924 { "rx_frames" },
6925 { "rx_align_errors" },
6926 { "rx_crc_errors" },
6927 { "rx_len_errors" },
6928 { "pause_off_state" },
6929 { "pause_on_state" },
6930 { "pause_received" },
6931};
6932
6933#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
6934
6935static const struct {
6936 const char string[ETH_GSTRING_LEN];
6937} niu_rxchan_stat_keys[] = {
6938 { "rx_channel" },
6939 { "rx_packets" },
6940 { "rx_bytes" },
6941 { "rx_dropped" },
6942 { "rx_errors" },
6943};
6944
6945#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
6946
6947static const struct {
6948 const char string[ETH_GSTRING_LEN];
6949} niu_txchan_stat_keys[] = {
6950 { "tx_channel" },
6951 { "tx_packets" },
6952 { "tx_bytes" },
6953 { "tx_errors" },
6954};
6955
6956#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
6957
6958static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6959{
6960 struct niu *np = netdev_priv(dev);
6961 int i;
6962
6963 if (stringset != ETH_SS_STATS)
6964 return;
6965
6966 if (np->flags & NIU_FLAGS_XMAC) {
6967 memcpy(data, niu_xmac_stat_keys,
6968 sizeof(niu_xmac_stat_keys));
6969 data += sizeof(niu_xmac_stat_keys);
6970 } else {
6971 memcpy(data, niu_bmac_stat_keys,
6972 sizeof(niu_bmac_stat_keys));
6973 data += sizeof(niu_bmac_stat_keys);
6974 }
6975 for (i = 0; i < np->num_rx_rings; i++) {
6976 memcpy(data, niu_rxchan_stat_keys,
6977 sizeof(niu_rxchan_stat_keys));
6978 data += sizeof(niu_rxchan_stat_keys);
6979 }
6980 for (i = 0; i < np->num_tx_rings; i++) {
6981 memcpy(data, niu_txchan_stat_keys,
6982 sizeof(niu_txchan_stat_keys));
6983 data += sizeof(niu_txchan_stat_keys);
6984 }
6985}
6986
6987static int niu_get_stats_count(struct net_device *dev)
6988{
6989 struct niu *np = netdev_priv(dev);
6990
6991 return ((np->flags & NIU_FLAGS_XMAC ?
6992 NUM_XMAC_STAT_KEYS :
6993 NUM_BMAC_STAT_KEYS) +
6994 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
6995 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
6996}
6997
6998static void niu_get_ethtool_stats(struct net_device *dev,
6999 struct ethtool_stats *stats, u64 *data)
7000{
7001 struct niu *np = netdev_priv(dev);
7002 int i;
7003
7004 niu_sync_mac_stats(np);
7005 if (np->flags & NIU_FLAGS_XMAC) {
7006 memcpy(data, &np->mac_stats.xmac,
7007 sizeof(struct niu_xmac_stats));
7008 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7009 } else {
7010 memcpy(data, &np->mac_stats.bmac,
7011 sizeof(struct niu_bmac_stats));
7012 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7013 }
7014 for (i = 0; i < np->num_rx_rings; i++) {
7015 struct rx_ring_info *rp = &np->rx_rings[i];
7016
7017 data[0] = rp->rx_channel;
7018 data[1] = rp->rx_packets;
7019 data[2] = rp->rx_bytes;
7020 data[3] = rp->rx_dropped;
7021 data[4] = rp->rx_errors;
7022 data += 5;
7023 }
7024 for (i = 0; i < np->num_tx_rings; i++) {
7025 struct tx_ring_info *rp = &np->tx_rings[i];
7026
7027 data[0] = rp->tx_channel;
7028 data[1] = rp->tx_packets;
7029 data[2] = rp->tx_bytes;
7030 data[3] = rp->tx_errors;
7031 data += 4;
7032 }
7033}
7034
7035static u64 niu_led_state_save(struct niu *np)
7036{
7037 if (np->flags & NIU_FLAGS_XMAC)
7038 return nr64_mac(XMAC_CONFIG);
7039 else
7040 return nr64_mac(BMAC_XIF_CONFIG);
7041}
7042
7043static void niu_led_state_restore(struct niu *np, u64 val)
7044{
7045 if (np->flags & NIU_FLAGS_XMAC)
7046 nw64_mac(XMAC_CONFIG, val);
7047 else
7048 nw64_mac(BMAC_XIF_CONFIG, val);
7049}
7050
7051static void niu_force_led(struct niu *np, int on)
7052{
7053 u64 val, reg, bit;
7054
7055 if (np->flags & NIU_FLAGS_XMAC) {
7056 reg = XMAC_CONFIG;
7057 bit = XMAC_CONFIG_FORCE_LED_ON;
7058 } else {
7059 reg = BMAC_XIF_CONFIG;
7060 bit = BMAC_XIF_CONFIG_LINK_LED;
7061 }
7062
7063 val = nr64_mac(reg);
7064 if (on)
7065 val |= bit;
7066 else
7067 val &= ~bit;
7068 nw64_mac(reg, val);
7069}
7070
7071static int niu_phys_id(struct net_device *dev, u32 data)
7072{
7073 struct niu *np = netdev_priv(dev);
7074 u64 orig_led_state;
7075 int i;
7076
7077 if (!netif_running(dev))
7078 return -EAGAIN;
7079
7080 if (data == 0)
7081 data = 2;
7082
7083 orig_led_state = niu_led_state_save(np);
7084 for (i = 0; i < (data * 2); i++) {
7085 int on = ((i % 2) == 0);
7086
7087 niu_force_led(np, on);
7088
7089 if (msleep_interruptible(500))
7090 break;
7091 }
7092 niu_led_state_restore(np, orig_led_state);
7093
7094 return 0;
7095}
7096
7097static const struct ethtool_ops niu_ethtool_ops = {
7098 .get_drvinfo = niu_get_drvinfo,
7099 .get_link = ethtool_op_get_link,
7100 .get_msglevel = niu_get_msglevel,
7101 .set_msglevel = niu_set_msglevel,
7102 .get_eeprom_len = niu_get_eeprom_len,
7103 .get_eeprom = niu_get_eeprom,
7104 .get_settings = niu_get_settings,
7105 .set_settings = niu_set_settings,
7106 .get_strings = niu_get_strings,
7107 .get_stats_count = niu_get_stats_count,
7108 .get_ethtool_stats = niu_get_ethtool_stats,
7109 .phys_id = niu_phys_id,
b4653e99
SB		 7110 .get_rxhash = niu_get_hash_opts,
7111 .set_rxhash = niu_set_hash_opts,
a3138df9
DM		 7112};
7113
7114static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7115 int ldg, int ldn)
7116{
7117 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7118 return -EINVAL;
7119 if (ldn < 0 || ldn > LDN_MAX)
7120 return -EINVAL;
7121
7122 parent->ldg_map[ldn] = ldg;
7123
7124 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7125 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7126 * the firmware, and we're not supposed to change them.
7127 * Validate the mapping, because if it's wrong we probably
7128 * won't get any interrupts and that's painful to debug.
7129 */
7130 if (nr64(LDG_NUM(ldn)) != ldg) {
7131 dev_err(np->device, PFX "Port %u, mis-matched "
7132 "LDG assignment "
7133 "for ldn %d, should be %d is %llu\n",
7134 np->port, ldn, ldg,
7135 (unsigned long long) nr64(LDG_NUM(ldn)));
7136 return -EINVAL;
7137 }
7138 } else
7139 nw64(LDG_NUM(ldn), ldg);
7140
7141 return 0;
7142}
7143
7144static int niu_set_ldg_timer_res(struct niu *np, int res)
7145{
7146 if (res < 0 || res > LDG_TIMER_RES_VAL)
7147 return -EINVAL;
7148
7149
7150 nw64(LDG_TIMER_RES, res);
7151
7152 return 0;
7153}
7154
7155static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7156{
7157 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7158 (func < 0 || func > 3) ||
7159 (vector < 0 || vector > 0x1f))
7160 return -EINVAL;
7161
7162 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7163
7164 return 0;
7165}
7166
7167static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7168{
7169 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7170 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7171 int limit;
7172
7173 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7174 return -EINVAL;
7175
7176 frame = frame_base;
7177 nw64(ESPC_PIO_STAT, frame);
7178 limit = 64;
7179 do {
7180 udelay(5);
7181 frame = nr64(ESPC_PIO_STAT);
7182 if (frame & ESPC_PIO_STAT_READ_END)
7183 break;
7184 } while (limit--);
7185 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7186 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7187 (unsigned long long) frame);
7188 return -ENODEV;
7189 }
7190
7191 frame = frame_base;
7192 nw64(ESPC_PIO_STAT, frame);
7193 limit = 64;
7194 do {
7195 udelay(5);
7196 frame = nr64(ESPC_PIO_STAT);
7197 if (frame & ESPC_PIO_STAT_READ_END)
7198 break;
7199 } while (limit--);
7200 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7201 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7202 (unsigned long long) frame);
7203 return -ENODEV;
7204 }
7205
7206 frame = nr64(ESPC_PIO_STAT);
7207 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
7208}
7209
7210static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
7211{
7212 int err = niu_pci_eeprom_read(np, off);
7213 u16 val;
7214
7215 if (err < 0)
7216 return err;
7217 val = (err << 8);
7218 err = niu_pci_eeprom_read(np, off + 1);
7219 if (err < 0)
7220 return err;
7221 val |= (err & 0xff);
7222
7223 return val;
7224}
7225
7226static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
7227{
7228 int err = niu_pci_eeprom_read(np, off);
7229 u16 val;
7230
7231 if (err < 0)
7232 return err;
7233
7234 val = (err & 0xff);
7235 err = niu_pci_eeprom_read(np, off + 1);
7236 if (err < 0)
7237 return err;
7238
7239 val |= (err & 0xff) << 8;
7240
7241 return val;
7242}
7243
7244static int __devinit niu_pci_vpd_get_propname(struct niu *np,
7245 u32 off,
7246 char *namebuf,
7247 int namebuf_len)
7248{
7249 int i;
7250
7251 for (i = 0; i < namebuf_len; i++) {
7252 int err = niu_pci_eeprom_read(np, off + i);
7253 if (err < 0)
7254 return err;
7255 *namebuf++ = err;
7256 if (!err)
7257 break;
7258 }
7259 if (i >= namebuf_len)
7260 return -EINVAL;
7261
7262 return i + 1;
7263}
7264
7265static void __devinit niu_vpd_parse_version(struct niu *np)
7266{
7267 struct niu_vpd *vpd = &np->vpd;
7268 int len = strlen(vpd->version) + 1;
7269 const char *s = vpd->version;
7270 int i;
7271
7272 for (i = 0; i < len - 5; i++) {
7273 if (!strncmp(s + i, "FCode ", 5))
7274 break;
7275 }
7276 if (i >= len - 5)
7277 return;
7278
7279 s += i + 5;
7280 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
7281
7282 niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
7283 vpd->fcode_major, vpd->fcode_minor);
7284 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
7285 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
7286 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
7287 np->flags |= NIU_FLAGS_VPD_VALID;
7288}
7289
7290/* ESPC_PIO_EN_ENABLE must be set */
7291static int __devinit niu_pci_vpd_scan_props(struct niu *np,
7292 u32 start, u32 end)
7293{
7294 unsigned int found_mask = 0;
7295#define FOUND_MASK_MODEL 0x00000001
7296#define FOUND_MASK_BMODEL 0x00000002
7297#define FOUND_MASK_VERS 0x00000004
7298#define FOUND_MASK_MAC 0x00000008
7299#define FOUND_MASK_NMAC 0x00000010
7300#define FOUND_MASK_PHY 0x00000020
7301#define FOUND_MASK_ALL 0x0000003f
7302
7303 niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
7304 start, end);
7305 while (start < end) {
7306 int len, err, instance, type, prop_len;
7307 char namebuf[64];
7308 u8 *prop_buf;
7309 int max_len;
7310
7311 if (found_mask == FOUND_MASK_ALL) {
7312 niu_vpd_parse_version(np);
7313 return 1;
7314 }
7315
7316 err = niu_pci_eeprom_read(np, start + 2);
7317 if (err < 0)
7318 return err;
7319 len = err;
7320 start += 3;
7321
7322 instance = niu_pci_eeprom_read(np, start);
7323 type = niu_pci_eeprom_read(np, start + 3);
7324 prop_len = niu_pci_eeprom_read(np, start + 4);
7325 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
7326 if (err < 0)
7327 return err;
7328
7329 prop_buf = NULL;
7330 max_len = 0;
7331 if (!strcmp(namebuf, "model")) {
7332 prop_buf = np->vpd.model;
7333 max_len = NIU_VPD_MODEL_MAX;
7334 found_mask |= FOUND_MASK_MODEL;
7335 } else if (!strcmp(namebuf, "board-model")) {
7336 prop_buf = np->vpd.board_model;
7337 max_len = NIU_VPD_BD_MODEL_MAX;
7338 found_mask |= FOUND_MASK_BMODEL;
7339 } else if (!strcmp(namebuf, "version")) {
7340 prop_buf = np->vpd.version;
7341 max_len = NIU_VPD_VERSION_MAX;
7342 found_mask |= FOUND_MASK_VERS;
7343 } else if (!strcmp(namebuf, "local-mac-address")) {
7344 prop_buf = np->vpd.local_mac;
7345 max_len = ETH_ALEN;
7346 found_mask |= FOUND_MASK_MAC;
7347 } else if (!strcmp(namebuf, "num-mac-addresses")) {
7348 prop_buf = &np->vpd.mac_num;
7349 max_len = 1;
7350 found_mask |= FOUND_MASK_NMAC;
7351 } else if (!strcmp(namebuf, "phy-type")) {
7352 prop_buf = np->vpd.phy_type;
7353 max_len = NIU_VPD_PHY_TYPE_MAX;
7354 found_mask |= FOUND_MASK_PHY;
7355 }
7356
7357 if (max_len && prop_len > max_len) {
7358 dev_err(np->device, PFX "Property '%s' length (%d) is "
7359 "too long.\n", namebuf, prop_len);
7360 return -EINVAL;
7361 }
7362
7363 if (prop_buf) {
7364 u32 off = start + 5 + err;
7365 int i;
7366
7367 niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
7368 "len[%d]\n", namebuf, prop_len);
7369 for (i = 0; i < prop_len; i++)
7370 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
7371 }
7372
7373 start += len;
7374 }
7375
7376 return 0;
7377}
7378
7379/* ESPC_PIO_EN_ENABLE must be set */
7380static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
7381{
7382 u32 offset;
7383 int err;
7384
7385 err = niu_pci_eeprom_read16_swp(np, start + 1);
7386 if (err < 0)
7387 return;
7388
7389 offset = err + 3;
7390
7391 while (start + offset < ESPC_EEPROM_SIZE) {
7392 u32 here = start + offset;
7393 u32 end;
7394
7395 err = niu_pci_eeprom_read(np, here);
7396 if (err != 0x90)
7397 return;
7398
7399 err = niu_pci_eeprom_read16_swp(np, here + 1);
7400 if (err < 0)
7401 return;
7402
7403 here = start + offset + 3;
7404 end = start + offset + err;
7405
7406 offset += err;
7407
7408 err = niu_pci_vpd_scan_props(np, here, end);
7409 if (err < 0 || err == 1)
7410 return;
7411 }
7412}
7413
7414/* ESPC_PIO_EN_ENABLE must be set */
7415static u32 __devinit niu_pci_vpd_offset(struct niu *np)
7416{
7417 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
7418 int err;
7419
7420 while (start < end) {
7421 ret = start;
7422
7423 /* ROM header signature? */
7424 err = niu_pci_eeprom_read16(np, start + 0);
7425 if (err != 0x55aa)
7426 return 0;
7427
7428 /* Apply offset to PCI data structure. */
7429 err = niu_pci_eeprom_read16(np, start + 23);
7430 if (err < 0)
7431 return 0;
7432 start += err;
7433
7434 /* Check for "PCIR" signature. */
7435 err = niu_pci_eeprom_read16(np, start + 0);
7436 if (err != 0x5043)
7437 return 0;
7438 err = niu_pci_eeprom_read16(np, start + 2);
7439 if (err != 0x4952)
7440 return 0;
7441
7442 /* Check for OBP image type. */
7443 err = niu_pci_eeprom_read(np, start + 20);
7444 if (err < 0)
7445 return 0;
7446 if (err != 0x01) {
7447 err = niu_pci_eeprom_read(np, ret + 2);
7448 if (err < 0)
7449 return 0;
7450
7451 start = ret + (err * 512);
7452 continue;
7453 }
7454
7455 err = niu_pci_eeprom_read16_swp(np, start + 8);
7456 if (err < 0)
7457 return err;
7458 ret += err;
7459
7460 err = niu_pci_eeprom_read(np, ret + 0);
7461 if (err != 0x82)
7462 return 0;
7463
7464 return ret;
7465 }
7466
7467 return 0;
7468}
7469
7470static int __devinit niu_phy_type_prop_decode(struct niu *np,
7471 const char *phy_prop)
7472{
7473 if (!strcmp(phy_prop, "mif")) {
7474 /* 1G copper, MII */
7475 np->flags &= ~(NIU_FLAGS_FIBER |
7476 NIU_FLAGS_10G);
7477 np->mac_xcvr = MAC_XCVR_MII;
7478 } else if (!strcmp(phy_prop, "xgf")) {
7479 /* 10G fiber, XPCS */
7480 np->flags |= (NIU_FLAGS_10G |
7481 NIU_FLAGS_FIBER);
7482 np->mac_xcvr = MAC_XCVR_XPCS;
7483 } else if (!strcmp(phy_prop, "pcs")) {
7484 /* 1G fiber, PCS */
7485 np->flags &= ~NIU_FLAGS_10G;
7486 np->flags |= NIU_FLAGS_FIBER;
7487 np->mac_xcvr = MAC_XCVR_PCS;
7488 } else if (!strcmp(phy_prop, "xgc")) {
7489 /* 10G copper, XPCS */
7490 np->flags |= NIU_FLAGS_10G;
7491 np->flags &= ~NIU_FLAGS_FIBER;
7492 np->mac_xcvr = MAC_XCVR_XPCS;
e3e081e1
SB		 7493 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
7494 /* 10G Serdes or 1G Serdes, default to 10G */
7495 np->flags |= NIU_FLAGS_10G;
7496 np->flags &= ~NIU_FLAGS_FIBER;
7497 np->flags |= NIU_FLAGS_XCVR_SERDES;
7498 np->mac_xcvr = MAC_XCVR_XPCS;
a3138df9
DM		 7499 } else {
7500 return -EINVAL;
7501 }
7502 return 0;
7503}
7504
7f7c4072
MW		 7505static int niu_pci_vpd_get_nports(struct niu *np)
7506{
7507 int ports = 0;
7508
f9af8574
MW		 7509 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
7510 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
7511 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
7512 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
7513 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7f7c4072 7514 ports = 4;
f9af8574
MW		 7515 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
7516 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
7517 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
7518 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7f7c4072
MW		 7519 ports = 2;
7520 }
7521
7522 return ports;
7523}
7524
a3138df9
DM		 7525static void __devinit niu_pci_vpd_validate(struct niu *np)
7526{
7527 struct net_device *dev = np->dev;
7528 struct niu_vpd *vpd = &np->vpd;
7529 u8 val8;
7530
7531 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
7532 dev_err(np->device, PFX "VPD MAC invalid, "
7533 "falling back to SPROM.\n");
7534
7535 np->flags &= ~NIU_FLAGS_VPD_VALID;
7536 return;
7537 }
7538
f9af8574
MW		 7539 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
7540 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 7541 np->flags |= NIU_FLAGS_10G;
7542 np->flags &= ~NIU_FLAGS_FIBER;
7543 np->flags |= NIU_FLAGS_XCVR_SERDES;
7544 np->mac_xcvr = MAC_XCVR_PCS;
7545 if (np->port > 1) {
7546 np->flags |= NIU_FLAGS_FIBER;
7547 np->flags &= ~NIU_FLAGS_10G;
7548 }
7549 if (np->flags & NIU_FLAGS_10G)
7550 np->mac_xcvr = MAC_XCVR_XPCS;
f9af8574 7551 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 7552 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
7553 NIU_FLAGS_HOTPLUG_PHY);
5fbd7e24 7554 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
a3138df9
DM		 7555 dev_err(np->device, PFX "Illegal phy string [%s].\n",
7556 np->vpd.phy_type);
7557 dev_err(np->device, PFX "Falling back to SPROM.\n");
7558 np->flags &= ~NIU_FLAGS_VPD_VALID;
7559 return;
7560 }
7561
7562 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
7563
7564 val8 = dev->perm_addr[5];
7565 dev->perm_addr[5] += np->port;
7566 if (dev->perm_addr[5] < val8)
7567 dev->perm_addr[4]++;
7568
7569 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7570}
7571
7572static int __devinit niu_pci_probe_sprom(struct niu *np)
7573{
7574 struct net_device *dev = np->dev;
7575 int len, i;
7576 u64 val, sum;
7577 u8 val8;
7578
7579 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
7580 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
7581 len = val / 4;
7582
7583 np->eeprom_len = len;
7584
7585 niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
7586
7587 sum = 0;
7588 for (i = 0; i < len; i++) {
7589 val = nr64(ESPC_NCR(i));
7590 sum += (val >> 0) & 0xff;
7591 sum += (val >> 8) & 0xff;
7592 sum += (val >> 16) & 0xff;
7593 sum += (val >> 24) & 0xff;
7594 }
7595 niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
7596 if ((sum & 0xff) != 0xab) {
7597 dev_err(np->device, PFX "Bad SPROM checksum "
7598 "(%x, should be 0xab)\n", (int) (sum & 0xff));
7599 return -EINVAL;
7600 }
7601
7602 val = nr64(ESPC_PHY_TYPE);
7603 switch (np->port) {
7604 case 0:
a9d41192 7605 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
a3138df9
DM		 7606 ESPC_PHY_TYPE_PORT0_SHIFT;
7607 break;
7608 case 1:
a9d41192 7609 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
a3138df9
DM		 7610 ESPC_PHY_TYPE_PORT1_SHIFT;
7611 break;
7612 case 2:
a9d41192 7613 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
a3138df9
DM		 7614 ESPC_PHY_TYPE_PORT2_SHIFT;
7615 break;
7616 case 3:
a9d41192 7617 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
a3138df9
DM		 7618 ESPC_PHY_TYPE_PORT3_SHIFT;
7619 break;
7620 default:
7621 dev_err(np->device, PFX "Bogus port number %u\n",
7622 np->port);
7623 return -EINVAL;
7624 }
a9d41192 7625 niudbg(PROBE, "SPROM: PHY type %x\n", val8);
a3138df9 7626
a9d41192 7627 switch (val8) {
a3138df9
DM		 7628 case ESPC_PHY_TYPE_1G_COPPER:
7629 /* 1G copper, MII */
7630 np->flags &= ~(NIU_FLAGS_FIBER |
7631 NIU_FLAGS_10G);
7632 np->mac_xcvr = MAC_XCVR_MII;
7633 break;
7634
7635 case ESPC_PHY_TYPE_1G_FIBER:
7636 /* 1G fiber, PCS */
7637 np->flags &= ~NIU_FLAGS_10G;
7638 np->flags |= NIU_FLAGS_FIBER;
7639 np->mac_xcvr = MAC_XCVR_PCS;
7640 break;
7641
7642 case ESPC_PHY_TYPE_10G_COPPER:
7643 /* 10G copper, XPCS */
7644 np->flags |= NIU_FLAGS_10G;
7645 np->flags &= ~NIU_FLAGS_FIBER;
7646 np->mac_xcvr = MAC_XCVR_XPCS;
7647 break;
7648
7649 case ESPC_PHY_TYPE_10G_FIBER:
7650 /* 10G fiber, XPCS */
7651 np->flags |= (NIU_FLAGS_10G |
7652 NIU_FLAGS_FIBER);
7653 np->mac_xcvr = MAC_XCVR_XPCS;
7654 break;
7655
7656 default:
a9d41192 7657 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
a3138df9
DM		 7658 return -EINVAL;
7659 }
7660
7661 val = nr64(ESPC_MAC_ADDR0);
7662 niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
7663 (unsigned long long) val);
7664 dev->perm_addr[0] = (val >> 0) & 0xff;
7665 dev->perm_addr[1] = (val >> 8) & 0xff;
7666 dev->perm_addr[2] = (val >> 16) & 0xff;
7667 dev->perm_addr[3] = (val >> 24) & 0xff;
7668
7669 val = nr64(ESPC_MAC_ADDR1);
7670 niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
7671 (unsigned long long) val);
7672 dev->perm_addr[4] = (val >> 0) & 0xff;
7673 dev->perm_addr[5] = (val >> 8) & 0xff;
7674
7675 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7676 dev_err(np->device, PFX "SPROM MAC address invalid\n");
7677 dev_err(np->device, PFX "[ \n");
7678 for (i = 0; i < 6; i++)
7679 printk("%02x ", dev->perm_addr[i]);
7680 printk("]\n");
7681 return -EINVAL;
7682 }
7683
7684 val8 = dev->perm_addr[5];
7685 dev->perm_addr[5] += np->port;
7686 if (dev->perm_addr[5] < val8)
7687 dev->perm_addr[4]++;
7688
7689 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7690
7691 val = nr64(ESPC_MOD_STR_LEN);
7692 niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
7693 (unsigned long long) val);
e6a5fdf5 7694 if (val >= 8 * 4)
a3138df9
DM		 7695 return -EINVAL;
7696
7697 for (i = 0; i < val; i += 4) {
7698 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
7699
7700 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
7701 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
7702 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
7703 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
7704 }
7705 np->vpd.model[val] = '\0';
7706
7707 val = nr64(ESPC_BD_MOD_STR_LEN);
7708 niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
7709 (unsigned long long) val);
e6a5fdf5 7710 if (val >= 4 * 4)
a3138df9
DM		 7711 return -EINVAL;
7712
7713 for (i = 0; i < val; i += 4) {
7714 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
7715
7716 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
7717 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
7718 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
7719 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
7720 }
7721 np->vpd.board_model[val] = '\0';
7722
7723 np->vpd.mac_num =
7724 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
7725 niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
7726 np->vpd.mac_num);
7727
7728 return 0;
7729}
7730
7731static int __devinit niu_get_and_validate_port(struct niu *np)
7732{
7733 struct niu_parent *parent = np->parent;
7734
7735 if (np->port <= 1)
7736 np->flags |= NIU_FLAGS_XMAC;
7737
7738 if (!parent->num_ports) {
7739 if (parent->plat_type == PLAT_TYPE_NIU) {
7740 parent->num_ports = 2;
7741 } else {
7f7c4072
MW		 7742 parent->num_ports = niu_pci_vpd_get_nports(np);
7743 if (!parent->num_ports) {
7744 /* Fall back to SPROM as last resort.
7745 * This will fail on most cards.
7746 */
7747 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
7748 ESPC_NUM_PORTS_MACS_VAL;
7749
be0c007a
DM		 7750 /* All of the current probing methods fail on
7751 * Maramba on-board parts.
7752 */
7f7c4072 7753 if (!parent->num_ports)
be0c007a 7754 parent->num_ports = 4;
7f7c4072 7755 }
a3138df9
DM		 7756 }
7757 }
7758
7759 niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
7760 np->port, parent->num_ports);
7761 if (np->port >= parent->num_ports)
7762 return -ENODEV;
7763
7764 return 0;
7765}
7766
7767static int __devinit phy_record(struct niu_parent *parent,
7768 struct phy_probe_info *p,
7769 int dev_id_1, int dev_id_2, u8 phy_port,
7770 int type)
7771{
7772 u32 id = (dev_id_1 << 16) | dev_id_2;
7773 u8 idx;
7774
7775 if (dev_id_1 < 0 || dev_id_2 < 0)
7776 return 0;
7777 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
b0de8e40 7778 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
a5d6ab56
MW		 7779 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
7780 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
a3138df9
DM		 7781 return 0;
7782 } else {
7783 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
7784 return 0;
7785 }
7786
7787 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7788 parent->index, id,
7789 (type == PHY_TYPE_PMA_PMD ?
7790 "PMA/PMD" :
7791 (type == PHY_TYPE_PCS ?
7792 "PCS" : "MII")),
7793 phy_port);
7794
7795 if (p->cur[type] >= NIU_MAX_PORTS) {
7796 printk(KERN_ERR PFX "Too many PHY ports.\n");
7797 return -EINVAL;
7798 }
7799 idx = p->cur[type];
7800 p->phy_id[type][idx] = id;
7801 p->phy_port[type][idx] = phy_port;
7802 p->cur[type] = idx + 1;
7803 return 0;
7804}
7805
7806static int __devinit port_has_10g(struct phy_probe_info *p, int port)
7807{
7808 int i;
7809
7810 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
7811 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
7812 return 1;
7813 }
7814 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
7815 if (p->phy_port[PHY_TYPE_PCS][i] == port)
7816 return 1;
7817 }
7818
7819 return 0;
7820}
7821
7822static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
7823{
7824 int port, cnt;
7825
7826 cnt = 0;
7827 *lowest = 32;
7828 for (port = 8; port < 32; port++) {
7829 if (port_has_10g(p, port)) {
7830 if (!cnt)
7831 *lowest = port;
7832 cnt++;
7833 }
7834 }
7835
7836 return cnt;
7837}
7838
7839static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
7840{
7841 *lowest = 32;
7842 if (p->cur[PHY_TYPE_MII])
7843 *lowest = p->phy_port[PHY_TYPE_MII][0];
7844
7845 return p->cur[PHY_TYPE_MII];
7846}
7847
7848static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
7849{
7850 int num_ports = parent->num_ports;
7851 int i;
7852
7853 for (i = 0; i < num_ports; i++) {
7854 parent->rxchan_per_port[i] = (16 / num_ports);
7855 parent->txchan_per_port[i] = (16 / num_ports);
7856
7857 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7858 "[%u TX chans]\n",
7859 parent->index, i,
7860 parent->rxchan_per_port[i],
7861 parent->txchan_per_port[i]);
7862 }
7863}
7864
7865static void __devinit niu_divide_channels(struct niu_parent *parent,
7866 int num_10g, int num_1g)
7867{
7868 int num_ports = parent->num_ports;
7869 int rx_chans_per_10g, rx_chans_per_1g;
7870 int tx_chans_per_10g, tx_chans_per_1g;
7871 int i, tot_rx, tot_tx;
7872
7873 if (!num_10g || !num_1g) {
7874 rx_chans_per_10g = rx_chans_per_1g =
7875 (NIU_NUM_RXCHAN / num_ports);
7876 tx_chans_per_10g = tx_chans_per_1g =
7877 (NIU_NUM_TXCHAN / num_ports);
7878 } else {
7879 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
7880 rx_chans_per_10g = (NIU_NUM_RXCHAN -
7881 (rx_chans_per_1g * num_1g)) /
7882 num_10g;
7883
7884 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
7885 tx_chans_per_10g = (NIU_NUM_TXCHAN -
7886 (tx_chans_per_1g * num_1g)) /
7887 num_10g;
7888 }
7889
7890 tot_rx = tot_tx = 0;
7891 for (i = 0; i < num_ports; i++) {
7892 int type = phy_decode(parent->port_phy, i);
7893
7894 if (type == PORT_TYPE_10G) {
7895 parent->rxchan_per_port[i] = rx_chans_per_10g;
7896 parent->txchan_per_port[i] = tx_chans_per_10g;
7897 } else {
7898 parent->rxchan_per_port[i] = rx_chans_per_1g;
7899 parent->txchan_per_port[i] = tx_chans_per_1g;
7900 }
7901 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7902 "[%u TX chans]\n",
7903 parent->index, i,
7904 parent->rxchan_per_port[i],
7905 parent->txchan_per_port[i]);
7906 tot_rx += parent->rxchan_per_port[i];
7907 tot_tx += parent->txchan_per_port[i];
7908 }
7909
7910 if (tot_rx > NIU_NUM_RXCHAN) {
7911 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
7912 "resetting to one per port.\n",
7913 parent->index, tot_rx);
7914 for (i = 0; i < num_ports; i++)
7915 parent->rxchan_per_port[i] = 1;
7916 }
7917 if (tot_tx > NIU_NUM_TXCHAN) {
7918 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
7919 "resetting to one per port.\n",
7920 parent->index, tot_tx);
7921 for (i = 0; i < num_ports; i++)
7922 parent->txchan_per_port[i] = 1;
7923 }
7924 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
7925 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
7926 "RX[%d] TX[%d]\n",
7927 parent->index, tot_rx, tot_tx);
7928 }
7929}
7930
7931static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
7932 int num_10g, int num_1g)
7933{
7934 int i, num_ports = parent->num_ports;
7935 int rdc_group, rdc_groups_per_port;
7936 int rdc_channel_base;
7937
7938 rdc_group = 0;
7939 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
7940
7941 rdc_channel_base = 0;
7942
7943 for (i = 0; i < num_ports; i++) {
7944 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
7945 int grp, num_channels = parent->rxchan_per_port[i];
7946 int this_channel_offset;
7947
7948 tp->first_table_num = rdc_group;
7949 tp->num_tables = rdc_groups_per_port;
7950 this_channel_offset = 0;
7951 for (grp = 0; grp < tp->num_tables; grp++) {
7952 struct rdc_table *rt = &tp->tables[grp];
7953 int slot;
7954
7955 pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
7956 parent->index, i, tp->first_table_num + grp);
7957 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
7958 rt->rxdma_channel[slot] =
7959 rdc_channel_base + this_channel_offset;
7960
7961 printk("%d ", rt->rxdma_channel[slot]);
7962
7963 if (++this_channel_offset == num_channels)
7964 this_channel_offset = 0;
7965 }
7966 printk("]\n");
7967 }
7968
7969 parent->rdc_default[i] = rdc_channel_base;
7970
7971 rdc_channel_base += num_channels;
7972 rdc_group += rdc_groups_per_port;
7973 }
7974}
7975
7976static int __devinit fill_phy_probe_info(struct niu *np,
7977 struct niu_parent *parent,
7978 struct phy_probe_info *info)
7979{
7980 unsigned long flags;
7981 int port, err;
7982
7983 memset(info, 0, sizeof(*info));
7984
7985 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
7986 niu_lock_parent(np, flags);
7987 err = 0;
7988 for (port = 8; port < 32; port++) {
7989 int dev_id_1, dev_id_2;
7990
7991 dev_id_1 = mdio_read(np, port,
7992 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
7993 dev_id_2 = mdio_read(np, port,
7994 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
7995 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7996 PHY_TYPE_PMA_PMD);
7997 if (err)
7998 break;
7999 dev_id_1 = mdio_read(np, port,
8000 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8001 dev_id_2 = mdio_read(np, port,
8002 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8003 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8004 PHY_TYPE_PCS);
8005 if (err)
8006 break;
8007 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8008 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8009 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8010 PHY_TYPE_MII);
8011 if (err)
8012 break;
8013 }
8014 niu_unlock_parent(np, flags);
8015
8016 return err;
8017}
8018
8019static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8020{
8021 struct phy_probe_info *info = &parent->phy_probe_info;
8022 int lowest_10g, lowest_1g;
8023 int num_10g, num_1g;
8024 u32 val;
8025 int err;
8026
e3e081e1
SB		 8027 num_10g = num_1g = 0;
8028
f9af8574
MW		 8029 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8030 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8031 num_10g = 0;
8032 num_1g = 2;
8033 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8034 parent->num_ports = 4;
8035 val = (phy_encode(PORT_TYPE_1G, 0) |
8036 phy_encode(PORT_TYPE_1G, 1) |
a3138df9
DM		 8037 phy_encode(PORT_TYPE_1G, 2) |
8038 phy_encode(PORT_TYPE_1G, 3));
f9af8574 8039 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8040 num_10g = 2;
8041 num_1g = 0;
8042 parent->num_ports = 2;
8043 val = (phy_encode(PORT_TYPE_10G, 0) |
8044 phy_encode(PORT_TYPE_10G, 1));
e3e081e1
SB		 8045 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8046 (parent->plat_type == PLAT_TYPE_NIU)) {
8047 /* this is the Monza case */
8048 if (np->flags & NIU_FLAGS_10G) {
8049 val = (phy_encode(PORT_TYPE_10G, 0) |
8050 phy_encode(PORT_TYPE_10G, 1));
8051 } else {
8052 val = (phy_encode(PORT_TYPE_1G, 0) |
8053 phy_encode(PORT_TYPE_1G, 1));
8054 }
5fbd7e24
MW		 8055 } else {
8056 err = fill_phy_probe_info(np, parent, info);
8057 if (err)
8058 return err;
a3138df9 8059
5fbd7e24
MW		 8060 num_10g = count_10g_ports(info, &lowest_10g);
8061 num_1g = count_1g_ports(info, &lowest_1g);
a3138df9 8062
5fbd7e24
MW		 8063 switch ((num_10g << 4) | num_1g) {
8064 case 0x24:
8065 if (lowest_1g == 10)
8066 parent->plat_type = PLAT_TYPE_VF_P0;
8067 else if (lowest_1g == 26)
8068 parent->plat_type = PLAT_TYPE_VF_P1;
8069 else
8070 goto unknown_vg_1g_port;
a3138df9 8071
5fbd7e24
MW		 8072 /* fallthru */
8073 case 0x22:
a3138df9 8074 val = (phy_encode(PORT_TYPE_10G, 0) |
a3138df9
DM		 8075 phy_encode(PORT_TYPE_10G, 1) |
8076 phy_encode(PORT_TYPE_1G, 2) |
8077 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24 8078 break;
a3138df9 8079
5fbd7e24
MW		 8080 case 0x20:
8081 val = (phy_encode(PORT_TYPE_10G, 0) |
8082 phy_encode(PORT_TYPE_10G, 1));
8083 break;
a3138df9 8084
5fbd7e24
MW		 8085 case 0x10:
8086 val = phy_encode(PORT_TYPE_10G, np->port);
8087 break;
a3138df9 8088
5fbd7e24
MW		 8089 case 0x14:
8090 if (lowest_1g == 10)
8091 parent->plat_type = PLAT_TYPE_VF_P0;
8092 else if (lowest_1g == 26)
8093 parent->plat_type = PLAT_TYPE_VF_P1;
8094 else
8095 goto unknown_vg_1g_port;
8096
8097 /* fallthru */
8098 case 0x13:
8099 if ((lowest_10g & 0x7) == 0)
8100 val = (phy_encode(PORT_TYPE_10G, 0) |
8101 phy_encode(PORT_TYPE_1G, 1) |
8102 phy_encode(PORT_TYPE_1G, 2) |
8103 phy_encode(PORT_TYPE_1G, 3));
8104 else
8105 val = (phy_encode(PORT_TYPE_1G, 0) |
8106 phy_encode(PORT_TYPE_10G, 1) |
8107 phy_encode(PORT_TYPE_1G, 2) |
8108 phy_encode(PORT_TYPE_1G, 3));
8109 break;
8110
8111 case 0x04:
8112 if (lowest_1g == 10)
8113 parent->plat_type = PLAT_TYPE_VF_P0;
8114 else if (lowest_1g == 26)
8115 parent->plat_type = PLAT_TYPE_VF_P1;
8116 else
8117 goto unknown_vg_1g_port;
8118
8119 val = (phy_encode(PORT_TYPE_1G, 0) |
8120 phy_encode(PORT_TYPE_1G, 1) |
8121 phy_encode(PORT_TYPE_1G, 2) |
8122 phy_encode(PORT_TYPE_1G, 3));
8123 break;
8124
8125 default:
8126 printk(KERN_ERR PFX "Unsupported port config "
8127 "10G[%d] 1G[%d]\n",
8128 num_10g, num_1g);
8129 return -EINVAL;
8130 }
a3138df9
DM		 8131 }
8132
8133 parent->port_phy = val;
8134
8135 if (parent->plat_type == PLAT_TYPE_NIU)
8136 niu_n2_divide_channels(parent);
8137 else
8138 niu_divide_channels(parent, num_10g, num_1g);
8139
8140 niu_divide_rdc_groups(parent, num_10g, num_1g);
8141
8142 return 0;
8143
8144unknown_vg_1g_port:
8145 printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
8146 lowest_1g);
8147 return -EINVAL;
8148}
8149
8150static int __devinit niu_probe_ports(struct niu *np)
8151{
8152 struct niu_parent *parent = np->parent;
8153 int err, i;
8154
8155 niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
8156 parent->port_phy);
8157
8158 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8159 err = walk_phys(np, parent);
8160 if (err)
8161 return err;
8162
8163 niu_set_ldg_timer_res(np, 2);
8164 for (i = 0; i <= LDN_MAX; i++)
8165 niu_ldn_irq_enable(np, i, 0);
8166 }
8167
8168 if (parent->port_phy == PORT_PHY_INVALID)
8169 return -EINVAL;
8170
8171 return 0;
8172}
8173
8174static int __devinit niu_classifier_swstate_init(struct niu *np)
8175{
8176 struct niu_classifier *cp = &np->clas;
8177
8178 niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
8179 np->parent->tcam_num_entries);
8180
8181 cp->tcam_index = (u16) np->port;
8182 cp->h1_init = 0xffffffff;
8183 cp->h2_init = 0xffff;
8184
8185 return fflp_early_init(np);
8186}
8187
8188static void __devinit niu_link_config_init(struct niu *np)
8189{
8190 struct niu_link_config *lp = &np->link_config;
8191
8192 lp->advertising = (ADVERTISED_10baseT_Half |
8193 ADVERTISED_10baseT_Full |
8194 ADVERTISED_100baseT_Half |
8195 ADVERTISED_100baseT_Full |
8196 ADVERTISED_1000baseT_Half |
8197 ADVERTISED_1000baseT_Full |
8198 ADVERTISED_10000baseT_Full |
8199 ADVERTISED_Autoneg);
8200 lp->speed = lp->active_speed = SPEED_INVALID;
8201 lp->duplex = lp->active_duplex = DUPLEX_INVALID;
8202#if 0
8203 lp->loopback_mode = LOOPBACK_MAC;
8204 lp->active_speed = SPEED_10000;
8205 lp->active_duplex = DUPLEX_FULL;
8206#else
8207 lp->loopback_mode = LOOPBACK_DISABLED;
8208#endif
8209}
8210
8211static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
8212{
8213 switch (np->port) {
8214 case 0:
8215 np->mac_regs = np->regs + XMAC_PORT0_OFF;
8216 np->ipp_off = 0x00000;
8217 np->pcs_off = 0x04000;
8218 np->xpcs_off = 0x02000;
8219 break;
8220
8221 case 1:
8222 np->mac_regs = np->regs + XMAC_PORT1_OFF;
8223 np->ipp_off = 0x08000;
8224 np->pcs_off = 0x0a000;
8225 np->xpcs_off = 0x08000;
8226 break;
8227
8228 case 2:
8229 np->mac_regs = np->regs + BMAC_PORT2_OFF;
8230 np->ipp_off = 0x04000;
8231 np->pcs_off = 0x0e000;
8232 np->xpcs_off = ~0UL;
8233 break;
8234
8235 case 3:
8236 np->mac_regs = np->regs + BMAC_PORT3_OFF;
8237 np->ipp_off = 0x0c000;
8238 np->pcs_off = 0x12000;
8239 np->xpcs_off = ~0UL;
8240 break;
8241
8242 default:
8243 dev_err(np->device, PFX "Port %u is invalid, cannot "
8244 "compute MAC block offset.\n", np->port);
8245 return -EINVAL;
8246 }
8247
8248 return 0;
8249}
8250
8251static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
8252{
8253 struct msix_entry msi_vec[NIU_NUM_LDG];
8254 struct niu_parent *parent = np->parent;
8255 struct pci_dev *pdev = np->pdev;
8256 int i, num_irqs, err;
8257 u8 first_ldg;
8258
8259 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
8260 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
8261 ldg_num_map[i] = first_ldg + i;
8262
8263 num_irqs = (parent->rxchan_per_port[np->port] +
8264 parent->txchan_per_port[np->port] +
8265 (np->port == 0 ? 3 : 1));
8266 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
8267
8268retry:
8269 for (i = 0; i < num_irqs; i++) {
8270 msi_vec[i].vector = 0;
8271 msi_vec[i].entry = i;
8272 }
8273
8274 err = pci_enable_msix(pdev, msi_vec, num_irqs);
8275 if (err < 0) {
8276 np->flags &= ~NIU_FLAGS_MSIX;
8277 return;
8278 }
8279 if (err > 0) {
8280 num_irqs = err;
8281 goto retry;
8282 }
8283
8284 np->flags |= NIU_FLAGS_MSIX;
8285 for (i = 0; i < num_irqs; i++)
8286 np->ldg[i].irq = msi_vec[i].vector;
8287 np->num_ldg = num_irqs;
8288}
8289
8290static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
8291{
8292#ifdef CONFIG_SPARC64
8293 struct of_device *op = np->op;
8294 const u32 *int_prop;
8295 int i;
8296
8297 int_prop = of_get_property(op->node, "interrupts", NULL);
8298 if (!int_prop)
8299 return -ENODEV;
8300
8301 for (i = 0; i < op->num_irqs; i++) {
8302 ldg_num_map[i] = int_prop[i];
8303 np->ldg[i].irq = op->irqs[i];
8304 }
8305
8306 np->num_ldg = op->num_irqs;
8307
8308 return 0;
8309#else
8310 return -EINVAL;
8311#endif
8312}
8313
8314static int __devinit niu_ldg_init(struct niu *np)
8315{
8316 struct niu_parent *parent = np->parent;
8317 u8 ldg_num_map[NIU_NUM_LDG];
8318 int first_chan, num_chan;
8319 int i, err, ldg_rotor;
8320 u8 port;
8321
8322 np->num_ldg = 1;
8323 np->ldg[0].irq = np->dev->irq;
8324 if (parent->plat_type == PLAT_TYPE_NIU) {
8325 err = niu_n2_irq_init(np, ldg_num_map);
8326 if (err)
8327 return err;
8328 } else
8329 niu_try_msix(np, ldg_num_map);
8330
8331 port = np->port;
8332 for (i = 0; i < np->num_ldg; i++) {
8333 struct niu_ldg *lp = &np->ldg[i];
8334
8335 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
8336
8337 lp->np = np;
8338 lp->ldg_num = ldg_num_map[i];
8339 lp->timer = 2; /* XXX */
8340
8341 /* On N2 NIU the firmware has setup the SID mappings so they go
8342 * to the correct values that will route the LDG to the proper
8343 * interrupt in the NCU interrupt table.
8344 */
8345 if (np->parent->plat_type != PLAT_TYPE_NIU) {
8346 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
8347 if (err)
8348 return err;
8349 }
8350 }
8351
8352 /* We adopt the LDG assignment ordering used by the N2 NIU
8353 * 'interrupt' properties because that simplifies a lot of
8354 * things. This ordering is:
8355 *
8356 * MAC
8357 * MIF (if port zero)
8358 * SYSERR (if port zero)
8359 * RX channels
8360 * TX channels
8361 */
8362
8363 ldg_rotor = 0;
8364
8365 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
8366 LDN_MAC(port));
8367 if (err)
8368 return err;
8369
8370 ldg_rotor++;
8371 if (ldg_rotor == np->num_ldg)
8372 ldg_rotor = 0;
8373
8374 if (port == 0) {
8375 err = niu_ldg_assign_ldn(np, parent,
8376 ldg_num_map[ldg_rotor],
8377 LDN_MIF);
8378 if (err)
8379 return err;
8380
8381 ldg_rotor++;
8382 if (ldg_rotor == np->num_ldg)
8383 ldg_rotor = 0;
8384
8385 err = niu_ldg_assign_ldn(np, parent,
8386 ldg_num_map[ldg_rotor],
8387 LDN_DEVICE_ERROR);
8388 if (err)
8389 return err;
8390
8391 ldg_rotor++;
8392 if (ldg_rotor == np->num_ldg)
8393 ldg_rotor = 0;
8394
8395 }
8396
8397 first_chan = 0;
8398 for (i = 0; i < port; i++)
8399 first_chan += parent->rxchan_per_port[port];
8400 num_chan = parent->rxchan_per_port[port];
8401
8402 for (i = first_chan; i < (first_chan + num_chan); i++) {
8403 err = niu_ldg_assign_ldn(np, parent,
8404 ldg_num_map[ldg_rotor],
8405 LDN_RXDMA(i));
8406 if (err)
8407 return err;
8408 ldg_rotor++;
8409 if (ldg_rotor == np->num_ldg)
8410 ldg_rotor = 0;
8411 }
8412
8413 first_chan = 0;
8414 for (i = 0; i < port; i++)
8415 first_chan += parent->txchan_per_port[port];
8416 num_chan = parent->txchan_per_port[port];
8417 for (i = first_chan; i < (first_chan + num_chan); i++) {
8418 err = niu_ldg_assign_ldn(np, parent,
8419 ldg_num_map[ldg_rotor],
8420 LDN_TXDMA(i));
8421 if (err)
8422 return err;
8423 ldg_rotor++;
8424 if (ldg_rotor == np->num_ldg)
8425 ldg_rotor = 0;
8426 }
8427
8428 return 0;
8429}
8430
8431static void __devexit niu_ldg_free(struct niu *np)
8432{
8433 if (np->flags & NIU_FLAGS_MSIX)
8434 pci_disable_msix(np->pdev);
8435}
8436
8437static int __devinit niu_get_of_props(struct niu *np)
8438{
8439#ifdef CONFIG_SPARC64
8440 struct net_device *dev = np->dev;
8441 struct device_node *dp;
8442 const char *phy_type;
8443 const u8 *mac_addr;
f9af8574 8444 const char *model;
a3138df9
DM		 8445 int prop_len;
8446
8447 if (np->parent->plat_type == PLAT_TYPE_NIU)
8448 dp = np->op->node;
8449 else
8450 dp = pci_device_to_OF_node(np->pdev);
8451
8452 phy_type = of_get_property(dp, "phy-type", &prop_len);
8453 if (!phy_type) {
8454 dev_err(np->device, PFX "%s: OF node lacks "
8455 "phy-type property\n",
8456 dp->full_name);
8457 return -EINVAL;
8458 }
8459
8460 if (!strcmp(phy_type, "none"))
8461 return -ENODEV;
8462
8463 strcpy(np->vpd.phy_type, phy_type);
8464
8465 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8466 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
8467 dp->full_name, np->vpd.phy_type);
8468 return -EINVAL;
8469 }
8470
8471 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
8472 if (!mac_addr) {
8473 dev_err(np->device, PFX "%s: OF node lacks "
8474 "local-mac-address property\n",
8475 dp->full_name);
8476 return -EINVAL;
8477 }
8478 if (prop_len != dev->addr_len) {
8479 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
8480 "is wrong.\n",
8481 dp->full_name, prop_len);
8482 }
8483 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
8484 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8485 int i;
8486
8487 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
8488 dp->full_name);
8489 dev_err(np->device, PFX "%s: [ \n",
8490 dp->full_name);
8491 for (i = 0; i < 6; i++)
8492 printk("%02x ", dev->perm_addr[i]);
8493 printk("]\n");
8494 return -EINVAL;
8495 }
8496
8497 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
f9af8574
MW		 8498
8499 model = of_get_property(dp, "model", &prop_len);
8500
8501 if (model)
8502 strcpy(np->vpd.model, model);
a3138df9
DM		 8503
8504 return 0;
8505#else
8506 return -EINVAL;
8507#endif
8508}
8509
8510static int __devinit niu_get_invariants(struct niu *np)
8511{
8512 int err, have_props;
8513 u32 offset;
8514
8515 err = niu_get_of_props(np);
8516 if (err == -ENODEV)
8517 return err;
8518
8519 have_props = !err;
8520
a3138df9
DM		 8521 err = niu_init_mac_ipp_pcs_base(np);
8522 if (err)
8523 return err;
8524
7f7c4072
MW		 8525 if (have_props) {
8526 err = niu_get_and_validate_port(np);
8527 if (err)
8528 return err;
8529
8530 } else {
a3138df9
DM		 8531 if (np->parent->plat_type == PLAT_TYPE_NIU)
8532 return -EINVAL;
8533
8534 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
8535 offset = niu_pci_vpd_offset(np);
8536 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
8537 offset);
8538 if (offset)
8539 niu_pci_vpd_fetch(np, offset);
8540 nw64(ESPC_PIO_EN, 0);
8541
7f7c4072 8542 if (np->flags & NIU_FLAGS_VPD_VALID) {
a3138df9 8543 niu_pci_vpd_validate(np);
7f7c4072
MW		 8544 err = niu_get_and_validate_port(np);
8545 if (err)
8546 return err;
8547 }
a3138df9
DM		 8548
8549 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7f7c4072
MW		 8550 err = niu_get_and_validate_port(np);
8551 if (err)
8552 return err;
a3138df9
DM		 8553 err = niu_pci_probe_sprom(np);
8554 if (err)
8555 return err;
8556 }
8557 }
8558
8559 err = niu_probe_ports(np);
8560 if (err)
8561 return err;
8562
8563 niu_ldg_init(np);
8564
8565 niu_classifier_swstate_init(np);
8566 niu_link_config_init(np);
8567
8568 err = niu_determine_phy_disposition(np);
8569 if (!err)
8570 err = niu_init_link(np);
8571
8572 return err;
8573}
8574
8575static LIST_HEAD(niu_parent_list);
8576static DEFINE_MUTEX(niu_parent_lock);
8577static int niu_parent_index;
8578
8579static ssize_t show_port_phy(struct device *dev,
8580 struct device_attribute *attr, char *buf)
8581{
8582 struct platform_device *plat_dev = to_platform_device(dev);
8583 struct niu_parent *p = plat_dev->dev.platform_data;
8584 u32 port_phy = p->port_phy;
8585 char *orig_buf = buf;
8586 int i;
8587
8588 if (port_phy == PORT_PHY_UNKNOWN ||
8589 port_phy == PORT_PHY_INVALID)
8590 return 0;
8591
8592 for (i = 0; i < p->num_ports; i++) {
8593 const char *type_str;
8594 int type;
8595
8596 type = phy_decode(port_phy, i);
8597 if (type == PORT_TYPE_10G)
8598 type_str = "10G";
8599 else
8600 type_str = "1G";
8601 buf += sprintf(buf,
8602 (i == 0) ? "%s" : " %s",
8603 type_str);
8604 }
8605 buf += sprintf(buf, "\n");
8606 return buf - orig_buf;
8607}
8608
8609static ssize_t show_plat_type(struct device *dev,
8610 struct device_attribute *attr, char *buf)
8611{
8612 struct platform_device *plat_dev = to_platform_device(dev);
8613 struct niu_parent *p = plat_dev->dev.platform_data;
8614 const char *type_str;
8615
8616 switch (p->plat_type) {
8617 case PLAT_TYPE_ATLAS:
8618 type_str = "atlas";
8619 break;
8620 case PLAT_TYPE_NIU:
8621 type_str = "niu";
8622 break;
8623 case PLAT_TYPE_VF_P0:
8624 type_str = "vf_p0";
8625 break;
8626 case PLAT_TYPE_VF_P1:
8627 type_str = "vf_p1";
8628 break;
8629 default:
8630 type_str = "unknown";
8631 break;
8632 }
8633
8634 return sprintf(buf, "%s\n", type_str);
8635}
8636
8637static ssize_t __show_chan_per_port(struct device *dev,
8638 struct device_attribute *attr, char *buf,
8639 int rx)
8640{
8641 struct platform_device *plat_dev = to_platform_device(dev);
8642 struct niu_parent *p = plat_dev->dev.platform_data;
8643 char *orig_buf = buf;
8644 u8 *arr;
8645 int i;
8646
8647 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
8648
8649 for (i = 0; i < p->num_ports; i++) {
8650 buf += sprintf(buf,
8651 (i == 0) ? "%d" : " %d",
8652 arr[i]);
8653 }
8654 buf += sprintf(buf, "\n");
8655
8656 return buf - orig_buf;
8657}
8658
8659static ssize_t show_rxchan_per_port(struct device *dev,
8660 struct device_attribute *attr, char *buf)
8661{
8662 return __show_chan_per_port(dev, attr, buf, 1);
8663}
8664
8665static ssize_t show_txchan_per_port(struct device *dev,
8666 struct device_attribute *attr, char *buf)
8667{
8668 return __show_chan_per_port(dev, attr, buf, 1);
8669}
8670
8671static ssize_t show_num_ports(struct device *dev,
8672 struct device_attribute *attr, char *buf)
8673{
8674 struct platform_device *plat_dev = to_platform_device(dev);
8675 struct niu_parent *p = plat_dev->dev.platform_data;
8676
8677 return sprintf(buf, "%d\n", p->num_ports);
8678}
8679
8680static struct device_attribute niu_parent_attributes[] = {
8681 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
8682 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
8683 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
8684 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
8685 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
8686 {}
8687};
8688
8689static struct niu_parent * __devinit niu_new_parent(struct niu *np,
8690 union niu_parent_id *id,
8691 u8 ptype)
8692{
8693 struct platform_device *plat_dev;
8694 struct niu_parent *p;
8695 int i;
8696
8697 niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
8698
8699 plat_dev = platform_device_register_simple("niu", niu_parent_index,
8700 NULL, 0);
8701 if (!plat_dev)
8702 return NULL;
8703
8704 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
8705 int err = device_create_file(&plat_dev->dev,
8706 &niu_parent_attributes[i]);
8707 if (err)
8708 goto fail_unregister;
8709 }
8710
8711 p = kzalloc(sizeof(*p), GFP_KERNEL);
8712 if (!p)
8713 goto fail_unregister;
8714
8715 p->index = niu_parent_index++;
8716
8717 plat_dev->dev.platform_data = p;
8718 p->plat_dev = plat_dev;
8719
8720 memcpy(&p->id, id, sizeof(*id));
8721 p->plat_type = ptype;
8722 INIT_LIST_HEAD(&p->list);
8723 atomic_set(&p->refcnt, 0);
8724 list_add(&p->list, &niu_parent_list);
8725 spin_lock_init(&p->lock);
8726
8727 p->rxdma_clock_divider = 7500;
8728
8729 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
8730 if (p->plat_type == PLAT_TYPE_NIU)
8731 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
8732
8733 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
8734 int index = i - CLASS_CODE_USER_PROG1;
8735
8736 p->tcam_key[index] = TCAM_KEY_TSEL;
8737 p->flow_key[index] = (FLOW_KEY_IPSA |
8738 FLOW_KEY_IPDA |
8739 FLOW_KEY_PROTO |
8740 (FLOW_KEY_L4_BYTE12 <<
8741 FLOW_KEY_L4_0_SHIFT) |
8742 (FLOW_KEY_L4_BYTE12 <<
8743 FLOW_KEY_L4_1_SHIFT));
8744 }
8745
8746 for (i = 0; i < LDN_MAX + 1; i++)
8747 p->ldg_map[i] = LDG_INVALID;
8748
8749 return p;
8750
8751fail_unregister:
8752 platform_device_unregister(plat_dev);
8753 return NULL;
8754}
8755
8756static struct niu_parent * __devinit niu_get_parent(struct niu *np,
8757 union niu_parent_id *id,
8758 u8 ptype)
8759{
8760 struct niu_parent *p, *tmp;
8761 int port = np->port;
8762
8763 niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
8764 ptype, port);
8765
8766 mutex_lock(&niu_parent_lock);
8767 p = NULL;
8768 list_for_each_entry(tmp, &niu_parent_list, list) {
8769 if (!memcmp(id, &tmp->id, sizeof(*id))) {
8770 p = tmp;
8771 break;
8772 }
8773 }
8774 if (!p)
8775 p = niu_new_parent(np, id, ptype);
8776
8777 if (p) {
8778 char port_name[6];
8779 int err;
8780
8781 sprintf(port_name, "port%d", port);
8782 err = sysfs_create_link(&p->plat_dev->dev.kobj,
8783 &np->device->kobj,
8784 port_name);
8785 if (!err) {
8786 p->ports[port] = np;
8787 atomic_inc(&p->refcnt);
8788 }
8789 }
8790 mutex_unlock(&niu_parent_lock);
8791
8792 return p;
8793}
8794
8795static void niu_put_parent(struct niu *np)
8796{
8797 struct niu_parent *p = np->parent;
8798 u8 port = np->port;
8799 char port_name[6];
8800
8801 BUG_ON(!p || p->ports[port] != np);
8802
8803 niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
8804
8805 sprintf(port_name, "port%d", port);
8806
8807 mutex_lock(&niu_parent_lock);
8808
8809 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
8810
8811 p->ports[port] = NULL;
8812 np->parent = NULL;
8813
8814 if (atomic_dec_and_test(&p->refcnt)) {
8815 list_del(&p->list);
8816 platform_device_unregister(p->plat_dev);
8817 }
8818
8819 mutex_unlock(&niu_parent_lock);
8820}
8821
8822static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
8823 u64 *handle, gfp_t flag)
8824{
8825 dma_addr_t dh;
8826 void *ret;
8827
8828 ret = dma_alloc_coherent(dev, size, &dh, flag);
8829 if (ret)
8830 *handle = dh;
8831 return ret;
8832}
8833
8834static void niu_pci_free_coherent(struct device *dev, size_t size,
8835 void *cpu_addr, u64 handle)
8836{
8837 dma_free_coherent(dev, size, cpu_addr, handle);
8838}
8839
8840static u64 niu_pci_map_page(struct device *dev, struct page *page,
8841 unsigned long offset, size_t size,
8842 enum dma_data_direction direction)
8843{
8844 return dma_map_page(dev, page, offset, size, direction);
8845}
8846
8847static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
8848 size_t size, enum dma_data_direction direction)
8849{
8850 return dma_unmap_page(dev, dma_address, size, direction);
8851}
8852
8853static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
8854 size_t size,
8855 enum dma_data_direction direction)
8856{
8857 return dma_map_single(dev, cpu_addr, size, direction);
8858}
8859
8860static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
8861 size_t size,
8862 enum dma_data_direction direction)
8863{
8864 dma_unmap_single(dev, dma_address, size, direction);
8865}
8866
8867static const struct niu_ops niu_pci_ops = {
8868 .alloc_coherent = niu_pci_alloc_coherent,
8869 .free_coherent = niu_pci_free_coherent,
8870 .map_page = niu_pci_map_page,
8871 .unmap_page = niu_pci_unmap_page,
8872 .map_single = niu_pci_map_single,
8873 .unmap_single = niu_pci_unmap_single,
8874};
8875
8876static void __devinit niu_driver_version(void)
8877{
8878 static int niu_version_printed;
8879
8880 if (niu_version_printed++ == 0)
8881 pr_info("%s", version);
8882}
8883
8884static struct net_device * __devinit niu_alloc_and_init(
8885 struct device *gen_dev, struct pci_dev *pdev,
8886 struct of_device *op, const struct niu_ops *ops,
8887 u8 port)
8888{
b4c21639 8889 struct net_device *dev;
a3138df9
DM		 8890 struct niu *np;
8891
b4c21639 8892 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
a3138df9
DM		 8893 if (!dev) {
8894 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
8895 return NULL;
8896 }
8897
8898 SET_NETDEV_DEV(dev, gen_dev);
8899
8900 np = netdev_priv(dev);
8901 np->dev = dev;
8902 np->pdev = pdev;
8903 np->op = op;
8904 np->device = gen_dev;
8905 np->ops = ops;
8906
8907 np->msg_enable = niu_debug;
8908
8909 spin_lock_init(&np->lock);
8910 INIT_WORK(&np->reset_task, niu_reset_task);
8911
8912 np->port = port;
8913
8914 return dev;
8915}
8916
2c9171d4
SH		 8917static const struct net_device_ops niu_netdev_ops = {
8918 .ndo_open = niu_open,
8919 .ndo_stop = niu_close,
00829823 8920 .ndo_start_xmit = niu_start_xmit,
2c9171d4
SH		 8921 .ndo_get_stats = niu_get_stats,
8922 .ndo_set_multicast_list = niu_set_rx_mode,
8923 .ndo_validate_addr = eth_validate_addr,
8924 .ndo_set_mac_address = niu_set_mac_addr,
8925 .ndo_do_ioctl = niu_ioctl,
8926 .ndo_tx_timeout = niu_tx_timeout,
8927 .ndo_change_mtu = niu_change_mtu,
8928};
8929
a3138df9
DM		 8930static void __devinit niu_assign_netdev_ops(struct net_device *dev)
8931{
2c9171d4 8932 dev->netdev_ops = &niu_netdev_ops;
a3138df9
DM		 8933 dev->ethtool_ops = &niu_ethtool_ops;
8934 dev->watchdog_timeo = NIU_TX_TIMEOUT;
a3138df9
DM		 8935}
8936
8937static void __devinit niu_device_announce(struct niu *np)
8938{
8939 struct net_device *dev = np->dev;
a3138df9 8940
e174961c 8941 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
a3138df9 8942
5fbd7e24
MW		 8943 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
8944 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8945 dev->name,
8946 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
8947 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
8948 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
8949 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
8950 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
8951 np->vpd.phy_type);
8952 } else {
8953 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8954 dev->name,
8955 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
8956 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
e3e081e1
SB		 8957 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
8958 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
8959 "COPPER")),
5fbd7e24
MW		 8960 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
8961 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
8962 np->vpd.phy_type);
8963 }
a3138df9
DM		 8964}
8965
8966static int __devinit niu_pci_init_one(struct pci_dev *pdev,
8967 const struct pci_device_id *ent)
8968{
a3138df9
DM		 8969 union niu_parent_id parent_id;
8970 struct net_device *dev;
8971 struct niu *np;
8972 int err, pos;
8973 u64 dma_mask;
8974 u16 val16;
8975
8976 niu_driver_version();
8977
8978 err = pci_enable_device(pdev);
8979 if (err) {
8980 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
8981 "aborting.\n");
8982 return err;
8983 }
8984
8985 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
8986 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
8987 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
8988 "base addresses, aborting.\n");
8989 err = -ENODEV;
8990 goto err_out_disable_pdev;
8991 }
8992
8993 err = pci_request_regions(pdev, DRV_MODULE_NAME);
8994 if (err) {
8995 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
8996 "aborting.\n");
8997 goto err_out_disable_pdev;
8998 }
8999
9000 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9001 if (pos <= 0) {
9002 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
9003 "aborting.\n");
9004 goto err_out_free_res;
9005 }
9006
9007 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9008 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9009 if (!dev) {
9010 err = -ENOMEM;
9011 goto err_out_free_res;
9012 }
9013 np = netdev_priv(dev);
9014
9015 memset(&parent_id, 0, sizeof(parent_id));
9016 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9017 parent_id.pci.bus = pdev->bus->number;
9018 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9019
9020 np->parent = niu_get_parent(np, &parent_id,
9021 PLAT_TYPE_ATLAS);
9022 if (!np->parent) {
9023 err = -ENOMEM;
9024 goto err_out_free_dev;
9025 }
9026
9027 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9028 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9029 val16 |= (PCI_EXP_DEVCTL_CERE |
9030 PCI_EXP_DEVCTL_NFERE |
9031 PCI_EXP_DEVCTL_FERE |
9032 PCI_EXP_DEVCTL_URRE |
9033 PCI_EXP_DEVCTL_RELAX_EN);
9034 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9035
9036 dma_mask = DMA_44BIT_MASK;
9037 err = pci_set_dma_mask(pdev, dma_mask);
9038 if (!err) {
9039 dev->features |= NETIF_F_HIGHDMA;
9040 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9041 if (err) {
9042 dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
9043 "DMA for consistent allocations, "
9044 "aborting.\n");
9045 goto err_out_release_parent;
9046 }
9047 }
9048 if (err || dma_mask == DMA_32BIT_MASK) {
9049 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
9050 if (err) {
9051 dev_err(&pdev->dev, PFX "No usable DMA configuration, "
9052 "aborting.\n");
9053 goto err_out_release_parent;
9054 }
9055 }
9056
9057 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9058
19ecb6ba 9059 np->regs = pci_ioremap_bar(pdev, 0);
a3138df9
DM		 9060 if (!np->regs) {
9061 dev_err(&pdev->dev, PFX "Cannot map device registers, "
9062 "aborting.\n");
9063 err = -ENOMEM;
9064 goto err_out_release_parent;
9065 }
9066
9067 pci_set_master(pdev);
9068 pci_save_state(pdev);
9069
9070 dev->irq = pdev->irq;
9071
9072 niu_assign_netdev_ops(dev);
9073
9074 err = niu_get_invariants(np);
9075 if (err) {
9076 if (err != -ENODEV)
9077 dev_err(&pdev->dev, PFX "Problem fetching invariants "
9078 "of chip, aborting.\n");
9079 goto err_out_iounmap;
9080 }
9081
9082 err = register_netdev(dev);
9083 if (err) {
9084 dev_err(&pdev->dev, PFX "Cannot register net device, "
9085 "aborting.\n");
9086 goto err_out_iounmap;
9087 }
9088
9089 pci_set_drvdata(pdev, dev);
9090
9091 niu_device_announce(np);
9092
9093 return 0;
9094
9095err_out_iounmap:
9096 if (np->regs) {
9097 iounmap(np->regs);
9098 np->regs = NULL;
9099 }
9100
9101err_out_release_parent:
9102 niu_put_parent(np);
9103
9104err_out_free_dev:
9105 free_netdev(dev);
9106
9107err_out_free_res:
9108 pci_release_regions(pdev);
9109
9110err_out_disable_pdev:
9111 pci_disable_device(pdev);
9112 pci_set_drvdata(pdev, NULL);
9113
9114 return err;
9115}
9116
9117static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9118{
9119 struct net_device *dev = pci_get_drvdata(pdev);
9120
9121 if (dev) {
9122 struct niu *np = netdev_priv(dev);
9123
9124 unregister_netdev(dev);
9125 if (np->regs) {
9126 iounmap(np->regs);
9127 np->regs = NULL;
9128 }
9129
9130 niu_ldg_free(np);
9131
9132 niu_put_parent(np);
9133
9134 free_netdev(dev);
9135 pci_release_regions(pdev);
9136 pci_disable_device(pdev);
9137 pci_set_drvdata(pdev, NULL);
9138 }
9139}
9140
9141static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9142{
9143 struct net_device *dev = pci_get_drvdata(pdev);
9144 struct niu *np = netdev_priv(dev);
9145 unsigned long flags;
9146
9147 if (!netif_running(dev))
9148 return 0;
9149
9150 flush_scheduled_work();
9151 niu_netif_stop(np);
9152
9153 del_timer_sync(&np->timer);
9154
9155 spin_lock_irqsave(&np->lock, flags);
9156 niu_enable_interrupts(np, 0);
9157 spin_unlock_irqrestore(&np->lock, flags);
9158
9159 netif_device_detach(dev);
9160
9161 spin_lock_irqsave(&np->lock, flags);
9162 niu_stop_hw(np);
9163 spin_unlock_irqrestore(&np->lock, flags);
9164
9165 pci_save_state(pdev);
9166
9167 return 0;
9168}
9169
9170static int niu_resume(struct pci_dev *pdev)
9171{
9172 struct net_device *dev = pci_get_drvdata(pdev);
9173 struct niu *np = netdev_priv(dev);
9174 unsigned long flags;
9175 int err;
9176
9177 if (!netif_running(dev))
9178 return 0;
9179
9180 pci_restore_state(pdev);
9181
9182 netif_device_attach(dev);
9183
9184 spin_lock_irqsave(&np->lock, flags);
9185
9186 err = niu_init_hw(np);
9187 if (!err) {
9188 np->timer.expires = jiffies + HZ;
9189 add_timer(&np->timer);
9190 niu_netif_start(np);
9191 }
9192
9193 spin_unlock_irqrestore(&np->lock, flags);
9194
9195 return err;
9196}
9197
9198static struct pci_driver niu_pci_driver = {
9199 .name = DRV_MODULE_NAME,
9200 .id_table = niu_pci_tbl,
9201 .probe = niu_pci_init_one,
9202 .remove = __devexit_p(niu_pci_remove_one),
9203 .suspend = niu_suspend,
9204 .resume = niu_resume,
9205};
9206
9207#ifdef CONFIG_SPARC64
9208static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9209 u64 *dma_addr, gfp_t flag)
9210{
9211 unsigned long order = get_order(size);
9212 unsigned long page = __get_free_pages(flag, order);
9213
9214 if (page == 0UL)
9215 return NULL;
9216 memset((char *)page, 0, PAGE_SIZE << order);
9217 *dma_addr = __pa(page);
9218
9219 return (void *) page;
9220}
9221
9222static void niu_phys_free_coherent(struct device *dev, size_t size,
9223 void *cpu_addr, u64 handle)
9224{
9225 unsigned long order = get_order(size);
9226
9227 free_pages((unsigned long) cpu_addr, order);
9228}
9229
9230static u64 niu_phys_map_page(struct device *dev, struct page *page,
9231 unsigned long offset, size_t size,
9232 enum dma_data_direction direction)
9233{
9234 return page_to_phys(page) + offset;
9235}
9236
9237static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
9238 size_t size, enum dma_data_direction direction)
9239{
9240 /* Nothing to do. */
9241}
9242
9243static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
9244 size_t size,
9245 enum dma_data_direction direction)
9246{
9247 return __pa(cpu_addr);
9248}
9249
9250static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
9251 size_t size,
9252 enum dma_data_direction direction)
9253{
9254 /* Nothing to do. */
9255}
9256
9257static const struct niu_ops niu_phys_ops = {
9258 .alloc_coherent = niu_phys_alloc_coherent,
9259 .free_coherent = niu_phys_free_coherent,
9260 .map_page = niu_phys_map_page,
9261 .unmap_page = niu_phys_unmap_page,
9262 .map_single = niu_phys_map_single,
9263 .unmap_single = niu_phys_unmap_single,
9264};
9265
9266static unsigned long res_size(struct resource *r)
9267{
9268 return r->end - r->start + 1UL;
9269}
9270
9271static int __devinit niu_of_probe(struct of_device *op,
9272 const struct of_device_id *match)
9273{
9274 union niu_parent_id parent_id;
9275 struct net_device *dev;
9276 struct niu *np;
9277 const u32 *reg;
9278 int err;
9279
9280 niu_driver_version();
9281
9282 reg = of_get_property(op->node, "reg", NULL);
9283 if (!reg) {
9284 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
9285 op->node->full_name);
9286 return -ENODEV;
9287 }
9288
9289 dev = niu_alloc_and_init(&op->dev, NULL, op,
9290 &niu_phys_ops, reg[0] & 0x1);
9291 if (!dev) {
9292 err = -ENOMEM;
9293 goto err_out;
9294 }
9295 np = netdev_priv(dev);
9296
9297 memset(&parent_id, 0, sizeof(parent_id));
9298 parent_id.of = of_get_parent(op->node);
9299
9300 np->parent = niu_get_parent(np, &parent_id,
9301 PLAT_TYPE_NIU);
9302 if (!np->parent) {
9303 err = -ENOMEM;
9304 goto err_out_free_dev;
9305 }
9306
9307 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9308
9309 np->regs = of_ioremap(&op->resource[1], 0,
9310 res_size(&op->resource[1]),
9311 "niu regs");
9312 if (!np->regs) {
9313 dev_err(&op->dev, PFX "Cannot map device registers, "
9314 "aborting.\n");
9315 err = -ENOMEM;
9316 goto err_out_release_parent;
9317 }
9318
9319 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
9320 res_size(&op->resource[2]),
9321 "niu vregs-1");
9322 if (!np->vir_regs_1) {
9323 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
9324 "aborting.\n");
9325 err = -ENOMEM;
9326 goto err_out_iounmap;
9327 }
9328
9329 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
9330 res_size(&op->resource[3]),
9331 "niu vregs-2");
9332 if (!np->vir_regs_2) {
9333 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
9334 "aborting.\n");
9335 err = -ENOMEM;
9336 goto err_out_iounmap;
9337 }
9338
9339 niu_assign_netdev_ops(dev);
9340
9341 err = niu_get_invariants(np);
9342 if (err) {
9343 if (err != -ENODEV)
9344 dev_err(&op->dev, PFX "Problem fetching invariants "
9345 "of chip, aborting.\n");
9346 goto err_out_iounmap;
9347 }
9348
9349 err = register_netdev(dev);
9350 if (err) {
9351 dev_err(&op->dev, PFX "Cannot register net device, "
9352 "aborting.\n");
9353 goto err_out_iounmap;
9354 }
9355
9356 dev_set_drvdata(&op->dev, dev);
9357
9358 niu_device_announce(np);
9359
9360 return 0;
9361
9362err_out_iounmap:
9363 if (np->vir_regs_1) {
9364 of_iounmap(&op->resource[2], np->vir_regs_1,
9365 res_size(&op->resource[2]));
9366 np->vir_regs_1 = NULL;
9367 }
9368
9369 if (np->vir_regs_2) {
9370 of_iounmap(&op->resource[3], np->vir_regs_2,
9371 res_size(&op->resource[3]));
9372 np->vir_regs_2 = NULL;
9373 }
9374
9375 if (np->regs) {
9376 of_iounmap(&op->resource[1], np->regs,
9377 res_size(&op->resource[1]));
9378 np->regs = NULL;
9379 }
9380
9381err_out_release_parent:
9382 niu_put_parent(np);
9383
9384err_out_free_dev:
9385 free_netdev(dev);
9386
9387err_out:
9388 return err;
9389}
9390
9391static int __devexit niu_of_remove(struct of_device *op)
9392{
9393 struct net_device *dev = dev_get_drvdata(&op->dev);
9394
9395 if (dev) {
9396 struct niu *np = netdev_priv(dev);
9397
9398 unregister_netdev(dev);
9399
9400 if (np->vir_regs_1) {
9401 of_iounmap(&op->resource[2], np->vir_regs_1,
9402 res_size(&op->resource[2]));
9403 np->vir_regs_1 = NULL;
9404 }
9405
9406 if (np->vir_regs_2) {
9407 of_iounmap(&op->resource[3], np->vir_regs_2,
9408 res_size(&op->resource[3]));
9409 np->vir_regs_2 = NULL;
9410 }
9411
9412 if (np->regs) {
9413 of_iounmap(&op->resource[1], np->regs,
9414 res_size(&op->resource[1]));
9415 np->regs = NULL;
9416 }
9417
9418 niu_ldg_free(np);
9419
9420 niu_put_parent(np);
9421
9422 free_netdev(dev);
9423 dev_set_drvdata(&op->dev, NULL);
9424 }
9425 return 0;
9426}
9427
fd098316 9428static const struct of_device_id niu_match[] = {
a3138df9
DM		 9429 {
9430 .name = "network",
9431 .compatible = "SUNW,niusl",
9432 },
9433 {},
9434};
9435MODULE_DEVICE_TABLE(of, niu_match);
9436
9437static struct of_platform_driver niu_of_driver = {
9438 .name = "niu",
9439 .match_table = niu_match,
9440 .probe = niu_of_probe,
9441 .remove = __devexit_p(niu_of_remove),
9442};
9443
9444#endif /* CONFIG_SPARC64 */
9445
9446static int __init niu_init(void)
9447{
9448 int err = 0;
9449
81429973 9450 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
a3138df9
DM		 9451
9452 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
9453
9454#ifdef CONFIG_SPARC64
9455 err = of_register_driver(&niu_of_driver, &of_bus_type);
9456#endif
9457
9458 if (!err) {
9459 err = pci_register_driver(&niu_pci_driver);
9460#ifdef CONFIG_SPARC64
9461 if (err)
9462 of_unregister_driver(&niu_of_driver);
9463#endif
9464 }
9465
9466 return err;
9467}
9468
9469static void __exit niu_exit(void)
9470{
9471 pci_unregister_driver(&niu_pci_driver);
9472#ifdef CONFIG_SPARC64
9473 of_unregister_driver(&niu_of_driver);
9474#endif
9475}
9476
9477module_init(niu_init);
9478module_exit(niu_exit);
Linux kernel - Deliverables
This page took 0.635826 seconds and 5 git commands to generate.