Commit | Line | Data |
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f5cd7872 OJ |
1 | /* |
2 | * Copyright (C) 2006-2007 PA Semi, Inc | |
3 | * | |
4 | * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/dmaengine.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/netdevice.h> | |
27 | #include <linux/etherdevice.h> | |
28 | #include <asm/dma-mapping.h> | |
29 | #include <linux/in.h> | |
30 | #include <linux/skbuff.h> | |
31 | ||
32 | #include <linux/ip.h> | |
33 | #include <linux/tcp.h> | |
34 | #include <net/checksum.h> | |
35 | ||
771f7404 | 36 | #include <asm/irq.h> |
af289e80 | 37 | #include <asm/firmware.h> |
771f7404 | 38 | |
f5cd7872 OJ |
39 | #include "pasemi_mac.h" |
40 | ||
8dc121a4 OJ |
41 | /* We have our own align, since ppc64 in general has it at 0 because |
42 | * of design flaws in some of the server bridge chips. However, for | |
43 | * PWRficient doing the unaligned copies is more expensive than doing | |
44 | * unaligned DMA, so make sure the data is aligned instead. | |
45 | */ | |
46 | #define LOCAL_SKB_ALIGN 2 | |
f5cd7872 OJ |
47 | |
48 | /* TODO list | |
49 | * | |
f5cd7872 OJ |
50 | * - Multicast support |
51 | * - Large MTU support | |
7ddeae2c OJ |
52 | * - SW LRO |
53 | * - Multiqueue RX/TX | |
f5cd7872 OJ |
54 | */ |
55 | ||
56 | ||
57 | /* Must be a power of two */ | |
ad5da10a OJ |
58 | #define RX_RING_SIZE 4096 |
59 | #define TX_RING_SIZE 4096 | |
f5cd7872 | 60 | |
ceb51361 OJ |
61 | #define DEFAULT_MSG_ENABLE \ |
62 | (NETIF_MSG_DRV | \ | |
63 | NETIF_MSG_PROBE | \ | |
64 | NETIF_MSG_LINK | \ | |
65 | NETIF_MSG_TIMER | \ | |
66 | NETIF_MSG_IFDOWN | \ | |
67 | NETIF_MSG_IFUP | \ | |
68 | NETIF_MSG_RX_ERR | \ | |
69 | NETIF_MSG_TX_ERR) | |
70 | ||
fc9e4d2a OJ |
71 | #define TX_RING(mac, num) ((mac)->tx->ring[(num) & (TX_RING_SIZE-1)]) |
72 | #define TX_RING_INFO(mac, num) ((mac)->tx->ring_info[(num) & (TX_RING_SIZE-1)]) | |
73 | #define RX_RING(mac, num) ((mac)->rx->ring[(num) & (RX_RING_SIZE-1)]) | |
74 | #define RX_RING_INFO(mac, num) ((mac)->rx->ring_info[(num) & (RX_RING_SIZE-1)]) | |
f5cd7872 OJ |
75 | #define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)]) |
76 | ||
021fa22e OJ |
77 | #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \ |
78 | & ((ring)->size - 1)) | |
79 | #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring)) | |
80 | ||
f5cd7872 OJ |
81 | #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ |
82 | ||
ceb51361 OJ |
83 | MODULE_LICENSE("GPL"); |
84 | MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>"); | |
85 | MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver"); | |
86 | ||
87 | static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */ | |
88 | module_param(debug, int, 0); | |
89 | MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value"); | |
f5cd7872 OJ |
90 | |
91 | static struct pasdma_status *dma_status; | |
92 | ||
af289e80 OJ |
93 | static int translation_enabled(void) |
94 | { | |
95 | #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE) | |
96 | return 1; | |
97 | #else | |
98 | return firmware_has_feature(FW_FEATURE_LPAR); | |
99 | #endif | |
100 | } | |
101 | ||
a85b9422 OJ |
102 | static void write_iob_reg(struct pasemi_mac *mac, unsigned int reg, |
103 | unsigned int val) | |
104 | { | |
b6e05a1b | 105 | out_le32(mac->iob_regs+reg, val); |
a85b9422 OJ |
106 | } |
107 | ||
108 | static unsigned int read_mac_reg(struct pasemi_mac *mac, unsigned int reg) | |
109 | { | |
b6e05a1b | 110 | return in_le32(mac->regs+reg); |
a85b9422 OJ |
111 | } |
112 | ||
113 | static void write_mac_reg(struct pasemi_mac *mac, unsigned int reg, | |
114 | unsigned int val) | |
115 | { | |
b6e05a1b | 116 | out_le32(mac->regs+reg, val); |
a85b9422 OJ |
117 | } |
118 | ||
119 | static unsigned int read_dma_reg(struct pasemi_mac *mac, unsigned int reg) | |
120 | { | |
b6e05a1b | 121 | return in_le32(mac->dma_regs+reg); |
a85b9422 OJ |
122 | } |
123 | ||
124 | static void write_dma_reg(struct pasemi_mac *mac, unsigned int reg, | |
125 | unsigned int val) | |
126 | { | |
b6e05a1b | 127 | out_le32(mac->dma_regs+reg, val); |
a85b9422 OJ |
128 | } |
129 | ||
f5cd7872 OJ |
130 | static int pasemi_get_mac_addr(struct pasemi_mac *mac) |
131 | { | |
132 | struct pci_dev *pdev = mac->pdev; | |
133 | struct device_node *dn = pci_device_to_OF_node(pdev); | |
1af7f056 | 134 | int len; |
f5cd7872 OJ |
135 | const u8 *maddr; |
136 | u8 addr[6]; | |
137 | ||
138 | if (!dn) { | |
139 | dev_dbg(&pdev->dev, | |
140 | "No device node for mac, not configuring\n"); | |
141 | return -ENOENT; | |
142 | } | |
143 | ||
1af7f056 | 144 | maddr = of_get_property(dn, "local-mac-address", &len); |
145 | ||
146 | if (maddr && len == 6) { | |
147 | memcpy(mac->mac_addr, maddr, 6); | |
148 | return 0; | |
149 | } | |
150 | ||
151 | /* Some old versions of firmware mistakenly uses mac-address | |
152 | * (and as a string) instead of a byte array in local-mac-address. | |
153 | */ | |
a5fd22eb | 154 | |
a5fd22eb | 155 | if (maddr == NULL) |
9028780a | 156 | maddr = of_get_property(dn, "mac-address", NULL); |
a5fd22eb | 157 | |
f5cd7872 OJ |
158 | if (maddr == NULL) { |
159 | dev_warn(&pdev->dev, | |
160 | "no mac address in device tree, not configuring\n"); | |
161 | return -ENOENT; | |
162 | } | |
163 | ||
1af7f056 | 164 | |
f5cd7872 OJ |
165 | if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0], |
166 | &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) { | |
167 | dev_warn(&pdev->dev, | |
168 | "can't parse mac address, not configuring\n"); | |
169 | return -EINVAL; | |
170 | } | |
171 | ||
1af7f056 | 172 | memcpy(mac->mac_addr, addr, 6); |
173 | ||
f5cd7872 OJ |
174 | return 0; |
175 | } | |
176 | ||
ad3c20d1 OJ |
177 | static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac, |
178 | struct sk_buff *skb, | |
179 | dma_addr_t *dmas) | |
180 | { | |
181 | int f; | |
182 | int nfrags = skb_shinfo(skb)->nr_frags; | |
183 | ||
184 | pci_unmap_single(mac->dma_pdev, dmas[0], skb_headlen(skb), | |
185 | PCI_DMA_TODEVICE); | |
186 | ||
187 | for (f = 0; f < nfrags; f++) { | |
188 | skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; | |
189 | ||
190 | pci_unmap_page(mac->dma_pdev, dmas[f+1], frag->size, | |
191 | PCI_DMA_TODEVICE); | |
192 | } | |
193 | dev_kfree_skb_irq(skb); | |
194 | ||
195 | /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs, | |
196 | * aligned up to a power of 2 | |
197 | */ | |
198 | return (nfrags + 3) & ~1; | |
199 | } | |
200 | ||
f5cd7872 OJ |
201 | static int pasemi_mac_setup_rx_resources(struct net_device *dev) |
202 | { | |
203 | struct pasemi_mac_rxring *ring; | |
204 | struct pasemi_mac *mac = netdev_priv(dev); | |
205 | int chan_id = mac->dma_rxch; | |
af289e80 | 206 | unsigned int cfg; |
f5cd7872 OJ |
207 | |
208 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
209 | ||
210 | if (!ring) | |
211 | goto out_ring; | |
212 | ||
213 | spin_lock_init(&ring->lock); | |
214 | ||
021fa22e | 215 | ring->size = RX_RING_SIZE; |
fc9e4d2a | 216 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 OJ |
217 | RX_RING_SIZE, GFP_KERNEL); |
218 | ||
fc9e4d2a OJ |
219 | if (!ring->ring_info) |
220 | goto out_ring_info; | |
f5cd7872 OJ |
221 | |
222 | /* Allocate descriptors */ | |
fc9e4d2a OJ |
223 | ring->ring = dma_alloc_coherent(&mac->dma_pdev->dev, |
224 | RX_RING_SIZE * sizeof(u64), | |
f5cd7872 OJ |
225 | &ring->dma, GFP_KERNEL); |
226 | ||
fc9e4d2a OJ |
227 | if (!ring->ring) |
228 | goto out_ring_desc; | |
f5cd7872 | 229 | |
fc9e4d2a | 230 | memset(ring->ring, 0, RX_RING_SIZE * sizeof(u64)); |
f5cd7872 OJ |
231 | |
232 | ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev, | |
233 | RX_RING_SIZE * sizeof(u64), | |
234 | &ring->buf_dma, GFP_KERNEL); | |
235 | if (!ring->buffers) | |
236 | goto out_buffers; | |
237 | ||
238 | memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64)); | |
239 | ||
a85b9422 | 240 | write_dma_reg(mac, PAS_DMA_RXCHAN_BASEL(chan_id), PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma)); |
f5cd7872 | 241 | |
a85b9422 OJ |
242 | write_dma_reg(mac, PAS_DMA_RXCHAN_BASEU(chan_id), |
243 | PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) | | |
fc9e4d2a | 244 | PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3)); |
f5cd7872 | 245 | |
af289e80 OJ |
246 | cfg = PAS_DMA_RXCHAN_CFG_HBU(2); |
247 | ||
248 | if (translation_enabled()) | |
249 | cfg |= PAS_DMA_RXCHAN_CFG_CTR; | |
250 | ||
251 | write_dma_reg(mac, PAS_DMA_RXCHAN_CFG(chan_id), cfg); | |
f5cd7872 | 252 | |
a85b9422 | 253 | write_dma_reg(mac, PAS_DMA_RXINT_BASEL(mac->dma_if), |
af289e80 | 254 | PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma)); |
f5cd7872 | 255 | |
a85b9422 | 256 | write_dma_reg(mac, PAS_DMA_RXINT_BASEU(mac->dma_if), |
af289e80 | 257 | PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) | |
a85b9422 | 258 | PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); |
f5cd7872 | 259 | |
af289e80 OJ |
260 | cfg = PAS_DMA_RXINT_CFG_DHL(3) | PAS_DMA_RXINT_CFG_L2 | |
261 | PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP | | |
262 | PAS_DMA_RXINT_CFG_HEN; | |
263 | ||
264 | if (translation_enabled()) | |
265 | cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR; | |
266 | ||
267 | write_dma_reg(mac, PAS_DMA_RXINT_CFG(mac->dma_if), cfg); | |
c0efd52b | 268 | |
f5cd7872 OJ |
269 | ring->next_to_fill = 0; |
270 | ring->next_to_clean = 0; | |
271 | ||
272 | snprintf(ring->irq_name, sizeof(ring->irq_name), | |
273 | "%s rx", dev->name); | |
274 | mac->rx = ring; | |
275 | ||
276 | return 0; | |
277 | ||
278 | out_buffers: | |
279 | dma_free_coherent(&mac->dma_pdev->dev, | |
fc9e4d2a OJ |
280 | RX_RING_SIZE * sizeof(u64), |
281 | mac->rx->ring, mac->rx->dma); | |
282 | out_ring_desc: | |
283 | kfree(ring->ring_info); | |
284 | out_ring_info: | |
f5cd7872 OJ |
285 | kfree(ring); |
286 | out_ring: | |
287 | return -ENOMEM; | |
288 | } | |
289 | ||
290 | ||
291 | static int pasemi_mac_setup_tx_resources(struct net_device *dev) | |
292 | { | |
293 | struct pasemi_mac *mac = netdev_priv(dev); | |
294 | u32 val; | |
295 | int chan_id = mac->dma_txch; | |
296 | struct pasemi_mac_txring *ring; | |
af289e80 | 297 | unsigned int cfg; |
f5cd7872 OJ |
298 | |
299 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
300 | if (!ring) | |
301 | goto out_ring; | |
302 | ||
303 | spin_lock_init(&ring->lock); | |
304 | ||
021fa22e | 305 | ring->size = TX_RING_SIZE; |
fc9e4d2a | 306 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 | 307 | TX_RING_SIZE, GFP_KERNEL); |
fc9e4d2a OJ |
308 | if (!ring->ring_info) |
309 | goto out_ring_info; | |
f5cd7872 OJ |
310 | |
311 | /* Allocate descriptors */ | |
fc9e4d2a OJ |
312 | ring->ring = dma_alloc_coherent(&mac->dma_pdev->dev, |
313 | TX_RING_SIZE * sizeof(u64), | |
f5cd7872 | 314 | &ring->dma, GFP_KERNEL); |
fc9e4d2a OJ |
315 | if (!ring->ring) |
316 | goto out_ring_desc; | |
f5cd7872 | 317 | |
fc9e4d2a | 318 | memset(ring->ring, 0, TX_RING_SIZE * sizeof(u64)); |
f5cd7872 | 319 | |
a85b9422 OJ |
320 | write_dma_reg(mac, PAS_DMA_TXCHAN_BASEL(chan_id), |
321 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); | |
f5cd7872 | 322 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); |
fc9e4d2a | 323 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3); |
f5cd7872 | 324 | |
a85b9422 | 325 | write_dma_reg(mac, PAS_DMA_TXCHAN_BASEU(chan_id), val); |
f5cd7872 | 326 | |
af289e80 OJ |
327 | cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE | |
328 | PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | | |
329 | PAS_DMA_TXCHAN_CFG_UP | | |
330 | PAS_DMA_TXCHAN_CFG_WT(2); | |
331 | ||
332 | if (translation_enabled()) | |
333 | cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; | |
334 | ||
335 | write_dma_reg(mac, PAS_DMA_TXCHAN_CFG(chan_id), cfg); | |
f5cd7872 | 336 | |
021fa22e | 337 | ring->next_to_fill = 0; |
f5cd7872 OJ |
338 | ring->next_to_clean = 0; |
339 | ||
340 | snprintf(ring->irq_name, sizeof(ring->irq_name), | |
341 | "%s tx", dev->name); | |
342 | mac->tx = ring; | |
343 | ||
344 | return 0; | |
345 | ||
fc9e4d2a OJ |
346 | out_ring_desc: |
347 | kfree(ring->ring_info); | |
348 | out_ring_info: | |
f5cd7872 OJ |
349 | kfree(ring); |
350 | out_ring: | |
351 | return -ENOMEM; | |
352 | } | |
353 | ||
354 | static void pasemi_mac_free_tx_resources(struct net_device *dev) | |
355 | { | |
356 | struct pasemi_mac *mac = netdev_priv(dev); | |
ad3c20d1 | 357 | unsigned int i, j; |
f5cd7872 | 358 | struct pasemi_mac_buffer *info; |
ad3c20d1 OJ |
359 | dma_addr_t dmas[MAX_SKB_FRAGS+1]; |
360 | int freed; | |
ad5da10a | 361 | int start, limit; |
fc9e4d2a | 362 | |
ad5da10a OJ |
363 | start = mac->tx->next_to_clean; |
364 | limit = mac->tx->next_to_fill; | |
365 | ||
366 | /* Compensate for when fill has wrapped and clean has not */ | |
367 | if (start > limit) | |
368 | limit += TX_RING_SIZE; | |
369 | ||
370 | for (i = start; i < limit; i += freed) { | |
fc9e4d2a OJ |
371 | info = &TX_RING_INFO(mac, i+1); |
372 | if (info->dma && info->skb) { | |
ad3c20d1 OJ |
373 | for (j = 0; j <= skb_shinfo(info->skb)->nr_frags; j++) |
374 | dmas[j] = TX_RING_INFO(mac, i+1+j).dma; | |
375 | freed = pasemi_mac_unmap_tx_skb(mac, info->skb, dmas); | |
376 | } else | |
377 | freed = 2; | |
f5cd7872 OJ |
378 | } |
379 | ||
ad3c20d1 OJ |
380 | for (i = 0; i < TX_RING_SIZE; i++) |
381 | TX_RING(mac, i) = 0; | |
382 | ||
f5cd7872 | 383 | dma_free_coherent(&mac->dma_pdev->dev, |
fc9e4d2a OJ |
384 | TX_RING_SIZE * sizeof(u64), |
385 | mac->tx->ring, mac->tx->dma); | |
f5cd7872 | 386 | |
fc9e4d2a | 387 | kfree(mac->tx->ring_info); |
f5cd7872 OJ |
388 | kfree(mac->tx); |
389 | mac->tx = NULL; | |
390 | } | |
391 | ||
392 | static void pasemi_mac_free_rx_resources(struct net_device *dev) | |
393 | { | |
394 | struct pasemi_mac *mac = netdev_priv(dev); | |
395 | unsigned int i; | |
396 | struct pasemi_mac_buffer *info; | |
f5cd7872 OJ |
397 | |
398 | for (i = 0; i < RX_RING_SIZE; i++) { | |
fc9e4d2a OJ |
399 | info = &RX_RING_INFO(mac, i); |
400 | if (info->skb && info->dma) { | |
401 | pci_unmap_single(mac->dma_pdev, | |
402 | info->dma, | |
403 | info->skb->len, | |
404 | PCI_DMA_FROMDEVICE); | |
405 | dev_kfree_skb_any(info->skb); | |
f5cd7872 | 406 | } |
fc9e4d2a OJ |
407 | info->dma = 0; |
408 | info->skb = NULL; | |
f5cd7872 OJ |
409 | } |
410 | ||
fc9e4d2a OJ |
411 | for (i = 0; i < RX_RING_SIZE; i++) |
412 | RX_RING(mac, i) = 0; | |
413 | ||
f5cd7872 | 414 | dma_free_coherent(&mac->dma_pdev->dev, |
fc9e4d2a OJ |
415 | RX_RING_SIZE * sizeof(u64), |
416 | mac->rx->ring, mac->rx->dma); | |
f5cd7872 OJ |
417 | |
418 | dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64), | |
419 | mac->rx->buffers, mac->rx->buf_dma); | |
420 | ||
fc9e4d2a | 421 | kfree(mac->rx->ring_info); |
f5cd7872 OJ |
422 | kfree(mac->rx); |
423 | mac->rx = NULL; | |
424 | } | |
425 | ||
928773c2 | 426 | static void pasemi_mac_replenish_rx_ring(struct net_device *dev, int limit) |
f5cd7872 OJ |
427 | { |
428 | struct pasemi_mac *mac = netdev_priv(dev); | |
b5254eee | 429 | int fill, count; |
f5cd7872 | 430 | |
cd4ceb24 | 431 | if (limit <= 0) |
f5cd7872 OJ |
432 | return; |
433 | ||
b5254eee | 434 | fill = mac->rx->next_to_fill; |
928773c2 | 435 | for (count = 0; count < limit; count++) { |
fc9e4d2a OJ |
436 | struct pasemi_mac_buffer *info = &RX_RING_INFO(mac, fill); |
437 | u64 *buff = &RX_BUFF(mac, fill); | |
f5cd7872 OJ |
438 | struct sk_buff *skb; |
439 | dma_addr_t dma; | |
440 | ||
fc9e4d2a OJ |
441 | /* Entry in use? */ |
442 | WARN_ON(*buff); | |
443 | ||
9f05cfe2 OJ |
444 | /* skb might still be in there for recycle on short receives */ |
445 | if (info->skb) | |
446 | skb = info->skb; | |
8dc121a4 | 447 | else { |
9f05cfe2 | 448 | skb = dev_alloc_skb(BUF_SIZE); |
8dc121a4 OJ |
449 | skb_reserve(skb, LOCAL_SKB_ALIGN); |
450 | } | |
f5cd7872 | 451 | |
9f05cfe2 | 452 | if (unlikely(!skb)) |
f5cd7872 | 453 | break; |
f5cd7872 | 454 | |
8dc121a4 OJ |
455 | dma = pci_map_single(mac->dma_pdev, skb->data, |
456 | BUF_SIZE - LOCAL_SKB_ALIGN, | |
f5cd7872 OJ |
457 | PCI_DMA_FROMDEVICE); |
458 | ||
cd4ceb24 | 459 | if (unlikely(dma_mapping_error(dma))) { |
f5cd7872 | 460 | dev_kfree_skb_irq(info->skb); |
f5cd7872 OJ |
461 | break; |
462 | } | |
463 | ||
464 | info->skb = skb; | |
465 | info->dma = dma; | |
466 | *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma); | |
fc9e4d2a | 467 | fill++; |
f5cd7872 OJ |
468 | } |
469 | ||
470 | wmb(); | |
471 | ||
928773c2 | 472 | write_dma_reg(mac, PAS_DMA_RXINT_INCR(mac->dma_if), count); |
f5cd7872 | 473 | |
b5254eee OJ |
474 | mac->rx->next_to_fill = (mac->rx->next_to_fill + count) & |
475 | (RX_RING_SIZE - 1); | |
f5cd7872 OJ |
476 | } |
477 | ||
1b0335ea OJ |
478 | static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac) |
479 | { | |
52a94351 | 480 | unsigned int reg, pcnt; |
1b0335ea OJ |
481 | /* Re-enable packet count interrupts: finally |
482 | * ack the packet count interrupt we got in rx_intr. | |
483 | */ | |
484 | ||
52a94351 | 485 | pcnt = *mac->rx_status & PAS_STATUS_PCNT_M; |
1b0335ea | 486 | |
52a94351 | 487 | reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; |
1b0335ea | 488 | |
a85b9422 | 489 | write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg); |
1b0335ea OJ |
490 | } |
491 | ||
492 | static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac) | |
493 | { | |
52a94351 | 494 | unsigned int reg, pcnt; |
1b0335ea OJ |
495 | |
496 | /* Re-enable packet count interrupts */ | |
52a94351 | 497 | pcnt = *mac->tx_status & PAS_STATUS_PCNT_M; |
1b0335ea | 498 | |
52a94351 | 499 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; |
1b0335ea | 500 | |
a85b9422 | 501 | write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg); |
1b0335ea OJ |
502 | } |
503 | ||
504 | ||
69c29d89 OJ |
505 | static inline void pasemi_mac_rx_error(struct pasemi_mac *mac, u64 macrx) |
506 | { | |
507 | unsigned int rcmdsta, ccmdsta; | |
508 | ||
509 | if (!netif_msg_rx_err(mac)) | |
510 | return; | |
511 | ||
512 | rcmdsta = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); | |
513 | ccmdsta = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch)); | |
514 | ||
515 | printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n", | |
516 | macrx, *mac->rx_status); | |
517 | ||
518 | printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n", | |
519 | rcmdsta, ccmdsta); | |
520 | } | |
521 | ||
522 | static inline void pasemi_mac_tx_error(struct pasemi_mac *mac, u64 mactx) | |
523 | { | |
524 | unsigned int cmdsta; | |
525 | ||
526 | if (!netif_msg_tx_err(mac)) | |
527 | return; | |
528 | ||
529 | cmdsta = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch)); | |
530 | ||
531 | printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\ | |
532 | "tx status 0x%016lx\n", mactx, *mac->tx_status); | |
533 | ||
534 | printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta); | |
535 | } | |
536 | ||
f5cd7872 OJ |
537 | static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit) |
538 | { | |
cd4ceb24 OJ |
539 | unsigned int n; |
540 | int count; | |
cd4ceb24 OJ |
541 | struct pasemi_mac_buffer *info; |
542 | struct sk_buff *skb; | |
b5254eee | 543 | unsigned int len; |
cd4ceb24 OJ |
544 | u64 macrx; |
545 | dma_addr_t dma; | |
b5254eee OJ |
546 | int buf_index; |
547 | u64 eval; | |
f5cd7872 OJ |
548 | |
549 | spin_lock(&mac->rx->lock); | |
550 | ||
cd4ceb24 | 551 | n = mac->rx->next_to_clean; |
f5cd7872 | 552 | |
b5254eee OJ |
553 | prefetch(RX_RING(mac, n)); |
554 | ||
555 | for (count = 0; count < limit; count++) { | |
fc9e4d2a | 556 | macrx = RX_RING(mac, n); |
f5cd7872 | 557 | |
69c29d89 OJ |
558 | if ((macrx & XCT_MACRX_E) || |
559 | (*mac->rx_status & PAS_STATUS_ERROR)) | |
560 | pasemi_mac_rx_error(mac, macrx); | |
561 | ||
cd4ceb24 | 562 | if (!(macrx & XCT_MACRX_O)) |
f5cd7872 OJ |
563 | break; |
564 | ||
f5cd7872 OJ |
565 | info = NULL; |
566 | ||
b5254eee | 567 | BUG_ON(!(macrx & XCT_MACRX_RR_8BRES)); |
f5cd7872 | 568 | |
b5254eee OJ |
569 | eval = (RX_RING(mac, n+1) & XCT_RXRES_8B_EVAL_M) >> |
570 | XCT_RXRES_8B_EVAL_S; | |
571 | buf_index = eval-1; | |
572 | ||
573 | dma = (RX_RING(mac, n+2) & XCT_PTR_ADDR_M); | |
574 | info = &RX_RING_INFO(mac, buf_index); | |
fc9e4d2a | 575 | |
9f05cfe2 | 576 | skb = info->skb; |
f5cd7872 | 577 | |
ad5da10a OJ |
578 | prefetch(skb); |
579 | prefetch(&skb->data_len); | |
f5cd7872 | 580 | |
cd4ceb24 | 581 | len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S; |
f5cd7872 | 582 | |
9f05cfe2 | 583 | if (len < 256) { |
8dc121a4 OJ |
584 | struct sk_buff *new_skb; |
585 | ||
586 | new_skb = netdev_alloc_skb(mac->netdev, | |
587 | len + LOCAL_SKB_ALIGN); | |
9f05cfe2 | 588 | if (new_skb) { |
8dc121a4 | 589 | skb_reserve(new_skb, LOCAL_SKB_ALIGN); |
73344863 | 590 | memcpy(new_skb->data, skb->data, len); |
9f05cfe2 OJ |
591 | /* save the skb in buffer_info as good */ |
592 | skb = new_skb; | |
593 | } | |
594 | /* else just continue with the old one */ | |
595 | } else | |
596 | info->skb = NULL; | |
f5cd7872 | 597 | |
ad5da10a OJ |
598 | pci_unmap_single(mac->dma_pdev, dma, len, PCI_DMA_FROMDEVICE); |
599 | ||
600 | info->dma = 0; | |
fc9e4d2a | 601 | |
f5cd7872 OJ |
602 | skb_put(skb, len); |
603 | ||
26fcfa95 | 604 | if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) { |
38bf3184 | 605 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
cd4ceb24 | 606 | skb->csum = (macrx & XCT_MACRX_CSUM_M) >> |
f5cd7872 OJ |
607 | XCT_MACRX_CSUM_S; |
608 | } else | |
609 | skb->ip_summed = CHECKSUM_NONE; | |
610 | ||
09f75cd7 JG |
611 | mac->netdev->stats.rx_bytes += len; |
612 | mac->netdev->stats.rx_packets++; | |
f5cd7872 | 613 | |
26fcfa95 | 614 | skb->protocol = eth_type_trans(skb, mac->netdev); |
f5cd7872 OJ |
615 | netif_receive_skb(skb); |
616 | ||
fc9e4d2a OJ |
617 | RX_RING(mac, n) = 0; |
618 | RX_RING(mac, n+1) = 0; | |
cd4ceb24 | 619 | |
ad5da10a OJ |
620 | /* Need to zero it out since hardware doesn't, since the |
621 | * replenish loop uses it to tell when it's done. | |
622 | */ | |
b5254eee | 623 | RX_BUFF(mac, buf_index) = 0; |
ad5da10a | 624 | |
b5254eee | 625 | n += 4; |
f5cd7872 OJ |
626 | } |
627 | ||
9a50bebd OJ |
628 | if (n > RX_RING_SIZE) { |
629 | /* Errata 5971 workaround: L2 target of headers */ | |
630 | write_iob_reg(mac, PAS_IOB_COM_PKTHDRCNT, 0); | |
631 | n &= (RX_RING_SIZE-1); | |
632 | } | |
b5254eee | 633 | |
fc9e4d2a | 634 | mac->rx->next_to_clean = n; |
b5254eee OJ |
635 | |
636 | /* Increase is in number of 16-byte entries, and since each descriptor | |
637 | * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with | |
638 | * count*2. | |
639 | */ | |
640 | write_dma_reg(mac, PAS_DMA_RXCHAN_INCR(mac->dma_rxch), count << 1); | |
641 | ||
642 | pasemi_mac_replenish_rx_ring(mac->netdev, count); | |
f5cd7872 OJ |
643 | |
644 | spin_unlock(&mac->rx->lock); | |
645 | ||
646 | return count; | |
647 | } | |
648 | ||
ad3c20d1 OJ |
649 | /* Can't make this too large or we blow the kernel stack limits */ |
650 | #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS) | |
651 | ||
f5cd7872 OJ |
652 | static int pasemi_mac_clean_tx(struct pasemi_mac *mac) |
653 | { | |
ad3c20d1 | 654 | int i, j; |
ad5da10a OJ |
655 | unsigned int start, descr_count, buf_count, batch_limit; |
656 | unsigned int ring_limit; | |
02df6cfa | 657 | unsigned int total_count; |
ca7e235f | 658 | unsigned long flags; |
ad3c20d1 OJ |
659 | struct sk_buff *skbs[TX_CLEAN_BATCHSIZE]; |
660 | dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1]; | |
f5cd7872 | 661 | |
02df6cfa | 662 | total_count = 0; |
ad5da10a | 663 | batch_limit = TX_CLEAN_BATCHSIZE; |
02df6cfa | 664 | restart: |
f5cd7872 OJ |
665 | spin_lock_irqsave(&mac->tx->lock, flags); |
666 | ||
667 | start = mac->tx->next_to_clean; | |
ad5da10a OJ |
668 | ring_limit = mac->tx->next_to_fill; |
669 | ||
670 | /* Compensate for when fill has wrapped but clean has not */ | |
671 | if (start > ring_limit) | |
672 | ring_limit += TX_RING_SIZE; | |
02df6cfa | 673 | |
ad3c20d1 OJ |
674 | buf_count = 0; |
675 | descr_count = 0; | |
f5cd7872 | 676 | |
ad3c20d1 | 677 | for (i = start; |
ad5da10a | 678 | descr_count < batch_limit && i < ring_limit; |
ad3c20d1 | 679 | i += buf_count) { |
fc9e4d2a | 680 | u64 mactx = TX_RING(mac, i); |
ad5da10a | 681 | struct sk_buff *skb; |
ad3c20d1 | 682 | |
fc9e4d2a | 683 | if ((mactx & XCT_MACTX_E) || |
69c29d89 | 684 | (*mac->tx_status & PAS_STATUS_ERROR)) |
fc9e4d2a | 685 | pasemi_mac_tx_error(mac, mactx); |
69c29d89 | 686 | |
fc9e4d2a | 687 | if (unlikely(mactx & XCT_MACTX_O)) |
02df6cfa | 688 | /* Not yet transmitted */ |
f5cd7872 OJ |
689 | break; |
690 | ||
ad5da10a OJ |
691 | skb = TX_RING_INFO(mac, i+1).skb; |
692 | skbs[descr_count] = skb; | |
ad3c20d1 | 693 | |
ad5da10a OJ |
694 | buf_count = 2 + skb_shinfo(skb)->nr_frags; |
695 | for (j = 0; j <= skb_shinfo(skb)->nr_frags; j++) | |
ad3c20d1 OJ |
696 | dmas[descr_count][j] = TX_RING_INFO(mac, i+1+j).dma; |
697 | ||
fc9e4d2a OJ |
698 | TX_RING(mac, i) = 0; |
699 | TX_RING(mac, i+1) = 0; | |
700 | ||
ad3c20d1 OJ |
701 | /* Since we always fill with an even number of entries, make |
702 | * sure we skip any unused one at the end as well. | |
703 | */ | |
704 | if (buf_count & 1) | |
705 | buf_count++; | |
706 | descr_count++; | |
f5cd7872 | 707 | } |
ad5da10a | 708 | mac->tx->next_to_clean = i & (TX_RING_SIZE-1); |
ad3c20d1 | 709 | |
f5cd7872 | 710 | spin_unlock_irqrestore(&mac->tx->lock, flags); |
0ce68c74 OJ |
711 | netif_wake_queue(mac->netdev); |
712 | ||
ad3c20d1 OJ |
713 | for (i = 0; i < descr_count; i++) |
714 | pasemi_mac_unmap_tx_skb(mac, skbs[i], dmas[i]); | |
02df6cfa | 715 | |
ad3c20d1 | 716 | total_count += descr_count; |
02df6cfa OJ |
717 | |
718 | /* If the batch was full, try to clean more */ | |
ad5da10a | 719 | if (descr_count == batch_limit) |
02df6cfa OJ |
720 | goto restart; |
721 | ||
722 | return total_count; | |
f5cd7872 OJ |
723 | } |
724 | ||
725 | ||
726 | static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) | |
727 | { | |
728 | struct net_device *dev = data; | |
729 | struct pasemi_mac *mac = netdev_priv(dev); | |
730 | unsigned int reg; | |
731 | ||
6dfa7522 | 732 | if (!(*mac->rx_status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
733 | return IRQ_NONE; |
734 | ||
6dfa7522 OJ |
735 | /* Don't reset packet count so it won't fire again but clear |
736 | * all others. | |
737 | */ | |
738 | ||
6dfa7522 OJ |
739 | reg = 0; |
740 | if (*mac->rx_status & PAS_STATUS_SOFT) | |
741 | reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; | |
742 | if (*mac->rx_status & PAS_STATUS_ERROR) | |
743 | reg |= PAS_IOB_DMA_RXCH_RESET_DINTC; | |
f5cd7872 OJ |
744 | if (*mac->rx_status & PAS_STATUS_TIMER) |
745 | reg |= PAS_IOB_DMA_RXCH_RESET_TINTC; | |
746 | ||
bea3348e | 747 | netif_rx_schedule(dev, &mac->napi); |
6dfa7522 | 748 | |
a85b9422 | 749 | write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg); |
f5cd7872 OJ |
750 | |
751 | return IRQ_HANDLED; | |
752 | } | |
753 | ||
754 | static irqreturn_t pasemi_mac_tx_intr(int irq, void *data) | |
755 | { | |
756 | struct net_device *dev = data; | |
757 | struct pasemi_mac *mac = netdev_priv(dev); | |
52a94351 | 758 | unsigned int reg, pcnt; |
f5cd7872 | 759 | |
6dfa7522 | 760 | if (!(*mac->tx_status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
761 | return IRQ_NONE; |
762 | ||
763 | pasemi_mac_clean_tx(mac); | |
764 | ||
52a94351 OJ |
765 | pcnt = *mac->tx_status & PAS_STATUS_PCNT_M; |
766 | ||
767 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; | |
6dfa7522 OJ |
768 | |
769 | if (*mac->tx_status & PAS_STATUS_SOFT) | |
770 | reg |= PAS_IOB_DMA_TXCH_RESET_SINTC; | |
771 | if (*mac->tx_status & PAS_STATUS_ERROR) | |
772 | reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; | |
f5cd7872 | 773 | |
a85b9422 | 774 | write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg); |
f5cd7872 | 775 | |
f5cd7872 OJ |
776 | return IRQ_HANDLED; |
777 | } | |
778 | ||
bb6e9590 OJ |
779 | static void pasemi_adjust_link(struct net_device *dev) |
780 | { | |
781 | struct pasemi_mac *mac = netdev_priv(dev); | |
782 | int msg; | |
783 | unsigned int flags; | |
784 | unsigned int new_flags; | |
785 | ||
786 | if (!mac->phydev->link) { | |
787 | /* If no link, MAC speed settings don't matter. Just report | |
788 | * link down and return. | |
789 | */ | |
790 | if (mac->link && netif_msg_link(mac)) | |
791 | printk(KERN_INFO "%s: Link is down.\n", dev->name); | |
792 | ||
793 | netif_carrier_off(dev); | |
794 | mac->link = 0; | |
795 | ||
796 | return; | |
797 | } else | |
798 | netif_carrier_on(dev); | |
799 | ||
a85b9422 | 800 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
bb6e9590 OJ |
801 | new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | |
802 | PAS_MAC_CFG_PCFG_TSR_M); | |
803 | ||
804 | if (!mac->phydev->duplex) | |
805 | new_flags |= PAS_MAC_CFG_PCFG_HD; | |
806 | ||
807 | switch (mac->phydev->speed) { | |
808 | case 1000: | |
809 | new_flags |= PAS_MAC_CFG_PCFG_SPD_1G | | |
810 | PAS_MAC_CFG_PCFG_TSR_1G; | |
811 | break; | |
812 | case 100: | |
813 | new_flags |= PAS_MAC_CFG_PCFG_SPD_100M | | |
814 | PAS_MAC_CFG_PCFG_TSR_100M; | |
815 | break; | |
816 | case 10: | |
817 | new_flags |= PAS_MAC_CFG_PCFG_SPD_10M | | |
818 | PAS_MAC_CFG_PCFG_TSR_10M; | |
819 | break; | |
820 | default: | |
821 | printk("Unsupported speed %d\n", mac->phydev->speed); | |
822 | } | |
823 | ||
824 | /* Print on link or speed/duplex change */ | |
825 | msg = mac->link != mac->phydev->link || flags != new_flags; | |
826 | ||
827 | mac->duplex = mac->phydev->duplex; | |
828 | mac->speed = mac->phydev->speed; | |
829 | mac->link = mac->phydev->link; | |
830 | ||
831 | if (new_flags != flags) | |
a85b9422 | 832 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags); |
bb6e9590 OJ |
833 | |
834 | if (msg && netif_msg_link(mac)) | |
835 | printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", | |
836 | dev->name, mac->speed, mac->duplex ? "full" : "half"); | |
837 | } | |
838 | ||
839 | static int pasemi_mac_phy_init(struct net_device *dev) | |
840 | { | |
841 | struct pasemi_mac *mac = netdev_priv(dev); | |
842 | struct device_node *dn, *phy_dn; | |
843 | struct phy_device *phydev; | |
844 | unsigned int phy_id; | |
845 | const phandle *ph; | |
846 | const unsigned int *prop; | |
847 | struct resource r; | |
848 | int ret; | |
849 | ||
850 | dn = pci_device_to_OF_node(mac->pdev); | |
9028780a | 851 | ph = of_get_property(dn, "phy-handle", NULL); |
bb6e9590 OJ |
852 | if (!ph) |
853 | return -ENODEV; | |
854 | phy_dn = of_find_node_by_phandle(*ph); | |
855 | ||
9028780a | 856 | prop = of_get_property(phy_dn, "reg", NULL); |
bb6e9590 OJ |
857 | ret = of_address_to_resource(phy_dn->parent, 0, &r); |
858 | if (ret) | |
859 | goto err; | |
860 | ||
861 | phy_id = *prop; | |
862 | snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id); | |
863 | ||
864 | of_node_put(phy_dn); | |
865 | ||
866 | mac->link = 0; | |
867 | mac->speed = 0; | |
868 | mac->duplex = -1; | |
869 | ||
870 | phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII); | |
871 | ||
872 | if (IS_ERR(phydev)) { | |
873 | printk(KERN_ERR "%s: Could not attach to phy\n", dev->name); | |
874 | return PTR_ERR(phydev); | |
875 | } | |
876 | ||
877 | mac->phydev = phydev; | |
878 | ||
879 | return 0; | |
880 | ||
881 | err: | |
882 | of_node_put(phy_dn); | |
883 | return -ENODEV; | |
884 | } | |
885 | ||
886 | ||
f5cd7872 OJ |
887 | static int pasemi_mac_open(struct net_device *dev) |
888 | { | |
889 | struct pasemi_mac *mac = netdev_priv(dev); | |
771f7404 | 890 | int base_irq; |
f5cd7872 OJ |
891 | unsigned int flags; |
892 | int ret; | |
893 | ||
894 | /* enable rx section */ | |
a85b9422 | 895 | write_dma_reg(mac, PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN); |
f5cd7872 OJ |
896 | |
897 | /* enable tx section */ | |
a85b9422 | 898 | write_dma_reg(mac, PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); |
f5cd7872 OJ |
899 | |
900 | flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | | |
901 | PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | | |
902 | PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); | |
903 | ||
a85b9422 | 904 | write_mac_reg(mac, PAS_MAC_CFG_TXP, flags); |
f5cd7872 | 905 | |
a85b9422 OJ |
906 | write_iob_reg(mac, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch), |
907 | PAS_IOB_DMA_RXCH_CFG_CNTTH(0)); | |
f5cd7872 | 908 | |
a85b9422 | 909 | write_iob_reg(mac, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch), |
02df6cfa | 910 | PAS_IOB_DMA_TXCH_CFG_CNTTH(128)); |
f5cd7872 | 911 | |
1b0335ea OJ |
912 | /* Clear out any residual packet count state from firmware */ |
913 | pasemi_mac_restart_rx_intr(mac); | |
914 | pasemi_mac_restart_tx_intr(mac); | |
915 | ||
6dfa7522 | 916 | /* 0xffffff is max value, about 16ms */ |
a85b9422 OJ |
917 | write_iob_reg(mac, PAS_IOB_DMA_COM_TIMEOUTCFG, |
918 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff)); | |
f5cd7872 | 919 | |
f5cd7872 OJ |
920 | ret = pasemi_mac_setup_rx_resources(dev); |
921 | if (ret) | |
922 | goto out_rx_resources; | |
923 | ||
924 | ret = pasemi_mac_setup_tx_resources(dev); | |
925 | if (ret) | |
926 | goto out_tx_resources; | |
927 | ||
a85b9422 OJ |
928 | write_mac_reg(mac, PAS_MAC_IPC_CHNL, |
929 | PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) | | |
930 | PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch)); | |
f5cd7872 OJ |
931 | |
932 | /* enable rx if */ | |
a85b9422 | 933 | write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), |
9e81d331 OJ |
934 | PAS_DMA_RXINT_RCMDSTA_EN | |
935 | PAS_DMA_RXINT_RCMDSTA_DROPS_M | | |
936 | PAS_DMA_RXINT_RCMDSTA_BP | | |
937 | PAS_DMA_RXINT_RCMDSTA_OO | | |
938 | PAS_DMA_RXINT_RCMDSTA_BT); | |
f5cd7872 OJ |
939 | |
940 | /* enable rx channel */ | |
a85b9422 OJ |
941 | write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), |
942 | PAS_DMA_RXCHAN_CCMDSTA_EN | | |
9e81d331 OJ |
943 | PAS_DMA_RXCHAN_CCMDSTA_DU | |
944 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
945 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
946 | PAS_DMA_RXCHAN_CCMDSTA_DT); | |
f5cd7872 OJ |
947 | |
948 | /* enable tx channel */ | |
a85b9422 | 949 | write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), |
9e81d331 OJ |
950 | PAS_DMA_TXCHAN_TCMDSTA_EN | |
951 | PAS_DMA_TXCHAN_TCMDSTA_SZ | | |
952 | PAS_DMA_TXCHAN_TCMDSTA_DB | | |
953 | PAS_DMA_TXCHAN_TCMDSTA_DE | | |
954 | PAS_DMA_TXCHAN_TCMDSTA_DA); | |
f5cd7872 | 955 | |
928773c2 | 956 | pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE); |
f5cd7872 | 957 | |
b5254eee OJ |
958 | write_dma_reg(mac, PAS_DMA_RXCHAN_INCR(mac->dma_rxch), RX_RING_SIZE>>1); |
959 | ||
36033766 OJ |
960 | flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE | |
961 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; | |
962 | ||
963 | if (mac->type == MAC_TYPE_GMAC) | |
964 | flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; | |
965 | else | |
966 | flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G; | |
967 | ||
968 | /* Enable interface in MAC */ | |
969 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
970 | ||
bb6e9590 OJ |
971 | ret = pasemi_mac_phy_init(dev); |
972 | /* Some configs don't have PHYs (XAUI etc), so don't complain about | |
973 | * failed init due to -ENODEV. | |
974 | */ | |
975 | if (ret && ret != -ENODEV) | |
976 | dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret); | |
977 | ||
f5cd7872 | 978 | netif_start_queue(dev); |
bea3348e | 979 | napi_enable(&mac->napi); |
f5cd7872 | 980 | |
771f7404 OJ |
981 | /* Interrupts are a bit different for our DMA controller: While |
982 | * it's got one a regular PCI device header, the interrupt there | |
983 | * is really the base of the range it's using. Each tx and rx | |
984 | * channel has it's own interrupt source. | |
985 | */ | |
986 | ||
987 | base_irq = virq_to_hw(mac->dma_pdev->irq); | |
988 | ||
989 | mac->tx_irq = irq_create_mapping(NULL, base_irq + mac->dma_txch); | |
990 | mac->rx_irq = irq_create_mapping(NULL, base_irq + 20 + mac->dma_txch); | |
991 | ||
992 | ret = request_irq(mac->tx_irq, &pasemi_mac_tx_intr, IRQF_DISABLED, | |
f5cd7872 OJ |
993 | mac->tx->irq_name, dev); |
994 | if (ret) { | |
995 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
771f7404 | 996 | base_irq + mac->dma_txch, ret); |
f5cd7872 OJ |
997 | goto out_tx_int; |
998 | } | |
999 | ||
771f7404 | 1000 | ret = request_irq(mac->rx_irq, &pasemi_mac_rx_intr, IRQF_DISABLED, |
f5cd7872 OJ |
1001 | mac->rx->irq_name, dev); |
1002 | if (ret) { | |
1003 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
771f7404 | 1004 | base_irq + 20 + mac->dma_rxch, ret); |
f5cd7872 OJ |
1005 | goto out_rx_int; |
1006 | } | |
1007 | ||
bb6e9590 OJ |
1008 | if (mac->phydev) |
1009 | phy_start(mac->phydev); | |
1010 | ||
f5cd7872 OJ |
1011 | return 0; |
1012 | ||
1013 | out_rx_int: | |
771f7404 | 1014 | free_irq(mac->tx_irq, dev); |
f5cd7872 | 1015 | out_tx_int: |
bea3348e | 1016 | napi_disable(&mac->napi); |
f5cd7872 OJ |
1017 | netif_stop_queue(dev); |
1018 | pasemi_mac_free_tx_resources(dev); | |
1019 | out_tx_resources: | |
1020 | pasemi_mac_free_rx_resources(dev); | |
1021 | out_rx_resources: | |
1022 | ||
1023 | return ret; | |
1024 | } | |
1025 | ||
1026 | #define MAX_RETRIES 5000 | |
1027 | ||
1028 | static int pasemi_mac_close(struct net_device *dev) | |
1029 | { | |
1030 | struct pasemi_mac *mac = netdev_priv(dev); | |
9e81d331 | 1031 | unsigned int sta; |
f5cd7872 OJ |
1032 | int retries; |
1033 | ||
bb6e9590 OJ |
1034 | if (mac->phydev) { |
1035 | phy_stop(mac->phydev); | |
1036 | phy_disconnect(mac->phydev); | |
1037 | } | |
1038 | ||
f5cd7872 | 1039 | netif_stop_queue(dev); |
bea3348e | 1040 | napi_disable(&mac->napi); |
f5cd7872 | 1041 | |
9e81d331 OJ |
1042 | sta = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
1043 | if (sta & (PAS_DMA_RXINT_RCMDSTA_BP | | |
1044 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1045 | PAS_DMA_RXINT_RCMDSTA_BT)) | |
1046 | printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta); | |
1047 | ||
1048 | sta = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch)); | |
1049 | if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU | | |
1050 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1051 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1052 | PAS_DMA_RXCHAN_CCMDSTA_DT)) | |
1053 | printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta); | |
1054 | ||
1055 | sta = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch)); | |
1056 | if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | | |
1057 | PAS_DMA_TXCHAN_TCMDSTA_DB | | |
1058 | PAS_DMA_TXCHAN_TCMDSTA_DE | | |
1059 | PAS_DMA_TXCHAN_TCMDSTA_DA)) | |
1060 | printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta); | |
1061 | ||
f5cd7872 OJ |
1062 | /* Clean out any pending buffers */ |
1063 | pasemi_mac_clean_tx(mac); | |
1064 | pasemi_mac_clean_rx(mac, RX_RING_SIZE); | |
1065 | ||
1066 | /* Disable interface */ | |
a85b9422 OJ |
1067 | write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), PAS_DMA_TXCHAN_TCMDSTA_ST); |
1068 | write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), PAS_DMA_RXINT_RCMDSTA_ST); | |
1069 | write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), PAS_DMA_RXCHAN_CCMDSTA_ST); | |
f5cd7872 OJ |
1070 | |
1071 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
9e81d331 OJ |
1072 | sta = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch)); |
1073 | if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) | |
f5cd7872 OJ |
1074 | break; |
1075 | cond_resched(); | |
1076 | } | |
1077 | ||
9e81d331 | 1078 | if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT) |
f5cd7872 | 1079 | dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n"); |
f5cd7872 OJ |
1080 | |
1081 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
9e81d331 OJ |
1082 | sta = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch)); |
1083 | if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) | |
f5cd7872 OJ |
1084 | break; |
1085 | cond_resched(); | |
1086 | } | |
1087 | ||
9e81d331 | 1088 | if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT) |
f5cd7872 | 1089 | dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n"); |
f5cd7872 OJ |
1090 | |
1091 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
9e81d331 OJ |
1092 | sta = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
1093 | if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT)) | |
f5cd7872 OJ |
1094 | break; |
1095 | cond_resched(); | |
1096 | } | |
1097 | ||
9e81d331 | 1098 | if (sta & PAS_DMA_RXINT_RCMDSTA_ACT) |
f5cd7872 | 1099 | dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n"); |
f5cd7872 OJ |
1100 | |
1101 | /* Then, disable the channel. This must be done separately from | |
1102 | * stopping, since you can't disable when active. | |
1103 | */ | |
1104 | ||
a85b9422 OJ |
1105 | write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0); |
1106 | write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0); | |
1107 | write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); | |
f5cd7872 | 1108 | |
771f7404 OJ |
1109 | free_irq(mac->tx_irq, dev); |
1110 | free_irq(mac->rx_irq, dev); | |
f5cd7872 OJ |
1111 | |
1112 | /* Free resources */ | |
1113 | pasemi_mac_free_rx_resources(dev); | |
1114 | pasemi_mac_free_tx_resources(dev); | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) | |
1120 | { | |
1121 | struct pasemi_mac *mac = netdev_priv(dev); | |
1122 | struct pasemi_mac_txring *txring; | |
ad3c20d1 OJ |
1123 | u64 dflags, mactx; |
1124 | dma_addr_t map[MAX_SKB_FRAGS+1]; | |
1125 | unsigned int map_size[MAX_SKB_FRAGS+1]; | |
ca7e235f | 1126 | unsigned long flags; |
ad3c20d1 | 1127 | int i, nfrags; |
f5cd7872 OJ |
1128 | |
1129 | dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_SS | XCT_MACTX_CRC_PAD; | |
1130 | ||
1131 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
d56f90a7 ACM |
1132 | const unsigned char *nh = skb_network_header(skb); |
1133 | ||
eddc9ec5 | 1134 | switch (ip_hdr(skb)->protocol) { |
f5cd7872 OJ |
1135 | case IPPROTO_TCP: |
1136 | dflags |= XCT_MACTX_CSUM_TCP; | |
cfe1fc77 | 1137 | dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2); |
d56f90a7 | 1138 | dflags |= XCT_MACTX_IPO(nh - skb->data); |
f5cd7872 OJ |
1139 | break; |
1140 | case IPPROTO_UDP: | |
1141 | dflags |= XCT_MACTX_CSUM_UDP; | |
cfe1fc77 | 1142 | dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2); |
d56f90a7 | 1143 | dflags |= XCT_MACTX_IPO(nh - skb->data); |
f5cd7872 OJ |
1144 | break; |
1145 | } | |
1146 | } | |
1147 | ||
ad3c20d1 OJ |
1148 | nfrags = skb_shinfo(skb)->nr_frags; |
1149 | ||
1150 | map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb), | |
1151 | PCI_DMA_TODEVICE); | |
1152 | map_size[0] = skb_headlen(skb); | |
1153 | if (dma_mapping_error(map[0])) | |
1154 | goto out_err_nolock; | |
1155 | ||
1156 | for (i = 0; i < nfrags; i++) { | |
1157 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
f5cd7872 | 1158 | |
ad3c20d1 OJ |
1159 | map[i+1] = pci_map_page(mac->dma_pdev, frag->page, |
1160 | frag->page_offset, frag->size, | |
1161 | PCI_DMA_TODEVICE); | |
1162 | map_size[i+1] = frag->size; | |
1163 | if (dma_mapping_error(map[i+1])) { | |
1164 | nfrags = i; | |
1165 | goto out_err_nolock; | |
1166 | } | |
1167 | } | |
f5cd7872 | 1168 | |
26fcfa95 | 1169 | mactx = dflags | XCT_MACTX_LLEN(skb->len); |
26fcfa95 | 1170 | |
f5cd7872 OJ |
1171 | txring = mac->tx; |
1172 | ||
1173 | spin_lock_irqsave(&txring->lock, flags); | |
1174 | ||
ad5da10a OJ |
1175 | /* Avoid stepping on the same cache line that the DMA controller |
1176 | * is currently about to send, so leave at least 8 words available. | |
1177 | * Total free space needed is mactx + fragments + 8 | |
1178 | */ | |
1179 | if (RING_AVAIL(txring) < nfrags + 10) { | |
1180 | /* no room -- stop the queue and wait for tx intr */ | |
1181 | netif_stop_queue(dev); | |
1182 | goto out_err; | |
f5cd7872 OJ |
1183 | } |
1184 | ||
fc9e4d2a | 1185 | TX_RING(mac, txring->next_to_fill) = mactx; |
ad3c20d1 OJ |
1186 | txring->next_to_fill++; |
1187 | TX_RING_INFO(mac, txring->next_to_fill).skb = skb; | |
1188 | for (i = 0; i <= nfrags; i++) { | |
1189 | TX_RING(mac, txring->next_to_fill+i) = | |
1190 | XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); | |
1191 | TX_RING_INFO(mac, txring->next_to_fill+i).dma = map[i]; | |
1192 | } | |
1193 | ||
1194 | /* We have to add an even number of 8-byte entries to the ring | |
1195 | * even if the last one is unused. That means always an odd number | |
1196 | * of pointers + one mactx descriptor. | |
1197 | */ | |
1198 | if (nfrags & 1) | |
1199 | nfrags++; | |
fc9e4d2a | 1200 | |
ad5da10a OJ |
1201 | txring->next_to_fill = (txring->next_to_fill + nfrags + 1) & |
1202 | (TX_RING_SIZE-1); | |
f5cd7872 | 1203 | |
09f75cd7 JG |
1204 | dev->stats.tx_packets++; |
1205 | dev->stats.tx_bytes += skb->len; | |
f5cd7872 OJ |
1206 | |
1207 | spin_unlock_irqrestore(&txring->lock, flags); | |
1208 | ||
ad3c20d1 | 1209 | write_dma_reg(mac, PAS_DMA_TXCHAN_INCR(mac->dma_txch), (nfrags+2) >> 1); |
f5cd7872 OJ |
1210 | |
1211 | return NETDEV_TX_OK; | |
1212 | ||
1213 | out_err: | |
1214 | spin_unlock_irqrestore(&txring->lock, flags); | |
ad3c20d1 OJ |
1215 | out_err_nolock: |
1216 | while (nfrags--) | |
1217 | pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags], | |
1218 | PCI_DMA_TODEVICE); | |
1219 | ||
f5cd7872 OJ |
1220 | return NETDEV_TX_BUSY; |
1221 | } | |
1222 | ||
f5cd7872 OJ |
1223 | static void pasemi_mac_set_rx_mode(struct net_device *dev) |
1224 | { | |
1225 | struct pasemi_mac *mac = netdev_priv(dev); | |
1226 | unsigned int flags; | |
1227 | ||
a85b9422 | 1228 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
f5cd7872 OJ |
1229 | |
1230 | /* Set promiscuous */ | |
1231 | if (dev->flags & IFF_PROMISC) | |
1232 | flags |= PAS_MAC_CFG_PCFG_PR; | |
1233 | else | |
1234 | flags &= ~PAS_MAC_CFG_PCFG_PR; | |
1235 | ||
a85b9422 | 1236 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); |
f5cd7872 OJ |
1237 | } |
1238 | ||
1239 | ||
bea3348e | 1240 | static int pasemi_mac_poll(struct napi_struct *napi, int budget) |
f5cd7872 | 1241 | { |
bea3348e SH |
1242 | struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi); |
1243 | struct net_device *dev = mac->netdev; | |
1244 | int pkts; | |
f5cd7872 | 1245 | |
829185e9 | 1246 | pasemi_mac_clean_tx(mac); |
bea3348e SH |
1247 | pkts = pasemi_mac_clean_rx(mac, budget); |
1248 | if (pkts < budget) { | |
f5cd7872 | 1249 | /* all done, no more packets present */ |
bea3348e | 1250 | netif_rx_complete(dev, napi); |
f5cd7872 | 1251 | |
1b0335ea | 1252 | pasemi_mac_restart_rx_intr(mac); |
f5cd7872 | 1253 | } |
bea3348e | 1254 | return pkts; |
f5cd7872 OJ |
1255 | } |
1256 | ||
b6e05a1b OJ |
1257 | static void __iomem * __devinit map_onedev(struct pci_dev *p, int index) |
1258 | { | |
1259 | struct device_node *dn; | |
1260 | void __iomem *ret; | |
1261 | ||
1262 | dn = pci_device_to_OF_node(p); | |
1263 | if (!dn) | |
1264 | goto fallback; | |
1265 | ||
1266 | ret = of_iomap(dn, index); | |
1267 | if (!ret) | |
1268 | goto fallback; | |
1269 | ||
1270 | return ret; | |
1271 | fallback: | |
1272 | /* This is hardcoded and ugly, but we have some firmware versions | |
1273 | * that don't provide the register space in the device tree. Luckily | |
1274 | * they are at well-known locations so we can just do the math here. | |
1275 | */ | |
1276 | return ioremap(0xe0000000 + (p->devfn << 12), 0x2000); | |
1277 | } | |
1278 | ||
1279 | static int __devinit pasemi_mac_map_regs(struct pasemi_mac *mac) | |
1280 | { | |
1281 | struct resource res; | |
1282 | struct device_node *dn; | |
1283 | int err; | |
1284 | ||
1285 | mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); | |
1286 | if (!mac->dma_pdev) { | |
1287 | dev_err(&mac->pdev->dev, "Can't find DMA Controller\n"); | |
1288 | return -ENODEV; | |
1289 | } | |
1290 | ||
1291 | mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); | |
1292 | if (!mac->iob_pdev) { | |
1293 | dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n"); | |
1294 | return -ENODEV; | |
1295 | } | |
1296 | ||
1297 | mac->regs = map_onedev(mac->pdev, 0); | |
1298 | mac->dma_regs = map_onedev(mac->dma_pdev, 0); | |
1299 | mac->iob_regs = map_onedev(mac->iob_pdev, 0); | |
1300 | ||
1301 | if (!mac->regs || !mac->dma_regs || !mac->iob_regs) { | |
1302 | dev_err(&mac->pdev->dev, "Can't map registers\n"); | |
1303 | return -ENODEV; | |
1304 | } | |
1305 | ||
1306 | /* The dma status structure is located in the I/O bridge, and | |
1307 | * is cache coherent. | |
1308 | */ | |
1309 | if (!dma_status) { | |
1310 | dn = pci_device_to_OF_node(mac->iob_pdev); | |
1311 | if (dn) | |
1312 | err = of_address_to_resource(dn, 1, &res); | |
1313 | if (!dn || err) { | |
1314 | /* Fallback for old firmware */ | |
1315 | res.start = 0xfd800000; | |
1316 | res.end = res.start + 0x1000; | |
1317 | } | |
1318 | dma_status = __ioremap(res.start, res.end-res.start, 0); | |
1319 | } | |
1320 | ||
1321 | return 0; | |
1322 | } | |
1323 | ||
f5cd7872 OJ |
1324 | static int __devinit |
1325 | pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1326 | { | |
1327 | static int index = 0; | |
1328 | struct net_device *dev; | |
1329 | struct pasemi_mac *mac; | |
1330 | int err; | |
0795af57 | 1331 | DECLARE_MAC_BUF(mac_buf); |
f5cd7872 OJ |
1332 | |
1333 | err = pci_enable_device(pdev); | |
1334 | if (err) | |
1335 | return err; | |
1336 | ||
1337 | dev = alloc_etherdev(sizeof(struct pasemi_mac)); | |
1338 | if (dev == NULL) { | |
1339 | dev_err(&pdev->dev, | |
1340 | "pasemi_mac: Could not allocate ethernet device.\n"); | |
1341 | err = -ENOMEM; | |
1342 | goto out_disable_device; | |
1343 | } | |
1344 | ||
f5cd7872 OJ |
1345 | pci_set_drvdata(pdev, dev); |
1346 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1347 | ||
1348 | mac = netdev_priv(dev); | |
1349 | ||
1350 | mac->pdev = pdev; | |
1351 | mac->netdev = dev; | |
f5cd7872 | 1352 | |
bea3348e SH |
1353 | netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64); |
1354 | ||
ad3c20d1 | 1355 | dev->features = NETIF_F_HW_CSUM | NETIF_F_LLTX | NETIF_F_SG; |
bea3348e | 1356 | |
f5cd7872 OJ |
1357 | /* These should come out of the device tree eventually */ |
1358 | mac->dma_txch = index; | |
1359 | mac->dma_rxch = index; | |
1360 | ||
1361 | /* We probe GMAC before XAUI, but the DMA interfaces are | |
1362 | * in XAUI, GMAC order. | |
1363 | */ | |
1364 | if (index < 4) | |
1365 | mac->dma_if = index + 2; | |
1366 | else | |
1367 | mac->dma_if = index - 4; | |
1368 | index++; | |
1369 | ||
1370 | switch (pdev->device) { | |
1371 | case 0xa005: | |
1372 | mac->type = MAC_TYPE_GMAC; | |
1373 | break; | |
1374 | case 0xa006: | |
1375 | mac->type = MAC_TYPE_XAUI; | |
1376 | break; | |
1377 | default: | |
1378 | err = -ENODEV; | |
1379 | goto out; | |
1380 | } | |
1381 | ||
1382 | /* get mac addr from device tree */ | |
1383 | if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) { | |
1384 | err = -ENODEV; | |
1385 | goto out; | |
1386 | } | |
1387 | memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr)); | |
1388 | ||
1389 | dev->open = pasemi_mac_open; | |
1390 | dev->stop = pasemi_mac_close; | |
1391 | dev->hard_start_xmit = pasemi_mac_start_tx; | |
f5cd7872 | 1392 | dev->set_multicast_list = pasemi_mac_set_rx_mode; |
f5cd7872 | 1393 | |
b6e05a1b OJ |
1394 | err = pasemi_mac_map_regs(mac); |
1395 | if (err) | |
1396 | goto out; | |
f5cd7872 OJ |
1397 | |
1398 | mac->rx_status = &dma_status->rx_sta[mac->dma_rxch]; | |
1399 | mac->tx_status = &dma_status->tx_sta[mac->dma_txch]; | |
1400 | ||
ceb51361 OJ |
1401 | mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
1402 | ||
bb6e9590 OJ |
1403 | /* Enable most messages by default */ |
1404 | mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1405 | ||
f5cd7872 OJ |
1406 | err = register_netdev(dev); |
1407 | ||
1408 | if (err) { | |
1409 | dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n", | |
1410 | err); | |
1411 | goto out; | |
69c29d89 | 1412 | } else if netif_msg_probe(mac) |
f5cd7872 | 1413 | printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, " |
0795af57 | 1414 | "hw addr %s\n", |
f5cd7872 OJ |
1415 | dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI", |
1416 | mac->dma_if, mac->dma_txch, mac->dma_rxch, | |
0795af57 | 1417 | print_mac(mac_buf, dev->dev_addr)); |
f5cd7872 OJ |
1418 | |
1419 | return err; | |
1420 | ||
1421 | out: | |
b6e05a1b OJ |
1422 | if (mac->iob_pdev) |
1423 | pci_dev_put(mac->iob_pdev); | |
1424 | if (mac->dma_pdev) | |
1425 | pci_dev_put(mac->dma_pdev); | |
1426 | if (mac->dma_regs) | |
1427 | iounmap(mac->dma_regs); | |
1428 | if (mac->iob_regs) | |
1429 | iounmap(mac->iob_regs); | |
1430 | if (mac->regs) | |
1431 | iounmap(mac->regs); | |
1432 | ||
f5cd7872 OJ |
1433 | free_netdev(dev); |
1434 | out_disable_device: | |
1435 | pci_disable_device(pdev); | |
1436 | return err; | |
1437 | ||
1438 | } | |
1439 | ||
1440 | static void __devexit pasemi_mac_remove(struct pci_dev *pdev) | |
1441 | { | |
1442 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1443 | struct pasemi_mac *mac; | |
1444 | ||
1445 | if (!netdev) | |
1446 | return; | |
1447 | ||
1448 | mac = netdev_priv(netdev); | |
1449 | ||
1450 | unregister_netdev(netdev); | |
1451 | ||
1452 | pci_disable_device(pdev); | |
1453 | pci_dev_put(mac->dma_pdev); | |
1454 | pci_dev_put(mac->iob_pdev); | |
1455 | ||
b6e05a1b OJ |
1456 | iounmap(mac->regs); |
1457 | iounmap(mac->dma_regs); | |
1458 | iounmap(mac->iob_regs); | |
1459 | ||
f5cd7872 OJ |
1460 | pci_set_drvdata(pdev, NULL); |
1461 | free_netdev(netdev); | |
1462 | } | |
1463 | ||
1464 | static struct pci_device_id pasemi_mac_pci_tbl[] = { | |
1465 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) }, | |
1466 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) }, | |
fd178254 | 1467 | { }, |
f5cd7872 OJ |
1468 | }; |
1469 | ||
1470 | MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl); | |
1471 | ||
1472 | static struct pci_driver pasemi_mac_driver = { | |
1473 | .name = "pasemi_mac", | |
1474 | .id_table = pasemi_mac_pci_tbl, | |
1475 | .probe = pasemi_mac_probe, | |
1476 | .remove = __devexit_p(pasemi_mac_remove), | |
1477 | }; | |
1478 | ||
1479 | static void __exit pasemi_mac_cleanup_module(void) | |
1480 | { | |
1481 | pci_unregister_driver(&pasemi_mac_driver); | |
1482 | __iounmap(dma_status); | |
1483 | dma_status = NULL; | |
1484 | } | |
1485 | ||
1486 | int pasemi_mac_init_module(void) | |
1487 | { | |
1488 | return pci_register_driver(&pasemi_mac_driver); | |
1489 | } | |
1490 | ||
f5cd7872 OJ |
1491 | module_init(pasemi_mac_init_module); |
1492 | module_exit(pasemi_mac_cleanup_module); |