Commit | Line | Data |
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f5cd7872 OJ |
1 | /* |
2 | * Copyright (C) 2006-2007 PA Semi, Inc | |
3 | * | |
4 | * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/dmaengine.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/netdevice.h> | |
27 | #include <linux/etherdevice.h> | |
28 | #include <asm/dma-mapping.h> | |
29 | #include <linux/in.h> | |
30 | #include <linux/skbuff.h> | |
31 | ||
32 | #include <linux/ip.h> | |
33 | #include <linux/tcp.h> | |
34 | #include <net/checksum.h> | |
28ae79f5 | 35 | #include <linux/inet_lro.h> |
f5cd7872 | 36 | |
771f7404 | 37 | #include <asm/irq.h> |
af289e80 | 38 | #include <asm/firmware.h> |
40afa531 | 39 | #include <asm/pasemi_dma.h> |
771f7404 | 40 | |
f5cd7872 OJ |
41 | #include "pasemi_mac.h" |
42 | ||
8dc121a4 OJ |
43 | /* We have our own align, since ppc64 in general has it at 0 because |
44 | * of design flaws in some of the server bridge chips. However, for | |
45 | * PWRficient doing the unaligned copies is more expensive than doing | |
46 | * unaligned DMA, so make sure the data is aligned instead. | |
47 | */ | |
48 | #define LOCAL_SKB_ALIGN 2 | |
f5cd7872 OJ |
49 | |
50 | /* TODO list | |
51 | * | |
f5cd7872 OJ |
52 | * - Multicast support |
53 | * - Large MTU support | |
7ddeae2c OJ |
54 | * - SW LRO |
55 | * - Multiqueue RX/TX | |
f5cd7872 OJ |
56 | */ |
57 | ||
28ae79f5 OJ |
58 | #define LRO_MAX_AGGR 64 |
59 | ||
ef1ea0b4 | 60 | #define PE_MIN_MTU 64 |
8d636d8b | 61 | #define PE_MAX_MTU 9000 |
ef1ea0b4 OJ |
62 | #define PE_DEF_MTU ETH_DATA_LEN |
63 | ||
ceb51361 OJ |
64 | #define DEFAULT_MSG_ENABLE \ |
65 | (NETIF_MSG_DRV | \ | |
66 | NETIF_MSG_PROBE | \ | |
67 | NETIF_MSG_LINK | \ | |
68 | NETIF_MSG_TIMER | \ | |
69 | NETIF_MSG_IFDOWN | \ | |
70 | NETIF_MSG_IFUP | \ | |
71 | NETIF_MSG_RX_ERR | \ | |
72 | NETIF_MSG_TX_ERR) | |
73 | ||
ceb51361 OJ |
74 | MODULE_LICENSE("GPL"); |
75 | MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>"); | |
76 | MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver"); | |
77 | ||
78 | static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */ | |
79 | module_param(debug, int, 0); | |
80 | MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value"); | |
f5cd7872 | 81 | |
e37c772e OJ |
82 | extern const struct ethtool_ops pasemi_mac_ethtool_ops; |
83 | ||
af289e80 OJ |
84 | static int translation_enabled(void) |
85 | { | |
86 | #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE) | |
87 | return 1; | |
88 | #else | |
89 | return firmware_has_feature(FW_FEATURE_LPAR); | |
90 | #endif | |
91 | } | |
92 | ||
34c20624 | 93 | static void write_iob_reg(unsigned int reg, unsigned int val) |
a85b9422 | 94 | { |
34c20624 | 95 | pasemi_write_iob_reg(reg, val); |
a85b9422 OJ |
96 | } |
97 | ||
5c15332b | 98 | static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg) |
a85b9422 | 99 | { |
34c20624 | 100 | return pasemi_read_mac_reg(mac->dma_if, reg); |
a85b9422 OJ |
101 | } |
102 | ||
5c15332b | 103 | static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg, |
a85b9422 OJ |
104 | unsigned int val) |
105 | { | |
34c20624 | 106 | pasemi_write_mac_reg(mac->dma_if, reg, val); |
a85b9422 OJ |
107 | } |
108 | ||
34c20624 | 109 | static unsigned int read_dma_reg(unsigned int reg) |
a85b9422 | 110 | { |
34c20624 | 111 | return pasemi_read_dma_reg(reg); |
a85b9422 OJ |
112 | } |
113 | ||
34c20624 | 114 | static void write_dma_reg(unsigned int reg, unsigned int val) |
a85b9422 | 115 | { |
34c20624 | 116 | pasemi_write_dma_reg(reg, val); |
a85b9422 OJ |
117 | } |
118 | ||
5c15332b | 119 | static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
120 | { |
121 | return mac->rx; | |
122 | } | |
123 | ||
5c15332b | 124 | static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
125 | { |
126 | return mac->tx; | |
127 | } | |
128 | ||
5c15332b OJ |
129 | static inline void prefetch_skb(const struct sk_buff *skb) |
130 | { | |
131 | const void *d = skb; | |
132 | ||
133 | prefetch(d); | |
134 | prefetch(d+64); | |
135 | prefetch(d+128); | |
136 | prefetch(d+192); | |
137 | } | |
138 | ||
34c20624 OJ |
139 | static int mac_to_intf(struct pasemi_mac *mac) |
140 | { | |
141 | struct pci_dev *pdev = mac->pdev; | |
142 | u32 tmp; | |
143 | int nintf, off, i, j; | |
144 | int devfn = pdev->devfn; | |
145 | ||
146 | tmp = read_dma_reg(PAS_DMA_CAP_IFI); | |
147 | nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S; | |
148 | off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S; | |
149 | ||
150 | /* IOFF contains the offset to the registers containing the | |
151 | * DMA interface-to-MAC-pci-id mappings, and NIN contains number | |
152 | * of total interfaces. Each register contains 4 devfns. | |
153 | * Just do a linear search until we find the devfn of the MAC | |
154 | * we're trying to look up. | |
155 | */ | |
156 | ||
157 | for (i = 0; i < (nintf+3)/4; i++) { | |
158 | tmp = read_dma_reg(off+4*i); | |
159 | for (j = 0; j < 4; j++) { | |
160 | if (((tmp >> (8*j)) & 0xff) == devfn) | |
161 | return i*4 + j; | |
162 | } | |
163 | } | |
164 | return -1; | |
165 | } | |
166 | ||
ef1ea0b4 OJ |
167 | static void pasemi_mac_intf_disable(struct pasemi_mac *mac) |
168 | { | |
169 | unsigned int flags; | |
170 | ||
171 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); | |
172 | flags &= ~PAS_MAC_CFG_PCFG_PE; | |
173 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
174 | } | |
175 | ||
176 | static void pasemi_mac_intf_enable(struct pasemi_mac *mac) | |
177 | { | |
178 | unsigned int flags; | |
179 | ||
180 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); | |
181 | flags |= PAS_MAC_CFG_PCFG_PE; | |
182 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
183 | } | |
184 | ||
f5cd7872 OJ |
185 | static int pasemi_get_mac_addr(struct pasemi_mac *mac) |
186 | { | |
187 | struct pci_dev *pdev = mac->pdev; | |
188 | struct device_node *dn = pci_device_to_OF_node(pdev); | |
1af7f056 | 189 | int len; |
f5cd7872 OJ |
190 | const u8 *maddr; |
191 | u8 addr[6]; | |
192 | ||
193 | if (!dn) { | |
194 | dev_dbg(&pdev->dev, | |
195 | "No device node for mac, not configuring\n"); | |
196 | return -ENOENT; | |
197 | } | |
198 | ||
1af7f056 | 199 | maddr = of_get_property(dn, "local-mac-address", &len); |
200 | ||
201 | if (maddr && len == 6) { | |
202 | memcpy(mac->mac_addr, maddr, 6); | |
203 | return 0; | |
204 | } | |
205 | ||
206 | /* Some old versions of firmware mistakenly uses mac-address | |
207 | * (and as a string) instead of a byte array in local-mac-address. | |
208 | */ | |
a5fd22eb | 209 | |
a5fd22eb | 210 | if (maddr == NULL) |
9028780a | 211 | maddr = of_get_property(dn, "mac-address", NULL); |
a5fd22eb | 212 | |
f5cd7872 OJ |
213 | if (maddr == NULL) { |
214 | dev_warn(&pdev->dev, | |
215 | "no mac address in device tree, not configuring\n"); | |
216 | return -ENOENT; | |
217 | } | |
218 | ||
219 | if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0], | |
220 | &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) { | |
221 | dev_warn(&pdev->dev, | |
222 | "can't parse mac address, not configuring\n"); | |
223 | return -EINVAL; | |
224 | } | |
225 | ||
1af7f056 | 226 | memcpy(mac->mac_addr, addr, 6); |
227 | ||
f5cd7872 OJ |
228 | return 0; |
229 | } | |
230 | ||
5cea73b0 OJ |
231 | static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p) |
232 | { | |
233 | struct pasemi_mac *mac = netdev_priv(dev); | |
234 | struct sockaddr *addr = p; | |
235 | unsigned int adr0, adr1; | |
236 | ||
237 | if (!is_valid_ether_addr(addr->sa_data)) | |
238 | return -EINVAL; | |
239 | ||
240 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
241 | ||
242 | adr0 = dev->dev_addr[2] << 24 | | |
243 | dev->dev_addr[3] << 16 | | |
244 | dev->dev_addr[4] << 8 | | |
245 | dev->dev_addr[5]; | |
246 | adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1); | |
247 | adr1 &= ~0xffff; | |
248 | adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1]; | |
249 | ||
250 | pasemi_mac_intf_disable(mac); | |
251 | write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0); | |
252 | write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1); | |
253 | pasemi_mac_intf_enable(mac); | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
28ae79f5 OJ |
258 | static int get_skb_hdr(struct sk_buff *skb, void **iphdr, |
259 | void **tcph, u64 *hdr_flags, void *data) | |
260 | { | |
261 | u64 macrx = (u64) data; | |
262 | unsigned int ip_len; | |
263 | struct iphdr *iph; | |
264 | ||
265 | /* IPv4 header checksum failed */ | |
266 | if ((macrx & XCT_MACRX_HTY_M) != XCT_MACRX_HTY_IPV4_OK) | |
267 | return -1; | |
268 | ||
269 | /* non tcp packet */ | |
270 | skb_reset_network_header(skb); | |
271 | iph = ip_hdr(skb); | |
272 | if (iph->protocol != IPPROTO_TCP) | |
273 | return -1; | |
274 | ||
275 | ip_len = ip_hdrlen(skb); | |
276 | skb_set_transport_header(skb, ip_len); | |
277 | *tcph = tcp_hdr(skb); | |
278 | ||
279 | /* check if ip header and tcp header are complete */ | |
77321233 | 280 | if (ntohs(iph->tot_len) < ip_len + tcp_hdrlen(skb)) |
28ae79f5 OJ |
281 | return -1; |
282 | ||
283 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
284 | *iphdr = iph; | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
ad3c20d1 | 289 | static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac, |
7e9916e9 | 290 | const int nfrags, |
ad3c20d1 | 291 | struct sk_buff *skb, |
5c15332b | 292 | const dma_addr_t *dmas) |
ad3c20d1 OJ |
293 | { |
294 | int f; | |
5c15332b | 295 | struct pci_dev *pdev = mac->dma_pdev; |
ad3c20d1 | 296 | |
5c15332b | 297 | pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
298 | |
299 | for (f = 0; f < nfrags; f++) { | |
300 | skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; | |
301 | ||
5c15332b | 302 | pci_unmap_page(pdev, dmas[f+1], frag->size, PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
303 | } |
304 | dev_kfree_skb_irq(skb); | |
305 | ||
306 | /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs, | |
307 | * aligned up to a power of 2 | |
308 | */ | |
309 | return (nfrags + 3) & ~1; | |
310 | } | |
311 | ||
8d636d8b OJ |
312 | static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac) |
313 | { | |
314 | struct pasemi_mac_csring *ring; | |
315 | u32 val; | |
316 | unsigned int cfg; | |
317 | int chno; | |
318 | ||
319 | ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring), | |
320 | offsetof(struct pasemi_mac_csring, chan)); | |
321 | ||
322 | if (!ring) { | |
323 | dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n"); | |
324 | goto out_chan; | |
325 | } | |
326 | ||
327 | chno = ring->chan.chno; | |
328 | ||
329 | ring->size = CS_RING_SIZE; | |
330 | ring->next_to_fill = 0; | |
331 | ||
332 | /* Allocate descriptors */ | |
333 | if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE)) | |
334 | goto out_ring_desc; | |
335 | ||
336 | write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), | |
337 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
338 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); | |
339 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3); | |
340 | ||
341 | write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); | |
342 | ||
343 | ring->events[0] = pasemi_dma_alloc_flag(); | |
344 | ring->events[1] = pasemi_dma_alloc_flag(); | |
345 | if (ring->events[0] < 0 || ring->events[1] < 0) | |
346 | goto out_flags; | |
347 | ||
348 | pasemi_dma_clear_flag(ring->events[0]); | |
349 | pasemi_dma_clear_flag(ring->events[1]); | |
350 | ||
351 | ring->fun = pasemi_dma_alloc_fun(); | |
352 | if (ring->fun < 0) | |
353 | goto out_fun; | |
354 | ||
355 | cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP | | |
356 | PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) | | |
357 | PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ; | |
358 | ||
359 | if (translation_enabled()) | |
360 | cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; | |
361 | ||
362 | write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); | |
363 | ||
364 | /* enable channel */ | |
365 | pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | | |
366 | PAS_DMA_TXCHAN_TCMDSTA_DB | | |
367 | PAS_DMA_TXCHAN_TCMDSTA_DE | | |
368 | PAS_DMA_TXCHAN_TCMDSTA_DA); | |
369 | ||
370 | return ring; | |
371 | ||
372 | out_fun: | |
373 | out_flags: | |
374 | if (ring->events[0] >= 0) | |
375 | pasemi_dma_free_flag(ring->events[0]); | |
376 | if (ring->events[1] >= 0) | |
377 | pasemi_dma_free_flag(ring->events[1]); | |
378 | pasemi_dma_free_ring(&ring->chan); | |
379 | out_ring_desc: | |
380 | pasemi_dma_free_chan(&ring->chan); | |
381 | out_chan: | |
382 | ||
383 | return NULL; | |
384 | } | |
385 | ||
386 | static void pasemi_mac_setup_csrings(struct pasemi_mac *mac) | |
387 | { | |
388 | int i; | |
389 | mac->cs[0] = pasemi_mac_setup_csring(mac); | |
390 | if (mac->type == MAC_TYPE_XAUI) | |
391 | mac->cs[1] = pasemi_mac_setup_csring(mac); | |
392 | else | |
393 | mac->cs[1] = 0; | |
394 | ||
395 | for (i = 0; i < MAX_CS; i++) | |
396 | if (mac->cs[i]) | |
397 | mac->num_cs++; | |
398 | } | |
399 | ||
400 | static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring) | |
401 | { | |
402 | pasemi_dma_stop_chan(&csring->chan); | |
403 | pasemi_dma_free_flag(csring->events[0]); | |
404 | pasemi_dma_free_flag(csring->events[1]); | |
405 | pasemi_dma_free_ring(&csring->chan); | |
406 | pasemi_dma_free_chan(&csring->chan); | |
1724ac2e | 407 | pasemi_dma_free_fun(csring->fun); |
8d636d8b OJ |
408 | } |
409 | ||
5c15332b | 410 | static int pasemi_mac_setup_rx_resources(const struct net_device *dev) |
f5cd7872 OJ |
411 | { |
412 | struct pasemi_mac_rxring *ring; | |
413 | struct pasemi_mac *mac = netdev_priv(dev); | |
34c20624 | 414 | int chno; |
af289e80 | 415 | unsigned int cfg; |
f5cd7872 | 416 | |
34c20624 OJ |
417 | ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring), |
418 | offsetof(struct pasemi_mac_rxring, chan)); | |
f5cd7872 | 419 | |
34c20624 OJ |
420 | if (!ring) { |
421 | dev_err(&mac->pdev->dev, "Can't allocate RX channel\n"); | |
422 | goto out_chan; | |
423 | } | |
424 | chno = ring->chan.chno; | |
f5cd7872 OJ |
425 | |
426 | spin_lock_init(&ring->lock); | |
427 | ||
021fa22e | 428 | ring->size = RX_RING_SIZE; |
fc9e4d2a | 429 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 OJ |
430 | RX_RING_SIZE, GFP_KERNEL); |
431 | ||
fc9e4d2a OJ |
432 | if (!ring->ring_info) |
433 | goto out_ring_info; | |
f5cd7872 OJ |
434 | |
435 | /* Allocate descriptors */ | |
34c20624 | 436 | if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE)) |
fc9e4d2a | 437 | goto out_ring_desc; |
f5cd7872 | 438 | |
f5cd7872 OJ |
439 | ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev, |
440 | RX_RING_SIZE * sizeof(u64), | |
441 | &ring->buf_dma, GFP_KERNEL); | |
442 | if (!ring->buffers) | |
34c20624 | 443 | goto out_ring_desc; |
f5cd7872 OJ |
444 | |
445 | memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64)); | |
446 | ||
34c20624 OJ |
447 | write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno), |
448 | PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
f5cd7872 | 449 | |
34c20624 OJ |
450 | write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno), |
451 | PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) | | |
452 | PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 453 | |
5c15332b | 454 | cfg = PAS_DMA_RXCHAN_CFG_HBU(2); |
af289e80 OJ |
455 | |
456 | if (translation_enabled()) | |
457 | cfg |= PAS_DMA_RXCHAN_CFG_CTR; | |
458 | ||
34c20624 | 459 | write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg); |
f5cd7872 | 460 | |
34c20624 OJ |
461 | write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if), |
462 | PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma)); | |
f5cd7872 | 463 | |
34c20624 OJ |
464 | write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if), |
465 | PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) | | |
466 | PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 467 | |
5c15332b | 468 | cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 | |
af289e80 OJ |
469 | PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP | |
470 | PAS_DMA_RXINT_CFG_HEN; | |
471 | ||
472 | if (translation_enabled()) | |
473 | cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR; | |
474 | ||
34c20624 | 475 | write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg); |
c0efd52b | 476 | |
f5cd7872 OJ |
477 | ring->next_to_fill = 0; |
478 | ring->next_to_clean = 0; | |
72b05b99 | 479 | ring->mac = mac; |
f5cd7872 OJ |
480 | mac->rx = ring; |
481 | ||
482 | return 0; | |
483 | ||
fc9e4d2a OJ |
484 | out_ring_desc: |
485 | kfree(ring->ring_info); | |
486 | out_ring_info: | |
34c20624 OJ |
487 | pasemi_dma_free_chan(&ring->chan); |
488 | out_chan: | |
f5cd7872 OJ |
489 | return -ENOMEM; |
490 | } | |
491 | ||
72b05b99 | 492 | static struct pasemi_mac_txring * |
5c15332b | 493 | pasemi_mac_setup_tx_resources(const struct net_device *dev) |
f5cd7872 OJ |
494 | { |
495 | struct pasemi_mac *mac = netdev_priv(dev); | |
496 | u32 val; | |
f5cd7872 | 497 | struct pasemi_mac_txring *ring; |
af289e80 | 498 | unsigned int cfg; |
34c20624 | 499 | int chno; |
f5cd7872 | 500 | |
34c20624 OJ |
501 | ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring), |
502 | offsetof(struct pasemi_mac_txring, chan)); | |
503 | ||
504 | if (!ring) { | |
505 | dev_err(&mac->pdev->dev, "Can't allocate TX channel\n"); | |
506 | goto out_chan; | |
507 | } | |
508 | ||
509 | chno = ring->chan.chno; | |
f5cd7872 OJ |
510 | |
511 | spin_lock_init(&ring->lock); | |
512 | ||
021fa22e | 513 | ring->size = TX_RING_SIZE; |
fc9e4d2a | 514 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 | 515 | TX_RING_SIZE, GFP_KERNEL); |
fc9e4d2a OJ |
516 | if (!ring->ring_info) |
517 | goto out_ring_info; | |
f5cd7872 OJ |
518 | |
519 | /* Allocate descriptors */ | |
34c20624 | 520 | if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE)) |
fc9e4d2a | 521 | goto out_ring_desc; |
f5cd7872 | 522 | |
34c20624 OJ |
523 | write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), |
524 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
525 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); | |
fc9e4d2a | 526 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3); |
f5cd7872 | 527 | |
34c20624 | 528 | write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); |
f5cd7872 | 529 | |
af289e80 OJ |
530 | cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE | |
531 | PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | | |
532 | PAS_DMA_TXCHAN_CFG_UP | | |
8d636d8b | 533 | PAS_DMA_TXCHAN_CFG_WT(4); |
af289e80 OJ |
534 | |
535 | if (translation_enabled()) | |
536 | cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; | |
537 | ||
34c20624 | 538 | write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); |
f5cd7872 | 539 | |
021fa22e | 540 | ring->next_to_fill = 0; |
f5cd7872 | 541 | ring->next_to_clean = 0; |
72b05b99 | 542 | ring->mac = mac; |
f5cd7872 | 543 | |
72b05b99 | 544 | return ring; |
f5cd7872 | 545 | |
fc9e4d2a OJ |
546 | out_ring_desc: |
547 | kfree(ring->ring_info); | |
548 | out_ring_info: | |
34c20624 OJ |
549 | pasemi_dma_free_chan(&ring->chan); |
550 | out_chan: | |
72b05b99 | 551 | return NULL; |
f5cd7872 OJ |
552 | } |
553 | ||
72b05b99 | 554 | static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac) |
f5cd7872 | 555 | { |
72b05b99 | 556 | struct pasemi_mac_txring *txring = tx_ring(mac); |
ad3c20d1 | 557 | unsigned int i, j; |
f5cd7872 | 558 | struct pasemi_mac_buffer *info; |
ad3c20d1 | 559 | dma_addr_t dmas[MAX_SKB_FRAGS+1]; |
7e9916e9 | 560 | int freed, nfrags; |
ad5da10a | 561 | int start, limit; |
fc9e4d2a | 562 | |
72b05b99 OJ |
563 | start = txring->next_to_clean; |
564 | limit = txring->next_to_fill; | |
ad5da10a OJ |
565 | |
566 | /* Compensate for when fill has wrapped and clean has not */ | |
567 | if (start > limit) | |
568 | limit += TX_RING_SIZE; | |
569 | ||
570 | for (i = start; i < limit; i += freed) { | |
72b05b99 | 571 | info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)]; |
fc9e4d2a | 572 | if (info->dma && info->skb) { |
7e9916e9 OJ |
573 | nfrags = skb_shinfo(info->skb)->nr_frags; |
574 | for (j = 0; j <= nfrags; j++) | |
72b05b99 OJ |
575 | dmas[j] = txring->ring_info[(i+1+j) & |
576 | (TX_RING_SIZE-1)].dma; | |
7e9916e9 OJ |
577 | freed = pasemi_mac_unmap_tx_skb(mac, nfrags, |
578 | info->skb, dmas); | |
ad3c20d1 OJ |
579 | } else |
580 | freed = 2; | |
f5cd7872 OJ |
581 | } |
582 | ||
72b05b99 | 583 | kfree(txring->ring_info); |
34c20624 OJ |
584 | pasemi_dma_free_chan(&txring->chan); |
585 | ||
f5cd7872 OJ |
586 | } |
587 | ||
ef1ea0b4 | 588 | static void pasemi_mac_free_rx_buffers(struct pasemi_mac *mac) |
f5cd7872 | 589 | { |
72b05b99 | 590 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
f5cd7872 OJ |
591 | unsigned int i; |
592 | struct pasemi_mac_buffer *info; | |
f5cd7872 OJ |
593 | |
594 | for (i = 0; i < RX_RING_SIZE; i++) { | |
72b05b99 | 595 | info = &RX_DESC_INFO(rx, i); |
fc9e4d2a OJ |
596 | if (info->skb && info->dma) { |
597 | pci_unmap_single(mac->dma_pdev, | |
598 | info->dma, | |
599 | info->skb->len, | |
600 | PCI_DMA_FROMDEVICE); | |
601 | dev_kfree_skb_any(info->skb); | |
f5cd7872 | 602 | } |
fc9e4d2a OJ |
603 | info->dma = 0; |
604 | info->skb = NULL; | |
f5cd7872 OJ |
605 | } |
606 | ||
fc9e4d2a | 607 | for (i = 0; i < RX_RING_SIZE; i++) |
ef1ea0b4 OJ |
608 | RX_BUFF(rx, i) = 0; |
609 | } | |
610 | ||
611 | static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac) | |
612 | { | |
613 | pasemi_mac_free_rx_buffers(mac); | |
fc9e4d2a | 614 | |
f5cd7872 | 615 | dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64), |
72b05b99 | 616 | rx_ring(mac)->buffers, rx_ring(mac)->buf_dma); |
f5cd7872 | 617 | |
72b05b99 | 618 | kfree(rx_ring(mac)->ring_info); |
34c20624 | 619 | pasemi_dma_free_chan(&rx_ring(mac)->chan); |
f5cd7872 OJ |
620 | mac->rx = NULL; |
621 | } | |
622 | ||
5c15332b OJ |
623 | static void pasemi_mac_replenish_rx_ring(const struct net_device *dev, |
624 | const int limit) | |
f5cd7872 | 625 | { |
5c15332b | 626 | const struct pasemi_mac *mac = netdev_priv(dev); |
72b05b99 | 627 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
b5254eee | 628 | int fill, count; |
f5cd7872 | 629 | |
cd4ceb24 | 630 | if (limit <= 0) |
f5cd7872 OJ |
631 | return; |
632 | ||
72b05b99 | 633 | fill = rx_ring(mac)->next_to_fill; |
928773c2 | 634 | for (count = 0; count < limit; count++) { |
72b05b99 OJ |
635 | struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill); |
636 | u64 *buff = &RX_BUFF(rx, fill); | |
f5cd7872 OJ |
637 | struct sk_buff *skb; |
638 | dma_addr_t dma; | |
639 | ||
fc9e4d2a OJ |
640 | /* Entry in use? */ |
641 | WARN_ON(*buff); | |
642 | ||
ef1ea0b4 | 643 | skb = dev_alloc_skb(mac->bufsz); |
5d894944 | 644 | skb_reserve(skb, LOCAL_SKB_ALIGN); |
f5cd7872 | 645 | |
9f05cfe2 | 646 | if (unlikely(!skb)) |
f5cd7872 | 647 | break; |
f5cd7872 | 648 | |
8dc121a4 | 649 | dma = pci_map_single(mac->dma_pdev, skb->data, |
ef1ea0b4 | 650 | mac->bufsz - LOCAL_SKB_ALIGN, |
f5cd7872 OJ |
651 | PCI_DMA_FROMDEVICE); |
652 | ||
8d8bb39b | 653 | if (unlikely(pci_dma_mapping_error(mac->dma_pdev, dma))) { |
f5cd7872 | 654 | dev_kfree_skb_irq(info->skb); |
f5cd7872 OJ |
655 | break; |
656 | } | |
657 | ||
658 | info->skb = skb; | |
659 | info->dma = dma; | |
ef1ea0b4 | 660 | *buff = XCT_RXB_LEN(mac->bufsz) | XCT_RXB_ADDR(dma); |
fc9e4d2a | 661 | fill++; |
f5cd7872 OJ |
662 | } |
663 | ||
664 | wmb(); | |
665 | ||
34c20624 | 666 | write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count); |
f5cd7872 | 667 | |
72b05b99 | 668 | rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) & |
b5254eee | 669 | (RX_RING_SIZE - 1); |
f5cd7872 OJ |
670 | } |
671 | ||
5c15332b | 672 | static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac) |
1b0335ea | 673 | { |
906674ab | 674 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
52a94351 | 675 | unsigned int reg, pcnt; |
1b0335ea OJ |
676 | /* Re-enable packet count interrupts: finally |
677 | * ack the packet count interrupt we got in rx_intr. | |
678 | */ | |
679 | ||
906674ab | 680 | pcnt = *rx->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 681 | |
52a94351 | 682 | reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; |
1b0335ea | 683 | |
906674ab OJ |
684 | if (*rx->chan.status & PAS_STATUS_TIMER) |
685 | reg |= PAS_IOB_DMA_RXCH_RESET_TINTC; | |
686 | ||
34c20624 | 687 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg); |
1b0335ea OJ |
688 | } |
689 | ||
5c15332b | 690 | static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac) |
1b0335ea | 691 | { |
52a94351 | 692 | unsigned int reg, pcnt; |
1b0335ea OJ |
693 | |
694 | /* Re-enable packet count interrupts */ | |
34c20624 | 695 | pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 696 | |
52a94351 | 697 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; |
1b0335ea | 698 | |
34c20624 | 699 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg); |
1b0335ea OJ |
700 | } |
701 | ||
702 | ||
5c15332b OJ |
703 | static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac, |
704 | const u64 macrx) | |
69c29d89 OJ |
705 | { |
706 | unsigned int rcmdsta, ccmdsta; | |
34c20624 | 707 | struct pasemi_dmachan *chan = &rx_ring(mac)->chan; |
69c29d89 OJ |
708 | |
709 | if (!netif_msg_rx_err(mac)) | |
710 | return; | |
711 | ||
34c20624 OJ |
712 | rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
713 | ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno)); | |
69c29d89 OJ |
714 | |
715 | printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n", | |
34c20624 | 716 | macrx, *chan->status); |
69c29d89 OJ |
717 | |
718 | printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n", | |
719 | rcmdsta, ccmdsta); | |
720 | } | |
721 | ||
5c15332b OJ |
722 | static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac, |
723 | const u64 mactx) | |
69c29d89 OJ |
724 | { |
725 | unsigned int cmdsta; | |
34c20624 | 726 | struct pasemi_dmachan *chan = &tx_ring(mac)->chan; |
69c29d89 OJ |
727 | |
728 | if (!netif_msg_tx_err(mac)) | |
729 | return; | |
730 | ||
34c20624 | 731 | cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno)); |
69c29d89 OJ |
732 | |
733 | printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\ | |
34c20624 | 734 | "tx status 0x%016lx\n", mactx, *chan->status); |
69c29d89 OJ |
735 | |
736 | printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta); | |
737 | } | |
738 | ||
5c15332b OJ |
739 | static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx, |
740 | const int limit) | |
f5cd7872 | 741 | { |
5c15332b | 742 | const struct pasemi_dmachan *chan = &rx->chan; |
72b05b99 | 743 | struct pasemi_mac *mac = rx->mac; |
5c15332b | 744 | struct pci_dev *pdev = mac->dma_pdev; |
cd4ceb24 | 745 | unsigned int n; |
5c15332b | 746 | int count, buf_index, tot_bytes, packets; |
cd4ceb24 OJ |
747 | struct pasemi_mac_buffer *info; |
748 | struct sk_buff *skb; | |
b5254eee | 749 | unsigned int len; |
5c15332b | 750 | u64 macrx, eval; |
cd4ceb24 | 751 | dma_addr_t dma; |
5c15332b OJ |
752 | |
753 | tot_bytes = 0; | |
754 | packets = 0; | |
f5cd7872 | 755 | |
72b05b99 | 756 | spin_lock(&rx->lock); |
f5cd7872 | 757 | |
72b05b99 | 758 | n = rx->next_to_clean; |
f5cd7872 | 759 | |
72b05b99 | 760 | prefetch(&RX_DESC(rx, n)); |
b5254eee OJ |
761 | |
762 | for (count = 0; count < limit; count++) { | |
72b05b99 | 763 | macrx = RX_DESC(rx, n); |
5c15332b | 764 | prefetch(&RX_DESC(rx, n+4)); |
f5cd7872 | 765 | |
69c29d89 | 766 | if ((macrx & XCT_MACRX_E) || |
34c20624 | 767 | (*chan->status & PAS_STATUS_ERROR)) |
69c29d89 OJ |
768 | pasemi_mac_rx_error(mac, macrx); |
769 | ||
cd4ceb24 | 770 | if (!(macrx & XCT_MACRX_O)) |
f5cd7872 OJ |
771 | break; |
772 | ||
f5cd7872 OJ |
773 | info = NULL; |
774 | ||
b5254eee | 775 | BUG_ON(!(macrx & XCT_MACRX_RR_8BRES)); |
f5cd7872 | 776 | |
72b05b99 | 777 | eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >> |
b5254eee OJ |
778 | XCT_RXRES_8B_EVAL_S; |
779 | buf_index = eval-1; | |
780 | ||
72b05b99 OJ |
781 | dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M); |
782 | info = &RX_DESC_INFO(rx, buf_index); | |
fc9e4d2a | 783 | |
9f05cfe2 | 784 | skb = info->skb; |
f5cd7872 | 785 | |
5c15332b | 786 | prefetch_skb(skb); |
f5cd7872 | 787 | |
cd4ceb24 | 788 | len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S; |
f5cd7872 | 789 | |
ef1ea0b4 | 790 | pci_unmap_single(pdev, dma, mac->bufsz - LOCAL_SKB_ALIGN, |
5c15332b | 791 | PCI_DMA_FROMDEVICE); |
32bee776 OJ |
792 | |
793 | if (macrx & XCT_MACRX_CRC) { | |
794 | /* CRC error flagged */ | |
795 | mac->netdev->stats.rx_errors++; | |
796 | mac->netdev->stats.rx_crc_errors++; | |
4352d826 | 797 | /* No need to free skb, it'll be reused */ |
32bee776 OJ |
798 | goto next; |
799 | } | |
800 | ||
5d894944 | 801 | info->skb = NULL; |
ad5da10a | 802 | info->dma = 0; |
fc9e4d2a | 803 | |
26fcfa95 | 804 | if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) { |
38bf3184 | 805 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
cd4ceb24 | 806 | skb->csum = (macrx & XCT_MACRX_CSUM_M) >> |
f5cd7872 OJ |
807 | XCT_MACRX_CSUM_S; |
808 | } else | |
809 | skb->ip_summed = CHECKSUM_NONE; | |
810 | ||
5c15332b OJ |
811 | packets++; |
812 | tot_bytes += len; | |
813 | ||
814 | /* Don't include CRC */ | |
815 | skb_put(skb, len-4); | |
f5cd7872 | 816 | |
26fcfa95 | 817 | skb->protocol = eth_type_trans(skb, mac->netdev); |
28ae79f5 | 818 | lro_receive_skb(&mac->lro_mgr, skb, (void *)macrx); |
f5cd7872 | 819 | |
32bee776 | 820 | next: |
72b05b99 OJ |
821 | RX_DESC(rx, n) = 0; |
822 | RX_DESC(rx, n+1) = 0; | |
cd4ceb24 | 823 | |
ad5da10a OJ |
824 | /* Need to zero it out since hardware doesn't, since the |
825 | * replenish loop uses it to tell when it's done. | |
826 | */ | |
72b05b99 | 827 | RX_BUFF(rx, buf_index) = 0; |
ad5da10a | 828 | |
b5254eee | 829 | n += 4; |
f5cd7872 OJ |
830 | } |
831 | ||
9a50bebd OJ |
832 | if (n > RX_RING_SIZE) { |
833 | /* Errata 5971 workaround: L2 target of headers */ | |
34c20624 | 834 | write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0); |
9a50bebd OJ |
835 | n &= (RX_RING_SIZE-1); |
836 | } | |
b5254eee | 837 | |
72b05b99 | 838 | rx_ring(mac)->next_to_clean = n; |
b5254eee | 839 | |
28ae79f5 OJ |
840 | lro_flush_all(&mac->lro_mgr); |
841 | ||
b5254eee OJ |
842 | /* Increase is in number of 16-byte entries, and since each descriptor |
843 | * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with | |
844 | * count*2. | |
845 | */ | |
34c20624 | 846 | write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1); |
b5254eee OJ |
847 | |
848 | pasemi_mac_replenish_rx_ring(mac->netdev, count); | |
f5cd7872 | 849 | |
5c15332b OJ |
850 | mac->netdev->stats.rx_bytes += tot_bytes; |
851 | mac->netdev->stats.rx_packets += packets; | |
852 | ||
72b05b99 | 853 | spin_unlock(&rx_ring(mac)->lock); |
f5cd7872 OJ |
854 | |
855 | return count; | |
856 | } | |
857 | ||
ad3c20d1 OJ |
858 | /* Can't make this too large or we blow the kernel stack limits */ |
859 | #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS) | |
860 | ||
72b05b99 | 861 | static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring) |
f5cd7872 | 862 | { |
34c20624 | 863 | struct pasemi_dmachan *chan = &txring->chan; |
72b05b99 | 864 | struct pasemi_mac *mac = txring->mac; |
ad3c20d1 | 865 | int i, j; |
ad5da10a OJ |
866 | unsigned int start, descr_count, buf_count, batch_limit; |
867 | unsigned int ring_limit; | |
02df6cfa | 868 | unsigned int total_count; |
ca7e235f | 869 | unsigned long flags; |
ad3c20d1 OJ |
870 | struct sk_buff *skbs[TX_CLEAN_BATCHSIZE]; |
871 | dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1]; | |
7e9916e9 OJ |
872 | int nf[TX_CLEAN_BATCHSIZE]; |
873 | int nr_frags; | |
f5cd7872 | 874 | |
02df6cfa | 875 | total_count = 0; |
ad5da10a | 876 | batch_limit = TX_CLEAN_BATCHSIZE; |
02df6cfa | 877 | restart: |
72b05b99 | 878 | spin_lock_irqsave(&txring->lock, flags); |
f5cd7872 | 879 | |
72b05b99 OJ |
880 | start = txring->next_to_clean; |
881 | ring_limit = txring->next_to_fill; | |
ad5da10a | 882 | |
7e9916e9 OJ |
883 | prefetch(&TX_DESC_INFO(txring, start+1).skb); |
884 | ||
ad5da10a OJ |
885 | /* Compensate for when fill has wrapped but clean has not */ |
886 | if (start > ring_limit) | |
887 | ring_limit += TX_RING_SIZE; | |
02df6cfa | 888 | |
ad3c20d1 OJ |
889 | buf_count = 0; |
890 | descr_count = 0; | |
f5cd7872 | 891 | |
ad3c20d1 | 892 | for (i = start; |
ad5da10a | 893 | descr_count < batch_limit && i < ring_limit; |
ad3c20d1 | 894 | i += buf_count) { |
72b05b99 | 895 | u64 mactx = TX_DESC(txring, i); |
ad5da10a | 896 | struct sk_buff *skb; |
ad3c20d1 | 897 | |
fc9e4d2a | 898 | if ((mactx & XCT_MACTX_E) || |
34c20624 | 899 | (*chan->status & PAS_STATUS_ERROR)) |
fc9e4d2a | 900 | pasemi_mac_tx_error(mac, mactx); |
69c29d89 | 901 | |
8d636d8b OJ |
902 | /* Skip over control descriptors */ |
903 | if (!(mactx & XCT_MACTX_LLEN_M)) { | |
904 | TX_DESC(txring, i) = 0; | |
905 | TX_DESC(txring, i+1) = 0; | |
906 | buf_count = 2; | |
907 | continue; | |
908 | } | |
909 | ||
910 | skb = TX_DESC_INFO(txring, i+1).skb; | |
911 | nr_frags = TX_DESC_INFO(txring, i).dma; | |
912 | ||
fc9e4d2a | 913 | if (unlikely(mactx & XCT_MACTX_O)) |
02df6cfa | 914 | /* Not yet transmitted */ |
f5cd7872 OJ |
915 | break; |
916 | ||
7e9916e9 OJ |
917 | buf_count = 2 + nr_frags; |
918 | /* Since we always fill with an even number of entries, make | |
919 | * sure we skip any unused one at the end as well. | |
920 | */ | |
921 | if (buf_count & 1) | |
922 | buf_count++; | |
ad3c20d1 | 923 | |
7e9916e9 | 924 | for (j = 0; j <= nr_frags; j++) |
72b05b99 | 925 | dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma; |
ad3c20d1 | 926 | |
7e9916e9 OJ |
927 | skbs[descr_count] = skb; |
928 | nf[descr_count] = nr_frags; | |
929 | ||
72b05b99 OJ |
930 | TX_DESC(txring, i) = 0; |
931 | TX_DESC(txring, i+1) = 0; | |
fc9e4d2a | 932 | |
ad3c20d1 | 933 | descr_count++; |
f5cd7872 | 934 | } |
72b05b99 | 935 | txring->next_to_clean = i & (TX_RING_SIZE-1); |
ad3c20d1 | 936 | |
72b05b99 | 937 | spin_unlock_irqrestore(&txring->lock, flags); |
0ce68c74 OJ |
938 | netif_wake_queue(mac->netdev); |
939 | ||
ad3c20d1 | 940 | for (i = 0; i < descr_count; i++) |
7e9916e9 | 941 | pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]); |
02df6cfa | 942 | |
ad3c20d1 | 943 | total_count += descr_count; |
02df6cfa OJ |
944 | |
945 | /* If the batch was full, try to clean more */ | |
ad5da10a | 946 | if (descr_count == batch_limit) |
02df6cfa OJ |
947 | goto restart; |
948 | ||
949 | return total_count; | |
f5cd7872 OJ |
950 | } |
951 | ||
952 | ||
953 | static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) | |
954 | { | |
5c15332b | 955 | const struct pasemi_mac_rxring *rxring = data; |
34c20624 OJ |
956 | struct pasemi_mac *mac = rxring->mac; |
957 | struct net_device *dev = mac->netdev; | |
5c15332b | 958 | const struct pasemi_dmachan *chan = &rxring->chan; |
f5cd7872 OJ |
959 | unsigned int reg; |
960 | ||
34c20624 | 961 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
962 | return IRQ_NONE; |
963 | ||
6dfa7522 OJ |
964 | /* Don't reset packet count so it won't fire again but clear |
965 | * all others. | |
966 | */ | |
967 | ||
6dfa7522 | 968 | reg = 0; |
34c20624 | 969 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 970 | reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; |
34c20624 | 971 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 972 | reg |= PAS_IOB_DMA_RXCH_RESET_DINTC; |
f5cd7872 | 973 | |
bea3348e | 974 | netif_rx_schedule(dev, &mac->napi); |
6dfa7522 | 975 | |
34c20624 | 976 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg); |
f5cd7872 OJ |
977 | |
978 | return IRQ_HANDLED; | |
979 | } | |
980 | ||
61cec3bd OJ |
981 | #define TX_CLEAN_INTERVAL HZ |
982 | ||
983 | static void pasemi_mac_tx_timer(unsigned long data) | |
984 | { | |
985 | struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data; | |
986 | struct pasemi_mac *mac = txring->mac; | |
987 | ||
988 | pasemi_mac_clean_tx(txring); | |
989 | ||
990 | mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL); | |
991 | ||
992 | pasemi_mac_restart_tx_intr(mac); | |
993 | } | |
994 | ||
f5cd7872 OJ |
995 | static irqreturn_t pasemi_mac_tx_intr(int irq, void *data) |
996 | { | |
72b05b99 | 997 | struct pasemi_mac_txring *txring = data; |
5c15332b | 998 | const struct pasemi_dmachan *chan = &txring->chan; |
61cec3bd OJ |
999 | struct pasemi_mac *mac = txring->mac; |
1000 | unsigned int reg; | |
f5cd7872 | 1001 | |
34c20624 | 1002 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
1003 | return IRQ_NONE; |
1004 | ||
61cec3bd | 1005 | reg = 0; |
6dfa7522 | 1006 | |
34c20624 | 1007 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 1008 | reg |= PAS_IOB_DMA_TXCH_RESET_SINTC; |
34c20624 | 1009 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 1010 | reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; |
f5cd7872 | 1011 | |
61cec3bd OJ |
1012 | mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2); |
1013 | ||
1014 | netif_rx_schedule(mac->netdev, &mac->napi); | |
1015 | ||
1016 | if (reg) | |
1017 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg); | |
f5cd7872 | 1018 | |
f5cd7872 OJ |
1019 | return IRQ_HANDLED; |
1020 | } | |
1021 | ||
bb6e9590 OJ |
1022 | static void pasemi_adjust_link(struct net_device *dev) |
1023 | { | |
1024 | struct pasemi_mac *mac = netdev_priv(dev); | |
1025 | int msg; | |
1026 | unsigned int flags; | |
1027 | unsigned int new_flags; | |
1028 | ||
1029 | if (!mac->phydev->link) { | |
1030 | /* If no link, MAC speed settings don't matter. Just report | |
1031 | * link down and return. | |
1032 | */ | |
1033 | if (mac->link && netif_msg_link(mac)) | |
1034 | printk(KERN_INFO "%s: Link is down.\n", dev->name); | |
1035 | ||
1036 | netif_carrier_off(dev); | |
b0cd2f90 | 1037 | pasemi_mac_intf_disable(mac); |
bb6e9590 OJ |
1038 | mac->link = 0; |
1039 | ||
1040 | return; | |
b0cd2f90 OJ |
1041 | } else { |
1042 | pasemi_mac_intf_enable(mac); | |
bb6e9590 | 1043 | netif_carrier_on(dev); |
b0cd2f90 | 1044 | } |
bb6e9590 | 1045 | |
a85b9422 | 1046 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
bb6e9590 OJ |
1047 | new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | |
1048 | PAS_MAC_CFG_PCFG_TSR_M); | |
1049 | ||
1050 | if (!mac->phydev->duplex) | |
1051 | new_flags |= PAS_MAC_CFG_PCFG_HD; | |
1052 | ||
1053 | switch (mac->phydev->speed) { | |
1054 | case 1000: | |
1055 | new_flags |= PAS_MAC_CFG_PCFG_SPD_1G | | |
1056 | PAS_MAC_CFG_PCFG_TSR_1G; | |
1057 | break; | |
1058 | case 100: | |
1059 | new_flags |= PAS_MAC_CFG_PCFG_SPD_100M | | |
1060 | PAS_MAC_CFG_PCFG_TSR_100M; | |
1061 | break; | |
1062 | case 10: | |
1063 | new_flags |= PAS_MAC_CFG_PCFG_SPD_10M | | |
1064 | PAS_MAC_CFG_PCFG_TSR_10M; | |
1065 | break; | |
1066 | default: | |
1067 | printk("Unsupported speed %d\n", mac->phydev->speed); | |
1068 | } | |
1069 | ||
1070 | /* Print on link or speed/duplex change */ | |
1071 | msg = mac->link != mac->phydev->link || flags != new_flags; | |
1072 | ||
1073 | mac->duplex = mac->phydev->duplex; | |
1074 | mac->speed = mac->phydev->speed; | |
1075 | mac->link = mac->phydev->link; | |
1076 | ||
1077 | if (new_flags != flags) | |
a85b9422 | 1078 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags); |
bb6e9590 OJ |
1079 | |
1080 | if (msg && netif_msg_link(mac)) | |
1081 | printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", | |
1082 | dev->name, mac->speed, mac->duplex ? "full" : "half"); | |
1083 | } | |
1084 | ||
1085 | static int pasemi_mac_phy_init(struct net_device *dev) | |
1086 | { | |
1087 | struct pasemi_mac *mac = netdev_priv(dev); | |
1088 | struct device_node *dn, *phy_dn; | |
1089 | struct phy_device *phydev; | |
1090 | unsigned int phy_id; | |
1091 | const phandle *ph; | |
1092 | const unsigned int *prop; | |
1093 | struct resource r; | |
1094 | int ret; | |
1095 | ||
1096 | dn = pci_device_to_OF_node(mac->pdev); | |
9028780a | 1097 | ph = of_get_property(dn, "phy-handle", NULL); |
bb6e9590 OJ |
1098 | if (!ph) |
1099 | return -ENODEV; | |
1100 | phy_dn = of_find_node_by_phandle(*ph); | |
1101 | ||
9028780a | 1102 | prop = of_get_property(phy_dn, "reg", NULL); |
bb6e9590 OJ |
1103 | ret = of_address_to_resource(phy_dn->parent, 0, &r); |
1104 | if (ret) | |
1105 | goto err; | |
1106 | ||
1107 | phy_id = *prop; | |
fb28ad35 KS |
1108 | snprintf(mac->phy_id, sizeof(mac->phy_id), "%x:%02x", |
1109 | (int)r.start, phy_id); | |
bb6e9590 OJ |
1110 | |
1111 | of_node_put(phy_dn); | |
1112 | ||
1113 | mac->link = 0; | |
1114 | mac->speed = 0; | |
1115 | mac->duplex = -1; | |
1116 | ||
1117 | phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII); | |
1118 | ||
1119 | if (IS_ERR(phydev)) { | |
1120 | printk(KERN_ERR "%s: Could not attach to phy\n", dev->name); | |
1121 | return PTR_ERR(phydev); | |
1122 | } | |
1123 | ||
1124 | mac->phydev = phydev; | |
1125 | ||
1126 | return 0; | |
1127 | ||
1128 | err: | |
1129 | of_node_put(phy_dn); | |
1130 | return -ENODEV; | |
1131 | } | |
1132 | ||
1133 | ||
f5cd7872 OJ |
1134 | static int pasemi_mac_open(struct net_device *dev) |
1135 | { | |
1136 | struct pasemi_mac *mac = netdev_priv(dev); | |
1137 | unsigned int flags; | |
e37c772e | 1138 | int i, ret; |
f5cd7872 OJ |
1139 | |
1140 | flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | | |
1141 | PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | | |
1142 | PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); | |
1143 | ||
a85b9422 | 1144 | write_mac_reg(mac, PAS_MAC_CFG_TXP, flags); |
f5cd7872 | 1145 | |
f5cd7872 OJ |
1146 | ret = pasemi_mac_setup_rx_resources(dev); |
1147 | if (ret) | |
1148 | goto out_rx_resources; | |
1149 | ||
34c20624 | 1150 | mac->tx = pasemi_mac_setup_tx_resources(dev); |
72b05b99 OJ |
1151 | |
1152 | if (!mac->tx) | |
1153 | goto out_tx_ring; | |
f5cd7872 | 1154 | |
1724ac2e OJ |
1155 | /* We might already have allocated rings in case mtu was changed |
1156 | * before interface was brought up. | |
1157 | */ | |
1158 | if (dev->mtu > 1500 && !mac->num_cs) { | |
8d636d8b OJ |
1159 | pasemi_mac_setup_csrings(mac); |
1160 | if (!mac->num_cs) | |
1161 | goto out_tx_ring; | |
1162 | } | |
1163 | ||
e37c772e OJ |
1164 | /* Zero out rmon counters */ |
1165 | for (i = 0; i < 32; i++) | |
1166 | write_mac_reg(mac, PAS_MAC_RMON(i), 0); | |
1167 | ||
906674ab OJ |
1168 | /* 0x3ff with 33MHz clock is about 31us */ |
1169 | write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG, | |
1170 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff)); | |
1171 | ||
34c20624 | 1172 | write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno), |
28ae79f5 | 1173 | PAS_IOB_DMA_RXCH_CFG_CNTTH(256)); |
34c20624 OJ |
1174 | |
1175 | write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno), | |
61cec3bd | 1176 | PAS_IOB_DMA_TXCH_CFG_CNTTH(32)); |
34c20624 | 1177 | |
a85b9422 | 1178 | write_mac_reg(mac, PAS_MAC_IPC_CHNL, |
34c20624 OJ |
1179 | PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) | |
1180 | PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno)); | |
f5cd7872 OJ |
1181 | |
1182 | /* enable rx if */ | |
34c20624 OJ |
1183 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), |
1184 | PAS_DMA_RXINT_RCMDSTA_EN | | |
1185 | PAS_DMA_RXINT_RCMDSTA_DROPS_M | | |
1186 | PAS_DMA_RXINT_RCMDSTA_BP | | |
1187 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1188 | PAS_DMA_RXINT_RCMDSTA_BT); | |
f5cd7872 OJ |
1189 | |
1190 | /* enable rx channel */ | |
34c20624 OJ |
1191 | pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU | |
1192 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1193 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1194 | PAS_DMA_RXCHAN_CCMDSTA_DT); | |
f5cd7872 OJ |
1195 | |
1196 | /* enable tx channel */ | |
34c20624 OJ |
1197 | pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | |
1198 | PAS_DMA_TXCHAN_TCMDSTA_DB | | |
1199 | PAS_DMA_TXCHAN_TCMDSTA_DE | | |
1200 | PAS_DMA_TXCHAN_TCMDSTA_DA); | |
f5cd7872 | 1201 | |
928773c2 | 1202 | pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE); |
f5cd7872 | 1203 | |
34c20624 OJ |
1204 | write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno), |
1205 | RX_RING_SIZE>>1); | |
b5254eee | 1206 | |
72b05b99 OJ |
1207 | /* Clear out any residual packet count state from firmware */ |
1208 | pasemi_mac_restart_rx_intr(mac); | |
1209 | pasemi_mac_restart_tx_intr(mac); | |
1210 | ||
b0cd2f90 | 1211 | flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; |
36033766 OJ |
1212 | |
1213 | if (mac->type == MAC_TYPE_GMAC) | |
1214 | flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; | |
1215 | else | |
1216 | flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G; | |
1217 | ||
1218 | /* Enable interface in MAC */ | |
1219 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
1220 | ||
bb6e9590 | 1221 | ret = pasemi_mac_phy_init(dev); |
b0cd2f90 OJ |
1222 | if (ret) { |
1223 | /* Since we won't get link notification, just enable RX */ | |
1224 | pasemi_mac_intf_enable(mac); | |
1225 | if (mac->type == MAC_TYPE_GMAC) { | |
1226 | /* Warn for missing PHY on SGMII (1Gig) ports */ | |
1227 | dev_warn(&mac->pdev->dev, | |
1228 | "PHY init failed: %d.\n", ret); | |
1229 | dev_warn(&mac->pdev->dev, | |
1230 | "Defaulting to 1Gbit full duplex\n"); | |
1231 | } | |
8304b633 | 1232 | } |
bb6e9590 | 1233 | |
f5cd7872 | 1234 | netif_start_queue(dev); |
bea3348e | 1235 | napi_enable(&mac->napi); |
f5cd7872 | 1236 | |
72b05b99 OJ |
1237 | snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx", |
1238 | dev->name); | |
771f7404 | 1239 | |
34c20624 | 1240 | ret = request_irq(mac->tx->chan.irq, &pasemi_mac_tx_intr, IRQF_DISABLED, |
72b05b99 | 1241 | mac->tx_irq_name, mac->tx); |
f5cd7872 OJ |
1242 | if (ret) { |
1243 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1244 | mac->tx->chan.irq, ret); |
f5cd7872 OJ |
1245 | goto out_tx_int; |
1246 | } | |
1247 | ||
72b05b99 OJ |
1248 | snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx", |
1249 | dev->name); | |
1250 | ||
34c20624 OJ |
1251 | ret = request_irq(mac->rx->chan.irq, &pasemi_mac_rx_intr, IRQF_DISABLED, |
1252 | mac->rx_irq_name, mac->rx); | |
f5cd7872 OJ |
1253 | if (ret) { |
1254 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1255 | mac->rx->chan.irq, ret); |
f5cd7872 OJ |
1256 | goto out_rx_int; |
1257 | } | |
1258 | ||
bb6e9590 OJ |
1259 | if (mac->phydev) |
1260 | phy_start(mac->phydev); | |
1261 | ||
61cec3bd OJ |
1262 | init_timer(&mac->tx->clean_timer); |
1263 | mac->tx->clean_timer.function = pasemi_mac_tx_timer; | |
1264 | mac->tx->clean_timer.data = (unsigned long)mac->tx; | |
1265 | mac->tx->clean_timer.expires = jiffies+HZ; | |
1266 | add_timer(&mac->tx->clean_timer); | |
1267 | ||
f5cd7872 OJ |
1268 | return 0; |
1269 | ||
1270 | out_rx_int: | |
34c20624 | 1271 | free_irq(mac->tx->chan.irq, mac->tx); |
f5cd7872 | 1272 | out_tx_int: |
bea3348e | 1273 | napi_disable(&mac->napi); |
f5cd7872 | 1274 | netif_stop_queue(dev); |
72b05b99 OJ |
1275 | out_tx_ring: |
1276 | if (mac->tx) | |
1277 | pasemi_mac_free_tx_resources(mac); | |
1278 | pasemi_mac_free_rx_resources(mac); | |
f5cd7872 OJ |
1279 | out_rx_resources: |
1280 | ||
1281 | return ret; | |
1282 | } | |
1283 | ||
1284 | #define MAX_RETRIES 5000 | |
1285 | ||
ef1ea0b4 OJ |
1286 | static void pasemi_mac_pause_txchan(struct pasemi_mac *mac) |
1287 | { | |
1288 | unsigned int sta, retries; | |
1289 | int txch = tx_ring(mac)->chan.chno; | |
1290 | ||
1291 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), | |
1292 | PAS_DMA_TXCHAN_TCMDSTA_ST); | |
1293 | ||
1294 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1295 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); | |
1296 | if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) | |
1297 | break; | |
1298 | cond_resched(); | |
1299 | } | |
1300 | ||
1301 | if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT) | |
1302 | dev_err(&mac->dma_pdev->dev, | |
1303 | "Failed to stop tx channel, tcmdsta %08x\n", sta); | |
1304 | ||
1305 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0); | |
1306 | } | |
1307 | ||
1308 | static void pasemi_mac_pause_rxchan(struct pasemi_mac *mac) | |
1309 | { | |
1310 | unsigned int sta, retries; | |
1311 | int rxch = rx_ring(mac)->chan.chno; | |
1312 | ||
1313 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), | |
1314 | PAS_DMA_RXCHAN_CCMDSTA_ST); | |
1315 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1316 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); | |
1317 | if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) | |
1318 | break; | |
1319 | cond_resched(); | |
1320 | } | |
1321 | ||
1322 | if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT) | |
1323 | dev_err(&mac->dma_pdev->dev, | |
1324 | "Failed to stop rx channel, ccmdsta 08%x\n", sta); | |
1325 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0); | |
1326 | } | |
1327 | ||
1328 | static void pasemi_mac_pause_rxint(struct pasemi_mac *mac) | |
1329 | { | |
1330 | unsigned int sta, retries; | |
1331 | ||
1332 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | |
1333 | PAS_DMA_RXINT_RCMDSTA_ST); | |
1334 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1335 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); | |
1336 | if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT)) | |
1337 | break; | |
1338 | cond_resched(); | |
1339 | } | |
1340 | ||
1341 | if (sta & PAS_DMA_RXINT_RCMDSTA_ACT) | |
1342 | dev_err(&mac->dma_pdev->dev, | |
1343 | "Failed to stop rx interface, rcmdsta %08x\n", sta); | |
1344 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); | |
1345 | } | |
1346 | ||
f5cd7872 OJ |
1347 | static int pasemi_mac_close(struct net_device *dev) |
1348 | { | |
1349 | struct pasemi_mac *mac = netdev_priv(dev); | |
9e81d331 | 1350 | unsigned int sta; |
8d636d8b | 1351 | int rxch, txch, i; |
34c20624 OJ |
1352 | |
1353 | rxch = rx_ring(mac)->chan.chno; | |
1354 | txch = tx_ring(mac)->chan.chno; | |
f5cd7872 | 1355 | |
bb6e9590 OJ |
1356 | if (mac->phydev) { |
1357 | phy_stop(mac->phydev); | |
1358 | phy_disconnect(mac->phydev); | |
1359 | } | |
1360 | ||
61cec3bd OJ |
1361 | del_timer_sync(&mac->tx->clean_timer); |
1362 | ||
f5cd7872 | 1363 | netif_stop_queue(dev); |
bea3348e | 1364 | napi_disable(&mac->napi); |
f5cd7872 | 1365 | |
34c20624 | 1366 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
9e81d331 OJ |
1367 | if (sta & (PAS_DMA_RXINT_RCMDSTA_BP | |
1368 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1369 | PAS_DMA_RXINT_RCMDSTA_BT)) | |
1370 | printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta); | |
1371 | ||
34c20624 | 1372 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); |
9e81d331 OJ |
1373 | if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU | |
1374 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1375 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1376 | PAS_DMA_RXCHAN_CCMDSTA_DT)) | |
1377 | printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta); | |
1378 | ||
34c20624 | 1379 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); |
72b05b99 OJ |
1380 | if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB | |
1381 | PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA)) | |
9e81d331 OJ |
1382 | printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta); |
1383 | ||
f5cd7872 | 1384 | /* Clean out any pending buffers */ |
72b05b99 OJ |
1385 | pasemi_mac_clean_tx(tx_ring(mac)); |
1386 | pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); | |
f5cd7872 | 1387 | |
ef1ea0b4 OJ |
1388 | pasemi_mac_pause_txchan(mac); |
1389 | pasemi_mac_pause_rxint(mac); | |
1390 | pasemi_mac_pause_rxchan(mac); | |
1145d954 | 1391 | pasemi_mac_intf_disable(mac); |
f5cd7872 | 1392 | |
34c20624 OJ |
1393 | free_irq(mac->tx->chan.irq, mac->tx); |
1394 | free_irq(mac->rx->chan.irq, mac->rx); | |
f5cd7872 | 1395 | |
1724ac2e | 1396 | for (i = 0; i < mac->num_cs; i++) { |
8d636d8b | 1397 | pasemi_mac_free_csring(mac->cs[i]); |
1724ac2e OJ |
1398 | mac->cs[i] = NULL; |
1399 | } | |
1400 | ||
1401 | mac->num_cs = 0; | |
8d636d8b | 1402 | |
f5cd7872 | 1403 | /* Free resources */ |
72b05b99 OJ |
1404 | pasemi_mac_free_rx_resources(mac); |
1405 | pasemi_mac_free_tx_resources(mac); | |
f5cd7872 OJ |
1406 | |
1407 | return 0; | |
1408 | } | |
1409 | ||
8d636d8b OJ |
1410 | static void pasemi_mac_queue_csdesc(const struct sk_buff *skb, |
1411 | const dma_addr_t *map, | |
1412 | const unsigned int *map_size, | |
1413 | struct pasemi_mac_txring *txring, | |
1414 | struct pasemi_mac_csring *csring) | |
1415 | { | |
1416 | u64 fund; | |
1417 | dma_addr_t cs_dest; | |
1418 | const int nh_off = skb_network_offset(skb); | |
1419 | const int nh_len = skb_network_header_len(skb); | |
1420 | const int nfrags = skb_shinfo(skb)->nr_frags; | |
1421 | int cs_size, i, fill, hdr, cpyhdr, evt; | |
1422 | dma_addr_t csdma; | |
1423 | ||
1424 | fund = XCT_FUN_ST | XCT_FUN_RR_8BRES | | |
1425 | XCT_FUN_O | XCT_FUN_FUN(csring->fun) | | |
1426 | XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) | | |
1427 | XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE; | |
1428 | ||
1429 | switch (ip_hdr(skb)->protocol) { | |
1430 | case IPPROTO_TCP: | |
1431 | fund |= XCT_FUN_SIG_TCP4; | |
1432 | /* TCP checksum is 16 bytes into the header */ | |
1433 | cs_dest = map[0] + skb_transport_offset(skb) + 16; | |
1434 | break; | |
1435 | case IPPROTO_UDP: | |
1436 | fund |= XCT_FUN_SIG_UDP4; | |
1437 | /* UDP checksum is 6 bytes into the header */ | |
1438 | cs_dest = map[0] + skb_transport_offset(skb) + 6; | |
1439 | break; | |
1440 | default: | |
1441 | BUG(); | |
1442 | } | |
1443 | ||
1444 | /* Do the checksum offloaded */ | |
1445 | fill = csring->next_to_fill; | |
1446 | hdr = fill; | |
1447 | ||
1448 | CS_DESC(csring, fill++) = fund; | |
1449 | /* Room for 8BRES. Checksum result is really 2 bytes into it */ | |
1450 | csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2; | |
1451 | CS_DESC(csring, fill++) = 0; | |
1452 | ||
1453 | CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off); | |
1454 | for (i = 1; i <= nfrags; i++) | |
1455 | CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); | |
1456 | ||
1457 | fill += i; | |
1458 | if (fill & 1) | |
1459 | fill++; | |
1460 | ||
1461 | /* Copy the result into the TCP packet */ | |
1462 | cpyhdr = fill; | |
1463 | CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) | | |
1464 | XCT_FUN_LLEN(2) | XCT_FUN_SE; | |
1465 | CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T; | |
1466 | CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma); | |
1467 | fill++; | |
1468 | ||
1469 | evt = !csring->last_event; | |
1470 | csring->last_event = evt; | |
1471 | ||
1472 | /* Event handshaking with MAC TX */ | |
1473 | CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1474 | CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]); | |
1475 | CS_DESC(csring, fill++) = 0; | |
1476 | CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1477 | CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]); | |
1478 | CS_DESC(csring, fill++) = 0; | |
1479 | csring->next_to_fill = fill & (CS_RING_SIZE-1); | |
1480 | ||
1481 | cs_size = fill - hdr; | |
1482 | write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1); | |
1483 | ||
1484 | /* TX-side event handshaking */ | |
1485 | fill = txring->next_to_fill; | |
1486 | TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1487 | CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]); | |
1488 | TX_DESC(txring, fill++) = 0; | |
1489 | TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1490 | CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]); | |
1491 | TX_DESC(txring, fill++) = 0; | |
1492 | txring->next_to_fill = fill; | |
1493 | ||
1494 | write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2); | |
1495 | ||
1496 | return; | |
1497 | } | |
1498 | ||
f5cd7872 OJ |
1499 | static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) |
1500 | { | |
8d636d8b OJ |
1501 | struct pasemi_mac * const mac = netdev_priv(dev); |
1502 | struct pasemi_mac_txring * const txring = tx_ring(mac); | |
1503 | struct pasemi_mac_csring *csring; | |
1504 | u64 dflags = 0; | |
1505 | u64 mactx; | |
ad3c20d1 OJ |
1506 | dma_addr_t map[MAX_SKB_FRAGS+1]; |
1507 | unsigned int map_size[MAX_SKB_FRAGS+1]; | |
ca7e235f | 1508 | unsigned long flags; |
ad3c20d1 | 1509 | int i, nfrags; |
5c15332b | 1510 | int fill; |
8d636d8b OJ |
1511 | const int nh_off = skb_network_offset(skb); |
1512 | const int nh_len = skb_network_header_len(skb); | |
f5cd7872 | 1513 | |
8d636d8b | 1514 | prefetch(&txring->ring_info); |
d56f90a7 | 1515 | |
8d636d8b | 1516 | dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD; |
f5cd7872 | 1517 | |
ad3c20d1 OJ |
1518 | nfrags = skb_shinfo(skb)->nr_frags; |
1519 | ||
1520 | map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb), | |
1521 | PCI_DMA_TODEVICE); | |
1522 | map_size[0] = skb_headlen(skb); | |
8d8bb39b | 1523 | if (pci_dma_mapping_error(mac->dma_pdev, map[0])) |
ad3c20d1 OJ |
1524 | goto out_err_nolock; |
1525 | ||
1526 | for (i = 0; i < nfrags; i++) { | |
1527 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
f5cd7872 | 1528 | |
ad3c20d1 OJ |
1529 | map[i+1] = pci_map_page(mac->dma_pdev, frag->page, |
1530 | frag->page_offset, frag->size, | |
1531 | PCI_DMA_TODEVICE); | |
1532 | map_size[i+1] = frag->size; | |
8d8bb39b | 1533 | if (pci_dma_mapping_error(mac->dma_pdev, map[i+1])) { |
ad3c20d1 OJ |
1534 | nfrags = i; |
1535 | goto out_err_nolock; | |
1536 | } | |
1537 | } | |
f5cd7872 | 1538 | |
8d636d8b OJ |
1539 | if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) { |
1540 | switch (ip_hdr(skb)->protocol) { | |
1541 | case IPPROTO_TCP: | |
1542 | dflags |= XCT_MACTX_CSUM_TCP; | |
1543 | dflags |= XCT_MACTX_IPH(nh_len >> 2); | |
1544 | dflags |= XCT_MACTX_IPO(nh_off); | |
1545 | break; | |
1546 | case IPPROTO_UDP: | |
1547 | dflags |= XCT_MACTX_CSUM_UDP; | |
1548 | dflags |= XCT_MACTX_IPH(nh_len >> 2); | |
1549 | dflags |= XCT_MACTX_IPO(nh_off); | |
1550 | break; | |
1551 | default: | |
1552 | WARN_ON(1); | |
1553 | } | |
1554 | } | |
26fcfa95 | 1555 | |
8d636d8b | 1556 | mactx = dflags | XCT_MACTX_LLEN(skb->len); |
f5cd7872 OJ |
1557 | |
1558 | spin_lock_irqsave(&txring->lock, flags); | |
1559 | ||
ad5da10a OJ |
1560 | /* Avoid stepping on the same cache line that the DMA controller |
1561 | * is currently about to send, so leave at least 8 words available. | |
1562 | * Total free space needed is mactx + fragments + 8 | |
1563 | */ | |
8d636d8b | 1564 | if (RING_AVAIL(txring) < nfrags + 14) { |
ad5da10a OJ |
1565 | /* no room -- stop the queue and wait for tx intr */ |
1566 | netif_stop_queue(dev); | |
1567 | goto out_err; | |
f5cd7872 OJ |
1568 | } |
1569 | ||
8d636d8b OJ |
1570 | /* Queue up checksum + event descriptors, if needed */ |
1571 | if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) { | |
1572 | csring = mac->cs[mac->last_cs]; | |
1573 | mac->last_cs = (mac->last_cs + 1) % mac->num_cs; | |
1574 | ||
1575 | pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring); | |
1576 | } | |
1577 | ||
1578 | fill = txring->next_to_fill; | |
5c15332b | 1579 | TX_DESC(txring, fill) = mactx; |
7e9916e9 | 1580 | TX_DESC_INFO(txring, fill).dma = nfrags; |
5c15332b OJ |
1581 | fill++; |
1582 | TX_DESC_INFO(txring, fill).skb = skb; | |
ad3c20d1 | 1583 | for (i = 0; i <= nfrags; i++) { |
5c15332b | 1584 | TX_DESC(txring, fill+i) = |
72b05b99 | 1585 | XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); |
5c15332b | 1586 | TX_DESC_INFO(txring, fill+i).dma = map[i]; |
ad3c20d1 OJ |
1587 | } |
1588 | ||
1589 | /* We have to add an even number of 8-byte entries to the ring | |
1590 | * even if the last one is unused. That means always an odd number | |
1591 | * of pointers + one mactx descriptor. | |
1592 | */ | |
1593 | if (nfrags & 1) | |
1594 | nfrags++; | |
fc9e4d2a | 1595 | |
5c15332b | 1596 | txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1); |
f5cd7872 | 1597 | |
09f75cd7 JG |
1598 | dev->stats.tx_packets++; |
1599 | dev->stats.tx_bytes += skb->len; | |
f5cd7872 OJ |
1600 | |
1601 | spin_unlock_irqrestore(&txring->lock, flags); | |
1602 | ||
34c20624 | 1603 | write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1); |
f5cd7872 OJ |
1604 | |
1605 | return NETDEV_TX_OK; | |
1606 | ||
1607 | out_err: | |
1608 | spin_unlock_irqrestore(&txring->lock, flags); | |
ad3c20d1 OJ |
1609 | out_err_nolock: |
1610 | while (nfrags--) | |
1611 | pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags], | |
1612 | PCI_DMA_TODEVICE); | |
1613 | ||
f5cd7872 OJ |
1614 | return NETDEV_TX_BUSY; |
1615 | } | |
1616 | ||
f5cd7872 OJ |
1617 | static void pasemi_mac_set_rx_mode(struct net_device *dev) |
1618 | { | |
5c15332b | 1619 | const struct pasemi_mac *mac = netdev_priv(dev); |
f5cd7872 OJ |
1620 | unsigned int flags; |
1621 | ||
a85b9422 | 1622 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
f5cd7872 OJ |
1623 | |
1624 | /* Set promiscuous */ | |
1625 | if (dev->flags & IFF_PROMISC) | |
1626 | flags |= PAS_MAC_CFG_PCFG_PR; | |
1627 | else | |
1628 | flags &= ~PAS_MAC_CFG_PCFG_PR; | |
1629 | ||
a85b9422 | 1630 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); |
f5cd7872 OJ |
1631 | } |
1632 | ||
1633 | ||
bea3348e | 1634 | static int pasemi_mac_poll(struct napi_struct *napi, int budget) |
f5cd7872 | 1635 | { |
bea3348e SH |
1636 | struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi); |
1637 | struct net_device *dev = mac->netdev; | |
1638 | int pkts; | |
f5cd7872 | 1639 | |
72b05b99 OJ |
1640 | pasemi_mac_clean_tx(tx_ring(mac)); |
1641 | pkts = pasemi_mac_clean_rx(rx_ring(mac), budget); | |
bea3348e | 1642 | if (pkts < budget) { |
f5cd7872 | 1643 | /* all done, no more packets present */ |
bea3348e | 1644 | netif_rx_complete(dev, napi); |
f5cd7872 | 1645 | |
1b0335ea | 1646 | pasemi_mac_restart_rx_intr(mac); |
61cec3bd | 1647 | pasemi_mac_restart_tx_intr(mac); |
f5cd7872 | 1648 | } |
bea3348e | 1649 | return pkts; |
f5cd7872 OJ |
1650 | } |
1651 | ||
6e62040c NC |
1652 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1653 | /* | |
1654 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1655 | * without having to re-enable interrupts. It's not called while | |
1656 | * the interrupt routine is executing. | |
1657 | */ | |
1658 | static void pasemi_mac_netpoll(struct net_device *dev) | |
1659 | { | |
1660 | const struct pasemi_mac *mac = netdev_priv(dev); | |
1661 | ||
1662 | disable_irq(mac->tx->chan.irq); | |
1663 | pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx); | |
1664 | enable_irq(mac->tx->chan.irq); | |
1665 | ||
1666 | disable_irq(mac->rx->chan.irq); | |
1667 | pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx); | |
1668 | enable_irq(mac->rx->chan.irq); | |
1669 | } | |
1670 | #endif | |
1671 | ||
ef1ea0b4 OJ |
1672 | static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu) |
1673 | { | |
1674 | struct pasemi_mac *mac = netdev_priv(dev); | |
1675 | unsigned int reg; | |
8d636d8b | 1676 | unsigned int rcmdsta = 0; |
ef1ea0b4 | 1677 | int running; |
8d636d8b | 1678 | int ret = 0; |
ef1ea0b4 OJ |
1679 | |
1680 | if (new_mtu < PE_MIN_MTU || new_mtu > PE_MAX_MTU) | |
1681 | return -EINVAL; | |
1682 | ||
1683 | running = netif_running(dev); | |
1684 | ||
1685 | if (running) { | |
1686 | /* Need to stop the interface, clean out all already | |
1687 | * received buffers, free all unused buffers on the RX | |
1688 | * interface ring, then finally re-fill the rx ring with | |
1689 | * the new-size buffers and restart. | |
1690 | */ | |
1691 | ||
1692 | napi_disable(&mac->napi); | |
1693 | netif_tx_disable(dev); | |
1694 | pasemi_mac_intf_disable(mac); | |
1695 | ||
1696 | rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); | |
1697 | pasemi_mac_pause_rxint(mac); | |
1698 | pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); | |
1699 | pasemi_mac_free_rx_buffers(mac); | |
8d636d8b OJ |
1700 | |
1701 | } | |
1702 | ||
1703 | /* Setup checksum channels if large MTU and none already allocated */ | |
1704 | if (new_mtu > 1500 && !mac->num_cs) { | |
1705 | pasemi_mac_setup_csrings(mac); | |
1706 | if (!mac->num_cs) { | |
1707 | ret = -ENOMEM; | |
1708 | goto out; | |
1709 | } | |
ef1ea0b4 OJ |
1710 | } |
1711 | ||
1712 | /* Change maxf, i.e. what size frames are accepted. | |
1713 | * Need room for ethernet header and CRC word | |
1714 | */ | |
1715 | reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG); | |
1716 | reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M; | |
1717 | reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4); | |
1718 | write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg); | |
1719 | ||
1720 | dev->mtu = new_mtu; | |
1721 | /* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ | |
1722 | mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; | |
1723 | ||
8d636d8b | 1724 | out: |
ef1ea0b4 OJ |
1725 | if (running) { |
1726 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | |
1727 | rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN); | |
1728 | ||
1729 | rx_ring(mac)->next_to_fill = 0; | |
1730 | pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE-1); | |
1731 | ||
1732 | napi_enable(&mac->napi); | |
1733 | netif_start_queue(dev); | |
1734 | pasemi_mac_intf_enable(mac); | |
1735 | } | |
1736 | ||
8d636d8b | 1737 | return ret; |
ef1ea0b4 OJ |
1738 | } |
1739 | ||
f5cd7872 OJ |
1740 | static int __devinit |
1741 | pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1742 | { | |
f5cd7872 OJ |
1743 | struct net_device *dev; |
1744 | struct pasemi_mac *mac; | |
1745 | int err; | |
1746 | ||
1747 | err = pci_enable_device(pdev); | |
1748 | if (err) | |
1749 | return err; | |
1750 | ||
1751 | dev = alloc_etherdev(sizeof(struct pasemi_mac)); | |
1752 | if (dev == NULL) { | |
1753 | dev_err(&pdev->dev, | |
1754 | "pasemi_mac: Could not allocate ethernet device.\n"); | |
1755 | err = -ENOMEM; | |
1756 | goto out_disable_device; | |
1757 | } | |
1758 | ||
f5cd7872 OJ |
1759 | pci_set_drvdata(pdev, dev); |
1760 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1761 | ||
1762 | mac = netdev_priv(dev); | |
1763 | ||
1764 | mac->pdev = pdev; | |
1765 | mac->netdev = dev; | |
f5cd7872 | 1766 | |
bea3348e SH |
1767 | netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64); |
1768 | ||
5c15332b | 1769 | dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG | |
25156784 | 1770 | NETIF_F_HIGHDMA | NETIF_F_GSO; |
bea3348e | 1771 | |
28ae79f5 OJ |
1772 | mac->lro_mgr.max_aggr = LRO_MAX_AGGR; |
1773 | mac->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS; | |
1774 | mac->lro_mgr.lro_arr = mac->lro_desc; | |
1775 | mac->lro_mgr.get_skb_header = get_skb_hdr; | |
1776 | mac->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID; | |
1777 | mac->lro_mgr.dev = mac->netdev; | |
1778 | mac->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1779 | mac->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
1780 | ||
1781 | ||
34c20624 OJ |
1782 | mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); |
1783 | if (!mac->dma_pdev) { | |
1784 | dev_err(&mac->pdev->dev, "Can't find DMA Controller\n"); | |
1785 | err = -ENODEV; | |
1786 | goto out; | |
1787 | } | |
f5cd7872 | 1788 | |
34c20624 OJ |
1789 | mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); |
1790 | if (!mac->iob_pdev) { | |
1791 | dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n"); | |
1792 | err = -ENODEV; | |
1793 | goto out; | |
1794 | } | |
1795 | ||
1796 | /* get mac addr from device tree */ | |
1797 | if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) { | |
1798 | err = -ENODEV; | |
1799 | goto out; | |
1800 | } | |
1801 | memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr)); | |
1802 | ||
1803 | mac->dma_if = mac_to_intf(mac); | |
1804 | if (mac->dma_if < 0) { | |
1805 | dev_err(&mac->pdev->dev, "Can't map DMA interface\n"); | |
1806 | err = -ENODEV; | |
1807 | goto out; | |
1808 | } | |
f5cd7872 OJ |
1809 | |
1810 | switch (pdev->device) { | |
1811 | case 0xa005: | |
1812 | mac->type = MAC_TYPE_GMAC; | |
1813 | break; | |
1814 | case 0xa006: | |
1815 | mac->type = MAC_TYPE_XAUI; | |
1816 | break; | |
1817 | default: | |
1818 | err = -ENODEV; | |
1819 | goto out; | |
1820 | } | |
1821 | ||
f5cd7872 OJ |
1822 | dev->open = pasemi_mac_open; |
1823 | dev->stop = pasemi_mac_close; | |
1824 | dev->hard_start_xmit = pasemi_mac_start_tx; | |
f5cd7872 | 1825 | dev->set_multicast_list = pasemi_mac_set_rx_mode; |
5cea73b0 | 1826 | dev->set_mac_address = pasemi_mac_set_mac_addr; |
ef1ea0b4 OJ |
1827 | dev->mtu = PE_DEF_MTU; |
1828 | /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ | |
1829 | mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; | |
6e62040c NC |
1830 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1831 | dev->poll_controller = pasemi_mac_netpoll; | |
1832 | #endif | |
ef1ea0b4 OJ |
1833 | |
1834 | dev->change_mtu = pasemi_mac_change_mtu; | |
e37c772e | 1835 | dev->ethtool_ops = &pasemi_mac_ethtool_ops; |
f5cd7872 | 1836 | |
b6e05a1b OJ |
1837 | if (err) |
1838 | goto out; | |
f5cd7872 | 1839 | |
ceb51361 OJ |
1840 | mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
1841 | ||
bb6e9590 OJ |
1842 | /* Enable most messages by default */ |
1843 | mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1844 | ||
f5cd7872 OJ |
1845 | err = register_netdev(dev); |
1846 | ||
1847 | if (err) { | |
1848 | dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n", | |
1849 | err); | |
1850 | goto out; | |
69c29d89 | 1851 | } else if netif_msg_probe(mac) |
e174961c | 1852 | printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %pM\n", |
f5cd7872 | 1853 | dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI", |
e174961c | 1854 | mac->dma_if, dev->dev_addr); |
f5cd7872 OJ |
1855 | |
1856 | return err; | |
1857 | ||
1858 | out: | |
b6e05a1b OJ |
1859 | if (mac->iob_pdev) |
1860 | pci_dev_put(mac->iob_pdev); | |
1861 | if (mac->dma_pdev) | |
1862 | pci_dev_put(mac->dma_pdev); | |
b6e05a1b | 1863 | |
f5cd7872 OJ |
1864 | free_netdev(dev); |
1865 | out_disable_device: | |
1866 | pci_disable_device(pdev); | |
1867 | return err; | |
1868 | ||
1869 | } | |
1870 | ||
1871 | static void __devexit pasemi_mac_remove(struct pci_dev *pdev) | |
1872 | { | |
1873 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1874 | struct pasemi_mac *mac; | |
1875 | ||
1876 | if (!netdev) | |
1877 | return; | |
1878 | ||
1879 | mac = netdev_priv(netdev); | |
1880 | ||
1881 | unregister_netdev(netdev); | |
1882 | ||
1883 | pci_disable_device(pdev); | |
1884 | pci_dev_put(mac->dma_pdev); | |
1885 | pci_dev_put(mac->iob_pdev); | |
1886 | ||
34c20624 OJ |
1887 | pasemi_dma_free_chan(&mac->tx->chan); |
1888 | pasemi_dma_free_chan(&mac->rx->chan); | |
b6e05a1b | 1889 | |
f5cd7872 OJ |
1890 | pci_set_drvdata(pdev, NULL); |
1891 | free_netdev(netdev); | |
1892 | } | |
1893 | ||
1894 | static struct pci_device_id pasemi_mac_pci_tbl[] = { | |
1895 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) }, | |
1896 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) }, | |
fd178254 | 1897 | { }, |
f5cd7872 OJ |
1898 | }; |
1899 | ||
1900 | MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl); | |
1901 | ||
1902 | static struct pci_driver pasemi_mac_driver = { | |
1903 | .name = "pasemi_mac", | |
1904 | .id_table = pasemi_mac_pci_tbl, | |
1905 | .probe = pasemi_mac_probe, | |
1906 | .remove = __devexit_p(pasemi_mac_remove), | |
1907 | }; | |
1908 | ||
1909 | static void __exit pasemi_mac_cleanup_module(void) | |
1910 | { | |
1911 | pci_unregister_driver(&pasemi_mac_driver); | |
f5cd7872 OJ |
1912 | } |
1913 | ||
1914 | int pasemi_mac_init_module(void) | |
1915 | { | |
34c20624 OJ |
1916 | int err; |
1917 | ||
1918 | err = pasemi_dma_init(); | |
1919 | if (err) | |
1920 | return err; | |
1921 | ||
f5cd7872 OJ |
1922 | return pci_register_driver(&pasemi_mac_driver); |
1923 | } | |
1924 | ||
f5cd7872 OJ |
1925 | module_init(pasemi_mac_init_module); |
1926 | module_exit(pasemi_mac_cleanup_module); |