Commit | Line | Data |
---|---|---|
f5cd7872 OJ |
1 | /* |
2 | * Copyright (C) 2006-2007 PA Semi, Inc | |
3 | * | |
4 | * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/dmaengine.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/netdevice.h> | |
27 | #include <linux/etherdevice.h> | |
28 | #include <asm/dma-mapping.h> | |
29 | #include <linux/in.h> | |
30 | #include <linux/skbuff.h> | |
31 | ||
32 | #include <linux/ip.h> | |
33 | #include <linux/tcp.h> | |
34 | #include <net/checksum.h> | |
28ae79f5 | 35 | #include <linux/inet_lro.h> |
f5cd7872 | 36 | |
771f7404 | 37 | #include <asm/irq.h> |
af289e80 | 38 | #include <asm/firmware.h> |
40afa531 | 39 | #include <asm/pasemi_dma.h> |
771f7404 | 40 | |
f5cd7872 OJ |
41 | #include "pasemi_mac.h" |
42 | ||
8dc121a4 OJ |
43 | /* We have our own align, since ppc64 in general has it at 0 because |
44 | * of design flaws in some of the server bridge chips. However, for | |
45 | * PWRficient doing the unaligned copies is more expensive than doing | |
46 | * unaligned DMA, so make sure the data is aligned instead. | |
47 | */ | |
48 | #define LOCAL_SKB_ALIGN 2 | |
f5cd7872 OJ |
49 | |
50 | /* TODO list | |
51 | * | |
f5cd7872 OJ |
52 | * - Multicast support |
53 | * - Large MTU support | |
7ddeae2c OJ |
54 | * - SW LRO |
55 | * - Multiqueue RX/TX | |
f5cd7872 OJ |
56 | */ |
57 | ||
58 | ||
59 | /* Must be a power of two */ | |
28ae79f5 | 60 | #define RX_RING_SIZE 2048 |
ad5da10a | 61 | #define TX_RING_SIZE 4096 |
f5cd7872 | 62 | |
28ae79f5 OJ |
63 | #define LRO_MAX_AGGR 64 |
64 | ||
ceb51361 OJ |
65 | #define DEFAULT_MSG_ENABLE \ |
66 | (NETIF_MSG_DRV | \ | |
67 | NETIF_MSG_PROBE | \ | |
68 | NETIF_MSG_LINK | \ | |
69 | NETIF_MSG_TIMER | \ | |
70 | NETIF_MSG_IFDOWN | \ | |
71 | NETIF_MSG_IFUP | \ | |
72 | NETIF_MSG_RX_ERR | \ | |
73 | NETIF_MSG_TX_ERR) | |
74 | ||
34c20624 | 75 | #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)]) |
72b05b99 | 76 | #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)]) |
34c20624 | 77 | #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)]) |
72b05b99 OJ |
78 | #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)]) |
79 | #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)]) | |
f5cd7872 | 80 | |
021fa22e OJ |
81 | #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \ |
82 | & ((ring)->size - 1)) | |
83 | #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring)) | |
84 | ||
f5cd7872 OJ |
85 | #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ |
86 | ||
ceb51361 OJ |
87 | MODULE_LICENSE("GPL"); |
88 | MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>"); | |
89 | MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver"); | |
90 | ||
91 | static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */ | |
92 | module_param(debug, int, 0); | |
93 | MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value"); | |
f5cd7872 | 94 | |
af289e80 OJ |
95 | static int translation_enabled(void) |
96 | { | |
97 | #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE) | |
98 | return 1; | |
99 | #else | |
100 | return firmware_has_feature(FW_FEATURE_LPAR); | |
101 | #endif | |
102 | } | |
103 | ||
34c20624 | 104 | static void write_iob_reg(unsigned int reg, unsigned int val) |
a85b9422 | 105 | { |
34c20624 | 106 | pasemi_write_iob_reg(reg, val); |
a85b9422 OJ |
107 | } |
108 | ||
5c15332b | 109 | static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg) |
a85b9422 | 110 | { |
34c20624 | 111 | return pasemi_read_mac_reg(mac->dma_if, reg); |
a85b9422 OJ |
112 | } |
113 | ||
5c15332b | 114 | static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg, |
a85b9422 OJ |
115 | unsigned int val) |
116 | { | |
34c20624 | 117 | pasemi_write_mac_reg(mac->dma_if, reg, val); |
a85b9422 OJ |
118 | } |
119 | ||
34c20624 | 120 | static unsigned int read_dma_reg(unsigned int reg) |
a85b9422 | 121 | { |
34c20624 | 122 | return pasemi_read_dma_reg(reg); |
a85b9422 OJ |
123 | } |
124 | ||
34c20624 | 125 | static void write_dma_reg(unsigned int reg, unsigned int val) |
a85b9422 | 126 | { |
34c20624 | 127 | pasemi_write_dma_reg(reg, val); |
a85b9422 OJ |
128 | } |
129 | ||
5c15332b | 130 | static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
131 | { |
132 | return mac->rx; | |
133 | } | |
134 | ||
5c15332b | 135 | static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
136 | { |
137 | return mac->tx; | |
138 | } | |
139 | ||
5c15332b OJ |
140 | static inline void prefetch_skb(const struct sk_buff *skb) |
141 | { | |
142 | const void *d = skb; | |
143 | ||
144 | prefetch(d); | |
145 | prefetch(d+64); | |
146 | prefetch(d+128); | |
147 | prefetch(d+192); | |
148 | } | |
149 | ||
34c20624 OJ |
150 | static int mac_to_intf(struct pasemi_mac *mac) |
151 | { | |
152 | struct pci_dev *pdev = mac->pdev; | |
153 | u32 tmp; | |
154 | int nintf, off, i, j; | |
155 | int devfn = pdev->devfn; | |
156 | ||
157 | tmp = read_dma_reg(PAS_DMA_CAP_IFI); | |
158 | nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S; | |
159 | off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S; | |
160 | ||
161 | /* IOFF contains the offset to the registers containing the | |
162 | * DMA interface-to-MAC-pci-id mappings, and NIN contains number | |
163 | * of total interfaces. Each register contains 4 devfns. | |
164 | * Just do a linear search until we find the devfn of the MAC | |
165 | * we're trying to look up. | |
166 | */ | |
167 | ||
168 | for (i = 0; i < (nintf+3)/4; i++) { | |
169 | tmp = read_dma_reg(off+4*i); | |
170 | for (j = 0; j < 4; j++) { | |
171 | if (((tmp >> (8*j)) & 0xff) == devfn) | |
172 | return i*4 + j; | |
173 | } | |
174 | } | |
175 | return -1; | |
176 | } | |
177 | ||
f5cd7872 OJ |
178 | static int pasemi_get_mac_addr(struct pasemi_mac *mac) |
179 | { | |
180 | struct pci_dev *pdev = mac->pdev; | |
181 | struct device_node *dn = pci_device_to_OF_node(pdev); | |
1af7f056 | 182 | int len; |
f5cd7872 OJ |
183 | const u8 *maddr; |
184 | u8 addr[6]; | |
185 | ||
186 | if (!dn) { | |
187 | dev_dbg(&pdev->dev, | |
188 | "No device node for mac, not configuring\n"); | |
189 | return -ENOENT; | |
190 | } | |
191 | ||
1af7f056 | 192 | maddr = of_get_property(dn, "local-mac-address", &len); |
193 | ||
194 | if (maddr && len == 6) { | |
195 | memcpy(mac->mac_addr, maddr, 6); | |
196 | return 0; | |
197 | } | |
198 | ||
199 | /* Some old versions of firmware mistakenly uses mac-address | |
200 | * (and as a string) instead of a byte array in local-mac-address. | |
201 | */ | |
a5fd22eb | 202 | |
a5fd22eb | 203 | if (maddr == NULL) |
9028780a | 204 | maddr = of_get_property(dn, "mac-address", NULL); |
a5fd22eb | 205 | |
f5cd7872 OJ |
206 | if (maddr == NULL) { |
207 | dev_warn(&pdev->dev, | |
208 | "no mac address in device tree, not configuring\n"); | |
209 | return -ENOENT; | |
210 | } | |
211 | ||
212 | if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0], | |
213 | &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) { | |
214 | dev_warn(&pdev->dev, | |
215 | "can't parse mac address, not configuring\n"); | |
216 | return -EINVAL; | |
217 | } | |
218 | ||
1af7f056 | 219 | memcpy(mac->mac_addr, addr, 6); |
220 | ||
f5cd7872 OJ |
221 | return 0; |
222 | } | |
223 | ||
5cea73b0 OJ |
224 | static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p) |
225 | { | |
226 | struct pasemi_mac *mac = netdev_priv(dev); | |
227 | struct sockaddr *addr = p; | |
228 | unsigned int adr0, adr1; | |
229 | ||
230 | if (!is_valid_ether_addr(addr->sa_data)) | |
231 | return -EINVAL; | |
232 | ||
233 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
234 | ||
235 | adr0 = dev->dev_addr[2] << 24 | | |
236 | dev->dev_addr[3] << 16 | | |
237 | dev->dev_addr[4] << 8 | | |
238 | dev->dev_addr[5]; | |
239 | adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1); | |
240 | adr1 &= ~0xffff; | |
241 | adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1]; | |
242 | ||
243 | pasemi_mac_intf_disable(mac); | |
244 | write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0); | |
245 | write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1); | |
246 | pasemi_mac_intf_enable(mac); | |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
28ae79f5 OJ |
251 | static int get_skb_hdr(struct sk_buff *skb, void **iphdr, |
252 | void **tcph, u64 *hdr_flags, void *data) | |
253 | { | |
254 | u64 macrx = (u64) data; | |
255 | unsigned int ip_len; | |
256 | struct iphdr *iph; | |
257 | ||
258 | /* IPv4 header checksum failed */ | |
259 | if ((macrx & XCT_MACRX_HTY_M) != XCT_MACRX_HTY_IPV4_OK) | |
260 | return -1; | |
261 | ||
262 | /* non tcp packet */ | |
263 | skb_reset_network_header(skb); | |
264 | iph = ip_hdr(skb); | |
265 | if (iph->protocol != IPPROTO_TCP) | |
266 | return -1; | |
267 | ||
268 | ip_len = ip_hdrlen(skb); | |
269 | skb_set_transport_header(skb, ip_len); | |
270 | *tcph = tcp_hdr(skb); | |
271 | ||
272 | /* check if ip header and tcp header are complete */ | |
273 | if (iph->tot_len < ip_len + tcp_hdrlen(skb)) | |
274 | return -1; | |
275 | ||
276 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
277 | *iphdr = iph; | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
ad3c20d1 | 282 | static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac, |
7e9916e9 | 283 | const int nfrags, |
ad3c20d1 | 284 | struct sk_buff *skb, |
5c15332b | 285 | const dma_addr_t *dmas) |
ad3c20d1 OJ |
286 | { |
287 | int f; | |
5c15332b | 288 | struct pci_dev *pdev = mac->dma_pdev; |
ad3c20d1 | 289 | |
5c15332b | 290 | pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
291 | |
292 | for (f = 0; f < nfrags; f++) { | |
293 | skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; | |
294 | ||
5c15332b | 295 | pci_unmap_page(pdev, dmas[f+1], frag->size, PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
296 | } |
297 | dev_kfree_skb_irq(skb); | |
298 | ||
299 | /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs, | |
300 | * aligned up to a power of 2 | |
301 | */ | |
302 | return (nfrags + 3) & ~1; | |
303 | } | |
304 | ||
5c15332b | 305 | static int pasemi_mac_setup_rx_resources(const struct net_device *dev) |
f5cd7872 OJ |
306 | { |
307 | struct pasemi_mac_rxring *ring; | |
308 | struct pasemi_mac *mac = netdev_priv(dev); | |
34c20624 | 309 | int chno; |
af289e80 | 310 | unsigned int cfg; |
f5cd7872 | 311 | |
34c20624 OJ |
312 | ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring), |
313 | offsetof(struct pasemi_mac_rxring, chan)); | |
f5cd7872 | 314 | |
34c20624 OJ |
315 | if (!ring) { |
316 | dev_err(&mac->pdev->dev, "Can't allocate RX channel\n"); | |
317 | goto out_chan; | |
318 | } | |
319 | chno = ring->chan.chno; | |
f5cd7872 OJ |
320 | |
321 | spin_lock_init(&ring->lock); | |
322 | ||
021fa22e | 323 | ring->size = RX_RING_SIZE; |
fc9e4d2a | 324 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 OJ |
325 | RX_RING_SIZE, GFP_KERNEL); |
326 | ||
fc9e4d2a OJ |
327 | if (!ring->ring_info) |
328 | goto out_ring_info; | |
f5cd7872 OJ |
329 | |
330 | /* Allocate descriptors */ | |
34c20624 | 331 | if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE)) |
fc9e4d2a | 332 | goto out_ring_desc; |
f5cd7872 | 333 | |
f5cd7872 OJ |
334 | ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev, |
335 | RX_RING_SIZE * sizeof(u64), | |
336 | &ring->buf_dma, GFP_KERNEL); | |
337 | if (!ring->buffers) | |
34c20624 | 338 | goto out_ring_desc; |
f5cd7872 OJ |
339 | |
340 | memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64)); | |
341 | ||
34c20624 OJ |
342 | write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno), |
343 | PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
f5cd7872 | 344 | |
34c20624 OJ |
345 | write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno), |
346 | PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) | | |
347 | PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 348 | |
5c15332b | 349 | cfg = PAS_DMA_RXCHAN_CFG_HBU(2); |
af289e80 OJ |
350 | |
351 | if (translation_enabled()) | |
352 | cfg |= PAS_DMA_RXCHAN_CFG_CTR; | |
353 | ||
34c20624 | 354 | write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg); |
f5cd7872 | 355 | |
34c20624 OJ |
356 | write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if), |
357 | PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma)); | |
f5cd7872 | 358 | |
34c20624 OJ |
359 | write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if), |
360 | PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) | | |
361 | PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 362 | |
5c15332b | 363 | cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 | |
af289e80 OJ |
364 | PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP | |
365 | PAS_DMA_RXINT_CFG_HEN; | |
366 | ||
367 | if (translation_enabled()) | |
368 | cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR; | |
369 | ||
34c20624 | 370 | write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg); |
c0efd52b | 371 | |
f5cd7872 OJ |
372 | ring->next_to_fill = 0; |
373 | ring->next_to_clean = 0; | |
72b05b99 | 374 | ring->mac = mac; |
f5cd7872 OJ |
375 | mac->rx = ring; |
376 | ||
377 | return 0; | |
378 | ||
fc9e4d2a OJ |
379 | out_ring_desc: |
380 | kfree(ring->ring_info); | |
381 | out_ring_info: | |
34c20624 OJ |
382 | pasemi_dma_free_chan(&ring->chan); |
383 | out_chan: | |
f5cd7872 OJ |
384 | return -ENOMEM; |
385 | } | |
386 | ||
72b05b99 | 387 | static struct pasemi_mac_txring * |
5c15332b | 388 | pasemi_mac_setup_tx_resources(const struct net_device *dev) |
f5cd7872 OJ |
389 | { |
390 | struct pasemi_mac *mac = netdev_priv(dev); | |
391 | u32 val; | |
f5cd7872 | 392 | struct pasemi_mac_txring *ring; |
af289e80 | 393 | unsigned int cfg; |
34c20624 | 394 | int chno; |
f5cd7872 | 395 | |
34c20624 OJ |
396 | ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring), |
397 | offsetof(struct pasemi_mac_txring, chan)); | |
398 | ||
399 | if (!ring) { | |
400 | dev_err(&mac->pdev->dev, "Can't allocate TX channel\n"); | |
401 | goto out_chan; | |
402 | } | |
403 | ||
404 | chno = ring->chan.chno; | |
f5cd7872 OJ |
405 | |
406 | spin_lock_init(&ring->lock); | |
407 | ||
021fa22e | 408 | ring->size = TX_RING_SIZE; |
fc9e4d2a | 409 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 | 410 | TX_RING_SIZE, GFP_KERNEL); |
fc9e4d2a OJ |
411 | if (!ring->ring_info) |
412 | goto out_ring_info; | |
f5cd7872 OJ |
413 | |
414 | /* Allocate descriptors */ | |
34c20624 | 415 | if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE)) |
fc9e4d2a | 416 | goto out_ring_desc; |
f5cd7872 | 417 | |
34c20624 OJ |
418 | write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), |
419 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
420 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); | |
fc9e4d2a | 421 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3); |
f5cd7872 | 422 | |
34c20624 | 423 | write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); |
f5cd7872 | 424 | |
af289e80 OJ |
425 | cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE | |
426 | PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | | |
427 | PAS_DMA_TXCHAN_CFG_UP | | |
428 | PAS_DMA_TXCHAN_CFG_WT(2); | |
429 | ||
430 | if (translation_enabled()) | |
431 | cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; | |
432 | ||
34c20624 | 433 | write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); |
f5cd7872 | 434 | |
021fa22e | 435 | ring->next_to_fill = 0; |
f5cd7872 | 436 | ring->next_to_clean = 0; |
72b05b99 | 437 | ring->mac = mac; |
f5cd7872 | 438 | |
72b05b99 | 439 | return ring; |
f5cd7872 | 440 | |
fc9e4d2a OJ |
441 | out_ring_desc: |
442 | kfree(ring->ring_info); | |
443 | out_ring_info: | |
34c20624 OJ |
444 | pasemi_dma_free_chan(&ring->chan); |
445 | out_chan: | |
72b05b99 | 446 | return NULL; |
f5cd7872 OJ |
447 | } |
448 | ||
72b05b99 | 449 | static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac) |
f5cd7872 | 450 | { |
72b05b99 | 451 | struct pasemi_mac_txring *txring = tx_ring(mac); |
ad3c20d1 | 452 | unsigned int i, j; |
f5cd7872 | 453 | struct pasemi_mac_buffer *info; |
ad3c20d1 | 454 | dma_addr_t dmas[MAX_SKB_FRAGS+1]; |
7e9916e9 | 455 | int freed, nfrags; |
ad5da10a | 456 | int start, limit; |
fc9e4d2a | 457 | |
72b05b99 OJ |
458 | start = txring->next_to_clean; |
459 | limit = txring->next_to_fill; | |
ad5da10a OJ |
460 | |
461 | /* Compensate for when fill has wrapped and clean has not */ | |
462 | if (start > limit) | |
463 | limit += TX_RING_SIZE; | |
464 | ||
465 | for (i = start; i < limit; i += freed) { | |
72b05b99 | 466 | info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)]; |
fc9e4d2a | 467 | if (info->dma && info->skb) { |
7e9916e9 OJ |
468 | nfrags = skb_shinfo(info->skb)->nr_frags; |
469 | for (j = 0; j <= nfrags; j++) | |
72b05b99 OJ |
470 | dmas[j] = txring->ring_info[(i+1+j) & |
471 | (TX_RING_SIZE-1)].dma; | |
7e9916e9 OJ |
472 | freed = pasemi_mac_unmap_tx_skb(mac, nfrags, |
473 | info->skb, dmas); | |
ad3c20d1 OJ |
474 | } else |
475 | freed = 2; | |
f5cd7872 OJ |
476 | } |
477 | ||
72b05b99 | 478 | kfree(txring->ring_info); |
34c20624 OJ |
479 | pasemi_dma_free_chan(&txring->chan); |
480 | ||
f5cd7872 OJ |
481 | } |
482 | ||
72b05b99 | 483 | static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac) |
f5cd7872 | 484 | { |
72b05b99 | 485 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
f5cd7872 OJ |
486 | unsigned int i; |
487 | struct pasemi_mac_buffer *info; | |
f5cd7872 OJ |
488 | |
489 | for (i = 0; i < RX_RING_SIZE; i++) { | |
72b05b99 | 490 | info = &RX_DESC_INFO(rx, i); |
fc9e4d2a OJ |
491 | if (info->skb && info->dma) { |
492 | pci_unmap_single(mac->dma_pdev, | |
493 | info->dma, | |
494 | info->skb->len, | |
495 | PCI_DMA_FROMDEVICE); | |
496 | dev_kfree_skb_any(info->skb); | |
f5cd7872 | 497 | } |
fc9e4d2a OJ |
498 | info->dma = 0; |
499 | info->skb = NULL; | |
f5cd7872 OJ |
500 | } |
501 | ||
fc9e4d2a | 502 | for (i = 0; i < RX_RING_SIZE; i++) |
72b05b99 | 503 | RX_DESC(rx, i) = 0; |
fc9e4d2a | 504 | |
f5cd7872 | 505 | dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64), |
72b05b99 | 506 | rx_ring(mac)->buffers, rx_ring(mac)->buf_dma); |
f5cd7872 | 507 | |
72b05b99 | 508 | kfree(rx_ring(mac)->ring_info); |
34c20624 | 509 | pasemi_dma_free_chan(&rx_ring(mac)->chan); |
f5cd7872 OJ |
510 | mac->rx = NULL; |
511 | } | |
512 | ||
5c15332b OJ |
513 | static void pasemi_mac_replenish_rx_ring(const struct net_device *dev, |
514 | const int limit) | |
f5cd7872 | 515 | { |
5c15332b | 516 | const struct pasemi_mac *mac = netdev_priv(dev); |
72b05b99 | 517 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
b5254eee | 518 | int fill, count; |
f5cd7872 | 519 | |
cd4ceb24 | 520 | if (limit <= 0) |
f5cd7872 OJ |
521 | return; |
522 | ||
72b05b99 | 523 | fill = rx_ring(mac)->next_to_fill; |
928773c2 | 524 | for (count = 0; count < limit; count++) { |
72b05b99 OJ |
525 | struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill); |
526 | u64 *buff = &RX_BUFF(rx, fill); | |
f5cd7872 OJ |
527 | struct sk_buff *skb; |
528 | dma_addr_t dma; | |
529 | ||
fc9e4d2a OJ |
530 | /* Entry in use? */ |
531 | WARN_ON(*buff); | |
532 | ||
5d894944 OJ |
533 | skb = dev_alloc_skb(BUF_SIZE); |
534 | skb_reserve(skb, LOCAL_SKB_ALIGN); | |
f5cd7872 | 535 | |
9f05cfe2 | 536 | if (unlikely(!skb)) |
f5cd7872 | 537 | break; |
f5cd7872 | 538 | |
8dc121a4 OJ |
539 | dma = pci_map_single(mac->dma_pdev, skb->data, |
540 | BUF_SIZE - LOCAL_SKB_ALIGN, | |
f5cd7872 OJ |
541 | PCI_DMA_FROMDEVICE); |
542 | ||
cd4ceb24 | 543 | if (unlikely(dma_mapping_error(dma))) { |
f5cd7872 | 544 | dev_kfree_skb_irq(info->skb); |
f5cd7872 OJ |
545 | break; |
546 | } | |
547 | ||
548 | info->skb = skb; | |
549 | info->dma = dma; | |
550 | *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma); | |
fc9e4d2a | 551 | fill++; |
f5cd7872 OJ |
552 | } |
553 | ||
554 | wmb(); | |
555 | ||
34c20624 | 556 | write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count); |
f5cd7872 | 557 | |
72b05b99 | 558 | rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) & |
b5254eee | 559 | (RX_RING_SIZE - 1); |
f5cd7872 OJ |
560 | } |
561 | ||
5c15332b | 562 | static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac) |
1b0335ea | 563 | { |
906674ab | 564 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
52a94351 | 565 | unsigned int reg, pcnt; |
1b0335ea OJ |
566 | /* Re-enable packet count interrupts: finally |
567 | * ack the packet count interrupt we got in rx_intr. | |
568 | */ | |
569 | ||
906674ab | 570 | pcnt = *rx->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 571 | |
52a94351 | 572 | reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; |
1b0335ea | 573 | |
906674ab OJ |
574 | if (*rx->chan.status & PAS_STATUS_TIMER) |
575 | reg |= PAS_IOB_DMA_RXCH_RESET_TINTC; | |
576 | ||
34c20624 | 577 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg); |
1b0335ea OJ |
578 | } |
579 | ||
5c15332b | 580 | static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac) |
1b0335ea | 581 | { |
52a94351 | 582 | unsigned int reg, pcnt; |
1b0335ea OJ |
583 | |
584 | /* Re-enable packet count interrupts */ | |
34c20624 | 585 | pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 586 | |
52a94351 | 587 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; |
1b0335ea | 588 | |
34c20624 | 589 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg); |
1b0335ea OJ |
590 | } |
591 | ||
592 | ||
5c15332b OJ |
593 | static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac, |
594 | const u64 macrx) | |
69c29d89 OJ |
595 | { |
596 | unsigned int rcmdsta, ccmdsta; | |
34c20624 | 597 | struct pasemi_dmachan *chan = &rx_ring(mac)->chan; |
69c29d89 OJ |
598 | |
599 | if (!netif_msg_rx_err(mac)) | |
600 | return; | |
601 | ||
34c20624 OJ |
602 | rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
603 | ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno)); | |
69c29d89 OJ |
604 | |
605 | printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n", | |
34c20624 | 606 | macrx, *chan->status); |
69c29d89 OJ |
607 | |
608 | printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n", | |
609 | rcmdsta, ccmdsta); | |
610 | } | |
611 | ||
5c15332b OJ |
612 | static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac, |
613 | const u64 mactx) | |
69c29d89 OJ |
614 | { |
615 | unsigned int cmdsta; | |
34c20624 | 616 | struct pasemi_dmachan *chan = &tx_ring(mac)->chan; |
69c29d89 OJ |
617 | |
618 | if (!netif_msg_tx_err(mac)) | |
619 | return; | |
620 | ||
34c20624 | 621 | cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno)); |
69c29d89 OJ |
622 | |
623 | printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\ | |
34c20624 | 624 | "tx status 0x%016lx\n", mactx, *chan->status); |
69c29d89 OJ |
625 | |
626 | printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta); | |
627 | } | |
628 | ||
5c15332b OJ |
629 | static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx, |
630 | const int limit) | |
f5cd7872 | 631 | { |
5c15332b | 632 | const struct pasemi_dmachan *chan = &rx->chan; |
72b05b99 | 633 | struct pasemi_mac *mac = rx->mac; |
5c15332b | 634 | struct pci_dev *pdev = mac->dma_pdev; |
cd4ceb24 | 635 | unsigned int n; |
5c15332b | 636 | int count, buf_index, tot_bytes, packets; |
cd4ceb24 OJ |
637 | struct pasemi_mac_buffer *info; |
638 | struct sk_buff *skb; | |
b5254eee | 639 | unsigned int len; |
5c15332b | 640 | u64 macrx, eval; |
cd4ceb24 | 641 | dma_addr_t dma; |
5c15332b OJ |
642 | |
643 | tot_bytes = 0; | |
644 | packets = 0; | |
f5cd7872 | 645 | |
72b05b99 | 646 | spin_lock(&rx->lock); |
f5cd7872 | 647 | |
72b05b99 | 648 | n = rx->next_to_clean; |
f5cd7872 | 649 | |
72b05b99 | 650 | prefetch(&RX_DESC(rx, n)); |
b5254eee OJ |
651 | |
652 | for (count = 0; count < limit; count++) { | |
72b05b99 | 653 | macrx = RX_DESC(rx, n); |
5c15332b | 654 | prefetch(&RX_DESC(rx, n+4)); |
f5cd7872 | 655 | |
69c29d89 | 656 | if ((macrx & XCT_MACRX_E) || |
34c20624 | 657 | (*chan->status & PAS_STATUS_ERROR)) |
69c29d89 OJ |
658 | pasemi_mac_rx_error(mac, macrx); |
659 | ||
cd4ceb24 | 660 | if (!(macrx & XCT_MACRX_O)) |
f5cd7872 OJ |
661 | break; |
662 | ||
f5cd7872 OJ |
663 | info = NULL; |
664 | ||
b5254eee | 665 | BUG_ON(!(macrx & XCT_MACRX_RR_8BRES)); |
f5cd7872 | 666 | |
72b05b99 | 667 | eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >> |
b5254eee OJ |
668 | XCT_RXRES_8B_EVAL_S; |
669 | buf_index = eval-1; | |
670 | ||
72b05b99 OJ |
671 | dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M); |
672 | info = &RX_DESC_INFO(rx, buf_index); | |
fc9e4d2a | 673 | |
9f05cfe2 | 674 | skb = info->skb; |
f5cd7872 | 675 | |
5c15332b | 676 | prefetch_skb(skb); |
f5cd7872 | 677 | |
cd4ceb24 | 678 | len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S; |
f5cd7872 | 679 | |
5c15332b OJ |
680 | pci_unmap_single(pdev, dma, BUF_SIZE-LOCAL_SKB_ALIGN, |
681 | PCI_DMA_FROMDEVICE); | |
32bee776 OJ |
682 | |
683 | if (macrx & XCT_MACRX_CRC) { | |
684 | /* CRC error flagged */ | |
685 | mac->netdev->stats.rx_errors++; | |
686 | mac->netdev->stats.rx_crc_errors++; | |
4352d826 | 687 | /* No need to free skb, it'll be reused */ |
32bee776 OJ |
688 | goto next; |
689 | } | |
690 | ||
5d894944 | 691 | info->skb = NULL; |
ad5da10a | 692 | info->dma = 0; |
fc9e4d2a | 693 | |
26fcfa95 | 694 | if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) { |
38bf3184 | 695 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
cd4ceb24 | 696 | skb->csum = (macrx & XCT_MACRX_CSUM_M) >> |
f5cd7872 OJ |
697 | XCT_MACRX_CSUM_S; |
698 | } else | |
699 | skb->ip_summed = CHECKSUM_NONE; | |
700 | ||
5c15332b OJ |
701 | packets++; |
702 | tot_bytes += len; | |
703 | ||
704 | /* Don't include CRC */ | |
705 | skb_put(skb, len-4); | |
f5cd7872 | 706 | |
26fcfa95 | 707 | skb->protocol = eth_type_trans(skb, mac->netdev); |
28ae79f5 | 708 | lro_receive_skb(&mac->lro_mgr, skb, (void *)macrx); |
f5cd7872 | 709 | |
32bee776 | 710 | next: |
72b05b99 OJ |
711 | RX_DESC(rx, n) = 0; |
712 | RX_DESC(rx, n+1) = 0; | |
cd4ceb24 | 713 | |
ad5da10a OJ |
714 | /* Need to zero it out since hardware doesn't, since the |
715 | * replenish loop uses it to tell when it's done. | |
716 | */ | |
72b05b99 | 717 | RX_BUFF(rx, buf_index) = 0; |
ad5da10a | 718 | |
b5254eee | 719 | n += 4; |
f5cd7872 OJ |
720 | } |
721 | ||
9a50bebd OJ |
722 | if (n > RX_RING_SIZE) { |
723 | /* Errata 5971 workaround: L2 target of headers */ | |
34c20624 | 724 | write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0); |
9a50bebd OJ |
725 | n &= (RX_RING_SIZE-1); |
726 | } | |
b5254eee | 727 | |
72b05b99 | 728 | rx_ring(mac)->next_to_clean = n; |
b5254eee | 729 | |
28ae79f5 OJ |
730 | lro_flush_all(&mac->lro_mgr); |
731 | ||
b5254eee OJ |
732 | /* Increase is in number of 16-byte entries, and since each descriptor |
733 | * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with | |
734 | * count*2. | |
735 | */ | |
34c20624 | 736 | write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1); |
b5254eee OJ |
737 | |
738 | pasemi_mac_replenish_rx_ring(mac->netdev, count); | |
f5cd7872 | 739 | |
5c15332b OJ |
740 | mac->netdev->stats.rx_bytes += tot_bytes; |
741 | mac->netdev->stats.rx_packets += packets; | |
742 | ||
72b05b99 | 743 | spin_unlock(&rx_ring(mac)->lock); |
f5cd7872 OJ |
744 | |
745 | return count; | |
746 | } | |
747 | ||
ad3c20d1 OJ |
748 | /* Can't make this too large or we blow the kernel stack limits */ |
749 | #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS) | |
750 | ||
72b05b99 | 751 | static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring) |
f5cd7872 | 752 | { |
34c20624 | 753 | struct pasemi_dmachan *chan = &txring->chan; |
72b05b99 | 754 | struct pasemi_mac *mac = txring->mac; |
ad3c20d1 | 755 | int i, j; |
ad5da10a OJ |
756 | unsigned int start, descr_count, buf_count, batch_limit; |
757 | unsigned int ring_limit; | |
02df6cfa | 758 | unsigned int total_count; |
ca7e235f | 759 | unsigned long flags; |
ad3c20d1 OJ |
760 | struct sk_buff *skbs[TX_CLEAN_BATCHSIZE]; |
761 | dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1]; | |
7e9916e9 OJ |
762 | int nf[TX_CLEAN_BATCHSIZE]; |
763 | int nr_frags; | |
f5cd7872 | 764 | |
02df6cfa | 765 | total_count = 0; |
ad5da10a | 766 | batch_limit = TX_CLEAN_BATCHSIZE; |
02df6cfa | 767 | restart: |
72b05b99 | 768 | spin_lock_irqsave(&txring->lock, flags); |
f5cd7872 | 769 | |
72b05b99 OJ |
770 | start = txring->next_to_clean; |
771 | ring_limit = txring->next_to_fill; | |
ad5da10a | 772 | |
7e9916e9 OJ |
773 | prefetch(&TX_DESC_INFO(txring, start+1).skb); |
774 | ||
ad5da10a OJ |
775 | /* Compensate for when fill has wrapped but clean has not */ |
776 | if (start > ring_limit) | |
777 | ring_limit += TX_RING_SIZE; | |
02df6cfa | 778 | |
ad3c20d1 OJ |
779 | buf_count = 0; |
780 | descr_count = 0; | |
f5cd7872 | 781 | |
ad3c20d1 | 782 | for (i = start; |
ad5da10a | 783 | descr_count < batch_limit && i < ring_limit; |
ad3c20d1 | 784 | i += buf_count) { |
72b05b99 | 785 | u64 mactx = TX_DESC(txring, i); |
ad5da10a | 786 | struct sk_buff *skb; |
ad3c20d1 | 787 | |
7e9916e9 OJ |
788 | skb = TX_DESC_INFO(txring, i+1).skb; |
789 | nr_frags = TX_DESC_INFO(txring, i).dma; | |
790 | ||
fc9e4d2a | 791 | if ((mactx & XCT_MACTX_E) || |
34c20624 | 792 | (*chan->status & PAS_STATUS_ERROR)) |
fc9e4d2a | 793 | pasemi_mac_tx_error(mac, mactx); |
69c29d89 | 794 | |
fc9e4d2a | 795 | if (unlikely(mactx & XCT_MACTX_O)) |
02df6cfa | 796 | /* Not yet transmitted */ |
f5cd7872 OJ |
797 | break; |
798 | ||
7e9916e9 OJ |
799 | buf_count = 2 + nr_frags; |
800 | /* Since we always fill with an even number of entries, make | |
801 | * sure we skip any unused one at the end as well. | |
802 | */ | |
803 | if (buf_count & 1) | |
804 | buf_count++; | |
ad3c20d1 | 805 | |
7e9916e9 | 806 | for (j = 0; j <= nr_frags; j++) |
72b05b99 | 807 | dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma; |
ad3c20d1 | 808 | |
7e9916e9 OJ |
809 | skbs[descr_count] = skb; |
810 | nf[descr_count] = nr_frags; | |
811 | ||
72b05b99 OJ |
812 | TX_DESC(txring, i) = 0; |
813 | TX_DESC(txring, i+1) = 0; | |
fc9e4d2a | 814 | |
ad3c20d1 | 815 | descr_count++; |
f5cd7872 | 816 | } |
72b05b99 | 817 | txring->next_to_clean = i & (TX_RING_SIZE-1); |
ad3c20d1 | 818 | |
72b05b99 | 819 | spin_unlock_irqrestore(&txring->lock, flags); |
0ce68c74 OJ |
820 | netif_wake_queue(mac->netdev); |
821 | ||
ad3c20d1 | 822 | for (i = 0; i < descr_count; i++) |
7e9916e9 | 823 | pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]); |
02df6cfa | 824 | |
ad3c20d1 | 825 | total_count += descr_count; |
02df6cfa OJ |
826 | |
827 | /* If the batch was full, try to clean more */ | |
ad5da10a | 828 | if (descr_count == batch_limit) |
02df6cfa OJ |
829 | goto restart; |
830 | ||
831 | return total_count; | |
f5cd7872 OJ |
832 | } |
833 | ||
834 | ||
835 | static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) | |
836 | { | |
5c15332b | 837 | const struct pasemi_mac_rxring *rxring = data; |
34c20624 OJ |
838 | struct pasemi_mac *mac = rxring->mac; |
839 | struct net_device *dev = mac->netdev; | |
5c15332b | 840 | const struct pasemi_dmachan *chan = &rxring->chan; |
f5cd7872 OJ |
841 | unsigned int reg; |
842 | ||
34c20624 | 843 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
844 | return IRQ_NONE; |
845 | ||
6dfa7522 OJ |
846 | /* Don't reset packet count so it won't fire again but clear |
847 | * all others. | |
848 | */ | |
849 | ||
6dfa7522 | 850 | reg = 0; |
34c20624 | 851 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 852 | reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; |
34c20624 | 853 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 854 | reg |= PAS_IOB_DMA_RXCH_RESET_DINTC; |
f5cd7872 | 855 | |
bea3348e | 856 | netif_rx_schedule(dev, &mac->napi); |
6dfa7522 | 857 | |
34c20624 | 858 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg); |
f5cd7872 OJ |
859 | |
860 | return IRQ_HANDLED; | |
861 | } | |
862 | ||
61cec3bd OJ |
863 | #define TX_CLEAN_INTERVAL HZ |
864 | ||
865 | static void pasemi_mac_tx_timer(unsigned long data) | |
866 | { | |
867 | struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data; | |
868 | struct pasemi_mac *mac = txring->mac; | |
869 | ||
870 | pasemi_mac_clean_tx(txring); | |
871 | ||
872 | mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL); | |
873 | ||
874 | pasemi_mac_restart_tx_intr(mac); | |
875 | } | |
876 | ||
f5cd7872 OJ |
877 | static irqreturn_t pasemi_mac_tx_intr(int irq, void *data) |
878 | { | |
72b05b99 | 879 | struct pasemi_mac_txring *txring = data; |
5c15332b | 880 | const struct pasemi_dmachan *chan = &txring->chan; |
61cec3bd OJ |
881 | struct pasemi_mac *mac = txring->mac; |
882 | unsigned int reg; | |
f5cd7872 | 883 | |
34c20624 | 884 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
885 | return IRQ_NONE; |
886 | ||
61cec3bd | 887 | reg = 0; |
6dfa7522 | 888 | |
34c20624 | 889 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 890 | reg |= PAS_IOB_DMA_TXCH_RESET_SINTC; |
34c20624 | 891 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 892 | reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; |
f5cd7872 | 893 | |
61cec3bd OJ |
894 | mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2); |
895 | ||
896 | netif_rx_schedule(mac->netdev, &mac->napi); | |
897 | ||
898 | if (reg) | |
899 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg); | |
f5cd7872 | 900 | |
f5cd7872 OJ |
901 | return IRQ_HANDLED; |
902 | } | |
903 | ||
b0cd2f90 OJ |
904 | static void pasemi_mac_intf_disable(struct pasemi_mac *mac) |
905 | { | |
906 | unsigned int flags; | |
907 | ||
908 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); | |
909 | flags &= ~PAS_MAC_CFG_PCFG_PE; | |
910 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
911 | } | |
912 | ||
913 | static void pasemi_mac_intf_enable(struct pasemi_mac *mac) | |
914 | { | |
915 | unsigned int flags; | |
916 | ||
917 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); | |
918 | flags |= PAS_MAC_CFG_PCFG_PE; | |
919 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
920 | } | |
921 | ||
bb6e9590 OJ |
922 | static void pasemi_adjust_link(struct net_device *dev) |
923 | { | |
924 | struct pasemi_mac *mac = netdev_priv(dev); | |
925 | int msg; | |
926 | unsigned int flags; | |
927 | unsigned int new_flags; | |
928 | ||
929 | if (!mac->phydev->link) { | |
930 | /* If no link, MAC speed settings don't matter. Just report | |
931 | * link down and return. | |
932 | */ | |
933 | if (mac->link && netif_msg_link(mac)) | |
934 | printk(KERN_INFO "%s: Link is down.\n", dev->name); | |
935 | ||
936 | netif_carrier_off(dev); | |
b0cd2f90 | 937 | pasemi_mac_intf_disable(mac); |
bb6e9590 OJ |
938 | mac->link = 0; |
939 | ||
940 | return; | |
b0cd2f90 OJ |
941 | } else { |
942 | pasemi_mac_intf_enable(mac); | |
bb6e9590 | 943 | netif_carrier_on(dev); |
b0cd2f90 | 944 | } |
bb6e9590 | 945 | |
a85b9422 | 946 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
bb6e9590 OJ |
947 | new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | |
948 | PAS_MAC_CFG_PCFG_TSR_M); | |
949 | ||
950 | if (!mac->phydev->duplex) | |
951 | new_flags |= PAS_MAC_CFG_PCFG_HD; | |
952 | ||
953 | switch (mac->phydev->speed) { | |
954 | case 1000: | |
955 | new_flags |= PAS_MAC_CFG_PCFG_SPD_1G | | |
956 | PAS_MAC_CFG_PCFG_TSR_1G; | |
957 | break; | |
958 | case 100: | |
959 | new_flags |= PAS_MAC_CFG_PCFG_SPD_100M | | |
960 | PAS_MAC_CFG_PCFG_TSR_100M; | |
961 | break; | |
962 | case 10: | |
963 | new_flags |= PAS_MAC_CFG_PCFG_SPD_10M | | |
964 | PAS_MAC_CFG_PCFG_TSR_10M; | |
965 | break; | |
966 | default: | |
967 | printk("Unsupported speed %d\n", mac->phydev->speed); | |
968 | } | |
969 | ||
970 | /* Print on link or speed/duplex change */ | |
971 | msg = mac->link != mac->phydev->link || flags != new_flags; | |
972 | ||
973 | mac->duplex = mac->phydev->duplex; | |
974 | mac->speed = mac->phydev->speed; | |
975 | mac->link = mac->phydev->link; | |
976 | ||
977 | if (new_flags != flags) | |
a85b9422 | 978 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags); |
bb6e9590 OJ |
979 | |
980 | if (msg && netif_msg_link(mac)) | |
981 | printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", | |
982 | dev->name, mac->speed, mac->duplex ? "full" : "half"); | |
983 | } | |
984 | ||
985 | static int pasemi_mac_phy_init(struct net_device *dev) | |
986 | { | |
987 | struct pasemi_mac *mac = netdev_priv(dev); | |
988 | struct device_node *dn, *phy_dn; | |
989 | struct phy_device *phydev; | |
990 | unsigned int phy_id; | |
991 | const phandle *ph; | |
992 | const unsigned int *prop; | |
993 | struct resource r; | |
994 | int ret; | |
995 | ||
996 | dn = pci_device_to_OF_node(mac->pdev); | |
9028780a | 997 | ph = of_get_property(dn, "phy-handle", NULL); |
bb6e9590 OJ |
998 | if (!ph) |
999 | return -ENODEV; | |
1000 | phy_dn = of_find_node_by_phandle(*ph); | |
1001 | ||
9028780a | 1002 | prop = of_get_property(phy_dn, "reg", NULL); |
bb6e9590 OJ |
1003 | ret = of_address_to_resource(phy_dn->parent, 0, &r); |
1004 | if (ret) | |
1005 | goto err; | |
1006 | ||
1007 | phy_id = *prop; | |
1008 | snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id); | |
1009 | ||
1010 | of_node_put(phy_dn); | |
1011 | ||
1012 | mac->link = 0; | |
1013 | mac->speed = 0; | |
1014 | mac->duplex = -1; | |
1015 | ||
1016 | phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII); | |
1017 | ||
1018 | if (IS_ERR(phydev)) { | |
1019 | printk(KERN_ERR "%s: Could not attach to phy\n", dev->name); | |
1020 | return PTR_ERR(phydev); | |
1021 | } | |
1022 | ||
1023 | mac->phydev = phydev; | |
1024 | ||
1025 | return 0; | |
1026 | ||
1027 | err: | |
1028 | of_node_put(phy_dn); | |
1029 | return -ENODEV; | |
1030 | } | |
1031 | ||
1032 | ||
f5cd7872 OJ |
1033 | static int pasemi_mac_open(struct net_device *dev) |
1034 | { | |
1035 | struct pasemi_mac *mac = netdev_priv(dev); | |
1036 | unsigned int flags; | |
1037 | int ret; | |
1038 | ||
1039 | /* enable rx section */ | |
34c20624 | 1040 | write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN); |
f5cd7872 OJ |
1041 | |
1042 | /* enable tx section */ | |
34c20624 | 1043 | write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); |
f5cd7872 OJ |
1044 | |
1045 | flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | | |
1046 | PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | | |
1047 | PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); | |
1048 | ||
a85b9422 | 1049 | write_mac_reg(mac, PAS_MAC_CFG_TXP, flags); |
f5cd7872 | 1050 | |
f5cd7872 OJ |
1051 | ret = pasemi_mac_setup_rx_resources(dev); |
1052 | if (ret) | |
1053 | goto out_rx_resources; | |
1054 | ||
34c20624 | 1055 | mac->tx = pasemi_mac_setup_tx_resources(dev); |
72b05b99 OJ |
1056 | |
1057 | if (!mac->tx) | |
1058 | goto out_tx_ring; | |
f5cd7872 | 1059 | |
906674ab OJ |
1060 | /* 0x3ff with 33MHz clock is about 31us */ |
1061 | write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG, | |
1062 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff)); | |
1063 | ||
34c20624 | 1064 | write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno), |
28ae79f5 | 1065 | PAS_IOB_DMA_RXCH_CFG_CNTTH(256)); |
34c20624 OJ |
1066 | |
1067 | write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno), | |
61cec3bd | 1068 | PAS_IOB_DMA_TXCH_CFG_CNTTH(32)); |
34c20624 | 1069 | |
a85b9422 | 1070 | write_mac_reg(mac, PAS_MAC_IPC_CHNL, |
34c20624 OJ |
1071 | PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) | |
1072 | PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno)); | |
f5cd7872 OJ |
1073 | |
1074 | /* enable rx if */ | |
34c20624 OJ |
1075 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), |
1076 | PAS_DMA_RXINT_RCMDSTA_EN | | |
1077 | PAS_DMA_RXINT_RCMDSTA_DROPS_M | | |
1078 | PAS_DMA_RXINT_RCMDSTA_BP | | |
1079 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1080 | PAS_DMA_RXINT_RCMDSTA_BT); | |
f5cd7872 OJ |
1081 | |
1082 | /* enable rx channel */ | |
34c20624 OJ |
1083 | pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU | |
1084 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1085 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1086 | PAS_DMA_RXCHAN_CCMDSTA_DT); | |
f5cd7872 OJ |
1087 | |
1088 | /* enable tx channel */ | |
34c20624 OJ |
1089 | pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | |
1090 | PAS_DMA_TXCHAN_TCMDSTA_DB | | |
1091 | PAS_DMA_TXCHAN_TCMDSTA_DE | | |
1092 | PAS_DMA_TXCHAN_TCMDSTA_DA); | |
f5cd7872 | 1093 | |
928773c2 | 1094 | pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE); |
f5cd7872 | 1095 | |
34c20624 OJ |
1096 | write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno), |
1097 | RX_RING_SIZE>>1); | |
b5254eee | 1098 | |
72b05b99 OJ |
1099 | /* Clear out any residual packet count state from firmware */ |
1100 | pasemi_mac_restart_rx_intr(mac); | |
1101 | pasemi_mac_restart_tx_intr(mac); | |
1102 | ||
b0cd2f90 | 1103 | flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; |
36033766 OJ |
1104 | |
1105 | if (mac->type == MAC_TYPE_GMAC) | |
1106 | flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; | |
1107 | else | |
1108 | flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G; | |
1109 | ||
1110 | /* Enable interface in MAC */ | |
1111 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
1112 | ||
bb6e9590 | 1113 | ret = pasemi_mac_phy_init(dev); |
b0cd2f90 OJ |
1114 | if (ret) { |
1115 | /* Since we won't get link notification, just enable RX */ | |
1116 | pasemi_mac_intf_enable(mac); | |
1117 | if (mac->type == MAC_TYPE_GMAC) { | |
1118 | /* Warn for missing PHY on SGMII (1Gig) ports */ | |
1119 | dev_warn(&mac->pdev->dev, | |
1120 | "PHY init failed: %d.\n", ret); | |
1121 | dev_warn(&mac->pdev->dev, | |
1122 | "Defaulting to 1Gbit full duplex\n"); | |
1123 | } | |
8304b633 | 1124 | } |
bb6e9590 | 1125 | |
f5cd7872 | 1126 | netif_start_queue(dev); |
bea3348e | 1127 | napi_enable(&mac->napi); |
f5cd7872 | 1128 | |
72b05b99 OJ |
1129 | snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx", |
1130 | dev->name); | |
771f7404 | 1131 | |
34c20624 | 1132 | ret = request_irq(mac->tx->chan.irq, &pasemi_mac_tx_intr, IRQF_DISABLED, |
72b05b99 | 1133 | mac->tx_irq_name, mac->tx); |
f5cd7872 OJ |
1134 | if (ret) { |
1135 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1136 | mac->tx->chan.irq, ret); |
f5cd7872 OJ |
1137 | goto out_tx_int; |
1138 | } | |
1139 | ||
72b05b99 OJ |
1140 | snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx", |
1141 | dev->name); | |
1142 | ||
34c20624 OJ |
1143 | ret = request_irq(mac->rx->chan.irq, &pasemi_mac_rx_intr, IRQF_DISABLED, |
1144 | mac->rx_irq_name, mac->rx); | |
f5cd7872 OJ |
1145 | if (ret) { |
1146 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1147 | mac->rx->chan.irq, ret); |
f5cd7872 OJ |
1148 | goto out_rx_int; |
1149 | } | |
1150 | ||
bb6e9590 OJ |
1151 | if (mac->phydev) |
1152 | phy_start(mac->phydev); | |
1153 | ||
61cec3bd OJ |
1154 | init_timer(&mac->tx->clean_timer); |
1155 | mac->tx->clean_timer.function = pasemi_mac_tx_timer; | |
1156 | mac->tx->clean_timer.data = (unsigned long)mac->tx; | |
1157 | mac->tx->clean_timer.expires = jiffies+HZ; | |
1158 | add_timer(&mac->tx->clean_timer); | |
1159 | ||
f5cd7872 OJ |
1160 | return 0; |
1161 | ||
1162 | out_rx_int: | |
34c20624 | 1163 | free_irq(mac->tx->chan.irq, mac->tx); |
f5cd7872 | 1164 | out_tx_int: |
bea3348e | 1165 | napi_disable(&mac->napi); |
f5cd7872 | 1166 | netif_stop_queue(dev); |
72b05b99 OJ |
1167 | out_tx_ring: |
1168 | if (mac->tx) | |
1169 | pasemi_mac_free_tx_resources(mac); | |
1170 | pasemi_mac_free_rx_resources(mac); | |
f5cd7872 OJ |
1171 | out_rx_resources: |
1172 | ||
1173 | return ret; | |
1174 | } | |
1175 | ||
1176 | #define MAX_RETRIES 5000 | |
1177 | ||
1178 | static int pasemi_mac_close(struct net_device *dev) | |
1179 | { | |
1180 | struct pasemi_mac *mac = netdev_priv(dev); | |
9e81d331 | 1181 | unsigned int sta; |
f5cd7872 | 1182 | int retries; |
34c20624 OJ |
1183 | int rxch, txch; |
1184 | ||
1185 | rxch = rx_ring(mac)->chan.chno; | |
1186 | txch = tx_ring(mac)->chan.chno; | |
f5cd7872 | 1187 | |
bb6e9590 OJ |
1188 | if (mac->phydev) { |
1189 | phy_stop(mac->phydev); | |
1190 | phy_disconnect(mac->phydev); | |
1191 | } | |
1192 | ||
61cec3bd OJ |
1193 | del_timer_sync(&mac->tx->clean_timer); |
1194 | ||
f5cd7872 | 1195 | netif_stop_queue(dev); |
bea3348e | 1196 | napi_disable(&mac->napi); |
f5cd7872 | 1197 | |
34c20624 | 1198 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
9e81d331 OJ |
1199 | if (sta & (PAS_DMA_RXINT_RCMDSTA_BP | |
1200 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1201 | PAS_DMA_RXINT_RCMDSTA_BT)) | |
1202 | printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta); | |
1203 | ||
34c20624 | 1204 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); |
9e81d331 OJ |
1205 | if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU | |
1206 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1207 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1208 | PAS_DMA_RXCHAN_CCMDSTA_DT)) | |
1209 | printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta); | |
1210 | ||
34c20624 | 1211 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); |
72b05b99 OJ |
1212 | if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB | |
1213 | PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA)) | |
9e81d331 OJ |
1214 | printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta); |
1215 | ||
f5cd7872 | 1216 | /* Clean out any pending buffers */ |
72b05b99 OJ |
1217 | pasemi_mac_clean_tx(tx_ring(mac)); |
1218 | pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); | |
f5cd7872 OJ |
1219 | |
1220 | /* Disable interface */ | |
34c20624 | 1221 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), |
72b05b99 | 1222 | PAS_DMA_TXCHAN_TCMDSTA_ST); |
34c20624 | 1223 | write_dma_reg( PAS_DMA_RXINT_RCMDSTA(mac->dma_if), |
72b05b99 | 1224 | PAS_DMA_RXINT_RCMDSTA_ST); |
34c20624 | 1225 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), |
72b05b99 | 1226 | PAS_DMA_RXCHAN_CCMDSTA_ST); |
f5cd7872 OJ |
1227 | |
1228 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
34c20624 | 1229 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(rxch)); |
9e81d331 | 1230 | if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) |
f5cd7872 OJ |
1231 | break; |
1232 | cond_resched(); | |
1233 | } | |
1234 | ||
9e81d331 | 1235 | if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT) |
34c20624 | 1236 | dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n"); |
f5cd7872 OJ |
1237 | |
1238 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
34c20624 | 1239 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); |
9e81d331 | 1240 | if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) |
f5cd7872 OJ |
1241 | break; |
1242 | cond_resched(); | |
1243 | } | |
1244 | ||
9e81d331 | 1245 | if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT) |
f5cd7872 | 1246 | dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n"); |
f5cd7872 OJ |
1247 | |
1248 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
34c20624 | 1249 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
9e81d331 | 1250 | if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT)) |
f5cd7872 OJ |
1251 | break; |
1252 | cond_resched(); | |
1253 | } | |
1254 | ||
9e81d331 | 1255 | if (sta & PAS_DMA_RXINT_RCMDSTA_ACT) |
f5cd7872 | 1256 | dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n"); |
f5cd7872 OJ |
1257 | |
1258 | /* Then, disable the channel. This must be done separately from | |
1259 | * stopping, since you can't disable when active. | |
1260 | */ | |
1261 | ||
34c20624 OJ |
1262 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0); |
1263 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0); | |
1264 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); | |
f5cd7872 | 1265 | |
34c20624 OJ |
1266 | free_irq(mac->tx->chan.irq, mac->tx); |
1267 | free_irq(mac->rx->chan.irq, mac->rx); | |
f5cd7872 OJ |
1268 | |
1269 | /* Free resources */ | |
72b05b99 OJ |
1270 | pasemi_mac_free_rx_resources(mac); |
1271 | pasemi_mac_free_tx_resources(mac); | |
f5cd7872 OJ |
1272 | |
1273 | return 0; | |
1274 | } | |
1275 | ||
1276 | static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) | |
1277 | { | |
1278 | struct pasemi_mac *mac = netdev_priv(dev); | |
1279 | struct pasemi_mac_txring *txring; | |
ad3c20d1 OJ |
1280 | u64 dflags, mactx; |
1281 | dma_addr_t map[MAX_SKB_FRAGS+1]; | |
1282 | unsigned int map_size[MAX_SKB_FRAGS+1]; | |
ca7e235f | 1283 | unsigned long flags; |
ad3c20d1 | 1284 | int i, nfrags; |
5c15332b | 1285 | int fill; |
f5cd7872 | 1286 | |
dbd62af7 | 1287 | dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD; |
f5cd7872 OJ |
1288 | |
1289 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
d56f90a7 ACM |
1290 | const unsigned char *nh = skb_network_header(skb); |
1291 | ||
eddc9ec5 | 1292 | switch (ip_hdr(skb)->protocol) { |
f5cd7872 OJ |
1293 | case IPPROTO_TCP: |
1294 | dflags |= XCT_MACTX_CSUM_TCP; | |
cfe1fc77 | 1295 | dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2); |
d56f90a7 | 1296 | dflags |= XCT_MACTX_IPO(nh - skb->data); |
f5cd7872 OJ |
1297 | break; |
1298 | case IPPROTO_UDP: | |
1299 | dflags |= XCT_MACTX_CSUM_UDP; | |
cfe1fc77 | 1300 | dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2); |
d56f90a7 | 1301 | dflags |= XCT_MACTX_IPO(nh - skb->data); |
f5cd7872 OJ |
1302 | break; |
1303 | } | |
1304 | } | |
1305 | ||
ad3c20d1 OJ |
1306 | nfrags = skb_shinfo(skb)->nr_frags; |
1307 | ||
1308 | map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb), | |
1309 | PCI_DMA_TODEVICE); | |
1310 | map_size[0] = skb_headlen(skb); | |
1311 | if (dma_mapping_error(map[0])) | |
1312 | goto out_err_nolock; | |
1313 | ||
1314 | for (i = 0; i < nfrags; i++) { | |
1315 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
f5cd7872 | 1316 | |
ad3c20d1 OJ |
1317 | map[i+1] = pci_map_page(mac->dma_pdev, frag->page, |
1318 | frag->page_offset, frag->size, | |
1319 | PCI_DMA_TODEVICE); | |
1320 | map_size[i+1] = frag->size; | |
1321 | if (dma_mapping_error(map[i+1])) { | |
1322 | nfrags = i; | |
1323 | goto out_err_nolock; | |
1324 | } | |
1325 | } | |
f5cd7872 | 1326 | |
26fcfa95 | 1327 | mactx = dflags | XCT_MACTX_LLEN(skb->len); |
26fcfa95 | 1328 | |
72b05b99 | 1329 | txring = tx_ring(mac); |
f5cd7872 OJ |
1330 | |
1331 | spin_lock_irqsave(&txring->lock, flags); | |
1332 | ||
5c15332b OJ |
1333 | fill = txring->next_to_fill; |
1334 | ||
ad5da10a OJ |
1335 | /* Avoid stepping on the same cache line that the DMA controller |
1336 | * is currently about to send, so leave at least 8 words available. | |
1337 | * Total free space needed is mactx + fragments + 8 | |
1338 | */ | |
1339 | if (RING_AVAIL(txring) < nfrags + 10) { | |
1340 | /* no room -- stop the queue and wait for tx intr */ | |
1341 | netif_stop_queue(dev); | |
1342 | goto out_err; | |
f5cd7872 OJ |
1343 | } |
1344 | ||
5c15332b | 1345 | TX_DESC(txring, fill) = mactx; |
7e9916e9 | 1346 | TX_DESC_INFO(txring, fill).dma = nfrags; |
5c15332b OJ |
1347 | fill++; |
1348 | TX_DESC_INFO(txring, fill).skb = skb; | |
ad3c20d1 | 1349 | for (i = 0; i <= nfrags; i++) { |
5c15332b | 1350 | TX_DESC(txring, fill+i) = |
72b05b99 | 1351 | XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); |
5c15332b | 1352 | TX_DESC_INFO(txring, fill+i).dma = map[i]; |
ad3c20d1 OJ |
1353 | } |
1354 | ||
1355 | /* We have to add an even number of 8-byte entries to the ring | |
1356 | * even if the last one is unused. That means always an odd number | |
1357 | * of pointers + one mactx descriptor. | |
1358 | */ | |
1359 | if (nfrags & 1) | |
1360 | nfrags++; | |
fc9e4d2a | 1361 | |
5c15332b | 1362 | txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1); |
f5cd7872 | 1363 | |
09f75cd7 JG |
1364 | dev->stats.tx_packets++; |
1365 | dev->stats.tx_bytes += skb->len; | |
f5cd7872 OJ |
1366 | |
1367 | spin_unlock_irqrestore(&txring->lock, flags); | |
1368 | ||
34c20624 | 1369 | write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1); |
f5cd7872 OJ |
1370 | |
1371 | return NETDEV_TX_OK; | |
1372 | ||
1373 | out_err: | |
1374 | spin_unlock_irqrestore(&txring->lock, flags); | |
ad3c20d1 OJ |
1375 | out_err_nolock: |
1376 | while (nfrags--) | |
1377 | pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags], | |
1378 | PCI_DMA_TODEVICE); | |
1379 | ||
f5cd7872 OJ |
1380 | return NETDEV_TX_BUSY; |
1381 | } | |
1382 | ||
f5cd7872 OJ |
1383 | static void pasemi_mac_set_rx_mode(struct net_device *dev) |
1384 | { | |
5c15332b | 1385 | const struct pasemi_mac *mac = netdev_priv(dev); |
f5cd7872 OJ |
1386 | unsigned int flags; |
1387 | ||
a85b9422 | 1388 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
f5cd7872 OJ |
1389 | |
1390 | /* Set promiscuous */ | |
1391 | if (dev->flags & IFF_PROMISC) | |
1392 | flags |= PAS_MAC_CFG_PCFG_PR; | |
1393 | else | |
1394 | flags &= ~PAS_MAC_CFG_PCFG_PR; | |
1395 | ||
a85b9422 | 1396 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); |
f5cd7872 OJ |
1397 | } |
1398 | ||
1399 | ||
bea3348e | 1400 | static int pasemi_mac_poll(struct napi_struct *napi, int budget) |
f5cd7872 | 1401 | { |
bea3348e SH |
1402 | struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi); |
1403 | struct net_device *dev = mac->netdev; | |
1404 | int pkts; | |
f5cd7872 | 1405 | |
72b05b99 OJ |
1406 | pasemi_mac_clean_tx(tx_ring(mac)); |
1407 | pkts = pasemi_mac_clean_rx(rx_ring(mac), budget); | |
bea3348e | 1408 | if (pkts < budget) { |
f5cd7872 | 1409 | /* all done, no more packets present */ |
bea3348e | 1410 | netif_rx_complete(dev, napi); |
f5cd7872 | 1411 | |
1b0335ea | 1412 | pasemi_mac_restart_rx_intr(mac); |
61cec3bd | 1413 | pasemi_mac_restart_tx_intr(mac); |
f5cd7872 | 1414 | } |
bea3348e | 1415 | return pkts; |
f5cd7872 OJ |
1416 | } |
1417 | ||
1418 | static int __devinit | |
1419 | pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1420 | { | |
f5cd7872 OJ |
1421 | struct net_device *dev; |
1422 | struct pasemi_mac *mac; | |
1423 | int err; | |
0795af57 | 1424 | DECLARE_MAC_BUF(mac_buf); |
f5cd7872 OJ |
1425 | |
1426 | err = pci_enable_device(pdev); | |
1427 | if (err) | |
1428 | return err; | |
1429 | ||
1430 | dev = alloc_etherdev(sizeof(struct pasemi_mac)); | |
1431 | if (dev == NULL) { | |
1432 | dev_err(&pdev->dev, | |
1433 | "pasemi_mac: Could not allocate ethernet device.\n"); | |
1434 | err = -ENOMEM; | |
1435 | goto out_disable_device; | |
1436 | } | |
1437 | ||
f5cd7872 OJ |
1438 | pci_set_drvdata(pdev, dev); |
1439 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1440 | ||
1441 | mac = netdev_priv(dev); | |
1442 | ||
1443 | mac->pdev = pdev; | |
1444 | mac->netdev = dev; | |
f5cd7872 | 1445 | |
bea3348e SH |
1446 | netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64); |
1447 | ||
5c15332b OJ |
1448 | dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG | |
1449 | NETIF_F_HIGHDMA; | |
bea3348e | 1450 | |
28ae79f5 OJ |
1451 | mac->lro_mgr.max_aggr = LRO_MAX_AGGR; |
1452 | mac->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS; | |
1453 | mac->lro_mgr.lro_arr = mac->lro_desc; | |
1454 | mac->lro_mgr.get_skb_header = get_skb_hdr; | |
1455 | mac->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID; | |
1456 | mac->lro_mgr.dev = mac->netdev; | |
1457 | mac->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1458 | mac->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
1459 | ||
1460 | ||
34c20624 OJ |
1461 | mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); |
1462 | if (!mac->dma_pdev) { | |
1463 | dev_err(&mac->pdev->dev, "Can't find DMA Controller\n"); | |
1464 | err = -ENODEV; | |
1465 | goto out; | |
1466 | } | |
f5cd7872 | 1467 | |
34c20624 OJ |
1468 | mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); |
1469 | if (!mac->iob_pdev) { | |
1470 | dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n"); | |
1471 | err = -ENODEV; | |
1472 | goto out; | |
1473 | } | |
1474 | ||
1475 | /* get mac addr from device tree */ | |
1476 | if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) { | |
1477 | err = -ENODEV; | |
1478 | goto out; | |
1479 | } | |
1480 | memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr)); | |
1481 | ||
1482 | mac->dma_if = mac_to_intf(mac); | |
1483 | if (mac->dma_if < 0) { | |
1484 | dev_err(&mac->pdev->dev, "Can't map DMA interface\n"); | |
1485 | err = -ENODEV; | |
1486 | goto out; | |
1487 | } | |
f5cd7872 OJ |
1488 | |
1489 | switch (pdev->device) { | |
1490 | case 0xa005: | |
1491 | mac->type = MAC_TYPE_GMAC; | |
1492 | break; | |
1493 | case 0xa006: | |
1494 | mac->type = MAC_TYPE_XAUI; | |
1495 | break; | |
1496 | default: | |
1497 | err = -ENODEV; | |
1498 | goto out; | |
1499 | } | |
1500 | ||
f5cd7872 OJ |
1501 | dev->open = pasemi_mac_open; |
1502 | dev->stop = pasemi_mac_close; | |
1503 | dev->hard_start_xmit = pasemi_mac_start_tx; | |
f5cd7872 | 1504 | dev->set_multicast_list = pasemi_mac_set_rx_mode; |
5cea73b0 | 1505 | dev->set_mac_address = pasemi_mac_set_mac_addr; |
f5cd7872 | 1506 | |
b6e05a1b OJ |
1507 | if (err) |
1508 | goto out; | |
f5cd7872 | 1509 | |
ceb51361 OJ |
1510 | mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
1511 | ||
bb6e9590 OJ |
1512 | /* Enable most messages by default */ |
1513 | mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1514 | ||
f5cd7872 OJ |
1515 | err = register_netdev(dev); |
1516 | ||
1517 | if (err) { | |
1518 | dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n", | |
1519 | err); | |
1520 | goto out; | |
69c29d89 | 1521 | } else if netif_msg_probe(mac) |
72b05b99 | 1522 | printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %s\n", |
f5cd7872 | 1523 | dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI", |
72b05b99 | 1524 | mac->dma_if, print_mac(mac_buf, dev->dev_addr)); |
f5cd7872 OJ |
1525 | |
1526 | return err; | |
1527 | ||
1528 | out: | |
b6e05a1b OJ |
1529 | if (mac->iob_pdev) |
1530 | pci_dev_put(mac->iob_pdev); | |
1531 | if (mac->dma_pdev) | |
1532 | pci_dev_put(mac->dma_pdev); | |
b6e05a1b | 1533 | |
f5cd7872 OJ |
1534 | free_netdev(dev); |
1535 | out_disable_device: | |
1536 | pci_disable_device(pdev); | |
1537 | return err; | |
1538 | ||
1539 | } | |
1540 | ||
1541 | static void __devexit pasemi_mac_remove(struct pci_dev *pdev) | |
1542 | { | |
1543 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1544 | struct pasemi_mac *mac; | |
1545 | ||
1546 | if (!netdev) | |
1547 | return; | |
1548 | ||
1549 | mac = netdev_priv(netdev); | |
1550 | ||
1551 | unregister_netdev(netdev); | |
1552 | ||
1553 | pci_disable_device(pdev); | |
1554 | pci_dev_put(mac->dma_pdev); | |
1555 | pci_dev_put(mac->iob_pdev); | |
1556 | ||
34c20624 OJ |
1557 | pasemi_dma_free_chan(&mac->tx->chan); |
1558 | pasemi_dma_free_chan(&mac->rx->chan); | |
b6e05a1b | 1559 | |
f5cd7872 OJ |
1560 | pci_set_drvdata(pdev, NULL); |
1561 | free_netdev(netdev); | |
1562 | } | |
1563 | ||
1564 | static struct pci_device_id pasemi_mac_pci_tbl[] = { | |
1565 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) }, | |
1566 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) }, | |
fd178254 | 1567 | { }, |
f5cd7872 OJ |
1568 | }; |
1569 | ||
1570 | MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl); | |
1571 | ||
1572 | static struct pci_driver pasemi_mac_driver = { | |
1573 | .name = "pasemi_mac", | |
1574 | .id_table = pasemi_mac_pci_tbl, | |
1575 | .probe = pasemi_mac_probe, | |
1576 | .remove = __devexit_p(pasemi_mac_remove), | |
1577 | }; | |
1578 | ||
1579 | static void __exit pasemi_mac_cleanup_module(void) | |
1580 | { | |
1581 | pci_unregister_driver(&pasemi_mac_driver); | |
f5cd7872 OJ |
1582 | } |
1583 | ||
1584 | int pasemi_mac_init_module(void) | |
1585 | { | |
34c20624 OJ |
1586 | int err; |
1587 | ||
1588 | err = pasemi_dma_init(); | |
1589 | if (err) | |
1590 | return err; | |
1591 | ||
f5cd7872 OJ |
1592 | return pci_register_driver(&pasemi_mac_driver); |
1593 | } | |
1594 | ||
f5cd7872 OJ |
1595 | module_init(pasemi_mac_init_module); |
1596 | module_exit(pasemi_mac_cleanup_module); |