Commit | Line | Data |
---|---|---|
f5cd7872 OJ |
1 | /* |
2 | * Copyright (C) 2006-2007 PA Semi, Inc | |
3 | * | |
4 | * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/dmaengine.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/netdevice.h> | |
27 | #include <linux/etherdevice.h> | |
28 | #include <asm/dma-mapping.h> | |
29 | #include <linux/in.h> | |
30 | #include <linux/skbuff.h> | |
31 | ||
32 | #include <linux/ip.h> | |
33 | #include <linux/tcp.h> | |
34 | #include <net/checksum.h> | |
28ae79f5 | 35 | #include <linux/inet_lro.h> |
f5cd7872 | 36 | |
771f7404 | 37 | #include <asm/irq.h> |
af289e80 | 38 | #include <asm/firmware.h> |
40afa531 | 39 | #include <asm/pasemi_dma.h> |
771f7404 | 40 | |
f5cd7872 OJ |
41 | #include "pasemi_mac.h" |
42 | ||
8dc121a4 OJ |
43 | /* We have our own align, since ppc64 in general has it at 0 because |
44 | * of design flaws in some of the server bridge chips. However, for | |
45 | * PWRficient doing the unaligned copies is more expensive than doing | |
46 | * unaligned DMA, so make sure the data is aligned instead. | |
47 | */ | |
48 | #define LOCAL_SKB_ALIGN 2 | |
f5cd7872 OJ |
49 | |
50 | /* TODO list | |
51 | * | |
f5cd7872 OJ |
52 | * - Multicast support |
53 | * - Large MTU support | |
7ddeae2c OJ |
54 | * - SW LRO |
55 | * - Multiqueue RX/TX | |
f5cd7872 OJ |
56 | */ |
57 | ||
58 | ||
59 | /* Must be a power of two */ | |
28ae79f5 | 60 | #define RX_RING_SIZE 2048 |
ad5da10a | 61 | #define TX_RING_SIZE 4096 |
f5cd7872 | 62 | |
28ae79f5 OJ |
63 | #define LRO_MAX_AGGR 64 |
64 | ||
ceb51361 OJ |
65 | #define DEFAULT_MSG_ENABLE \ |
66 | (NETIF_MSG_DRV | \ | |
67 | NETIF_MSG_PROBE | \ | |
68 | NETIF_MSG_LINK | \ | |
69 | NETIF_MSG_TIMER | \ | |
70 | NETIF_MSG_IFDOWN | \ | |
71 | NETIF_MSG_IFUP | \ | |
72 | NETIF_MSG_RX_ERR | \ | |
73 | NETIF_MSG_TX_ERR) | |
74 | ||
34c20624 | 75 | #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)]) |
72b05b99 | 76 | #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)]) |
34c20624 | 77 | #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)]) |
72b05b99 OJ |
78 | #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)]) |
79 | #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)]) | |
f5cd7872 | 80 | |
021fa22e OJ |
81 | #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \ |
82 | & ((ring)->size - 1)) | |
83 | #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring)) | |
84 | ||
f5cd7872 OJ |
85 | #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ |
86 | ||
ceb51361 OJ |
87 | MODULE_LICENSE("GPL"); |
88 | MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>"); | |
89 | MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver"); | |
90 | ||
91 | static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */ | |
92 | module_param(debug, int, 0); | |
93 | MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value"); | |
f5cd7872 | 94 | |
af289e80 OJ |
95 | static int translation_enabled(void) |
96 | { | |
97 | #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE) | |
98 | return 1; | |
99 | #else | |
100 | return firmware_has_feature(FW_FEATURE_LPAR); | |
101 | #endif | |
102 | } | |
103 | ||
34c20624 | 104 | static void write_iob_reg(unsigned int reg, unsigned int val) |
a85b9422 | 105 | { |
34c20624 | 106 | pasemi_write_iob_reg(reg, val); |
a85b9422 OJ |
107 | } |
108 | ||
5c15332b | 109 | static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg) |
a85b9422 | 110 | { |
34c20624 | 111 | return pasemi_read_mac_reg(mac->dma_if, reg); |
a85b9422 OJ |
112 | } |
113 | ||
5c15332b | 114 | static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg, |
a85b9422 OJ |
115 | unsigned int val) |
116 | { | |
34c20624 | 117 | pasemi_write_mac_reg(mac->dma_if, reg, val); |
a85b9422 OJ |
118 | } |
119 | ||
34c20624 | 120 | static unsigned int read_dma_reg(unsigned int reg) |
a85b9422 | 121 | { |
34c20624 | 122 | return pasemi_read_dma_reg(reg); |
a85b9422 OJ |
123 | } |
124 | ||
34c20624 | 125 | static void write_dma_reg(unsigned int reg, unsigned int val) |
a85b9422 | 126 | { |
34c20624 | 127 | pasemi_write_dma_reg(reg, val); |
a85b9422 OJ |
128 | } |
129 | ||
5c15332b | 130 | static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
131 | { |
132 | return mac->rx; | |
133 | } | |
134 | ||
5c15332b | 135 | static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
136 | { |
137 | return mac->tx; | |
138 | } | |
139 | ||
5c15332b OJ |
140 | static inline void prefetch_skb(const struct sk_buff *skb) |
141 | { | |
142 | const void *d = skb; | |
143 | ||
144 | prefetch(d); | |
145 | prefetch(d+64); | |
146 | prefetch(d+128); | |
147 | prefetch(d+192); | |
148 | } | |
149 | ||
34c20624 OJ |
150 | static int mac_to_intf(struct pasemi_mac *mac) |
151 | { | |
152 | struct pci_dev *pdev = mac->pdev; | |
153 | u32 tmp; | |
154 | int nintf, off, i, j; | |
155 | int devfn = pdev->devfn; | |
156 | ||
157 | tmp = read_dma_reg(PAS_DMA_CAP_IFI); | |
158 | nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S; | |
159 | off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S; | |
160 | ||
161 | /* IOFF contains the offset to the registers containing the | |
162 | * DMA interface-to-MAC-pci-id mappings, and NIN contains number | |
163 | * of total interfaces. Each register contains 4 devfns. | |
164 | * Just do a linear search until we find the devfn of the MAC | |
165 | * we're trying to look up. | |
166 | */ | |
167 | ||
168 | for (i = 0; i < (nintf+3)/4; i++) { | |
169 | tmp = read_dma_reg(off+4*i); | |
170 | for (j = 0; j < 4; j++) { | |
171 | if (((tmp >> (8*j)) & 0xff) == devfn) | |
172 | return i*4 + j; | |
173 | } | |
174 | } | |
175 | return -1; | |
176 | } | |
177 | ||
f5cd7872 OJ |
178 | static int pasemi_get_mac_addr(struct pasemi_mac *mac) |
179 | { | |
180 | struct pci_dev *pdev = mac->pdev; | |
181 | struct device_node *dn = pci_device_to_OF_node(pdev); | |
1af7f056 | 182 | int len; |
f5cd7872 OJ |
183 | const u8 *maddr; |
184 | u8 addr[6]; | |
185 | ||
186 | if (!dn) { | |
187 | dev_dbg(&pdev->dev, | |
188 | "No device node for mac, not configuring\n"); | |
189 | return -ENOENT; | |
190 | } | |
191 | ||
1af7f056 | 192 | maddr = of_get_property(dn, "local-mac-address", &len); |
193 | ||
194 | if (maddr && len == 6) { | |
195 | memcpy(mac->mac_addr, maddr, 6); | |
196 | return 0; | |
197 | } | |
198 | ||
199 | /* Some old versions of firmware mistakenly uses mac-address | |
200 | * (and as a string) instead of a byte array in local-mac-address. | |
201 | */ | |
a5fd22eb | 202 | |
a5fd22eb | 203 | if (maddr == NULL) |
9028780a | 204 | maddr = of_get_property(dn, "mac-address", NULL); |
a5fd22eb | 205 | |
f5cd7872 OJ |
206 | if (maddr == NULL) { |
207 | dev_warn(&pdev->dev, | |
208 | "no mac address in device tree, not configuring\n"); | |
209 | return -ENOENT; | |
210 | } | |
211 | ||
212 | if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0], | |
213 | &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) { | |
214 | dev_warn(&pdev->dev, | |
215 | "can't parse mac address, not configuring\n"); | |
216 | return -EINVAL; | |
217 | } | |
218 | ||
1af7f056 | 219 | memcpy(mac->mac_addr, addr, 6); |
220 | ||
f5cd7872 OJ |
221 | return 0; |
222 | } | |
223 | ||
28ae79f5 OJ |
224 | static int get_skb_hdr(struct sk_buff *skb, void **iphdr, |
225 | void **tcph, u64 *hdr_flags, void *data) | |
226 | { | |
227 | u64 macrx = (u64) data; | |
228 | unsigned int ip_len; | |
229 | struct iphdr *iph; | |
230 | ||
231 | /* IPv4 header checksum failed */ | |
232 | if ((macrx & XCT_MACRX_HTY_M) != XCT_MACRX_HTY_IPV4_OK) | |
233 | return -1; | |
234 | ||
235 | /* non tcp packet */ | |
236 | skb_reset_network_header(skb); | |
237 | iph = ip_hdr(skb); | |
238 | if (iph->protocol != IPPROTO_TCP) | |
239 | return -1; | |
240 | ||
241 | ip_len = ip_hdrlen(skb); | |
242 | skb_set_transport_header(skb, ip_len); | |
243 | *tcph = tcp_hdr(skb); | |
244 | ||
245 | /* check if ip header and tcp header are complete */ | |
246 | if (iph->tot_len < ip_len + tcp_hdrlen(skb)) | |
247 | return -1; | |
248 | ||
249 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
250 | *iphdr = iph; | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
ad3c20d1 | 255 | static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac, |
7e9916e9 | 256 | const int nfrags, |
ad3c20d1 | 257 | struct sk_buff *skb, |
5c15332b | 258 | const dma_addr_t *dmas) |
ad3c20d1 OJ |
259 | { |
260 | int f; | |
5c15332b | 261 | struct pci_dev *pdev = mac->dma_pdev; |
ad3c20d1 | 262 | |
5c15332b | 263 | pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
264 | |
265 | for (f = 0; f < nfrags; f++) { | |
266 | skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; | |
267 | ||
5c15332b | 268 | pci_unmap_page(pdev, dmas[f+1], frag->size, PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
269 | } |
270 | dev_kfree_skb_irq(skb); | |
271 | ||
272 | /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs, | |
273 | * aligned up to a power of 2 | |
274 | */ | |
275 | return (nfrags + 3) & ~1; | |
276 | } | |
277 | ||
5c15332b | 278 | static int pasemi_mac_setup_rx_resources(const struct net_device *dev) |
f5cd7872 OJ |
279 | { |
280 | struct pasemi_mac_rxring *ring; | |
281 | struct pasemi_mac *mac = netdev_priv(dev); | |
34c20624 | 282 | int chno; |
af289e80 | 283 | unsigned int cfg; |
f5cd7872 | 284 | |
34c20624 OJ |
285 | ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring), |
286 | offsetof(struct pasemi_mac_rxring, chan)); | |
f5cd7872 | 287 | |
34c20624 OJ |
288 | if (!ring) { |
289 | dev_err(&mac->pdev->dev, "Can't allocate RX channel\n"); | |
290 | goto out_chan; | |
291 | } | |
292 | chno = ring->chan.chno; | |
f5cd7872 OJ |
293 | |
294 | spin_lock_init(&ring->lock); | |
295 | ||
021fa22e | 296 | ring->size = RX_RING_SIZE; |
fc9e4d2a | 297 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 OJ |
298 | RX_RING_SIZE, GFP_KERNEL); |
299 | ||
fc9e4d2a OJ |
300 | if (!ring->ring_info) |
301 | goto out_ring_info; | |
f5cd7872 OJ |
302 | |
303 | /* Allocate descriptors */ | |
34c20624 | 304 | if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE)) |
fc9e4d2a | 305 | goto out_ring_desc; |
f5cd7872 | 306 | |
f5cd7872 OJ |
307 | ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev, |
308 | RX_RING_SIZE * sizeof(u64), | |
309 | &ring->buf_dma, GFP_KERNEL); | |
310 | if (!ring->buffers) | |
34c20624 | 311 | goto out_ring_desc; |
f5cd7872 OJ |
312 | |
313 | memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64)); | |
314 | ||
34c20624 OJ |
315 | write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno), |
316 | PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
f5cd7872 | 317 | |
34c20624 OJ |
318 | write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno), |
319 | PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) | | |
320 | PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 321 | |
5c15332b | 322 | cfg = PAS_DMA_RXCHAN_CFG_HBU(2); |
af289e80 OJ |
323 | |
324 | if (translation_enabled()) | |
325 | cfg |= PAS_DMA_RXCHAN_CFG_CTR; | |
326 | ||
34c20624 | 327 | write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg); |
f5cd7872 | 328 | |
34c20624 OJ |
329 | write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if), |
330 | PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma)); | |
f5cd7872 | 331 | |
34c20624 OJ |
332 | write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if), |
333 | PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) | | |
334 | PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 335 | |
5c15332b | 336 | cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 | |
af289e80 OJ |
337 | PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP | |
338 | PAS_DMA_RXINT_CFG_HEN; | |
339 | ||
340 | if (translation_enabled()) | |
341 | cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR; | |
342 | ||
34c20624 | 343 | write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg); |
c0efd52b | 344 | |
f5cd7872 OJ |
345 | ring->next_to_fill = 0; |
346 | ring->next_to_clean = 0; | |
72b05b99 | 347 | ring->mac = mac; |
f5cd7872 OJ |
348 | mac->rx = ring; |
349 | ||
350 | return 0; | |
351 | ||
fc9e4d2a OJ |
352 | out_ring_desc: |
353 | kfree(ring->ring_info); | |
354 | out_ring_info: | |
34c20624 OJ |
355 | pasemi_dma_free_chan(&ring->chan); |
356 | out_chan: | |
f5cd7872 OJ |
357 | return -ENOMEM; |
358 | } | |
359 | ||
72b05b99 | 360 | static struct pasemi_mac_txring * |
5c15332b | 361 | pasemi_mac_setup_tx_resources(const struct net_device *dev) |
f5cd7872 OJ |
362 | { |
363 | struct pasemi_mac *mac = netdev_priv(dev); | |
364 | u32 val; | |
f5cd7872 | 365 | struct pasemi_mac_txring *ring; |
af289e80 | 366 | unsigned int cfg; |
34c20624 | 367 | int chno; |
f5cd7872 | 368 | |
34c20624 OJ |
369 | ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring), |
370 | offsetof(struct pasemi_mac_txring, chan)); | |
371 | ||
372 | if (!ring) { | |
373 | dev_err(&mac->pdev->dev, "Can't allocate TX channel\n"); | |
374 | goto out_chan; | |
375 | } | |
376 | ||
377 | chno = ring->chan.chno; | |
f5cd7872 OJ |
378 | |
379 | spin_lock_init(&ring->lock); | |
380 | ||
021fa22e | 381 | ring->size = TX_RING_SIZE; |
fc9e4d2a | 382 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 | 383 | TX_RING_SIZE, GFP_KERNEL); |
fc9e4d2a OJ |
384 | if (!ring->ring_info) |
385 | goto out_ring_info; | |
f5cd7872 OJ |
386 | |
387 | /* Allocate descriptors */ | |
34c20624 | 388 | if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE)) |
fc9e4d2a | 389 | goto out_ring_desc; |
f5cd7872 | 390 | |
34c20624 OJ |
391 | write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), |
392 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
393 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); | |
fc9e4d2a | 394 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3); |
f5cd7872 | 395 | |
34c20624 | 396 | write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); |
f5cd7872 | 397 | |
af289e80 OJ |
398 | cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE | |
399 | PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | | |
400 | PAS_DMA_TXCHAN_CFG_UP | | |
401 | PAS_DMA_TXCHAN_CFG_WT(2); | |
402 | ||
403 | if (translation_enabled()) | |
404 | cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; | |
405 | ||
34c20624 | 406 | write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); |
f5cd7872 | 407 | |
021fa22e | 408 | ring->next_to_fill = 0; |
f5cd7872 | 409 | ring->next_to_clean = 0; |
72b05b99 | 410 | ring->mac = mac; |
f5cd7872 | 411 | |
72b05b99 | 412 | return ring; |
f5cd7872 | 413 | |
fc9e4d2a OJ |
414 | out_ring_desc: |
415 | kfree(ring->ring_info); | |
416 | out_ring_info: | |
34c20624 OJ |
417 | pasemi_dma_free_chan(&ring->chan); |
418 | out_chan: | |
72b05b99 | 419 | return NULL; |
f5cd7872 OJ |
420 | } |
421 | ||
72b05b99 | 422 | static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac) |
f5cd7872 | 423 | { |
72b05b99 | 424 | struct pasemi_mac_txring *txring = tx_ring(mac); |
ad3c20d1 | 425 | unsigned int i, j; |
f5cd7872 | 426 | struct pasemi_mac_buffer *info; |
ad3c20d1 | 427 | dma_addr_t dmas[MAX_SKB_FRAGS+1]; |
7e9916e9 | 428 | int freed, nfrags; |
ad5da10a | 429 | int start, limit; |
fc9e4d2a | 430 | |
72b05b99 OJ |
431 | start = txring->next_to_clean; |
432 | limit = txring->next_to_fill; | |
ad5da10a OJ |
433 | |
434 | /* Compensate for when fill has wrapped and clean has not */ | |
435 | if (start > limit) | |
436 | limit += TX_RING_SIZE; | |
437 | ||
438 | for (i = start; i < limit; i += freed) { | |
72b05b99 | 439 | info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)]; |
fc9e4d2a | 440 | if (info->dma && info->skb) { |
7e9916e9 OJ |
441 | nfrags = skb_shinfo(info->skb)->nr_frags; |
442 | for (j = 0; j <= nfrags; j++) | |
72b05b99 OJ |
443 | dmas[j] = txring->ring_info[(i+1+j) & |
444 | (TX_RING_SIZE-1)].dma; | |
7e9916e9 OJ |
445 | freed = pasemi_mac_unmap_tx_skb(mac, nfrags, |
446 | info->skb, dmas); | |
ad3c20d1 OJ |
447 | } else |
448 | freed = 2; | |
f5cd7872 OJ |
449 | } |
450 | ||
72b05b99 | 451 | kfree(txring->ring_info); |
34c20624 OJ |
452 | pasemi_dma_free_chan(&txring->chan); |
453 | ||
f5cd7872 OJ |
454 | } |
455 | ||
72b05b99 | 456 | static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac) |
f5cd7872 | 457 | { |
72b05b99 | 458 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
f5cd7872 OJ |
459 | unsigned int i; |
460 | struct pasemi_mac_buffer *info; | |
f5cd7872 OJ |
461 | |
462 | for (i = 0; i < RX_RING_SIZE; i++) { | |
72b05b99 | 463 | info = &RX_DESC_INFO(rx, i); |
fc9e4d2a OJ |
464 | if (info->skb && info->dma) { |
465 | pci_unmap_single(mac->dma_pdev, | |
466 | info->dma, | |
467 | info->skb->len, | |
468 | PCI_DMA_FROMDEVICE); | |
469 | dev_kfree_skb_any(info->skb); | |
f5cd7872 | 470 | } |
fc9e4d2a OJ |
471 | info->dma = 0; |
472 | info->skb = NULL; | |
f5cd7872 OJ |
473 | } |
474 | ||
fc9e4d2a | 475 | for (i = 0; i < RX_RING_SIZE; i++) |
72b05b99 | 476 | RX_DESC(rx, i) = 0; |
fc9e4d2a | 477 | |
f5cd7872 | 478 | dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64), |
72b05b99 | 479 | rx_ring(mac)->buffers, rx_ring(mac)->buf_dma); |
f5cd7872 | 480 | |
72b05b99 | 481 | kfree(rx_ring(mac)->ring_info); |
34c20624 | 482 | pasemi_dma_free_chan(&rx_ring(mac)->chan); |
f5cd7872 OJ |
483 | mac->rx = NULL; |
484 | } | |
485 | ||
5c15332b OJ |
486 | static void pasemi_mac_replenish_rx_ring(const struct net_device *dev, |
487 | const int limit) | |
f5cd7872 | 488 | { |
5c15332b | 489 | const struct pasemi_mac *mac = netdev_priv(dev); |
72b05b99 | 490 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
b5254eee | 491 | int fill, count; |
f5cd7872 | 492 | |
cd4ceb24 | 493 | if (limit <= 0) |
f5cd7872 OJ |
494 | return; |
495 | ||
72b05b99 | 496 | fill = rx_ring(mac)->next_to_fill; |
928773c2 | 497 | for (count = 0; count < limit; count++) { |
72b05b99 OJ |
498 | struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill); |
499 | u64 *buff = &RX_BUFF(rx, fill); | |
f5cd7872 OJ |
500 | struct sk_buff *skb; |
501 | dma_addr_t dma; | |
502 | ||
fc9e4d2a OJ |
503 | /* Entry in use? */ |
504 | WARN_ON(*buff); | |
505 | ||
9f05cfe2 OJ |
506 | /* skb might still be in there for recycle on short receives */ |
507 | if (info->skb) | |
508 | skb = info->skb; | |
8dc121a4 | 509 | else { |
9f05cfe2 | 510 | skb = dev_alloc_skb(BUF_SIZE); |
8dc121a4 OJ |
511 | skb_reserve(skb, LOCAL_SKB_ALIGN); |
512 | } | |
f5cd7872 | 513 | |
9f05cfe2 | 514 | if (unlikely(!skb)) |
f5cd7872 | 515 | break; |
f5cd7872 | 516 | |
8dc121a4 OJ |
517 | dma = pci_map_single(mac->dma_pdev, skb->data, |
518 | BUF_SIZE - LOCAL_SKB_ALIGN, | |
f5cd7872 OJ |
519 | PCI_DMA_FROMDEVICE); |
520 | ||
cd4ceb24 | 521 | if (unlikely(dma_mapping_error(dma))) { |
f5cd7872 | 522 | dev_kfree_skb_irq(info->skb); |
f5cd7872 OJ |
523 | break; |
524 | } | |
525 | ||
526 | info->skb = skb; | |
527 | info->dma = dma; | |
528 | *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma); | |
fc9e4d2a | 529 | fill++; |
f5cd7872 OJ |
530 | } |
531 | ||
532 | wmb(); | |
533 | ||
34c20624 | 534 | write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count); |
f5cd7872 | 535 | |
72b05b99 | 536 | rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) & |
b5254eee | 537 | (RX_RING_SIZE - 1); |
f5cd7872 OJ |
538 | } |
539 | ||
5c15332b | 540 | static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac) |
1b0335ea | 541 | { |
906674ab | 542 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
52a94351 | 543 | unsigned int reg, pcnt; |
1b0335ea OJ |
544 | /* Re-enable packet count interrupts: finally |
545 | * ack the packet count interrupt we got in rx_intr. | |
546 | */ | |
547 | ||
906674ab | 548 | pcnt = *rx->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 549 | |
52a94351 | 550 | reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; |
1b0335ea | 551 | |
906674ab OJ |
552 | if (*rx->chan.status & PAS_STATUS_TIMER) |
553 | reg |= PAS_IOB_DMA_RXCH_RESET_TINTC; | |
554 | ||
34c20624 | 555 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg); |
1b0335ea OJ |
556 | } |
557 | ||
5c15332b | 558 | static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac) |
1b0335ea | 559 | { |
52a94351 | 560 | unsigned int reg, pcnt; |
1b0335ea OJ |
561 | |
562 | /* Re-enable packet count interrupts */ | |
34c20624 | 563 | pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 564 | |
52a94351 | 565 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; |
1b0335ea | 566 | |
34c20624 | 567 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg); |
1b0335ea OJ |
568 | } |
569 | ||
570 | ||
5c15332b OJ |
571 | static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac, |
572 | const u64 macrx) | |
69c29d89 OJ |
573 | { |
574 | unsigned int rcmdsta, ccmdsta; | |
34c20624 | 575 | struct pasemi_dmachan *chan = &rx_ring(mac)->chan; |
69c29d89 OJ |
576 | |
577 | if (!netif_msg_rx_err(mac)) | |
578 | return; | |
579 | ||
34c20624 OJ |
580 | rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
581 | ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno)); | |
69c29d89 OJ |
582 | |
583 | printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n", | |
34c20624 | 584 | macrx, *chan->status); |
69c29d89 OJ |
585 | |
586 | printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n", | |
587 | rcmdsta, ccmdsta); | |
588 | } | |
589 | ||
5c15332b OJ |
590 | static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac, |
591 | const u64 mactx) | |
69c29d89 OJ |
592 | { |
593 | unsigned int cmdsta; | |
34c20624 | 594 | struct pasemi_dmachan *chan = &tx_ring(mac)->chan; |
69c29d89 OJ |
595 | |
596 | if (!netif_msg_tx_err(mac)) | |
597 | return; | |
598 | ||
34c20624 | 599 | cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno)); |
69c29d89 OJ |
600 | |
601 | printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\ | |
34c20624 | 602 | "tx status 0x%016lx\n", mactx, *chan->status); |
69c29d89 OJ |
603 | |
604 | printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta); | |
605 | } | |
606 | ||
5c15332b OJ |
607 | static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx, |
608 | const int limit) | |
f5cd7872 | 609 | { |
5c15332b | 610 | const struct pasemi_dmachan *chan = &rx->chan; |
72b05b99 | 611 | struct pasemi_mac *mac = rx->mac; |
5c15332b | 612 | struct pci_dev *pdev = mac->dma_pdev; |
cd4ceb24 | 613 | unsigned int n; |
5c15332b | 614 | int count, buf_index, tot_bytes, packets; |
cd4ceb24 OJ |
615 | struct pasemi_mac_buffer *info; |
616 | struct sk_buff *skb; | |
b5254eee | 617 | unsigned int len; |
5c15332b | 618 | u64 macrx, eval; |
cd4ceb24 | 619 | dma_addr_t dma; |
5c15332b OJ |
620 | |
621 | tot_bytes = 0; | |
622 | packets = 0; | |
f5cd7872 | 623 | |
72b05b99 | 624 | spin_lock(&rx->lock); |
f5cd7872 | 625 | |
72b05b99 | 626 | n = rx->next_to_clean; |
f5cd7872 | 627 | |
72b05b99 | 628 | prefetch(&RX_DESC(rx, n)); |
b5254eee OJ |
629 | |
630 | for (count = 0; count < limit; count++) { | |
72b05b99 | 631 | macrx = RX_DESC(rx, n); |
5c15332b | 632 | prefetch(&RX_DESC(rx, n+4)); |
f5cd7872 | 633 | |
69c29d89 | 634 | if ((macrx & XCT_MACRX_E) || |
34c20624 | 635 | (*chan->status & PAS_STATUS_ERROR)) |
69c29d89 OJ |
636 | pasemi_mac_rx_error(mac, macrx); |
637 | ||
cd4ceb24 | 638 | if (!(macrx & XCT_MACRX_O)) |
f5cd7872 OJ |
639 | break; |
640 | ||
f5cd7872 OJ |
641 | info = NULL; |
642 | ||
b5254eee | 643 | BUG_ON(!(macrx & XCT_MACRX_RR_8BRES)); |
f5cd7872 | 644 | |
72b05b99 | 645 | eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >> |
b5254eee OJ |
646 | XCT_RXRES_8B_EVAL_S; |
647 | buf_index = eval-1; | |
648 | ||
72b05b99 OJ |
649 | dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M); |
650 | info = &RX_DESC_INFO(rx, buf_index); | |
fc9e4d2a | 651 | |
9f05cfe2 | 652 | skb = info->skb; |
f5cd7872 | 653 | |
5c15332b | 654 | prefetch_skb(skb); |
f5cd7872 | 655 | |
cd4ceb24 | 656 | len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S; |
f5cd7872 | 657 | |
5c15332b OJ |
658 | pci_unmap_single(pdev, dma, BUF_SIZE-LOCAL_SKB_ALIGN, |
659 | PCI_DMA_FROMDEVICE); | |
32bee776 OJ |
660 | |
661 | if (macrx & XCT_MACRX_CRC) { | |
662 | /* CRC error flagged */ | |
663 | mac->netdev->stats.rx_errors++; | |
664 | mac->netdev->stats.rx_crc_errors++; | |
4352d826 | 665 | /* No need to free skb, it'll be reused */ |
32bee776 OJ |
666 | goto next; |
667 | } | |
668 | ||
9f05cfe2 | 669 | if (len < 256) { |
8dc121a4 OJ |
670 | struct sk_buff *new_skb; |
671 | ||
672 | new_skb = netdev_alloc_skb(mac->netdev, | |
673 | len + LOCAL_SKB_ALIGN); | |
9f05cfe2 | 674 | if (new_skb) { |
8dc121a4 | 675 | skb_reserve(new_skb, LOCAL_SKB_ALIGN); |
73344863 | 676 | memcpy(new_skb->data, skb->data, len); |
9f05cfe2 OJ |
677 | /* save the skb in buffer_info as good */ |
678 | skb = new_skb; | |
679 | } | |
680 | /* else just continue with the old one */ | |
681 | } else | |
682 | info->skb = NULL; | |
f5cd7872 | 683 | |
ad5da10a | 684 | info->dma = 0; |
fc9e4d2a | 685 | |
26fcfa95 | 686 | if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) { |
38bf3184 | 687 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
cd4ceb24 | 688 | skb->csum = (macrx & XCT_MACRX_CSUM_M) >> |
f5cd7872 OJ |
689 | XCT_MACRX_CSUM_S; |
690 | } else | |
691 | skb->ip_summed = CHECKSUM_NONE; | |
692 | ||
5c15332b OJ |
693 | packets++; |
694 | tot_bytes += len; | |
695 | ||
696 | /* Don't include CRC */ | |
697 | skb_put(skb, len-4); | |
f5cd7872 | 698 | |
26fcfa95 | 699 | skb->protocol = eth_type_trans(skb, mac->netdev); |
28ae79f5 | 700 | lro_receive_skb(&mac->lro_mgr, skb, (void *)macrx); |
f5cd7872 | 701 | |
32bee776 | 702 | next: |
72b05b99 OJ |
703 | RX_DESC(rx, n) = 0; |
704 | RX_DESC(rx, n+1) = 0; | |
cd4ceb24 | 705 | |
ad5da10a OJ |
706 | /* Need to zero it out since hardware doesn't, since the |
707 | * replenish loop uses it to tell when it's done. | |
708 | */ | |
72b05b99 | 709 | RX_BUFF(rx, buf_index) = 0; |
ad5da10a | 710 | |
b5254eee | 711 | n += 4; |
f5cd7872 OJ |
712 | } |
713 | ||
9a50bebd OJ |
714 | if (n > RX_RING_SIZE) { |
715 | /* Errata 5971 workaround: L2 target of headers */ | |
34c20624 | 716 | write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0); |
9a50bebd OJ |
717 | n &= (RX_RING_SIZE-1); |
718 | } | |
b5254eee | 719 | |
72b05b99 | 720 | rx_ring(mac)->next_to_clean = n; |
b5254eee | 721 | |
28ae79f5 OJ |
722 | lro_flush_all(&mac->lro_mgr); |
723 | ||
b5254eee OJ |
724 | /* Increase is in number of 16-byte entries, and since each descriptor |
725 | * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with | |
726 | * count*2. | |
727 | */ | |
34c20624 | 728 | write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1); |
b5254eee OJ |
729 | |
730 | pasemi_mac_replenish_rx_ring(mac->netdev, count); | |
f5cd7872 | 731 | |
5c15332b OJ |
732 | mac->netdev->stats.rx_bytes += tot_bytes; |
733 | mac->netdev->stats.rx_packets += packets; | |
734 | ||
72b05b99 | 735 | spin_unlock(&rx_ring(mac)->lock); |
f5cd7872 OJ |
736 | |
737 | return count; | |
738 | } | |
739 | ||
ad3c20d1 OJ |
740 | /* Can't make this too large or we blow the kernel stack limits */ |
741 | #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS) | |
742 | ||
72b05b99 | 743 | static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring) |
f5cd7872 | 744 | { |
34c20624 | 745 | struct pasemi_dmachan *chan = &txring->chan; |
72b05b99 | 746 | struct pasemi_mac *mac = txring->mac; |
ad3c20d1 | 747 | int i, j; |
ad5da10a OJ |
748 | unsigned int start, descr_count, buf_count, batch_limit; |
749 | unsigned int ring_limit; | |
02df6cfa | 750 | unsigned int total_count; |
ca7e235f | 751 | unsigned long flags; |
ad3c20d1 OJ |
752 | struct sk_buff *skbs[TX_CLEAN_BATCHSIZE]; |
753 | dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1]; | |
7e9916e9 OJ |
754 | int nf[TX_CLEAN_BATCHSIZE]; |
755 | int nr_frags; | |
f5cd7872 | 756 | |
02df6cfa | 757 | total_count = 0; |
ad5da10a | 758 | batch_limit = TX_CLEAN_BATCHSIZE; |
02df6cfa | 759 | restart: |
72b05b99 | 760 | spin_lock_irqsave(&txring->lock, flags); |
f5cd7872 | 761 | |
72b05b99 OJ |
762 | start = txring->next_to_clean; |
763 | ring_limit = txring->next_to_fill; | |
ad5da10a | 764 | |
7e9916e9 OJ |
765 | prefetch(&TX_DESC_INFO(txring, start+1).skb); |
766 | ||
ad5da10a OJ |
767 | /* Compensate for when fill has wrapped but clean has not */ |
768 | if (start > ring_limit) | |
769 | ring_limit += TX_RING_SIZE; | |
02df6cfa | 770 | |
ad3c20d1 OJ |
771 | buf_count = 0; |
772 | descr_count = 0; | |
f5cd7872 | 773 | |
ad3c20d1 | 774 | for (i = start; |
ad5da10a | 775 | descr_count < batch_limit && i < ring_limit; |
ad3c20d1 | 776 | i += buf_count) { |
72b05b99 | 777 | u64 mactx = TX_DESC(txring, i); |
ad5da10a | 778 | struct sk_buff *skb; |
ad3c20d1 | 779 | |
7e9916e9 OJ |
780 | skb = TX_DESC_INFO(txring, i+1).skb; |
781 | nr_frags = TX_DESC_INFO(txring, i).dma; | |
782 | ||
fc9e4d2a | 783 | if ((mactx & XCT_MACTX_E) || |
34c20624 | 784 | (*chan->status & PAS_STATUS_ERROR)) |
fc9e4d2a | 785 | pasemi_mac_tx_error(mac, mactx); |
69c29d89 | 786 | |
fc9e4d2a | 787 | if (unlikely(mactx & XCT_MACTX_O)) |
02df6cfa | 788 | /* Not yet transmitted */ |
f5cd7872 OJ |
789 | break; |
790 | ||
7e9916e9 OJ |
791 | buf_count = 2 + nr_frags; |
792 | /* Since we always fill with an even number of entries, make | |
793 | * sure we skip any unused one at the end as well. | |
794 | */ | |
795 | if (buf_count & 1) | |
796 | buf_count++; | |
ad3c20d1 | 797 | |
7e9916e9 | 798 | for (j = 0; j <= nr_frags; j++) |
72b05b99 | 799 | dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma; |
ad3c20d1 | 800 | |
7e9916e9 OJ |
801 | skbs[descr_count] = skb; |
802 | nf[descr_count] = nr_frags; | |
803 | ||
72b05b99 OJ |
804 | TX_DESC(txring, i) = 0; |
805 | TX_DESC(txring, i+1) = 0; | |
fc9e4d2a | 806 | |
ad3c20d1 | 807 | descr_count++; |
f5cd7872 | 808 | } |
72b05b99 | 809 | txring->next_to_clean = i & (TX_RING_SIZE-1); |
ad3c20d1 | 810 | |
72b05b99 | 811 | spin_unlock_irqrestore(&txring->lock, flags); |
0ce68c74 OJ |
812 | netif_wake_queue(mac->netdev); |
813 | ||
ad3c20d1 | 814 | for (i = 0; i < descr_count; i++) |
7e9916e9 | 815 | pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]); |
02df6cfa | 816 | |
ad3c20d1 | 817 | total_count += descr_count; |
02df6cfa OJ |
818 | |
819 | /* If the batch was full, try to clean more */ | |
ad5da10a | 820 | if (descr_count == batch_limit) |
02df6cfa OJ |
821 | goto restart; |
822 | ||
823 | return total_count; | |
f5cd7872 OJ |
824 | } |
825 | ||
826 | ||
827 | static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) | |
828 | { | |
5c15332b | 829 | const struct pasemi_mac_rxring *rxring = data; |
34c20624 OJ |
830 | struct pasemi_mac *mac = rxring->mac; |
831 | struct net_device *dev = mac->netdev; | |
5c15332b | 832 | const struct pasemi_dmachan *chan = &rxring->chan; |
f5cd7872 OJ |
833 | unsigned int reg; |
834 | ||
34c20624 | 835 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
836 | return IRQ_NONE; |
837 | ||
6dfa7522 OJ |
838 | /* Don't reset packet count so it won't fire again but clear |
839 | * all others. | |
840 | */ | |
841 | ||
6dfa7522 | 842 | reg = 0; |
34c20624 | 843 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 844 | reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; |
34c20624 | 845 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 846 | reg |= PAS_IOB_DMA_RXCH_RESET_DINTC; |
f5cd7872 | 847 | |
bea3348e | 848 | netif_rx_schedule(dev, &mac->napi); |
6dfa7522 | 849 | |
34c20624 | 850 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg); |
f5cd7872 OJ |
851 | |
852 | return IRQ_HANDLED; | |
853 | } | |
854 | ||
61cec3bd OJ |
855 | #define TX_CLEAN_INTERVAL HZ |
856 | ||
857 | static void pasemi_mac_tx_timer(unsigned long data) | |
858 | { | |
859 | struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data; | |
860 | struct pasemi_mac *mac = txring->mac; | |
861 | ||
862 | pasemi_mac_clean_tx(txring); | |
863 | ||
864 | mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL); | |
865 | ||
866 | pasemi_mac_restart_tx_intr(mac); | |
867 | } | |
868 | ||
f5cd7872 OJ |
869 | static irqreturn_t pasemi_mac_tx_intr(int irq, void *data) |
870 | { | |
72b05b99 | 871 | struct pasemi_mac_txring *txring = data; |
5c15332b | 872 | const struct pasemi_dmachan *chan = &txring->chan; |
61cec3bd OJ |
873 | struct pasemi_mac *mac = txring->mac; |
874 | unsigned int reg; | |
f5cd7872 | 875 | |
34c20624 | 876 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
877 | return IRQ_NONE; |
878 | ||
61cec3bd | 879 | reg = 0; |
6dfa7522 | 880 | |
34c20624 | 881 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 882 | reg |= PAS_IOB_DMA_TXCH_RESET_SINTC; |
34c20624 | 883 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 884 | reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; |
f5cd7872 | 885 | |
61cec3bd OJ |
886 | mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2); |
887 | ||
888 | netif_rx_schedule(mac->netdev, &mac->napi); | |
889 | ||
890 | if (reg) | |
891 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg); | |
f5cd7872 | 892 | |
f5cd7872 OJ |
893 | return IRQ_HANDLED; |
894 | } | |
895 | ||
bb6e9590 OJ |
896 | static void pasemi_adjust_link(struct net_device *dev) |
897 | { | |
898 | struct pasemi_mac *mac = netdev_priv(dev); | |
899 | int msg; | |
900 | unsigned int flags; | |
901 | unsigned int new_flags; | |
902 | ||
903 | if (!mac->phydev->link) { | |
904 | /* If no link, MAC speed settings don't matter. Just report | |
905 | * link down and return. | |
906 | */ | |
907 | if (mac->link && netif_msg_link(mac)) | |
908 | printk(KERN_INFO "%s: Link is down.\n", dev->name); | |
909 | ||
910 | netif_carrier_off(dev); | |
911 | mac->link = 0; | |
912 | ||
913 | return; | |
914 | } else | |
915 | netif_carrier_on(dev); | |
916 | ||
a85b9422 | 917 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
bb6e9590 OJ |
918 | new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | |
919 | PAS_MAC_CFG_PCFG_TSR_M); | |
920 | ||
921 | if (!mac->phydev->duplex) | |
922 | new_flags |= PAS_MAC_CFG_PCFG_HD; | |
923 | ||
924 | switch (mac->phydev->speed) { | |
925 | case 1000: | |
926 | new_flags |= PAS_MAC_CFG_PCFG_SPD_1G | | |
927 | PAS_MAC_CFG_PCFG_TSR_1G; | |
928 | break; | |
929 | case 100: | |
930 | new_flags |= PAS_MAC_CFG_PCFG_SPD_100M | | |
931 | PAS_MAC_CFG_PCFG_TSR_100M; | |
932 | break; | |
933 | case 10: | |
934 | new_flags |= PAS_MAC_CFG_PCFG_SPD_10M | | |
935 | PAS_MAC_CFG_PCFG_TSR_10M; | |
936 | break; | |
937 | default: | |
938 | printk("Unsupported speed %d\n", mac->phydev->speed); | |
939 | } | |
940 | ||
941 | /* Print on link or speed/duplex change */ | |
942 | msg = mac->link != mac->phydev->link || flags != new_flags; | |
943 | ||
944 | mac->duplex = mac->phydev->duplex; | |
945 | mac->speed = mac->phydev->speed; | |
946 | mac->link = mac->phydev->link; | |
947 | ||
948 | if (new_flags != flags) | |
a85b9422 | 949 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags); |
bb6e9590 OJ |
950 | |
951 | if (msg && netif_msg_link(mac)) | |
952 | printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", | |
953 | dev->name, mac->speed, mac->duplex ? "full" : "half"); | |
954 | } | |
955 | ||
956 | static int pasemi_mac_phy_init(struct net_device *dev) | |
957 | { | |
958 | struct pasemi_mac *mac = netdev_priv(dev); | |
959 | struct device_node *dn, *phy_dn; | |
960 | struct phy_device *phydev; | |
961 | unsigned int phy_id; | |
962 | const phandle *ph; | |
963 | const unsigned int *prop; | |
964 | struct resource r; | |
965 | int ret; | |
966 | ||
967 | dn = pci_device_to_OF_node(mac->pdev); | |
9028780a | 968 | ph = of_get_property(dn, "phy-handle", NULL); |
bb6e9590 OJ |
969 | if (!ph) |
970 | return -ENODEV; | |
971 | phy_dn = of_find_node_by_phandle(*ph); | |
972 | ||
9028780a | 973 | prop = of_get_property(phy_dn, "reg", NULL); |
bb6e9590 OJ |
974 | ret = of_address_to_resource(phy_dn->parent, 0, &r); |
975 | if (ret) | |
976 | goto err; | |
977 | ||
978 | phy_id = *prop; | |
979 | snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id); | |
980 | ||
981 | of_node_put(phy_dn); | |
982 | ||
983 | mac->link = 0; | |
984 | mac->speed = 0; | |
985 | mac->duplex = -1; | |
986 | ||
987 | phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII); | |
988 | ||
989 | if (IS_ERR(phydev)) { | |
990 | printk(KERN_ERR "%s: Could not attach to phy\n", dev->name); | |
991 | return PTR_ERR(phydev); | |
992 | } | |
993 | ||
994 | mac->phydev = phydev; | |
995 | ||
996 | return 0; | |
997 | ||
998 | err: | |
999 | of_node_put(phy_dn); | |
1000 | return -ENODEV; | |
1001 | } | |
1002 | ||
1003 | ||
f5cd7872 OJ |
1004 | static int pasemi_mac_open(struct net_device *dev) |
1005 | { | |
1006 | struct pasemi_mac *mac = netdev_priv(dev); | |
1007 | unsigned int flags; | |
1008 | int ret; | |
1009 | ||
1010 | /* enable rx section */ | |
34c20624 | 1011 | write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN); |
f5cd7872 OJ |
1012 | |
1013 | /* enable tx section */ | |
34c20624 | 1014 | write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); |
f5cd7872 OJ |
1015 | |
1016 | flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | | |
1017 | PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | | |
1018 | PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); | |
1019 | ||
a85b9422 | 1020 | write_mac_reg(mac, PAS_MAC_CFG_TXP, flags); |
f5cd7872 | 1021 | |
f5cd7872 OJ |
1022 | ret = pasemi_mac_setup_rx_resources(dev); |
1023 | if (ret) | |
1024 | goto out_rx_resources; | |
1025 | ||
34c20624 | 1026 | mac->tx = pasemi_mac_setup_tx_resources(dev); |
72b05b99 OJ |
1027 | |
1028 | if (!mac->tx) | |
1029 | goto out_tx_ring; | |
f5cd7872 | 1030 | |
906674ab OJ |
1031 | /* 0x3ff with 33MHz clock is about 31us */ |
1032 | write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG, | |
1033 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff)); | |
1034 | ||
34c20624 | 1035 | write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno), |
28ae79f5 | 1036 | PAS_IOB_DMA_RXCH_CFG_CNTTH(256)); |
34c20624 OJ |
1037 | |
1038 | write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno), | |
61cec3bd | 1039 | PAS_IOB_DMA_TXCH_CFG_CNTTH(32)); |
34c20624 | 1040 | |
a85b9422 | 1041 | write_mac_reg(mac, PAS_MAC_IPC_CHNL, |
34c20624 OJ |
1042 | PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) | |
1043 | PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno)); | |
f5cd7872 OJ |
1044 | |
1045 | /* enable rx if */ | |
34c20624 OJ |
1046 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), |
1047 | PAS_DMA_RXINT_RCMDSTA_EN | | |
1048 | PAS_DMA_RXINT_RCMDSTA_DROPS_M | | |
1049 | PAS_DMA_RXINT_RCMDSTA_BP | | |
1050 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1051 | PAS_DMA_RXINT_RCMDSTA_BT); | |
f5cd7872 OJ |
1052 | |
1053 | /* enable rx channel */ | |
34c20624 OJ |
1054 | pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU | |
1055 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1056 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1057 | PAS_DMA_RXCHAN_CCMDSTA_DT); | |
f5cd7872 OJ |
1058 | |
1059 | /* enable tx channel */ | |
34c20624 OJ |
1060 | pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | |
1061 | PAS_DMA_TXCHAN_TCMDSTA_DB | | |
1062 | PAS_DMA_TXCHAN_TCMDSTA_DE | | |
1063 | PAS_DMA_TXCHAN_TCMDSTA_DA); | |
f5cd7872 | 1064 | |
928773c2 | 1065 | pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE); |
f5cd7872 | 1066 | |
34c20624 OJ |
1067 | write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno), |
1068 | RX_RING_SIZE>>1); | |
b5254eee | 1069 | |
72b05b99 OJ |
1070 | /* Clear out any residual packet count state from firmware */ |
1071 | pasemi_mac_restart_rx_intr(mac); | |
1072 | pasemi_mac_restart_tx_intr(mac); | |
1073 | ||
36033766 OJ |
1074 | flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE | |
1075 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; | |
1076 | ||
1077 | if (mac->type == MAC_TYPE_GMAC) | |
1078 | flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; | |
1079 | else | |
1080 | flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G; | |
1081 | ||
1082 | /* Enable interface in MAC */ | |
1083 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
1084 | ||
bb6e9590 OJ |
1085 | ret = pasemi_mac_phy_init(dev); |
1086 | /* Some configs don't have PHYs (XAUI etc), so don't complain about | |
1087 | * failed init due to -ENODEV. | |
1088 | */ | |
1089 | if (ret && ret != -ENODEV) | |
1090 | dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret); | |
1091 | ||
f5cd7872 | 1092 | netif_start_queue(dev); |
bea3348e | 1093 | napi_enable(&mac->napi); |
f5cd7872 | 1094 | |
72b05b99 OJ |
1095 | snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx", |
1096 | dev->name); | |
771f7404 | 1097 | |
34c20624 | 1098 | ret = request_irq(mac->tx->chan.irq, &pasemi_mac_tx_intr, IRQF_DISABLED, |
72b05b99 | 1099 | mac->tx_irq_name, mac->tx); |
f5cd7872 OJ |
1100 | if (ret) { |
1101 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1102 | mac->tx->chan.irq, ret); |
f5cd7872 OJ |
1103 | goto out_tx_int; |
1104 | } | |
1105 | ||
72b05b99 OJ |
1106 | snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx", |
1107 | dev->name); | |
1108 | ||
34c20624 OJ |
1109 | ret = request_irq(mac->rx->chan.irq, &pasemi_mac_rx_intr, IRQF_DISABLED, |
1110 | mac->rx_irq_name, mac->rx); | |
f5cd7872 OJ |
1111 | if (ret) { |
1112 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1113 | mac->rx->chan.irq, ret); |
f5cd7872 OJ |
1114 | goto out_rx_int; |
1115 | } | |
1116 | ||
bb6e9590 OJ |
1117 | if (mac->phydev) |
1118 | phy_start(mac->phydev); | |
1119 | ||
61cec3bd OJ |
1120 | init_timer(&mac->tx->clean_timer); |
1121 | mac->tx->clean_timer.function = pasemi_mac_tx_timer; | |
1122 | mac->tx->clean_timer.data = (unsigned long)mac->tx; | |
1123 | mac->tx->clean_timer.expires = jiffies+HZ; | |
1124 | add_timer(&mac->tx->clean_timer); | |
1125 | ||
f5cd7872 OJ |
1126 | return 0; |
1127 | ||
1128 | out_rx_int: | |
34c20624 | 1129 | free_irq(mac->tx->chan.irq, mac->tx); |
f5cd7872 | 1130 | out_tx_int: |
bea3348e | 1131 | napi_disable(&mac->napi); |
f5cd7872 | 1132 | netif_stop_queue(dev); |
72b05b99 OJ |
1133 | out_tx_ring: |
1134 | if (mac->tx) | |
1135 | pasemi_mac_free_tx_resources(mac); | |
1136 | pasemi_mac_free_rx_resources(mac); | |
f5cd7872 OJ |
1137 | out_rx_resources: |
1138 | ||
1139 | return ret; | |
1140 | } | |
1141 | ||
1142 | #define MAX_RETRIES 5000 | |
1143 | ||
1144 | static int pasemi_mac_close(struct net_device *dev) | |
1145 | { | |
1146 | struct pasemi_mac *mac = netdev_priv(dev); | |
9e81d331 | 1147 | unsigned int sta; |
f5cd7872 | 1148 | int retries; |
34c20624 OJ |
1149 | int rxch, txch; |
1150 | ||
1151 | rxch = rx_ring(mac)->chan.chno; | |
1152 | txch = tx_ring(mac)->chan.chno; | |
f5cd7872 | 1153 | |
bb6e9590 OJ |
1154 | if (mac->phydev) { |
1155 | phy_stop(mac->phydev); | |
1156 | phy_disconnect(mac->phydev); | |
1157 | } | |
1158 | ||
61cec3bd OJ |
1159 | del_timer_sync(&mac->tx->clean_timer); |
1160 | ||
f5cd7872 | 1161 | netif_stop_queue(dev); |
bea3348e | 1162 | napi_disable(&mac->napi); |
f5cd7872 | 1163 | |
34c20624 | 1164 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
9e81d331 OJ |
1165 | if (sta & (PAS_DMA_RXINT_RCMDSTA_BP | |
1166 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1167 | PAS_DMA_RXINT_RCMDSTA_BT)) | |
1168 | printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta); | |
1169 | ||
34c20624 | 1170 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); |
9e81d331 OJ |
1171 | if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU | |
1172 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1173 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1174 | PAS_DMA_RXCHAN_CCMDSTA_DT)) | |
1175 | printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta); | |
1176 | ||
34c20624 | 1177 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); |
72b05b99 OJ |
1178 | if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB | |
1179 | PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA)) | |
9e81d331 OJ |
1180 | printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta); |
1181 | ||
f5cd7872 | 1182 | /* Clean out any pending buffers */ |
72b05b99 OJ |
1183 | pasemi_mac_clean_tx(tx_ring(mac)); |
1184 | pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); | |
f5cd7872 OJ |
1185 | |
1186 | /* Disable interface */ | |
34c20624 | 1187 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), |
72b05b99 | 1188 | PAS_DMA_TXCHAN_TCMDSTA_ST); |
34c20624 | 1189 | write_dma_reg( PAS_DMA_RXINT_RCMDSTA(mac->dma_if), |
72b05b99 | 1190 | PAS_DMA_RXINT_RCMDSTA_ST); |
34c20624 | 1191 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), |
72b05b99 | 1192 | PAS_DMA_RXCHAN_CCMDSTA_ST); |
f5cd7872 OJ |
1193 | |
1194 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
34c20624 | 1195 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(rxch)); |
9e81d331 | 1196 | if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) |
f5cd7872 OJ |
1197 | break; |
1198 | cond_resched(); | |
1199 | } | |
1200 | ||
9e81d331 | 1201 | if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT) |
34c20624 | 1202 | dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n"); |
f5cd7872 OJ |
1203 | |
1204 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
34c20624 | 1205 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); |
9e81d331 | 1206 | if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) |
f5cd7872 OJ |
1207 | break; |
1208 | cond_resched(); | |
1209 | } | |
1210 | ||
9e81d331 | 1211 | if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT) |
f5cd7872 | 1212 | dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n"); |
f5cd7872 OJ |
1213 | |
1214 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
34c20624 | 1215 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
9e81d331 | 1216 | if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT)) |
f5cd7872 OJ |
1217 | break; |
1218 | cond_resched(); | |
1219 | } | |
1220 | ||
9e81d331 | 1221 | if (sta & PAS_DMA_RXINT_RCMDSTA_ACT) |
f5cd7872 | 1222 | dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n"); |
f5cd7872 OJ |
1223 | |
1224 | /* Then, disable the channel. This must be done separately from | |
1225 | * stopping, since you can't disable when active. | |
1226 | */ | |
1227 | ||
34c20624 OJ |
1228 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0); |
1229 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0); | |
1230 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); | |
f5cd7872 | 1231 | |
34c20624 OJ |
1232 | free_irq(mac->tx->chan.irq, mac->tx); |
1233 | free_irq(mac->rx->chan.irq, mac->rx); | |
f5cd7872 OJ |
1234 | |
1235 | /* Free resources */ | |
72b05b99 OJ |
1236 | pasemi_mac_free_rx_resources(mac); |
1237 | pasemi_mac_free_tx_resources(mac); | |
f5cd7872 OJ |
1238 | |
1239 | return 0; | |
1240 | } | |
1241 | ||
1242 | static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) | |
1243 | { | |
1244 | struct pasemi_mac *mac = netdev_priv(dev); | |
1245 | struct pasemi_mac_txring *txring; | |
ad3c20d1 OJ |
1246 | u64 dflags, mactx; |
1247 | dma_addr_t map[MAX_SKB_FRAGS+1]; | |
1248 | unsigned int map_size[MAX_SKB_FRAGS+1]; | |
ca7e235f | 1249 | unsigned long flags; |
ad3c20d1 | 1250 | int i, nfrags; |
5c15332b | 1251 | int fill; |
f5cd7872 | 1252 | |
dbd62af7 | 1253 | dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD; |
f5cd7872 OJ |
1254 | |
1255 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
d56f90a7 ACM |
1256 | const unsigned char *nh = skb_network_header(skb); |
1257 | ||
eddc9ec5 | 1258 | switch (ip_hdr(skb)->protocol) { |
f5cd7872 OJ |
1259 | case IPPROTO_TCP: |
1260 | dflags |= XCT_MACTX_CSUM_TCP; | |
cfe1fc77 | 1261 | dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2); |
d56f90a7 | 1262 | dflags |= XCT_MACTX_IPO(nh - skb->data); |
f5cd7872 OJ |
1263 | break; |
1264 | case IPPROTO_UDP: | |
1265 | dflags |= XCT_MACTX_CSUM_UDP; | |
cfe1fc77 | 1266 | dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2); |
d56f90a7 | 1267 | dflags |= XCT_MACTX_IPO(nh - skb->data); |
f5cd7872 OJ |
1268 | break; |
1269 | } | |
1270 | } | |
1271 | ||
ad3c20d1 OJ |
1272 | nfrags = skb_shinfo(skb)->nr_frags; |
1273 | ||
1274 | map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb), | |
1275 | PCI_DMA_TODEVICE); | |
1276 | map_size[0] = skb_headlen(skb); | |
1277 | if (dma_mapping_error(map[0])) | |
1278 | goto out_err_nolock; | |
1279 | ||
1280 | for (i = 0; i < nfrags; i++) { | |
1281 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
f5cd7872 | 1282 | |
ad3c20d1 OJ |
1283 | map[i+1] = pci_map_page(mac->dma_pdev, frag->page, |
1284 | frag->page_offset, frag->size, | |
1285 | PCI_DMA_TODEVICE); | |
1286 | map_size[i+1] = frag->size; | |
1287 | if (dma_mapping_error(map[i+1])) { | |
1288 | nfrags = i; | |
1289 | goto out_err_nolock; | |
1290 | } | |
1291 | } | |
f5cd7872 | 1292 | |
26fcfa95 | 1293 | mactx = dflags | XCT_MACTX_LLEN(skb->len); |
26fcfa95 | 1294 | |
72b05b99 | 1295 | txring = tx_ring(mac); |
f5cd7872 OJ |
1296 | |
1297 | spin_lock_irqsave(&txring->lock, flags); | |
1298 | ||
5c15332b OJ |
1299 | fill = txring->next_to_fill; |
1300 | ||
ad5da10a OJ |
1301 | /* Avoid stepping on the same cache line that the DMA controller |
1302 | * is currently about to send, so leave at least 8 words available. | |
1303 | * Total free space needed is mactx + fragments + 8 | |
1304 | */ | |
1305 | if (RING_AVAIL(txring) < nfrags + 10) { | |
1306 | /* no room -- stop the queue and wait for tx intr */ | |
1307 | netif_stop_queue(dev); | |
1308 | goto out_err; | |
f5cd7872 OJ |
1309 | } |
1310 | ||
5c15332b | 1311 | TX_DESC(txring, fill) = mactx; |
7e9916e9 | 1312 | TX_DESC_INFO(txring, fill).dma = nfrags; |
5c15332b OJ |
1313 | fill++; |
1314 | TX_DESC_INFO(txring, fill).skb = skb; | |
ad3c20d1 | 1315 | for (i = 0; i <= nfrags; i++) { |
5c15332b | 1316 | TX_DESC(txring, fill+i) = |
72b05b99 | 1317 | XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); |
5c15332b | 1318 | TX_DESC_INFO(txring, fill+i).dma = map[i]; |
ad3c20d1 OJ |
1319 | } |
1320 | ||
1321 | /* We have to add an even number of 8-byte entries to the ring | |
1322 | * even if the last one is unused. That means always an odd number | |
1323 | * of pointers + one mactx descriptor. | |
1324 | */ | |
1325 | if (nfrags & 1) | |
1326 | nfrags++; | |
fc9e4d2a | 1327 | |
5c15332b | 1328 | txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1); |
f5cd7872 | 1329 | |
09f75cd7 JG |
1330 | dev->stats.tx_packets++; |
1331 | dev->stats.tx_bytes += skb->len; | |
f5cd7872 OJ |
1332 | |
1333 | spin_unlock_irqrestore(&txring->lock, flags); | |
1334 | ||
34c20624 | 1335 | write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1); |
f5cd7872 OJ |
1336 | |
1337 | return NETDEV_TX_OK; | |
1338 | ||
1339 | out_err: | |
1340 | spin_unlock_irqrestore(&txring->lock, flags); | |
ad3c20d1 OJ |
1341 | out_err_nolock: |
1342 | while (nfrags--) | |
1343 | pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags], | |
1344 | PCI_DMA_TODEVICE); | |
1345 | ||
f5cd7872 OJ |
1346 | return NETDEV_TX_BUSY; |
1347 | } | |
1348 | ||
f5cd7872 OJ |
1349 | static void pasemi_mac_set_rx_mode(struct net_device *dev) |
1350 | { | |
5c15332b | 1351 | const struct pasemi_mac *mac = netdev_priv(dev); |
f5cd7872 OJ |
1352 | unsigned int flags; |
1353 | ||
a85b9422 | 1354 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
f5cd7872 OJ |
1355 | |
1356 | /* Set promiscuous */ | |
1357 | if (dev->flags & IFF_PROMISC) | |
1358 | flags |= PAS_MAC_CFG_PCFG_PR; | |
1359 | else | |
1360 | flags &= ~PAS_MAC_CFG_PCFG_PR; | |
1361 | ||
a85b9422 | 1362 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); |
f5cd7872 OJ |
1363 | } |
1364 | ||
1365 | ||
bea3348e | 1366 | static int pasemi_mac_poll(struct napi_struct *napi, int budget) |
f5cd7872 | 1367 | { |
bea3348e SH |
1368 | struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi); |
1369 | struct net_device *dev = mac->netdev; | |
1370 | int pkts; | |
f5cd7872 | 1371 | |
72b05b99 OJ |
1372 | pasemi_mac_clean_tx(tx_ring(mac)); |
1373 | pkts = pasemi_mac_clean_rx(rx_ring(mac), budget); | |
bea3348e | 1374 | if (pkts < budget) { |
f5cd7872 | 1375 | /* all done, no more packets present */ |
bea3348e | 1376 | netif_rx_complete(dev, napi); |
f5cd7872 | 1377 | |
1b0335ea | 1378 | pasemi_mac_restart_rx_intr(mac); |
61cec3bd | 1379 | pasemi_mac_restart_tx_intr(mac); |
f5cd7872 | 1380 | } |
bea3348e | 1381 | return pkts; |
f5cd7872 OJ |
1382 | } |
1383 | ||
1384 | static int __devinit | |
1385 | pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
1386 | { | |
f5cd7872 OJ |
1387 | struct net_device *dev; |
1388 | struct pasemi_mac *mac; | |
1389 | int err; | |
0795af57 | 1390 | DECLARE_MAC_BUF(mac_buf); |
f5cd7872 OJ |
1391 | |
1392 | err = pci_enable_device(pdev); | |
1393 | if (err) | |
1394 | return err; | |
1395 | ||
1396 | dev = alloc_etherdev(sizeof(struct pasemi_mac)); | |
1397 | if (dev == NULL) { | |
1398 | dev_err(&pdev->dev, | |
1399 | "pasemi_mac: Could not allocate ethernet device.\n"); | |
1400 | err = -ENOMEM; | |
1401 | goto out_disable_device; | |
1402 | } | |
1403 | ||
f5cd7872 OJ |
1404 | pci_set_drvdata(pdev, dev); |
1405 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1406 | ||
1407 | mac = netdev_priv(dev); | |
1408 | ||
1409 | mac->pdev = pdev; | |
1410 | mac->netdev = dev; | |
f5cd7872 | 1411 | |
bea3348e SH |
1412 | netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64); |
1413 | ||
5c15332b OJ |
1414 | dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG | |
1415 | NETIF_F_HIGHDMA; | |
bea3348e | 1416 | |
28ae79f5 OJ |
1417 | mac->lro_mgr.max_aggr = LRO_MAX_AGGR; |
1418 | mac->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS; | |
1419 | mac->lro_mgr.lro_arr = mac->lro_desc; | |
1420 | mac->lro_mgr.get_skb_header = get_skb_hdr; | |
1421 | mac->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID; | |
1422 | mac->lro_mgr.dev = mac->netdev; | |
1423 | mac->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1424 | mac->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
1425 | ||
1426 | ||
34c20624 OJ |
1427 | mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); |
1428 | if (!mac->dma_pdev) { | |
1429 | dev_err(&mac->pdev->dev, "Can't find DMA Controller\n"); | |
1430 | err = -ENODEV; | |
1431 | goto out; | |
1432 | } | |
f5cd7872 | 1433 | |
34c20624 OJ |
1434 | mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); |
1435 | if (!mac->iob_pdev) { | |
1436 | dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n"); | |
1437 | err = -ENODEV; | |
1438 | goto out; | |
1439 | } | |
1440 | ||
1441 | /* get mac addr from device tree */ | |
1442 | if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) { | |
1443 | err = -ENODEV; | |
1444 | goto out; | |
1445 | } | |
1446 | memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr)); | |
1447 | ||
1448 | mac->dma_if = mac_to_intf(mac); | |
1449 | if (mac->dma_if < 0) { | |
1450 | dev_err(&mac->pdev->dev, "Can't map DMA interface\n"); | |
1451 | err = -ENODEV; | |
1452 | goto out; | |
1453 | } | |
f5cd7872 OJ |
1454 | |
1455 | switch (pdev->device) { | |
1456 | case 0xa005: | |
1457 | mac->type = MAC_TYPE_GMAC; | |
1458 | break; | |
1459 | case 0xa006: | |
1460 | mac->type = MAC_TYPE_XAUI; | |
1461 | break; | |
1462 | default: | |
1463 | err = -ENODEV; | |
1464 | goto out; | |
1465 | } | |
1466 | ||
f5cd7872 OJ |
1467 | dev->open = pasemi_mac_open; |
1468 | dev->stop = pasemi_mac_close; | |
1469 | dev->hard_start_xmit = pasemi_mac_start_tx; | |
f5cd7872 | 1470 | dev->set_multicast_list = pasemi_mac_set_rx_mode; |
f5cd7872 | 1471 | |
b6e05a1b OJ |
1472 | if (err) |
1473 | goto out; | |
f5cd7872 | 1474 | |
ceb51361 OJ |
1475 | mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
1476 | ||
bb6e9590 OJ |
1477 | /* Enable most messages by default */ |
1478 | mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1479 | ||
f5cd7872 OJ |
1480 | err = register_netdev(dev); |
1481 | ||
1482 | if (err) { | |
1483 | dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n", | |
1484 | err); | |
1485 | goto out; | |
69c29d89 | 1486 | } else if netif_msg_probe(mac) |
72b05b99 | 1487 | printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %s\n", |
f5cd7872 | 1488 | dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI", |
72b05b99 | 1489 | mac->dma_if, print_mac(mac_buf, dev->dev_addr)); |
f5cd7872 OJ |
1490 | |
1491 | return err; | |
1492 | ||
1493 | out: | |
b6e05a1b OJ |
1494 | if (mac->iob_pdev) |
1495 | pci_dev_put(mac->iob_pdev); | |
1496 | if (mac->dma_pdev) | |
1497 | pci_dev_put(mac->dma_pdev); | |
b6e05a1b | 1498 | |
f5cd7872 OJ |
1499 | free_netdev(dev); |
1500 | out_disable_device: | |
1501 | pci_disable_device(pdev); | |
1502 | return err; | |
1503 | ||
1504 | } | |
1505 | ||
1506 | static void __devexit pasemi_mac_remove(struct pci_dev *pdev) | |
1507 | { | |
1508 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1509 | struct pasemi_mac *mac; | |
1510 | ||
1511 | if (!netdev) | |
1512 | return; | |
1513 | ||
1514 | mac = netdev_priv(netdev); | |
1515 | ||
1516 | unregister_netdev(netdev); | |
1517 | ||
1518 | pci_disable_device(pdev); | |
1519 | pci_dev_put(mac->dma_pdev); | |
1520 | pci_dev_put(mac->iob_pdev); | |
1521 | ||
34c20624 OJ |
1522 | pasemi_dma_free_chan(&mac->tx->chan); |
1523 | pasemi_dma_free_chan(&mac->rx->chan); | |
b6e05a1b | 1524 | |
f5cd7872 OJ |
1525 | pci_set_drvdata(pdev, NULL); |
1526 | free_netdev(netdev); | |
1527 | } | |
1528 | ||
1529 | static struct pci_device_id pasemi_mac_pci_tbl[] = { | |
1530 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) }, | |
1531 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) }, | |
fd178254 | 1532 | { }, |
f5cd7872 OJ |
1533 | }; |
1534 | ||
1535 | MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl); | |
1536 | ||
1537 | static struct pci_driver pasemi_mac_driver = { | |
1538 | .name = "pasemi_mac", | |
1539 | .id_table = pasemi_mac_pci_tbl, | |
1540 | .probe = pasemi_mac_probe, | |
1541 | .remove = __devexit_p(pasemi_mac_remove), | |
1542 | }; | |
1543 | ||
1544 | static void __exit pasemi_mac_cleanup_module(void) | |
1545 | { | |
1546 | pci_unregister_driver(&pasemi_mac_driver); | |
f5cd7872 OJ |
1547 | } |
1548 | ||
1549 | int pasemi_mac_init_module(void) | |
1550 | { | |
34c20624 OJ |
1551 | int err; |
1552 | ||
1553 | err = pasemi_dma_init(); | |
1554 | if (err) | |
1555 | return err; | |
1556 | ||
f5cd7872 OJ |
1557 | return pci_register_driver(&pasemi_mac_driver); |
1558 | } | |
1559 | ||
f5cd7872 OJ |
1560 | module_init(pasemi_mac_init_module); |
1561 | module_exit(pasemi_mac_cleanup_module); |