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pcmcia: pcmcia_request_window() doesn't need a pointer to a pointer
[deliverable/linux.git] / drivers / net / pcmcia / nmclan_cs.c
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1da177e4
LT		 1/* ----------------------------------------------------------------------------
2Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47-------------------------------------------------------------------------------
48Driver Notes and Issues
49-------------------------------------------------------------------------------
50
511. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
552. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
603. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
634. There is a bad slow-down problem in this driver.
64
655. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68-------------------------------------------------------------------------------
69History
70-------------------------------------------------------------------------------
71Log: nmclan_cs.c,v
113aa838 72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
1da177e4
LT		 73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
9695/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
10095/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
10395/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
10595/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
10995/05/10 rpao V0.07 Statistics.
11095/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112---------------------------------------------------------------------------- */
113
114#define DRV_NAME "nmclan_cs"
115#define DRV_VERSION "0.16"
116
117
118/* ----------------------------------------------------------------------------
119Conditional Compilation Options
120---------------------------------------------------------------------------- */
121
122#define MULTI_TX 0
123#define RESET_ON_TIMEOUT 1
124#define TX_INTERRUPTABLE 1
125#define RESET_XILINX 0
126
127/* ----------------------------------------------------------------------------
128Include Files
129---------------------------------------------------------------------------- */
130
131#include <linux/module.h>
132#include <linux/kernel.h>
133#include <linux/init.h>
134#include <linux/ptrace.h>
135#include <linux/slab.h>
136#include <linux/string.h>
137#include <linux/timer.h>
138#include <linux/interrupt.h>
139#include <linux/in.h>
140#include <linux/delay.h>
141#include <linux/ethtool.h>
142#include <linux/netdevice.h>
143#include <linux/etherdevice.h>
144#include <linux/skbuff.h>
145#include <linux/if_arp.h>
146#include <linux/ioport.h>
147#include <linux/bitops.h>
148
1da177e4
LT		 149#include <pcmcia/cs_types.h>
150#include <pcmcia/cs.h>
151#include <pcmcia/cisreg.h>
152#include <pcmcia/cistpl.h>
153#include <pcmcia/ds.h>
154
155#include <asm/uaccess.h>
156#include <asm/io.h>
157#include <asm/system.h>
158
159/* ----------------------------------------------------------------------------
160Defines
161---------------------------------------------------------------------------- */
162
163#define ETHER_ADDR_LEN ETH_ALEN
164 /* 6 bytes in an Ethernet Address */
165#define MACE_LADRF_LEN 8
166 /* 8 bytes in Logical Address Filter */
167
168/* Loop Control Defines */
169#define MACE_MAX_IR_ITERATIONS 10
170#define MACE_MAX_RX_ITERATIONS 12
171 /*
172 TBD: Dean brought this up, and I assumed the hardware would
173 handle it:
174
175 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
176 non-zero when the isr exits. We may not get another interrupt
177 to process the remaining packets for some time.
178 */
179
180/*
181The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
182which manages the interface between the MACE and the PCMCIA bus. It
183also includes buffer management for the 32K x 8 SRAM to control up to
184four transmit and 12 receive frames at a time.
185*/
186#define AM2150_MAX_TX_FRAMES 4
187#define AM2150_MAX_RX_FRAMES 12
188
189/* Am2150 Ethernet Card I/O Mapping */
190#define AM2150_RCV 0x00
191#define AM2150_XMT 0x04
192#define AM2150_XMT_SKIP 0x09
193#define AM2150_RCV_NEXT 0x0A
194#define AM2150_RCV_FRAME_COUNT 0x0B
195#define AM2150_MACE_BANK 0x0C
196#define AM2150_MACE_BASE 0x10
197
198/* MACE Registers */
199#define MACE_RCVFIFO 0
200#define MACE_XMTFIFO 1
201#define MACE_XMTFC 2
202#define MACE_XMTFS 3
203#define MACE_XMTRC 4
204#define MACE_RCVFC 5
205#define MACE_RCVFS 6
206#define MACE_FIFOFC 7
207#define MACE_IR 8
208#define MACE_IMR 9
209#define MACE_PR 10
210#define MACE_BIUCC 11
211#define MACE_FIFOCC 12
212#define MACE_MACCC 13
213#define MACE_PLSCC 14
214#define MACE_PHYCC 15
215#define MACE_CHIPIDL 16
216#define MACE_CHIPIDH 17
217#define MACE_IAC 18
218/* Reserved */
219#define MACE_LADRF 20
220#define MACE_PADR 21
221/* Reserved */
222/* Reserved */
223#define MACE_MPC 24
224/* Reserved */
225#define MACE_RNTPC 26
226#define MACE_RCVCC 27
227/* Reserved */
228#define MACE_UTR 29
229#define MACE_RTR1 30
230#define MACE_RTR2 31
231
232/* MACE Bit Masks */
233#define MACE_XMTRC_EXDEF 0x80
234#define MACE_XMTRC_XMTRC 0x0F
235
236#define MACE_XMTFS_XMTSV 0x80
237#define MACE_XMTFS_UFLO 0x40
238#define MACE_XMTFS_LCOL 0x20
239#define MACE_XMTFS_MORE 0x10
240#define MACE_XMTFS_ONE 0x08
241#define MACE_XMTFS_DEFER 0x04
242#define MACE_XMTFS_LCAR 0x02
243#define MACE_XMTFS_RTRY 0x01
244
245#define MACE_RCVFS_RCVSTS 0xF000
246#define MACE_RCVFS_OFLO 0x8000
247#define MACE_RCVFS_CLSN 0x4000
248#define MACE_RCVFS_FRAM 0x2000
249#define MACE_RCVFS_FCS 0x1000
250
251#define MACE_FIFOFC_RCVFC 0xF0
252#define MACE_FIFOFC_XMTFC 0x0F
253
254#define MACE_IR_JAB 0x80
255#define MACE_IR_BABL 0x40
256#define MACE_IR_CERR 0x20
257#define MACE_IR_RCVCCO 0x10
258#define MACE_IR_RNTPCO 0x08
259#define MACE_IR_MPCO 0x04
260#define MACE_IR_RCVINT 0x02
261#define MACE_IR_XMTINT 0x01
262
263#define MACE_MACCC_PROM 0x80
264#define MACE_MACCC_DXMT2PD 0x40
265#define MACE_MACCC_EMBA 0x20
266#define MACE_MACCC_RESERVED 0x10
267#define MACE_MACCC_DRCVPA 0x08
268#define MACE_MACCC_DRCVBC 0x04
269#define MACE_MACCC_ENXMT 0x02
270#define MACE_MACCC_ENRCV 0x01
271
272#define MACE_PHYCC_LNKFL 0x80
273#define MACE_PHYCC_DLNKTST 0x40
274#define MACE_PHYCC_REVPOL 0x20
275#define MACE_PHYCC_DAPC 0x10
276#define MACE_PHYCC_LRT 0x08
277#define MACE_PHYCC_ASEL 0x04
278#define MACE_PHYCC_RWAKE 0x02
279#define MACE_PHYCC_AWAKE 0x01
280
281#define MACE_IAC_ADDRCHG 0x80
282#define MACE_IAC_PHYADDR 0x04
283#define MACE_IAC_LOGADDR 0x02
284
285#define MACE_UTR_RTRE 0x80
286#define MACE_UTR_RTRD 0x40
287#define MACE_UTR_RPA 0x20
288#define MACE_UTR_FCOLL 0x10
289#define MACE_UTR_RCVFCSE 0x08
290#define MACE_UTR_LOOP_INCL_MENDEC 0x06
291#define MACE_UTR_LOOP_NO_MENDEC 0x04
292#define MACE_UTR_LOOP_EXTERNAL 0x02
293#define MACE_UTR_LOOP_NONE 0x00
294#define MACE_UTR_RESERVED 0x01
295
296/* Switch MACE register bank (only 0 and 1 are valid) */
297#define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
298
299#define MACE_IMR_DEFAULT \
300 (0xFF - \
301 ( \
302 MACE_IR_CERR | \
303 MACE_IR_RCVCCO | \
304 MACE_IR_RNTPCO | \
305 MACE_IR_MPCO | \
306 MACE_IR_RCVINT | \
307 MACE_IR_XMTINT \
308 ) \
309 )
310#undef MACE_IMR_DEFAULT
311#define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
312
313#define TX_TIMEOUT ((400*HZ)/1000)
314
315/* ----------------------------------------------------------------------------
316Type Definitions
317---------------------------------------------------------------------------- */
318
319typedef struct _mace_statistics {
320 /* MACE_XMTFS */
321 int xmtsv;
322 int uflo;
323 int lcol;
324 int more;
325 int one;
326 int defer;
327 int lcar;
328 int rtry;
329
330 /* MACE_XMTRC */
331 int exdef;
332 int xmtrc;
333
334 /* RFS1--Receive Status (RCVSTS) */
335 int oflo;
336 int clsn;
337 int fram;
338 int fcs;
339
340 /* RFS2--Runt Packet Count (RNTPC) */
341 int rfs_rntpc;
342
343 /* RFS3--Receive Collision Count (RCVCC) */
344 int rfs_rcvcc;
345
346 /* MACE_IR */
347 int jab;
348 int babl;
349 int cerr;
350 int rcvcco;
351 int rntpco;
352 int mpco;
353
354 /* MACE_MPC */
355 int mpc;
356
357 /* MACE_RNTPC */
358 int rntpc;
359
360 /* MACE_RCVCC */
361 int rcvcc;
362} mace_statistics;
363
364typedef struct _mace_private {
fd238232 365 struct pcmcia_device *p_dev;
1da177e4
LT		 366 dev_node_t node;
367 struct net_device_stats linux_stats; /* Linux statistics counters */
368 mace_statistics mace_stats; /* MACE chip statistics counters */
369
370 /* restore_multicast_list() state variables */
371 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
372 int multicast_num_addrs;
373
374 char tx_free_frames; /* Number of free transmit frame buffers */
375 char tx_irq_disabled; /* MACE TX interrupt disabled */
376
377 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
378} mace_private;
379
380/* ----------------------------------------------------------------------------
381Private Global Variables
382---------------------------------------------------------------------------- */
383
f71e1309 384static const char *if_names[]={
1da177e4
LT		 385 "Auto", "10baseT", "BNC",
386};
387
388/* ----------------------------------------------------------------------------
389Parameters
390 These are the parameters that can be set during loading with
391 'insmod'.
392---------------------------------------------------------------------------- */
393
394MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
395MODULE_LICENSE("GPL");
396
397#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
398
399/* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
400INT_MODULE_PARM(if_port, 0);
401
1da177e4
LT		 402
403/* ----------------------------------------------------------------------------
404Function Prototypes
405---------------------------------------------------------------------------- */
406
15b99ac1 407static int nmclan_config(struct pcmcia_device *link);
fba395ee 408static void nmclan_release(struct pcmcia_device *link);
1da177e4
LT		 409
410static void nmclan_reset(struct net_device *dev);
411static int mace_config(struct net_device *dev, struct ifmap *map);
412static int mace_open(struct net_device *dev);
413static int mace_close(struct net_device *dev);
dbf02fae
SH		 414static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
415 struct net_device *dev);
1da177e4 416static void mace_tx_timeout(struct net_device *dev);
7d12e780 417static irqreturn_t mace_interrupt(int irq, void *dev_id);
1da177e4
LT		 418static struct net_device_stats *mace_get_stats(struct net_device *dev);
419static int mace_rx(struct net_device *dev, unsigned char RxCnt);
420static void restore_multicast_list(struct net_device *dev);
421static void set_multicast_list(struct net_device *dev);
7282d491 422static const struct ethtool_ops netdev_ethtool_ops;
1da177e4
LT		 423
424
cc3b4866 425static void nmclan_detach(struct pcmcia_device *p_dev);
1da177e4 426
28b1801d
SH		 427static const struct net_device_ops mace_netdev_ops = {
428 .ndo_open = mace_open,
429 .ndo_stop = mace_close,
430 .ndo_start_xmit = mace_start_xmit,
431 .ndo_tx_timeout = mace_tx_timeout,
432 .ndo_set_config = mace_config,
433 .ndo_get_stats = mace_get_stats,
434 .ndo_set_multicast_list = set_multicast_list,
435 .ndo_change_mtu = eth_change_mtu,
436 .ndo_set_mac_address = eth_mac_addr,
437 .ndo_validate_addr = eth_validate_addr,
438};
439
1da177e4
LT		 440/* ----------------------------------------------------------------------------
441nmclan_attach
442 Creates an "instance" of the driver, allocating local data
443 structures for one device. The device is registered with Card
444 Services.
445---------------------------------------------------------------------------- */
446
15b99ac1 447static int nmclan_probe(struct pcmcia_device *link)
1da177e4
LT		 448{
449 mace_private *lp;
1da177e4 450 struct net_device *dev;
1da177e4 451
dd0fab5b 452 dev_dbg(&link->dev, "nmclan_attach()\n");
1da177e4
LT		 453
454 /* Create new ethernet device */
455 dev = alloc_etherdev(sizeof(mace_private));
456 if (!dev)
f8cfa618 457 return -ENOMEM;
1da177e4 458 lp = netdev_priv(dev);
fba395ee 459 lp->p_dev = link;
1da177e4
LT		 460 link->priv = dev;
461
462 spin_lock_init(&lp->bank_lock);
463 link->io.NumPorts1 = 32;
464 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
465 link->io.IOAddrLines = 5;
466 link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
467 link->irq.IRQInfo1 = IRQ_LEVEL_ID;
468 link->irq.Handler = &mace_interrupt;
469 link->irq.Instance = dev;
470 link->conf.Attributes = CONF_ENABLE_IRQ;
1da177e4
LT		 471 link->conf.IntType = INT_MEMORY_AND_IO;
472 link->conf.ConfigIndex = 1;
473 link->conf.Present = PRESENT_OPTION;
474
475 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
476
28b1801d 477 dev->netdev_ops = &mace_netdev_ops;
1da177e4 478 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
1da177e4 479 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 480
15b99ac1 481 return nmclan_config(link);
1da177e4
LT		 482} /* nmclan_attach */
483
484/* ----------------------------------------------------------------------------
485nmclan_detach
486 This deletes a driver "instance". The device is de-registered
487 with Card Services. If it has been released, all local data
488 structures are freed. Otherwise, the structures will be freed
489 when the device is released.
490---------------------------------------------------------------------------- */
491
fba395ee 492static void nmclan_detach(struct pcmcia_device *link)
1da177e4
LT		 493{
494 struct net_device *dev = link->priv;
1da177e4 495
dd0fab5b 496 dev_dbg(&link->dev, "nmclan_detach\n");
1da177e4 497
fd238232 498 if (link->dev_node)
1da177e4
LT		 499 unregister_netdev(dev);
500
e2d40963 501 nmclan_release(link);
1da177e4 502
1da177e4
LT		 503 free_netdev(dev);
504} /* nmclan_detach */
505
506/* ----------------------------------------------------------------------------
507mace_read
508 Reads a MACE register. This is bank independent; however, the
509 caller must ensure that this call is not interruptable. We are
510 assuming that during normal operation, the MACE is always in
511 bank 0.
512---------------------------------------------------------------------------- */
906da809 513static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
1da177e4
LT		 514{
515 int data = 0xFF;
516 unsigned long flags;
517
518 switch (reg >> 4) {
519 case 0: /* register 0-15 */
520 data = inb(ioaddr + AM2150_MACE_BASE + reg);
521 break;
522 case 1: /* register 16-31 */
523 spin_lock_irqsave(&lp->bank_lock, flags);
524 MACEBANK(1);
525 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
526 MACEBANK(0);
527 spin_unlock_irqrestore(&lp->bank_lock, flags);
528 break;
529 }
530 return (data & 0xFF);
531} /* mace_read */
532
533/* ----------------------------------------------------------------------------
534mace_write
535 Writes to a MACE register. This is bank independent; however,
536 the caller must ensure that this call is not interruptable. We
537 are assuming that during normal operation, the MACE is always in
538 bank 0.
539---------------------------------------------------------------------------- */
906da809
OJ		 540static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
541 int data)
1da177e4
LT		 542{
543 unsigned long flags;
544
545 switch (reg >> 4) {
546 case 0: /* register 0-15 */
547 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
548 break;
549 case 1: /* register 16-31 */
550 spin_lock_irqsave(&lp->bank_lock, flags);
551 MACEBANK(1);
552 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
553 MACEBANK(0);
554 spin_unlock_irqrestore(&lp->bank_lock, flags);
555 break;
556 }
557} /* mace_write */
558
559/* ----------------------------------------------------------------------------
560mace_init
561 Resets the MACE chip.
562---------------------------------------------------------------------------- */
906da809 563static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
1da177e4
LT		 564{
565 int i;
566 int ct = 0;
567
568 /* MACE Software reset */
569 mace_write(lp, ioaddr, MACE_BIUCC, 1);
570 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
571 /* Wait for reset bit to be cleared automatically after <= 200ns */;
572 if(++ct > 500)
573 {
574 printk(KERN_ERR "mace: reset failed, card removed ?\n");
575 return -1;
576 }
577 udelay(1);
578 }
579 mace_write(lp, ioaddr, MACE_BIUCC, 0);
580
581 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
582 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
583
584 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
585 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
586
587 /*
588 * Bit 2-1 PORTSEL[1-0] Port Select.
589 * 00 AUI/10Base-2
590 * 01 10Base-T
591 * 10 DAI Port (reserved in Am2150)
592 * 11 GPSI
593 * For this card, only the first two are valid.
594 * So, PLSCC should be set to
595 * 0x00 for 10Base-2
596 * 0x02 for 10Base-T
597 * Or just set ASEL in PHYCC below!
598 */
599 switch (if_port) {
600 case 1:
601 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
602 break;
603 case 2:
604 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
605 break;
606 default:
607 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
608 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
609 and the MACE device will automatically select the operating media
610 interface port. */
611 break;
612 }
613
614 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
615 /* Poll ADDRCHG bit */
616 ct = 0;
617 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
618 {
619 if(++ ct > 500)
620 {
621 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
622 return -1;
623 }
624 }
625 /* Set PADR register */
626 for (i = 0; i < ETHER_ADDR_LEN; i++)
627 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
628
629 /* MAC Configuration Control Register should be written last */
630 /* Let set_multicast_list set this. */
631 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
632 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
633 return 0;
634} /* mace_init */
635
636/* ----------------------------------------------------------------------------
637nmclan_config
638 This routine is scheduled to run after a CARD_INSERTION event
639 is received, to configure the PCMCIA socket, and to make the
640 ethernet device available to the system.
641---------------------------------------------------------------------------- */
642
15b99ac1 643static int nmclan_config(struct pcmcia_device *link)
1da177e4 644{
1da177e4
LT		 645 struct net_device *dev = link->priv;
646 mace_private *lp = netdev_priv(dev);
dddfbd82
DB		 647 u8 *buf;
648 size_t len;
dd0fab5b 649 int i, ret;
906da809 650 unsigned int ioaddr;
1da177e4 651
dd0fab5b
DB		 652 dev_dbg(&link->dev, "nmclan_config\n");
653
654 ret = pcmcia_request_io(link, &link->io);
655 if (ret)
656 goto failed;
657 ret = pcmcia_request_irq(link, &link->irq);
658 if (ret)
659 goto failed;
660 ret = pcmcia_request_configuration(link, &link->conf);
661 if (ret)
662 goto failed;
1da177e4 663
1da177e4
LT		 664 dev->irq = link->irq.AssignedIRQ;
665 dev->base_addr = link->io.BasePort1;
666
667 ioaddr = dev->base_addr;
668
669 /* Read the ethernet address from the CIS. */
dddfbd82
DB		 670 len = pcmcia_get_tuple(link, 0x80, &buf);
671 if (!buf || len < ETHER_ADDR_LEN) {
672 kfree(buf);
673 goto failed;
674 }
675 memcpy(dev->dev_addr, buf, ETHER_ADDR_LEN);
676 kfree(buf);
1da177e4
LT		 677
678 /* Verify configuration by reading the MACE ID. */
679 {
680 char sig[2];
681
682 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
683 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
684 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
dd0fab5b 685 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
1da177e4
LT		 686 sig[0], sig[1]);
687 } else {
688 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
689 " be 0x40 0x?9\n", sig[0], sig[1]);
15b99ac1 690 return -ENODEV;
1da177e4
LT		 691 }
692 }
693
694 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
695 goto failed;
696
697 /* The if_port symbol can be set when the module is loaded */
698 if (if_port <= 2)
699 dev->if_port = if_port;
700 else
701 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
702
fd238232 703 link->dev_node = &lp->node;
fba395ee 704 SET_NETDEV_DEV(dev, &handle_to_dev(link));
1da177e4
LT		 705
706 i = register_netdev(dev);
707 if (i != 0) {
708 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
fd238232 709 link->dev_node = NULL;
1da177e4
LT		 710 goto failed;
711 }
712
713 strcpy(lp->node.dev_name, dev->name);
714
0795af57 715 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port,"
e174961c 716 " hw_addr %pM\n",
0795af57 717 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port],
e174961c 718 dev->dev_addr);
15b99ac1 719 return 0;
1da177e4 720
1da177e4 721failed:
15b99ac1
DB		 722 nmclan_release(link);
723 return -ENODEV;
1da177e4
LT		 724} /* nmclan_config */
725
726/* ----------------------------------------------------------------------------
727nmclan_release
728 After a card is removed, nmclan_release() will unregister the
729 net device, and release the PCMCIA configuration. If the device
730 is still open, this will be postponed until it is closed.
731---------------------------------------------------------------------------- */
fba395ee 732static void nmclan_release(struct pcmcia_device *link)
1da177e4 733{
dd0fab5b 734 dev_dbg(&link->dev, "nmclan_release\n");
fba395ee 735 pcmcia_disable_device(link);
1da177e4
LT		 736}
737
fba395ee 738static int nmclan_suspend(struct pcmcia_device *link)
98e4c28b 739{
98e4c28b
DB		 740 struct net_device *dev = link->priv;
741
e2d40963 742 if (link->open)
8661bb5b 743 netif_device_detach(dev);
98e4c28b
DB		 744
745 return 0;
746}
747
fba395ee 748static int nmclan_resume(struct pcmcia_device *link)
98e4c28b 749{
98e4c28b
DB		 750 struct net_device *dev = link->priv;
751
e2d40963 752 if (link->open) {
8661bb5b
DB		 753 nmclan_reset(dev);
754 netif_device_attach(dev);
98e4c28b
DB		 755 }
756
757 return 0;
758}
759
1da177e4
LT		 760
761/* ----------------------------------------------------------------------------
762nmclan_reset
763 Reset and restore all of the Xilinx and MACE registers.
764---------------------------------------------------------------------------- */
765static void nmclan_reset(struct net_device *dev)
766{
767 mace_private *lp = netdev_priv(dev);
768
769#if RESET_XILINX
fba395ee 770 struct pcmcia_device *link = &lp->link;
1da177e4
LT		 771 conf_reg_t reg;
772 u_long OrigCorValue;
773
774 /* Save original COR value */
775 reg.Function = 0;
776 reg.Action = CS_READ;
777 reg.Offset = CISREG_COR;
778 reg.Value = 0;
fba395ee 779 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 780 OrigCorValue = reg.Value;
781
782 /* Reset Xilinx */
783 reg.Action = CS_WRITE;
784 reg.Offset = CISREG_COR;
dd0fab5b 785 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
1da177e4
LT		 786 OrigCorValue);
787 reg.Value = COR_SOFT_RESET;
fba395ee 788 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 789 /* Need to wait for 20 ms for PCMCIA to finish reset. */
790
791 /* Restore original COR configuration index */
792 reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
fba395ee 793 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 794 /* Xilinx is now completely reset along with the MACE chip. */
795 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
796
797#endif /* #if RESET_XILINX */
798
799 /* Xilinx is now completely reset along with the MACE chip. */
800 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
801
802 /* Reinitialize the MACE chip for operation. */
803 mace_init(lp, dev->base_addr, dev->dev_addr);
804 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
805
806 /* Restore the multicast list and enable TX and RX. */
807 restore_multicast_list(dev);
808} /* nmclan_reset */
809
810/* ----------------------------------------------------------------------------
811mace_config
812 [Someone tell me what this is supposed to do? Is if_port a defined
813 standard? If so, there should be defines to indicate 1=10Base-T,
814 2=10Base-2, etc. including limited automatic detection.]
815---------------------------------------------------------------------------- */
816static int mace_config(struct net_device *dev, struct ifmap *map)
817{
818 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
819 if (map->port <= 2) {
820 dev->if_port = map->port;
821 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
822 if_names[dev->if_port]);
823 } else
824 return -EINVAL;
825 }
826 return 0;
827} /* mace_config */
828
829/* ----------------------------------------------------------------------------
830mace_open
831 Open device driver.
832---------------------------------------------------------------------------- */
833static int mace_open(struct net_device *dev)
834{
906da809 835 unsigned int ioaddr = dev->base_addr;
1da177e4 836 mace_private *lp = netdev_priv(dev);
fba395ee 837 struct pcmcia_device *link = lp->p_dev;
1da177e4 838
9940ec36 839 if (!pcmcia_dev_present(link))
1da177e4
LT		 840 return -ENODEV;
841
842 link->open++;
843
844 MACEBANK(0);
845
846 netif_start_queue(dev);
847 nmclan_reset(dev);
848
849 return 0; /* Always succeed */
850} /* mace_open */
851
852/* ----------------------------------------------------------------------------
853mace_close
854 Closes device driver.
855---------------------------------------------------------------------------- */
856static int mace_close(struct net_device *dev)
857{
906da809 858 unsigned int ioaddr = dev->base_addr;
1da177e4 859 mace_private *lp = netdev_priv(dev);
fba395ee 860 struct pcmcia_device *link = lp->p_dev;
1da177e4 861
dd0fab5b 862 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
1da177e4
LT		 863
864 /* Mask off all interrupts from the MACE chip. */
865 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
866
867 link->open--;
868 netif_stop_queue(dev);
869
870 return 0;
871} /* mace_close */
872
873static void netdev_get_drvinfo(struct net_device *dev,
874 struct ethtool_drvinfo *info)
875{
876 strcpy(info->driver, DRV_NAME);
877 strcpy(info->version, DRV_VERSION);
878 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
879}
880
7282d491 881static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4 882 .get_drvinfo = netdev_get_drvinfo,
1da177e4
LT		 883};
884
885/* ----------------------------------------------------------------------------
886mace_start_xmit
887 This routine begins the packet transmit function. When completed,
888 it will generate a transmit interrupt.
889
890 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
891 returns 0, the "packet is now solely the responsibility of the
892 driver." If _start_xmit returns non-zero, the "transmission
893 failed, put skb back into a list."
894---------------------------------------------------------------------------- */
895
896static void mace_tx_timeout(struct net_device *dev)
897{
898 mace_private *lp = netdev_priv(dev);
fba395ee 899 struct pcmcia_device *link = lp->p_dev;
1da177e4
LT		 900
901 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
902#if RESET_ON_TIMEOUT
903 printk("resetting card\n");
994917f8 904 pcmcia_reset_card(link->socket);
1da177e4
LT		 905#else /* #if RESET_ON_TIMEOUT */
906 printk("NOT resetting card\n");
907#endif /* #if RESET_ON_TIMEOUT */
908 dev->trans_start = jiffies;
909 netif_wake_queue(dev);
910}
911
dbf02fae
SH		 912static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
913 struct net_device *dev)
1da177e4
LT		 914{
915 mace_private *lp = netdev_priv(dev);
906da809 916 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 917
918 netif_stop_queue(dev);
919
dd0fab5b 920 pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
1da177e4
LT		 921 dev->name, (long)skb->len);
922
923#if (!TX_INTERRUPTABLE)
924 /* Disable MACE TX interrupts. */
925 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
926 ioaddr + AM2150_MACE_BASE + MACE_IMR);
927 lp->tx_irq_disabled=1;
928#endif /* #if (!TX_INTERRUPTABLE) */
929
930 {
931 /* This block must not be interrupted by another transmit request!
932 mace_tx_timeout will take care of timer-based retransmissions from
933 the upper layers. The interrupt handler is guaranteed never to
934 service a transmit interrupt while we are in here.
935 */
936
937 lp->linux_stats.tx_bytes += skb->len;
938 lp->tx_free_frames--;
939
940 /* WARNING: Write the _exact_ number of bytes written in the header! */
941 /* Put out the word header [must be an outw()] . . . */
942 outw(skb->len, ioaddr + AM2150_XMT);
943 /* . . . and the packet [may be any combination of outw() and outb()] */
944 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
945 if (skb->len & 1) {
946 /* Odd byte transfer */
947 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
948 }
949
950 dev->trans_start = jiffies;
951
952#if MULTI_TX
953 if (lp->tx_free_frames > 0)
954 netif_start_queue(dev);
955#endif /* #if MULTI_TX */
956 }
957
958#if (!TX_INTERRUPTABLE)
959 /* Re-enable MACE TX interrupts. */
960 lp->tx_irq_disabled=0;
961 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
962#endif /* #if (!TX_INTERRUPTABLE) */
963
964 dev_kfree_skb(skb);
965
6ed10654 966 return NETDEV_TX_OK;
1da177e4
LT		 967} /* mace_start_xmit */
968
969/* ----------------------------------------------------------------------------
970mace_interrupt
971 The interrupt handler.
972---------------------------------------------------------------------------- */
7d12e780 973static irqreturn_t mace_interrupt(int irq, void *dev_id)
1da177e4
LT		 974{
975 struct net_device *dev = (struct net_device *) dev_id;
976 mace_private *lp = netdev_priv(dev);
906da809 977 unsigned int ioaddr;
1da177e4
LT		 978 int status;
979 int IntrCnt = MACE_MAX_IR_ITERATIONS;
980
981 if (dev == NULL) {
dd0fab5b 982 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
1da177e4
LT		 983 irq);
984 return IRQ_NONE;
985 }
986
c196d80f
MG		 987 ioaddr = dev->base_addr;
988
1da177e4
LT		 989 if (lp->tx_irq_disabled) {
990 printk(
991 (lp->tx_irq_disabled?
992 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
993 "[isr=%02X, imr=%02X]\n":
994 KERN_NOTICE "%s: Re-entering the interrupt handler "
995 "[isr=%02X, imr=%02X]\n"),
996 dev->name,
997 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
998 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
999 );
1000 /* WARNING: MACE_IR has been read! */
1001 return IRQ_NONE;
1002 }
1003
1004 if (!netif_device_present(dev)) {
dd0fab5b 1005 pr_debug("%s: interrupt from dead card\n", dev->name);
1da177e4
LT		 1006 return IRQ_NONE;
1007 }
1008
1009 do {
1010 /* WARNING: MACE_IR is a READ/CLEAR port! */
1011 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1012
dd0fab5b 1013 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1da177e4
LT		 1014
1015 if (status & MACE_IR_RCVINT) {
1016 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1017 }
1018
1019 if (status & MACE_IR_XMTINT) {
1020 unsigned char fifofc;
1021 unsigned char xmtrc;
1022 unsigned char xmtfs;
1023
1024 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1025 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1026 lp->linux_stats.tx_errors++;
1027 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1028 }
1029
1030 /* Transmit Retry Count (XMTRC, reg 4) */
1031 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1032 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1033 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1034
1035 if (
1036 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1037 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1038 ) {
1039 lp->mace_stats.xmtsv++;
1040
1041 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1042 if (xmtfs & MACE_XMTFS_UFLO) {
1043 /* Underflow. Indicates that the Transmit FIFO emptied before
1044 the end of frame was reached. */
1045 lp->mace_stats.uflo++;
1046 }
1047 if (xmtfs & MACE_XMTFS_LCOL) {
1048 /* Late Collision */
1049 lp->mace_stats.lcol++;
1050 }
1051 if (xmtfs & MACE_XMTFS_MORE) {
1052 /* MORE than one retry was needed */
1053 lp->mace_stats.more++;
1054 }
1055 if (xmtfs & MACE_XMTFS_ONE) {
1056 /* Exactly ONE retry occurred */
1057 lp->mace_stats.one++;
1058 }
1059 if (xmtfs & MACE_XMTFS_DEFER) {
1060 /* Transmission was defered */
1061 lp->mace_stats.defer++;
1062 }
1063 if (xmtfs & MACE_XMTFS_LCAR) {
1064 /* Loss of carrier */
1065 lp->mace_stats.lcar++;
1066 }
1067 if (xmtfs & MACE_XMTFS_RTRY) {
1068 /* Retry error: transmit aborted after 16 attempts */
1069 lp->mace_stats.rtry++;
1070 }
1071 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1072
1073 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1074
1075 lp->linux_stats.tx_packets++;
1076 lp->tx_free_frames++;
1077 netif_wake_queue(dev);
1078 } /* if (status & MACE_IR_XMTINT) */
1079
1080 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1081 if (status & MACE_IR_JAB) {
1082 /* Jabber Error. Excessive transmit duration (20-150ms). */
1083 lp->mace_stats.jab++;
1084 }
1085 if (status & MACE_IR_BABL) {
1086 /* Babble Error. >1518 bytes transmitted. */
1087 lp->mace_stats.babl++;
1088 }
1089 if (status & MACE_IR_CERR) {
1090 /* Collision Error. CERR indicates the absence of the
1091 Signal Quality Error Test message after a packet
1092 transmission. */
1093 lp->mace_stats.cerr++;
1094 }
1095 if (status & MACE_IR_RCVCCO) {
1096 /* Receive Collision Count Overflow; */
1097 lp->mace_stats.rcvcco++;
1098 }
1099 if (status & MACE_IR_RNTPCO) {
1100 /* Runt Packet Count Overflow */
1101 lp->mace_stats.rntpco++;
1102 }
1103 if (status & MACE_IR_MPCO) {
1104 /* Missed Packet Count Overflow */
1105 lp->mace_stats.mpco++;
1106 }
1107 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1108
1109 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1110
1111 return IRQ_HANDLED;
1112} /* mace_interrupt */
1113
1114/* ----------------------------------------------------------------------------
1115mace_rx
1116 Receives packets.
1117---------------------------------------------------------------------------- */
1118static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1119{
1120 mace_private *lp = netdev_priv(dev);
906da809 1121 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1122 unsigned char rx_framecnt;
1123 unsigned short rx_status;
1124
1125 while (
1126 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1127 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1128 (RxCnt--)
1129 ) {
1130 rx_status = inw(ioaddr + AM2150_RCV);
1131
dd0fab5b 1132 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1da177e4
LT		 1133 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1134
1135 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1136 lp->linux_stats.rx_errors++;
1137 if (rx_status & MACE_RCVFS_OFLO) {
1138 lp->mace_stats.oflo++;
1139 }
1140 if (rx_status & MACE_RCVFS_CLSN) {
1141 lp->mace_stats.clsn++;
1142 }
1143 if (rx_status & MACE_RCVFS_FRAM) {
1144 lp->mace_stats.fram++;
1145 }
1146 if (rx_status & MACE_RCVFS_FCS) {
1147 lp->mace_stats.fcs++;
1148 }
1149 } else {
1150 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1151 /* Auto Strip is off, always subtract 4 */
1152 struct sk_buff *skb;
1153
1154 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1155 /* runt packet count */
1156 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1157 /* rcv collision count */
1158
dd0fab5b 1159 pr_debug(" receiving packet size 0x%X rx_status"
1da177e4
LT		 1160 " 0x%X.\n", pkt_len, rx_status);
1161
1162 skb = dev_alloc_skb(pkt_len+2);
1163
1164 if (skb != NULL) {
1da177e4
LT		 1165 skb_reserve(skb, 2);
1166 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1167 if (pkt_len & 1)
27a884dc 1168 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1da177e4
LT		 1169 skb->protocol = eth_type_trans(skb, dev);
1170
1171 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1172
1da177e4 1173 lp->linux_stats.rx_packets++;
6f258910 1174 lp->linux_stats.rx_bytes += pkt_len;
1da177e4
LT		 1175 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1176 continue;
1177 } else {
dd0fab5b 1178 pr_debug("%s: couldn't allocate a sk_buff of size"
1da177e4
LT		 1179 " %d.\n", dev->name, pkt_len);
1180 lp->linux_stats.rx_dropped++;
1181 }
1182 }
1183 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1184 } /* while */
1185
1186 return 0;
1187} /* mace_rx */
1188
1189/* ----------------------------------------------------------------------------
1190pr_linux_stats
1191---------------------------------------------------------------------------- */
1192static void pr_linux_stats(struct net_device_stats *pstats)
1193{
dd0fab5b
DB		 1194 pr_debug("pr_linux_stats\n");
1195 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n",
1da177e4 1196 (long)pstats->rx_packets, (long)pstats->tx_packets);
dd0fab5b 1197 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n",
1da177e4 1198 (long)pstats->rx_errors, (long)pstats->tx_errors);
dd0fab5b 1199 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n",
1da177e4 1200 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
dd0fab5b 1201 pr_debug(" multicast=%-7ld collisions=%ld\n",
1da177e4
LT		 1202 (long)pstats->multicast, (long)pstats->collisions);
1203
dd0fab5b 1204 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n",
1da177e4 1205 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
dd0fab5b 1206 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1da177e4 1207 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
dd0fab5b 1208 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1da177e4
LT		 1209 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1210
dd0fab5b 1211 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1da177e4 1212 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
dd0fab5b 1213 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1da177e4 1214 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
dd0fab5b 1215 pr_debug(" tx_window_errors=%ld\n",
1da177e4
LT		 1216 (long)pstats->tx_window_errors);
1217} /* pr_linux_stats */
1218
1219/* ----------------------------------------------------------------------------
1220pr_mace_stats
1221---------------------------------------------------------------------------- */
1222static void pr_mace_stats(mace_statistics *pstats)
1223{
dd0fab5b 1224 pr_debug("pr_mace_stats\n");
1da177e4 1225
dd0fab5b 1226 pr_debug(" xmtsv=%-7d uflo=%d\n",
1da177e4 1227 pstats->xmtsv, pstats->uflo);
dd0fab5b 1228 pr_debug(" lcol=%-7d more=%d\n",
1da177e4 1229 pstats->lcol, pstats->more);
dd0fab5b 1230 pr_debug(" one=%-7d defer=%d\n",
1da177e4 1231 pstats->one, pstats->defer);
dd0fab5b 1232 pr_debug(" lcar=%-7d rtry=%d\n",
1da177e4
LT		 1233 pstats->lcar, pstats->rtry);
1234
1235 /* MACE_XMTRC */
dd0fab5b 1236 pr_debug(" exdef=%-7d xmtrc=%d\n",
1da177e4
LT		 1237 pstats->exdef, pstats->xmtrc);
1238
1239 /* RFS1--Receive Status (RCVSTS) */
dd0fab5b 1240 pr_debug(" oflo=%-7d clsn=%d\n",
1da177e4 1241 pstats->oflo, pstats->clsn);
dd0fab5b 1242 pr_debug(" fram=%-7d fcs=%d\n",
1da177e4
LT		 1243 pstats->fram, pstats->fcs);
1244
1245 /* RFS2--Runt Packet Count (RNTPC) */
1246 /* RFS3--Receive Collision Count (RCVCC) */
dd0fab5b 1247 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1da177e4
LT		 1248 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1249
1250 /* MACE_IR */
dd0fab5b 1251 pr_debug(" jab=%-7d babl=%d\n",
1da177e4 1252 pstats->jab, pstats->babl);
dd0fab5b 1253 pr_debug(" cerr=%-7d rcvcco=%d\n",
1da177e4 1254 pstats->cerr, pstats->rcvcco);
dd0fab5b 1255 pr_debug(" rntpco=%-7d mpco=%d\n",
1da177e4
LT		 1256 pstats->rntpco, pstats->mpco);
1257
1258 /* MACE_MPC */
dd0fab5b 1259 pr_debug(" mpc=%d\n", pstats->mpc);
1da177e4
LT		 1260
1261 /* MACE_RNTPC */
dd0fab5b 1262 pr_debug(" rntpc=%d\n", pstats->rntpc);
1da177e4
LT		 1263
1264 /* MACE_RCVCC */
dd0fab5b 1265 pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1da177e4
LT		 1266
1267} /* pr_mace_stats */
1268
1269/* ----------------------------------------------------------------------------
1270update_stats
1271 Update statistics. We change to register window 1, so this
1272 should be run single-threaded if the device is active. This is
1273 expected to be a rare operation, and it's simpler for the rest
1274 of the driver to assume that window 0 is always valid rather
1275 than use a special window-state variable.
1276
1277 oflo & uflo should _never_ occur since it would mean the Xilinx
1278 was not able to transfer data between the MACE FIFO and the
1279 card's SRAM fast enough. If this happens, something is
1280 seriously wrong with the hardware.
1281---------------------------------------------------------------------------- */
906da809 1282static void update_stats(unsigned int ioaddr, struct net_device *dev)
1da177e4
LT		 1283{
1284 mace_private *lp = netdev_priv(dev);
1285
1286 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1287 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1288 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1289 /* At this point, mace_stats is fully updated for this call.
1290 We may now update the linux_stats. */
1291
1292 /* The MACE has no equivalent for linux_stats field which are commented
1293 out. */
1294
1295 /* lp->linux_stats.multicast; */
1296 lp->linux_stats.collisions =
1297 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1298 /* Collision: The MACE may retry sending a packet 15 times
1299 before giving up. The retry count is in XMTRC.
1300 Does each retry constitute a collision?
1301 If so, why doesn't the RCVCC record these collisions? */
1302
1303 /* detailed rx_errors: */
1304 lp->linux_stats.rx_length_errors =
1305 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1306 /* lp->linux_stats.rx_over_errors */
1307 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1308 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1309 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1310 lp->linux_stats.rx_missed_errors =
1311 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1312
1313 /* detailed tx_errors */
1314 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1315 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1316 /* LCAR usually results from bad cabling. */
1317 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1318 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1319 /* lp->linux_stats.tx_window_errors; */
1320
1321 return;
1322} /* update_stats */
1323
1324/* ----------------------------------------------------------------------------
1325mace_get_stats
1326 Gathers ethernet statistics from the MACE chip.
1327---------------------------------------------------------------------------- */
1328static struct net_device_stats *mace_get_stats(struct net_device *dev)
1329{
1330 mace_private *lp = netdev_priv(dev);
1331
1332 update_stats(dev->base_addr, dev);
1333
dd0fab5b 1334 pr_debug("%s: updating the statistics.\n", dev->name);
1da177e4
LT		 1335 pr_linux_stats(&lp->linux_stats);
1336 pr_mace_stats(&lp->mace_stats);
1337
1338 return &lp->linux_stats;
1339} /* net_device_stats */
1340
1341/* ----------------------------------------------------------------------------
1342updateCRC
1343 Modified from Am79C90 data sheet.
1344---------------------------------------------------------------------------- */
1345
1346#ifdef BROKEN_MULTICAST
1347
1348static void updateCRC(int *CRC, int bit)
1349{
1350 int poly[]={
1351 1,1,1,0, 1,1,0,1,
1352 1,0,1,1, 1,0,0,0,
1353 1,0,0,0, 0,0,1,1,
1354 0,0,1,0, 0,0,0,0
1355 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1356 CRC generator polynomial. */
1357
1358 int j;
1359
1360 /* shift CRC and control bit (CRC[32]) */
1361 for (j = 32; j > 0; j--)
1362 CRC[j] = CRC[j-1];
1363 CRC[0] = 0;
1364
1365 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1366 if (bit ^ CRC[32])
1367 for (j = 0; j < 32; j++)
1368 CRC[j] ^= poly[j];
1369} /* updateCRC */
1370
1371/* ----------------------------------------------------------------------------
1372BuildLAF
1373 Build logical address filter.
1374 Modified from Am79C90 data sheet.
1375
1376Input
1377 ladrf: logical address filter (contents initialized to 0)
1378 adr: ethernet address
1379---------------------------------------------------------------------------- */
1380static void BuildLAF(int *ladrf, int *adr)
1381{
1382 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1383
1384 int i, byte; /* temporary array indices */
1385 int hashcode; /* the output object */
1386
1387 CRC[32]=0;
1388
1389 for (byte = 0; byte < 6; byte++)
1390 for (i = 0; i < 8; i++)
1391 updateCRC(CRC, (adr[byte] >> i) & 1);
1392
1393 hashcode = 0;
1394 for (i = 0; i < 6; i++)
1395 hashcode = (hashcode << 1) + CRC[i];
1396
1397 byte = hashcode >> 3;
1398 ladrf[byte] |= (1 << (hashcode & 7));
1399
1400#ifdef PCMCIA_DEBUG
dd0fab5b 1401 if (0)
ad361c98
JP		 1402 printk(KERN_DEBUG " adr =%pM\n", adr);
1403 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1404 for (i = 0; i < 8; i++)
1405 printk(KERN_CONT " %02X", ladrf[i]);
1406 printk(KERN_CONT "\n");
1da177e4
LT		 1407 }
1408#endif
1409} /* BuildLAF */
1410
1411/* ----------------------------------------------------------------------------
1412restore_multicast_list
1413 Restores the multicast filter for MACE chip to the last
1414 set_multicast_list() call.
1415
1416Input
1417 multicast_num_addrs
1418 multicast_ladrf[]
1419---------------------------------------------------------------------------- */
1420static void restore_multicast_list(struct net_device *dev)
1421{
1422 mace_private *lp = netdev_priv(dev);
1423 int num_addrs = lp->multicast_num_addrs;
1424 int *ladrf = lp->multicast_ladrf;
906da809 1425 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1426 int i;
1427
dd0fab5b 1428 pr_debug("%s: restoring Rx mode to %d addresses.\n",
1da177e4
LT		 1429 dev->name, num_addrs);
1430
1431 if (num_addrs > 0) {
1432
dd0fab5b 1433 pr_debug("Attempt to restore multicast list detected.\n");
1da177e4
LT		 1434
1435 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1436 /* Poll ADDRCHG bit */
1437 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1438 ;
1439 /* Set LADRF register */
1440 for (i = 0; i < MACE_LADRF_LEN; i++)
1441 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1442
1443 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1444 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1445
1446 } else if (num_addrs < 0) {
1447
1448 /* Promiscuous mode: receive all packets */
1449 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1450 mace_write(lp, ioaddr, MACE_MACCC,
1451 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1452 );
1453
1454 } else {
1455
1456 /* Normal mode */
1457 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1458 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1459
1460 }
1461} /* restore_multicast_list */
1462
1463/* ----------------------------------------------------------------------------
1464set_multicast_list
1465 Set or clear the multicast filter for this adaptor.
1466
1467Input
1468 num_addrs == -1 Promiscuous mode, receive all packets
1469 num_addrs == 0 Normal mode, clear multicast list
1470 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1471 best-effort filtering.
1472Output
1473 multicast_num_addrs
1474 multicast_ladrf[]
1475---------------------------------------------------------------------------- */
1476
1477static void set_multicast_list(struct net_device *dev)
1478{
1479 mace_private *lp = netdev_priv(dev);
1480 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1481 int i;
1482 struct dev_mc_list *dmi = dev->mc_list;
1483
1484#ifdef PCMCIA_DEBUG
dd0fab5b 1485 {
1da177e4
LT		 1486 static int old;
1487 if (dev->mc_count != old) {
1488 old = dev->mc_count;
dd0fab5b 1489 pr_debug("%s: setting Rx mode to %d addresses.\n",
1da177e4
LT		 1490 dev->name, old);
1491 }
1492 }
1493#endif
1494
1495 /* Set multicast_num_addrs. */
1496 lp->multicast_num_addrs = dev->mc_count;
1497
1498 /* Set multicast_ladrf. */
1499 if (num_addrs > 0) {
1500 /* Calculate multicast logical address filter */
1501 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1502 for (i = 0; i < dev->mc_count; i++) {
1503 memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1504 dmi = dmi->next;
1505 BuildLAF(lp->multicast_ladrf, adr);
1506 }
1507 }
1508
1509 restore_multicast_list(dev);
1510
1511} /* set_multicast_list */
1512
1513#endif /* BROKEN_MULTICAST */
1514
1515static void restore_multicast_list(struct net_device *dev)
1516{
906da809 1517 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1518 mace_private *lp = netdev_priv(dev);
1519
dd0fab5b 1520 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1da177e4
LT		 1521 lp->multicast_num_addrs);
1522
1523 if (dev->flags & IFF_PROMISC) {
1524 /* Promiscuous mode: receive all packets */
1525 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1526 mace_write(lp, ioaddr, MACE_MACCC,
1527 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1528 );
1529 } else {
1530 /* Normal mode */
1531 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1532 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1533 }
1534} /* restore_multicast_list */
1535
1536static void set_multicast_list(struct net_device *dev)
1537{
1538 mace_private *lp = netdev_priv(dev);
1539
1540#ifdef PCMCIA_DEBUG
dd0fab5b 1541 {
1da177e4
LT		 1542 static int old;
1543 if (dev->mc_count != old) {
1544 old = dev->mc_count;
dd0fab5b 1545 pr_debug("%s: setting Rx mode to %d addresses.\n",
1da177e4
LT		 1546 dev->name, old);
1547 }
1548 }
1549#endif
1550
1551 lp->multicast_num_addrs = dev->mc_count;
1552 restore_multicast_list(dev);
1553
1554} /* set_multicast_list */
1555
a58e26cb
DB		 1556static struct pcmcia_device_id nmclan_ids[] = {
1557 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
d277ad0e 1558 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
a58e26cb
DB		 1559 PCMCIA_DEVICE_NULL,
1560};
1561MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1562
1da177e4
LT		 1563static struct pcmcia_driver nmclan_cs_driver = {
1564 .owner = THIS_MODULE,
1565 .drv = {
1566 .name = "nmclan_cs",
1567 },
15b99ac1 1568 .probe = nmclan_probe,
cc3b4866 1569 .remove = nmclan_detach,
a58e26cb 1570 .id_table = nmclan_ids,
98e4c28b
DB		 1571 .suspend = nmclan_suspend,
1572 .resume = nmclan_resume,
1da177e4
LT		 1573};
1574
1575static int __init init_nmclan_cs(void)
1576{
1577 return pcmcia_register_driver(&nmclan_cs_driver);
1578}
1579
1580static void __exit exit_nmclan_cs(void)
1581{
1582 pcmcia_unregister_driver(&nmclan_cs_driver);
1da177e4
LT		 1583}
1584
1585module_init(init_nmclan_cs);
1586module_exit(exit_nmclan_cs);
Linux kernel - Deliverables
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