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[deliverable/linux.git] / drivers / net / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24#define DRV_NAME "pcnet32"
7de745e5
DF		 25#ifdef CONFIG_PCNET32_NAPI
26#define DRV_VERSION "1.33-NAPI"
27#else
28#define DRV_VERSION "1.33"
29#endif
30#define DRV_RELDATE "27.Jun.2006"
1da177e4
LT		 31#define PFX DRV_NAME ": "
32
4a5e8e29
JG		 33static const char *const version =
34 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/string.h>
39#include <linux/errno.h>
40#include <linux/ioport.h>
41#include <linux/slab.h>
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/delay.h>
45#include <linux/init.h>
46#include <linux/ethtool.h>
47#include <linux/mii.h>
48#include <linux/crc32.h>
49#include <linux/netdevice.h>
50#include <linux/etherdevice.h>
51#include <linux/skbuff.h>
52#include <linux/spinlock.h>
53#include <linux/moduleparam.h>
54#include <linux/bitops.h>
55
56#include <asm/dma.h>
57#include <asm/io.h>
58#include <asm/uaccess.h>
59#include <asm/irq.h>
60
61/*
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
63 */
64static struct pci_device_id pcnet32_pci_tbl[] = {
f2622a2b
DF		 65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
4a5e8e29
JG		 67
68 /*
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
71 */
f2622a2b
DF		 72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
4a5e8e29
JG		 74
75 { } /* terminate list */
1da177e4
LT		 76};
77
4a5e8e29 78MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 79
80static int cards_found;
81
82/*
83 * VLB I/O addresses
84 */
85static unsigned int pcnet32_portlist[] __initdata =
4a5e8e29 86 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4
LT		 87
88static int pcnet32_debug = 0;
4a5e8e29
JG		 89static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 91
92static struct net_device *pcnet32_dev;
93
94static int max_interrupt_work = 2;
95static int rx_copybreak = 200;
96
97#define PCNET32_PORT_AUI 0x00
98#define PCNET32_PORT_10BT 0x01
99#define PCNET32_PORT_GPSI 0x02
100#define PCNET32_PORT_MII 0x03
101
102#define PCNET32_PORT_PORTSEL 0x03
103#define PCNET32_PORT_ASEL 0x04
104#define PCNET32_PORT_100 0x40
105#define PCNET32_PORT_FD 0x80
106
107#define PCNET32_DMA_MASK 0xffffffff
108
109#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
111
112/*
113 * table to translate option values from tulip
114 * to internal options
115 */
f71e1309 116static const unsigned char options_mapping[] = {
4a5e8e29
JG		 117 PCNET32_PORT_ASEL, /* 0 Auto-select */
118 PCNET32_PORT_AUI, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL, /* 3 not supported */
121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL, /* 5 not supported */
123 PCNET32_PORT_ASEL, /* 6 not supported */
124 PCNET32_PORT_ASEL, /* 7 not supported */
125 PCNET32_PORT_ASEL, /* 8 not supported */
126 PCNET32_PORT_MII, /* 9 MII 10baseT */
127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT, /* 12 10BaseT */
130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
133 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 134};
135
136static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 137 "Loopback test (offline)"
1da177e4 138};
4a5e8e29 139
1da177e4
LT		 140#define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
141
ac62ef04 142#define PCNET32_NUM_REGS 136
1da177e4 143
4a5e8e29 144#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 145static int options[MAX_UNITS];
146static int full_duplex[MAX_UNITS];
147static int homepna[MAX_UNITS];
148
149/*
150 * Theory of Operation
151 *
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
157 */
158
1da177e4
LT		 159/*
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
163 */
164#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 165#define PCNET32_LOG_TX_BUFFERS 4
166#define PCNET32_LOG_RX_BUFFERS 5
167#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 169#endif
170
171#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 172#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 173
174#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 175#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4
LT		 176
177#define PKT_BUF_SZ 1544
178
179/* Offsets from base I/O address. */
180#define PCNET32_WIO_RDP 0x10
181#define PCNET32_WIO_RAP 0x12
182#define PCNET32_WIO_RESET 0x14
183#define PCNET32_WIO_BDP 0x16
184
185#define PCNET32_DWIO_RDP 0x10
186#define PCNET32_DWIO_RAP 0x14
187#define PCNET32_DWIO_RESET 0x18
188#define PCNET32_DWIO_BDP 0x1C
189
190#define PCNET32_TOTAL_SIZE 0x20
191
06c87850
DF		 192#define CSR0 0
193#define CSR0_INIT 0x1
194#define CSR0_START 0x2
195#define CSR0_STOP 0x4
196#define CSR0_TXPOLL 0x8
197#define CSR0_INTEN 0x40
198#define CSR0_IDON 0x0100
199#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200#define PCNET32_INIT_LOW 1
201#define PCNET32_INIT_HIGH 2
202#define CSR3 3
203#define CSR4 4
204#define CSR5 5
205#define CSR5_SUSPEND 0x0001
206#define CSR15 15
207#define PCNET32_MC_FILTER 8
208
8d916266
DF		 209#define PCNET32_79C970A 0x2621
210
1da177e4
LT		 211/* The PCNET32 Rx and Tx ring descriptors. */
212struct pcnet32_rx_head {
0b5bf225 213 u32 base;
b368a3fb 214 s16 buf_length; /* two`s complement of length */
0b5bf225
JG		 215 s16 status;
216 u32 msg_length;
217 u32 reserved;
1da177e4
LT		 218};
219
220struct pcnet32_tx_head {
0b5bf225 221 u32 base;
b368a3fb 222 s16 length; /* two`s complement of length */
0b5bf225
JG		 223 s16 status;
224 u32 misc;
225 u32 reserved;
1da177e4
LT		 226};
227
228/* The PCNET32 32-Bit initialization block, described in databook. */
229struct pcnet32_init_block {
0b5bf225
JG		 230 u16 mode;
231 u16 tlen_rlen;
232 u8 phys_addr[6];
233 u16 reserved;
234 u32 filter[2];
4a5e8e29 235 /* Receive and transmit ring base, along with extra bits. */
0b5bf225
JG		 236 u32 rx_ring;
237 u32 tx_ring;
1da177e4
LT		 238};
239
240/* PCnet32 access functions */
241struct pcnet32_access {
4a5e8e29
JG		 242 u16 (*read_csr) (unsigned long, int);
243 void (*write_csr) (unsigned long, int, u16);
244 u16 (*read_bcr) (unsigned long, int);
245 void (*write_bcr) (unsigned long, int, u16);
246 u16 (*read_rap) (unsigned long);
247 void (*write_rap) (unsigned long, u16);
248 void (*reset) (unsigned long);
1da177e4
LT		 249};
250
251/*
76209926
HWL		 252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 254 */
255struct pcnet32_private {
6ecb7667 256 struct pcnet32_init_block *init_block;
4a5e8e29 257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 258 struct pcnet32_rx_head *rx_ring;
259 struct pcnet32_tx_head *tx_ring;
6ecb7667
DF		 260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
261 returned by pci_alloc_consistent */
0b5bf225
JG		 262 struct pci_dev *pci_dev;
263 const char *name;
4a5e8e29 264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 265 struct sk_buff **tx_skbuff;
266 struct sk_buff **rx_skbuff;
267 dma_addr_t *tx_dma_addr;
268 dma_addr_t *rx_dma_addr;
269 struct pcnet32_access a;
270 spinlock_t lock; /* Guard lock */
271 unsigned int cur_rx, cur_tx; /* The next free ring entry */
272 unsigned int rx_ring_size; /* current rx ring size */
273 unsigned int tx_ring_size; /* current tx ring size */
274 unsigned int rx_mod_mask; /* rx ring modular mask */
275 unsigned int tx_mod_mask; /* tx ring modular mask */
276 unsigned short rx_len_bits;
277 unsigned short tx_len_bits;
278 dma_addr_t rx_ring_dma_addr;
279 dma_addr_t tx_ring_dma_addr;
280 unsigned int dirty_rx, /* ring entries to be freed. */
281 dirty_tx;
282
283 struct net_device_stats stats;
284 char tx_full;
285 char phycount; /* number of phys found */
286 int options;
287 unsigned int shared_irq:1, /* shared irq possible */
288 dxsuflo:1, /* disable transmit stop on uflo */
289 mii:1; /* mii port available */
290 struct net_device *next;
291 struct mii_if_info mii_if;
292 struct timer_list watchdog_timer;
293 struct timer_list blink_timer;
294 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 295
296 /* each bit indicates an available PHY */
0b5bf225 297 u32 phymask;
8d916266 298 unsigned short chip_version; /* which variant this is */
1da177e4
LT		 299};
300
4a5e8e29
JG		 301static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
302static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
303static int pcnet32_open(struct net_device *);
304static int pcnet32_init_ring(struct net_device *);
305static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
4a5e8e29 306static void pcnet32_tx_timeout(struct net_device *dev);
7d12e780 307static irqreturn_t pcnet32_interrupt(int, void *);
4a5e8e29 308static int pcnet32_close(struct net_device *);
1da177e4
LT		 309static struct net_device_stats *pcnet32_get_stats(struct net_device *);
310static void pcnet32_load_multicast(struct net_device *dev);
311static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 312static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 313static void pcnet32_watchdog(struct net_device *);
314static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 315static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
316 int val);
1da177e4
LT		 317static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
318static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 319 struct ethtool_test *eth_test, u64 * data);
320static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 321static int pcnet32_phys_id(struct net_device *dev, u32 data);
322static void pcnet32_led_blink_callback(struct net_device *dev);
323static int pcnet32_get_regs_len(struct net_device *dev);
324static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 325 void *ptr);
1bcd3153 326static void pcnet32_purge_tx_ring(struct net_device *dev);
a88c844c 327static int pcnet32_alloc_ring(struct net_device *dev, char *name);
eabf0415 328static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 329static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 330
4a5e8e29 331static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 332{
4a5e8e29
JG		 333 outw(index, addr + PCNET32_WIO_RAP);
334 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 335}
336
4a5e8e29 337static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 338{
4a5e8e29
JG		 339 outw(index, addr + PCNET32_WIO_RAP);
340 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 341}
342
4a5e8e29 343static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 344{
4a5e8e29
JG		 345 outw(index, addr + PCNET32_WIO_RAP);
346 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 347}
348
4a5e8e29 349static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 350{
4a5e8e29
JG		 351 outw(index, addr + PCNET32_WIO_RAP);
352 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 353}
354
4a5e8e29 355static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 356{
4a5e8e29 357 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 358}
359
4a5e8e29 360static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 361{
4a5e8e29 362 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 363}
364
4a5e8e29 365static void pcnet32_wio_reset(unsigned long addr)
1da177e4 366{
4a5e8e29 367 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 368}
369
4a5e8e29 370static int pcnet32_wio_check(unsigned long addr)
1da177e4 371{
4a5e8e29
JG		 372 outw(88, addr + PCNET32_WIO_RAP);
373 return (inw(addr + PCNET32_WIO_RAP) == 88);
1da177e4
LT		 374}
375
376static struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 377 .read_csr = pcnet32_wio_read_csr,
378 .write_csr = pcnet32_wio_write_csr,
379 .read_bcr = pcnet32_wio_read_bcr,
380 .write_bcr = pcnet32_wio_write_bcr,
381 .read_rap = pcnet32_wio_read_rap,
382 .write_rap = pcnet32_wio_write_rap,
383 .reset = pcnet32_wio_reset
1da177e4
LT		 384};
385
4a5e8e29 386static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 387{
4a5e8e29
JG		 388 outl(index, addr + PCNET32_DWIO_RAP);
389 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
1da177e4
LT		 390}
391
4a5e8e29 392static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 393{
4a5e8e29
JG		 394 outl(index, addr + PCNET32_DWIO_RAP);
395 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 396}
397
4a5e8e29 398static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 399{
4a5e8e29
JG		 400 outl(index, addr + PCNET32_DWIO_RAP);
401 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
1da177e4
LT		 402}
403
4a5e8e29 404static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 405{
4a5e8e29
JG		 406 outl(index, addr + PCNET32_DWIO_RAP);
407 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 408}
409
4a5e8e29 410static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 411{
4a5e8e29 412 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
1da177e4
LT		 413}
414
4a5e8e29 415static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 416{
4a5e8e29 417 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 418}
419
4a5e8e29 420static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 421{
4a5e8e29 422 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 423}
424
4a5e8e29 425static int pcnet32_dwio_check(unsigned long addr)
1da177e4 426{
4a5e8e29
JG		 427 outl(88, addr + PCNET32_DWIO_RAP);
428 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
1da177e4
LT		 429}
430
431static struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 432 .read_csr = pcnet32_dwio_read_csr,
433 .write_csr = pcnet32_dwio_write_csr,
434 .read_bcr = pcnet32_dwio_read_bcr,
435 .write_bcr = pcnet32_dwio_write_bcr,
436 .read_rap = pcnet32_dwio_read_rap,
437 .write_rap = pcnet32_dwio_write_rap,
438 .reset = pcnet32_dwio_reset
1da177e4
LT		 439};
440
06c87850
DF		 441static void pcnet32_netif_stop(struct net_device *dev)
442{
443 dev->trans_start = jiffies;
444 netif_poll_disable(dev);
445 netif_tx_disable(dev);
446}
447
448static void pcnet32_netif_start(struct net_device *dev)
449{
450 netif_wake_queue(dev);
451 netif_poll_enable(dev);
452}
453
454/*
455 * Allocate space for the new sized tx ring.
456 * Free old resources
457 * Save new resources.
458 * Any failure keeps old resources.
459 * Must be called with lp->lock held.
460 */
461static void pcnet32_realloc_tx_ring(struct net_device *dev,
462 struct pcnet32_private *lp,
463 unsigned int size)
464{
465 dma_addr_t new_ring_dma_addr;
466 dma_addr_t *new_dma_addr_list;
467 struct pcnet32_tx_head *new_tx_ring;
468 struct sk_buff **new_skb_list;
469
470 pcnet32_purge_tx_ring(dev);
471
472 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
473 sizeof(struct pcnet32_tx_head) *
474 (1 << size),
475 &new_ring_dma_addr);
476 if (new_tx_ring == NULL) {
477 if (netif_msg_drv(lp))
478 printk("\n" KERN_ERR
479 "%s: Consistent memory allocation failed.\n",
480 dev->name);
481 return;
482 }
483 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
484
485 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
486 GFP_ATOMIC);
487 if (!new_dma_addr_list) {
488 if (netif_msg_drv(lp))
489 printk("\n" KERN_ERR
490 "%s: Memory allocation failed.\n", dev->name);
491 goto free_new_tx_ring;
492 }
493
494 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
495 GFP_ATOMIC);
496 if (!new_skb_list) {
497 if (netif_msg_drv(lp))
498 printk("\n" KERN_ERR
499 "%s: Memory allocation failed.\n", dev->name);
500 goto free_new_lists;
501 }
502
503 kfree(lp->tx_skbuff);
504 kfree(lp->tx_dma_addr);
505 pci_free_consistent(lp->pci_dev,
506 sizeof(struct pcnet32_tx_head) *
507 lp->tx_ring_size, lp->tx_ring,
508 lp->tx_ring_dma_addr);
509
510 lp->tx_ring_size = (1 << size);
511 lp->tx_mod_mask = lp->tx_ring_size - 1;
512 lp->tx_len_bits = (size << 12);
513 lp->tx_ring = new_tx_ring;
514 lp->tx_ring_dma_addr = new_ring_dma_addr;
515 lp->tx_dma_addr = new_dma_addr_list;
516 lp->tx_skbuff = new_skb_list;
517 return;
518
519 free_new_lists:
520 kfree(new_dma_addr_list);
521 free_new_tx_ring:
522 pci_free_consistent(lp->pci_dev,
523 sizeof(struct pcnet32_tx_head) *
524 (1 << size),
525 new_tx_ring,
526 new_ring_dma_addr);
527 return;
528}
529
530/*
531 * Allocate space for the new sized rx ring.
532 * Re-use old receive buffers.
533 * alloc extra buffers
534 * free unneeded buffers
535 * free unneeded buffers
536 * Save new resources.
537 * Any failure keeps old resources.
538 * Must be called with lp->lock held.
539 */
540static void pcnet32_realloc_rx_ring(struct net_device *dev,
541 struct pcnet32_private *lp,
542 unsigned int size)
543{
544 dma_addr_t new_ring_dma_addr;
545 dma_addr_t *new_dma_addr_list;
546 struct pcnet32_rx_head *new_rx_ring;
547 struct sk_buff **new_skb_list;
548 int new, overlap;
549
550 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
551 sizeof(struct pcnet32_rx_head) *
552 (1 << size),
553 &new_ring_dma_addr);
554 if (new_rx_ring == NULL) {
555 if (netif_msg_drv(lp))
556 printk("\n" KERN_ERR
557 "%s: Consistent memory allocation failed.\n",
558 dev->name);
559 return;
560 }
561 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
562
563 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
564 GFP_ATOMIC);
565 if (!new_dma_addr_list) {
566 if (netif_msg_drv(lp))
567 printk("\n" KERN_ERR
568 "%s: Memory allocation failed.\n", dev->name);
569 goto free_new_rx_ring;
570 }
571
572 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
573 GFP_ATOMIC);
574 if (!new_skb_list) {
575 if (netif_msg_drv(lp))
576 printk("\n" KERN_ERR
577 "%s: Memory allocation failed.\n", dev->name);
578 goto free_new_lists;
579 }
580
581 /* first copy the current receive buffers */
582 overlap = min(size, lp->rx_ring_size);
583 for (new = 0; new < overlap; new++) {
584 new_rx_ring[new] = lp->rx_ring[new];
585 new_dma_addr_list[new] = lp->rx_dma_addr[new];
586 new_skb_list[new] = lp->rx_skbuff[new];
587 }
588 /* now allocate any new buffers needed */
589 for (; new < size; new++ ) {
590 struct sk_buff *rx_skbuff;
591 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
592 if (!(rx_skbuff = new_skb_list[new])) {
593 /* keep the original lists and buffers */
594 if (netif_msg_drv(lp))
595 printk(KERN_ERR
596 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
597 dev->name);
598 goto free_all_new;
599 }
600 skb_reserve(rx_skbuff, 2);
601
602 new_dma_addr_list[new] =
603 pci_map_single(lp->pci_dev, rx_skbuff->data,
604 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
605 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
606 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
607 new_rx_ring[new].status = le16_to_cpu(0x8000);
608 }
609 /* and free any unneeded buffers */
610 for (; new < lp->rx_ring_size; new++) {
611 if (lp->rx_skbuff[new]) {
612 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
613 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
614 dev_kfree_skb(lp->rx_skbuff[new]);
615 }
616 }
617
618 kfree(lp->rx_skbuff);
619 kfree(lp->rx_dma_addr);
620 pci_free_consistent(lp->pci_dev,
621 sizeof(struct pcnet32_rx_head) *
622 lp->rx_ring_size, lp->rx_ring,
623 lp->rx_ring_dma_addr);
624
625 lp->rx_ring_size = (1 << size);
626 lp->rx_mod_mask = lp->rx_ring_size - 1;
627 lp->rx_len_bits = (size << 4);
628 lp->rx_ring = new_rx_ring;
629 lp->rx_ring_dma_addr = new_ring_dma_addr;
630 lp->rx_dma_addr = new_dma_addr_list;
631 lp->rx_skbuff = new_skb_list;
632 return;
633
634 free_all_new:
635 for (; --new >= lp->rx_ring_size; ) {
636 if (new_skb_list[new]) {
637 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
638 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
639 dev_kfree_skb(new_skb_list[new]);
640 }
641 }
642 kfree(new_skb_list);
643 free_new_lists:
644 kfree(new_dma_addr_list);
645 free_new_rx_ring:
646 pci_free_consistent(lp->pci_dev,
647 sizeof(struct pcnet32_rx_head) *
648 (1 << size),
649 new_rx_ring,
650 new_ring_dma_addr);
651 return;
652}
653
ac5bfe40
DF		 654static void pcnet32_purge_rx_ring(struct net_device *dev)
655{
1e56a4b4 656 struct pcnet32_private *lp = netdev_priv(dev);
ac5bfe40
DF		 657 int i;
658
659 /* free all allocated skbuffs */
660 for (i = 0; i < lp->rx_ring_size; i++) {
661 lp->rx_ring[i].status = 0; /* CPU owns buffer */
662 wmb(); /* Make sure adapter sees owner change */
663 if (lp->rx_skbuff[i]) {
664 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
665 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
666 dev_kfree_skb_any(lp->rx_skbuff[i]);
667 }
668 lp->rx_skbuff[i] = NULL;
669 lp->rx_dma_addr[i] = 0;
670 }
671}
672
1da177e4
LT		 673#ifdef CONFIG_NET_POLL_CONTROLLER
674static void pcnet32_poll_controller(struct net_device *dev)
675{
4a5e8e29 676 disable_irq(dev->irq);
7d12e780 677 pcnet32_interrupt(0, dev);
4a5e8e29 678 enable_irq(dev->irq);
1da177e4
LT		 679}
680#endif
681
1da177e4
LT		 682static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
683{
1e56a4b4 684 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 685 unsigned long flags;
686 int r = -EOPNOTSUPP;
1da177e4 687
4a5e8e29
JG		 688 if (lp->mii) {
689 spin_lock_irqsave(&lp->lock, flags);
690 mii_ethtool_gset(&lp->mii_if, cmd);
691 spin_unlock_irqrestore(&lp->lock, flags);
692 r = 0;
693 }
694 return r;
1da177e4
LT		 695}
696
697static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
698{
1e56a4b4 699 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 700 unsigned long flags;
701 int r = -EOPNOTSUPP;
1da177e4 702
4a5e8e29
JG		 703 if (lp->mii) {
704 spin_lock_irqsave(&lp->lock, flags);
705 r = mii_ethtool_sset(&lp->mii_if, cmd);
706 spin_unlock_irqrestore(&lp->lock, flags);
707 }
708 return r;
1da177e4
LT		 709}
710
4a5e8e29
JG		 711static void pcnet32_get_drvinfo(struct net_device *dev,
712 struct ethtool_drvinfo *info)
1da177e4 713{
1e56a4b4 714 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 715
716 strcpy(info->driver, DRV_NAME);
717 strcpy(info->version, DRV_VERSION);
718 if (lp->pci_dev)
719 strcpy(info->bus_info, pci_name(lp->pci_dev));
720 else
721 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 722}
723
724static u32 pcnet32_get_link(struct net_device *dev)
725{
1e56a4b4 726 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 727 unsigned long flags;
728 int r;
1da177e4 729
4a5e8e29
JG		 730 spin_lock_irqsave(&lp->lock, flags);
731 if (lp->mii) {
732 r = mii_link_ok(&lp->mii_if);
8d916266 733 } else if (lp->chip_version >= PCNET32_79C970A) {
4a5e8e29
JG		 734 ulong ioaddr = dev->base_addr; /* card base I/O address */
735 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
8d916266
DF		 736 } else { /* can not detect link on really old chips */
737 r = 1;
4a5e8e29
JG		 738 }
739 spin_unlock_irqrestore(&lp->lock, flags);
740
741 return r;
1da177e4
LT		 742}
743
744static u32 pcnet32_get_msglevel(struct net_device *dev)
745{
1e56a4b4 746 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 747 return lp->msg_enable;
1da177e4
LT		 748}
749
750static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
751{
1e56a4b4 752 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 753 lp->msg_enable = value;
1da177e4
LT		 754}
755
756static int pcnet32_nway_reset(struct net_device *dev)
757{
1e56a4b4 758 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 759 unsigned long flags;
760 int r = -EOPNOTSUPP;
1da177e4 761
4a5e8e29
JG		 762 if (lp->mii) {
763 spin_lock_irqsave(&lp->lock, flags);
764 r = mii_nway_restart(&lp->mii_if);
765 spin_unlock_irqrestore(&lp->lock, flags);
766 }
767 return r;
1da177e4
LT		 768}
769
4a5e8e29
JG		 770static void pcnet32_get_ringparam(struct net_device *dev,
771 struct ethtool_ringparam *ering)
1da177e4 772{
1e56a4b4 773 struct pcnet32_private *lp = netdev_priv(dev);
1da177e4 774
6dcd60c2
DF		 775 ering->tx_max_pending = TX_MAX_RING_SIZE;
776 ering->tx_pending = lp->tx_ring_size;
777 ering->rx_max_pending = RX_MAX_RING_SIZE;
778 ering->rx_pending = lp->rx_ring_size;
eabf0415
HWL		 779}
780
4a5e8e29
JG		 781static int pcnet32_set_ringparam(struct net_device *dev,
782 struct ethtool_ringparam *ering)
eabf0415 783{
1e56a4b4 784 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 785 unsigned long flags;
06c87850
DF		 786 unsigned int size;
787 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 788 int i;
789
790 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
791 return -EINVAL;
792
793 if (netif_running(dev))
06c87850 794 pcnet32_netif_stop(dev);
4a5e8e29
JG		 795
796 spin_lock_irqsave(&lp->lock, flags);
06c87850
DF		 797 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
798
799 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
4a5e8e29
JG		 800
801 /* set the minimum ring size to 4, to allow the loopback test to work
802 * unchanged.
803 */
804 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
06c87850 805 if (size <= (1 << i))
4a5e8e29
JG		 806 break;
807 }
06c87850
DF		 808 if ((1 << i) != lp->tx_ring_size)
809 pcnet32_realloc_tx_ring(dev, lp, i);
b368a3fb 810
06c87850 811 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
4a5e8e29 812 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
06c87850 813 if (size <= (1 << i))
4a5e8e29
JG		 814 break;
815 }
06c87850
DF		 816 if ((1 << i) != lp->rx_ring_size)
817 pcnet32_realloc_rx_ring(dev, lp, i);
b368a3fb 818
06c87850
DF		 819 dev->weight = lp->rx_ring_size / 2;
820
821 if (netif_running(dev)) {
822 pcnet32_netif_start(dev);
823 pcnet32_restart(dev, CSR0_NORMAL);
4a5e8e29 824 }
eabf0415 825
4a5e8e29 826 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 827
06c87850
DF		 828 if (netif_msg_drv(lp))
829 printk(KERN_INFO
4a5e8e29
JG		 830 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
831 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 832
4a5e8e29 833 return 0;
1da177e4
LT		 834}
835
4a5e8e29
JG		 836static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
837 u8 * data)
1da177e4 838{
4a5e8e29 839 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 840}
841
842static int pcnet32_self_test_count(struct net_device *dev)
843{
4a5e8e29 844 return PCNET32_TEST_LEN;
1da177e4
LT		 845}
846
847static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 848 struct ethtool_test *test, u64 * data)
1da177e4 849{
1e56a4b4 850 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 851 int rc;
852
853 if (test->flags == ETH_TEST_FL_OFFLINE) {
854 rc = pcnet32_loopback_test(dev, data);
855 if (rc) {
856 if (netif_msg_hw(lp))
857 printk(KERN_DEBUG "%s: Loopback test failed.\n",
858 dev->name);
859 test->flags |= ETH_TEST_FL_FAILED;
860 } else if (netif_msg_hw(lp))
861 printk(KERN_DEBUG "%s: Loopback test passed.\n",
862 dev->name);
1da177e4 863 } else if (netif_msg_hw(lp))
4a5e8e29
JG		 864 printk(KERN_DEBUG
865 "%s: No tests to run (specify 'Offline' on ethtool).",
866 dev->name);
867} /* end pcnet32_ethtool_test */
1da177e4 868
4a5e8e29 869static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 870{
1e56a4b4 871 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 872 struct pcnet32_access *a = &lp->a; /* access to registers */
873 ulong ioaddr = dev->base_addr; /* card base I/O address */
874 struct sk_buff *skb; /* sk buff */
875 int x, i; /* counters */
876 int numbuffs = 4; /* number of TX/RX buffers and descs */
877 u16 status = 0x8300; /* TX ring status */
878 u16 teststatus; /* test of ring status */
879 int rc; /* return code */
880 int size; /* size of packets */
881 unsigned char *packet; /* source packet data */
882 static const int data_len = 60; /* length of source packets */
883 unsigned long flags;
884 unsigned long ticks;
885
4a5e8e29
JG		 886 rc = 1; /* default to fail */
887
888 if (netif_running(dev))
7de745e5
DF		 889#ifdef CONFIG_PCNET32_NAPI
890 pcnet32_netif_stop(dev);
891#else
4a5e8e29 892 pcnet32_close(dev);
7de745e5 893#endif
4a5e8e29
JG		 894
895 spin_lock_irqsave(&lp->lock, flags);
ac5bfe40
DF		 896 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
897
898 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
4a5e8e29
JG		 899
900 /* Reset the PCNET32 */
901 lp->a.reset(ioaddr);
b368a3fb 902 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
4a5e8e29
JG		 903
904 /* switch pcnet32 to 32bit mode */
905 lp->a.write_bcr(ioaddr, 20, 2);
906
4a5e8e29
JG		 907 /* purge & init rings but don't actually restart */
908 pcnet32_restart(dev, 0x0000);
909
ac5bfe40 910 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 911
912 /* Initialize Transmit buffers. */
913 size = data_len + 15;
914 for (x = 0; x < numbuffs; x++) {
915 if (!(skb = dev_alloc_skb(size))) {
916 if (netif_msg_hw(lp))
917 printk(KERN_DEBUG
918 "%s: Cannot allocate skb at line: %d!\n",
919 dev->name, __LINE__);
920 goto clean_up;
921 } else {
922 packet = skb->data;
923 skb_put(skb, size); /* create space for data */
924 lp->tx_skbuff[x] = skb;
925 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
926 lp->tx_ring[x].misc = 0;
927
928 /* put DA and SA into the skb */
929 for (i = 0; i < 6; i++)
930 *packet++ = dev->dev_addr[i];
931 for (i = 0; i < 6; i++)
932 *packet++ = dev->dev_addr[i];
933 /* type */
934 *packet++ = 0x08;
935 *packet++ = 0x06;
936 /* packet number */
937 *packet++ = x;
938 /* fill packet with data */
939 for (i = 0; i < data_len; i++)
940 *packet++ = i;
941
942 lp->tx_dma_addr[x] =
943 pci_map_single(lp->pci_dev, skb->data, skb->len,
944 PCI_DMA_TODEVICE);
945 lp->tx_ring[x].base =
946 (u32) le32_to_cpu(lp->tx_dma_addr[x]);
947 wmb(); /* Make sure owner changes after all others are visible */
948 lp->tx_ring[x].status = le16_to_cpu(status);
949 }
1da177e4 950 }
1da177e4 951
ac5bfe40
DF		 952 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
953 a->write_bcr(ioaddr, 32, x | 0x0002);
4a5e8e29 954
ac5bfe40
DF		 955 /* set int loopback in CSR15 */
956 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
957 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
4a5e8e29
JG		 958
959 teststatus = le16_to_cpu(0x8000);
ac5bfe40 960 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
4a5e8e29
JG		 961
962 /* Check status of descriptors */
963 for (x = 0; x < numbuffs; x++) {
964 ticks = 0;
965 rmb();
966 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
967 spin_unlock_irqrestore(&lp->lock, flags);
ac5bfe40 968 msleep(1);
4a5e8e29
JG		 969 spin_lock_irqsave(&lp->lock, flags);
970 rmb();
971 ticks++;
972 }
973 if (ticks == 200) {
974 if (netif_msg_hw(lp))
975 printk("%s: Desc %d failed to reset!\n",
976 dev->name, x);
977 break;
978 }
979 }
980
ac5bfe40 981 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 982 wmb();
983 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
984 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
985
986 for (x = 0; x < numbuffs; x++) {
987 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
988 skb = lp->rx_skbuff[x];
989 for (i = 0; i < size; i++) {
990 printk("%02x ", *(skb->data + i));
991 }
992 printk("\n");
993 }
994 }
1da177e4 995
4a5e8e29
JG		 996 x = 0;
997 rc = 0;
998 while (x < numbuffs && !rc) {
999 skb = lp->rx_skbuff[x];
1000 packet = lp->tx_skbuff[x]->data;
1001 for (i = 0; i < size; i++) {
1002 if (*(skb->data + i) != packet[i]) {
1003 if (netif_msg_hw(lp))
1004 printk(KERN_DEBUG
1005 "%s: Error in compare! %2x - %02x %02x\n",
1006 dev->name, i, *(skb->data + i),
1007 packet[i]);
1008 rc = 1;
1009 break;
1010 }
1011 }
1012 x++;
1013 }
1da177e4 1014
4a5e8e29 1015 clean_up:
ac5bfe40 1016 *data1 = rc;
4a5e8e29 1017 pcnet32_purge_tx_ring(dev);
1da177e4 1018
ac5bfe40
DF		 1019 x = a->read_csr(ioaddr, CSR15);
1020 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 1021
ac5bfe40
DF		 1022 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1023 a->write_bcr(ioaddr, 32, (x & ~0x0002));
4a5e8e29 1024
7de745e5
DF		 1025#ifdef CONFIG_PCNET32_NAPI
1026 if (netif_running(dev)) {
1027 pcnet32_netif_start(dev);
1028 pcnet32_restart(dev, CSR0_NORMAL);
1029 } else {
1030 pcnet32_purge_rx_ring(dev);
1031 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1032 }
1033 spin_unlock_irqrestore(&lp->lock, flags);
1034#else
4a5e8e29 1035 if (netif_running(dev)) {
ac5bfe40 1036 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29
JG		 1037 pcnet32_open(dev);
1038 } else {
ac5bfe40 1039 pcnet32_purge_rx_ring(dev);
4a5e8e29 1040 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
ac5bfe40 1041 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29 1042 }
7de745e5 1043#endif
4a5e8e29
JG		 1044
1045 return (rc);
1046} /* end pcnet32_loopback_test */
1da177e4
LT		 1047
1048static void pcnet32_led_blink_callback(struct net_device *dev)
1049{
1e56a4b4 1050 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1051 struct pcnet32_access *a = &lp->a;
1052 ulong ioaddr = dev->base_addr;
1053 unsigned long flags;
1054 int i;
1055
1056 spin_lock_irqsave(&lp->lock, flags);
1057 for (i = 4; i < 8; i++) {
1058 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1059 }
1060 spin_unlock_irqrestore(&lp->lock, flags);
1061
1062 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1da177e4
LT		 1063}
1064
1065static int pcnet32_phys_id(struct net_device *dev, u32 data)
1066{
1e56a4b4 1067 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1068 struct pcnet32_access *a = &lp->a;
1069 ulong ioaddr = dev->base_addr;
1070 unsigned long flags;
1071 int i, regs[4];
1072
1073 if (!lp->blink_timer.function) {
1074 init_timer(&lp->blink_timer);
1075 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1076 lp->blink_timer.data = (unsigned long)dev;
1077 }
1078
1079 /* Save the current value of the bcrs */
1080 spin_lock_irqsave(&lp->lock, flags);
1081 for (i = 4; i < 8; i++) {
1082 regs[i - 4] = a->read_bcr(ioaddr, i);
1083 }
1084 spin_unlock_irqrestore(&lp->lock, flags);
1085
1086 mod_timer(&lp->blink_timer, jiffies);
1087 set_current_state(TASK_INTERRUPTIBLE);
1088
1089 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1090 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1091
1092 msleep_interruptible(data * 1000);
1093 del_timer_sync(&lp->blink_timer);
1094
1095 /* Restore the original value of the bcrs */
1096 spin_lock_irqsave(&lp->lock, flags);
1097 for (i = 4; i < 8; i++) {
1098 a->write_bcr(ioaddr, i, regs[i - 4]);
1099 }
1100 spin_unlock_irqrestore(&lp->lock, flags);
1101
1102 return 0;
1da177e4
LT		 1103}
1104
df27f4a6
DF		 1105/*
1106 * lp->lock must be held.
1107 */
1108static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1109 int can_sleep)
1110{
1111 int csr5;
1e56a4b4 1112 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6
DF		 1113 struct pcnet32_access *a = &lp->a;
1114 ulong ioaddr = dev->base_addr;
1115 int ticks;
1116
8d916266
DF		 1117 /* really old chips have to be stopped. */
1118 if (lp->chip_version < PCNET32_79C970A)
1119 return 0;
1120
df27f4a6
DF		 1121 /* set SUSPEND (SPND) - CSR5 bit 0 */
1122 csr5 = a->read_csr(ioaddr, CSR5);
1123 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1124
1125 /* poll waiting for bit to be set */
1126 ticks = 0;
1127 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1128 spin_unlock_irqrestore(&lp->lock, *flags);
1129 if (can_sleep)
1130 msleep(1);
1131 else
1132 mdelay(1);
1133 spin_lock_irqsave(&lp->lock, *flags);
1134 ticks++;
1135 if (ticks > 200) {
1136 if (netif_msg_hw(lp))
1137 printk(KERN_DEBUG
1138 "%s: Error getting into suspend!\n",
1139 dev->name);
1140 return 0;
1141 }
1142 }
1143 return 1;
1144}
1145
3904c324
DF		 1146/*
1147 * process one receive descriptor entry
1148 */
1149
1150static void pcnet32_rx_entry(struct net_device *dev,
1151 struct pcnet32_private *lp,
1152 struct pcnet32_rx_head *rxp,
1153 int entry)
1154{
1155 int status = (short)le16_to_cpu(rxp->status) >> 8;
1156 int rx_in_place = 0;
1157 struct sk_buff *skb;
1158 short pkt_len;
1159
1160 if (status != 0x03) { /* There was an error. */
1161 /*
1162 * There is a tricky error noted by John Murphy,
1163 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1164 * buffers it's possible for a jabber packet to use two
1165 * buffers, with only the last correctly noting the error.
1166 */
1167 if (status & 0x01) /* Only count a general error at the */
1168 lp->stats.rx_errors++; /* end of a packet. */
1169 if (status & 0x20)
1170 lp->stats.rx_frame_errors++;
1171 if (status & 0x10)
1172 lp->stats.rx_over_errors++;
1173 if (status & 0x08)
1174 lp->stats.rx_crc_errors++;
1175 if (status & 0x04)
1176 lp->stats.rx_fifo_errors++;
1177 return;
1178 }
1179
1180 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1181
1182 /* Discard oversize frames. */
1183 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1184 if (netif_msg_drv(lp))
1185 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1186 dev->name, pkt_len);
1187 lp->stats.rx_errors++;
1188 return;
1189 }
1190 if (pkt_len < 60) {
1191 if (netif_msg_rx_err(lp))
1192 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1193 lp->stats.rx_errors++;
1194 return;
1195 }
1196
1197 if (pkt_len > rx_copybreak) {
1198 struct sk_buff *newskb;
1199
1200 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1201 skb_reserve(newskb, 2);
1202 skb = lp->rx_skbuff[entry];
1203 pci_unmap_single(lp->pci_dev,
1204 lp->rx_dma_addr[entry],
1205 PKT_BUF_SZ - 2,
1206 PCI_DMA_FROMDEVICE);
1207 skb_put(skb, pkt_len);
1208 lp->rx_skbuff[entry] = newskb;
3904c324
DF		 1209 lp->rx_dma_addr[entry] =
1210 pci_map_single(lp->pci_dev,
1211 newskb->data,
1212 PKT_BUF_SZ - 2,
1213 PCI_DMA_FROMDEVICE);
1214 rxp->base = le32_to_cpu(lp->rx_dma_addr[entry]);
1215 rx_in_place = 1;
1216 } else
1217 skb = NULL;
1218 } else {
1219 skb = dev_alloc_skb(pkt_len + 2);
1220 }
1221
1222 if (skb == NULL) {
1223 if (netif_msg_drv(lp))
1224 printk(KERN_ERR
1225 "%s: Memory squeeze, dropping packet.\n",
1226 dev->name);
1227 lp->stats.rx_dropped++;
1228 return;
1229 }
1230 skb->dev = dev;
1231 if (!rx_in_place) {
1232 skb_reserve(skb, 2); /* 16 byte align */
1233 skb_put(skb, pkt_len); /* Make room */
1234 pci_dma_sync_single_for_cpu(lp->pci_dev,
1235 lp->rx_dma_addr[entry],
b2cbbd8e 1236 pkt_len,
3904c324 1237 PCI_DMA_FROMDEVICE);
8c7b7faa 1238 skb_copy_to_linear_data(skb,
3904c324 1239 (unsigned char *)(lp->rx_skbuff[entry]->data),
8c7b7faa 1240 pkt_len);
3904c324
DF		 1241 pci_dma_sync_single_for_device(lp->pci_dev,
1242 lp->rx_dma_addr[entry],
b2cbbd8e 1243 pkt_len,
3904c324
DF		 1244 PCI_DMA_FROMDEVICE);
1245 }
1246 lp->stats.rx_bytes += skb->len;
1247 skb->protocol = eth_type_trans(skb, dev);
7de745e5
DF		 1248#ifdef CONFIG_PCNET32_NAPI
1249 netif_receive_skb(skb);
1250#else
3904c324 1251 netif_rx(skb);
7de745e5 1252#endif
3904c324
DF		 1253 dev->last_rx = jiffies;
1254 lp->stats.rx_packets++;
1255 return;
1256}
1257
7de745e5 1258static int pcnet32_rx(struct net_device *dev, int quota)
9691edd2 1259{
1e56a4b4 1260 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2 1261 int entry = lp->cur_rx & lp->rx_mod_mask;
3904c324
DF		 1262 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1263 int npackets = 0;
9691edd2
DF		 1264
1265 /* If we own the next entry, it's a new packet. Send it up. */
7de745e5 1266 while (quota > npackets && (short)le16_to_cpu(rxp->status) >= 0) {
3904c324
DF		 1267 pcnet32_rx_entry(dev, lp, rxp, entry);
1268 npackets += 1;
9691edd2 1269 /*
3904c324
DF		 1270 * The docs say that the buffer length isn't touched, but Andrew
1271 * Boyd of QNX reports that some revs of the 79C965 clear it.
9691edd2 1272 */
3904c324
DF		 1273 rxp->buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
1274 wmb(); /* Make sure owner changes after others are visible */
1275 rxp->status = le16_to_cpu(0x8000);
9691edd2 1276 entry = (++lp->cur_rx) & lp->rx_mod_mask;
3904c324 1277 rxp = &lp->rx_ring[entry];
9691edd2
DF		 1278 }
1279
7de745e5 1280 return npackets;
9691edd2
DF		 1281}
1282
7de745e5 1283static int pcnet32_tx(struct net_device *dev)
9691edd2 1284{
1e56a4b4 1285 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2
DF		 1286 unsigned int dirty_tx = lp->dirty_tx;
1287 int delta;
1288 int must_restart = 0;
1289
1290 while (dirty_tx != lp->cur_tx) {
1291 int entry = dirty_tx & lp->tx_mod_mask;
1292 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1293
1294 if (status < 0)
1295 break; /* It still hasn't been Txed */
1296
1297 lp->tx_ring[entry].base = 0;
1298
1299 if (status & 0x4000) {
3904c324 1300 /* There was a major error, log it. */
9691edd2
DF		 1301 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1302 lp->stats.tx_errors++;
1303 if (netif_msg_tx_err(lp))
1304 printk(KERN_ERR
1305 "%s: Tx error status=%04x err_status=%08x\n",
1306 dev->name, status,
1307 err_status);
1308 if (err_status & 0x04000000)
1309 lp->stats.tx_aborted_errors++;
1310 if (err_status & 0x08000000)
1311 lp->stats.tx_carrier_errors++;
1312 if (err_status & 0x10000000)
1313 lp->stats.tx_window_errors++;
1314#ifndef DO_DXSUFLO
1315 if (err_status & 0x40000000) {
1316 lp->stats.tx_fifo_errors++;
1317 /* Ackk! On FIFO errors the Tx unit is turned off! */
1318 /* Remove this verbosity later! */
1319 if (netif_msg_tx_err(lp))
1320 printk(KERN_ERR
7de745e5
DF		 1321 "%s: Tx FIFO error!\n",
1322 dev->name);
9691edd2
DF		 1323 must_restart = 1;
1324 }
1325#else
1326 if (err_status & 0x40000000) {
1327 lp->stats.tx_fifo_errors++;
1328 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1329 /* Ackk! On FIFO errors the Tx unit is turned off! */
1330 /* Remove this verbosity later! */
3904c324 1331 if (netif_msg_tx_err(lp))
9691edd2 1332 printk(KERN_ERR
7de745e5
DF		 1333 "%s: Tx FIFO error!\n",
1334 dev->name);
9691edd2
DF		 1335 must_restart = 1;
1336 }
1337 }
1338#endif
1339 } else {
1340 if (status & 0x1800)
1341 lp->stats.collisions++;
1342 lp->stats.tx_packets++;
1343 }
1344
1345 /* We must free the original skb */
1346 if (lp->tx_skbuff[entry]) {
1347 pci_unmap_single(lp->pci_dev,
1348 lp->tx_dma_addr[entry],
1349 lp->tx_skbuff[entry]->
1350 len, PCI_DMA_TODEVICE);
3904c324 1351 dev_kfree_skb_any(lp->tx_skbuff[entry]);
9691edd2
DF		 1352 lp->tx_skbuff[entry] = NULL;
1353 lp->tx_dma_addr[entry] = 0;
1354 }
1355 dirty_tx++;
1356 }
1357
3904c324 1358 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
9691edd2
DF		 1359 if (delta > lp->tx_ring_size) {
1360 if (netif_msg_drv(lp))
1361 printk(KERN_ERR
1362 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1363 dev->name, dirty_tx, lp->cur_tx,
1364 lp->tx_full);
1365 dirty_tx += lp->tx_ring_size;
1366 delta -= lp->tx_ring_size;
1367 }
1368
1369 if (lp->tx_full &&
1370 netif_queue_stopped(dev) &&
1371 delta < lp->tx_ring_size - 2) {
1372 /* The ring is no longer full, clear tbusy. */
1373 lp->tx_full = 0;
1374 netif_wake_queue(dev);
1375 }
1376 lp->dirty_tx = dirty_tx;
1377
1378 return must_restart;
1379}
1380
7de745e5
DF		 1381#ifdef CONFIG_PCNET32_NAPI
1382static int pcnet32_poll(struct net_device *dev, int *budget)
1383{
1e56a4b4 1384 struct pcnet32_private *lp = netdev_priv(dev);
7de745e5
DF		 1385 int quota = min(dev->quota, *budget);
1386 unsigned long ioaddr = dev->base_addr;
1387 unsigned long flags;
1388 u16 val;
1389
1390 quota = pcnet32_rx(dev, quota);
1391
1392 spin_lock_irqsave(&lp->lock, flags);
1393 if (pcnet32_tx(dev)) {
1394 /* reset the chip to clear the error condition, then restart */
1395 lp->a.reset(ioaddr);
1396 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1397 pcnet32_restart(dev, CSR0_START);
1398 netif_wake_queue(dev);
1399 }
1400 spin_unlock_irqrestore(&lp->lock, flags);
1401
1402 *budget -= quota;
1403 dev->quota -= quota;
1404
1405 if (dev->quota == 0) {
1406 return 1;
1407 }
1408
1409 netif_rx_complete(dev);
1410
1411 spin_lock_irqsave(&lp->lock, flags);
1412
1413 /* clear interrupt masks */
1414 val = lp->a.read_csr(ioaddr, CSR3);
1415 val &= 0x00ff;
1416 lp->a.write_csr(ioaddr, CSR3, val);
1417
1418 /* Set interrupt enable. */
1419 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1420 mmiowb();
1421 spin_unlock_irqrestore(&lp->lock, flags);
1422
1423 return 0;
1424}
1425#endif
1426
ac62ef04
DF		 1427#define PCNET32_REGS_PER_PHY 32
1428#define PCNET32_MAX_PHYS 32
1da177e4
LT		 1429static int pcnet32_get_regs_len(struct net_device *dev)
1430{
1e56a4b4 1431 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 1432 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 1433
4a5e8e29 1434 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1da177e4
LT		 1435}
1436
1437static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 1438 void *ptr)
1da177e4 1439{
4a5e8e29
JG		 1440 int i, csr0;
1441 u16 *buff = ptr;
1e56a4b4 1442 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1443 struct pcnet32_access *a = &lp->a;
1444 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 1445 unsigned long flags;
1446
1447 spin_lock_irqsave(&lp->lock, flags);
1448
df27f4a6
DF		 1449 csr0 = a->read_csr(ioaddr, CSR0);
1450 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1451 pcnet32_suspend(dev, &flags, 1);
1da177e4 1452
4a5e8e29
JG		 1453 /* read address PROM */
1454 for (i = 0; i < 16; i += 2)
1455 *buff++ = inw(ioaddr + i);
1456
1457 /* read control and status registers */
1458 for (i = 0; i < 90; i++) {
1459 *buff++ = a->read_csr(ioaddr, i);
1460 }
1461
1462 *buff++ = a->read_csr(ioaddr, 112);
1463 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 1464
4a5e8e29
JG		 1465 /* read bus configuration registers */
1466 for (i = 0; i < 30; i++) {
1467 *buff++ = a->read_bcr(ioaddr, i);
1468 }
1469 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1470 for (i = 31; i < 36; i++) {
1471 *buff++ = a->read_bcr(ioaddr, i);
1472 }
1473
1474 /* read mii phy registers */
1475 if (lp->mii) {
1476 int j;
1477 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1478 if (lp->phymask & (1 << j)) {
1479 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1480 lp->a.write_bcr(ioaddr, 33,
1481 (j << 5) | i);
1482 *buff++ = lp->a.read_bcr(ioaddr, 34);
1483 }
1484 }
1485 }
1486 }
1487
df27f4a6
DF		 1488 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1489 int csr5;
1490
4a5e8e29 1491 /* clear SUSPEND (SPND) - CSR5 bit 0 */
df27f4a6
DF		 1492 csr5 = a->read_csr(ioaddr, CSR5);
1493 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
4a5e8e29
JG		 1494 }
1495
1496 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 1497}
1498
7282d491 1499static const struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 1500 .get_settings = pcnet32_get_settings,
1501 .set_settings = pcnet32_set_settings,
1502 .get_drvinfo = pcnet32_get_drvinfo,
1503 .get_msglevel = pcnet32_get_msglevel,
1504 .set_msglevel = pcnet32_set_msglevel,
1505 .nway_reset = pcnet32_nway_reset,
1506 .get_link = pcnet32_get_link,
1507 .get_ringparam = pcnet32_get_ringparam,
1508 .set_ringparam = pcnet32_set_ringparam,
1509 .get_tx_csum = ethtool_op_get_tx_csum,
1510 .get_sg = ethtool_op_get_sg,
1511 .get_tso = ethtool_op_get_tso,
1512 .get_strings = pcnet32_get_strings,
1513 .self_test_count = pcnet32_self_test_count,
1514 .self_test = pcnet32_ethtool_test,
1515 .phys_id = pcnet32_phys_id,
1516 .get_regs_len = pcnet32_get_regs_len,
1517 .get_regs = pcnet32_get_regs,
1da177e4
LT		 1518};
1519
1520/* only probes for non-PCI devices, the rest are handled by
1521 * pci_register_driver via pcnet32_probe_pci */
1522
dcaf9769 1523static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1da177e4 1524{
4a5e8e29
JG		 1525 unsigned int *port, ioaddr;
1526
1527 /* search for PCnet32 VLB cards at known addresses */
1528 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1529 if (request_region
1530 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1531 /* check if there is really a pcnet chip on that ioaddr */
1532 if ((inb(ioaddr + 14) == 0x57)
1533 && (inb(ioaddr + 15) == 0x57)) {
1534 pcnet32_probe1(ioaddr, 0, NULL);
1535 } else {
1536 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1537 }
1538 }
1539 }
1da177e4
LT		 1540}
1541
1da177e4
LT		 1542static int __devinit
1543pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1544{
4a5e8e29
JG		 1545 unsigned long ioaddr;
1546 int err;
1547
1548 err = pci_enable_device(pdev);
1549 if (err < 0) {
1550 if (pcnet32_debug & NETIF_MSG_PROBE)
1551 printk(KERN_ERR PFX
1552 "failed to enable device -- err=%d\n", err);
1553 return err;
1554 }
1555 pci_set_master(pdev);
1556
1557 ioaddr = pci_resource_start(pdev, 0);
1558 if (!ioaddr) {
1559 if (pcnet32_debug & NETIF_MSG_PROBE)
1560 printk(KERN_ERR PFX
1561 "card has no PCI IO resources, aborting\n");
1562 return -ENODEV;
1563 }
1da177e4 1564
4a5e8e29
JG		 1565 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1566 if (pcnet32_debug & NETIF_MSG_PROBE)
1567 printk(KERN_ERR PFX
1568 "architecture does not support 32bit PCI busmaster DMA\n");
1569 return -ENODEV;
1570 }
1571 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1572 NULL) {
1573 if (pcnet32_debug & NETIF_MSG_PROBE)
1574 printk(KERN_ERR PFX
1575 "io address range already allocated\n");
1576 return -EBUSY;
1577 }
1da177e4 1578
4a5e8e29
JG		 1579 err = pcnet32_probe1(ioaddr, 1, pdev);
1580 if (err < 0) {
1581 pci_disable_device(pdev);
1582 }
1583 return err;
1da177e4
LT		 1584}
1585
1da177e4
LT		 1586/* pcnet32_probe1
1587 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1588 * pdev will be NULL when called from pcnet32_probe_vlbus.
1589 */
1590static int __devinit
1591pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1592{
4a5e8e29 1593 struct pcnet32_private *lp;
4a5e8e29
JG		 1594 int i, media;
1595 int fdx, mii, fset, dxsuflo;
1596 int chip_version;
1597 char *chipname;
1598 struct net_device *dev;
1599 struct pcnet32_access *a = NULL;
1600 u8 promaddr[6];
1601 int ret = -ENODEV;
1602
1603 /* reset the chip */
1604 pcnet32_wio_reset(ioaddr);
1605
1606 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1607 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1608 a = &pcnet32_wio;
1609 } else {
1610 pcnet32_dwio_reset(ioaddr);
1611 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1612 && pcnet32_dwio_check(ioaddr)) {
1613 a = &pcnet32_dwio;
1614 } else
1615 goto err_release_region;
1616 }
1617
1618 chip_version =
1619 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1620 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1621 printk(KERN_INFO " PCnet chip version is %#x.\n",
1622 chip_version);
1623 if ((chip_version & 0xfff) != 0x003) {
1624 if (pcnet32_debug & NETIF_MSG_PROBE)
1625 printk(KERN_INFO PFX "Unsupported chip version.\n");
1626 goto err_release_region;
1627 }
1628
1629 /* initialize variables */
1630 fdx = mii = fset = dxsuflo = 0;
1631 chip_version = (chip_version >> 12) & 0xffff;
1632
1633 switch (chip_version) {
1634 case 0x2420:
1635 chipname = "PCnet/PCI 79C970"; /* PCI */
1636 break;
1637 case 0x2430:
1638 if (shared)
1639 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1640 else
1641 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1642 break;
1643 case 0x2621:
1644 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1645 fdx = 1;
1646 break;
1647 case 0x2623:
1648 chipname = "PCnet/FAST 79C971"; /* PCI */
1649 fdx = 1;
1650 mii = 1;
1651 fset = 1;
1652 break;
1653 case 0x2624:
1654 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1655 fdx = 1;
1656 mii = 1;
1657 fset = 1;
1658 break;
1659 case 0x2625:
1660 chipname = "PCnet/FAST III 79C973"; /* PCI */
1661 fdx = 1;
1662 mii = 1;
1663 break;
1664 case 0x2626:
1665 chipname = "PCnet/Home 79C978"; /* PCI */
1666 fdx = 1;
1667 /*
1668 * This is based on specs published at www.amd.com. This section
1669 * assumes that a card with a 79C978 wants to go into standard
1670 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1671 * and the module option homepna=1 can select this instead.
1672 */
1673 media = a->read_bcr(ioaddr, 49);
1674 media &= ~3; /* default to 10Mb ethernet */
1675 if (cards_found < MAX_UNITS && homepna[cards_found])
1676 media |= 1; /* switch to home wiring mode */
1677 if (pcnet32_debug & NETIF_MSG_PROBE)
1678 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1679 (media & 1) ? "1" : "10");
1680 a->write_bcr(ioaddr, 49, media);
1681 break;
1682 case 0x2627:
1683 chipname = "PCnet/FAST III 79C975"; /* PCI */
1684 fdx = 1;
1685 mii = 1;
1686 break;
1687 case 0x2628:
1688 chipname = "PCnet/PRO 79C976";
1689 fdx = 1;
1690 mii = 1;
1691 break;
1692 default:
1693 if (pcnet32_debug & NETIF_MSG_PROBE)
1694 printk(KERN_INFO PFX
1695 "PCnet version %#x, no PCnet32 chip.\n",
1696 chip_version);
1697 goto err_release_region;
1698 }
1699
1da177e4 1700 /*
4a5e8e29
JG		 1701 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1702 * starting until the packet is loaded. Strike one for reliability, lose
1703 * one for latency - although on PCI this isnt a big loss. Older chips
1704 * have FIFO's smaller than a packet, so you can't do this.
1705 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1706 */
4a5e8e29
JG		 1707
1708 if (fset) {
1709 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1710 a->write_csr(ioaddr, 80,
1711 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1712 dxsuflo = 1;
1713 }
1714
6ecb7667 1715 dev = alloc_etherdev(sizeof(*lp));
4a5e8e29
JG		 1716 if (!dev) {
1717 if (pcnet32_debug & NETIF_MSG_PROBE)
1718 printk(KERN_ERR PFX "Memory allocation failed.\n");
1719 ret = -ENOMEM;
1720 goto err_release_region;
1721 }
1722 SET_NETDEV_DEV(dev, &pdev->dev);
1723
1da177e4 1724 if (pcnet32_debug & NETIF_MSG_PROBE)
4a5e8e29
JG		 1725 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1726
1727 /* In most chips, after a chip reset, the ethernet address is read from the
1728 * station address PROM at the base address and programmed into the
1729 * "Physical Address Registers" CSR12-14.
1730 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1731 * they disagree with the CSRs. If they miscompare, and the PROM addr
1732 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1733 */
1734 for (i = 0; i < 3; i++) {
1735 unsigned int val;
1736 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1737 /* There may be endianness issues here. */
1738 dev->dev_addr[2 * i] = val & 0x0ff;
1739 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1740 }
1741
1742 /* read PROM address and compare with CSR address */
1da177e4 1743 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1744 promaddr[i] = inb(ioaddr + i);
1745
1746 if (memcmp(promaddr, dev->dev_addr, 6)
1747 || !is_valid_ether_addr(dev->dev_addr)) {
1748 if (is_valid_ether_addr(promaddr)) {
1749 if (pcnet32_debug & NETIF_MSG_PROBE) {
1750 printk(" warning: CSR address invalid,\n");
1751 printk(KERN_INFO
1752 " using instead PROM address of");
1753 }
1754 memcpy(dev->dev_addr, promaddr, 6);
1755 }
1756 }
1757 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1758
1759 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1760 if (!is_valid_ether_addr(dev->perm_addr))
1761 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1762
1763 if (pcnet32_debug & NETIF_MSG_PROBE) {
1764 for (i = 0; i < 6; i++)
1765 printk(" %2.2x", dev->dev_addr[i]);
1766
1767 /* Version 0x2623 and 0x2624 */
1768 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1769 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1770 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1771 switch (i >> 10) {
1772 case 0:
1773 printk(" 20 bytes,");
1774 break;
1775 case 1:
1776 printk(" 64 bytes,");
1777 break;
1778 case 2:
1779 printk(" 128 bytes,");
1780 break;
1781 case 3:
1782 printk("~220 bytes,");
1783 break;
1784 }
1785 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1786 printk(" BCR18(%x):", i & 0xffff);
1787 if (i & (1 << 5))
1788 printk("BurstWrEn ");
1789 if (i & (1 << 6))
1790 printk("BurstRdEn ");
1791 if (i & (1 << 7))
1792 printk("DWordIO ");
1793 if (i & (1 << 11))
1794 printk("NoUFlow ");
1795 i = a->read_bcr(ioaddr, 25);
1796 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1797 i = a->read_bcr(ioaddr, 26);
1798 printk(" SRAM_BND=0x%04x,", i << 8);
1799 i = a->read_bcr(ioaddr, 27);
1800 if (i & (1 << 14))
1801 printk("LowLatRx");
1802 }
1803 }
1804
1805 dev->base_addr = ioaddr;
1e56a4b4 1806 lp = netdev_priv(dev);
4a5e8e29 1807 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
6ecb7667
DF		 1808 if ((lp->init_block =
1809 pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
4a5e8e29
JG		 1810 if (pcnet32_debug & NETIF_MSG_PROBE)
1811 printk(KERN_ERR PFX
1812 "Consistent memory allocation failed.\n");
1813 ret = -ENOMEM;
1814 goto err_free_netdev;
1815 }
4a5e8e29
JG		 1816 lp->pci_dev = pdev;
1817
1818 spin_lock_init(&lp->lock);
1819
1820 SET_MODULE_OWNER(dev);
1821 SET_NETDEV_DEV(dev, &pdev->dev);
4a5e8e29
JG		 1822 lp->name = chipname;
1823 lp->shared_irq = shared;
1824 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1825 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1826 lp->tx_mod_mask = lp->tx_ring_size - 1;
1827 lp->rx_mod_mask = lp->rx_ring_size - 1;
1828 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1829 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1830 lp->mii_if.full_duplex = fdx;
1831 lp->mii_if.phy_id_mask = 0x1f;
1832 lp->mii_if.reg_num_mask = 0x1f;
1833 lp->dxsuflo = dxsuflo;
1834 lp->mii = mii;
8d916266 1835 lp->chip_version = chip_version;
4a5e8e29
JG		 1836 lp->msg_enable = pcnet32_debug;
1837 if ((cards_found >= MAX_UNITS)
1838 || (options[cards_found] > sizeof(options_mapping)))
1839 lp->options = PCNET32_PORT_ASEL;
1840 else
1841 lp->options = options_mapping[options[cards_found]];
1842 lp->mii_if.dev = dev;
1843 lp->mii_if.mdio_read = mdio_read;
1844 lp->mii_if.mdio_write = mdio_write;
1845
1846 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1847 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1848 lp->options |= PCNET32_PORT_FD;
1849
1850 if (!a) {
1851 if (pcnet32_debug & NETIF_MSG_PROBE)
1852 printk(KERN_ERR PFX "No access methods\n");
1853 ret = -ENODEV;
1854 goto err_free_consistent;
1855 }
1856 lp->a = *a;
1857
1858 /* prior to register_netdev, dev->name is not yet correct */
1859 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1860 ret = -ENOMEM;
1861 goto err_free_ring;
1862 }
1863 /* detect special T1/E1 WAN card by checking for MAC address */
1864 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1da177e4 1865 && dev->dev_addr[2] == 0x75)
4a5e8e29 1866 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1867
6ecb7667
DF		 1868 lp->init_block->mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1869 lp->init_block->tlen_rlen =
4a5e8e29
JG		 1870 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1871 for (i = 0; i < 6; i++)
6ecb7667
DF		 1872 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1873 lp->init_block->filter[0] = 0x00000000;
1874 lp->init_block->filter[1] = 0x00000000;
1875 lp->init_block->rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1876 lp->init_block->tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
4a5e8e29
JG		 1877
1878 /* switch pcnet32 to 32bit mode */
1879 a->write_bcr(ioaddr, 20, 2);
1880
6ecb7667
DF		 1881 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1882 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29
JG		 1883
1884 if (pdev) { /* use the IRQ provided by PCI */
1885 dev->irq = pdev->irq;
1886 if (pcnet32_debug & NETIF_MSG_PROBE)
1887 printk(" assigned IRQ %d.\n", dev->irq);
1888 } else {
1889 unsigned long irq_mask = probe_irq_on();
1890
1891 /*
1892 * To auto-IRQ we enable the initialization-done and DMA error
1893 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1894 * boards will work.
1895 */
1896 /* Trigger an initialization just for the interrupt. */
b368a3fb 1897 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
4a5e8e29
JG		 1898 mdelay(1);
1899
1900 dev->irq = probe_irq_off(irq_mask);
1901 if (!dev->irq) {
1902 if (pcnet32_debug & NETIF_MSG_PROBE)
1903 printk(", failed to detect IRQ line.\n");
1904 ret = -ENODEV;
1905 goto err_free_ring;
1906 }
1907 if (pcnet32_debug & NETIF_MSG_PROBE)
1908 printk(", probed IRQ %d.\n", dev->irq);
1909 }
1da177e4 1910
4a5e8e29
JG		 1911 /* Set the mii phy_id so that we can query the link state */
1912 if (lp->mii) {
1913 /* lp->phycount and lp->phymask are set to 0 by memset above */
1914
1915 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1916 /* scan for PHYs */
1917 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1918 unsigned short id1, id2;
1919
1920 id1 = mdio_read(dev, i, MII_PHYSID1);
1921 if (id1 == 0xffff)
1922 continue;
1923 id2 = mdio_read(dev, i, MII_PHYSID2);
1924 if (id2 == 0xffff)
1925 continue;
1926 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1927 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1928 lp->phycount++;
1929 lp->phymask |= (1 << i);
1930 lp->mii_if.phy_id = i;
1931 if (pcnet32_debug & NETIF_MSG_PROBE)
1932 printk(KERN_INFO PFX
1933 "Found PHY %04x:%04x at address %d.\n",
1934 id1, id2, i);
1935 }
1936 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1937 if (lp->phycount > 1) {
1938 lp->options |= PCNET32_PORT_MII;
1939 }
1da177e4 1940 }
4a5e8e29
JG		 1941
1942 init_timer(&lp->watchdog_timer);
1943 lp->watchdog_timer.data = (unsigned long)dev;
1944 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1945
1946 /* The PCNET32-specific entries in the device structure. */
1947 dev->open = &pcnet32_open;
1948 dev->hard_start_xmit = &pcnet32_start_xmit;
1949 dev->stop = &pcnet32_close;
1950 dev->get_stats = &pcnet32_get_stats;
1951 dev->set_multicast_list = &pcnet32_set_multicast_list;
1952 dev->do_ioctl = &pcnet32_ioctl;
1953 dev->ethtool_ops = &pcnet32_ethtool_ops;
1954 dev->tx_timeout = pcnet32_tx_timeout;
1955 dev->watchdog_timeo = (5 * HZ);
7de745e5
DF		 1956 dev->weight = lp->rx_ring_size / 2;
1957#ifdef CONFIG_PCNET32_NAPI
1958 dev->poll = pcnet32_poll;
1959#endif
1da177e4
LT		 1960
1961#ifdef CONFIG_NET_POLL_CONTROLLER
4a5e8e29 1962 dev->poll_controller = pcnet32_poll_controller;
1da177e4
LT		 1963#endif
1964
4a5e8e29
JG		 1965 /* Fill in the generic fields of the device structure. */
1966 if (register_netdev(dev))
1967 goto err_free_ring;
1968
1969 if (pdev) {
1970 pci_set_drvdata(pdev, dev);
1971 } else {
1972 lp->next = pcnet32_dev;
1973 pcnet32_dev = dev;
1974 }
1975
1976 if (pcnet32_debug & NETIF_MSG_PROBE)
1977 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1978 cards_found++;
1979
1980 /* enable LED writes */
1981 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1982
4a5e8e29
JG		 1983 return 0;
1984
1985 err_free_ring:
1986 pcnet32_free_ring(dev);
1987 err_free_consistent:
6ecb7667
DF		 1988 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1989 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 1990 err_free_netdev:
1991 free_netdev(dev);
1992 err_release_region:
1993 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1994 return ret;
1995}
1da177e4 1996
a88c844c
DF		 1997/* if any allocation fails, caller must also call pcnet32_free_ring */
1998static int pcnet32_alloc_ring(struct net_device *dev, char *name)
eabf0415 1999{
1e56a4b4 2000 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 2001
4a5e8e29
JG		 2002 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
2003 sizeof(struct pcnet32_tx_head) *
2004 lp->tx_ring_size,
2005 &lp->tx_ring_dma_addr);
2006 if (lp->tx_ring == NULL) {
12fa30f3 2007 if (netif_msg_drv(lp))
4a5e8e29
JG		 2008 printk("\n" KERN_ERR PFX
2009 "%s: Consistent memory allocation failed.\n",
2010 name);
2011 return -ENOMEM;
2012 }
eabf0415 2013
4a5e8e29
JG		 2014 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2015 sizeof(struct pcnet32_rx_head) *
2016 lp->rx_ring_size,
2017 &lp->rx_ring_dma_addr);
2018 if (lp->rx_ring == NULL) {
12fa30f3 2019 if (netif_msg_drv(lp))
4a5e8e29
JG		 2020 printk("\n" KERN_ERR PFX
2021 "%s: Consistent memory allocation failed.\n",
2022 name);
2023 return -ENOMEM;
2024 }
eabf0415 2025
12fa30f3 2026 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2027 GFP_ATOMIC);
2028 if (!lp->tx_dma_addr) {
12fa30f3 2029 if (netif_msg_drv(lp))
4a5e8e29
JG		 2030 printk("\n" KERN_ERR PFX
2031 "%s: Memory allocation failed.\n", name);
2032 return -ENOMEM;
2033 }
4a5e8e29 2034
12fa30f3 2035 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2036 GFP_ATOMIC);
2037 if (!lp->rx_dma_addr) {
12fa30f3 2038 if (netif_msg_drv(lp))
4a5e8e29
JG		 2039 printk("\n" KERN_ERR PFX
2040 "%s: Memory allocation failed.\n", name);
2041 return -ENOMEM;
2042 }
4a5e8e29 2043
12fa30f3 2044 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2045 GFP_ATOMIC);
2046 if (!lp->tx_skbuff) {
12fa30f3 2047 if (netif_msg_drv(lp))
4a5e8e29
JG		 2048 printk("\n" KERN_ERR PFX
2049 "%s: Memory allocation failed.\n", name);
2050 return -ENOMEM;
2051 }
4a5e8e29 2052
12fa30f3 2053 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2054 GFP_ATOMIC);
2055 if (!lp->rx_skbuff) {
12fa30f3 2056 if (netif_msg_drv(lp))
4a5e8e29
JG		 2057 printk("\n" KERN_ERR PFX
2058 "%s: Memory allocation failed.\n", name);
2059 return -ENOMEM;
2060 }
4a5e8e29
JG		 2061
2062 return 0;
2063}
eabf0415
HWL		 2064
2065static void pcnet32_free_ring(struct net_device *dev)
2066{
1e56a4b4 2067 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 2068
4a5e8e29
JG		 2069 kfree(lp->tx_skbuff);
2070 lp->tx_skbuff = NULL;
eabf0415 2071
4a5e8e29
JG		 2072 kfree(lp->rx_skbuff);
2073 lp->rx_skbuff = NULL;
eabf0415 2074
4a5e8e29
JG		 2075 kfree(lp->tx_dma_addr);
2076 lp->tx_dma_addr = NULL;
eabf0415 2077
4a5e8e29
JG		 2078 kfree(lp->rx_dma_addr);
2079 lp->rx_dma_addr = NULL;
eabf0415 2080
4a5e8e29
JG		 2081 if (lp->tx_ring) {
2082 pci_free_consistent(lp->pci_dev,
2083 sizeof(struct pcnet32_tx_head) *
2084 lp->tx_ring_size, lp->tx_ring,
2085 lp->tx_ring_dma_addr);
2086 lp->tx_ring = NULL;
2087 }
eabf0415 2088
4a5e8e29
JG		 2089 if (lp->rx_ring) {
2090 pci_free_consistent(lp->pci_dev,
2091 sizeof(struct pcnet32_rx_head) *
2092 lp->rx_ring_size, lp->rx_ring,
2093 lp->rx_ring_dma_addr);
2094 lp->rx_ring = NULL;
2095 }
eabf0415
HWL		 2096}
2097
4a5e8e29 2098static int pcnet32_open(struct net_device *dev)
1da177e4 2099{
1e56a4b4 2100 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2101 unsigned long ioaddr = dev->base_addr;
2102 u16 val;
2103 int i;
2104 int rc;
2105 unsigned long flags;
2106
2107 if (request_irq(dev->irq, &pcnet32_interrupt,
1fb9df5d 2108 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 2109 (void *)dev)) {
2110 return -EAGAIN;
2111 }
2112
2113 spin_lock_irqsave(&lp->lock, flags);
2114 /* Check for a valid station address */
2115 if (!is_valid_ether_addr(dev->dev_addr)) {
2116 rc = -EINVAL;
2117 goto err_free_irq;
2118 }
2119
2120 /* Reset the PCNET32 */
2121 lp->a.reset(ioaddr);
2122
2123 /* switch pcnet32 to 32bit mode */
2124 lp->a.write_bcr(ioaddr, 20, 2);
2125
2126 if (netif_msg_ifup(lp))
2127 printk(KERN_DEBUG
2128 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2129 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2130 (u32) (lp->rx_ring_dma_addr),
6ecb7667 2131 (u32) (lp->init_dma_addr));
4a5e8e29
JG		 2132
2133 /* set/reset autoselect bit */
2134 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2135 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 2136 val |= 2;
4a5e8e29
JG		 2137 lp->a.write_bcr(ioaddr, 2, val);
2138
2139 /* handle full duplex setting */
2140 if (lp->mii_if.full_duplex) {
2141 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2142 if (lp->options & PCNET32_PORT_FD) {
2143 val |= 1;
2144 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2145 val |= 2;
2146 } else if (lp->options & PCNET32_PORT_ASEL) {
2147 /* workaround of xSeries250, turn on for 79C975 only */
8d916266 2148 if (lp->chip_version == 0x2627)
4a5e8e29
JG		 2149 val |= 3;
2150 }
2151 lp->a.write_bcr(ioaddr, 9, val);
2152 }
2153
2154 /* set/reset GPSI bit in test register */
2155 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2156 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2157 val |= 0x10;
2158 lp->a.write_csr(ioaddr, 124, val);
2159
2160 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2161 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2964bbd7
DF		 2162 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2163 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 2164 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29
JG		 2165 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2166 if (netif_msg_link(lp))
2167 printk(KERN_DEBUG
2168 "%s: Setting 100Mb-Full Duplex.\n",
2169 dev->name);
2170 }
2171 }
2172 if (lp->phycount < 2) {
2173 /*
2174 * 24 Jun 2004 according AMD, in order to change the PHY,
2175 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2176 * duplex, and/or enable auto negotiation, and clear DANAS
2177 */
2178 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2179 lp->a.write_bcr(ioaddr, 32,
2180 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2181 /* disable Auto Negotiation, set 10Mpbs, HD */
2182 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2183 if (lp->options & PCNET32_PORT_FD)
2184 val |= 0x10;
2185 if (lp->options & PCNET32_PORT_100)
2186 val |= 0x08;
2187 lp->a.write_bcr(ioaddr, 32, val);
2188 } else {
2189 if (lp->options & PCNET32_PORT_ASEL) {
2190 lp->a.write_bcr(ioaddr, 32,
2191 lp->a.read_bcr(ioaddr,
2192 32) | 0x0080);
2193 /* enable auto negotiate, setup, disable fd */
2194 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2195 val |= 0x20;
2196 lp->a.write_bcr(ioaddr, 32, val);
2197 }
2198 }
2199 } else {
2200 int first_phy = -1;
2201 u16 bmcr;
2202 u32 bcr9;
2203 struct ethtool_cmd ecmd;
2204
2205 /*
2206 * There is really no good other way to handle multiple PHYs
2207 * other than turning off all automatics
2208 */
2209 val = lp->a.read_bcr(ioaddr, 2);
2210 lp->a.write_bcr(ioaddr, 2, val & ~2);
2211 val = lp->a.read_bcr(ioaddr, 32);
2212 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2213
2214 if (!(lp->options & PCNET32_PORT_ASEL)) {
2215 /* setup ecmd */
2216 ecmd.port = PORT_MII;
2217 ecmd.transceiver = XCVR_INTERNAL;
2218 ecmd.autoneg = AUTONEG_DISABLE;
2219 ecmd.speed =
2220 lp->
2221 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2222 bcr9 = lp->a.read_bcr(ioaddr, 9);
2223
2224 if (lp->options & PCNET32_PORT_FD) {
2225 ecmd.duplex = DUPLEX_FULL;
2226 bcr9 |= (1 << 0);
2227 } else {
2228 ecmd.duplex = DUPLEX_HALF;
2229 bcr9 |= ~(1 << 0);
2230 }
2231 lp->a.write_bcr(ioaddr, 9, bcr9);
ac62ef04 2232 }
4a5e8e29
JG		 2233
2234 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2235 if (lp->phymask & (1 << i)) {
2236 /* isolate all but the first PHY */
2237 bmcr = mdio_read(dev, i, MII_BMCR);
2238 if (first_phy == -1) {
2239 first_phy = i;
2240 mdio_write(dev, i, MII_BMCR,
2241 bmcr & ~BMCR_ISOLATE);
2242 } else {
2243 mdio_write(dev, i, MII_BMCR,
2244 bmcr | BMCR_ISOLATE);
2245 }
2246 /* use mii_ethtool_sset to setup PHY */
2247 lp->mii_if.phy_id = i;
2248 ecmd.phy_address = i;
2249 if (lp->options & PCNET32_PORT_ASEL) {
2250 mii_ethtool_gset(&lp->mii_if, &ecmd);
2251 ecmd.autoneg = AUTONEG_ENABLE;
2252 }
2253 mii_ethtool_sset(&lp->mii_if, &ecmd);
2254 }
2255 }
2256 lp->mii_if.phy_id = first_phy;
2257 if (netif_msg_link(lp))
2258 printk(KERN_INFO "%s: Using PHY number %d.\n",
2259 dev->name, first_phy);
2260 }
1da177e4
LT		 2261
2262#ifdef DO_DXSUFLO
4a5e8e29 2263 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
b368a3fb 2264 val = lp->a.read_csr(ioaddr, CSR3);
4a5e8e29 2265 val |= 0x40;
b368a3fb 2266 lp->a.write_csr(ioaddr, CSR3, val);
4a5e8e29 2267 }
1da177e4
LT		 2268#endif
2269
6ecb7667 2270 lp->init_block->mode =
4a5e8e29
JG		 2271 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2272 pcnet32_load_multicast(dev);
2273
2274 if (pcnet32_init_ring(dev)) {
2275 rc = -ENOMEM;
2276 goto err_free_ring;
2277 }
2278
2279 /* Re-initialize the PCNET32, and start it when done. */
6ecb7667
DF		 2280 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2281 lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29 2282
b368a3fb
DF		 2283 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2284 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2285
2286 netif_start_queue(dev);
2287
8d916266
DF		 2288 if (lp->chip_version >= PCNET32_79C970A) {
2289 /* Print the link status and start the watchdog */
2290 pcnet32_check_media(dev, 1);
2291 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2292 }
4a5e8e29
JG		 2293
2294 i = 0;
2295 while (i++ < 100)
b368a3fb 2296 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29
JG		 2297 break;
2298 /*
2299 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2300 * reports that doing so triggers a bug in the '974.
2301 */
b368a3fb 2302 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
4a5e8e29
JG		 2303
2304 if (netif_msg_ifup(lp))
2305 printk(KERN_DEBUG
2306 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2307 dev->name, i,
6ecb7667 2308 (u32) (lp->init_dma_addr),
b368a3fb 2309 lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2310
2311 spin_unlock_irqrestore(&lp->lock, flags);
2312
2313 return 0; /* Always succeed */
2314
2315 err_free_ring:
2316 /* free any allocated skbuffs */
ac5bfe40 2317 pcnet32_purge_rx_ring(dev);
4a5e8e29 2318
4a5e8e29
JG		 2319 /*
2320 * Switch back to 16bit mode to avoid problems with dumb
2321 * DOS packet driver after a warm reboot
2322 */
2323 lp->a.write_bcr(ioaddr, 20, 4);
2324
2325 err_free_irq:
2326 spin_unlock_irqrestore(&lp->lock, flags);
2327 free_irq(dev->irq, dev);
2328 return rc;
1da177e4
LT		 2329}
2330
2331/*
2332 * The LANCE has been halted for one reason or another (busmaster memory
2333 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2334 * etc.). Modern LANCE variants always reload their ring-buffer
2335 * configuration when restarted, so we must reinitialize our ring
2336 * context before restarting. As part of this reinitialization,
2337 * find all packets still on the Tx ring and pretend that they had been
2338 * sent (in effect, drop the packets on the floor) - the higher-level
2339 * protocols will time out and retransmit. It'd be better to shuffle
2340 * these skbs to a temp list and then actually re-Tx them after
2341 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2342 */
2343
4a5e8e29 2344static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 2345{
1e56a4b4 2346 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2347 int i;
1da177e4 2348
4a5e8e29
JG		 2349 for (i = 0; i < lp->tx_ring_size; i++) {
2350 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2351 wmb(); /* Make sure adapter sees owner change */
2352 if (lp->tx_skbuff[i]) {
2353 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2354 lp->tx_skbuff[i]->len,
2355 PCI_DMA_TODEVICE);
2356 dev_kfree_skb_any(lp->tx_skbuff[i]);
2357 }
2358 lp->tx_skbuff[i] = NULL;
2359 lp->tx_dma_addr[i] = 0;
2360 }
2361}
1da177e4
LT		 2362
2363/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 2364static int pcnet32_init_ring(struct net_device *dev)
1da177e4 2365{
1e56a4b4 2366 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2367 int i;
2368
2369 lp->tx_full = 0;
2370 lp->cur_rx = lp->cur_tx = 0;
2371 lp->dirty_rx = lp->dirty_tx = 0;
2372
2373 for (i = 0; i < lp->rx_ring_size; i++) {
2374 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2375 if (rx_skbuff == NULL) {
2376 if (!
2377 (rx_skbuff = lp->rx_skbuff[i] =
2378 dev_alloc_skb(PKT_BUF_SZ))) {
2379 /* there is not much, we can do at this point */
b368a3fb 2380 if (netif_msg_drv(lp))
4a5e8e29
JG		 2381 printk(KERN_ERR
2382 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2383 dev->name);
2384 return -1;
2385 }
2386 skb_reserve(rx_skbuff, 2);
2387 }
2388
2389 rmb();
2390 if (lp->rx_dma_addr[i] == 0)
2391 lp->rx_dma_addr[i] =
2392 pci_map_single(lp->pci_dev, rx_skbuff->data,
2393 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2394 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
2395 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2396 wmb(); /* Make sure owner changes after all others are visible */
2397 lp->rx_ring[i].status = le16_to_cpu(0x8000);
2398 }
2399 /* The Tx buffer address is filled in as needed, but we do need to clear
2400 * the upper ownership bit. */
2401 for (i = 0; i < lp->tx_ring_size; i++) {
2402 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2403 wmb(); /* Make sure adapter sees owner change */
2404 lp->tx_ring[i].base = 0;
2405 lp->tx_dma_addr[i] = 0;
2406 }
2407
6ecb7667 2408 lp->init_block->tlen_rlen =
4a5e8e29
JG		 2409 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
2410 for (i = 0; i < 6; i++)
6ecb7667
DF		 2411 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2412 lp->init_block->rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
2413 lp->init_block->tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
4a5e8e29
JG		 2414 wmb(); /* Make sure all changes are visible */
2415 return 0;
1da177e4
LT		 2416}
2417
2418/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2419 * then flush the pending transmit operations, re-initialize the ring,
2420 * and tell the chip to initialize.
2421 */
4a5e8e29 2422static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 2423{
1e56a4b4 2424 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2425 unsigned long ioaddr = dev->base_addr;
2426 int i;
1da177e4 2427
4a5e8e29
JG		 2428 /* wait for stop */
2429 for (i = 0; i < 100; i++)
b368a3fb 2430 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
4a5e8e29 2431 break;
1da177e4 2432
4a5e8e29
JG		 2433 if (i >= 100 && netif_msg_drv(lp))
2434 printk(KERN_ERR
2435 "%s: pcnet32_restart timed out waiting for stop.\n",
2436 dev->name);
1da177e4 2437
4a5e8e29
JG		 2438 pcnet32_purge_tx_ring(dev);
2439 if (pcnet32_init_ring(dev))
2440 return;
1da177e4 2441
4a5e8e29 2442 /* ReInit Ring */
b368a3fb 2443 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2444 i = 0;
2445 while (i++ < 1000)
b368a3fb 2446 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29 2447 break;
1da177e4 2448
b368a3fb 2449 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
1da177e4
LT		 2450}
2451
4a5e8e29 2452static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 2453{
1e56a4b4 2454 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2455 unsigned long ioaddr = dev->base_addr, flags;
2456
2457 spin_lock_irqsave(&lp->lock, flags);
2458 /* Transmitter timeout, serious problems. */
2459 if (pcnet32_debug & NETIF_MSG_DRV)
2460 printk(KERN_ERR
2461 "%s: transmit timed out, status %4.4x, resetting.\n",
b368a3fb
DF		 2462 dev->name, lp->a.read_csr(ioaddr, CSR0));
2463 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
4a5e8e29
JG		 2464 lp->stats.tx_errors++;
2465 if (netif_msg_tx_err(lp)) {
2466 int i;
2467 printk(KERN_DEBUG
2468 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2469 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2470 lp->cur_rx);
2471 for (i = 0; i < lp->rx_ring_size; i++)
2472 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2473 le32_to_cpu(lp->rx_ring[i].base),
2474 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2475 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2476 le16_to_cpu(lp->rx_ring[i].status));
2477 for (i = 0; i < lp->tx_ring_size; i++)
2478 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2479 le32_to_cpu(lp->tx_ring[i].base),
2480 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2481 le32_to_cpu(lp->tx_ring[i].misc),
2482 le16_to_cpu(lp->tx_ring[i].status));
2483 printk("\n");
2484 }
b368a3fb 2485 pcnet32_restart(dev, CSR0_NORMAL);
1da177e4 2486
4a5e8e29
JG		 2487 dev->trans_start = jiffies;
2488 netif_wake_queue(dev);
1da177e4 2489
4a5e8e29
JG		 2490 spin_unlock_irqrestore(&lp->lock, flags);
2491}
2492
2493static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 2494{
1e56a4b4 2495 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2496 unsigned long ioaddr = dev->base_addr;
2497 u16 status;
2498 int entry;
2499 unsigned long flags;
1da177e4 2500
4a5e8e29 2501 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2502
4a5e8e29
JG		 2503 if (netif_msg_tx_queued(lp)) {
2504 printk(KERN_DEBUG
2505 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
b368a3fb 2506 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2507 }
1da177e4 2508
4a5e8e29
JG		 2509 /* Default status -- will not enable Successful-TxDone
2510 * interrupt when that option is available to us.
2511 */
2512 status = 0x8300;
1da177e4 2513
4a5e8e29 2514 /* Fill in a Tx ring entry */
1da177e4 2515
4a5e8e29
JG		 2516 /* Mask to ring buffer boundary. */
2517 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 2518
4a5e8e29
JG		 2519 /* Caution: the write order is important here, set the status
2520 * with the "ownership" bits last. */
1da177e4 2521
4a5e8e29 2522 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1da177e4 2523
4a5e8e29 2524 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 2525
4a5e8e29
JG		 2526 lp->tx_skbuff[entry] = skb;
2527 lp->tx_dma_addr[entry] =
2528 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2529 lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
2530 wmb(); /* Make sure owner changes after all others are visible */
2531 lp->tx_ring[entry].status = le16_to_cpu(status);
1da177e4 2532
4a5e8e29
JG		 2533 lp->cur_tx++;
2534 lp->stats.tx_bytes += skb->len;
1da177e4 2535
4a5e8e29 2536 /* Trigger an immediate send poll. */
b368a3fb 2537 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
1da177e4 2538
4a5e8e29 2539 dev->trans_start = jiffies;
1da177e4 2540
4a5e8e29
JG		 2541 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2542 lp->tx_full = 1;
2543 netif_stop_queue(dev);
2544 }
2545 spin_unlock_irqrestore(&lp->lock, flags);
2546 return 0;
1da177e4
LT		 2547}
2548
2549/* The PCNET32 interrupt handler. */
2550static irqreturn_t
7d12e780 2551pcnet32_interrupt(int irq, void *dev_id)
1da177e4 2552{
4a5e8e29
JG		 2553 struct net_device *dev = dev_id;
2554 struct pcnet32_private *lp;
2555 unsigned long ioaddr;
5c99346a 2556 u16 csr0;
4a5e8e29 2557 int boguscnt = max_interrupt_work;
4a5e8e29 2558
4a5e8e29 2559 ioaddr = dev->base_addr;
1e56a4b4 2560 lp = netdev_priv(dev);
1da177e4 2561
4a5e8e29
JG		 2562 spin_lock(&lp->lock);
2563
3904c324
DF		 2564 csr0 = lp->a.read_csr(ioaddr, CSR0);
2565 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
4a5e8e29
JG		 2566 if (csr0 == 0xffff) {
2567 break; /* PCMCIA remove happened */
2568 }
2569 /* Acknowledge all of the current interrupt sources ASAP. */
3904c324 2570 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
4a5e8e29 2571
4a5e8e29
JG		 2572 if (netif_msg_intr(lp))
2573 printk(KERN_DEBUG
2574 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
3904c324 2575 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2576
4a5e8e29
JG		 2577 /* Log misc errors. */
2578 if (csr0 & 0x4000)
2579 lp->stats.tx_errors++; /* Tx babble. */
2580 if (csr0 & 0x1000) {
2581 /*
3904c324
DF		 2582 * This happens when our receive ring is full. This
2583 * shouldn't be a problem as we will see normal rx
2584 * interrupts for the frames in the receive ring. But
2585 * there are some PCI chipsets (I can reproduce this
2586 * on SP3G with Intel saturn chipset) which have
2587 * sometimes problems and will fill up the receive
2588 * ring with error descriptors. In this situation we
2589 * don't get a rx interrupt, but a missed frame
7de745e5 2590 * interrupt sooner or later.
4a5e8e29 2591 */
4a5e8e29
JG		 2592 lp->stats.rx_errors++; /* Missed a Rx frame. */
2593 }
2594 if (csr0 & 0x0800) {
2595 if (netif_msg_drv(lp))
2596 printk(KERN_ERR
2597 "%s: Bus master arbitration failure, status %4.4x.\n",
2598 dev->name, csr0);
2599 /* unlike for the lance, there is no restart needed */
1da177e4 2600 }
7de745e5
DF		 2601#ifdef CONFIG_PCNET32_NAPI
2602 if (netif_rx_schedule_prep(dev)) {
2603 u16 val;
2604 /* set interrupt masks */
2605 val = lp->a.read_csr(ioaddr, CSR3);
2606 val |= 0x5f00;
2607 lp->a.write_csr(ioaddr, CSR3, val);
2608 mmiowb();
2609 __netif_rx_schedule(dev);
2610 break;
2611 }
2612#else
2613 pcnet32_rx(dev, dev->weight);
2614 if (pcnet32_tx(dev)) {
4a5e8e29
JG		 2615 /* reset the chip to clear the error condition, then restart */
2616 lp->a.reset(ioaddr);
7de745e5 2617 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
b368a3fb 2618 pcnet32_restart(dev, CSR0_START);
4a5e8e29 2619 netif_wake_queue(dev);
1da177e4 2620 }
7de745e5 2621#endif
3904c324 2622 csr0 = lp->a.read_csr(ioaddr, CSR0);
4a5e8e29
JG		 2623 }
2624
7de745e5 2625#ifndef CONFIG_PCNET32_NAPI
4a5e8e29 2626 /* Set interrupt enable. */
b368a3fb 2627 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
7de745e5 2628#endif
4a5e8e29
JG		 2629
2630 if (netif_msg_intr(lp))
2631 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
b368a3fb 2632 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2633
2634 spin_unlock(&lp->lock);
2635
2636 return IRQ_HANDLED;
1da177e4
LT		 2637}
2638
4a5e8e29 2639static int pcnet32_close(struct net_device *dev)
1da177e4 2640{
4a5e8e29 2641 unsigned long ioaddr = dev->base_addr;
1e56a4b4 2642 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2643 unsigned long flags;
1da177e4 2644
4a5e8e29 2645 del_timer_sync(&lp->watchdog_timer);
1da177e4 2646
4a5e8e29 2647 netif_stop_queue(dev);
1da177e4 2648
4a5e8e29 2649 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2650
4a5e8e29 2651 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
1da177e4 2652
4a5e8e29
JG		 2653 if (netif_msg_ifdown(lp))
2654 printk(KERN_DEBUG
2655 "%s: Shutting down ethercard, status was %2.2x.\n",
b368a3fb 2656 dev->name, lp->a.read_csr(ioaddr, CSR0));
1da177e4 2657
4a5e8e29 2658 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
b368a3fb 2659 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
1da177e4 2660
4a5e8e29
JG		 2661 /*
2662 * Switch back to 16bit mode to avoid problems with dumb
2663 * DOS packet driver after a warm reboot
2664 */
2665 lp->a.write_bcr(ioaddr, 20, 4);
1da177e4 2666
4a5e8e29 2667 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2668
4a5e8e29 2669 free_irq(dev->irq, dev);
1da177e4 2670
4a5e8e29 2671 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2672
ac5bfe40
DF		 2673 pcnet32_purge_rx_ring(dev);
2674 pcnet32_purge_tx_ring(dev);
1da177e4 2675
4a5e8e29 2676 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2677
4a5e8e29 2678 return 0;
1da177e4
LT		 2679}
2680
4a5e8e29 2681static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2682{
1e56a4b4 2683 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2684 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2685 unsigned long flags;
2686
2687 spin_lock_irqsave(&lp->lock, flags);
4a5e8e29 2688 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
4a5e8e29
JG		 2689 spin_unlock_irqrestore(&lp->lock, flags);
2690
2691 return &lp->stats;
1da177e4
LT		 2692}
2693
2694/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2695static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2696{
1e56a4b4 2697 struct pcnet32_private *lp = netdev_priv(dev);
6ecb7667 2698 volatile struct pcnet32_init_block *ib = lp->init_block;
4a5e8e29
JG		 2699 volatile u16 *mcast_table = (u16 *) & ib->filter;
2700 struct dev_mc_list *dmi = dev->mc_list;
df27f4a6 2701 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2702 char *addrs;
2703 int i;
2704 u32 crc;
2705
2706 /* set all multicast bits */
2707 if (dev->flags & IFF_ALLMULTI) {
2708 ib->filter[0] = 0xffffffff;
2709 ib->filter[1] = 0xffffffff;
df27f4a6
DF		 2710 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2711 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2712 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2713 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
4a5e8e29
JG		 2714 return;
2715 }
2716 /* clear the multicast filter */
2717 ib->filter[0] = 0;
2718 ib->filter[1] = 0;
2719
2720 /* Add addresses */
2721 for (i = 0; i < dev->mc_count; i++) {
2722 addrs = dmi->dmi_addr;
2723 dmi = dmi->next;
2724
2725 /* multicast address? */
2726 if (!(*addrs & 1))
2727 continue;
2728
2729 crc = ether_crc_le(6, addrs);
2730 crc = crc >> 26;
2731 mcast_table[crc >> 4] =
2732 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2733 (1 << (crc & 0xf)));
2734 }
df27f4a6
DF		 2735 for (i = 0; i < 4; i++)
2736 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2737 le16_to_cpu(mcast_table[i]));
1da177e4 2738 return;
1da177e4
LT		 2739}
2740
1da177e4
LT		 2741/*
2742 * Set or clear the multicast filter for this adaptor.
2743 */
2744static void pcnet32_set_multicast_list(struct net_device *dev)
2745{
4a5e8e29 2746 unsigned long ioaddr = dev->base_addr, flags;
1e56a4b4 2747 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6 2748 int csr15, suspended;
4a5e8e29
JG		 2749
2750 spin_lock_irqsave(&lp->lock, flags);
df27f4a6
DF		 2751 suspended = pcnet32_suspend(dev, &flags, 0);
2752 csr15 = lp->a.read_csr(ioaddr, CSR15);
4a5e8e29
JG		 2753 if (dev->flags & IFF_PROMISC) {
2754 /* Log any net taps. */
2755 if (netif_msg_hw(lp))
2756 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2757 dev->name);
6ecb7667 2758 lp->init_block->mode =
4a5e8e29
JG		 2759 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2760 7);
df27f4a6 2761 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
4a5e8e29 2762 } else {
6ecb7667 2763 lp->init_block->mode =
4a5e8e29 2764 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
df27f4a6 2765 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
4a5e8e29
JG		 2766 pcnet32_load_multicast(dev);
2767 }
2768
df27f4a6
DF		 2769 if (suspended) {
2770 int csr5;
2771 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2772 csr5 = lp->a.read_csr(ioaddr, CSR5);
2773 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
b368a3fb 2774 } else {
df27f4a6
DF		 2775 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2776 pcnet32_restart(dev, CSR0_NORMAL);
2777 netif_wake_queue(dev);
2778 }
4a5e8e29
JG		 2779
2780 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2781}
2782
2783/* This routine assumes that the lp->lock is held */
2784static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2785{
1e56a4b4 2786 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2787 unsigned long ioaddr = dev->base_addr;
2788 u16 val_out;
1da177e4 2789
4a5e8e29
JG		 2790 if (!lp->mii)
2791 return 0;
1da177e4 2792
4a5e8e29
JG		 2793 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2794 val_out = lp->a.read_bcr(ioaddr, 34);
1da177e4 2795
4a5e8e29 2796 return val_out;
1da177e4
LT		 2797}
2798
2799/* This routine assumes that the lp->lock is held */
2800static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2801{
1e56a4b4 2802 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2803 unsigned long ioaddr = dev->base_addr;
1da177e4 2804
4a5e8e29
JG		 2805 if (!lp->mii)
2806 return;
1da177e4 2807
4a5e8e29
JG		 2808 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2809 lp->a.write_bcr(ioaddr, 34, val);
1da177e4
LT		 2810}
2811
2812static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2813{
1e56a4b4 2814 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2815 int rc;
2816 unsigned long flags;
1da177e4 2817
4a5e8e29
JG		 2818 /* SIOC[GS]MIIxxx ioctls */
2819 if (lp->mii) {
2820 spin_lock_irqsave(&lp->lock, flags);
2821 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2822 spin_unlock_irqrestore(&lp->lock, flags);
2823 } else {
2824 rc = -EOPNOTSUPP;
2825 }
1da177e4 2826
4a5e8e29 2827 return rc;
1da177e4
LT		 2828}
2829
ac62ef04
DF		 2830static int pcnet32_check_otherphy(struct net_device *dev)
2831{
1e56a4b4 2832 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2833 struct mii_if_info mii = lp->mii_if;
2834 u16 bmcr;
2835 int i;
ac62ef04 2836
4a5e8e29
JG		 2837 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2838 if (i == lp->mii_if.phy_id)
2839 continue; /* skip active phy */
2840 if (lp->phymask & (1 << i)) {
2841 mii.phy_id = i;
2842 if (mii_link_ok(&mii)) {
2843 /* found PHY with active link */
2844 if (netif_msg_link(lp))
2845 printk(KERN_INFO
2846 "%s: Using PHY number %d.\n",
2847 dev->name, i);
2848
2849 /* isolate inactive phy */
2850 bmcr =
2851 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2852 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2853 bmcr | BMCR_ISOLATE);
2854
2855 /* de-isolate new phy */
2856 bmcr = mdio_read(dev, i, MII_BMCR);
2857 mdio_write(dev, i, MII_BMCR,
2858 bmcr & ~BMCR_ISOLATE);
2859
2860 /* set new phy address */
2861 lp->mii_if.phy_id = i;
2862 return 1;
2863 }
2864 }
ac62ef04 2865 }
4a5e8e29 2866 return 0;
ac62ef04
DF		 2867}
2868
2869/*
2870 * Show the status of the media. Similar to mii_check_media however it
2871 * correctly shows the link speed for all (tested) pcnet32 variants.
2872 * Devices with no mii just report link state without speed.
2873 *
2874 * Caller is assumed to hold and release the lp->lock.
2875 */
2876
2877static void pcnet32_check_media(struct net_device *dev, int verbose)
2878{
1e56a4b4 2879 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2880 int curr_link;
2881 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2882 u32 bcr9;
2883
ac62ef04 2884 if (lp->mii) {
4a5e8e29 2885 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2886 } else {
4a5e8e29
JG		 2887 ulong ioaddr = dev->base_addr; /* card base I/O address */
2888 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2889 }
2890 if (!curr_link) {
2891 if (prev_link || verbose) {
2892 netif_carrier_off(dev);
2893 if (netif_msg_link(lp))
2894 printk(KERN_INFO "%s: link down\n", dev->name);
2895 }
2896 if (lp->phycount > 1) {
2897 curr_link = pcnet32_check_otherphy(dev);
2898 prev_link = 0;
2899 }
2900 } else if (verbose || !prev_link) {
2901 netif_carrier_on(dev);
2902 if (lp->mii) {
2903 if (netif_msg_link(lp)) {
2904 struct ethtool_cmd ecmd;
2905 mii_ethtool_gset(&lp->mii_if, &ecmd);
2906 printk(KERN_INFO
2907 "%s: link up, %sMbps, %s-duplex\n",
2908 dev->name,
2909 (ecmd.speed == SPEED_100) ? "100" : "10",
2910 (ecmd.duplex ==
2911 DUPLEX_FULL) ? "full" : "half");
2912 }
2913 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2914 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2915 if (lp->mii_if.full_duplex)
2916 bcr9 |= (1 << 0);
2917 else
2918 bcr9 &= ~(1 << 0);
2919 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2920 }
2921 } else {
2922 if (netif_msg_link(lp))
2923 printk(KERN_INFO "%s: link up\n", dev->name);
2924 }
ac62ef04 2925 }
ac62ef04
DF		 2926}
2927
2928/*
2929 * Check for loss of link and link establishment.
2930 * Can not use mii_check_media because it does nothing if mode is forced.
2931 */
2932
1da177e4
LT		 2933static void pcnet32_watchdog(struct net_device *dev)
2934{
1e56a4b4 2935 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2936 unsigned long flags;
1da177e4 2937
4a5e8e29
JG		 2938 /* Print the link status if it has changed */
2939 spin_lock_irqsave(&lp->lock, flags);
2940 pcnet32_check_media(dev, 0);
2941 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2942
4a5e8e29 2943 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1da177e4
LT		 2944}
2945
2946static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2947{
4a5e8e29
JG		 2948 struct net_device *dev = pci_get_drvdata(pdev);
2949
2950 if (dev) {
1e56a4b4 2951 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2952
2953 unregister_netdev(dev);
2954 pcnet32_free_ring(dev);
2955 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
6ecb7667
DF		 2956 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2957 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 2958 free_netdev(dev);
2959 pci_disable_device(pdev);
2960 pci_set_drvdata(pdev, NULL);
2961 }
1da177e4
LT		 2962}
2963
2964static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 2965 .name = DRV_NAME,
2966 .probe = pcnet32_probe_pci,
2967 .remove = __devexit_p(pcnet32_remove_one),
2968 .id_table = pcnet32_pci_tbl,
1da177e4
LT		 2969};
2970
2971/* An additional parameter that may be passed in... */
2972static int debug = -1;
2973static int tx_start_pt = -1;
2974static int pcnet32_have_pci;
2975
2976module_param(debug, int, 0);
2977MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2978module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 2979MODULE_PARM_DESC(max_interrupt_work,
2980 DRV_NAME " maximum events handled per interrupt");
1da177e4 2981module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 2982MODULE_PARM_DESC(rx_copybreak,
2983 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 2984module_param(tx_start_pt, int, 0);
2985MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2986module_param(pcnet32vlb, int, 0);
2987MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2988module_param_array(options, int, NULL, 0);
2989MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2990module_param_array(full_duplex, int, NULL, 0);
2991MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2992/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2993module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 2994MODULE_PARM_DESC(homepna,
2995 DRV_NAME
2996 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 2997
2998MODULE_AUTHOR("Thomas Bogendoerfer");
2999MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3000MODULE_LICENSE("GPL");
3001
3002#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3003
3004static int __init pcnet32_init_module(void)
3005{
4a5e8e29 3006 printk(KERN_INFO "%s", version);
1da177e4 3007
4a5e8e29 3008 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 3009
4a5e8e29
JG		 3010 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3011 tx_start = tx_start_pt;
1da177e4 3012
4a5e8e29 3013 /* find the PCI devices */
29917620 3014 if (!pci_register_driver(&pcnet32_driver))
4a5e8e29 3015 pcnet32_have_pci = 1;
1da177e4 3016
4a5e8e29
JG		 3017 /* should we find any remaining VLbus devices ? */
3018 if (pcnet32vlb)
dcaf9769 3019 pcnet32_probe_vlbus(pcnet32_portlist);
1da177e4 3020
4a5e8e29
JG		 3021 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3022 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1da177e4 3023
4a5e8e29 3024 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 3025}
3026
3027static void __exit pcnet32_cleanup_module(void)
3028{
4a5e8e29
JG		 3029 struct net_device *next_dev;
3030
3031 while (pcnet32_dev) {
1e56a4b4 3032 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
4a5e8e29
JG		 3033 next_dev = lp->next;
3034 unregister_netdev(pcnet32_dev);
3035 pcnet32_free_ring(pcnet32_dev);
3036 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
6ecb7667
DF		 3037 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3038 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 3039 free_netdev(pcnet32_dev);
3040 pcnet32_dev = next_dev;
3041 }
1da177e4 3042
4a5e8e29
JG		 3043 if (pcnet32_have_pci)
3044 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 3045}
3046
3047module_init(pcnet32_init_module);
3048module_exit(pcnet32_cleanup_module);
3049
3050/*
3051 * Local variables:
3052 * c-indent-level: 4
3053 * tab-width: 8
3054 * End:
3055 */
Linux kernel - Deliverables
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