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b560a58c FF |
1 | /* |
2 | * Broadcom BCM7xxx internal transceivers support. | |
3 | * | |
4 | * Copyright (C) 2014, Broadcom Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/phy.h> | |
14 | #include <linux/delay.h> | |
a1cba561 | 15 | #include "bcm-phy-lib.h" |
b560a58c FF |
16 | #include <linux/bitops.h> |
17 | #include <linux/brcmphy.h> | |
b8f9a029 | 18 | #include <linux/mdio.h> |
b560a58c FF |
19 | |
20 | /* Broadcom BCM7xxx internal PHY registers */ | |
b560a58c FF |
21 | |
22 | /* 40nm only register definitions */ | |
23 | #define MII_BCM7XXX_100TX_AUX_CTL 0x10 | |
24 | #define MII_BCM7XXX_100TX_FALSE_CAR 0x13 | |
25 | #define MII_BCM7XXX_100TX_DISC 0x14 | |
26 | #define MII_BCM7XXX_AUX_MODE 0x1d | |
27 | #define MII_BCM7XX_64CLK_MDIO BIT(12) | |
28 | #define MII_BCM7XXX_CORE_BASE1E 0x1e | |
29 | #define MII_BCM7XXX_TEST 0x1f | |
30 | #define MII_BCM7XXX_SHD_MODE_2 BIT(2) | |
31 | ||
a3622f2c FF |
32 | /* 28nm only register definitions */ |
33 | #define MISC_ADDR(base, channel) base, channel | |
34 | ||
35 | #define DSP_TAP10 MISC_ADDR(0x0a, 0) | |
36 | #define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1) | |
37 | #define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2) | |
38 | #define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0) | |
39 | ||
40 | #define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0) | |
41 | #define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1) | |
a490631f | 42 | #define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2) |
a3622f2c FF |
43 | #define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3) |
44 | #define AFE_TX_CONFIG MISC_ADDR(0x39, 0) | |
a490631f FF |
45 | #define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1) |
46 | #define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3) | |
a3622f2c FF |
47 | #define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0) |
48 | ||
49 | #define CORE_EXPB0 0xb0 | |
50 | ||
9c41f2ba FF |
51 | static void r_rc_cal_reset(struct phy_device *phydev) |
52 | { | |
53 | /* Reset R_CAL/RC_CAL Engine */ | |
a1cba561 | 54 | bcm_phy_write_exp(phydev, 0x00b0, 0x0010); |
9c41f2ba FF |
55 | |
56 | /* Disable Reset R_AL/RC_CAL Engine */ | |
a1cba561 | 57 | bcm_phy_write_exp(phydev, 0x00b0, 0x0000); |
9c41f2ba FF |
58 | } |
59 | ||
2a9df742 | 60 | static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev) |
b560a58c | 61 | { |
b560a58c FF |
62 | /* Increase VCO range to prevent unlocking problem of PLL at low |
63 | * temp | |
64 | */ | |
a1cba561 | 65 | bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048); |
b560a58c FF |
66 | |
67 | /* Change Ki to 011 */ | |
a1cba561 | 68 | bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b); |
b560a58c FF |
69 | |
70 | /* Disable loading of TVCO buffer to bandgap, set bandgap trim | |
71 | * to 111 | |
72 | */ | |
a1cba561 | 73 | bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20); |
b560a58c FF |
74 | |
75 | /* Adjust bias current trim by -3 */ | |
a1cba561 | 76 | bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b); |
b560a58c FF |
77 | |
78 | /* Switch to CORE_BASE1E */ | |
79 | phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd); | |
80 | ||
9c41f2ba | 81 | r_rc_cal_reset(phydev); |
b560a58c | 82 | |
9918542e | 83 | /* write AFE_RXCONFIG_0 */ |
a1cba561 | 84 | bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19); |
9918542e FF |
85 | |
86 | /* write AFE_RXCONFIG_1 */ | |
a1cba561 | 87 | bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f); |
9918542e FF |
88 | |
89 | /* write AFE_RX_LP_COUNTER */ | |
a1cba561 | 90 | bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); |
9918542e FF |
91 | |
92 | /* write AFE_HPF_TRIM_OTHERS */ | |
a1cba561 | 93 | bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b); |
9918542e FF |
94 | |
95 | /* write AFTE_TX_CONFIG */ | |
a1cba561 | 96 | bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800); |
9918542e | 97 | |
b560a58c FF |
98 | return 0; |
99 | } | |
100 | ||
a490631f FF |
101 | static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev) |
102 | { | |
103 | /* AFE_RXCONFIG_0 */ | |
a1cba561 | 104 | bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15); |
a490631f FF |
105 | |
106 | /* AFE_RXCONFIG_1 */ | |
a1cba561 | 107 | bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); |
a490631f FF |
108 | |
109 | /* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */ | |
a1cba561 | 110 | bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003); |
a490631f FF |
111 | |
112 | /* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */ | |
a1cba561 | 113 | bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); |
a490631f | 114 | |
6da8253b | 115 | /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */ |
a1cba561 | 116 | bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); |
a490631f FF |
117 | |
118 | /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */ | |
a1cba561 | 119 | bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); |
a490631f FF |
120 | |
121 | /* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */ | |
a1cba561 | 122 | bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020); |
a490631f FF |
123 | |
124 | /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal | |
125 | * offset for HT=0 code | |
126 | */ | |
a1cba561 | 127 | bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); |
a490631f FF |
128 | |
129 | /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */ | |
130 | phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010); | |
131 | ||
132 | /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */ | |
a1cba561 | 133 | bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); |
a490631f FF |
134 | |
135 | /* Reset R_CAL/RC_CAL engine */ | |
136 | r_rc_cal_reset(phydev); | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
0c2fdc25 FF |
141 | static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev) |
142 | { | |
143 | /* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */ | |
a1cba561 | 144 | bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f); |
0c2fdc25 | 145 | |
6da8253b | 146 | /* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */ |
a1cba561 | 147 | bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431); |
6da8253b | 148 | |
0c2fdc25 | 149 | /* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */ |
a1cba561 | 150 | bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da); |
0c2fdc25 FF |
151 | |
152 | /* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal | |
153 | * offset for HT=0 code | |
154 | */ | |
a1cba561 | 155 | bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3); |
0c2fdc25 FF |
156 | |
157 | /* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */ | |
158 | phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010); | |
159 | ||
160 | /* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */ | |
a1cba561 | 161 | bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b); |
0c2fdc25 FF |
162 | |
163 | /* Reset R_CAL/RC_CAL engine */ | |
164 | r_rc_cal_reset(phydev); | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
b560a58c FF |
169 | static int bcm7xxx_28nm_config_init(struct phy_device *phydev) |
170 | { | |
d8ebfed3 FF |
171 | u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags); |
172 | u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags); | |
173 | int ret = 0; | |
174 | ||
6ec259c1 FF |
175 | pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n", |
176 | dev_name(&phydev->dev), phydev->drv->name, rev, patch); | |
d8ebfed3 | 177 | |
8e346e15 FF |
178 | /* Dummy read to a register to workaround an issue upon reset where the |
179 | * internal inverter may not allow the first MDIO transaction to pass | |
180 | * the MDIO management controller and make us return 0xffff for such | |
181 | * reads. | |
182 | */ | |
183 | phy_read(phydev, MII_BMSR); | |
184 | ||
d8ebfed3 | 185 | switch (rev) { |
d8ebfed3 | 186 | case 0xb0: |
2a9df742 | 187 | ret = bcm7xxx_28nm_b0_afe_config_init(phydev); |
d8ebfed3 | 188 | break; |
a490631f FF |
189 | case 0xd0: |
190 | ret = bcm7xxx_28nm_d0_afe_config_init(phydev); | |
191 | break; | |
0c2fdc25 FF |
192 | case 0xe0: |
193 | case 0xf0: | |
60efff0c FF |
194 | /* Rev G0 introduces a roll over */ |
195 | case 0x10: | |
0c2fdc25 FF |
196 | ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev); |
197 | break; | |
d8ebfed3 | 198 | default: |
d8ebfed3 FF |
199 | break; |
200 | } | |
b560a58c | 201 | |
9df54dda FF |
202 | if (ret) |
203 | return ret; | |
204 | ||
a1cba561 | 205 | ret = bcm_phy_enable_eee(phydev); |
b8f9a029 FF |
206 | if (ret) |
207 | return ret; | |
208 | ||
a1cba561 | 209 | return bcm_phy_enable_apd(phydev, true); |
b560a58c FF |
210 | } |
211 | ||
4fd14e0b FF |
212 | static int bcm7xxx_28nm_resume(struct phy_device *phydev) |
213 | { | |
214 | int ret; | |
215 | ||
216 | /* Re-apply workarounds coming out suspend/resume */ | |
217 | ret = bcm7xxx_28nm_config_init(phydev); | |
218 | if (ret) | |
219 | return ret; | |
220 | ||
221 | /* 28nm Gigabit PHYs come out of reset without any half-duplex | |
222 | * or "hub" compliant advertised mode, fix that. This does not | |
223 | * cause any problems with the PHY library since genphy_config_aneg() | |
224 | * gracefully handles auto-negotiated and forced modes. | |
225 | */ | |
226 | return genphy_config_aneg(phydev); | |
227 | } | |
228 | ||
b560a58c FF |
229 | static int phy_set_clr_bits(struct phy_device *dev, int location, |
230 | int set_mask, int clr_mask) | |
231 | { | |
232 | int v, ret; | |
233 | ||
234 | v = phy_read(dev, location); | |
235 | if (v < 0) | |
236 | return v; | |
237 | ||
238 | v &= ~clr_mask; | |
239 | v |= set_mask; | |
240 | ||
241 | ret = phy_write(dev, location, v); | |
242 | if (ret < 0) | |
243 | return ret; | |
244 | ||
245 | return v; | |
246 | } | |
247 | ||
248 | static int bcm7xxx_config_init(struct phy_device *phydev) | |
249 | { | |
250 | int ret; | |
251 | ||
252 | /* Enable 64 clock MDIO */ | |
253 | phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO); | |
254 | phy_read(phydev, MII_BCM7XXX_AUX_MODE); | |
255 | ||
e18556ee FF |
256 | /* Workaround only required for 100Mbits/sec capable PHYs */ |
257 | if (phydev->supported & PHY_GBIT_FEATURES) | |
b560a58c FF |
258 | return 0; |
259 | ||
260 | /* set shadow mode 2 */ | |
261 | ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, | |
262 | MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2); | |
263 | if (ret < 0) | |
264 | return ret; | |
265 | ||
266 | /* set iddq_clkbias */ | |
267 | phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); | |
268 | udelay(10); | |
269 | ||
270 | /* reset iddq_clkbias */ | |
271 | phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); | |
272 | ||
273 | phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555); | |
274 | ||
275 | /* reset shadow mode 2 */ | |
276 | ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0); | |
277 | if (ret < 0) | |
278 | return ret; | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
283 | /* Workaround for putting the PHY in IDDQ mode, required | |
82c084f5 | 284 | * for all BCM7XXX 40nm and 65nm PHYs |
b560a58c FF |
285 | */ |
286 | static int bcm7xxx_suspend(struct phy_device *phydev) | |
287 | { | |
288 | int ret; | |
289 | const struct bcm7xxx_regs { | |
290 | int reg; | |
291 | u16 value; | |
292 | } bcm7xxx_suspend_cfg[] = { | |
293 | { MII_BCM7XXX_TEST, 0x008b }, | |
294 | { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 }, | |
295 | { MII_BCM7XXX_100TX_DISC, 0x7000 }, | |
296 | { MII_BCM7XXX_TEST, 0x000f }, | |
297 | { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 }, | |
298 | { MII_BCM7XXX_TEST, 0x000b }, | |
299 | }; | |
300 | unsigned int i; | |
301 | ||
302 | for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) { | |
303 | ret = phy_write(phydev, | |
304 | bcm7xxx_suspend_cfg[i].reg, | |
305 | bcm7xxx_suspend_cfg[i].value); | |
306 | if (ret) | |
307 | return ret; | |
308 | } | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | static int bcm7xxx_dummy_config_init(struct phy_device *phydev) | |
314 | { | |
315 | return 0; | |
316 | } | |
317 | ||
153df3c7 FF |
318 | #define BCM7XXX_28NM_GPHY(_oui, _name) \ |
319 | { \ | |
320 | .phy_id = (_oui), \ | |
321 | .phy_id_mask = 0xfffffff0, \ | |
322 | .name = _name, \ | |
323 | .features = PHY_GBIT_FEATURES | \ | |
324 | SUPPORTED_Pause | SUPPORTED_Asym_Pause, \ | |
325 | .flags = PHY_IS_INTERNAL, \ | |
2a9df742 | 326 | .config_init = bcm7xxx_28nm_config_init, \ |
153df3c7 FF |
327 | .config_aneg = genphy_config_aneg, \ |
328 | .read_status = genphy_read_status, \ | |
329 | .resume = bcm7xxx_28nm_resume, \ | |
330 | .driver = { .owner = THIS_MODULE }, \ | |
331 | } | |
332 | ||
b560a58c | 333 | static struct phy_driver bcm7xxx_driver[] = { |
430ad68f FF |
334 | BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"), |
335 | BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"), | |
153df3c7 FF |
336 | BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"), |
337 | BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"), | |
59e33c2b | 338 | BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"), |
153df3c7 | 339 | BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"), |
b560a58c | 340 | { |
d068b02c PG |
341 | .phy_id = PHY_ID_BCM7425, |
342 | .phy_id_mask = 0xfffffff0, | |
343 | .name = "Broadcom BCM7425", | |
344 | .features = PHY_GBIT_FEATURES | | |
345 | SUPPORTED_Pause | SUPPORTED_Asym_Pause, | |
cc4a84c3 | 346 | .flags = PHY_IS_INTERNAL, |
d068b02c PG |
347 | .config_init = bcm7xxx_config_init, |
348 | .config_aneg = genphy_config_aneg, | |
349 | .read_status = genphy_read_status, | |
350 | .suspend = bcm7xxx_suspend, | |
351 | .resume = bcm7xxx_config_init, | |
352 | .driver = { .owner = THIS_MODULE }, | |
353 | }, { | |
354 | .phy_id = PHY_ID_BCM7429, | |
355 | .phy_id_mask = 0xfffffff0, | |
356 | .name = "Broadcom BCM7429", | |
357 | .features = PHY_GBIT_FEATURES | | |
358 | SUPPORTED_Pause | SUPPORTED_Asym_Pause, | |
359 | .flags = PHY_IS_INTERNAL, | |
360 | .config_init = bcm7xxx_config_init, | |
361 | .config_aneg = genphy_config_aneg, | |
362 | .read_status = genphy_read_status, | |
363 | .suspend = bcm7xxx_suspend, | |
364 | .resume = bcm7xxx_config_init, | |
365 | .driver = { .owner = THIS_MODULE }, | |
366 | }, { | |
b560a58c FF |
367 | .phy_id = PHY_BCM_OUI_4, |
368 | .phy_id_mask = 0xffff0000, | |
369 | .name = "Broadcom BCM7XXX 40nm", | |
370 | .features = PHY_GBIT_FEATURES | | |
371 | SUPPORTED_Pause | SUPPORTED_Asym_Pause, | |
372 | .flags = PHY_IS_INTERNAL, | |
373 | .config_init = bcm7xxx_config_init, | |
374 | .config_aneg = genphy_config_aneg, | |
375 | .read_status = genphy_read_status, | |
376 | .suspend = bcm7xxx_suspend, | |
377 | .resume = bcm7xxx_config_init, | |
378 | .driver = { .owner = THIS_MODULE }, | |
379 | }, { | |
380 | .phy_id = PHY_BCM_OUI_5, | |
381 | .phy_id_mask = 0xffffff00, | |
382 | .name = "Broadcom BCM7XXX 65nm", | |
383 | .features = PHY_BASIC_FEATURES | | |
384 | SUPPORTED_Pause | SUPPORTED_Asym_Pause, | |
385 | .flags = PHY_IS_INTERNAL, | |
386 | .config_init = bcm7xxx_dummy_config_init, | |
387 | .config_aneg = genphy_config_aneg, | |
388 | .read_status = genphy_read_status, | |
389 | .suspend = bcm7xxx_suspend, | |
390 | .resume = bcm7xxx_config_init, | |
391 | .driver = { .owner = THIS_MODULE }, | |
392 | } }; | |
393 | ||
394 | static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = { | |
430ad68f FF |
395 | { PHY_ID_BCM7250, 0xfffffff0, }, |
396 | { PHY_ID_BCM7364, 0xfffffff0, }, | |
b560a58c | 397 | { PHY_ID_BCM7366, 0xfffffff0, }, |
d068b02c PG |
398 | { PHY_ID_BCM7425, 0xfffffff0, }, |
399 | { PHY_ID_BCM7429, 0xfffffff0, }, | |
b560a58c FF |
400 | { PHY_ID_BCM7439, 0xfffffff0, }, |
401 | { PHY_ID_BCM7445, 0xfffffff0, }, | |
b560a58c FF |
402 | { PHY_BCM_OUI_4, 0xffff0000 }, |
403 | { PHY_BCM_OUI_5, 0xffffff00 }, | |
404 | { } | |
405 | }; | |
406 | ||
50fd7150 | 407 | module_phy_driver(bcm7xxx_driver); |
b560a58c FF |
408 | |
409 | MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl); | |
410 | ||
411 | MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver"); | |
412 | MODULE_LICENSE("GPL"); | |
413 | MODULE_AUTHOR("Broadcom Corporation"); |