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Merge branch 'ethtool-perqueue-params'
[deliverable/linux.git] / drivers / net / phy / marvell.c
CommitLineData
00db8189
AF		 1/*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
3871c387
MS		 10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
00db8189
AF		 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
00db8189 18#include <linux/kernel.h>
00db8189
AF		 19#include <linux/string.h>
20#include <linux/errno.h>
21#include <linux/unistd.h>
00db8189
AF		 22#include <linux/interrupt.h>
23#include <linux/init.h>
24#include <linux/delay.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/spinlock.h>
29#include <linux/mm.h>
30#include <linux/module.h>
00db8189
AF		 31#include <linux/mii.h>
32#include <linux/ethtool.h>
33#include <linux/phy.h>
2f495c39 34#include <linux/marvell_phy.h>
cf41a51d 35#include <linux/of.h>
00db8189 36
eea3b201 37#include <linux/io.h>
00db8189 38#include <asm/irq.h>
eea3b201 39#include <linux/uaccess.h>
00db8189 40
27d916d6
DD		 41#define MII_MARVELL_PHY_PAGE 22
42
00db8189
AF		 43#define MII_M1011_IEVENT 0x13
44#define MII_M1011_IEVENT_CLEAR 0x0000
45
46#define MII_M1011_IMASK 0x12
47#define MII_M1011_IMASK_INIT 0x6400
48#define MII_M1011_IMASK_CLEAR 0x0000
49
76884679 50#define MII_M1011_PHY_SCR 0x10
239aa55b
DT		 51#define MII_M1011_PHY_SCR_MDI 0x0000
52#define MII_M1011_PHY_SCR_MDI_X 0x0020
76884679
AF		 53#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
54
07151bc9 55#define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
b0224175 56#define MII_M1145_PHY_EXT_SR 0x1b
76884679
AF		 57#define MII_M1145_PHY_EXT_CR 0x14
58#define MII_M1145_RGMII_RX_DELAY 0x0080
59#define MII_M1145_RGMII_TX_DELAY 0x0002
b0224175
VND		 60#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
61#define MII_M1145_HWCFG_MODE_MASK 0xf
62#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
76884679 63
99d881f9
VB		 64#define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
65#define MII_M1145_HWCFG_MODE_MASK 0xf
66#define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
67
76884679
AF		 68#define MII_M1111_PHY_LED_CONTROL 0x18
69#define MII_M1111_PHY_LED_DIRECT 0x4100
70#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682
KP		 71#define MII_M1111_PHY_EXT_CR 0x14
72#define MII_M1111_RX_DELAY 0x80
73#define MII_M1111_TX_DELAY 0x2
74#define MII_M1111_PHY_EXT_SR 0x1b
be937f1f
AS		 75
76#define MII_M1111_HWCFG_MODE_MASK 0xf
77#define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
78#define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
4117b5be 79#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
5f8cbc13 80#define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
be937f1f
AS		 81#define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
82#define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
83
84#define MII_M1111_COPPER 0
85#define MII_M1111_FIBER 1
86
c477d044
CC		 87#define MII_88E1121_PHY_MSCR_PAGE 2
88#define MII_88E1121_PHY_MSCR_REG 21
89#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
90#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
91#define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
92
337ac9d5
CC		 93#define MII_88E1318S_PHY_MSCR1_REG 16
94#define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
3ff1c259 95
3871c387
MS		 96/* Copper Specific Interrupt Enable Register */
97#define MII_88E1318S_PHY_CSIER 0x12
98/* WOL Event Interrupt Enable */
99#define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
100
101/* LED Timer Control Register */
102#define MII_88E1318S_PHY_LED_PAGE 0x03
103#define MII_88E1318S_PHY_LED_TCR 0x12
104#define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
105#define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
106#define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
107
108/* Magic Packet MAC address registers */
109#define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
110#define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
111#define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
112
113#define MII_88E1318S_PHY_WOL_PAGE 0x11
114#define MII_88E1318S_PHY_WOL_CTRL 0x10
115#define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
116#define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
117
140bc929
SP		 118#define MII_88E1121_PHY_LED_CTRL 16
119#define MII_88E1121_PHY_LED_PAGE 3
120#define MII_88E1121_PHY_LED_DEF 0x0030
140bc929 121
be937f1f
AS		 122#define MII_M1011_PHY_STATUS 0x11
123#define MII_M1011_PHY_STATUS_1000 0x8000
124#define MII_M1011_PHY_STATUS_100 0x4000
125#define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
126#define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
127#define MII_M1011_PHY_STATUS_RESOLVED 0x0800
128#define MII_M1011_PHY_STATUS_LINK 0x0400
129
3da09a51
MS		 130#define MII_M1116R_CONTROL_REG_MAC 21
131
6b358aed
SH		 132#define MII_88E3016_PHY_SPEC_CTRL 0x10
133#define MII_88E3016_DISABLE_SCRAMBLER 0x0200
134#define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
76884679 135
930b37ee
SR		 136#define MII_88E1510_GEN_CTRL_REG_1 0x14
137#define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
138#define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
139#define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
140
00db8189
AF		 141MODULE_DESCRIPTION("Marvell PHY driver");
142MODULE_AUTHOR("Andy Fleming");
143MODULE_LICENSE("GPL");
144
d2fa47d9
AL		 145struct marvell_hw_stat {
146 const char *string;
147 u8 page;
148 u8 reg;
149 u8 bits;
150};
151
152static struct marvell_hw_stat marvell_hw_stats[] = {
153 { "phy_receive_errors", 0, 21, 16},
154 { "phy_idle_errors", 0, 10, 8 },
155};
156
157struct marvell_priv {
158 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
159};
160
00db8189
AF		 161static int marvell_ack_interrupt(struct phy_device *phydev)
162{
163 int err;
164
165 /* Clear the interrupts by reading the reg */
166 err = phy_read(phydev, MII_M1011_IEVENT);
167
168 if (err < 0)
169 return err;
170
171 return 0;
172}
173
174static int marvell_config_intr(struct phy_device *phydev)
175{
176 int err;
177
76884679 178 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189
AF		 179 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
180 else
181 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
182
183 return err;
184}
185
239aa55b
DT		 186static int marvell_set_polarity(struct phy_device *phydev, int polarity)
187{
188 int reg;
189 int err;
190 int val;
191
192 /* get the current settings */
193 reg = phy_read(phydev, MII_M1011_PHY_SCR);
194 if (reg < 0)
195 return reg;
196
197 val = reg;
198 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
199 switch (polarity) {
200 case ETH_TP_MDI:
201 val |= MII_M1011_PHY_SCR_MDI;
202 break;
203 case ETH_TP_MDI_X:
204 val |= MII_M1011_PHY_SCR_MDI_X;
205 break;
206 case ETH_TP_MDI_AUTO:
207 case ETH_TP_MDI_INVALID:
208 default:
209 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
210 break;
211 }
212
213 if (val != reg) {
214 /* Set the new polarity value in the register */
215 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
216 if (err)
217 return err;
218 }
219
220 return 0;
221}
222
00db8189
AF		 223static int marvell_config_aneg(struct phy_device *phydev)
224{
225 int err;
226
227 /* The Marvell PHY has an errata which requires
228 * that certain registers get written in order
229 * to restart autonegotiation */
230 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
231
232 if (err < 0)
233 return err;
234
235 err = phy_write(phydev, 0x1d, 0x1f);
236 if (err < 0)
237 return err;
238
239 err = phy_write(phydev, 0x1e, 0x200c);
240 if (err < 0)
241 return err;
242
243 err = phy_write(phydev, 0x1d, 0x5);
244 if (err < 0)
245 return err;
246
247 err = phy_write(phydev, 0x1e, 0);
248 if (err < 0)
249 return err;
250
251 err = phy_write(phydev, 0x1e, 0x100);
252 if (err < 0)
253 return err;
254
239aa55b 255 err = marvell_set_polarity(phydev, phydev->mdix);
76884679
AF		 256 if (err < 0)
257 return err;
258
259 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
260 MII_M1111_PHY_LED_DIRECT);
261 if (err < 0)
262 return err;
00db8189
AF		 263
264 err = genphy_config_aneg(phydev);
8ff44985
AV		 265 if (err < 0)
266 return err;
00db8189 267
8ff44985
AV		 268 if (phydev->autoneg != AUTONEG_ENABLE) {
269 int bmcr;
270
271 /*
272 * A write to speed/duplex bits (that is performed by
273 * genphy_config_aneg() call above) must be followed by
274 * a software reset. Otherwise, the write has no effect.
275 */
276 bmcr = phy_read(phydev, MII_BMCR);
277 if (bmcr < 0)
278 return bmcr;
279
280 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
281 if (err < 0)
282 return err;
283 }
284
285 return 0;
00db8189
AF		 286}
287
cf41a51d
DD		 288#ifdef CONFIG_OF_MDIO
289/*
290 * Set and/or override some configuration registers based on the
291 * marvell,reg-init property stored in the of_node for the phydev.
292 *
293 * marvell,reg-init = <reg-page reg mask value>,...;
294 *
295 * There may be one or more sets of <reg-page reg mask value>:
296 *
297 * reg-page: which register bank to use.
298 * reg: the register.
299 * mask: if non-zero, ANDed with existing register value.
300 * value: ORed with the masked value and written to the regiser.
301 *
302 */
303static int marvell_of_reg_init(struct phy_device *phydev)
304{
305 const __be32 *paddr;
306 int len, i, saved_page, current_page, page_changed, ret;
307
e5a03bfd 308 if (!phydev->mdio.dev.of_node)
cf41a51d
DD		 309 return 0;
310
e5a03bfd
AL		 311 paddr = of_get_property(phydev->mdio.dev.of_node,
312 "marvell,reg-init", &len);
cf41a51d
DD		 313 if (!paddr || len < (4 * sizeof(*paddr)))
314 return 0;
315
316 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
317 if (saved_page < 0)
318 return saved_page;
319 page_changed = 0;
320 current_page = saved_page;
321
322 ret = 0;
323 len /= sizeof(*paddr);
324 for (i = 0; i < len - 3; i += 4) {
325 u16 reg_page = be32_to_cpup(paddr + i);
326 u16 reg = be32_to_cpup(paddr + i + 1);
327 u16 mask = be32_to_cpup(paddr + i + 2);
328 u16 val_bits = be32_to_cpup(paddr + i + 3);
329 int val;
330
331 if (reg_page != current_page) {
332 current_page = reg_page;
333 page_changed = 1;
334 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
335 if (ret < 0)
336 goto err;
337 }
338
339 val = 0;
340 if (mask) {
341 val = phy_read(phydev, reg);
342 if (val < 0) {
343 ret = val;
344 goto err;
345 }
346 val &= mask;
347 }
348 val |= val_bits;
349
350 ret = phy_write(phydev, reg, val);
351 if (ret < 0)
352 goto err;
353
354 }
355err:
356 if (page_changed) {
357 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
358 if (ret == 0)
359 ret = i;
360 }
361 return ret;
362}
363#else
364static int marvell_of_reg_init(struct phy_device *phydev)
365{
366 return 0;
367}
368#endif /* CONFIG_OF_MDIO */
369
140bc929
SP		 370static int m88e1121_config_aneg(struct phy_device *phydev)
371{
c477d044
CC		 372 int err, oldpage, mscr;
373
27d916d6 374 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
c477d044 375
27d916d6 376 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
c477d044
CC		 377 MII_88E1121_PHY_MSCR_PAGE);
378 if (err < 0)
379 return err;
be8c6480 380
32a64161 381 if (phy_interface_is_rgmii(phydev)) {
be8c6480
AP		 382
383 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
384 MII_88E1121_PHY_MSCR_DELAY_MASK;
385
386 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
387 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
388 MII_88E1121_PHY_MSCR_TX_DELAY);
389 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
390 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
391 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
392 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
393
394 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
395 if (err < 0)
396 return err;
397 }
c477d044 398
27d916d6 399 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 400
401 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
402 if (err < 0)
403 return err;
404
405 err = phy_write(phydev, MII_M1011_PHY_SCR,
406 MII_M1011_PHY_SCR_AUTO_CROSS);
407 if (err < 0)
408 return err;
409
27d916d6 410 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
140bc929 411
27d916d6 412 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
140bc929 413 phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
27d916d6 414 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
140bc929
SP		 415
416 err = genphy_config_aneg(phydev);
417
418 return err;
419}
420
337ac9d5 421static int m88e1318_config_aneg(struct phy_device *phydev)
3ff1c259
CC		 422{
423 int err, oldpage, mscr;
424
27d916d6 425 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
3ff1c259 426
27d916d6 427 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
3ff1c259
CC		 428 MII_88E1121_PHY_MSCR_PAGE);
429 if (err < 0)
430 return err;
431
337ac9d5
CC		 432 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
433 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
3ff1c259 434
337ac9d5 435 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
3ff1c259
CC		 436 if (err < 0)
437 return err;
438
27d916d6 439 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
3ff1c259
CC		 440 if (err < 0)
441 return err;
442
443 return m88e1121_config_aneg(phydev);
444}
445
930b37ee
SR		 446static int m88e1510_config_init(struct phy_device *phydev)
447{
448 int err;
449 int temp;
450
451 /* SGMII-to-Copper mode initialization */
452 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
453 /* Select page 18 */
454 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 18);
455 if (err < 0)
456 return err;
457
458 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
459 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
460 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
461 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
462 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
463 if (err < 0)
464 return err;
465
466 /* PHY reset is necessary after changing MODE[2:0] */
467 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
468 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
469 if (err < 0)
470 return err;
471
472 /* Reset page selection */
473 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
474 if (err < 0)
475 return err;
476 }
477
478 return 0;
479}
480
10e24caa
MS		 481static int m88e1510_config_aneg(struct phy_device *phydev)
482{
483 int err;
484
485 err = m88e1318_config_aneg(phydev);
486 if (err < 0)
487 return err;
488
489 return marvell_of_reg_init(phydev);
490}
491
3da09a51
MS		 492static int m88e1116r_config_init(struct phy_device *phydev)
493{
494 int temp;
495 int err;
496
497 temp = phy_read(phydev, MII_BMCR);
498 temp |= BMCR_RESET;
499 err = phy_write(phydev, MII_BMCR, temp);
500 if (err < 0)
501 return err;
502
503 mdelay(500);
504
505 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
506 if (err < 0)
507 return err;
508
509 temp = phy_read(phydev, MII_M1011_PHY_SCR);
510 temp |= (7 << 12); /* max number of gigabit attempts */
511 temp |= (1 << 11); /* enable downshift */
512 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
513 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
514 if (err < 0)
515 return err;
516
517 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
518 if (err < 0)
519 return err;
520 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
521 temp |= (1 << 5);
522 temp |= (1 << 4);
523 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
524 if (err < 0)
525 return err;
526 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
527 if (err < 0)
528 return err;
529
530 temp = phy_read(phydev, MII_BMCR);
531 temp |= BMCR_RESET;
532 err = phy_write(phydev, MII_BMCR, temp);
533 if (err < 0)
534 return err;
535
536 mdelay(500);
537
538 return 0;
539}
540
6b358aed
SH		 541static int m88e3016_config_init(struct phy_device *phydev)
542{
543 int reg;
544
545 /* Enable Scrambler and Auto-Crossover */
546 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
547 if (reg < 0)
548 return reg;
549
550 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
551 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
552
553 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
554 if (reg < 0)
555 return reg;
556
557 return 0;
558}
559
895ee682
KP		 560static int m88e1111_config_init(struct phy_device *phydev)
561{
562 int err;
be937f1f 563 int temp;
be937f1f 564
32a64161 565 if (phy_interface_is_rgmii(phydev)) {
895ee682 566
9daf5a76
KP		 567 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
568 if (temp < 0)
569 return temp;
895ee682 570
9daf5a76 571 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
895ee682 572 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
9daf5a76
KP		 573 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
574 temp &= ~MII_M1111_TX_DELAY;
575 temp |= MII_M1111_RX_DELAY;
576 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
577 temp &= ~MII_M1111_RX_DELAY;
578 temp |= MII_M1111_TX_DELAY;
895ee682
KP		 579 }
580
9daf5a76
KP		 581 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
582 if (err < 0)
583 return err;
584
895ee682
KP		 585 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
586 if (temp < 0)
587 return temp;
588
589 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
be937f1f 590
7239016d 591 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
be937f1f
AS		 592 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
593 else
594 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
895ee682
KP		 595
596 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
597 if (err < 0)
598 return err;
599 }
600
4117b5be 601 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
4117b5be
KJ		 602 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
603 if (temp < 0)
604 return temp;
605
606 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
607 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
32d0c1e1 608 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
4117b5be
KJ		 609
610 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
611 if (err < 0)
612 return err;
07151bc9
MB		 613
614 /* make sure copper is selected */
615 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
616 if (err < 0)
617 return err;
618
619 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
620 err & (~0xff));
621 if (err < 0)
622 return err;
4117b5be
KJ		 623 }
624
5f8cbc13
LYB		 625 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
626 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
627 if (temp < 0)
628 return temp;
629 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
630 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
631 if (err < 0)
632 return err;
633
634 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
635 if (temp < 0)
636 return temp;
637 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
638 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
639 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
640 if (err < 0)
641 return err;
642
643 /* soft reset */
644 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
645 if (err < 0)
646 return err;
647 do
648 temp = phy_read(phydev, MII_BMCR);
649 while (temp & BMCR_RESET);
650
651 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
652 if (temp < 0)
653 return temp;
654 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
655 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
656 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
657 if (err < 0)
658 return err;
659 }
660
cf41a51d
DD		 661 err = marvell_of_reg_init(phydev);
662 if (err < 0)
663 return err;
5f8cbc13 664
cc90cb3b 665 return phy_write(phydev, MII_BMCR, BMCR_RESET);
895ee682
KP		 666}
667
605f196e
RM		 668static int m88e1118_config_aneg(struct phy_device *phydev)
669{
670 int err;
671
672 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
673 if (err < 0)
674 return err;
675
676 err = phy_write(phydev, MII_M1011_PHY_SCR,
677 MII_M1011_PHY_SCR_AUTO_CROSS);
678 if (err < 0)
679 return err;
680
681 err = genphy_config_aneg(phydev);
682 return 0;
683}
684
685static int m88e1118_config_init(struct phy_device *phydev)
686{
687 int err;
688
689 /* Change address */
27d916d6 690 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
605f196e
RM		 691 if (err < 0)
692 return err;
693
694 /* Enable 1000 Mbit */
695 err = phy_write(phydev, 0x15, 0x1070);
696 if (err < 0)
697 return err;
698
699 /* Change address */
27d916d6 700 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
605f196e
RM		 701 if (err < 0)
702 return err;
703
704 /* Adjust LED Control */
2f495c39
BH		 705 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
706 err = phy_write(phydev, 0x10, 0x1100);
707 else
708 err = phy_write(phydev, 0x10, 0x021e);
605f196e
RM		 709 if (err < 0)
710 return err;
711
cf41a51d
DD		 712 err = marvell_of_reg_init(phydev);
713 if (err < 0)
714 return err;
715
605f196e 716 /* Reset address */
27d916d6 717 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
605f196e
RM		 718 if (err < 0)
719 return err;
720
cc90cb3b 721 return phy_write(phydev, MII_BMCR, BMCR_RESET);
605f196e
RM		 722}
723
90600732
DD		 724static int m88e1149_config_init(struct phy_device *phydev)
725{
726 int err;
727
728 /* Change address */
729 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
730 if (err < 0)
731 return err;
732
733 /* Enable 1000 Mbit */
734 err = phy_write(phydev, 0x15, 0x1048);
735 if (err < 0)
736 return err;
737
cf41a51d
DD		 738 err = marvell_of_reg_init(phydev);
739 if (err < 0)
740 return err;
741
90600732
DD		 742 /* Reset address */
743 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
744 if (err < 0)
745 return err;
746
cc90cb3b 747 return phy_write(phydev, MII_BMCR, BMCR_RESET);
90600732
DD		 748}
749
76884679
AF		 750static int m88e1145_config_init(struct phy_device *phydev)
751{
752 int err;
b0224175 753 int temp;
76884679
AF		 754
755 /* Take care of errata E0 & E1 */
756 err = phy_write(phydev, 0x1d, 0x001b);
757 if (err < 0)
758 return err;
759
760 err = phy_write(phydev, 0x1e, 0x418f);
761 if (err < 0)
762 return err;
763
764 err = phy_write(phydev, 0x1d, 0x0016);
765 if (err < 0)
766 return err;
767
768 err = phy_write(phydev, 0x1e, 0xa2da);
769 if (err < 0)
770 return err;
771
895ee682 772 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679
AF		 773 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
774 if (temp < 0)
775 return temp;
776
777 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
778
779 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
780 if (err < 0)
781 return err;
782
2f495c39 783 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
76884679
AF		 784 err = phy_write(phydev, 0x1d, 0x0012);
785 if (err < 0)
786 return err;
787
788 temp = phy_read(phydev, 0x1e);
789 if (temp < 0)
790 return temp;
791
792 temp &= 0xf03f;
793 temp |= 2 << 9; /* 36 ohm */
794 temp |= 2 << 6; /* 39 ohm */
795
796 err = phy_write(phydev, 0x1e, temp);
797 if (err < 0)
798 return err;
799
800 err = phy_write(phydev, 0x1d, 0x3);
801 if (err < 0)
802 return err;
803
804 err = phy_write(phydev, 0x1e, 0x8000);
805 if (err < 0)
806 return err;
807 }
808 }
809
b0224175
VND		 810 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
811 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
812 if (temp < 0)
813 return temp;
814
99d881f9 815 temp &= ~MII_M1145_HWCFG_MODE_MASK;
b0224175
VND		 816 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
817 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
818
819 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
820 if (err < 0)
821 return err;
822 }
823
cf41a51d
DD		 824 err = marvell_of_reg_init(phydev);
825 if (err < 0)
826 return err;
827
76884679
AF		 828 return 0;
829}
00db8189 830
be937f1f
AS		 831/* marvell_read_status
832 *
833 * Generic status code does not detect Fiber correctly!
f0c88f9c 834 * Description:
be937f1f
AS		 835 * Check the link, then figure out the current state
836 * by comparing what we advertise with what the link partner
837 * advertises. Start by checking the gigabit possibilities,
838 * then move on to 10/100.
839 */
840static int marvell_read_status(struct phy_device *phydev)
841{
842 int adv;
843 int err;
844 int lpa;
357cd64c 845 int lpagb;
be937f1f
AS		 846 int status = 0;
847
848 /* Update the link, but return if there
849 * was an error */
850 err = genphy_update_link(phydev);
851 if (err)
852 return err;
853
854 if (AUTONEG_ENABLE == phydev->autoneg) {
855 status = phy_read(phydev, MII_M1011_PHY_STATUS);
856 if (status < 0)
857 return status;
858
859 lpa = phy_read(phydev, MII_LPA);
860 if (lpa < 0)
861 return lpa;
862
357cd64c
RK		 863 lpagb = phy_read(phydev, MII_STAT1000);
864 if (lpagb < 0)
865 return lpagb;
866
be937f1f
AS		 867 adv = phy_read(phydev, MII_ADVERTISE);
868 if (adv < 0)
869 return adv;
870
357cd64c
RK		 871 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) |
872 mii_lpa_to_ethtool_lpa_t(lpa);
873
be937f1f
AS		 874 lpa &= adv;
875
876 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
877 phydev->duplex = DUPLEX_FULL;
878 else
879 phydev->duplex = DUPLEX_HALF;
880
881 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
882 phydev->pause = phydev->asym_pause = 0;
883
884 switch (status) {
885 case MII_M1011_PHY_STATUS_1000:
886 phydev->speed = SPEED_1000;
887 break;
888
889 case MII_M1011_PHY_STATUS_100:
890 phydev->speed = SPEED_100;
891 break;
892
893 default:
894 phydev->speed = SPEED_10;
895 break;
896 }
897
898 if (phydev->duplex == DUPLEX_FULL) {
899 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
900 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
901 }
902 } else {
903 int bmcr = phy_read(phydev, MII_BMCR);
904
905 if (bmcr < 0)
906 return bmcr;
907
908 if (bmcr & BMCR_FULLDPLX)
909 phydev->duplex = DUPLEX_FULL;
910 else
911 phydev->duplex = DUPLEX_HALF;
912
913 if (bmcr & BMCR_SPEED1000)
914 phydev->speed = SPEED_1000;
915 else if (bmcr & BMCR_SPEED100)
916 phydev->speed = SPEED_100;
917 else
918 phydev->speed = SPEED_10;
919
920 phydev->pause = phydev->asym_pause = 0;
357cd64c 921 phydev->lp_advertising = 0;
be937f1f
AS		 922 }
923
924 return 0;
925}
926
6b358aed
SH		 927static int marvell_aneg_done(struct phy_device *phydev)
928{
929 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
930 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
931}
932
dcd07be3
AG		 933static int m88e1121_did_interrupt(struct phy_device *phydev)
934{
935 int imask;
936
937 imask = phy_read(phydev, MII_M1011_IEVENT);
938
939 if (imask & MII_M1011_IMASK_INIT)
940 return 1;
941
942 return 0;
943}
944
3871c387
MS		 945static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
946{
947 wol->supported = WAKE_MAGIC;
948 wol->wolopts = 0;
949
950 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
951 MII_88E1318S_PHY_WOL_PAGE) < 0)
952 return;
953
954 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
955 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
956 wol->wolopts |= WAKE_MAGIC;
957
958 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
959 return;
960}
961
962static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
963{
964 int err, oldpage, temp;
965
966 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
967
968 if (wol->wolopts & WAKE_MAGIC) {
969 /* Explicitly switch to page 0x00, just to be sure */
970 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
971 if (err < 0)
972 return err;
973
974 /* Enable the WOL interrupt */
975 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
976 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
977 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
978 if (err < 0)
979 return err;
980
981 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
982 MII_88E1318S_PHY_LED_PAGE);
983 if (err < 0)
984 return err;
985
986 /* Setup LED[2] as interrupt pin (active low) */
987 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
988 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
989 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
990 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
991 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
992 if (err < 0)
993 return err;
994
995 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
996 MII_88E1318S_PHY_WOL_PAGE);
997 if (err < 0)
998 return err;
999
1000 /* Store the device address for the magic packet */
1001 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1002 ((phydev->attached_dev->dev_addr[5] << 8) |
1003 phydev->attached_dev->dev_addr[4]));
1004 if (err < 0)
1005 return err;
1006 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1007 ((phydev->attached_dev->dev_addr[3] << 8) |
1008 phydev->attached_dev->dev_addr[2]));
1009 if (err < 0)
1010 return err;
1011 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1012 ((phydev->attached_dev->dev_addr[1] << 8) |
1013 phydev->attached_dev->dev_addr[0]));
1014 if (err < 0)
1015 return err;
1016
1017 /* Clear WOL status and enable magic packet matching */
1018 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1019 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1020 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1021 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1022 if (err < 0)
1023 return err;
1024 } else {
1025 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1026 MII_88E1318S_PHY_WOL_PAGE);
1027 if (err < 0)
1028 return err;
1029
1030 /* Clear WOL status and disable magic packet matching */
1031 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1032 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1033 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1034 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1035 if (err < 0)
1036 return err;
1037 }
1038
1039 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1040 if (err < 0)
1041 return err;
1042
1043 return 0;
1044}
1045
d2fa47d9
AL		 1046static int marvell_get_sset_count(struct phy_device *phydev)
1047{
1048 return ARRAY_SIZE(marvell_hw_stats);
1049}
1050
1051static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1052{
1053 int i;
1054
1055 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
1056 memcpy(data + i * ETH_GSTRING_LEN,
1057 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1058 }
1059}
1060
1061#ifndef UINT64_MAX
1062#define UINT64_MAX (u64)(~((u64)0))
1063#endif
1064static u64 marvell_get_stat(struct phy_device *phydev, int i)
1065{
1066 struct marvell_hw_stat stat = marvell_hw_stats[i];
1067 struct marvell_priv *priv = phydev->priv;
1068 int err, oldpage;
1069 u64 val;
1070
1071 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1072 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1073 stat.page);
1074 if (err < 0)
1075 return UINT64_MAX;
1076
1077 val = phy_read(phydev, stat.reg);
1078 if (val < 0) {
1079 val = UINT64_MAX;
1080 } else {
1081 val = val & ((1 << stat.bits) - 1);
1082 priv->stats[i] += val;
1083 val = priv->stats[i];
1084 }
1085
1086 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1087
1088 return val;
1089}
1090
1091static void marvell_get_stats(struct phy_device *phydev,
1092 struct ethtool_stats *stats, u64 *data)
1093{
1094 int i;
1095
1096 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1097 data[i] = marvell_get_stat(phydev, i);
1098}
1099
1100static int marvell_probe(struct phy_device *phydev)
1101{
1102 struct marvell_priv *priv;
1103
e5a03bfd 1104 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
d2fa47d9
AL		 1105 if (!priv)
1106 return -ENOMEM;
1107
1108 phydev->priv = priv;
1109
1110 return 0;
1111}
1112
e5479239
OJ		 1113static struct phy_driver marvell_drivers[] = {
1114 {
2f495c39
BH		 1115 .phy_id = MARVELL_PHY_ID_88E1101,
1116 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1117 .name = "Marvell 88E1101",
1118 .features = PHY_GBIT_FEATURES,
d2fa47d9 1119 .probe = marvell_probe,
e5479239
OJ		 1120 .flags = PHY_HAS_INTERRUPT,
1121 .config_aneg = &marvell_config_aneg,
1122 .read_status = &genphy_read_status,
1123 .ack_interrupt = &marvell_ack_interrupt,
1124 .config_intr = &marvell_config_intr,
0898b448
SH		 1125 .resume = &genphy_resume,
1126 .suspend = &genphy_suspend,
d2fa47d9
AL		 1127 .get_sset_count = marvell_get_sset_count,
1128 .get_strings = marvell_get_strings,
1129 .get_stats = marvell_get_stats,
e5479239 1130 },
85cfb534 1131 {
2f495c39
BH		 1132 .phy_id = MARVELL_PHY_ID_88E1112,
1133 .phy_id_mask = MARVELL_PHY_ID_MASK,
85cfb534
OJ		 1134 .name = "Marvell 88E1112",
1135 .features = PHY_GBIT_FEATURES,
1136 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1137 .probe = marvell_probe,
85cfb534
OJ		 1138 .config_init = &m88e1111_config_init,
1139 .config_aneg = &marvell_config_aneg,
1140 .read_status = &genphy_read_status,
1141 .ack_interrupt = &marvell_ack_interrupt,
1142 .config_intr = &marvell_config_intr,
0898b448
SH		 1143 .resume = &genphy_resume,
1144 .suspend = &genphy_suspend,
d2fa47d9
AL		 1145 .get_sset_count = marvell_get_sset_count,
1146 .get_strings = marvell_get_strings,
1147 .get_stats = marvell_get_stats,
85cfb534 1148 },
e5479239 1149 {
2f495c39
BH		 1150 .phy_id = MARVELL_PHY_ID_88E1111,
1151 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1152 .name = "Marvell 88E1111",
1153 .features = PHY_GBIT_FEATURES,
1154 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1155 .probe = marvell_probe,
e5479239
OJ		 1156 .config_init = &m88e1111_config_init,
1157 .config_aneg = &marvell_config_aneg,
be937f1f 1158 .read_status = &marvell_read_status,
e5479239
OJ		 1159 .ack_interrupt = &marvell_ack_interrupt,
1160 .config_intr = &marvell_config_intr,
0898b448
SH		 1161 .resume = &genphy_resume,
1162 .suspend = &genphy_suspend,
d2fa47d9
AL		 1163 .get_sset_count = marvell_get_sset_count,
1164 .get_strings = marvell_get_strings,
1165 .get_stats = marvell_get_stats,
e5479239 1166 },
605f196e 1167 {
2f495c39
BH		 1168 .phy_id = MARVELL_PHY_ID_88E1118,
1169 .phy_id_mask = MARVELL_PHY_ID_MASK,
605f196e
RM		 1170 .name = "Marvell 88E1118",
1171 .features = PHY_GBIT_FEATURES,
1172 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1173 .probe = marvell_probe,
605f196e
RM		 1174 .config_init = &m88e1118_config_init,
1175 .config_aneg = &m88e1118_config_aneg,
1176 .read_status = &genphy_read_status,
1177 .ack_interrupt = &marvell_ack_interrupt,
1178 .config_intr = &marvell_config_intr,
0898b448
SH		 1179 .resume = &genphy_resume,
1180 .suspend = &genphy_suspend,
d2fa47d9
AL		 1181 .get_sset_count = marvell_get_sset_count,
1182 .get_strings = marvell_get_strings,
1183 .get_stats = marvell_get_stats,
605f196e 1184 },
140bc929 1185 {
2f495c39
BH		 1186 .phy_id = MARVELL_PHY_ID_88E1121R,
1187 .phy_id_mask = MARVELL_PHY_ID_MASK,
140bc929
SP		 1188 .name = "Marvell 88E1121R",
1189 .features = PHY_GBIT_FEATURES,
1190 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1191 .probe = marvell_probe,
140bc929
SP		 1192 .config_aneg = &m88e1121_config_aneg,
1193 .read_status = &marvell_read_status,
1194 .ack_interrupt = &marvell_ack_interrupt,
1195 .config_intr = &marvell_config_intr,
dcd07be3 1196 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1197 .resume = &genphy_resume,
1198 .suspend = &genphy_suspend,
d2fa47d9
AL		 1199 .get_sset_count = marvell_get_sset_count,
1200 .get_strings = marvell_get_strings,
1201 .get_stats = marvell_get_stats,
140bc929 1202 },
3ff1c259 1203 {
337ac9d5 1204 .phy_id = MARVELL_PHY_ID_88E1318S,
6ba74014 1205 .phy_id_mask = MARVELL_PHY_ID_MASK,
337ac9d5 1206 .name = "Marvell 88E1318S",
3ff1c259
CC		 1207 .features = PHY_GBIT_FEATURES,
1208 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1209 .probe = marvell_probe,
337ac9d5 1210 .config_aneg = &m88e1318_config_aneg,
3ff1c259
CC		 1211 .read_status = &marvell_read_status,
1212 .ack_interrupt = &marvell_ack_interrupt,
1213 .config_intr = &marvell_config_intr,
1214 .did_interrupt = &m88e1121_did_interrupt,
3871c387
MS		 1215 .get_wol = &m88e1318_get_wol,
1216 .set_wol = &m88e1318_set_wol,
0898b448
SH		 1217 .resume = &genphy_resume,
1218 .suspend = &genphy_suspend,
d2fa47d9
AL		 1219 .get_sset_count = marvell_get_sset_count,
1220 .get_strings = marvell_get_strings,
1221 .get_stats = marvell_get_stats,
3ff1c259 1222 },
e5479239 1223 {
2f495c39
BH		 1224 .phy_id = MARVELL_PHY_ID_88E1145,
1225 .phy_id_mask = MARVELL_PHY_ID_MASK,
e5479239
OJ		 1226 .name = "Marvell 88E1145",
1227 .features = PHY_GBIT_FEATURES,
1228 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1229 .probe = marvell_probe,
e5479239
OJ		 1230 .config_init = &m88e1145_config_init,
1231 .config_aneg = &marvell_config_aneg,
1232 .read_status = &genphy_read_status,
1233 .ack_interrupt = &marvell_ack_interrupt,
1234 .config_intr = &marvell_config_intr,
0898b448
SH		 1235 .resume = &genphy_resume,
1236 .suspend = &genphy_suspend,
d2fa47d9
AL		 1237 .get_sset_count = marvell_get_sset_count,
1238 .get_strings = marvell_get_strings,
1239 .get_stats = marvell_get_stats,
ac8c635a 1240 },
90600732
DD		 1241 {
1242 .phy_id = MARVELL_PHY_ID_88E1149R,
1243 .phy_id_mask = MARVELL_PHY_ID_MASK,
1244 .name = "Marvell 88E1149R",
1245 .features = PHY_GBIT_FEATURES,
1246 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1247 .probe = marvell_probe,
90600732
DD		 1248 .config_init = &m88e1149_config_init,
1249 .config_aneg = &m88e1118_config_aneg,
1250 .read_status = &genphy_read_status,
1251 .ack_interrupt = &marvell_ack_interrupt,
1252 .config_intr = &marvell_config_intr,
0898b448
SH		 1253 .resume = &genphy_resume,
1254 .suspend = &genphy_suspend,
d2fa47d9
AL		 1255 .get_sset_count = marvell_get_sset_count,
1256 .get_strings = marvell_get_strings,
1257 .get_stats = marvell_get_stats,
90600732 1258 },
ac8c635a 1259 {
2f495c39
BH		 1260 .phy_id = MARVELL_PHY_ID_88E1240,
1261 .phy_id_mask = MARVELL_PHY_ID_MASK,
ac8c635a
OJ		 1262 .name = "Marvell 88E1240",
1263 .features = PHY_GBIT_FEATURES,
1264 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1265 .probe = marvell_probe,
ac8c635a
OJ		 1266 .config_init = &m88e1111_config_init,
1267 .config_aneg = &marvell_config_aneg,
1268 .read_status = &genphy_read_status,
1269 .ack_interrupt = &marvell_ack_interrupt,
1270 .config_intr = &marvell_config_intr,
0898b448
SH		 1271 .resume = &genphy_resume,
1272 .suspend = &genphy_suspend,
d2fa47d9
AL		 1273 .get_sset_count = marvell_get_sset_count,
1274 .get_strings = marvell_get_strings,
1275 .get_stats = marvell_get_stats,
ac8c635a 1276 },
3da09a51
MS		 1277 {
1278 .phy_id = MARVELL_PHY_ID_88E1116R,
1279 .phy_id_mask = MARVELL_PHY_ID_MASK,
1280 .name = "Marvell 88E1116R",
1281 .features = PHY_GBIT_FEATURES,
1282 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1283 .probe = marvell_probe,
3da09a51
MS		 1284 .config_init = &m88e1116r_config_init,
1285 .config_aneg = &genphy_config_aneg,
1286 .read_status = &genphy_read_status,
1287 .ack_interrupt = &marvell_ack_interrupt,
1288 .config_intr = &marvell_config_intr,
0898b448
SH		 1289 .resume = &genphy_resume,
1290 .suspend = &genphy_suspend,
d2fa47d9
AL		 1291 .get_sset_count = marvell_get_sset_count,
1292 .get_strings = marvell_get_strings,
1293 .get_stats = marvell_get_stats,
3da09a51 1294 },
10e24caa
MS		 1295 {
1296 .phy_id = MARVELL_PHY_ID_88E1510,
1297 .phy_id_mask = MARVELL_PHY_ID_MASK,
1298 .name = "Marvell 88E1510",
1299 .features = PHY_GBIT_FEATURES,
1300 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1301 .probe = marvell_probe,
930b37ee 1302 .config_init = &m88e1510_config_init,
10e24caa
MS		 1303 .config_aneg = &m88e1510_config_aneg,
1304 .read_status = &marvell_read_status,
1305 .ack_interrupt = &marvell_ack_interrupt,
1306 .config_intr = &marvell_config_intr,
1307 .did_interrupt = &m88e1121_did_interrupt,
0898b448
SH		 1308 .resume = &genphy_resume,
1309 .suspend = &genphy_suspend,
d2fa47d9
AL		 1310 .get_sset_count = marvell_get_sset_count,
1311 .get_strings = marvell_get_strings,
1312 .get_stats = marvell_get_stats,
10e24caa 1313 },
819ec8e1
AL		 1314 {
1315 .phy_id = MARVELL_PHY_ID_88E1540,
1316 .phy_id_mask = MARVELL_PHY_ID_MASK,
1317 .name = "Marvell 88E1540",
1318 .features = PHY_GBIT_FEATURES,
1319 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1320 .probe = marvell_probe,
819ec8e1
AL		 1321 .config_aneg = &m88e1510_config_aneg,
1322 .read_status = &marvell_read_status,
1323 .ack_interrupt = &marvell_ack_interrupt,
1324 .config_intr = &marvell_config_intr,
1325 .did_interrupt = &m88e1121_did_interrupt,
1326 .resume = &genphy_resume,
1327 .suspend = &genphy_suspend,
d2fa47d9
AL		 1328 .get_sset_count = marvell_get_sset_count,
1329 .get_strings = marvell_get_strings,
1330 .get_stats = marvell_get_stats,
819ec8e1 1331 },
6b358aed
SH		 1332 {
1333 .phy_id = MARVELL_PHY_ID_88E3016,
1334 .phy_id_mask = MARVELL_PHY_ID_MASK,
1335 .name = "Marvell 88E3016",
1336 .features = PHY_BASIC_FEATURES,
1337 .flags = PHY_HAS_INTERRUPT,
d2fa47d9 1338 .probe = marvell_probe,
6b358aed
SH		 1339 .config_aneg = &genphy_config_aneg,
1340 .config_init = &m88e3016_config_init,
1341 .aneg_done = &marvell_aneg_done,
1342 .read_status = &marvell_read_status,
1343 .ack_interrupt = &marvell_ack_interrupt,
1344 .config_intr = &marvell_config_intr,
1345 .did_interrupt = &m88e1121_did_interrupt,
1346 .resume = &genphy_resume,
1347 .suspend = &genphy_suspend,
d2fa47d9
AL		 1348 .get_sset_count = marvell_get_sset_count,
1349 .get_strings = marvell_get_strings,
1350 .get_stats = marvell_get_stats,
6b358aed 1351 },
00db8189
AF		 1352};
1353
50fd7150 1354module_phy_driver(marvell_drivers);
4e4f10f6 1355
cf93c945 1356static struct mdio_device_id __maybe_unused marvell_tbl[] = {
f5e1cabf
MS		 1357 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1358 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1359 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1360 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1361 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1362 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1363 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1364 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1365 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3da09a51 1366 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
10e24caa 1367 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
819ec8e1 1368 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
6b358aed 1369 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
4e4f10f6
DW		 1370 { }
1371};
1372
1373MODULE_DEVICE_TABLE(mdio, marvell_tbl);
Linux kernel - Deliverables
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