[deliverable/linux.git] / drivers / net / phy / marvell.c

/*
 * drivers/net/phy/marvell.c
 *
 * Driver for Marvell PHYs
 *
 * Author: Andy Fleming
 *
 * Copyright (c) 2004 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/unistd.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/phy.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>

#define MII_M1011_IEVENT		0x13
#define MII_M1011_IEVENT_CLEAR		0x0000

#define MII_M1011_IMASK			0x12
#define MII_M1011_IMASK_INIT		0x6400
#define MII_M1011_IMASK_CLEAR		0x0000

#define MII_M1011_PHY_SCR		0x10
#define MII_M1011_PHY_SCR_AUTO_CROSS	0x0060

#define MII_M1145_PHY_EXT_CR		0x14
#define MII_M1145_RGMII_RX_DELAY	0x0080
#define MII_M1145_RGMII_TX_DELAY	0x0002

#define M1145_DEV_FLAGS_RESISTANCE	0x00000001

#define MII_M1111_PHY_LED_CONTROL	0x18
#define MII_M1111_PHY_LED_DIRECT	0x4100
#define MII_M1111_PHY_LED_COMBINE	0x411c
#define MII_M1111_PHY_EXT_CR		0x14
#define MII_M1111_RX_DELAY		0x80
#define MII_M1111_TX_DELAY		0x2
#define MII_M1111_PHY_EXT_SR		0x1b
#define MII_M1111_HWCFG_MODE_MASK	0xf
#define MII_M1111_HWCFG_MODE_RGMII	0xb
#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK	0x4

MODULE_DESCRIPTION("Marvell PHY driver");
MODULE_AUTHOR("Andy Fleming");
MODULE_LICENSE("GPL");

static int marvell_ack_interrupt(struct phy_device *phydev)
{
	int err;

	/* Clear the interrupts by reading the reg */
	err = phy_read(phydev, MII_M1011_IEVENT);

	if (err < 0)
		return err;

	return 0;
}

static int marvell_config_intr(struct phy_device *phydev)
{
	int err;

	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
		err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
	else
		err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);

	return err;
}

static int marvell_config_aneg(struct phy_device *phydev)
{
	int err;

	/* The Marvell PHY has an errata which requires
	 * that certain registers get written in order
	 * to restart autonegotiation */
	err = phy_write(phydev, MII_BMCR, BMCR_RESET);

	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1d, 0x1f);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0x200c);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1d, 0x5);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0x100);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_M1011_PHY_SCR,
			MII_M1011_PHY_SCR_AUTO_CROSS);
	if (err < 0)
		return err;

	err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
			MII_M1111_PHY_LED_DIRECT);
	if (err < 0)
		return err;

	err = genphy_config_aneg(phydev);

	return err;
}

static int m88e1111_config_init(struct phy_device *phydev)
{
	int err;

	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
		int temp;

		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
			temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
			if (temp < 0)
				return temp;

			temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);

			err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
			if (err < 0)
				return err;
		}

		temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
		if (temp < 0)
			return temp;

		temp &= ~(MII_M1111_HWCFG_MODE_MASK);
		temp |= MII_M1111_HWCFG_MODE_RGMII;

		err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
		if (err < 0)
			return err;
	}

	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
		int temp;

		temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
		if (temp < 0)
			return temp;

		temp &= ~(MII_M1111_HWCFG_MODE_MASK);
		temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;

		err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
		if (err < 0)
			return err;
	}

	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	if (err < 0)
		return err;

	return 0;
}

static int m88e1145_config_init(struct phy_device *phydev)
{
	int err;

	/* Take care of errata E0 & E1 */
	err = phy_write(phydev, 0x1d, 0x001b);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0x418f);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1d, 0x0016);
	if (err < 0)
		return err;

	err = phy_write(phydev, 0x1e, 0xa2da);
	if (err < 0)
		return err;

	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
		int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
		if (temp < 0)
			return temp;

		temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);

		err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
		if (err < 0)
			return err;

		if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
			err = phy_write(phydev, 0x1d, 0x0012);
			if (err < 0)
				return err;

			temp = phy_read(phydev, 0x1e);
			if (temp < 0)
				return temp;

			temp &= 0xf03f;
			temp |= 2 << 9;	/* 36 ohm */
			temp |= 2 << 6;	/* 39 ohm */

			err = phy_write(phydev, 0x1e, temp);
			if (err < 0)
				return err;

			err = phy_write(phydev, 0x1d, 0x3);
			if (err < 0)
				return err;

			err = phy_write(phydev, 0x1e, 0x8000);
			if (err < 0)
				return err;
		}
	}

	return 0;
}

static struct phy_driver m88e1101_driver = {
	.phy_id = 0x01410c60,
	.phy_id_mask = 0xfffffff0,
	.name = "Marvell 88E1101",
	.features = PHY_GBIT_FEATURES,
	.flags = PHY_HAS_INTERRUPT,
	.config_aneg = &marvell_config_aneg,
	.read_status = &genphy_read_status,
	.ack_interrupt = &marvell_ack_interrupt,
	.config_intr = &marvell_config_intr,
	.driver = {.owner = THIS_MODULE,},
};

static struct phy_driver m88e1111_driver = {
	.phy_id = 0x01410cc0,
	.phy_id_mask = 0xfffffff0,
	.name = "Marvell 88E1111",
	.features = PHY_GBIT_FEATURES,
	.flags = PHY_HAS_INTERRUPT,
	.config_aneg = &marvell_config_aneg,
	.read_status = &genphy_read_status,
	.ack_interrupt = &marvell_ack_interrupt,
	.config_intr = &marvell_config_intr,
	.config_init = &m88e1111_config_init,
	.driver = {.owner = THIS_MODULE,},
};

static struct phy_driver m88e1145_driver = {
	.phy_id = 0x01410cd0,
	.phy_id_mask = 0xfffffff0,
	.name = "Marvell 88E1145",
	.features = PHY_GBIT_FEATURES,
	.flags = PHY_HAS_INTERRUPT,
	.config_init = &m88e1145_config_init,
	.config_aneg = &marvell_config_aneg,
	.read_status = &genphy_read_status,
	.ack_interrupt = &marvell_ack_interrupt,
	.config_intr = &marvell_config_intr,
	.driver = {.owner = THIS_MODULE,},
};

static int __init marvell_init(void)
{
	int ret;

	ret = phy_driver_register(&m88e1101_driver);
	if (ret)
		return ret;

	ret = phy_driver_register(&m88e1111_driver);
	if (ret)
		goto err1111;

	ret = phy_driver_register(&m88e1145_driver);
	if (ret)
		goto err1145;

	return 0;

err1145:
	phy_driver_unregister(&m88e1111_driver);
err1111:
	phy_driver_unregister(&m88e1101_driver);
	return ret;
}

static void __exit marvell_exit(void)
{
	phy_driver_unregister(&m88e1101_driver);
	phy_driver_unregister(&m88e1111_driver);
	phy_driver_unregister(&m88e1145_driver);
}

module_init(marvell_init);
module_exit(marvell_exit);
Commit	Line	Data
00db8189 AF	1	/*
	2	* drivers/net/phy/marvell.c
	3	*
	4	* Driver for Marvell PHYs
	5	*
	6	* Author: Andy Fleming
	7	*
	8	* Copyright (c) 2004 Freescale Semiconductor, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*
	15	*/
00db8189	16	#include <linux/kernel.h>
00db8189 AF	17	#include <linux/string.h>
	18	#include <linux/errno.h>
	19	#include <linux/unistd.h>
	20	#include <linux/slab.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/init.h>
	23	#include <linux/delay.h>
	24	#include <linux/netdevice.h>
	25	#include <linux/etherdevice.h>
	26	#include <linux/skbuff.h>
	27	#include <linux/spinlock.h>
	28	#include <linux/mm.h>
	29	#include <linux/module.h>
00db8189 AF	30	#include <linux/mii.h>
	31	#include <linux/ethtool.h>
	32	#include <linux/phy.h>
	33
	34	#include <asm/io.h>
	35	#include <asm/irq.h>
	36	#include <asm/uaccess.h>
	37
	38	#define MII_M1011_IEVENT 0x13
	39	#define MII_M1011_IEVENT_CLEAR 0x0000
	40
	41	#define MII_M1011_IMASK 0x12
	42	#define MII_M1011_IMASK_INIT 0x6400
	43	#define MII_M1011_IMASK_CLEAR 0x0000
	44
76884679 AF	45	#define MII_M1011_PHY_SCR 0x10
	46	#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
	47
	48	#define MII_M1145_PHY_EXT_CR 0x14
	49	#define MII_M1145_RGMII_RX_DELAY 0x0080
	50	#define MII_M1145_RGMII_TX_DELAY 0x0002
	51
	52	#define M1145_DEV_FLAGS_RESISTANCE 0x00000001
	53
	54	#define MII_M1111_PHY_LED_CONTROL 0x18
	55	#define MII_M1111_PHY_LED_DIRECT 0x4100
	56	#define MII_M1111_PHY_LED_COMBINE 0x411c
895ee682 KP	57	#define MII_M1111_PHY_EXT_CR 0x14
	58	#define MII_M1111_RX_DELAY 0x80
	59	#define MII_M1111_TX_DELAY 0x2
	60	#define MII_M1111_PHY_EXT_SR 0x1b
	61	#define MII_M1111_HWCFG_MODE_MASK 0xf
	62	#define MII_M1111_HWCFG_MODE_RGMII 0xb
4117b5be	63	#define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
76884679	64
00db8189 AF	65	MODULE_DESCRIPTION("Marvell PHY driver");
	66	MODULE_AUTHOR("Andy Fleming");
	67	MODULE_LICENSE("GPL");
	68
	69	static int marvell_ack_interrupt(struct phy_device *phydev)
	70	{
	71	int err;
	72
	73	/* Clear the interrupts by reading the reg */
	74	err = phy_read(phydev, MII_M1011_IEVENT);
	75
	76	if (err < 0)
	77	return err;
	78
	79	return 0;
	80	}
	81
	82	static int marvell_config_intr(struct phy_device *phydev)
	83	{
	84	int err;
	85
76884679	86	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
00db8189 AF	87	err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
	88	else
	89	err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
	90
	91	return err;
	92	}
	93
	94	static int marvell_config_aneg(struct phy_device *phydev)
	95	{
	96	int err;
	97
	98	/* The Marvell PHY has an errata which requires
	99	* that certain registers get written in order
	100	* to restart autonegotiation */
	101	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	102
	103	if (err < 0)
	104	return err;
	105
	106	err = phy_write(phydev, 0x1d, 0x1f);
	107	if (err < 0)
	108	return err;
	109
	110	err = phy_write(phydev, 0x1e, 0x200c);
	111	if (err < 0)
	112	return err;
	113
	114	err = phy_write(phydev, 0x1d, 0x5);
	115	if (err < 0)
	116	return err;
	117
	118	err = phy_write(phydev, 0x1e, 0);
	119	if (err < 0)
	120	return err;
	121
	122	err = phy_write(phydev, 0x1e, 0x100);
	123	if (err < 0)
	124	return err;
	125
76884679 AF	126	err = phy_write(phydev, MII_M1011_PHY_SCR,
	127	MII_M1011_PHY_SCR_AUTO_CROSS);
	128	if (err < 0)
	129	return err;
	130
	131	err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
	132	MII_M1111_PHY_LED_DIRECT);
	133	if (err < 0)
	134	return err;
00db8189 AF	135
	136	err = genphy_config_aneg(phydev);
	137
	138	return err;
	139	}
	140
895ee682 KP	141	static int m88e1111_config_init(struct phy_device *phydev)
	142	{
	143	int err;
	144
	145	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) \|\|
	146	(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
	147	int temp;
	148
	149	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
	150	temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
	151	if (temp < 0)
	152	return temp;
	153
	154	temp \|= (MII_M1111_RX_DELAY \| MII_M1111_TX_DELAY);
	155
	156	err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
	157	if (err < 0)
	158	return err;
	159	}
	160
	161	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
	162	if (temp < 0)
	163	return temp;
	164
	165	temp &= ~(MII_M1111_HWCFG_MODE_MASK);
	166	temp \|= MII_M1111_HWCFG_MODE_RGMII;
	167
	168	err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
	169	if (err < 0)
	170	return err;
	171	}
	172
4117b5be KJ	173	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
	174	int temp;
	175
	176	temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
	177	if (temp < 0)
	178	return temp;
	179
	180	temp &= ~(MII_M1111_HWCFG_MODE_MASK);
	181	temp \|= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
	182
	183	err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
	184	if (err < 0)
	185	return err;
	186	}
	187
895ee682 KP	188	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
	189	if (err < 0)
	190	return err;
	191
	192	return 0;
	193	}
	194
76884679 AF	195	static int m88e1145_config_init(struct phy_device *phydev)
	196	{
	197	int err;
	198
	199	/* Take care of errata E0 & E1 */
	200	err = phy_write(phydev, 0x1d, 0x001b);
	201	if (err < 0)
	202	return err;
	203
	204	err = phy_write(phydev, 0x1e, 0x418f);
	205	if (err < 0)
	206	return err;
	207
	208	err = phy_write(phydev, 0x1d, 0x0016);
	209	if (err < 0)
	210	return err;
	211
	212	err = phy_write(phydev, 0x1e, 0xa2da);
	213	if (err < 0)
	214	return err;
	215
895ee682	216	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
76884679 AF	217	int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
	218	if (temp < 0)
	219	return temp;
	220
	221	temp \|= (MII_M1145_RGMII_RX_DELAY \| MII_M1145_RGMII_TX_DELAY);
	222
	223	err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
	224	if (err < 0)
	225	return err;
	226
	227	if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
	228	err = phy_write(phydev, 0x1d, 0x0012);
	229	if (err < 0)
	230	return err;
	231
	232	temp = phy_read(phydev, 0x1e);
	233	if (temp < 0)
	234	return temp;
	235
	236	temp &= 0xf03f;
	237	temp \|= 2 << 9; /* 36 ohm */
	238	temp \|= 2 << 6; /* 39 ohm */
	239
	240	err = phy_write(phydev, 0x1e, temp);
	241	if (err < 0)
	242	return err;
	243
	244	err = phy_write(phydev, 0x1d, 0x3);
	245	if (err < 0)
	246	return err;
	247
	248	err = phy_write(phydev, 0x1e, 0x8000);
	249	if (err < 0)
	250	return err;
	251	}
	252	}
	253
	254	return 0;
	255	}
00db8189 AF	256
00db8189 AF	257	static struct phy_driver m88e1101_driver = {
76884679 AF	258	.phy_id = 0x01410c60,
	259	.phy_id_mask = 0xfffffff0,
	260	.name = "Marvell 88E1101",
	261	.features = PHY_GBIT_FEATURES,
	262	.flags = PHY_HAS_INTERRUPT,
	263	.config_aneg = &marvell_config_aneg,
	264	.read_status = &genphy_read_status,
	265	.ack_interrupt = &marvell_ack_interrupt,
	266	.config_intr = &marvell_config_intr,
	267	.driver = {.owner = THIS_MODULE,},
	268	};
	269
895ee682	270	static struct phy_driver m88e1111_driver = {
76884679 AF	271	.phy_id = 0x01410cc0,
	272	.phy_id_mask = 0xfffffff0,
	273	.name = "Marvell 88E1111",
	274	.features = PHY_GBIT_FEATURES,
	275	.flags = PHY_HAS_INTERRUPT,
	276	.config_aneg = &marvell_config_aneg,
	277	.read_status = &genphy_read_status,
	278	.ack_interrupt = &marvell_ack_interrupt,
	279	.config_intr = &marvell_config_intr,
895ee682	280	.config_init = &m88e1111_config_init,
76884679 AF	281	.driver = {.owner = THIS_MODULE,},
	282	};
	283
	284	static struct phy_driver m88e1145_driver = {
	285	.phy_id = 0x01410cd0,
	286	.phy_id_mask = 0xfffffff0,
	287	.name = "Marvell 88E1145",
	288	.features = PHY_GBIT_FEATURES,
	289	.flags = PHY_HAS_INTERRUPT,
	290	.config_init = &m88e1145_config_init,
	291	.config_aneg = &marvell_config_aneg,
	292	.read_status = &genphy_read_status,
	293	.ack_interrupt = &marvell_ack_interrupt,
	294	.config_intr = &marvell_config_intr,
	295	.driver = {.owner = THIS_MODULE,},
00db8189 AF	296	};
	297
	298	static int __init marvell_init(void)
	299	{
76884679 AF	300	int ret;
	301
	302	ret = phy_driver_register(&m88e1101_driver);
	303	if (ret)
	304	return ret;
	305
895ee682	306	ret = phy_driver_register(&m88e1111_driver);
76884679	307	if (ret)
895ee682	308	goto err1111;
76884679 AF	309
	310	ret = phy_driver_register(&m88e1145_driver);
	311	if (ret)
	312	goto err1145;
	313
	314	return 0;
	315
895ee682 KP	316	err1145:
	317	phy_driver_unregister(&m88e1111_driver);
	318	err1111:
76884679 AF	319	phy_driver_unregister(&m88e1101_driver);
76884679 AF	320	return ret;
00db8189 AF	321	}
	322
	323	static void __exit marvell_exit(void)
	324	{
	325	phy_driver_unregister(&m88e1101_driver);
895ee682	326	phy_driver_unregister(&m88e1111_driver);
76884679	327	phy_driver_unregister(&m88e1145_driver);
00db8189 AF	328	}
	329
	330	module_init(marvell_init);
	331	module_exit(marvell_exit);