Commit | Line | Data |
---|---|---|
00db8189 AF |
1 | /* |
2 | * drivers/net/phy/marvell.c | |
3 | * | |
4 | * Driver for Marvell PHYs | |
5 | * | |
6 | * Author: Andy Fleming | |
7 | * | |
8 | * Copyright (c) 2004 Freescale Semiconductor, Inc. | |
9 | * | |
3871c387 MS |
10 | * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de> |
11 | * | |
00db8189 AF |
12 | * This program is free software; you can redistribute it and/or modify it |
13 | * under the terms of the GNU General Public License as published by the | |
14 | * Free Software Foundation; either version 2 of the License, or (at your | |
15 | * option) any later version. | |
16 | * | |
17 | */ | |
00db8189 | 18 | #include <linux/kernel.h> |
00db8189 AF |
19 | #include <linux/string.h> |
20 | #include <linux/errno.h> | |
21 | #include <linux/unistd.h> | |
00db8189 AF |
22 | #include <linux/interrupt.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/skbuff.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/module.h> | |
00db8189 AF |
31 | #include <linux/mii.h> |
32 | #include <linux/ethtool.h> | |
33 | #include <linux/phy.h> | |
2f495c39 | 34 | #include <linux/marvell_phy.h> |
cf41a51d | 35 | #include <linux/of.h> |
00db8189 | 36 | |
eea3b201 | 37 | #include <linux/io.h> |
00db8189 | 38 | #include <asm/irq.h> |
eea3b201 | 39 | #include <linux/uaccess.h> |
00db8189 | 40 | |
27d916d6 DD |
41 | #define MII_MARVELL_PHY_PAGE 22 |
42 | ||
00db8189 AF |
43 | #define MII_M1011_IEVENT 0x13 |
44 | #define MII_M1011_IEVENT_CLEAR 0x0000 | |
45 | ||
46 | #define MII_M1011_IMASK 0x12 | |
47 | #define MII_M1011_IMASK_INIT 0x6400 | |
48 | #define MII_M1011_IMASK_CLEAR 0x0000 | |
49 | ||
76884679 | 50 | #define MII_M1011_PHY_SCR 0x10 |
239aa55b DT |
51 | #define MII_M1011_PHY_SCR_MDI 0x0000 |
52 | #define MII_M1011_PHY_SCR_MDI_X 0x0020 | |
76884679 AF |
53 | #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060 |
54 | ||
07151bc9 | 55 | #define MII_M1145_PHY_EXT_ADDR_PAGE 0x16 |
b0224175 | 56 | #define MII_M1145_PHY_EXT_SR 0x1b |
76884679 AF |
57 | #define MII_M1145_PHY_EXT_CR 0x14 |
58 | #define MII_M1145_RGMII_RX_DELAY 0x0080 | |
59 | #define MII_M1145_RGMII_TX_DELAY 0x0002 | |
b0224175 VND |
60 | #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4 |
61 | #define MII_M1145_HWCFG_MODE_MASK 0xf | |
62 | #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000 | |
76884679 | 63 | |
99d881f9 VB |
64 | #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4 |
65 | #define MII_M1145_HWCFG_MODE_MASK 0xf | |
66 | #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000 | |
67 | ||
76884679 AF |
68 | #define MII_M1111_PHY_LED_CONTROL 0x18 |
69 | #define MII_M1111_PHY_LED_DIRECT 0x4100 | |
70 | #define MII_M1111_PHY_LED_COMBINE 0x411c | |
895ee682 KP |
71 | #define MII_M1111_PHY_EXT_CR 0x14 |
72 | #define MII_M1111_RX_DELAY 0x80 | |
73 | #define MII_M1111_TX_DELAY 0x2 | |
74 | #define MII_M1111_PHY_EXT_SR 0x1b | |
be937f1f AS |
75 | |
76 | #define MII_M1111_HWCFG_MODE_MASK 0xf | |
77 | #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb | |
78 | #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3 | |
4117b5be | 79 | #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4 |
5f8cbc13 | 80 | #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9 |
be937f1f AS |
81 | #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000 |
82 | #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000 | |
83 | ||
84 | #define MII_M1111_COPPER 0 | |
85 | #define MII_M1111_FIBER 1 | |
86 | ||
c477d044 CC |
87 | #define MII_88E1121_PHY_MSCR_PAGE 2 |
88 | #define MII_88E1121_PHY_MSCR_REG 21 | |
89 | #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5) | |
90 | #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4) | |
91 | #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4)) | |
92 | ||
337ac9d5 CC |
93 | #define MII_88E1318S_PHY_MSCR1_REG 16 |
94 | #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6) | |
3ff1c259 | 95 | |
3871c387 MS |
96 | /* Copper Specific Interrupt Enable Register */ |
97 | #define MII_88E1318S_PHY_CSIER 0x12 | |
98 | /* WOL Event Interrupt Enable */ | |
99 | #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7) | |
100 | ||
101 | /* LED Timer Control Register */ | |
102 | #define MII_88E1318S_PHY_LED_PAGE 0x03 | |
103 | #define MII_88E1318S_PHY_LED_TCR 0x12 | |
104 | #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15) | |
105 | #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7) | |
106 | #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11) | |
107 | ||
108 | /* Magic Packet MAC address registers */ | |
109 | #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17 | |
110 | #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18 | |
111 | #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19 | |
112 | ||
113 | #define MII_88E1318S_PHY_WOL_PAGE 0x11 | |
114 | #define MII_88E1318S_PHY_WOL_CTRL 0x10 | |
115 | #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12) | |
116 | #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14) | |
117 | ||
140bc929 SP |
118 | #define MII_88E1121_PHY_LED_CTRL 16 |
119 | #define MII_88E1121_PHY_LED_PAGE 3 | |
120 | #define MII_88E1121_PHY_LED_DEF 0x0030 | |
140bc929 | 121 | |
be937f1f AS |
122 | #define MII_M1011_PHY_STATUS 0x11 |
123 | #define MII_M1011_PHY_STATUS_1000 0x8000 | |
124 | #define MII_M1011_PHY_STATUS_100 0x4000 | |
125 | #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000 | |
126 | #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000 | |
127 | #define MII_M1011_PHY_STATUS_RESOLVED 0x0800 | |
128 | #define MII_M1011_PHY_STATUS_LINK 0x0400 | |
129 | ||
3da09a51 MS |
130 | #define MII_M1116R_CONTROL_REG_MAC 21 |
131 | ||
6b358aed SH |
132 | #define MII_88E3016_PHY_SPEC_CTRL 0x10 |
133 | #define MII_88E3016_DISABLE_SCRAMBLER 0x0200 | |
134 | #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030 | |
76884679 | 135 | |
00db8189 AF |
136 | MODULE_DESCRIPTION("Marvell PHY driver"); |
137 | MODULE_AUTHOR("Andy Fleming"); | |
138 | MODULE_LICENSE("GPL"); | |
139 | ||
d2fa47d9 AL |
140 | struct marvell_hw_stat { |
141 | const char *string; | |
142 | u8 page; | |
143 | u8 reg; | |
144 | u8 bits; | |
145 | }; | |
146 | ||
147 | static struct marvell_hw_stat marvell_hw_stats[] = { | |
148 | { "phy_receive_errors", 0, 21, 16}, | |
149 | { "phy_idle_errors", 0, 10, 8 }, | |
150 | }; | |
151 | ||
152 | struct marvell_priv { | |
153 | u64 stats[ARRAY_SIZE(marvell_hw_stats)]; | |
154 | }; | |
155 | ||
00db8189 AF |
156 | static int marvell_ack_interrupt(struct phy_device *phydev) |
157 | { | |
158 | int err; | |
159 | ||
160 | /* Clear the interrupts by reading the reg */ | |
161 | err = phy_read(phydev, MII_M1011_IEVENT); | |
162 | ||
163 | if (err < 0) | |
164 | return err; | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
169 | static int marvell_config_intr(struct phy_device *phydev) | |
170 | { | |
171 | int err; | |
172 | ||
76884679 | 173 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
00db8189 AF |
174 | err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT); |
175 | else | |
176 | err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); | |
177 | ||
178 | return err; | |
179 | } | |
180 | ||
239aa55b DT |
181 | static int marvell_set_polarity(struct phy_device *phydev, int polarity) |
182 | { | |
183 | int reg; | |
184 | int err; | |
185 | int val; | |
186 | ||
187 | /* get the current settings */ | |
188 | reg = phy_read(phydev, MII_M1011_PHY_SCR); | |
189 | if (reg < 0) | |
190 | return reg; | |
191 | ||
192 | val = reg; | |
193 | val &= ~MII_M1011_PHY_SCR_AUTO_CROSS; | |
194 | switch (polarity) { | |
195 | case ETH_TP_MDI: | |
196 | val |= MII_M1011_PHY_SCR_MDI; | |
197 | break; | |
198 | case ETH_TP_MDI_X: | |
199 | val |= MII_M1011_PHY_SCR_MDI_X; | |
200 | break; | |
201 | case ETH_TP_MDI_AUTO: | |
202 | case ETH_TP_MDI_INVALID: | |
203 | default: | |
204 | val |= MII_M1011_PHY_SCR_AUTO_CROSS; | |
205 | break; | |
206 | } | |
207 | ||
208 | if (val != reg) { | |
209 | /* Set the new polarity value in the register */ | |
210 | err = phy_write(phydev, MII_M1011_PHY_SCR, val); | |
211 | if (err) | |
212 | return err; | |
213 | } | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
00db8189 AF |
218 | static int marvell_config_aneg(struct phy_device *phydev) |
219 | { | |
220 | int err; | |
221 | ||
222 | /* The Marvell PHY has an errata which requires | |
223 | * that certain registers get written in order | |
224 | * to restart autonegotiation */ | |
225 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); | |
226 | ||
227 | if (err < 0) | |
228 | return err; | |
229 | ||
230 | err = phy_write(phydev, 0x1d, 0x1f); | |
231 | if (err < 0) | |
232 | return err; | |
233 | ||
234 | err = phy_write(phydev, 0x1e, 0x200c); | |
235 | if (err < 0) | |
236 | return err; | |
237 | ||
238 | err = phy_write(phydev, 0x1d, 0x5); | |
239 | if (err < 0) | |
240 | return err; | |
241 | ||
242 | err = phy_write(phydev, 0x1e, 0); | |
243 | if (err < 0) | |
244 | return err; | |
245 | ||
246 | err = phy_write(phydev, 0x1e, 0x100); | |
247 | if (err < 0) | |
248 | return err; | |
249 | ||
239aa55b | 250 | err = marvell_set_polarity(phydev, phydev->mdix); |
76884679 AF |
251 | if (err < 0) |
252 | return err; | |
253 | ||
254 | err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, | |
255 | MII_M1111_PHY_LED_DIRECT); | |
256 | if (err < 0) | |
257 | return err; | |
00db8189 AF |
258 | |
259 | err = genphy_config_aneg(phydev); | |
8ff44985 AV |
260 | if (err < 0) |
261 | return err; | |
00db8189 | 262 | |
8ff44985 AV |
263 | if (phydev->autoneg != AUTONEG_ENABLE) { |
264 | int bmcr; | |
265 | ||
266 | /* | |
267 | * A write to speed/duplex bits (that is performed by | |
268 | * genphy_config_aneg() call above) must be followed by | |
269 | * a software reset. Otherwise, the write has no effect. | |
270 | */ | |
271 | bmcr = phy_read(phydev, MII_BMCR); | |
272 | if (bmcr < 0) | |
273 | return bmcr; | |
274 | ||
275 | err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET); | |
276 | if (err < 0) | |
277 | return err; | |
278 | } | |
279 | ||
280 | return 0; | |
00db8189 AF |
281 | } |
282 | ||
cf41a51d DD |
283 | #ifdef CONFIG_OF_MDIO |
284 | /* | |
285 | * Set and/or override some configuration registers based on the | |
286 | * marvell,reg-init property stored in the of_node for the phydev. | |
287 | * | |
288 | * marvell,reg-init = <reg-page reg mask value>,...; | |
289 | * | |
290 | * There may be one or more sets of <reg-page reg mask value>: | |
291 | * | |
292 | * reg-page: which register bank to use. | |
293 | * reg: the register. | |
294 | * mask: if non-zero, ANDed with existing register value. | |
295 | * value: ORed with the masked value and written to the regiser. | |
296 | * | |
297 | */ | |
298 | static int marvell_of_reg_init(struct phy_device *phydev) | |
299 | { | |
300 | const __be32 *paddr; | |
301 | int len, i, saved_page, current_page, page_changed, ret; | |
302 | ||
303 | if (!phydev->dev.of_node) | |
304 | return 0; | |
305 | ||
306 | paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len); | |
307 | if (!paddr || len < (4 * sizeof(*paddr))) | |
308 | return 0; | |
309 | ||
310 | saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE); | |
311 | if (saved_page < 0) | |
312 | return saved_page; | |
313 | page_changed = 0; | |
314 | current_page = saved_page; | |
315 | ||
316 | ret = 0; | |
317 | len /= sizeof(*paddr); | |
318 | for (i = 0; i < len - 3; i += 4) { | |
319 | u16 reg_page = be32_to_cpup(paddr + i); | |
320 | u16 reg = be32_to_cpup(paddr + i + 1); | |
321 | u16 mask = be32_to_cpup(paddr + i + 2); | |
322 | u16 val_bits = be32_to_cpup(paddr + i + 3); | |
323 | int val; | |
324 | ||
325 | if (reg_page != current_page) { | |
326 | current_page = reg_page; | |
327 | page_changed = 1; | |
328 | ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page); | |
329 | if (ret < 0) | |
330 | goto err; | |
331 | } | |
332 | ||
333 | val = 0; | |
334 | if (mask) { | |
335 | val = phy_read(phydev, reg); | |
336 | if (val < 0) { | |
337 | ret = val; | |
338 | goto err; | |
339 | } | |
340 | val &= mask; | |
341 | } | |
342 | val |= val_bits; | |
343 | ||
344 | ret = phy_write(phydev, reg, val); | |
345 | if (ret < 0) | |
346 | goto err; | |
347 | ||
348 | } | |
349 | err: | |
350 | if (page_changed) { | |
351 | i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page); | |
352 | if (ret == 0) | |
353 | ret = i; | |
354 | } | |
355 | return ret; | |
356 | } | |
357 | #else | |
358 | static int marvell_of_reg_init(struct phy_device *phydev) | |
359 | { | |
360 | return 0; | |
361 | } | |
362 | #endif /* CONFIG_OF_MDIO */ | |
363 | ||
140bc929 SP |
364 | static int m88e1121_config_aneg(struct phy_device *phydev) |
365 | { | |
c477d044 CC |
366 | int err, oldpage, mscr; |
367 | ||
27d916d6 | 368 | oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); |
c477d044 | 369 | |
27d916d6 | 370 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, |
c477d044 CC |
371 | MII_88E1121_PHY_MSCR_PAGE); |
372 | if (err < 0) | |
373 | return err; | |
be8c6480 | 374 | |
32a64161 | 375 | if (phy_interface_is_rgmii(phydev)) { |
be8c6480 AP |
376 | |
377 | mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) & | |
378 | MII_88E1121_PHY_MSCR_DELAY_MASK; | |
379 | ||
380 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) | |
381 | mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY | | |
382 | MII_88E1121_PHY_MSCR_TX_DELAY); | |
383 | else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) | |
384 | mscr |= MII_88E1121_PHY_MSCR_RX_DELAY; | |
385 | else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) | |
386 | mscr |= MII_88E1121_PHY_MSCR_TX_DELAY; | |
387 | ||
388 | err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr); | |
389 | if (err < 0) | |
390 | return err; | |
391 | } | |
c477d044 | 392 | |
27d916d6 | 393 | phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); |
140bc929 SP |
394 | |
395 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); | |
396 | if (err < 0) | |
397 | return err; | |
398 | ||
399 | err = phy_write(phydev, MII_M1011_PHY_SCR, | |
400 | MII_M1011_PHY_SCR_AUTO_CROSS); | |
401 | if (err < 0) | |
402 | return err; | |
403 | ||
27d916d6 | 404 | oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); |
140bc929 | 405 | |
27d916d6 | 406 | phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE); |
140bc929 | 407 | phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF); |
27d916d6 | 408 | phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); |
140bc929 SP |
409 | |
410 | err = genphy_config_aneg(phydev); | |
411 | ||
412 | return err; | |
413 | } | |
414 | ||
337ac9d5 | 415 | static int m88e1318_config_aneg(struct phy_device *phydev) |
3ff1c259 CC |
416 | { |
417 | int err, oldpage, mscr; | |
418 | ||
27d916d6 | 419 | oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); |
3ff1c259 | 420 | |
27d916d6 | 421 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, |
3ff1c259 CC |
422 | MII_88E1121_PHY_MSCR_PAGE); |
423 | if (err < 0) | |
424 | return err; | |
425 | ||
337ac9d5 CC |
426 | mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG); |
427 | mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD; | |
3ff1c259 | 428 | |
337ac9d5 | 429 | err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr); |
3ff1c259 CC |
430 | if (err < 0) |
431 | return err; | |
432 | ||
27d916d6 | 433 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); |
3ff1c259 CC |
434 | if (err < 0) |
435 | return err; | |
436 | ||
437 | return m88e1121_config_aneg(phydev); | |
438 | } | |
439 | ||
10e24caa MS |
440 | static int m88e1510_config_aneg(struct phy_device *phydev) |
441 | { | |
442 | int err; | |
443 | ||
444 | err = m88e1318_config_aneg(phydev); | |
445 | if (err < 0) | |
446 | return err; | |
447 | ||
448 | return marvell_of_reg_init(phydev); | |
449 | } | |
450 | ||
3da09a51 MS |
451 | static int m88e1116r_config_init(struct phy_device *phydev) |
452 | { | |
453 | int temp; | |
454 | int err; | |
455 | ||
456 | temp = phy_read(phydev, MII_BMCR); | |
457 | temp |= BMCR_RESET; | |
458 | err = phy_write(phydev, MII_BMCR, temp); | |
459 | if (err < 0) | |
460 | return err; | |
461 | ||
462 | mdelay(500); | |
463 | ||
464 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); | |
465 | if (err < 0) | |
466 | return err; | |
467 | ||
468 | temp = phy_read(phydev, MII_M1011_PHY_SCR); | |
469 | temp |= (7 << 12); /* max number of gigabit attempts */ | |
470 | temp |= (1 << 11); /* enable downshift */ | |
471 | temp |= MII_M1011_PHY_SCR_AUTO_CROSS; | |
472 | err = phy_write(phydev, MII_M1011_PHY_SCR, temp); | |
473 | if (err < 0) | |
474 | return err; | |
475 | ||
476 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2); | |
477 | if (err < 0) | |
478 | return err; | |
479 | temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC); | |
480 | temp |= (1 << 5); | |
481 | temp |= (1 << 4); | |
482 | err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp); | |
483 | if (err < 0) | |
484 | return err; | |
485 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); | |
486 | if (err < 0) | |
487 | return err; | |
488 | ||
489 | temp = phy_read(phydev, MII_BMCR); | |
490 | temp |= BMCR_RESET; | |
491 | err = phy_write(phydev, MII_BMCR, temp); | |
492 | if (err < 0) | |
493 | return err; | |
494 | ||
495 | mdelay(500); | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
6b358aed SH |
500 | static int m88e3016_config_init(struct phy_device *phydev) |
501 | { | |
502 | int reg; | |
503 | ||
504 | /* Enable Scrambler and Auto-Crossover */ | |
505 | reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL); | |
506 | if (reg < 0) | |
507 | return reg; | |
508 | ||
509 | reg &= ~MII_88E3016_DISABLE_SCRAMBLER; | |
510 | reg |= MII_88E3016_AUTO_MDIX_CROSSOVER; | |
511 | ||
512 | reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg); | |
513 | if (reg < 0) | |
514 | return reg; | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
895ee682 KP |
519 | static int m88e1111_config_init(struct phy_device *phydev) |
520 | { | |
521 | int err; | |
be937f1f | 522 | int temp; |
be937f1f | 523 | |
32a64161 | 524 | if (phy_interface_is_rgmii(phydev)) { |
895ee682 | 525 | |
9daf5a76 KP |
526 | temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); |
527 | if (temp < 0) | |
528 | return temp; | |
895ee682 | 529 | |
9daf5a76 | 530 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { |
895ee682 | 531 | temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); |
9daf5a76 KP |
532 | } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { |
533 | temp &= ~MII_M1111_TX_DELAY; | |
534 | temp |= MII_M1111_RX_DELAY; | |
535 | } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { | |
536 | temp &= ~MII_M1111_RX_DELAY; | |
537 | temp |= MII_M1111_TX_DELAY; | |
895ee682 KP |
538 | } |
539 | ||
9daf5a76 KP |
540 | err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); |
541 | if (err < 0) | |
542 | return err; | |
543 | ||
895ee682 KP |
544 | temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); |
545 | if (temp < 0) | |
546 | return temp; | |
547 | ||
548 | temp &= ~(MII_M1111_HWCFG_MODE_MASK); | |
be937f1f | 549 | |
7239016d | 550 | if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES) |
be937f1f AS |
551 | temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII; |
552 | else | |
553 | temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII; | |
895ee682 KP |
554 | |
555 | err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); | |
556 | if (err < 0) | |
557 | return err; | |
558 | } | |
559 | ||
4117b5be | 560 | if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { |
4117b5be KJ |
561 | temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); |
562 | if (temp < 0) | |
563 | return temp; | |
564 | ||
565 | temp &= ~(MII_M1111_HWCFG_MODE_MASK); | |
566 | temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK; | |
32d0c1e1 | 567 | temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO; |
4117b5be KJ |
568 | |
569 | err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); | |
570 | if (err < 0) | |
571 | return err; | |
07151bc9 MB |
572 | |
573 | /* make sure copper is selected */ | |
574 | err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE); | |
575 | if (err < 0) | |
576 | return err; | |
577 | ||
578 | err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, | |
579 | err & (~0xff)); | |
580 | if (err < 0) | |
581 | return err; | |
4117b5be KJ |
582 | } |
583 | ||
5f8cbc13 LYB |
584 | if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { |
585 | temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); | |
586 | if (temp < 0) | |
587 | return temp; | |
588 | temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); | |
589 | err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); | |
590 | if (err < 0) | |
591 | return err; | |
592 | ||
593 | temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); | |
594 | if (temp < 0) | |
595 | return temp; | |
596 | temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); | |
597 | temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO; | |
598 | err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); | |
599 | if (err < 0) | |
600 | return err; | |
601 | ||
602 | /* soft reset */ | |
603 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); | |
604 | if (err < 0) | |
605 | return err; | |
606 | do | |
607 | temp = phy_read(phydev, MII_BMCR); | |
608 | while (temp & BMCR_RESET); | |
609 | ||
610 | temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); | |
611 | if (temp < 0) | |
612 | return temp; | |
613 | temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); | |
614 | temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO; | |
615 | err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); | |
616 | if (err < 0) | |
617 | return err; | |
618 | } | |
619 | ||
cf41a51d DD |
620 | err = marvell_of_reg_init(phydev); |
621 | if (err < 0) | |
622 | return err; | |
5f8cbc13 | 623 | |
cc90cb3b | 624 | return phy_write(phydev, MII_BMCR, BMCR_RESET); |
895ee682 KP |
625 | } |
626 | ||
605f196e RM |
627 | static int m88e1118_config_aneg(struct phy_device *phydev) |
628 | { | |
629 | int err; | |
630 | ||
631 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); | |
632 | if (err < 0) | |
633 | return err; | |
634 | ||
635 | err = phy_write(phydev, MII_M1011_PHY_SCR, | |
636 | MII_M1011_PHY_SCR_AUTO_CROSS); | |
637 | if (err < 0) | |
638 | return err; | |
639 | ||
640 | err = genphy_config_aneg(phydev); | |
641 | return 0; | |
642 | } | |
643 | ||
644 | static int m88e1118_config_init(struct phy_device *phydev) | |
645 | { | |
646 | int err; | |
647 | ||
648 | /* Change address */ | |
27d916d6 | 649 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); |
605f196e RM |
650 | if (err < 0) |
651 | return err; | |
652 | ||
653 | /* Enable 1000 Mbit */ | |
654 | err = phy_write(phydev, 0x15, 0x1070); | |
655 | if (err < 0) | |
656 | return err; | |
657 | ||
658 | /* Change address */ | |
27d916d6 | 659 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003); |
605f196e RM |
660 | if (err < 0) |
661 | return err; | |
662 | ||
663 | /* Adjust LED Control */ | |
2f495c39 BH |
664 | if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS) |
665 | err = phy_write(phydev, 0x10, 0x1100); | |
666 | else | |
667 | err = phy_write(phydev, 0x10, 0x021e); | |
605f196e RM |
668 | if (err < 0) |
669 | return err; | |
670 | ||
cf41a51d DD |
671 | err = marvell_of_reg_init(phydev); |
672 | if (err < 0) | |
673 | return err; | |
674 | ||
605f196e | 675 | /* Reset address */ |
27d916d6 | 676 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); |
605f196e RM |
677 | if (err < 0) |
678 | return err; | |
679 | ||
cc90cb3b | 680 | return phy_write(phydev, MII_BMCR, BMCR_RESET); |
605f196e RM |
681 | } |
682 | ||
90600732 DD |
683 | static int m88e1149_config_init(struct phy_device *phydev) |
684 | { | |
685 | int err; | |
686 | ||
687 | /* Change address */ | |
688 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); | |
689 | if (err < 0) | |
690 | return err; | |
691 | ||
692 | /* Enable 1000 Mbit */ | |
693 | err = phy_write(phydev, 0x15, 0x1048); | |
694 | if (err < 0) | |
695 | return err; | |
696 | ||
cf41a51d DD |
697 | err = marvell_of_reg_init(phydev); |
698 | if (err < 0) | |
699 | return err; | |
700 | ||
90600732 DD |
701 | /* Reset address */ |
702 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); | |
703 | if (err < 0) | |
704 | return err; | |
705 | ||
cc90cb3b | 706 | return phy_write(phydev, MII_BMCR, BMCR_RESET); |
90600732 DD |
707 | } |
708 | ||
76884679 AF |
709 | static int m88e1145_config_init(struct phy_device *phydev) |
710 | { | |
711 | int err; | |
b0224175 | 712 | int temp; |
76884679 AF |
713 | |
714 | /* Take care of errata E0 & E1 */ | |
715 | err = phy_write(phydev, 0x1d, 0x001b); | |
716 | if (err < 0) | |
717 | return err; | |
718 | ||
719 | err = phy_write(phydev, 0x1e, 0x418f); | |
720 | if (err < 0) | |
721 | return err; | |
722 | ||
723 | err = phy_write(phydev, 0x1d, 0x0016); | |
724 | if (err < 0) | |
725 | return err; | |
726 | ||
727 | err = phy_write(phydev, 0x1e, 0xa2da); | |
728 | if (err < 0) | |
729 | return err; | |
730 | ||
895ee682 | 731 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { |
76884679 AF |
732 | int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR); |
733 | if (temp < 0) | |
734 | return temp; | |
735 | ||
736 | temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY); | |
737 | ||
738 | err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp); | |
739 | if (err < 0) | |
740 | return err; | |
741 | ||
2f495c39 | 742 | if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) { |
76884679 AF |
743 | err = phy_write(phydev, 0x1d, 0x0012); |
744 | if (err < 0) | |
745 | return err; | |
746 | ||
747 | temp = phy_read(phydev, 0x1e); | |
748 | if (temp < 0) | |
749 | return temp; | |
750 | ||
751 | temp &= 0xf03f; | |
752 | temp |= 2 << 9; /* 36 ohm */ | |
753 | temp |= 2 << 6; /* 39 ohm */ | |
754 | ||
755 | err = phy_write(phydev, 0x1e, temp); | |
756 | if (err < 0) | |
757 | return err; | |
758 | ||
759 | err = phy_write(phydev, 0x1d, 0x3); | |
760 | if (err < 0) | |
761 | return err; | |
762 | ||
763 | err = phy_write(phydev, 0x1e, 0x8000); | |
764 | if (err < 0) | |
765 | return err; | |
766 | } | |
767 | } | |
768 | ||
b0224175 VND |
769 | if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { |
770 | temp = phy_read(phydev, MII_M1145_PHY_EXT_SR); | |
771 | if (temp < 0) | |
772 | return temp; | |
773 | ||
99d881f9 | 774 | temp &= ~MII_M1145_HWCFG_MODE_MASK; |
b0224175 VND |
775 | temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK; |
776 | temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO; | |
777 | ||
778 | err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp); | |
779 | if (err < 0) | |
780 | return err; | |
781 | } | |
782 | ||
cf41a51d DD |
783 | err = marvell_of_reg_init(phydev); |
784 | if (err < 0) | |
785 | return err; | |
786 | ||
76884679 AF |
787 | return 0; |
788 | } | |
00db8189 | 789 | |
be937f1f AS |
790 | /* marvell_read_status |
791 | * | |
792 | * Generic status code does not detect Fiber correctly! | |
f0c88f9c | 793 | * Description: |
be937f1f AS |
794 | * Check the link, then figure out the current state |
795 | * by comparing what we advertise with what the link partner | |
796 | * advertises. Start by checking the gigabit possibilities, | |
797 | * then move on to 10/100. | |
798 | */ | |
799 | static int marvell_read_status(struct phy_device *phydev) | |
800 | { | |
801 | int adv; | |
802 | int err; | |
803 | int lpa; | |
357cd64c | 804 | int lpagb; |
be937f1f AS |
805 | int status = 0; |
806 | ||
807 | /* Update the link, but return if there | |
808 | * was an error */ | |
809 | err = genphy_update_link(phydev); | |
810 | if (err) | |
811 | return err; | |
812 | ||
813 | if (AUTONEG_ENABLE == phydev->autoneg) { | |
814 | status = phy_read(phydev, MII_M1011_PHY_STATUS); | |
815 | if (status < 0) | |
816 | return status; | |
817 | ||
818 | lpa = phy_read(phydev, MII_LPA); | |
819 | if (lpa < 0) | |
820 | return lpa; | |
821 | ||
357cd64c RK |
822 | lpagb = phy_read(phydev, MII_STAT1000); |
823 | if (lpagb < 0) | |
824 | return lpagb; | |
825 | ||
be937f1f AS |
826 | adv = phy_read(phydev, MII_ADVERTISE); |
827 | if (adv < 0) | |
828 | return adv; | |
829 | ||
357cd64c RK |
830 | phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) | |
831 | mii_lpa_to_ethtool_lpa_t(lpa); | |
832 | ||
be937f1f AS |
833 | lpa &= adv; |
834 | ||
835 | if (status & MII_M1011_PHY_STATUS_FULLDUPLEX) | |
836 | phydev->duplex = DUPLEX_FULL; | |
837 | else | |
838 | phydev->duplex = DUPLEX_HALF; | |
839 | ||
840 | status = status & MII_M1011_PHY_STATUS_SPD_MASK; | |
841 | phydev->pause = phydev->asym_pause = 0; | |
842 | ||
843 | switch (status) { | |
844 | case MII_M1011_PHY_STATUS_1000: | |
845 | phydev->speed = SPEED_1000; | |
846 | break; | |
847 | ||
848 | case MII_M1011_PHY_STATUS_100: | |
849 | phydev->speed = SPEED_100; | |
850 | break; | |
851 | ||
852 | default: | |
853 | phydev->speed = SPEED_10; | |
854 | break; | |
855 | } | |
856 | ||
857 | if (phydev->duplex == DUPLEX_FULL) { | |
858 | phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; | |
859 | phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; | |
860 | } | |
861 | } else { | |
862 | int bmcr = phy_read(phydev, MII_BMCR); | |
863 | ||
864 | if (bmcr < 0) | |
865 | return bmcr; | |
866 | ||
867 | if (bmcr & BMCR_FULLDPLX) | |
868 | phydev->duplex = DUPLEX_FULL; | |
869 | else | |
870 | phydev->duplex = DUPLEX_HALF; | |
871 | ||
872 | if (bmcr & BMCR_SPEED1000) | |
873 | phydev->speed = SPEED_1000; | |
874 | else if (bmcr & BMCR_SPEED100) | |
875 | phydev->speed = SPEED_100; | |
876 | else | |
877 | phydev->speed = SPEED_10; | |
878 | ||
879 | phydev->pause = phydev->asym_pause = 0; | |
357cd64c | 880 | phydev->lp_advertising = 0; |
be937f1f AS |
881 | } |
882 | ||
883 | return 0; | |
884 | } | |
885 | ||
6b358aed SH |
886 | static int marvell_aneg_done(struct phy_device *phydev) |
887 | { | |
888 | int retval = phy_read(phydev, MII_M1011_PHY_STATUS); | |
889 | return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED); | |
890 | } | |
891 | ||
dcd07be3 AG |
892 | static int m88e1121_did_interrupt(struct phy_device *phydev) |
893 | { | |
894 | int imask; | |
895 | ||
896 | imask = phy_read(phydev, MII_M1011_IEVENT); | |
897 | ||
898 | if (imask & MII_M1011_IMASK_INIT) | |
899 | return 1; | |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
3871c387 MS |
904 | static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) |
905 | { | |
906 | wol->supported = WAKE_MAGIC; | |
907 | wol->wolopts = 0; | |
908 | ||
909 | if (phy_write(phydev, MII_MARVELL_PHY_PAGE, | |
910 | MII_88E1318S_PHY_WOL_PAGE) < 0) | |
911 | return; | |
912 | ||
913 | if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) & | |
914 | MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE) | |
915 | wol->wolopts |= WAKE_MAGIC; | |
916 | ||
917 | if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0) | |
918 | return; | |
919 | } | |
920 | ||
921 | static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) | |
922 | { | |
923 | int err, oldpage, temp; | |
924 | ||
925 | oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); | |
926 | ||
927 | if (wol->wolopts & WAKE_MAGIC) { | |
928 | /* Explicitly switch to page 0x00, just to be sure */ | |
929 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00); | |
930 | if (err < 0) | |
931 | return err; | |
932 | ||
933 | /* Enable the WOL interrupt */ | |
934 | temp = phy_read(phydev, MII_88E1318S_PHY_CSIER); | |
935 | temp |= MII_88E1318S_PHY_CSIER_WOL_EIE; | |
936 | err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp); | |
937 | if (err < 0) | |
938 | return err; | |
939 | ||
940 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, | |
941 | MII_88E1318S_PHY_LED_PAGE); | |
942 | if (err < 0) | |
943 | return err; | |
944 | ||
945 | /* Setup LED[2] as interrupt pin (active low) */ | |
946 | temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR); | |
947 | temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT; | |
948 | temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE; | |
949 | temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW; | |
950 | err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp); | |
951 | if (err < 0) | |
952 | return err; | |
953 | ||
954 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, | |
955 | MII_88E1318S_PHY_WOL_PAGE); | |
956 | if (err < 0) | |
957 | return err; | |
958 | ||
959 | /* Store the device address for the magic packet */ | |
960 | err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2, | |
961 | ((phydev->attached_dev->dev_addr[5] << 8) | | |
962 | phydev->attached_dev->dev_addr[4])); | |
963 | if (err < 0) | |
964 | return err; | |
965 | err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1, | |
966 | ((phydev->attached_dev->dev_addr[3] << 8) | | |
967 | phydev->attached_dev->dev_addr[2])); | |
968 | if (err < 0) | |
969 | return err; | |
970 | err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0, | |
971 | ((phydev->attached_dev->dev_addr[1] << 8) | | |
972 | phydev->attached_dev->dev_addr[0])); | |
973 | if (err < 0) | |
974 | return err; | |
975 | ||
976 | /* Clear WOL status and enable magic packet matching */ | |
977 | temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); | |
978 | temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; | |
979 | temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; | |
980 | err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); | |
981 | if (err < 0) | |
982 | return err; | |
983 | } else { | |
984 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, | |
985 | MII_88E1318S_PHY_WOL_PAGE); | |
986 | if (err < 0) | |
987 | return err; | |
988 | ||
989 | /* Clear WOL status and disable magic packet matching */ | |
990 | temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); | |
991 | temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; | |
992 | temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; | |
993 | err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); | |
994 | if (err < 0) | |
995 | return err; | |
996 | } | |
997 | ||
998 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); | |
999 | if (err < 0) | |
1000 | return err; | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
d2fa47d9 AL |
1005 | static int marvell_get_sset_count(struct phy_device *phydev) |
1006 | { | |
1007 | return ARRAY_SIZE(marvell_hw_stats); | |
1008 | } | |
1009 | ||
1010 | static void marvell_get_strings(struct phy_device *phydev, u8 *data) | |
1011 | { | |
1012 | int i; | |
1013 | ||
1014 | for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) { | |
1015 | memcpy(data + i * ETH_GSTRING_LEN, | |
1016 | marvell_hw_stats[i].string, ETH_GSTRING_LEN); | |
1017 | } | |
1018 | } | |
1019 | ||
1020 | #ifndef UINT64_MAX | |
1021 | #define UINT64_MAX (u64)(~((u64)0)) | |
1022 | #endif | |
1023 | static u64 marvell_get_stat(struct phy_device *phydev, int i) | |
1024 | { | |
1025 | struct marvell_hw_stat stat = marvell_hw_stats[i]; | |
1026 | struct marvell_priv *priv = phydev->priv; | |
1027 | int err, oldpage; | |
1028 | u64 val; | |
1029 | ||
1030 | oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); | |
1031 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, | |
1032 | stat.page); | |
1033 | if (err < 0) | |
1034 | return UINT64_MAX; | |
1035 | ||
1036 | val = phy_read(phydev, stat.reg); | |
1037 | if (val < 0) { | |
1038 | val = UINT64_MAX; | |
1039 | } else { | |
1040 | val = val & ((1 << stat.bits) - 1); | |
1041 | priv->stats[i] += val; | |
1042 | val = priv->stats[i]; | |
1043 | } | |
1044 | ||
1045 | phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); | |
1046 | ||
1047 | return val; | |
1048 | } | |
1049 | ||
1050 | static void marvell_get_stats(struct phy_device *phydev, | |
1051 | struct ethtool_stats *stats, u64 *data) | |
1052 | { | |
1053 | int i; | |
1054 | ||
1055 | for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) | |
1056 | data[i] = marvell_get_stat(phydev, i); | |
1057 | } | |
1058 | ||
1059 | static int marvell_probe(struct phy_device *phydev) | |
1060 | { | |
1061 | struct marvell_priv *priv; | |
1062 | ||
1063 | priv = devm_kzalloc(&phydev->dev, sizeof(*priv), GFP_KERNEL); | |
1064 | if (!priv) | |
1065 | return -ENOMEM; | |
1066 | ||
1067 | phydev->priv = priv; | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
e5479239 OJ |
1072 | static struct phy_driver marvell_drivers[] = { |
1073 | { | |
2f495c39 BH |
1074 | .phy_id = MARVELL_PHY_ID_88E1101, |
1075 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
e5479239 OJ |
1076 | .name = "Marvell 88E1101", |
1077 | .features = PHY_GBIT_FEATURES, | |
d2fa47d9 | 1078 | .probe = marvell_probe, |
e5479239 OJ |
1079 | .flags = PHY_HAS_INTERRUPT, |
1080 | .config_aneg = &marvell_config_aneg, | |
1081 | .read_status = &genphy_read_status, | |
1082 | .ack_interrupt = &marvell_ack_interrupt, | |
1083 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
1084 | .resume = &genphy_resume, |
1085 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1086 | .get_sset_count = marvell_get_sset_count, |
1087 | .get_strings = marvell_get_strings, | |
1088 | .get_stats = marvell_get_stats, | |
ac8c635a | 1089 | .driver = { .owner = THIS_MODULE }, |
e5479239 | 1090 | }, |
85cfb534 | 1091 | { |
2f495c39 BH |
1092 | .phy_id = MARVELL_PHY_ID_88E1112, |
1093 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
85cfb534 OJ |
1094 | .name = "Marvell 88E1112", |
1095 | .features = PHY_GBIT_FEATURES, | |
1096 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1097 | .probe = marvell_probe, |
85cfb534 OJ |
1098 | .config_init = &m88e1111_config_init, |
1099 | .config_aneg = &marvell_config_aneg, | |
1100 | .read_status = &genphy_read_status, | |
1101 | .ack_interrupt = &marvell_ack_interrupt, | |
1102 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
1103 | .resume = &genphy_resume, |
1104 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1105 | .get_sset_count = marvell_get_sset_count, |
1106 | .get_strings = marvell_get_strings, | |
1107 | .get_stats = marvell_get_stats, | |
ac8c635a | 1108 | .driver = { .owner = THIS_MODULE }, |
85cfb534 | 1109 | }, |
e5479239 | 1110 | { |
2f495c39 BH |
1111 | .phy_id = MARVELL_PHY_ID_88E1111, |
1112 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
e5479239 OJ |
1113 | .name = "Marvell 88E1111", |
1114 | .features = PHY_GBIT_FEATURES, | |
1115 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1116 | .probe = marvell_probe, |
e5479239 OJ |
1117 | .config_init = &m88e1111_config_init, |
1118 | .config_aneg = &marvell_config_aneg, | |
be937f1f | 1119 | .read_status = &marvell_read_status, |
e5479239 OJ |
1120 | .ack_interrupt = &marvell_ack_interrupt, |
1121 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
1122 | .resume = &genphy_resume, |
1123 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1124 | .get_sset_count = marvell_get_sset_count, |
1125 | .get_strings = marvell_get_strings, | |
1126 | .get_stats = marvell_get_stats, | |
ac8c635a | 1127 | .driver = { .owner = THIS_MODULE }, |
e5479239 | 1128 | }, |
605f196e | 1129 | { |
2f495c39 BH |
1130 | .phy_id = MARVELL_PHY_ID_88E1118, |
1131 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
605f196e RM |
1132 | .name = "Marvell 88E1118", |
1133 | .features = PHY_GBIT_FEATURES, | |
1134 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1135 | .probe = marvell_probe, |
605f196e RM |
1136 | .config_init = &m88e1118_config_init, |
1137 | .config_aneg = &m88e1118_config_aneg, | |
1138 | .read_status = &genphy_read_status, | |
1139 | .ack_interrupt = &marvell_ack_interrupt, | |
1140 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
1141 | .resume = &genphy_resume, |
1142 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1143 | .get_sset_count = marvell_get_sset_count, |
1144 | .get_strings = marvell_get_strings, | |
1145 | .get_stats = marvell_get_stats, | |
605f196e RM |
1146 | .driver = {.owner = THIS_MODULE,}, |
1147 | }, | |
140bc929 | 1148 | { |
2f495c39 BH |
1149 | .phy_id = MARVELL_PHY_ID_88E1121R, |
1150 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
140bc929 SP |
1151 | .name = "Marvell 88E1121R", |
1152 | .features = PHY_GBIT_FEATURES, | |
1153 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1154 | .probe = marvell_probe, |
140bc929 SP |
1155 | .config_aneg = &m88e1121_config_aneg, |
1156 | .read_status = &marvell_read_status, | |
1157 | .ack_interrupt = &marvell_ack_interrupt, | |
1158 | .config_intr = &marvell_config_intr, | |
dcd07be3 | 1159 | .did_interrupt = &m88e1121_did_interrupt, |
0898b448 SH |
1160 | .resume = &genphy_resume, |
1161 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1162 | .get_sset_count = marvell_get_sset_count, |
1163 | .get_strings = marvell_get_strings, | |
1164 | .get_stats = marvell_get_stats, | |
140bc929 SP |
1165 | .driver = { .owner = THIS_MODULE }, |
1166 | }, | |
3ff1c259 | 1167 | { |
337ac9d5 | 1168 | .phy_id = MARVELL_PHY_ID_88E1318S, |
6ba74014 | 1169 | .phy_id_mask = MARVELL_PHY_ID_MASK, |
337ac9d5 | 1170 | .name = "Marvell 88E1318S", |
3ff1c259 CC |
1171 | .features = PHY_GBIT_FEATURES, |
1172 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1173 | .probe = marvell_probe, |
337ac9d5 | 1174 | .config_aneg = &m88e1318_config_aneg, |
3ff1c259 CC |
1175 | .read_status = &marvell_read_status, |
1176 | .ack_interrupt = &marvell_ack_interrupt, | |
1177 | .config_intr = &marvell_config_intr, | |
1178 | .did_interrupt = &m88e1121_did_interrupt, | |
3871c387 MS |
1179 | .get_wol = &m88e1318_get_wol, |
1180 | .set_wol = &m88e1318_set_wol, | |
0898b448 SH |
1181 | .resume = &genphy_resume, |
1182 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1183 | .get_sset_count = marvell_get_sset_count, |
1184 | .get_strings = marvell_get_strings, | |
1185 | .get_stats = marvell_get_stats, | |
3ff1c259 CC |
1186 | .driver = { .owner = THIS_MODULE }, |
1187 | }, | |
e5479239 | 1188 | { |
2f495c39 BH |
1189 | .phy_id = MARVELL_PHY_ID_88E1145, |
1190 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
e5479239 OJ |
1191 | .name = "Marvell 88E1145", |
1192 | .features = PHY_GBIT_FEATURES, | |
1193 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1194 | .probe = marvell_probe, |
e5479239 OJ |
1195 | .config_init = &m88e1145_config_init, |
1196 | .config_aneg = &marvell_config_aneg, | |
1197 | .read_status = &genphy_read_status, | |
1198 | .ack_interrupt = &marvell_ack_interrupt, | |
1199 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
1200 | .resume = &genphy_resume, |
1201 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1202 | .get_sset_count = marvell_get_sset_count, |
1203 | .get_strings = marvell_get_strings, | |
1204 | .get_stats = marvell_get_stats, | |
ac8c635a OJ |
1205 | .driver = { .owner = THIS_MODULE }, |
1206 | }, | |
90600732 DD |
1207 | { |
1208 | .phy_id = MARVELL_PHY_ID_88E1149R, | |
1209 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
1210 | .name = "Marvell 88E1149R", | |
1211 | .features = PHY_GBIT_FEATURES, | |
1212 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1213 | .probe = marvell_probe, |
90600732 DD |
1214 | .config_init = &m88e1149_config_init, |
1215 | .config_aneg = &m88e1118_config_aneg, | |
1216 | .read_status = &genphy_read_status, | |
1217 | .ack_interrupt = &marvell_ack_interrupt, | |
1218 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
1219 | .resume = &genphy_resume, |
1220 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1221 | .get_sset_count = marvell_get_sset_count, |
1222 | .get_strings = marvell_get_strings, | |
1223 | .get_stats = marvell_get_stats, | |
90600732 DD |
1224 | .driver = { .owner = THIS_MODULE }, |
1225 | }, | |
ac8c635a | 1226 | { |
2f495c39 BH |
1227 | .phy_id = MARVELL_PHY_ID_88E1240, |
1228 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
ac8c635a OJ |
1229 | .name = "Marvell 88E1240", |
1230 | .features = PHY_GBIT_FEATURES, | |
1231 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1232 | .probe = marvell_probe, |
ac8c635a OJ |
1233 | .config_init = &m88e1111_config_init, |
1234 | .config_aneg = &marvell_config_aneg, | |
1235 | .read_status = &genphy_read_status, | |
1236 | .ack_interrupt = &marvell_ack_interrupt, | |
1237 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
1238 | .resume = &genphy_resume, |
1239 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1240 | .get_sset_count = marvell_get_sset_count, |
1241 | .get_strings = marvell_get_strings, | |
1242 | .get_stats = marvell_get_stats, | |
ac8c635a OJ |
1243 | .driver = { .owner = THIS_MODULE }, |
1244 | }, | |
3da09a51 MS |
1245 | { |
1246 | .phy_id = MARVELL_PHY_ID_88E1116R, | |
1247 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
1248 | .name = "Marvell 88E1116R", | |
1249 | .features = PHY_GBIT_FEATURES, | |
1250 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1251 | .probe = marvell_probe, |
3da09a51 MS |
1252 | .config_init = &m88e1116r_config_init, |
1253 | .config_aneg = &genphy_config_aneg, | |
1254 | .read_status = &genphy_read_status, | |
1255 | .ack_interrupt = &marvell_ack_interrupt, | |
1256 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
1257 | .resume = &genphy_resume, |
1258 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1259 | .get_sset_count = marvell_get_sset_count, |
1260 | .get_strings = marvell_get_strings, | |
1261 | .get_stats = marvell_get_stats, | |
3da09a51 MS |
1262 | .driver = { .owner = THIS_MODULE }, |
1263 | }, | |
10e24caa MS |
1264 | { |
1265 | .phy_id = MARVELL_PHY_ID_88E1510, | |
1266 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
1267 | .name = "Marvell 88E1510", | |
1268 | .features = PHY_GBIT_FEATURES, | |
1269 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1270 | .probe = marvell_probe, |
10e24caa MS |
1271 | .config_aneg = &m88e1510_config_aneg, |
1272 | .read_status = &marvell_read_status, | |
1273 | .ack_interrupt = &marvell_ack_interrupt, | |
1274 | .config_intr = &marvell_config_intr, | |
1275 | .did_interrupt = &m88e1121_did_interrupt, | |
0898b448 SH |
1276 | .resume = &genphy_resume, |
1277 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1278 | .get_sset_count = marvell_get_sset_count, |
1279 | .get_strings = marvell_get_strings, | |
1280 | .get_stats = marvell_get_stats, | |
10e24caa MS |
1281 | .driver = { .owner = THIS_MODULE }, |
1282 | }, | |
819ec8e1 AL |
1283 | { |
1284 | .phy_id = MARVELL_PHY_ID_88E1540, | |
1285 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
1286 | .name = "Marvell 88E1540", | |
1287 | .features = PHY_GBIT_FEATURES, | |
1288 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1289 | .probe = marvell_probe, |
819ec8e1 AL |
1290 | .config_aneg = &m88e1510_config_aneg, |
1291 | .read_status = &marvell_read_status, | |
1292 | .ack_interrupt = &marvell_ack_interrupt, | |
1293 | .config_intr = &marvell_config_intr, | |
1294 | .did_interrupt = &m88e1121_did_interrupt, | |
1295 | .resume = &genphy_resume, | |
1296 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1297 | .get_sset_count = marvell_get_sset_count, |
1298 | .get_strings = marvell_get_strings, | |
1299 | .get_stats = marvell_get_stats, | |
819ec8e1 AL |
1300 | .driver = { .owner = THIS_MODULE }, |
1301 | }, | |
6b358aed SH |
1302 | { |
1303 | .phy_id = MARVELL_PHY_ID_88E3016, | |
1304 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
1305 | .name = "Marvell 88E3016", | |
1306 | .features = PHY_BASIC_FEATURES, | |
1307 | .flags = PHY_HAS_INTERRUPT, | |
d2fa47d9 | 1308 | .probe = marvell_probe, |
6b358aed SH |
1309 | .config_aneg = &genphy_config_aneg, |
1310 | .config_init = &m88e3016_config_init, | |
1311 | .aneg_done = &marvell_aneg_done, | |
1312 | .read_status = &marvell_read_status, | |
1313 | .ack_interrupt = &marvell_ack_interrupt, | |
1314 | .config_intr = &marvell_config_intr, | |
1315 | .did_interrupt = &m88e1121_did_interrupt, | |
1316 | .resume = &genphy_resume, | |
1317 | .suspend = &genphy_suspend, | |
d2fa47d9 AL |
1318 | .get_sset_count = marvell_get_sset_count, |
1319 | .get_strings = marvell_get_strings, | |
1320 | .get_stats = marvell_get_stats, | |
6b358aed SH |
1321 | .driver = { .owner = THIS_MODULE }, |
1322 | }, | |
00db8189 AF |
1323 | }; |
1324 | ||
50fd7150 | 1325 | module_phy_driver(marvell_drivers); |
4e4f10f6 | 1326 | |
cf93c945 | 1327 | static struct mdio_device_id __maybe_unused marvell_tbl[] = { |
f5e1cabf MS |
1328 | { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK }, |
1329 | { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK }, | |
1330 | { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK }, | |
1331 | { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK }, | |
1332 | { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK }, | |
1333 | { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK }, | |
1334 | { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK }, | |
1335 | { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK }, | |
1336 | { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK }, | |
3da09a51 | 1337 | { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK }, |
10e24caa | 1338 | { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK }, |
819ec8e1 | 1339 | { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK }, |
6b358aed | 1340 | { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK }, |
4e4f10f6 DW |
1341 | { } |
1342 | }; | |
1343 | ||
1344 | MODULE_DEVICE_TABLE(mdio, marvell_tbl); |