Commit | Line | Data |
---|---|---|
af19b491 | 1 | /* |
40839129 SV |
2 | * QLogic qlcnic NIC Driver |
3 | * Copyright (c) 2009-2010 QLogic Corporation | |
af19b491 | 4 | * |
40839129 | 5 | * See LICENSE.qlcnic for copyright and licensing details. |
af19b491 AKS |
6 | */ |
7 | ||
8 | #include "qlcnic.h" | |
9 | ||
af19b491 AKS |
10 | static u32 |
11 | qlcnic_poll_rsp(struct qlcnic_adapter *adapter) | |
12 | { | |
13 | u32 rsp; | |
14 | int timeout = 0; | |
15 | ||
16 | do { | |
17 | /* give atleast 1ms for firmware to respond */ | |
18 | msleep(1); | |
19 | ||
20 | if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT) | |
21 | return QLCNIC_CDRP_RSP_TIMEOUT; | |
22 | ||
23 | rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET); | |
24 | } while (!QLCNIC_CDRP_IS_RSP(rsp)); | |
25 | ||
26 | return rsp; | |
27 | } | |
28 | ||
7eb9855d | 29 | u32 |
af19b491 AKS |
30 | qlcnic_issue_cmd(struct qlcnic_adapter *adapter, |
31 | u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd) | |
32 | { | |
33 | u32 rsp; | |
34 | u32 signature; | |
35 | u32 rcode = QLCNIC_RCODE_SUCCESS; | |
36 | struct pci_dev *pdev = adapter->pdev; | |
37 | ||
38 | signature = QLCNIC_CDRP_SIGNATURE_MAKE(pci_fn, version); | |
39 | ||
40 | /* Acquire semaphore before accessing CRB */ | |
41 | if (qlcnic_api_lock(adapter)) | |
42 | return QLCNIC_RCODE_TIMEOUT; | |
43 | ||
44 | QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature); | |
45 | QLCWR32(adapter, QLCNIC_ARG1_CRB_OFFSET, arg1); | |
46 | QLCWR32(adapter, QLCNIC_ARG2_CRB_OFFSET, arg2); | |
47 | QLCWR32(adapter, QLCNIC_ARG3_CRB_OFFSET, arg3); | |
48 | QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET, QLCNIC_CDRP_FORM_CMD(cmd)); | |
49 | ||
50 | rsp = qlcnic_poll_rsp(adapter); | |
51 | ||
52 | if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) { | |
53 | dev_err(&pdev->dev, "card response timeout.\n"); | |
54 | rcode = QLCNIC_RCODE_TIMEOUT; | |
55 | } else if (rsp == QLCNIC_CDRP_RSP_FAIL) { | |
56 | rcode = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET); | |
57 | dev_err(&pdev->dev, "failed card response code:0x%x\n", | |
58 | rcode); | |
59 | } | |
60 | ||
61 | /* Release semaphore */ | |
62 | qlcnic_api_unlock(adapter); | |
63 | ||
64 | return rcode; | |
65 | } | |
66 | ||
67 | int | |
68 | qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu) | |
69 | { | |
70 | struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx; | |
71 | ||
72 | if (recv_ctx->state == QLCNIC_HOST_CTX_STATE_ACTIVE) { | |
73 | if (qlcnic_issue_cmd(adapter, | |
2e9d722d AC |
74 | adapter->ahw.pci_func, |
75 | adapter->fw_hal_version, | |
76 | recv_ctx->context_id, | |
77 | mtu, | |
78 | 0, | |
79 | QLCNIC_CDRP_CMD_SET_MTU)) { | |
af19b491 AKS |
80 | |
81 | dev_err(&adapter->pdev->dev, "Failed to set mtu\n"); | |
82 | return -EIO; | |
83 | } | |
84 | } | |
85 | ||
86 | return 0; | |
87 | } | |
88 | ||
89 | static int | |
90 | qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter) | |
91 | { | |
92 | void *addr; | |
93 | struct qlcnic_hostrq_rx_ctx *prq; | |
94 | struct qlcnic_cardrsp_rx_ctx *prsp; | |
95 | struct qlcnic_hostrq_rds_ring *prq_rds; | |
96 | struct qlcnic_hostrq_sds_ring *prq_sds; | |
97 | struct qlcnic_cardrsp_rds_ring *prsp_rds; | |
98 | struct qlcnic_cardrsp_sds_ring *prsp_sds; | |
99 | struct qlcnic_host_rds_ring *rds_ring; | |
100 | struct qlcnic_host_sds_ring *sds_ring; | |
101 | ||
102 | dma_addr_t hostrq_phys_addr, cardrsp_phys_addr; | |
103 | u64 phys_addr; | |
104 | ||
105 | int i, nrds_rings, nsds_rings; | |
106 | size_t rq_size, rsp_size; | |
2e9d722d | 107 | u32 cap, reg, val, reg2; |
af19b491 AKS |
108 | int err; |
109 | ||
110 | struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx; | |
111 | ||
112 | nrds_rings = adapter->max_rds_rings; | |
113 | nsds_rings = adapter->max_sds_rings; | |
114 | ||
115 | rq_size = | |
116 | SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings, | |
117 | nsds_rings); | |
118 | rsp_size = | |
119 | SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings, | |
120 | nsds_rings); | |
121 | ||
122 | addr = pci_alloc_consistent(adapter->pdev, | |
123 | rq_size, &hostrq_phys_addr); | |
124 | if (addr == NULL) | |
125 | return -ENOMEM; | |
126 | prq = (struct qlcnic_hostrq_rx_ctx *)addr; | |
127 | ||
128 | addr = pci_alloc_consistent(adapter->pdev, | |
129 | rsp_size, &cardrsp_phys_addr); | |
130 | if (addr == NULL) { | |
131 | err = -ENOMEM; | |
132 | goto out_free_rq; | |
133 | } | |
134 | prsp = (struct qlcnic_cardrsp_rx_ctx *)addr; | |
135 | ||
136 | prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr); | |
137 | ||
8f891387 | 138 | cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
139 | | QLCNIC_CAP0_VALIDOFF); | |
af19b491 AKS |
140 | cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS); |
141 | ||
8f891387 | 142 | prq->valid_field_offset = offsetof(struct qlcnic_hostrq_rx_ctx, |
143 | msix_handler); | |
144 | prq->txrx_sds_binding = nsds_rings - 1; | |
145 | ||
af19b491 AKS |
146 | prq->capabilities[0] = cpu_to_le32(cap); |
147 | prq->host_int_crb_mode = | |
148 | cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED); | |
149 | prq->host_rds_crb_mode = | |
150 | cpu_to_le32(QLCNIC_HOST_RDS_CRB_MODE_UNIQUE); | |
151 | ||
152 | prq->num_rds_rings = cpu_to_le16(nrds_rings); | |
153 | prq->num_sds_rings = cpu_to_le16(nsds_rings); | |
154 | prq->rds_ring_offset = cpu_to_le32(0); | |
155 | ||
156 | val = le32_to_cpu(prq->rds_ring_offset) + | |
157 | (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings); | |
158 | prq->sds_ring_offset = cpu_to_le32(val); | |
159 | ||
160 | prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data + | |
161 | le32_to_cpu(prq->rds_ring_offset)); | |
162 | ||
163 | for (i = 0; i < nrds_rings; i++) { | |
164 | ||
165 | rds_ring = &recv_ctx->rds_rings[i]; | |
8a15ad1f | 166 | rds_ring->producer = 0; |
af19b491 AKS |
167 | |
168 | prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr); | |
169 | prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc); | |
170 | prq_rds[i].ring_kind = cpu_to_le32(i); | |
171 | prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size); | |
172 | } | |
173 | ||
174 | prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data + | |
175 | le32_to_cpu(prq->sds_ring_offset)); | |
176 | ||
177 | for (i = 0; i < nsds_rings; i++) { | |
178 | ||
179 | sds_ring = &recv_ctx->sds_rings[i]; | |
8a15ad1f AKS |
180 | sds_ring->consumer = 0; |
181 | memset(sds_ring->desc_head, 0, STATUS_DESC_RINGSIZE(sds_ring)); | |
af19b491 AKS |
182 | |
183 | prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr); | |
184 | prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc); | |
185 | prq_sds[i].msi_index = cpu_to_le16(i); | |
186 | } | |
187 | ||
188 | phys_addr = hostrq_phys_addr; | |
189 | err = qlcnic_issue_cmd(adapter, | |
190 | adapter->ahw.pci_func, | |
2e9d722d | 191 | adapter->fw_hal_version, |
af19b491 AKS |
192 | (u32)(phys_addr >> 32), |
193 | (u32)(phys_addr & 0xffffffff), | |
194 | rq_size, | |
195 | QLCNIC_CDRP_CMD_CREATE_RX_CTX); | |
196 | if (err) { | |
197 | dev_err(&adapter->pdev->dev, | |
198 | "Failed to create rx ctx in firmware%d\n", err); | |
199 | goto out_free_rsp; | |
200 | } | |
201 | ||
202 | ||
203 | prsp_rds = ((struct qlcnic_cardrsp_rds_ring *) | |
204 | &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]); | |
205 | ||
206 | for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) { | |
207 | rds_ring = &recv_ctx->rds_rings[i]; | |
208 | ||
209 | reg = le32_to_cpu(prsp_rds[i].host_producer_crb); | |
45918e2f | 210 | rds_ring->crb_rcv_producer = adapter->ahw.pci_base0 + reg; |
af19b491 AKS |
211 | } |
212 | ||
213 | prsp_sds = ((struct qlcnic_cardrsp_sds_ring *) | |
214 | &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]); | |
215 | ||
216 | for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) { | |
217 | sds_ring = &recv_ctx->sds_rings[i]; | |
218 | ||
219 | reg = le32_to_cpu(prsp_sds[i].host_consumer_crb); | |
2e9d722d | 220 | reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb); |
af19b491 | 221 | |
45918e2f AC |
222 | sds_ring->crb_sts_consumer = adapter->ahw.pci_base0 + reg; |
223 | sds_ring->crb_intr_mask = adapter->ahw.pci_base0 + reg2; | |
af19b491 AKS |
224 | } |
225 | ||
226 | recv_ctx->state = le32_to_cpu(prsp->host_ctx_state); | |
227 | recv_ctx->context_id = le16_to_cpu(prsp->context_id); | |
228 | recv_ctx->virt_port = prsp->virt_port; | |
229 | ||
230 | out_free_rsp: | |
231 | pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr); | |
232 | out_free_rq: | |
233 | pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr); | |
234 | return err; | |
235 | } | |
236 | ||
237 | static void | |
238 | qlcnic_fw_cmd_destroy_rx_ctx(struct qlcnic_adapter *adapter) | |
239 | { | |
240 | struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx; | |
241 | ||
242 | if (qlcnic_issue_cmd(adapter, | |
243 | adapter->ahw.pci_func, | |
2e9d722d | 244 | adapter->fw_hal_version, |
af19b491 AKS |
245 | recv_ctx->context_id, |
246 | QLCNIC_DESTROY_CTX_RESET, | |
247 | 0, | |
248 | QLCNIC_CDRP_CMD_DESTROY_RX_CTX)) { | |
249 | ||
250 | dev_err(&adapter->pdev->dev, | |
251 | "Failed to destroy rx ctx in firmware\n"); | |
252 | } | |
d626ad4d AKS |
253 | |
254 | recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED; | |
af19b491 AKS |
255 | } |
256 | ||
257 | static int | |
258 | qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter) | |
259 | { | |
260 | struct qlcnic_hostrq_tx_ctx *prq; | |
261 | struct qlcnic_hostrq_cds_ring *prq_cds; | |
262 | struct qlcnic_cardrsp_tx_ctx *prsp; | |
263 | void *rq_addr, *rsp_addr; | |
264 | size_t rq_size, rsp_size; | |
265 | u32 temp; | |
266 | int err; | |
267 | u64 phys_addr; | |
268 | dma_addr_t rq_phys_addr, rsp_phys_addr; | |
269 | struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring; | |
270 | ||
8a15ad1f AKS |
271 | /* reset host resources */ |
272 | tx_ring->producer = 0; | |
273 | tx_ring->sw_consumer = 0; | |
274 | *(tx_ring->hw_consumer) = 0; | |
275 | ||
af19b491 AKS |
276 | rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx); |
277 | rq_addr = pci_alloc_consistent(adapter->pdev, | |
278 | rq_size, &rq_phys_addr); | |
279 | if (!rq_addr) | |
280 | return -ENOMEM; | |
281 | ||
282 | rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx); | |
283 | rsp_addr = pci_alloc_consistent(adapter->pdev, | |
284 | rsp_size, &rsp_phys_addr); | |
285 | if (!rsp_addr) { | |
286 | err = -ENOMEM; | |
287 | goto out_free_rq; | |
288 | } | |
289 | ||
290 | memset(rq_addr, 0, rq_size); | |
291 | prq = (struct qlcnic_hostrq_tx_ctx *)rq_addr; | |
292 | ||
293 | memset(rsp_addr, 0, rsp_size); | |
294 | prsp = (struct qlcnic_cardrsp_tx_ctx *)rsp_addr; | |
295 | ||
296 | prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr); | |
297 | ||
298 | temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN | | |
299 | QLCNIC_CAP0_LSO); | |
300 | prq->capabilities[0] = cpu_to_le32(temp); | |
301 | ||
302 | prq->host_int_crb_mode = | |
303 | cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED); | |
304 | ||
305 | prq->interrupt_ctl = 0; | |
306 | prq->msi_index = 0; | |
307 | prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr); | |
308 | ||
309 | prq_cds = &prq->cds_ring; | |
310 | ||
311 | prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr); | |
312 | prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc); | |
313 | ||
314 | phys_addr = rq_phys_addr; | |
315 | err = qlcnic_issue_cmd(adapter, | |
316 | adapter->ahw.pci_func, | |
2e9d722d | 317 | adapter->fw_hal_version, |
af19b491 AKS |
318 | (u32)(phys_addr >> 32), |
319 | ((u32)phys_addr & 0xffffffff), | |
320 | rq_size, | |
321 | QLCNIC_CDRP_CMD_CREATE_TX_CTX); | |
322 | ||
323 | if (err == QLCNIC_RCODE_SUCCESS) { | |
324 | temp = le32_to_cpu(prsp->cds_ring.host_producer_crb); | |
45918e2f | 325 | tx_ring->crb_cmd_producer = adapter->ahw.pci_base0 + temp; |
af19b491 AKS |
326 | |
327 | adapter->tx_context_id = | |
328 | le16_to_cpu(prsp->context_id); | |
329 | } else { | |
330 | dev_err(&adapter->pdev->dev, | |
331 | "Failed to create tx ctx in firmware%d\n", err); | |
332 | err = -EIO; | |
333 | } | |
334 | ||
335 | pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr); | |
336 | ||
337 | out_free_rq: | |
338 | pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr); | |
339 | ||
340 | return err; | |
341 | } | |
342 | ||
343 | static void | |
344 | qlcnic_fw_cmd_destroy_tx_ctx(struct qlcnic_adapter *adapter) | |
345 | { | |
346 | if (qlcnic_issue_cmd(adapter, | |
347 | adapter->ahw.pci_func, | |
2e9d722d | 348 | adapter->fw_hal_version, |
af19b491 AKS |
349 | adapter->tx_context_id, |
350 | QLCNIC_DESTROY_CTX_RESET, | |
351 | 0, | |
352 | QLCNIC_CDRP_CMD_DESTROY_TX_CTX)) { | |
353 | ||
354 | dev_err(&adapter->pdev->dev, | |
355 | "Failed to destroy tx ctx in firmware\n"); | |
356 | } | |
357 | } | |
358 | ||
359 | int | |
360 | qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val) | |
361 | { | |
362 | ||
363 | if (qlcnic_issue_cmd(adapter, | |
364 | adapter->ahw.pci_func, | |
2e9d722d | 365 | adapter->fw_hal_version, |
af19b491 AKS |
366 | reg, |
367 | 0, | |
368 | 0, | |
369 | QLCNIC_CDRP_CMD_READ_PHY)) { | |
370 | ||
371 | return -EIO; | |
372 | } | |
373 | ||
374 | return QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET); | |
375 | } | |
376 | ||
377 | int | |
378 | qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val) | |
379 | { | |
380 | return qlcnic_issue_cmd(adapter, | |
381 | adapter->ahw.pci_func, | |
2e9d722d | 382 | adapter->fw_hal_version, |
af19b491 AKS |
383 | reg, |
384 | val, | |
385 | 0, | |
386 | QLCNIC_CDRP_CMD_WRITE_PHY); | |
387 | } | |
388 | ||
389 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter) | |
390 | { | |
391 | void *addr; | |
392 | int err; | |
393 | int ring; | |
394 | struct qlcnic_recv_context *recv_ctx; | |
395 | struct qlcnic_host_rds_ring *rds_ring; | |
396 | struct qlcnic_host_sds_ring *sds_ring; | |
397 | struct qlcnic_host_tx_ring *tx_ring; | |
398 | ||
399 | struct pci_dev *pdev = adapter->pdev; | |
400 | ||
401 | recv_ctx = &adapter->recv_ctx; | |
402 | tx_ring = adapter->tx_ring; | |
403 | ||
404 | tx_ring->hw_consumer = (__le32 *)pci_alloc_consistent(pdev, sizeof(u32), | |
405 | &tx_ring->hw_cons_phys_addr); | |
406 | if (tx_ring->hw_consumer == NULL) { | |
407 | dev_err(&pdev->dev, "failed to allocate tx consumer\n"); | |
408 | return -ENOMEM; | |
409 | } | |
410 | *(tx_ring->hw_consumer) = 0; | |
411 | ||
412 | /* cmd desc ring */ | |
413 | addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring), | |
414 | &tx_ring->phys_addr); | |
415 | ||
416 | if (addr == NULL) { | |
417 | dev_err(&pdev->dev, "failed to allocate tx desc ring\n"); | |
aadd8184 AC |
418 | err = -ENOMEM; |
419 | goto err_out_free; | |
af19b491 AKS |
420 | } |
421 | ||
422 | tx_ring->desc_head = (struct cmd_desc_type0 *)addr; | |
423 | ||
424 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
425 | rds_ring = &recv_ctx->rds_rings[ring]; | |
426 | addr = pci_alloc_consistent(adapter->pdev, | |
427 | RCV_DESC_RINGSIZE(rds_ring), | |
428 | &rds_ring->phys_addr); | |
429 | if (addr == NULL) { | |
430 | dev_err(&pdev->dev, | |
431 | "failed to allocate rds ring [%d]\n", ring); | |
432 | err = -ENOMEM; | |
433 | goto err_out_free; | |
434 | } | |
435 | rds_ring->desc_head = (struct rcv_desc *)addr; | |
436 | ||
437 | } | |
438 | ||
439 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { | |
440 | sds_ring = &recv_ctx->sds_rings[ring]; | |
441 | ||
442 | addr = pci_alloc_consistent(adapter->pdev, | |
443 | STATUS_DESC_RINGSIZE(sds_ring), | |
444 | &sds_ring->phys_addr); | |
445 | if (addr == NULL) { | |
446 | dev_err(&pdev->dev, | |
447 | "failed to allocate sds ring [%d]\n", ring); | |
448 | err = -ENOMEM; | |
449 | goto err_out_free; | |
450 | } | |
451 | sds_ring->desc_head = (struct status_desc *)addr; | |
452 | } | |
453 | ||
af19b491 AKS |
454 | return 0; |
455 | ||
456 | err_out_free: | |
457 | qlcnic_free_hw_resources(adapter); | |
458 | return err; | |
459 | } | |
460 | ||
8a15ad1f AKS |
461 | |
462 | int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter) | |
af19b491 | 463 | { |
8a15ad1f AKS |
464 | int err; |
465 | ||
b0044bcf | 466 | if (adapter->flags & QLCNIC_NEED_FLR) { |
c21fd48c | 467 | pci_reset_function(adapter->pdev); |
b0044bcf RB |
468 | adapter->flags &= ~QLCNIC_NEED_FLR; |
469 | } | |
c21fd48c | 470 | |
8a15ad1f AKS |
471 | err = qlcnic_fw_cmd_create_rx_ctx(adapter); |
472 | if (err) | |
473 | return err; | |
474 | ||
475 | err = qlcnic_fw_cmd_create_tx_ctx(adapter); | |
476 | if (err) { | |
477 | qlcnic_fw_cmd_destroy_rx_ctx(adapter); | |
478 | return err; | |
479 | } | |
af19b491 | 480 | |
8a15ad1f AKS |
481 | set_bit(__QLCNIC_FW_ATTACHED, &adapter->state); |
482 | return 0; | |
483 | } | |
af19b491 | 484 | |
8a15ad1f AKS |
485 | void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter) |
486 | { | |
af19b491 AKS |
487 | if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) { |
488 | qlcnic_fw_cmd_destroy_rx_ctx(adapter); | |
489 | qlcnic_fw_cmd_destroy_tx_ctx(adapter); | |
490 | ||
491 | /* Allow dma queues to drain after context reset */ | |
492 | msleep(20); | |
493 | } | |
8a15ad1f AKS |
494 | } |
495 | ||
496 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter) | |
497 | { | |
498 | struct qlcnic_recv_context *recv_ctx; | |
499 | struct qlcnic_host_rds_ring *rds_ring; | |
500 | struct qlcnic_host_sds_ring *sds_ring; | |
501 | struct qlcnic_host_tx_ring *tx_ring; | |
502 | int ring; | |
af19b491 AKS |
503 | |
504 | recv_ctx = &adapter->recv_ctx; | |
505 | ||
506 | tx_ring = adapter->tx_ring; | |
507 | if (tx_ring->hw_consumer != NULL) { | |
508 | pci_free_consistent(adapter->pdev, | |
509 | sizeof(u32), | |
510 | tx_ring->hw_consumer, | |
511 | tx_ring->hw_cons_phys_addr); | |
512 | tx_ring->hw_consumer = NULL; | |
513 | } | |
514 | ||
515 | if (tx_ring->desc_head != NULL) { | |
516 | pci_free_consistent(adapter->pdev, | |
517 | TX_DESC_RINGSIZE(tx_ring), | |
518 | tx_ring->desc_head, tx_ring->phys_addr); | |
519 | tx_ring->desc_head = NULL; | |
520 | } | |
521 | ||
522 | for (ring = 0; ring < adapter->max_rds_rings; ring++) { | |
523 | rds_ring = &recv_ctx->rds_rings[ring]; | |
524 | ||
525 | if (rds_ring->desc_head != NULL) { | |
526 | pci_free_consistent(adapter->pdev, | |
527 | RCV_DESC_RINGSIZE(rds_ring), | |
528 | rds_ring->desc_head, | |
529 | rds_ring->phys_addr); | |
530 | rds_ring->desc_head = NULL; | |
531 | } | |
532 | } | |
533 | ||
534 | for (ring = 0; ring < adapter->max_sds_rings; ring++) { | |
535 | sds_ring = &recv_ctx->sds_rings[ring]; | |
536 | ||
537 | if (sds_ring->desc_head != NULL) { | |
538 | pci_free_consistent(adapter->pdev, | |
539 | STATUS_DESC_RINGSIZE(sds_ring), | |
540 | sds_ring->desc_head, | |
541 | sds_ring->phys_addr); | |
542 | sds_ring->desc_head = NULL; | |
543 | } | |
544 | } | |
545 | } | |
546 | ||
2e9d722d AC |
547 | |
548 | /* Get MAC address of a NIC partition */ | |
549 | int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac) | |
550 | { | |
551 | int err; | |
552 | u32 arg1; | |
553 | ||
554 | arg1 = adapter->ahw.pci_func | BIT_8; | |
555 | err = qlcnic_issue_cmd(adapter, | |
556 | adapter->ahw.pci_func, | |
557 | adapter->fw_hal_version, | |
558 | arg1, | |
559 | 0, | |
560 | 0, | |
561 | QLCNIC_CDRP_CMD_MAC_ADDRESS); | |
562 | ||
7f9a0c34 | 563 | if (err == QLCNIC_RCODE_SUCCESS) |
2e9d722d AC |
564 | qlcnic_fetch_mac(adapter, QLCNIC_ARG1_CRB_OFFSET, |
565 | QLCNIC_ARG2_CRB_OFFSET, 0, mac); | |
7f9a0c34 | 566 | else { |
2e9d722d AC |
567 | dev_err(&adapter->pdev->dev, |
568 | "Failed to get mac address%d\n", err); | |
569 | err = -EIO; | |
570 | } | |
571 | ||
572 | return err; | |
573 | } | |
574 | ||
575 | /* Get info of a NIC partition */ | |
346fe763 RB |
576 | int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, |
577 | struct qlcnic_info *npar_info, u8 func_id) | |
2e9d722d AC |
578 | { |
579 | int err; | |
580 | dma_addr_t nic_dma_t; | |
581 | struct qlcnic_info *nic_info; | |
582 | void *nic_info_addr; | |
583 | size_t nic_size = sizeof(struct qlcnic_info); | |
584 | ||
585 | nic_info_addr = pci_alloc_consistent(adapter->pdev, | |
586 | nic_size, &nic_dma_t); | |
587 | if (!nic_info_addr) | |
588 | return -ENOMEM; | |
589 | memset(nic_info_addr, 0, nic_size); | |
590 | ||
591 | nic_info = (struct qlcnic_info *) nic_info_addr; | |
592 | err = qlcnic_issue_cmd(adapter, | |
593 | adapter->ahw.pci_func, | |
594 | adapter->fw_hal_version, | |
595 | MSD(nic_dma_t), | |
596 | LSD(nic_dma_t), | |
597 | (func_id << 16 | nic_size), | |
598 | QLCNIC_CDRP_CMD_GET_NIC_INFO); | |
599 | ||
600 | if (err == QLCNIC_RCODE_SUCCESS) { | |
cea8975e AC |
601 | npar_info->pci_func = le16_to_cpu(nic_info->pci_func); |
602 | npar_info->op_mode = le16_to_cpu(nic_info->op_mode); | |
346fe763 RB |
603 | npar_info->phys_port = le16_to_cpu(nic_info->phys_port); |
604 | npar_info->switch_mode = le16_to_cpu(nic_info->switch_mode); | |
605 | npar_info->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques); | |
606 | npar_info->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques); | |
607 | npar_info->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw); | |
608 | npar_info->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw); | |
609 | npar_info->capabilities = le32_to_cpu(nic_info->capabilities); | |
610 | npar_info->max_mtu = le16_to_cpu(nic_info->max_mtu); | |
0e33c664 | 611 | |
2e9d722d AC |
612 | dev_info(&adapter->pdev->dev, |
613 | "phy port: %d switch_mode: %d,\n" | |
614 | "\tmax_tx_q: %d max_rx_q: %d min_tx_bw: 0x%x,\n" | |
615 | "\tmax_tx_bw: 0x%x max_mtu:0x%x, capabilities: 0x%x\n", | |
346fe763 RB |
616 | npar_info->phys_port, npar_info->switch_mode, |
617 | npar_info->max_tx_ques, npar_info->max_rx_ques, | |
618 | npar_info->min_tx_bw, npar_info->max_tx_bw, | |
619 | npar_info->max_mtu, npar_info->capabilities); | |
2e9d722d AC |
620 | } else { |
621 | dev_err(&adapter->pdev->dev, | |
622 | "Failed to get nic info%d\n", err); | |
623 | err = -EIO; | |
624 | } | |
625 | ||
626 | pci_free_consistent(adapter->pdev, nic_size, nic_info_addr, nic_dma_t); | |
627 | return err; | |
628 | } | |
629 | ||
630 | /* Configure a NIC partition */ | |
631 | int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, struct qlcnic_info *nic) | |
632 | { | |
633 | int err = -EIO; | |
2e9d722d AC |
634 | dma_addr_t nic_dma_t; |
635 | void *nic_info_addr; | |
636 | struct qlcnic_info *nic_info; | |
637 | size_t nic_size = sizeof(struct qlcnic_info); | |
638 | ||
639 | if (adapter->op_mode != QLCNIC_MGMT_FUNC) | |
640 | return err; | |
641 | ||
2e9d722d AC |
642 | nic_info_addr = pci_alloc_consistent(adapter->pdev, nic_size, |
643 | &nic_dma_t); | |
644 | if (!nic_info_addr) | |
645 | return -ENOMEM; | |
646 | ||
647 | memset(nic_info_addr, 0, nic_size); | |
648 | nic_info = (struct qlcnic_info *)nic_info_addr; | |
649 | ||
650 | nic_info->pci_func = cpu_to_le16(nic->pci_func); | |
651 | nic_info->op_mode = cpu_to_le16(nic->op_mode); | |
652 | nic_info->phys_port = cpu_to_le16(nic->phys_port); | |
653 | nic_info->switch_mode = cpu_to_le16(nic->switch_mode); | |
654 | nic_info->capabilities = cpu_to_le32(nic->capabilities); | |
655 | nic_info->max_mac_filters = nic->max_mac_filters; | |
656 | nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques); | |
657 | nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques); | |
658 | nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw); | |
659 | nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw); | |
660 | ||
661 | err = qlcnic_issue_cmd(adapter, | |
662 | adapter->ahw.pci_func, | |
663 | adapter->fw_hal_version, | |
664 | MSD(nic_dma_t), | |
665 | LSD(nic_dma_t), | |
346fe763 | 666 | ((nic->pci_func << 16) | nic_size), |
2e9d722d AC |
667 | QLCNIC_CDRP_CMD_SET_NIC_INFO); |
668 | ||
669 | if (err != QLCNIC_RCODE_SUCCESS) { | |
670 | dev_err(&adapter->pdev->dev, | |
671 | "Failed to set nic info%d\n", err); | |
672 | err = -EIO; | |
673 | } | |
674 | ||
675 | pci_free_consistent(adapter->pdev, nic_size, nic_info_addr, nic_dma_t); | |
676 | return err; | |
677 | } | |
678 | ||
679 | /* Get PCI Info of a partition */ | |
346fe763 RB |
680 | int qlcnic_get_pci_info(struct qlcnic_adapter *adapter, |
681 | struct qlcnic_pci_info *pci_info) | |
2e9d722d AC |
682 | { |
683 | int err = 0, i; | |
684 | dma_addr_t pci_info_dma_t; | |
685 | struct qlcnic_pci_info *npar; | |
686 | void *pci_info_addr; | |
687 | size_t npar_size = sizeof(struct qlcnic_pci_info); | |
688 | size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC; | |
689 | ||
690 | pci_info_addr = pci_alloc_consistent(adapter->pdev, pci_size, | |
691 | &pci_info_dma_t); | |
692 | if (!pci_info_addr) | |
693 | return -ENOMEM; | |
694 | memset(pci_info_addr, 0, pci_size); | |
695 | ||
2e9d722d AC |
696 | npar = (struct qlcnic_pci_info *) pci_info_addr; |
697 | err = qlcnic_issue_cmd(adapter, | |
698 | adapter->ahw.pci_func, | |
699 | adapter->fw_hal_version, | |
700 | MSD(pci_info_dma_t), | |
701 | LSD(pci_info_dma_t), | |
702 | pci_size, | |
703 | QLCNIC_CDRP_CMD_GET_PCI_INFO); | |
704 | ||
705 | if (err == QLCNIC_RCODE_SUCCESS) { | |
346fe763 | 706 | for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++, pci_info++) { |
a1c0c459 SC |
707 | pci_info->id = le16_to_cpu(npar->id); |
708 | pci_info->active = le16_to_cpu(npar->active); | |
709 | pci_info->type = le16_to_cpu(npar->type); | |
346fe763 | 710 | pci_info->default_port = |
a1c0c459 | 711 | le16_to_cpu(npar->default_port); |
346fe763 | 712 | pci_info->tx_min_bw = |
a1c0c459 | 713 | le16_to_cpu(npar->tx_min_bw); |
346fe763 | 714 | pci_info->tx_max_bw = |
a1c0c459 | 715 | le16_to_cpu(npar->tx_max_bw); |
346fe763 | 716 | memcpy(pci_info->mac, npar->mac, ETH_ALEN); |
2e9d722d AC |
717 | } |
718 | } else { | |
719 | dev_err(&adapter->pdev->dev, | |
720 | "Failed to get PCI Info%d\n", err); | |
2e9d722d AC |
721 | err = -EIO; |
722 | } | |
2e9d722d | 723 | |
2e9d722d AC |
724 | pci_free_consistent(adapter->pdev, pci_size, pci_info_addr, |
725 | pci_info_dma_t); | |
726 | return err; | |
727 | } | |
728 | ||
2e9d722d AC |
729 | /* Configure eSwitch for port mirroring */ |
730 | int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id, | |
731 | u8 enable_mirroring, u8 pci_func) | |
732 | { | |
733 | int err = -EIO; | |
734 | u32 arg1; | |
735 | ||
736 | if (adapter->op_mode != QLCNIC_MGMT_FUNC || | |
737 | !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE)) | |
738 | return err; | |
739 | ||
740 | arg1 = id | (enable_mirroring ? BIT_4 : 0); | |
741 | arg1 |= pci_func << 8; | |
742 | ||
743 | err = qlcnic_issue_cmd(adapter, | |
744 | adapter->ahw.pci_func, | |
745 | adapter->fw_hal_version, | |
746 | arg1, | |
747 | 0, | |
748 | 0, | |
749 | QLCNIC_CDRP_CMD_SET_PORTMIRRORING); | |
750 | ||
751 | if (err != QLCNIC_RCODE_SUCCESS) { | |
752 | dev_err(&adapter->pdev->dev, | |
753 | "Failed to configure port mirroring%d on eswitch:%d\n", | |
754 | pci_func, id); | |
755 | } else { | |
756 | dev_info(&adapter->pdev->dev, | |
757 | "Configured eSwitch %d for port mirroring:%d\n", | |
758 | id, pci_func); | |
759 | } | |
760 | ||
761 | return err; | |
762 | } | |
763 | ||
b6021212 AKS |
764 | int qlcnic_get_port_stats(struct qlcnic_adapter *adapter, const u8 func, |
765 | const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) { | |
766 | ||
767 | size_t stats_size = sizeof(struct __qlcnic_esw_statistics); | |
63e74e9c | 768 | struct __qlcnic_esw_statistics *stats; |
b6021212 AKS |
769 | dma_addr_t stats_dma_t; |
770 | void *stats_addr; | |
771 | u32 arg1; | |
772 | int err; | |
773 | ||
774 | if (esw_stats == NULL) | |
775 | return -ENOMEM; | |
776 | ||
777 | if (adapter->op_mode != QLCNIC_MGMT_FUNC && | |
778 | func != adapter->ahw.pci_func) { | |
779 | dev_err(&adapter->pdev->dev, | |
780 | "Not privilege to query stats for func=%d", func); | |
781 | return -EIO; | |
782 | } | |
783 | ||
784 | stats_addr = pci_alloc_consistent(adapter->pdev, stats_size, | |
785 | &stats_dma_t); | |
786 | if (!stats_addr) { | |
787 | dev_err(&adapter->pdev->dev, "Unable to allocate memory\n"); | |
788 | return -ENOMEM; | |
789 | } | |
790 | memset(stats_addr, 0, stats_size); | |
791 | ||
792 | arg1 = func | QLCNIC_STATS_VERSION << 8 | QLCNIC_STATS_PORT << 12; | |
793 | arg1 |= rx_tx << 15 | stats_size << 16; | |
794 | ||
795 | err = qlcnic_issue_cmd(adapter, | |
796 | adapter->ahw.pci_func, | |
797 | adapter->fw_hal_version, | |
798 | arg1, | |
799 | MSD(stats_dma_t), | |
800 | LSD(stats_dma_t), | |
801 | QLCNIC_CDRP_CMD_GET_ESWITCH_STATS); | |
802 | ||
63e74e9c AKS |
803 | if (!err) { |
804 | stats = (struct __qlcnic_esw_statistics *)stats_addr; | |
805 | esw_stats->context_id = le16_to_cpu(stats->context_id); | |
806 | esw_stats->version = le16_to_cpu(stats->version); | |
807 | esw_stats->size = le16_to_cpu(stats->size); | |
808 | esw_stats->multicast_frames = | |
809 | le64_to_cpu(stats->multicast_frames); | |
810 | esw_stats->broadcast_frames = | |
811 | le64_to_cpu(stats->broadcast_frames); | |
812 | esw_stats->unicast_frames = le64_to_cpu(stats->unicast_frames); | |
813 | esw_stats->dropped_frames = le64_to_cpu(stats->dropped_frames); | |
814 | esw_stats->local_frames = le64_to_cpu(stats->local_frames); | |
815 | esw_stats->errors = le64_to_cpu(stats->errors); | |
816 | esw_stats->numbytes = le64_to_cpu(stats->numbytes); | |
817 | } | |
b6021212 AKS |
818 | |
819 | pci_free_consistent(adapter->pdev, stats_size, stats_addr, | |
820 | stats_dma_t); | |
821 | return err; | |
822 | } | |
823 | ||
824 | int qlcnic_get_eswitch_stats(struct qlcnic_adapter *adapter, const u8 eswitch, | |
825 | const u8 rx_tx, struct __qlcnic_esw_statistics *esw_stats) { | |
826 | ||
827 | struct __qlcnic_esw_statistics port_stats; | |
828 | u8 i; | |
829 | int ret = -EIO; | |
830 | ||
831 | if (esw_stats == NULL) | |
832 | return -ENOMEM; | |
833 | if (adapter->op_mode != QLCNIC_MGMT_FUNC) | |
834 | return -EIO; | |
835 | if (adapter->npars == NULL) | |
836 | return -EIO; | |
837 | ||
ef182805 AKS |
838 | memset(esw_stats, 0, sizeof(u64)); |
839 | esw_stats->unicast_frames = QLCNIC_ESW_STATS_NOT_AVAIL; | |
840 | esw_stats->multicast_frames = QLCNIC_ESW_STATS_NOT_AVAIL; | |
841 | esw_stats->broadcast_frames = QLCNIC_ESW_STATS_NOT_AVAIL; | |
842 | esw_stats->dropped_frames = QLCNIC_ESW_STATS_NOT_AVAIL; | |
843 | esw_stats->errors = QLCNIC_ESW_STATS_NOT_AVAIL; | |
844 | esw_stats->local_frames = QLCNIC_ESW_STATS_NOT_AVAIL; | |
845 | esw_stats->numbytes = QLCNIC_ESW_STATS_NOT_AVAIL; | |
b6021212 AKS |
846 | esw_stats->context_id = eswitch; |
847 | ||
848 | for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++) { | |
849 | if (adapter->npars[i].phy_port != eswitch) | |
850 | continue; | |
851 | ||
852 | memset(&port_stats, 0, sizeof(struct __qlcnic_esw_statistics)); | |
853 | if (qlcnic_get_port_stats(adapter, i, rx_tx, &port_stats)) | |
854 | continue; | |
855 | ||
856 | esw_stats->size = port_stats.size; | |
857 | esw_stats->version = port_stats.version; | |
ef182805 AKS |
858 | QLCNIC_ADD_ESW_STATS(esw_stats->unicast_frames, |
859 | port_stats.unicast_frames); | |
860 | QLCNIC_ADD_ESW_STATS(esw_stats->multicast_frames, | |
861 | port_stats.multicast_frames); | |
862 | QLCNIC_ADD_ESW_STATS(esw_stats->broadcast_frames, | |
863 | port_stats.broadcast_frames); | |
864 | QLCNIC_ADD_ESW_STATS(esw_stats->dropped_frames, | |
865 | port_stats.dropped_frames); | |
866 | QLCNIC_ADD_ESW_STATS(esw_stats->errors, | |
867 | port_stats.errors); | |
868 | QLCNIC_ADD_ESW_STATS(esw_stats->local_frames, | |
869 | port_stats.local_frames); | |
870 | QLCNIC_ADD_ESW_STATS(esw_stats->numbytes, | |
871 | port_stats.numbytes); | |
b6021212 AKS |
872 | ret = 0; |
873 | } | |
874 | return ret; | |
875 | } | |
876 | ||
877 | int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, const u8 func_esw, | |
878 | const u8 port, const u8 rx_tx) | |
879 | { | |
880 | ||
881 | u32 arg1; | |
882 | ||
883 | if (adapter->op_mode != QLCNIC_MGMT_FUNC) | |
884 | return -EIO; | |
885 | ||
886 | if (func_esw == QLCNIC_STATS_PORT) { | |
887 | if (port >= QLCNIC_MAX_PCI_FUNC) | |
888 | goto err_ret; | |
889 | } else if (func_esw == QLCNIC_STATS_ESWITCH) { | |
890 | if (port >= QLCNIC_NIU_MAX_XG_PORTS) | |
891 | goto err_ret; | |
892 | } else { | |
893 | goto err_ret; | |
894 | } | |
895 | ||
896 | if (rx_tx > QLCNIC_QUERY_TX_COUNTER) | |
897 | goto err_ret; | |
898 | ||
899 | arg1 = port | QLCNIC_STATS_VERSION << 8 | func_esw << 12; | |
900 | arg1 |= BIT_14 | rx_tx << 15; | |
901 | ||
902 | return qlcnic_issue_cmd(adapter, | |
903 | adapter->ahw.pci_func, | |
904 | adapter->fw_hal_version, | |
905 | arg1, | |
906 | 0, | |
907 | 0, | |
908 | QLCNIC_CDRP_CMD_GET_ESWITCH_STATS); | |
909 | ||
910 | err_ret: | |
911 | dev_err(&adapter->pdev->dev, "Invalid argument func_esw=%d port=%d" | |
912 | "rx_ctx=%d\n", func_esw, port, rx_tx); | |
913 | return -EIO; | |
914 | } | |
4e8acb01 RB |
915 | |
916 | static int | |
917 | __qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter, | |
918 | u32 *arg1, u32 *arg2) | |
919 | { | |
920 | int err = -EIO; | |
921 | u8 pci_func; | |
922 | pci_func = (*arg1 >> 8); | |
923 | err = qlcnic_issue_cmd(adapter, | |
924 | adapter->ahw.pci_func, | |
925 | adapter->fw_hal_version, | |
926 | *arg1, | |
927 | 0, | |
928 | 0, | |
929 | QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG); | |
930 | ||
931 | if (err == QLCNIC_RCODE_SUCCESS) { | |
932 | *arg1 = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET); | |
933 | *arg2 = QLCRD32(adapter, QLCNIC_ARG2_CRB_OFFSET); | |
934 | dev_info(&adapter->pdev->dev, | |
7373373d | 935 | "eSwitch port config for pci func %d\n", pci_func); |
4e8acb01 RB |
936 | } else { |
937 | dev_err(&adapter->pdev->dev, | |
7373373d RB |
938 | "Failed to get eswitch port config for pci func %d\n", |
939 | pci_func); | |
4e8acb01 RB |
940 | } |
941 | return err; | |
942 | } | |
943 | /* Configure eSwitch port | |
944 | op_mode = 0 for setting default port behavior | |
945 | op_mode = 1 for setting vlan id | |
946 | op_mode = 2 for deleting vlan id | |
947 | op_type = 0 for vlan_id | |
948 | op_type = 1 for port vlan_id | |
949 | */ | |
950 | int qlcnic_config_switch_port(struct qlcnic_adapter *adapter, | |
951 | struct qlcnic_esw_func_cfg *esw_cfg) | |
952 | { | |
953 | int err = -EIO; | |
954 | u32 arg1, arg2 = 0; | |
955 | u8 pci_func; | |
956 | ||
957 | if (adapter->op_mode != QLCNIC_MGMT_FUNC) | |
958 | return err; | |
959 | pci_func = esw_cfg->pci_func; | |
960 | arg1 = (adapter->npars[pci_func].phy_port & BIT_0); | |
961 | arg1 |= (pci_func << 8); | |
962 | ||
963 | if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2)) | |
964 | return err; | |
965 | arg1 &= ~(0x0ff << 8); | |
966 | arg1 |= (pci_func << 8); | |
967 | arg1 &= ~(BIT_2 | BIT_3); | |
968 | switch (esw_cfg->op_mode) { | |
969 | case QLCNIC_PORT_DEFAULTS: | |
970 | arg1 |= (BIT_4 | BIT_6 | BIT_7); | |
971 | arg2 |= (BIT_0 | BIT_1); | |
972 | if (adapter->capabilities & QLCNIC_FW_CAPABILITY_TSO) | |
973 | arg2 |= (BIT_2 | BIT_3); | |
974 | if (!(esw_cfg->discard_tagged)) | |
975 | arg1 &= ~BIT_4; | |
976 | if (!(esw_cfg->promisc_mode)) | |
977 | arg1 &= ~BIT_6; | |
7373373d | 978 | if (!(esw_cfg->mac_override)) |
4e8acb01 RB |
979 | arg1 &= ~BIT_7; |
980 | if (!(esw_cfg->mac_anti_spoof)) | |
981 | arg2 &= ~BIT_0; | |
982 | if (!(esw_cfg->offload_flags & BIT_0)) | |
983 | arg2 &= ~(BIT_1 | BIT_2 | BIT_3); | |
984 | if (!(esw_cfg->offload_flags & BIT_1)) | |
985 | arg2 &= ~BIT_2; | |
986 | if (!(esw_cfg->offload_flags & BIT_2)) | |
987 | arg2 &= ~BIT_3; | |
988 | break; | |
989 | case QLCNIC_ADD_VLAN: | |
990 | arg1 |= (BIT_2 | BIT_5); | |
991 | arg1 |= (esw_cfg->vlan_id << 16); | |
992 | break; | |
993 | case QLCNIC_DEL_VLAN: | |
994 | arg1 |= (BIT_3 | BIT_5); | |
995 | arg1 &= ~(0x0ffff << 16); | |
e9a47700 | 996 | break; |
4e8acb01 RB |
997 | default: |
998 | return err; | |
999 | } | |
1000 | ||
1001 | err = qlcnic_issue_cmd(adapter, | |
1002 | adapter->ahw.pci_func, | |
1003 | adapter->fw_hal_version, | |
1004 | arg1, | |
1005 | arg2, | |
1006 | 0, | |
1007 | QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH); | |
1008 | ||
1009 | if (err != QLCNIC_RCODE_SUCCESS) { | |
1010 | dev_err(&adapter->pdev->dev, | |
7373373d | 1011 | "Failed to configure eswitch pci func %d\n", pci_func); |
4e8acb01 RB |
1012 | } else { |
1013 | dev_info(&adapter->pdev->dev, | |
7373373d | 1014 | "Configured eSwitch for pci func %d\n", pci_func); |
4e8acb01 RB |
1015 | } |
1016 | ||
1017 | return err; | |
1018 | } | |
1019 | ||
1020 | int | |
1021 | qlcnic_get_eswitch_port_config(struct qlcnic_adapter *adapter, | |
1022 | struct qlcnic_esw_func_cfg *esw_cfg) | |
1023 | { | |
1024 | u32 arg1, arg2; | |
1025 | u8 phy_port; | |
1026 | if (adapter->op_mode == QLCNIC_MGMT_FUNC) | |
1027 | phy_port = adapter->npars[esw_cfg->pci_func].phy_port; | |
1028 | else | |
1029 | phy_port = adapter->physical_port; | |
1030 | arg1 = phy_port; | |
1031 | arg1 |= (esw_cfg->pci_func << 8); | |
1032 | if (__qlcnic_get_eswitch_port_config(adapter, &arg1, &arg2)) | |
1033 | return -EIO; | |
1034 | ||
1035 | esw_cfg->discard_tagged = !!(arg1 & BIT_4); | |
1036 | esw_cfg->host_vlan_tag = !!(arg1 & BIT_5); | |
1037 | esw_cfg->promisc_mode = !!(arg1 & BIT_6); | |
7373373d | 1038 | esw_cfg->mac_override = !!(arg1 & BIT_7); |
4e8acb01 RB |
1039 | esw_cfg->vlan_id = LSW(arg1 >> 16); |
1040 | esw_cfg->mac_anti_spoof = (arg2 & 0x1); | |
1041 | esw_cfg->offload_flags = ((arg2 >> 1) & 0x7); | |
1042 | ||
1043 | return 0; | |
1044 | } |