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af19b491 | 1 | /* |
40839129 SV |
2 | * QLogic qlcnic NIC Driver |
3 | * Copyright (c) 2009-2010 QLogic Corporation | |
af19b491 | 4 | * |
40839129 | 5 | * See LICENSE.qlcnic for copyright and licensing details. |
af19b491 AKS |
6 | */ |
7 | ||
8 | #ifndef __QLCNIC_HDR_H_ | |
9 | #define __QLCNIC_HDR_H_ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/types.h> | |
13 | ||
14 | /* | |
15 | * The basic unit of access when reading/writing control registers. | |
16 | */ | |
17 | ||
18 | enum { | |
19 | QLCNIC_HW_H0_CH_HUB_ADR = 0x05, | |
20 | QLCNIC_HW_H1_CH_HUB_ADR = 0x0E, | |
21 | QLCNIC_HW_H2_CH_HUB_ADR = 0x03, | |
22 | QLCNIC_HW_H3_CH_HUB_ADR = 0x01, | |
23 | QLCNIC_HW_H4_CH_HUB_ADR = 0x06, | |
24 | QLCNIC_HW_H5_CH_HUB_ADR = 0x07, | |
25 | QLCNIC_HW_H6_CH_HUB_ADR = 0x08 | |
26 | }; | |
27 | ||
28 | /* Hub 0 */ | |
29 | enum { | |
30 | QLCNIC_HW_MN_CRB_AGT_ADR = 0x15, | |
31 | QLCNIC_HW_MS_CRB_AGT_ADR = 0x25 | |
32 | }; | |
33 | ||
34 | /* Hub 1 */ | |
35 | enum { | |
36 | QLCNIC_HW_PS_CRB_AGT_ADR = 0x73, | |
37 | QLCNIC_HW_SS_CRB_AGT_ADR = 0x20, | |
38 | QLCNIC_HW_RPMX3_CRB_AGT_ADR = 0x0b, | |
39 | QLCNIC_HW_QMS_CRB_AGT_ADR = 0x00, | |
40 | QLCNIC_HW_SQGS0_CRB_AGT_ADR = 0x01, | |
41 | QLCNIC_HW_SQGS1_CRB_AGT_ADR = 0x02, | |
42 | QLCNIC_HW_SQGS2_CRB_AGT_ADR = 0x03, | |
43 | QLCNIC_HW_SQGS3_CRB_AGT_ADR = 0x04, | |
44 | QLCNIC_HW_C2C0_CRB_AGT_ADR = 0x58, | |
45 | QLCNIC_HW_C2C1_CRB_AGT_ADR = 0x59, | |
46 | QLCNIC_HW_C2C2_CRB_AGT_ADR = 0x5a, | |
47 | QLCNIC_HW_RPMX2_CRB_AGT_ADR = 0x0a, | |
48 | QLCNIC_HW_RPMX4_CRB_AGT_ADR = 0x0c, | |
49 | QLCNIC_HW_RPMX7_CRB_AGT_ADR = 0x0f, | |
50 | QLCNIC_HW_RPMX9_CRB_AGT_ADR = 0x12, | |
51 | QLCNIC_HW_SMB_CRB_AGT_ADR = 0x18 | |
52 | }; | |
53 | ||
54 | /* Hub 2 */ | |
55 | enum { | |
56 | QLCNIC_HW_NIU_CRB_AGT_ADR = 0x31, | |
57 | QLCNIC_HW_I2C0_CRB_AGT_ADR = 0x19, | |
58 | QLCNIC_HW_I2C1_CRB_AGT_ADR = 0x29, | |
59 | ||
60 | QLCNIC_HW_SN_CRB_AGT_ADR = 0x10, | |
61 | QLCNIC_HW_I2Q_CRB_AGT_ADR = 0x20, | |
62 | QLCNIC_HW_LPC_CRB_AGT_ADR = 0x22, | |
63 | QLCNIC_HW_ROMUSB_CRB_AGT_ADR = 0x21, | |
64 | QLCNIC_HW_QM_CRB_AGT_ADR = 0x66, | |
65 | QLCNIC_HW_SQG0_CRB_AGT_ADR = 0x60, | |
66 | QLCNIC_HW_SQG1_CRB_AGT_ADR = 0x61, | |
67 | QLCNIC_HW_SQG2_CRB_AGT_ADR = 0x62, | |
68 | QLCNIC_HW_SQG3_CRB_AGT_ADR = 0x63, | |
69 | QLCNIC_HW_RPMX1_CRB_AGT_ADR = 0x09, | |
70 | QLCNIC_HW_RPMX5_CRB_AGT_ADR = 0x0d, | |
71 | QLCNIC_HW_RPMX6_CRB_AGT_ADR = 0x0e, | |
72 | QLCNIC_HW_RPMX8_CRB_AGT_ADR = 0x11 | |
73 | }; | |
74 | ||
75 | /* Hub 3 */ | |
76 | enum { | |
77 | QLCNIC_HW_PH_CRB_AGT_ADR = 0x1A, | |
78 | QLCNIC_HW_SRE_CRB_AGT_ADR = 0x50, | |
79 | QLCNIC_HW_EG_CRB_AGT_ADR = 0x51, | |
80 | QLCNIC_HW_RPMX0_CRB_AGT_ADR = 0x08 | |
81 | }; | |
82 | ||
83 | /* Hub 4 */ | |
84 | enum { | |
85 | QLCNIC_HW_PEGN0_CRB_AGT_ADR = 0x40, | |
86 | QLCNIC_HW_PEGN1_CRB_AGT_ADR, | |
87 | QLCNIC_HW_PEGN2_CRB_AGT_ADR, | |
88 | QLCNIC_HW_PEGN3_CRB_AGT_ADR, | |
89 | QLCNIC_HW_PEGNI_CRB_AGT_ADR, | |
90 | QLCNIC_HW_PEGND_CRB_AGT_ADR, | |
91 | QLCNIC_HW_PEGNC_CRB_AGT_ADR, | |
92 | QLCNIC_HW_PEGR0_CRB_AGT_ADR, | |
93 | QLCNIC_HW_PEGR1_CRB_AGT_ADR, | |
94 | QLCNIC_HW_PEGR2_CRB_AGT_ADR, | |
95 | QLCNIC_HW_PEGR3_CRB_AGT_ADR, | |
96 | QLCNIC_HW_PEGN4_CRB_AGT_ADR | |
97 | }; | |
98 | ||
99 | /* Hub 5 */ | |
100 | enum { | |
101 | QLCNIC_HW_PEGS0_CRB_AGT_ADR = 0x40, | |
102 | QLCNIC_HW_PEGS1_CRB_AGT_ADR, | |
103 | QLCNIC_HW_PEGS2_CRB_AGT_ADR, | |
104 | QLCNIC_HW_PEGS3_CRB_AGT_ADR, | |
105 | QLCNIC_HW_PEGSI_CRB_AGT_ADR, | |
106 | QLCNIC_HW_PEGSD_CRB_AGT_ADR, | |
107 | QLCNIC_HW_PEGSC_CRB_AGT_ADR | |
108 | }; | |
109 | ||
110 | /* Hub 6 */ | |
111 | enum { | |
112 | QLCNIC_HW_CAS0_CRB_AGT_ADR = 0x46, | |
113 | QLCNIC_HW_CAS1_CRB_AGT_ADR = 0x47, | |
114 | QLCNIC_HW_CAS2_CRB_AGT_ADR = 0x48, | |
115 | QLCNIC_HW_CAS3_CRB_AGT_ADR = 0x49, | |
116 | QLCNIC_HW_NCM_CRB_AGT_ADR = 0x16, | |
117 | QLCNIC_HW_TMR_CRB_AGT_ADR = 0x17, | |
118 | QLCNIC_HW_XDMA_CRB_AGT_ADR = 0x05, | |
119 | QLCNIC_HW_OCM0_CRB_AGT_ADR = 0x06, | |
120 | QLCNIC_HW_OCM1_CRB_AGT_ADR = 0x07 | |
121 | }; | |
122 | ||
123 | /* Floaters - non existent modules */ | |
124 | #define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR 0x67 | |
125 | ||
126 | /* This field defines PCI/X adr [25:20] of agents on the CRB */ | |
127 | enum { | |
128 | QLCNIC_HW_PX_MAP_CRB_PH = 0, | |
129 | QLCNIC_HW_PX_MAP_CRB_PS, | |
130 | QLCNIC_HW_PX_MAP_CRB_MN, | |
131 | QLCNIC_HW_PX_MAP_CRB_MS, | |
132 | QLCNIC_HW_PX_MAP_CRB_PGR1, | |
133 | QLCNIC_HW_PX_MAP_CRB_SRE, | |
134 | QLCNIC_HW_PX_MAP_CRB_NIU, | |
135 | QLCNIC_HW_PX_MAP_CRB_QMN, | |
136 | QLCNIC_HW_PX_MAP_CRB_SQN0, | |
137 | QLCNIC_HW_PX_MAP_CRB_SQN1, | |
138 | QLCNIC_HW_PX_MAP_CRB_SQN2, | |
139 | QLCNIC_HW_PX_MAP_CRB_SQN3, | |
140 | QLCNIC_HW_PX_MAP_CRB_QMS, | |
141 | QLCNIC_HW_PX_MAP_CRB_SQS0, | |
142 | QLCNIC_HW_PX_MAP_CRB_SQS1, | |
143 | QLCNIC_HW_PX_MAP_CRB_SQS2, | |
144 | QLCNIC_HW_PX_MAP_CRB_SQS3, | |
145 | QLCNIC_HW_PX_MAP_CRB_PGN0, | |
146 | QLCNIC_HW_PX_MAP_CRB_PGN1, | |
147 | QLCNIC_HW_PX_MAP_CRB_PGN2, | |
148 | QLCNIC_HW_PX_MAP_CRB_PGN3, | |
149 | QLCNIC_HW_PX_MAP_CRB_PGND, | |
150 | QLCNIC_HW_PX_MAP_CRB_PGNI, | |
151 | QLCNIC_HW_PX_MAP_CRB_PGS0, | |
152 | QLCNIC_HW_PX_MAP_CRB_PGS1, | |
153 | QLCNIC_HW_PX_MAP_CRB_PGS2, | |
154 | QLCNIC_HW_PX_MAP_CRB_PGS3, | |
155 | QLCNIC_HW_PX_MAP_CRB_PGSD, | |
156 | QLCNIC_HW_PX_MAP_CRB_PGSI, | |
157 | QLCNIC_HW_PX_MAP_CRB_SN, | |
158 | QLCNIC_HW_PX_MAP_CRB_PGR2, | |
159 | QLCNIC_HW_PX_MAP_CRB_EG, | |
160 | QLCNIC_HW_PX_MAP_CRB_PH2, | |
161 | QLCNIC_HW_PX_MAP_CRB_PS2, | |
162 | QLCNIC_HW_PX_MAP_CRB_CAM, | |
163 | QLCNIC_HW_PX_MAP_CRB_CAS0, | |
164 | QLCNIC_HW_PX_MAP_CRB_CAS1, | |
165 | QLCNIC_HW_PX_MAP_CRB_CAS2, | |
166 | QLCNIC_HW_PX_MAP_CRB_C2C0, | |
167 | QLCNIC_HW_PX_MAP_CRB_C2C1, | |
168 | QLCNIC_HW_PX_MAP_CRB_TIMR, | |
169 | QLCNIC_HW_PX_MAP_CRB_PGR3, | |
170 | QLCNIC_HW_PX_MAP_CRB_RPMX1, | |
171 | QLCNIC_HW_PX_MAP_CRB_RPMX2, | |
172 | QLCNIC_HW_PX_MAP_CRB_RPMX3, | |
173 | QLCNIC_HW_PX_MAP_CRB_RPMX4, | |
174 | QLCNIC_HW_PX_MAP_CRB_RPMX5, | |
175 | QLCNIC_HW_PX_MAP_CRB_RPMX6, | |
176 | QLCNIC_HW_PX_MAP_CRB_RPMX7, | |
177 | QLCNIC_HW_PX_MAP_CRB_XDMA, | |
178 | QLCNIC_HW_PX_MAP_CRB_I2Q, | |
179 | QLCNIC_HW_PX_MAP_CRB_ROMUSB, | |
180 | QLCNIC_HW_PX_MAP_CRB_CAS3, | |
181 | QLCNIC_HW_PX_MAP_CRB_RPMX0, | |
182 | QLCNIC_HW_PX_MAP_CRB_RPMX8, | |
183 | QLCNIC_HW_PX_MAP_CRB_RPMX9, | |
184 | QLCNIC_HW_PX_MAP_CRB_OCM0, | |
185 | QLCNIC_HW_PX_MAP_CRB_OCM1, | |
186 | QLCNIC_HW_PX_MAP_CRB_SMB, | |
187 | QLCNIC_HW_PX_MAP_CRB_I2C0, | |
188 | QLCNIC_HW_PX_MAP_CRB_I2C1, | |
189 | QLCNIC_HW_PX_MAP_CRB_LPC, | |
190 | QLCNIC_HW_PX_MAP_CRB_PGNC, | |
191 | QLCNIC_HW_PX_MAP_CRB_PGR0 | |
192 | }; | |
193 | ||
2e9d722d AC |
194 | #define BIT_0 0x1 |
195 | #define BIT_1 0x2 | |
196 | #define BIT_2 0x4 | |
197 | #define BIT_3 0x8 | |
198 | #define BIT_4 0x10 | |
199 | #define BIT_5 0x20 | |
200 | #define BIT_6 0x40 | |
201 | #define BIT_7 0x80 | |
202 | #define BIT_8 0x100 | |
203 | #define BIT_9 0x200 | |
204 | #define BIT_10 0x400 | |
205 | #define BIT_11 0x800 | |
206 | #define BIT_12 0x1000 | |
207 | #define BIT_13 0x2000 | |
208 | #define BIT_14 0x4000 | |
209 | #define BIT_15 0x8000 | |
210 | #define BIT_16 0x10000 | |
211 | #define BIT_17 0x20000 | |
212 | #define BIT_18 0x40000 | |
213 | #define BIT_19 0x80000 | |
214 | #define BIT_20 0x100000 | |
215 | #define BIT_21 0x200000 | |
216 | #define BIT_22 0x400000 | |
217 | #define BIT_23 0x800000 | |
218 | #define BIT_24 0x1000000 | |
219 | #define BIT_25 0x2000000 | |
220 | #define BIT_26 0x4000000 | |
221 | #define BIT_27 0x8000000 | |
222 | #define BIT_28 0x10000000 | |
223 | #define BIT_29 0x20000000 | |
224 | #define BIT_30 0x40000000 | |
225 | #define BIT_31 0x80000000 | |
226 | ||
af19b491 AKS |
227 | /* This field defines CRB adr [31:20] of the agents */ |
228 | ||
229 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_MN \ | |
230 | ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MN_CRB_AGT_ADR) | |
231 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PH \ | |
232 | ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_PH_CRB_AGT_ADR) | |
233 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_MS \ | |
234 | ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MS_CRB_AGT_ADR) | |
235 | ||
236 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PS \ | |
237 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_PS_CRB_AGT_ADR) | |
238 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SS \ | |
239 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SS_CRB_AGT_ADR) | |
240 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3 \ | |
241 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX3_CRB_AGT_ADR) | |
242 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_QMS \ | |
243 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_QMS_CRB_AGT_ADR) | |
244 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS0 \ | |
245 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS0_CRB_AGT_ADR) | |
246 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS1 \ | |
247 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS1_CRB_AGT_ADR) | |
248 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS2 \ | |
249 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS2_CRB_AGT_ADR) | |
250 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS3 \ | |
251 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS3_CRB_AGT_ADR) | |
252 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C0 \ | |
253 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C0_CRB_AGT_ADR) | |
254 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C1 \ | |
255 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C1_CRB_AGT_ADR) | |
256 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2 \ | |
257 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX2_CRB_AGT_ADR) | |
258 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4 \ | |
259 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX4_CRB_AGT_ADR) | |
260 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7 \ | |
261 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX7_CRB_AGT_ADR) | |
262 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9 \ | |
263 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX9_CRB_AGT_ADR) | |
264 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SMB \ | |
265 | ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SMB_CRB_AGT_ADR) | |
266 | ||
267 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_NIU \ | |
268 | ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_NIU_CRB_AGT_ADR) | |
269 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0 \ | |
270 | ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C0_CRB_AGT_ADR) | |
271 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1 \ | |
272 | ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C1_CRB_AGT_ADR) | |
273 | ||
274 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SRE \ | |
275 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SRE_CRB_AGT_ADR) | |
276 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_EG \ | |
277 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_EG_CRB_AGT_ADR) | |
278 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0 \ | |
279 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX0_CRB_AGT_ADR) | |
280 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_QMN \ | |
281 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_QM_CRB_AGT_ADR) | |
282 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0 \ | |
283 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG0_CRB_AGT_ADR) | |
284 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1 \ | |
285 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG1_CRB_AGT_ADR) | |
286 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2 \ | |
287 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG2_CRB_AGT_ADR) | |
288 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3 \ | |
289 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG3_CRB_AGT_ADR) | |
290 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1 \ | |
291 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX1_CRB_AGT_ADR) | |
292 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5 \ | |
293 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX5_CRB_AGT_ADR) | |
294 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6 \ | |
295 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX6_CRB_AGT_ADR) | |
296 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8 \ | |
297 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX8_CRB_AGT_ADR) | |
298 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS0 \ | |
299 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS0_CRB_AGT_ADR) | |
300 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS1 \ | |
301 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS1_CRB_AGT_ADR) | |
302 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS2 \ | |
303 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS2_CRB_AGT_ADR) | |
304 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS3 \ | |
305 | ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS3_CRB_AGT_ADR) | |
306 | ||
307 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI \ | |
308 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNI_CRB_AGT_ADR) | |
309 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGND \ | |
310 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGND_CRB_AGT_ADR) | |
311 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0 \ | |
312 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN0_CRB_AGT_ADR) | |
313 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1 \ | |
314 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN1_CRB_AGT_ADR) | |
315 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2 \ | |
316 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN2_CRB_AGT_ADR) | |
317 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3 \ | |
318 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN3_CRB_AGT_ADR) | |
319 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4 \ | |
320 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN4_CRB_AGT_ADR) | |
321 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC \ | |
322 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNC_CRB_AGT_ADR) | |
323 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR0 \ | |
324 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR0_CRB_AGT_ADR) | |
325 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR1 \ | |
326 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR1_CRB_AGT_ADR) | |
327 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR2 \ | |
328 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR2_CRB_AGT_ADR) | |
329 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR3 \ | |
330 | ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR3_CRB_AGT_ADR) | |
331 | ||
332 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI \ | |
333 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSI_CRB_AGT_ADR) | |
334 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSD \ | |
335 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSD_CRB_AGT_ADR) | |
336 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0 \ | |
337 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS0_CRB_AGT_ADR) | |
338 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1 \ | |
339 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS1_CRB_AGT_ADR) | |
340 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2 \ | |
341 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS2_CRB_AGT_ADR) | |
342 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3 \ | |
343 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS3_CRB_AGT_ADR) | |
344 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSC \ | |
345 | ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSC_CRB_AGT_ADR) | |
346 | ||
347 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAM \ | |
348 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_NCM_CRB_AGT_ADR) | |
349 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR \ | |
350 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_TMR_CRB_AGT_ADR) | |
351 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA \ | |
352 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_XDMA_CRB_AGT_ADR) | |
353 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_SN \ | |
354 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_SN_CRB_AGT_ADR) | |
355 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q \ | |
356 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_I2Q_CRB_AGT_ADR) | |
357 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB \ | |
358 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_ROMUSB_CRB_AGT_ADR) | |
359 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0 \ | |
360 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM0_CRB_AGT_ADR) | |
361 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM1 \ | |
362 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM1_CRB_AGT_ADR) | |
363 | #define QLCNIC_HW_CRB_HUB_AGT_ADR_LPC \ | |
364 | ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_LPC_CRB_AGT_ADR) | |
365 | ||
366 | #define QLCNIC_SRE_MISC (QLCNIC_CRB_SRE + 0x0002c) | |
367 | ||
368 | #define QLCNIC_I2Q_CLR_PCI_HI (QLCNIC_CRB_I2Q + 0x00034) | |
369 | ||
370 | #define ROMUSB_GLB (QLCNIC_CRB_ROMUSB + 0x00000) | |
371 | #define ROMUSB_ROM (QLCNIC_CRB_ROMUSB + 0x10000) | |
372 | ||
373 | #define QLCNIC_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) | |
374 | #define QLCNIC_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) | |
375 | #define QLCNIC_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c) | |
376 | #define QLCNIC_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) | |
377 | #define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044) | |
378 | #define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) | |
379 | #define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8) | |
380 | ||
381 | #define QLCNIC_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n))) | |
382 | ||
383 | #define QLCNIC_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) | |
384 | #define QLCNIC_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) | |
385 | #define QLCNIC_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) | |
386 | #define QLCNIC_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) | |
387 | #define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) | |
388 | #define QLCNIC_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) | |
389 | ||
390 | /* Lock IDs for ROM lock */ | |
391 | #define ROM_LOCK_DRIVER 0x0d417340 | |
392 | ||
393 | /****************************************************************************** | |
394 | * | |
395 | * Definitions specific to M25P flash | |
396 | * | |
397 | ******************************************************************************* | |
398 | */ | |
399 | ||
400 | /* all are 1MB windows */ | |
401 | ||
402 | #define QLCNIC_PCI_CRB_WINDOWSIZE 0x00100000 | |
403 | #define QLCNIC_PCI_CRB_WINDOW(A) \ | |
404 | (QLCNIC_PCI_CRBSPACE + (A)*QLCNIC_PCI_CRB_WINDOWSIZE) | |
405 | ||
406 | #define QLCNIC_CRB_NIU QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_NIU) | |
407 | #define QLCNIC_CRB_SRE QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE) | |
408 | #define QLCNIC_CRB_ROMUSB \ | |
409 | QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB) | |
410 | #define QLCNIC_CRB_I2Q QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q) | |
411 | #define QLCNIC_CRB_I2C0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0) | |
412 | #define QLCNIC_CRB_SMB QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB) | |
413 | #define QLCNIC_CRB_MAX QLCNIC_PCI_CRB_WINDOW(64) | |
414 | ||
415 | #define QLCNIC_CRB_PCIX_HOST QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH) | |
416 | #define QLCNIC_CRB_PCIX_HOST2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH2) | |
417 | #define QLCNIC_CRB_PEG_NET_0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN0) | |
418 | #define QLCNIC_CRB_PEG_NET_1 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN1) | |
419 | #define QLCNIC_CRB_PEG_NET_2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN2) | |
420 | #define QLCNIC_CRB_PEG_NET_3 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN3) | |
421 | #define QLCNIC_CRB_PEG_NET_4 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SQS2) | |
422 | #define QLCNIC_CRB_PEG_NET_D QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGND) | |
423 | #define QLCNIC_CRB_PEG_NET_I QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGNI) | |
424 | #define QLCNIC_CRB_DDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_MN) | |
425 | #define QLCNIC_CRB_QDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SN) | |
426 | ||
427 | #define QLCNIC_CRB_PCIX_MD QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PS) | |
428 | #define QLCNIC_CRB_PCIE QLCNIC_CRB_PCIX_MD | |
429 | ||
430 | #define ISR_INT_VECTOR (QLCNIC_PCIX_PS_REG(PCIX_INT_VECTOR)) | |
431 | #define ISR_INT_MASK (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK)) | |
432 | #define ISR_INT_MASK_SLOW (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK)) | |
433 | #define ISR_INT_TARGET_STATUS (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS)) | |
434 | #define ISR_INT_TARGET_MASK (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK)) | |
435 | #define ISR_INT_TARGET_STATUS_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) | |
436 | #define ISR_INT_TARGET_MASK_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) | |
437 | #define ISR_INT_TARGET_STATUS_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) | |
438 | #define ISR_INT_TARGET_MASK_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) | |
439 | #define ISR_INT_TARGET_STATUS_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) | |
440 | #define ISR_INT_TARGET_MASK_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) | |
441 | #define ISR_INT_TARGET_STATUS_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F4)) | |
442 | #define ISR_INT_TARGET_MASK_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F4)) | |
443 | #define ISR_INT_TARGET_STATUS_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F5)) | |
444 | #define ISR_INT_TARGET_MASK_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) | |
445 | #define ISR_INT_TARGET_STATUS_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F6)) | |
446 | #define ISR_INT_TARGET_MASK_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F6)) | |
447 | #define ISR_INT_TARGET_STATUS_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F7)) | |
448 | #define ISR_INT_TARGET_MASK_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F7)) | |
449 | ||
450 | #define QLCNIC_PCI_MN_2M (0) | |
451 | #define QLCNIC_PCI_MS_2M (0x80000) | |
452 | #define QLCNIC_PCI_OCM0_2M (0x000c0000UL) | |
453 | #define QLCNIC_PCI_CRBSPACE (0x06000000UL) | |
897e8c7c DP |
454 | #define QLCNIC_PCI_CAMQM (0x04800000UL) |
455 | #define QLCNIC_PCI_CAMQM_END (0x04800800UL) | |
af19b491 AKS |
456 | #define QLCNIC_PCI_2MB_SIZE (0x00200000UL) |
457 | #define QLCNIC_PCI_CAMQM_2M_BASE (0x000ff800UL) | |
af19b491 AKS |
458 | |
459 | #define QLCNIC_CRB_CAM QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_CAM) | |
460 | ||
461 | #define QLCNIC_ADDR_DDR_NET (0x0000000000000000ULL) | |
462 | #define QLCNIC_ADDR_DDR_NET_MAX (0x000000000fffffffULL) | |
463 | #define QLCNIC_ADDR_OCM0 (0x0000000200000000ULL) | |
464 | #define QLCNIC_ADDR_OCM0_MAX (0x00000002000fffffULL) | |
465 | #define QLCNIC_ADDR_OCM1 (0x0000000200400000ULL) | |
466 | #define QLCNIC_ADDR_OCM1_MAX (0x00000002004fffffULL) | |
467 | #define QLCNIC_ADDR_QDR_NET (0x0000000300000000ULL) | |
b47acacd | 468 | #define QLCNIC_ADDR_QDR_NET_MAX (0x0000000307ffffffULL) |
af19b491 AKS |
469 | |
470 | /* | |
471 | * Register offsets for MN | |
472 | */ | |
473 | #define QLCNIC_MIU_CONTROL (0x000) | |
474 | #define QLCNIC_MIU_MN_CONTROL (QLCNIC_CRB_DDR_NET+QLCNIC_MIU_CONTROL) | |
475 | ||
476 | /* 200ms delay in each loop */ | |
477 | #define QLCNIC_NIU_PHY_WAITLEN 200000 | |
478 | /* 10 seconds before we give up */ | |
479 | #define QLCNIC_NIU_PHY_WAITMAX 50 | |
480 | #define QLCNIC_NIU_MAX_GBE_PORTS 4 | |
481 | #define QLCNIC_NIU_MAX_XG_PORTS 2 | |
482 | ||
483 | #define QLCNIC_NIU_MODE (QLCNIC_CRB_NIU + 0x00000) | |
484 | #define QLCNIC_NIU_GB_PAUSE_CTL (QLCNIC_CRB_NIU + 0x0030c) | |
485 | #define QLCNIC_NIU_XG_PAUSE_CTL (QLCNIC_CRB_NIU + 0x00098) | |
486 | ||
487 | #define QLCNIC_NIU_GB_MAC_CONFIG_0(I) \ | |
488 | (QLCNIC_CRB_NIU + 0x30000 + (I)*0x10000) | |
489 | #define QLCNIC_NIU_GB_MAC_CONFIG_1(I) \ | |
490 | (QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000) | |
491 | ||
492 | ||
493 | #define TEST_AGT_CTRL (0x00) | |
494 | ||
495 | #define TA_CTL_START 1 | |
496 | #define TA_CTL_ENABLE 2 | |
497 | #define TA_CTL_WRITE 4 | |
498 | #define TA_CTL_BUSY 8 | |
499 | ||
500 | /* | |
501 | * Register offsets for MN | |
502 | */ | |
503 | #define MIU_TEST_AGT_BASE (0x90) | |
504 | ||
505 | #define MIU_TEST_AGT_ADDR_LO (0x04) | |
506 | #define MIU_TEST_AGT_ADDR_HI (0x08) | |
507 | #define MIU_TEST_AGT_WRDATA_LO (0x10) | |
508 | #define MIU_TEST_AGT_WRDATA_HI (0x14) | |
509 | #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x20) | |
510 | #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x24) | |
511 | #define MIU_TEST_AGT_WRDATA(i) (0x10+(0x10*((i)>>1))+(4*((i)&1))) | |
512 | #define MIU_TEST_AGT_RDDATA_LO (0x18) | |
513 | #define MIU_TEST_AGT_RDDATA_HI (0x1c) | |
514 | #define MIU_TEST_AGT_RDDATA_UPPER_LO (0x28) | |
515 | #define MIU_TEST_AGT_RDDATA_UPPER_HI (0x2c) | |
516 | #define MIU_TEST_AGT_RDDATA(i) (0x18+(0x10*((i)>>1))+(4*((i)&1))) | |
517 | ||
518 | #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 | |
519 | #define MIU_TEST_AGT_UPPER_ADDR(off) (0) | |
520 | ||
521 | /* | |
522 | * Register offsets for MS | |
523 | */ | |
524 | #define SIU_TEST_AGT_BASE (0x60) | |
525 | ||
526 | #define SIU_TEST_AGT_ADDR_LO (0x04) | |
527 | #define SIU_TEST_AGT_ADDR_HI (0x18) | |
528 | #define SIU_TEST_AGT_WRDATA_LO (0x08) | |
529 | #define SIU_TEST_AGT_WRDATA_HI (0x0c) | |
530 | #define SIU_TEST_AGT_WRDATA(i) (0x08+(4*(i))) | |
531 | #define SIU_TEST_AGT_RDDATA_LO (0x10) | |
532 | #define SIU_TEST_AGT_RDDATA_HI (0x14) | |
533 | #define SIU_TEST_AGT_RDDATA(i) (0x10+(4*(i))) | |
534 | ||
535 | #define SIU_TEST_AGT_ADDR_MASK 0x3ffff8 | |
536 | #define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22) | |
537 | ||
538 | /* XG Link status */ | |
539 | #define XG_LINK_UP 0x10 | |
540 | #define XG_LINK_DOWN 0x20 | |
541 | ||
ff1b1bf8 SV |
542 | #define XG_LINK_UP_P3P 0x01 |
543 | #define XG_LINK_DOWN_P3P 0x02 | |
544 | #define XG_LINK_STATE_P3P_MASK 0xf | |
545 | #define XG_LINK_STATE_P3P(pcifn, val) \ | |
546 | (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3P_MASK) | |
547 | ||
548 | #define P3P_LINK_SPEED_MHZ 100 | |
549 | #define P3P_LINK_SPEED_MASK 0xff | |
550 | #define P3P_LINK_SPEED_REG(pcifn) \ | |
af19b491 | 551 | (CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4)) |
ff1b1bf8 SV |
552 | #define P3P_LINK_SPEED_VAL(pcifn, reg) \ |
553 | (((reg) >> (8 * ((pcifn) & 0x3))) & P3P_LINK_SPEED_MASK) | |
af19b491 AKS |
554 | |
555 | #define QLCNIC_CAM_RAM_BASE (QLCNIC_CRB_CAM + 0x02000) | |
556 | #define QLCNIC_CAM_RAM(reg) (QLCNIC_CAM_RAM_BASE + (reg)) | |
557 | #define QLCNIC_FW_VERSION_MAJOR (QLCNIC_CAM_RAM(0x150)) | |
558 | #define QLCNIC_FW_VERSION_MINOR (QLCNIC_CAM_RAM(0x154)) | |
559 | #define QLCNIC_FW_VERSION_SUB (QLCNIC_CAM_RAM(0x158)) | |
560 | #define QLCNIC_ROM_LOCK_ID (QLCNIC_CAM_RAM(0x100)) | |
561 | #define QLCNIC_PHY_LOCK_ID (QLCNIC_CAM_RAM(0x120)) | |
562 | #define QLCNIC_CRB_WIN_LOCK_ID (QLCNIC_CAM_RAM(0x124)) | |
563 | ||
564 | #define NIC_CRB_BASE (QLCNIC_CAM_RAM(0x200)) | |
565 | #define NIC_CRB_BASE_2 (QLCNIC_CAM_RAM(0x700)) | |
566 | #define QLCNIC_REG(X) (NIC_CRB_BASE+(X)) | |
567 | #define QLCNIC_REG_2(X) (NIC_CRB_BASE_2+(X)) | |
568 | ||
569 | #define QLCNIC_CDRP_CRB_OFFSET (QLCNIC_REG(0x18)) | |
570 | #define QLCNIC_ARG1_CRB_OFFSET (QLCNIC_REG(0x1c)) | |
571 | #define QLCNIC_ARG2_CRB_OFFSET (QLCNIC_REG(0x20)) | |
572 | #define QLCNIC_ARG3_CRB_OFFSET (QLCNIC_REG(0x24)) | |
573 | #define QLCNIC_SIGN_CRB_OFFSET (QLCNIC_REG(0x28)) | |
574 | ||
575 | #define CRB_CMDPEG_STATE (QLCNIC_REG(0x50)) | |
576 | #define CRB_RCVPEG_STATE (QLCNIC_REG(0x13c)) | |
577 | ||
ff1b1bf8 | 578 | #define CRB_XG_STATE_P3P (QLCNIC_REG(0x98)) |
af19b491 AKS |
579 | #define CRB_PF_LINK_SPEED_1 (QLCNIC_REG(0xe8)) |
580 | #define CRB_PF_LINK_SPEED_2 (QLCNIC_REG(0xec)) | |
581 | ||
af19b491 AKS |
582 | #define CRB_TEMP_STATE (QLCNIC_REG(0x1b4)) |
583 | ||
584 | #define CRB_V2P_0 (QLCNIC_REG(0x290)) | |
585 | #define CRB_V2P(port) (CRB_V2P_0+((port)*4)) | |
586 | #define CRB_DRIVER_VERSION (QLCNIC_REG(0x2a0)) | |
587 | ||
af19b491 AKS |
588 | #define CRB_FW_CAPABILITIES_1 (QLCNIC_CAM_RAM(0x128)) |
589 | #define CRB_MAC_BLOCK_START (QLCNIC_CAM_RAM(0x1c0)) | |
590 | ||
af19b491 AKS |
591 | /* |
592 | * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address | |
593 | * which can be read by the Phantom host to get producer/consumer indexes from | |
594 | * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following | |
595 | * registers will be used for the addresses of the ring's shared memory | |
596 | * on the Phantom. | |
597 | */ | |
598 | ||
599 | #define qlcnic_get_temp_val(x) ((x) >> 16) | |
600 | #define qlcnic_get_temp_state(x) ((x) & 0xffff) | |
601 | #define qlcnic_encode_temp(val, state) (((val) << 16) | (state)) | |
602 | ||
603 | /* | |
604 | * Temperature control. | |
605 | */ | |
606 | enum { | |
607 | QLCNIC_TEMP_NORMAL = 0x1, /* Normal operating range */ | |
608 | QLCNIC_TEMP_WARN, /* Sound alert, temperature getting high */ | |
609 | QLCNIC_TEMP_PANIC /* Fatal error, hardware has shut down. */ | |
610 | }; | |
611 | ||
612 | /* Lock IDs for PHY lock */ | |
613 | #define PHY_LOCK_DRIVER 0x44524956 | |
614 | ||
615 | /* Used for PS PCI Memory access */ | |
616 | #define PCIX_PS_OP_ADDR_LO (0x10000) | |
617 | /* via CRB (PS side only) */ | |
618 | #define PCIX_PS_OP_ADDR_HI (0x10004) | |
619 | ||
620 | #define PCIX_INT_VECTOR (0x10100) | |
621 | #define PCIX_INT_MASK (0x10104) | |
622 | ||
623 | #define PCIX_OCM_WINDOW (0x10800) | |
b5006dcb | 624 | #define PCIX_OCM_WINDOW_REG(func) (PCIX_OCM_WINDOW + 0x4 * (func)) |
af19b491 AKS |
625 | |
626 | #define PCIX_TARGET_STATUS (0x10118) | |
627 | #define PCIX_TARGET_STATUS_F1 (0x10160) | |
628 | #define PCIX_TARGET_STATUS_F2 (0x10164) | |
629 | #define PCIX_TARGET_STATUS_F3 (0x10168) | |
630 | #define PCIX_TARGET_STATUS_F4 (0x10360) | |
631 | #define PCIX_TARGET_STATUS_F5 (0x10364) | |
632 | #define PCIX_TARGET_STATUS_F6 (0x10368) | |
633 | #define PCIX_TARGET_STATUS_F7 (0x1036c) | |
634 | ||
635 | #define PCIX_TARGET_MASK (0x10128) | |
636 | #define PCIX_TARGET_MASK_F1 (0x10170) | |
637 | #define PCIX_TARGET_MASK_F2 (0x10174) | |
638 | #define PCIX_TARGET_MASK_F3 (0x10178) | |
639 | #define PCIX_TARGET_MASK_F4 (0x10370) | |
640 | #define PCIX_TARGET_MASK_F5 (0x10374) | |
641 | #define PCIX_TARGET_MASK_F6 (0x10378) | |
642 | #define PCIX_TARGET_MASK_F7 (0x1037c) | |
643 | ||
644 | #define PCIX_MSI_F(i) (0x13000+((i)*4)) | |
645 | ||
646 | #define QLCNIC_PCIX_PH_REG(reg) (QLCNIC_CRB_PCIE + (reg)) | |
647 | #define QLCNIC_PCIX_PS_REG(reg) (QLCNIC_CRB_PCIX_MD + (reg)) | |
648 | #define QLCNIC_PCIE_REG(reg) (QLCNIC_CRB_PCIE + (reg)) | |
649 | ||
650 | #define PCIE_SEM0_LOCK (0x1c000) | |
651 | #define PCIE_SEM0_UNLOCK (0x1c004) | |
652 | #define PCIE_SEM_LOCK(N) (PCIE_SEM0_LOCK + 8*(N)) | |
653 | #define PCIE_SEM_UNLOCK(N) (PCIE_SEM0_UNLOCK + 8*(N)) | |
654 | ||
655 | #define PCIE_SETUP_FUNCTION (0x12040) | |
656 | #define PCIE_SETUP_FUNCTION2 (0x12048) | |
657 | #define PCIE_MISCCFG_RC (0x1206c) | |
658 | #define PCIE_TGT_SPLIT_CHICKEN (0x12080) | |
659 | #define PCIE_CHICKEN3 (0x120c8) | |
660 | ||
661 | #define ISR_INT_STATE_REG (QLCNIC_PCIX_PS_REG(PCIE_MISCCFG_RC)) | |
662 | #define PCIE_MAX_MASTER_SPLIT (0x14048) | |
663 | ||
664 | #define QLCNIC_PORT_MODE_NONE 0 | |
665 | #define QLCNIC_PORT_MODE_XG 1 | |
666 | #define QLCNIC_PORT_MODE_GB 2 | |
667 | #define QLCNIC_PORT_MODE_802_3_AP 3 | |
668 | #define QLCNIC_PORT_MODE_AUTO_NEG 4 | |
669 | #define QLCNIC_PORT_MODE_AUTO_NEG_1G 5 | |
670 | #define QLCNIC_PORT_MODE_AUTO_NEG_XG 6 | |
671 | #define QLCNIC_PORT_MODE_ADDR (QLCNIC_CAM_RAM(0x24)) | |
672 | #define QLCNIC_WOL_PORT_MODE (QLCNIC_CAM_RAM(0x198)) | |
673 | ||
674 | #define QLCNIC_WOL_CONFIG_NV (QLCNIC_CAM_RAM(0x184)) | |
675 | #define QLCNIC_WOL_CONFIG (QLCNIC_CAM_RAM(0x188)) | |
676 | ||
677 | #define QLCNIC_PEG_TUNE_MN_PRESENT 0x1 | |
678 | #define QLCNIC_PEG_TUNE_CAPABILITY (QLCNIC_CAM_RAM(0x02c)) | |
679 | ||
680 | #define QLCNIC_DMA_WATCHDOG_CTRL (QLCNIC_CAM_RAM(0x14)) | |
681 | #define QLCNIC_PEG_ALIVE_COUNTER (QLCNIC_CAM_RAM(0xb0)) | |
682 | #define QLCNIC_PEG_HALT_STATUS1 (QLCNIC_CAM_RAM(0xa8)) | |
683 | #define QLCNIC_PEG_HALT_STATUS2 (QLCNIC_CAM_RAM(0xac)) | |
31018e06 | 684 | #define QLCNIC_CRB_DRV_ACTIVE (QLCNIC_CAM_RAM(0x138)) |
af19b491 AKS |
685 | #define QLCNIC_CRB_DEV_STATE (QLCNIC_CAM_RAM(0x140)) |
686 | ||
9f26f547 AC |
687 | #define QLCNIC_CRB_DRV_STATE (QLCNIC_CAM_RAM(0x144)) |
688 | #define QLCNIC_CRB_DRV_SCRATCH (QLCNIC_CAM_RAM(0x148)) | |
689 | #define QLCNIC_CRB_DEV_PARTITION_INFO (QLCNIC_CAM_RAM(0x14c)) | |
bbd8c6a4 | 690 | #define QLCNIC_CRB_DRV_IDC_VER (QLCNIC_CAM_RAM(0x174)) |
9f26f547 | 691 | #define QLCNIC_CRB_DEV_NPAR_STATE (QLCNIC_CAM_RAM(0x19c)) |
aa5e18c0 SC |
692 | #define QLCNIC_ROM_DEV_INIT_TIMEOUT (0x3e885c) |
693 | #define QLCNIC_ROM_DRV_RESET_TIMEOUT (0x3e8860) | |
af19b491 | 694 | |
bbd8c6a4 AKS |
695 | /* Device State */ |
696 | #define QLCNIC_DEV_COLD 0x1 | |
697 | #define QLCNIC_DEV_INITIALIZING 0x2 | |
698 | #define QLCNIC_DEV_READY 0x3 | |
699 | #define QLCNIC_DEV_NEED_RESET 0x4 | |
700 | #define QLCNIC_DEV_NEED_QUISCENT 0x5 | |
701 | #define QLCNIC_DEV_FAILED 0x6 | |
702 | #define QLCNIC_DEV_QUISCENT 0x7 | |
af19b491 | 703 | |
3c4b23b1 AKS |
704 | #define QLCNIC_DEV_NPAR_NON_OPER 0 /* NON Operational */ |
705 | #define QLCNIC_DEV_NPAR_OPER 1 /* NPAR Operational */ | |
706 | #define QLCNIC_DEV_NPAR_OPER_TIMEO 30 /* Operational time out */ | |
9f26f547 | 707 | |
b0044bcf | 708 | #define QLC_DEV_CHECK_ACTIVE(VAL, FN) ((VAL) & (1 << (FN * 4))) |
6d2a4724 AKS |
709 | #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) |
710 | #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) | |
711 | #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) | |
712 | #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) | |
713 | #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4))) | |
714 | ||
2e9d722d AC |
715 | #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4))) |
716 | #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4)) | |
717 | ||
718 | #define QLCNIC_TYPE_NIC 1 | |
719 | #define QLCNIC_TYPE_FCOE 2 | |
720 | #define QLCNIC_TYPE_ISCSI 3 | |
721 | ||
af19b491 | 722 | #define QLCNIC_RCODE_DRIVER_INFO 0x20000000 |
9f26f547 AC |
723 | #define QLCNIC_RCODE_DRIVER_CAN_RELOAD BIT_30 |
724 | #define QLCNIC_RCODE_FATAL_ERROR BIT_31 | |
af19b491 AKS |
725 | #define QLCNIC_FWERROR_PEGNUM(code) ((code) & 0xff) |
726 | #define QLCNIC_FWERROR_CODE(code) ((code >> 8) & 0xfffff) | |
727 | ||
bbd8c6a4 AKS |
728 | #define FW_POLL_DELAY (1 * HZ) |
729 | #define FW_FAIL_THRESH 2 | |
af19b491 | 730 | |
251b036a SC |
731 | #define QLCNIC_RESET_TIMEOUT_SECS 10 |
732 | #define QLCNIC_INIT_TIMEOUT_SECS 30 | |
4e70812b SC |
733 | #define QLCNIC_RCVPEG_CHECK_RETRY_COUNT 2000 |
734 | #define QLCNIC_RCVPEG_CHECK_DELAY 10 | |
735 | #define QLCNIC_CMDPEG_CHECK_RETRY_COUNT 60 | |
736 | #define QLCNIC_CMDPEG_CHECK_DELAY 500 | |
d4066833 | 737 | #define QLCNIC_HEARTBEAT_PERIOD_MSECS 200 |
4e70812b | 738 | #define QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT 45 |
251b036a | 739 | |
af19b491 AKS |
740 | #define ISR_MSI_INT_TRIGGER(FUNC) (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC))) |
741 | #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) | |
742 | ||
743 | /* | |
744 | * PCI Interrupt Vector Values. | |
745 | */ | |
746 | #define PCIX_INT_VECTOR_BIT_F0 0x0080 | |
747 | #define PCIX_INT_VECTOR_BIT_F1 0x0100 | |
748 | #define PCIX_INT_VECTOR_BIT_F2 0x0200 | |
749 | #define PCIX_INT_VECTOR_BIT_F3 0x0400 | |
750 | #define PCIX_INT_VECTOR_BIT_F4 0x0800 | |
751 | #define PCIX_INT_VECTOR_BIT_F5 0x1000 | |
752 | #define PCIX_INT_VECTOR_BIT_F6 0x2000 | |
753 | #define PCIX_INT_VECTOR_BIT_F7 0x4000 | |
754 | ||
755 | struct qlcnic_legacy_intr_set { | |
756 | u32 int_vec_bit; | |
757 | u32 tgt_status_reg; | |
758 | u32 tgt_mask_reg; | |
759 | u32 pci_int_reg; | |
760 | }; | |
761 | ||
2e9d722d AC |
762 | #define QLCNIC_FW_API 0x1b216c |
763 | #define QLCNIC_DRV_OP_MODE 0x1b2170 | |
764 | #define QLCNIC_MSIX_BASE 0x132110 | |
765 | #define QLCNIC_MAX_PCI_FUNC 8 | |
4e8acb01 | 766 | #define QLCNIC_MAX_VLAN_FILTERS 64 |
2e9d722d AC |
767 | |
768 | /* PCI function operational mode */ | |
769 | enum { | |
770 | QLCNIC_MGMT_FUNC = 0, | |
771 | QLCNIC_PRIV_FUNC = 1, | |
772 | QLCNIC_NON_PRIV_FUNC = 2 | |
773 | }; | |
774 | ||
4e8acb01 RB |
775 | enum { |
776 | QLCNIC_PORT_DEFAULTS = 0, | |
777 | QLCNIC_ADD_VLAN = 1, | |
778 | QLCNIC_DEL_VLAN = 2 | |
779 | }; | |
780 | ||
2e9d722d AC |
781 | #define QLC_DEV_DRV_DEFAULT 0x11111111 |
782 | ||
783 | #define LSB(x) ((uint8_t)(x)) | |
784 | #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) | |
785 | ||
786 | #define LSW(x) ((uint16_t)((uint32_t)(x))) | |
787 | #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) | |
788 | ||
789 | #define LSD(x) ((uint32_t)((uint64_t)(x))) | |
790 | #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) | |
791 | ||
af19b491 AKS |
792 | #define QLCNIC_LEGACY_INTR_CONFIG \ |
793 | { \ | |
794 | { \ | |
795 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \ | |
796 | .tgt_status_reg = ISR_INT_TARGET_STATUS, \ | |
797 | .tgt_mask_reg = ISR_INT_TARGET_MASK, \ | |
798 | .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \ | |
799 | \ | |
800 | { \ | |
801 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \ | |
802 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \ | |
803 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \ | |
804 | .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \ | |
805 | \ | |
806 | { \ | |
807 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \ | |
808 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \ | |
809 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \ | |
810 | .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \ | |
811 | \ | |
812 | { \ | |
813 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \ | |
814 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \ | |
815 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \ | |
816 | .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \ | |
817 | \ | |
818 | { \ | |
819 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \ | |
820 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \ | |
821 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \ | |
822 | .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \ | |
823 | \ | |
824 | { \ | |
825 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \ | |
826 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \ | |
827 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \ | |
828 | .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \ | |
829 | \ | |
830 | { \ | |
831 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \ | |
832 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \ | |
833 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \ | |
834 | .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \ | |
835 | \ | |
836 | { \ | |
837 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \ | |
838 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \ | |
839 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \ | |
840 | .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \ | |
841 | } | |
842 | ||
843 | /* NIU REGS */ | |
844 | ||
845 | #define _qlcnic_crb_get_bit(var, bit) ((var >> bit) & 0x1) | |
846 | ||
847 | /* | |
848 | * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3) | |
849 | * | |
850 | * Bit 0 : enable_tx => 1:enable frame xmit, 0:disable | |
851 | * Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream | |
852 | * Bit 2 : enable_rx => 1:enable frame recv, 0:disable | |
853 | * Bit 3 : rx_synced => R/O: recv enable synched to recv stream | |
854 | * Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable | |
855 | * Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore | |
856 | * Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal | |
857 | * Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op | |
858 | * Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op | |
859 | * Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op | |
860 | * Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op | |
861 | * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op | |
862 | */ | |
863 | #define qlcnic_gb_rx_flowctl(config_word) \ | |
864 | ((config_word) |= 1 << 5) | |
865 | #define qlcnic_gb_get_rx_flowctl(config_word) \ | |
866 | _qlcnic_crb_get_bit((config_word), 5) | |
867 | #define qlcnic_gb_unset_rx_flowctl(config_word) \ | |
868 | ((config_word) &= ~(1 << 5)) | |
869 | ||
870 | /* | |
871 | * NIU GB Pause Ctl Register | |
872 | */ | |
873 | ||
874 | #define qlcnic_gb_set_gb0_mask(config_word) \ | |
875 | ((config_word) |= 1 << 0) | |
876 | #define qlcnic_gb_set_gb1_mask(config_word) \ | |
877 | ((config_word) |= 1 << 2) | |
878 | #define qlcnic_gb_set_gb2_mask(config_word) \ | |
879 | ((config_word) |= 1 << 4) | |
880 | #define qlcnic_gb_set_gb3_mask(config_word) \ | |
881 | ((config_word) |= 1 << 6) | |
882 | ||
883 | #define qlcnic_gb_get_gb0_mask(config_word) \ | |
884 | _qlcnic_crb_get_bit((config_word), 0) | |
885 | #define qlcnic_gb_get_gb1_mask(config_word) \ | |
886 | _qlcnic_crb_get_bit((config_word), 2) | |
887 | #define qlcnic_gb_get_gb2_mask(config_word) \ | |
888 | _qlcnic_crb_get_bit((config_word), 4) | |
889 | #define qlcnic_gb_get_gb3_mask(config_word) \ | |
890 | _qlcnic_crb_get_bit((config_word), 6) | |
891 | ||
892 | #define qlcnic_gb_unset_gb0_mask(config_word) \ | |
893 | ((config_word) &= ~(1 << 0)) | |
894 | #define qlcnic_gb_unset_gb1_mask(config_word) \ | |
895 | ((config_word) &= ~(1 << 2)) | |
896 | #define qlcnic_gb_unset_gb2_mask(config_word) \ | |
897 | ((config_word) &= ~(1 << 4)) | |
898 | #define qlcnic_gb_unset_gb3_mask(config_word) \ | |
899 | ((config_word) &= ~(1 << 6)) | |
900 | ||
901 | /* | |
902 | * NIU XG Pause Ctl Register | |
903 | * | |
904 | * Bit 0 : xg0_mask => 1:disable tx pause frames | |
905 | * Bit 1 : xg0_request => 1:request single pause frame | |
906 | * Bit 2 : xg0_on_off => 1:request is pause on, 0:off | |
907 | * Bit 3 : xg1_mask => 1:disable tx pause frames | |
908 | * Bit 4 : xg1_request => 1:request single pause frame | |
909 | * Bit 5 : xg1_on_off => 1:request is pause on, 0:off | |
910 | */ | |
911 | ||
912 | #define qlcnic_xg_set_xg0_mask(config_word) \ | |
913 | ((config_word) |= 1 << 0) | |
914 | #define qlcnic_xg_set_xg1_mask(config_word) \ | |
915 | ((config_word) |= 1 << 3) | |
916 | ||
917 | #define qlcnic_xg_get_xg0_mask(config_word) \ | |
918 | _qlcnic_crb_get_bit((config_word), 0) | |
919 | #define qlcnic_xg_get_xg1_mask(config_word) \ | |
920 | _qlcnic_crb_get_bit((config_word), 3) | |
921 | ||
922 | #define qlcnic_xg_unset_xg0_mask(config_word) \ | |
923 | ((config_word) &= ~(1 << 0)) | |
924 | #define qlcnic_xg_unset_xg1_mask(config_word) \ | |
925 | ((config_word) &= ~(1 << 3)) | |
926 | ||
927 | /* | |
928 | * NIU XG Pause Ctl Register | |
929 | * | |
930 | * Bit 0 : xg0_mask => 1:disable tx pause frames | |
931 | * Bit 1 : xg0_request => 1:request single pause frame | |
932 | * Bit 2 : xg0_on_off => 1:request is pause on, 0:off | |
933 | * Bit 3 : xg1_mask => 1:disable tx pause frames | |
934 | * Bit 4 : xg1_request => 1:request single pause frame | |
935 | * Bit 5 : xg1_on_off => 1:request is pause on, 0:off | |
936 | */ | |
937 | ||
938 | /* | |
939 | * PHY-Specific MII control/status registers. | |
940 | */ | |
941 | #define QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG 4 | |
942 | #define QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17 | |
943 | ||
944 | /* | |
945 | * PHY-Specific Status Register (reg 17). | |
946 | * | |
947 | * Bit 0 : jabber => 1:jabber detected, 0:not | |
948 | * Bit 1 : polarity => 1:polarity reversed, 0:normal | |
949 | * Bit 2 : recvpause => 1:receive pause enabled, 0:disabled | |
950 | * Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled | |
951 | * Bit 4 : energydetect => 1:sleep, 0:active | |
952 | * Bit 5 : downshift => 1:downshift, 0:no downshift | |
953 | * Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover) | |
954 | * Bits 7-9 : cablelen => not valid in 10Mb/s mode | |
955 | * 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m | |
956 | * Bit 10 : link => 1:link up, 0:link down | |
957 | * Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet | |
958 | * Bit 12 : pagercvd => 1:page received, 0:page not received | |
959 | * Bit 13 : duplex => 1:full duplex, 0:half duplex | |
960 | * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd | |
961 | */ | |
962 | ||
963 | #define qlcnic_get_phy_speed(config_word) (((config_word) >> 14) & 0x03) | |
964 | ||
965 | #define qlcnic_set_phy_speed(config_word, val) \ | |
966 | ((config_word) |= ((val & 0x03) << 14)) | |
967 | #define qlcnic_set_phy_duplex(config_word) \ | |
968 | ((config_word) |= 1 << 13) | |
969 | #define qlcnic_clear_phy_duplex(config_word) \ | |
970 | ((config_word) &= ~(1 << 13)) | |
971 | ||
972 | #define qlcnic_get_phy_link(config_word) \ | |
973 | _qlcnic_crb_get_bit(config_word, 10) | |
974 | #define qlcnic_get_phy_duplex(config_word) \ | |
975 | _qlcnic_crb_get_bit(config_word, 13) | |
976 | ||
977 | #define QLCNIC_NIU_NON_PROMISC_MODE 0 | |
978 | #define QLCNIC_NIU_PROMISC_MODE 1 | |
979 | #define QLCNIC_NIU_ALLMULTI_MODE 2 | |
980 | ||
981 | struct crb_128M_2M_sub_block_map { | |
982 | unsigned valid; | |
983 | unsigned start_128M; | |
984 | unsigned end_128M; | |
985 | unsigned start_2M; | |
986 | }; | |
987 | ||
988 | struct crb_128M_2M_block_map{ | |
989 | struct crb_128M_2M_sub_block_map sub_block[16]; | |
990 | }; | |
991 | #endif /* __QLCNIC_HDR_H_ */ |